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1.1 root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2: ;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3: ;; Contributed by Richard Kenner ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23: ;; Define an insn type attribute. This is used in function unit delay
24: ;; computations.
1.1.1.2 root 25: (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
1.1 root 26: (const_string "integer"))
27:
28: ;; Memory delivers its result in two cycles.
29: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30:
31: ;; We consider floating-point insns to deliver their result in two cycles
32: ;; to try to intersperse integer and FP operations.
33: (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34:
35: ;; Most integer comparisons are ready in four cycles (a stall of three).
36: (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37:
38: ;; Some integer comparisons aren't ready for five cycles (a stall of four).
39: (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40:
41: ;; Floating-point comparisons take eight cycles.
42: (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
1.1.1.2 root 43:
44: ;; Branches on LR cannot be done until five cycles after LR is set.
45: (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
1.1 root 46:
47: ;; Start with fixed-point load and store insns. Here we put only the more
48: ;; complex forms. Basic data transfer is done later.
49:
50: (define_expand "zero_extendqisi2"
1.1.1.3 ! root 51: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 52: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1.1 root 53: ""
54: "")
55:
56: (define_insn ""
1.1.1.3 ! root 57: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 58: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
59: ""
60: "@
61: lbz%U1%X1 %0,%1
62: rlinm %0,%1,0,24,31"
63: [(set_attr "type" "load,*")])
64:
65: (define_insn ""
66: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 67: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1.1 root 68: (const_int 0)))
69: (clobber (match_scratch:SI 2 "=r"))]
70: ""
71: "andil. %2,%1,255"
72: [(set_attr "type" "compare")])
73:
74: (define_insn ""
75: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 ! root 76: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1.1 root 77: (const_int 0)))
1.1.1.3 ! root 78: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 79: (zero_extend:SI (match_dup 1)))]
80: ""
81: "andil. %0,%1,255"
82: [(set_attr "type" "compare")])
83:
84: (define_expand "zero_extendqihi2"
1.1.1.3 ! root 85: [(set (match_operand:HI 0 "gpc_reg_operand" "")
! 86: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1.1 root 87: ""
88: "")
89:
90: (define_insn ""
1.1.1.3 ! root 91: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1.1 root 92: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
93: ""
94: "@
95: lbz%U1%X1 %0,%1
96: rlinm %0,%1,0,24,31"
97: [(set_attr "type" "load,*")])
98:
99: (define_expand "zero_extendhisi2"
1.1.1.3 ! root 100: [(set (match_operand:SI 0 "gpc_reg_operand" "r")
! 101: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1.1 root 102: ""
103: "")
104:
105: (define_insn ""
1.1.1.3 ! root 106: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 107: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
108: ""
109: "@
110: lhz%U1%X1 %0,%1
111: rlinm %0,%1,0,16,31"
112: [(set_attr "type" "load,*")])
113:
114: (define_insn ""
115: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 116: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 117: (const_int 0)))
118: (clobber (match_scratch:SI 2 "=r"))]
119: ""
120: "andil. %2,%1,65535"
121: [(set_attr "type" "compare")])
122:
123: (define_insn ""
124: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 ! root 125: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 126: (const_int 0)))
1.1.1.3 ! root 127: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 128: (zero_extend:SI (match_dup 1)))]
129: ""
130: "andil. %0,%1,65535"
131: [(set_attr "type" "compare")])
132:
133: (define_expand "extendhisi2"
1.1.1.3 ! root 134: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 135: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1.1 root 136: ""
137: "")
138:
139: (define_insn ""
1.1.1.3 ! root 140: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 141: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
142: ""
143: "@
144: lha%U1%X1 %0,%1
145: exts %0,%1"
146: [(set_attr "type" "load,*")])
147:
148: (define_insn ""
149: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 150: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 151: (const_int 0)))
152: (clobber (match_scratch:SI 2 "=r"))]
153: ""
154: "exts. %2,%1"
155: [(set_attr "type" "compare")])
156:
157: (define_insn ""
158: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 ! root 159: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 160: (const_int 0)))
1.1.1.3 ! root 161: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 162: (sign_extend:SI (match_dup 1)))]
163: ""
164: "exts. %0,%1"
165: [(set_attr "type" "compare")])
166:
167: ;; Fixed-point arithmetic insns.
1.1.1.3 ! root 168: (define_insn "addsi3"
! 169: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 170: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
1.1 root 171: (match_operand:SI 2 "add_operand" "rI,J")))]
172: ""
173: "@
174: a%I2 %0,%1,%2
175: cau %0,%1,%u2")
176:
177: (define_insn ""
178: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 179: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 180: (match_operand:SI 2 "reg_or_short_operand" "rI"))
181: (const_int 0)))
182: (clobber (match_scratch:SI 3 "=r"))]
183: ""
184: "a%I2. %3,%1,%2"
185: [(set_attr "type" "compare")])
186:
187: (define_insn ""
188: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 189: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 190: (match_operand:SI 2 "reg_or_short_operand" "rI"))
191: (const_int 0)))
1.1.1.3 ! root 192: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 193: (plus:SI (match_dup 1) (match_dup 2)))]
194: ""
195: "a%I2. %0,%1,%2"
196: [(set_attr "type" "compare")])
197:
1.1.1.3 ! root 198: ;; Split an add that we can't do in one insn into two insns, each of which
! 199: ;; does one 16-bit part. This is used by combine. Note that the low-order
! 200: ;; add should be last in case the result gets used in an address.
! 201:
! 202: (define_split
! 203: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 204: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 205: (match_operand:SI 2 "non_add_cint_operand" "")))]
! 206: ""
! 207: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
! 208: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
! 209: "
1.1 root 210: {
1.1.1.3 ! root 211: int low = INTVAL (operands[2]) & 0xffff;
! 212: int high = (unsigned) INTVAL (operands[2]) >> 16;
1.1 root 213:
1.1.1.3 ! root 214: if (low & 0x8000)
! 215: high++, low |= 0xffff0000;
1.1 root 216:
1.1.1.3 ! root 217: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
! 218: operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
1.1 root 219: }")
220:
221: (define_insn "one_cmplsi2"
1.1.1.3 ! root 222: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 223: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 224: ""
225: "sfi %0,%1,-1")
226:
227: (define_insn ""
1.1.1.3 ! root 228: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 229: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1.1.1.3 ! root 230: (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1.1 root 231: ""
232: "@
233: sf %0,%2,%1
234: sfi %0,%2,%1")
235:
236: (define_insn ""
237: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 238: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 239: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 240: (const_int 0)))
241: (clobber (match_scratch:SI 3 "=r"))]
242: ""
243: "sf. %3,%2,%1"
244: [(set_attr "type" "compare")])
245:
246: (define_insn ""
247: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 248: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 249: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 250: (const_int 0)))
1.1.1.3 ! root 251: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 252: (minus:SI (match_dup 1) (match_dup 2)))]
253: ""
254: "sf. %0,%2,%1"
255: [(set_attr "type" "compare")])
256:
257: (define_expand "subsi3"
1.1.1.3 ! root 258: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 259: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
260: (match_operand:SI 2 "reg_or_cint_operand" "")))]
261: ""
262: "
263: {
264: if (GET_CODE (operands[2]) == CONST_INT)
265: {
266: emit_insn (gen_addsi3 (operands[0], operands[1],
267: negate_rtx (SImode, operands[2])));
268: DONE;
269: }
270: }")
271:
272: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
273: ;; instruction and some auxiliary computations. Then we just have a single
274: ;; DEFINE_INSN for doz[i].
275:
276: (define_expand "sminsi3"
277: [(set (match_dup 3)
1.1.1.3 ! root 278: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 279: (match_operand:SI 2 "reg_or_short_operand" ""))
280: (const_int 0)
281: (minus:SI (match_dup 2) (match_dup 1))))
1.1.1.3 ! root 282: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 283: (minus:SI (match_dup 2) (match_dup 3)))]
284: ""
285: "
286: { operands[3] = gen_reg_rtx (SImode); }")
287:
288: (define_expand "smaxsi3"
289: [(set (match_dup 3)
1.1.1.3 ! root 290: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 291: (match_operand:SI 2 "reg_or_short_operand" ""))
292: (const_int 0)
293: (minus:SI (match_dup 2) (match_dup 1))))
1.1.1.3 ! root 294: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 295: (plus:SI (match_dup 3) (match_dup 1)))]
296: ""
297: "
298: { operands[3] = gen_reg_rtx (SImode); }")
299:
300: (define_expand "uminsi3"
1.1.1.3 ! root 301: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 302: (const_int -2147483648)))
1.1.1.3 ! root 303: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1.1 root 304: (const_int -2147483648)))
305: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
306: (const_int 0)
307: (minus:SI (match_dup 4) (match_dup 3))))
1.1.1.3 ! root 308: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 309: (minus:SI (match_dup 2) (match_dup 3)))]
310: ""
311: "
312: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
313:
314: (define_expand "umaxsi3"
1.1.1.3 ! root 315: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 316: (const_int -2147483648)))
1.1.1.3 ! root 317: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1.1 root 318: (const_int -2147483648)))
319: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
320: (const_int 0)
321: (minus:SI (match_dup 4) (match_dup 3))))
1.1.1.3 ! root 322: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 323: (plus:SI (match_dup 3) (match_dup 1)))]
324: ""
325: "
326: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
327:
328: (define_insn ""
1.1.1.3 ! root 329: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 330: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 331: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 332: (const_int 0)
333: (minus:SI (match_dup 2) (match_dup 1))))]
334: ""
335: "doz%I2 %0,%1,%2")
336:
337: (define_insn ""
338: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
339: (compare:CC
1.1.1.3 ! root 340: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 341: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 342: (const_int 0)
343: (minus:SI (match_dup 2) (match_dup 1)))
344: (const_int 0)))
345: (clobber (match_scratch:SI 3 "=r"))]
346: ""
347: "doz%I2. %3,%1,%2"
348: [(set_attr "type" "delayed_compare")])
349:
350: (define_insn ""
351: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
352: (compare:CC
1.1.1.3 ! root 353: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 354: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 355: (const_int 0)
356: (minus:SI (match_dup 2) (match_dup 1)))
357: (const_int 0)))
1.1.1.3 ! root 358: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 359: (if_then_else:SI (gt (match_dup 1) (match_dup 2))
360: (const_int 0)
361: (minus:SI (match_dup 2) (match_dup 1))))]
362: ""
363: "doz%I2. %0,%1,%2"
364: [(set_attr "type" "delayed_compare")])
365:
366: ;; We don't need abs with condition code because such comparisons should
367: ;; never be done.
368: (define_insn "abssi2"
1.1.1.3 ! root 369: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 370: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 371: ""
372: "abs %0,%1")
373:
374: (define_insn ""
1.1.1.3 ! root 375: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 376: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1.1 root 377: ""
378: "nabs %0,%1")
379:
380: (define_insn "negsi2"
1.1.1.3 ! root 381: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 382: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 383: ""
384: "neg %0,%1")
385:
386: (define_insn ""
387: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 388: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 389: (const_int 0)))
390: (clobber (match_scratch:SI 2 "=r"))]
391: ""
392: "neg. %2,%1"
393: [(set_attr "type" "compare")])
394:
395: (define_insn ""
396: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 ! root 397: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 398: (const_int 0)))
1.1.1.3 ! root 399: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 400: (neg:SI (match_dup 1)))]
401: ""
402: "neg. %0,%1"
403: [(set_attr "type" "compare")])
404:
405: (define_insn "ffssi2"
406: [(set (match_operand:SI 0 "register_operand" "=&r")
407: (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
408: ""
409: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
410:
411: ;; There is no need for (set (condition) (compare (ffs) 0)) because that
412: ;; can be simplified to an ordinary comparison. A parallel set and compare
413: ;; might be used, so include it.
414:
415: (define_insn ""
416: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
417: (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
418: (const_int 0)))
419: (set (match_operand:SI 0 "register_operand" "=&r")
420: (ffs:SI (match_dup 1)))]
421: ""
422: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
423: [(set_attr "type" "compare")])
424:
425: (define_insn "mulsi3"
1.1.1.3 ! root 426: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 427: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1.1 root 428: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
429: (clobber (match_scratch:SI 3 "=q,q"))]
430: ""
431: "@
432: muls %0,%1,%2
433: muli %0,%1,%2")
434:
435: (define_insn ""
436: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 437: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 438: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 439: (const_int 0)))
440: (clobber (match_scratch:SI 3 "=r"))
441: (clobber (match_scratch:SI 4 "=q"))]
442: ""
443: "muls. %3,%1,%2"
444: [(set_attr "type" "delayed_compare")])
445:
446: (define_insn ""
447: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 448: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 449: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 450: (const_int 0)))
1.1.1.3 ! root 451: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 452: (mult:SI (match_dup 1) (match_dup 2)))
453: (clobber (match_scratch:SI 4 "=q"))]
454: ""
455: "muls. %0,%1,%2"
456: [(set_attr "type" "delayed_compare")])
457:
458: ;; Operand 1 is divided by operand 2; quotient goes to operand
459: ;; 0 and remainder to operand 3.
460: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
461:
462: (define_insn "divmodsi4"
1.1.1.3 ! root 463: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 464: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 465: (match_operand:SI 2 "gpc_reg_operand" "r")))
! 466: (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1.1 root 467: (mod:SI (match_dup 1) (match_dup 2)))]
468: ""
469: "divs %0,%1,%2")
470:
471: ;; For powers of two we can do srai/aze for divide and then adjust for
472: ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
473: (define_expand "divsi3"
1.1.1.3 ! root 474: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 475: (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 476: (match_operand:SI 2 "reg_or_cint_operand" "")))]
477: ""
478: "
479: {
480: if (GET_CODE (operands[2]) != CONST_INT
481: || exact_log2 (INTVAL (operands[2])) < 0)
482: FAIL;
483: }")
484:
485: (define_expand "modsi3"
486: [(set (match_dup 3)
1.1.1.3 ! root 487: (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 488: (match_operand:SI 2 "reg_or_cint_operand" "")))
489: (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
490: (clobber (scratch:SI))])
1.1.1.3 ! root 491: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 492: (minus:SI (match_dup 1) (match_dup 4)))]
493: ""
494: "
495: {
496: int i = exact_log2 (INTVAL (operands[2]));
497:
498: if (GET_CODE (operands[2]) != CONST_INT || i < 0)
499: FAIL;
500:
501: operands[3] = gen_reg_rtx (SImode);
502: operands[4] = gen_reg_rtx (SImode);
503: operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
504: }")
505:
506: (define_insn ""
1.1.1.3 ! root 507: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 508: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 509: (match_operand:SI 2 "const_int_operand" "N")))]
510: "exact_log2 (INTVAL (operands[2])) >= 0"
511: "srai %0,%1,%p2\;aze %0,%0")
512:
513: (define_insn ""
514: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 515: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 516: (match_operand:SI 2 "const_int_operand" "N")))
517: (clobber (match_scratch:SI 3 "=r"))]
518: "exact_log2 (INTVAL (operands[2])) >= 0"
519: "srai %3,%1,%p2\;aze. %3,%3"
520: [(set_attr "type" "compare")])
521:
522: (define_insn ""
523: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 524: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 525: (match_operand:SI 2 "const_int_operand" "N")))
1.1.1.3 ! root 526: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 527: (div:SI (match_dup 1) (match_dup 2)))]
528: "exact_log2 (INTVAL (operands[2])) >= 0"
529: "srai %0,%1,%p2\;aze. %0,%0"
530: [(set_attr "type" "compare")])
531:
532: (define_insn ""
1.1.1.3 ! root 533: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 534: (udiv:SI
535: (plus:DI (lshift:DI
1.1.1.3 ! root 536: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 537: (const_int 32))
538: (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
1.1.1.3 ! root 539: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 540: (set (match_operand:SI 4 "register_operand" "=*q")
541: (umod:SI
542: (plus:DI (lshift:DI
543: (zero_extend:DI (match_dup 1)) (const_int 32))
544: (zero_extend:DI (match_dup 2)))
545: (match_dup 3)))]
546:
547: ""
548: "div %0,%1,%3")
549:
550: ;; To do unsigned divide we handle the cases of the divisor looking like a
551: ;; negative number. If it is a constant that is less than 2**31, we don't
552: ;; have to worry about the branches. So make a few subroutines here.
553: ;;
554: ;; First comes the normal case.
555: (define_expand "udivmodsi4_normal"
556: [(set (match_dup 4) (const_int 0))
557: (parallel [(set (match_operand:SI 0 "" "")
558: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
559: (const_int 32))
560: (zero_extend:DI (match_operand:SI 1 "" "")))
561: (match_operand:SI 2 "" "")))
562: (set (match_operand:SI 3 "" "")
563: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
564: (const_int 32))
565: (zero_extend:DI (match_dup 1)))
566: (match_dup 2)))])]
567: ""
568: "
569: { operands[4] = gen_reg_rtx (SImode); }")
570:
571: ;; This handles the branches.
572: (define_expand "udivmodsi4_tests"
573: [(set (match_operand:SI 0 "" "") (const_int 0))
574: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
575: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
576: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
577: (label_ref (match_operand:SI 4 "" "")) (pc)))
578: (set (match_dup 0) (const_int 1))
579: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
580: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
581: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
582: (label_ref (match_dup 4)) (pc)))]
583: ""
584: "
585: { operands[5] = gen_reg_rtx (CCUNSmode);
586: operands[6] = gen_reg_rtx (CCmode);
587: }")
588:
589: (define_expand "udivmodsi4"
1.1.1.3 ! root 590: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 591: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 592: (match_operand:SI 2 "reg_or_cint_operand" "")))
1.1.1.3 ! root 593: (set (match_operand:SI 3 "gpc_reg_operand" "")
1.1 root 594: (umod:SI (match_dup 1) (match_dup 2)))])]
595: ""
596: "
597: {
598: rtx label = 0;
599:
600: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
601: {
602: operands[2] = force_reg (SImode, operands[2]);
603: label = gen_label_rtx ();
604: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
605: operands[3], label));
606: }
607: else
608: operands[2] = force_reg (SImode, operands[2]);
609:
610: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
611: operands[3]));
612: if (label)
613: emit_label (label);
614:
615: DONE;
616: }")
617:
618: (define_insn "andsi3"
1.1.1.3 ! root 619: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
! 620: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 621: (match_operand:SI 2 "and_operand" "?r,L,K,J")))
622: (clobber (match_scratch:CC 3 "=X,X,x,x"))]
623: ""
624: "@
625: and %0,%1,%2
626: rlinm %0,%1,0,%m2,%M2
627: andil. %0,%1,%b2
628: andiu. %0,%1,%u2")
629:
630: (define_insn ""
631: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1.1.1.3 ! root 632: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 633: (match_operand:SI 2 "and_operand" "r,K,J,L"))
634: (const_int 0)))
635: (clobber (match_scratch:SI 3 "=r,r,r,r"))]
636: ""
637: "@
638: and. %3,%1,%2
639: andil. %3,%1,%b2
640: andiu. %3,%1,%u2
641: rlinm. %3,%1,0,%m2,%M2"
642: [(set_attr "type" "compare,compare,compare,delayed_compare")])
643:
644: (define_insn ""
645: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1.1.1.3 ! root 646: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 647: (match_operand:SI 2 "and_operand" "r,K,J,L"))
648: (const_int 0)))
1.1.1.3 ! root 649: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1.1 root 650: (and:SI (match_dup 1) (match_dup 2)))]
651: ""
652: "@
653: and. %0,%1,%2
654: andil. %0,%1,%b2
655: andiu. %0,%1,%u2
656: rlinm. %0,%1,0,%m2,%M2"
657: [(set_attr "type" "compare,compare,compare,delayed_compare")])
658:
1.1.1.3 ! root 659: ;; Take a AND with a constant that cannot be done in a single insn and try to
! 660: ;; split it into two insns. This does not verify that the insns are valid
! 661: ;; since this need not be done as combine will do it.
! 662:
! 663: (define_split
! 664: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 665: (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 666: (match_operand:SI 2 "non_and_cint_operand" "")))]
! 667: ""
! 668: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
! 669: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
! 670: "
! 671: {
! 672: int maskval = INTVAL (operands[2]);
! 673: int i, transitions, last_bit_value;
! 674: int orig = maskval, first_c = maskval, second_c;
! 675:
! 676: /* We know that MASKVAL must have more than 2 bit-transitions. Start at
! 677: the low-order bit and count for the third transition. When we get there,
! 678: make a first mask that has everything to the left of that position
! 679: a one. Then make the second mask to turn off whatever else is needed. */
! 680:
! 681: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
! 682: {
! 683: if (((maskval >>= 1) & 1) != last_bit_value)
! 684: last_bit_value ^= 1, transitions++;
! 685:
! 686: if (transitions > 2)
! 687: {
! 688: first_c |= (~0) << i;
! 689: break;
! 690: }
! 691: }
! 692:
! 693: second_c = orig | ~ first_c;
! 694:
! 695: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
! 696: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
! 697: }")
! 698:
! 699: (define_insn "iorsi3"
! 700: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
! 701: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1.1 root 702: (match_operand:SI 2 "logical_operand" "r,K,J")))]
703: ""
704: "@
705: or %0,%1,%2
706: oril %0,%1,%b2
707: oriu %0,%1,%u2")
708:
709: (define_insn ""
710: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 711: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 712: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 713: (const_int 0)))
714: (clobber (match_scratch:SI 3 "=r"))]
715: ""
716: "or. %3,%1,%2"
717: [(set_attr "type" "compare")])
718:
719: (define_insn ""
720: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 721: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 722: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 723: (const_int 0)))
1.1.1.3 ! root 724: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 725: (ior:SI (match_dup 1) (match_dup 2)))]
726: ""
727: "or. %0,%1,%2"
728: [(set_attr "type" "compare")])
729:
1.1.1.3 ! root 730: ;; Split an IOR that we can't do in one insn into two insns, each of which
! 731: ;; does one 16-bit part. This is used by combine.
! 732:
! 733: (define_split
! 734: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 735: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 736: (match_operand:SI 2 "non_logical_cint_operand" "")))]
! 737: ""
! 738: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
! 739: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
! 740: "
1.1 root 741: {
1.1.1.3 ! root 742: operands[3] = gen_rtx (CONST_INT, VOIDmode,
! 743: INTVAL (operands[2]) & 0xffff0000);
! 744: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1.1 root 745: }")
746:
1.1.1.3 ! root 747: (define_insn "xorsi3"
! 748: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
! 749: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1.1 root 750: (match_operand:SI 2 "logical_operand" "r,K,J")))]
751: ""
752: "@
753: xor %0,%1,%2
754: xoril %0,%1,%b2
755: xoriu %0,%1,%u2")
756:
757: (define_insn ""
758: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 759: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 760: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 761: (const_int 0)))
762: (clobber (match_scratch:SI 3 "=r"))]
763: ""
764: "xor. %3,%1,%2"
765: [(set_attr "type" "compare")])
766:
767: (define_insn ""
768: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 769: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! 770: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 771: (const_int 0)))
1.1.1.3 ! root 772: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 773: (xor:SI (match_dup 1) (match_dup 2)))]
774: ""
775: "xor. %0,%1,%2"
776: [(set_attr "type" "compare")])
777:
1.1.1.3 ! root 778: ;; Split an XOR that we can't do in one insn into two insns, each of which
! 779: ;; does one 16-bit part. This is used by combine.
! 780:
! 781: (define_split
! 782: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 783: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 784: (match_operand:SI 2 "non_logical_cint_operand" "")))]
! 785: ""
! 786: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
! 787: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
! 788: "
1.1 root 789: {
1.1.1.3 ! root 790: operands[3] = gen_rtx (CONST_INT, VOIDmode,
! 791: INTVAL (operands[2]) & 0xffff0000);
! 792: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1.1 root 793: }")
794:
795: (define_insn ""
1.1.1.3 ! root 796: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 797: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
! 798: (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 799: ""
800: "eqv %0,%1,%2")
801:
802: (define_insn ""
803: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 804: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
! 805: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 806: (const_int 0)))
807: (clobber (match_scratch:SI 3 "=r"))]
808: ""
809: "eqv. %3,%1,%2"
810: [(set_attr "type" "compare")])
811:
812: (define_insn ""
813: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 814: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
! 815: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 816: (const_int 0)))
1.1.1.3 ! root 817: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 818: (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
819: ""
820: "eqv. %0,%1,%2"
821: [(set_attr "type" "compare")])
822:
823: (define_insn ""
1.1.1.3 ! root 824: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 825: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 826: (match_operand:SI 2 "gpc_reg_operand" "r")))]
1.1 root 827: ""
828: "andc %0,%2,%1")
829:
830: (define_insn ""
831: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 832: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 833: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 834: (const_int 0)))
835: (clobber (match_scratch:SI 3 "=r"))]
836: ""
837: "andc. %3,%2,%1"
838: [(set_attr "type" "compare")])
839:
840: (define_insn ""
841: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 842: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 843: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 844: (const_int 0)))
1.1.1.3 ! root 845: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 846: (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
847: ""
848: "andc. %0,%2,%1"
849: [(set_attr "type" "compare")])
850:
851: (define_insn ""
1.1.1.3 ! root 852: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 853: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 854: (match_operand:SI 2 "gpc_reg_operand" "r")))]
1.1 root 855: ""
856: "orc %0,%2,%1")
857:
858: (define_insn ""
859: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 860: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 861: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 862: (const_int 0)))
863: (clobber (match_scratch:SI 3 "=r"))]
864: ""
865: "orc. %3,%2,%1"
866: [(set_attr "type" "compare")])
867:
868: (define_insn ""
869: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 870: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 871: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 872: (const_int 0)))
1.1.1.3 ! root 873: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 874: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
875: ""
876: "orc. %0,%2,%1"
877: [(set_attr "type" "compare")])
878:
879: (define_insn ""
1.1.1.3 ! root 880: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 881: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 882: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 883: ""
884: "nand %0,%1,%2")
885:
886: (define_insn ""
887: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 888: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 889: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 890: (const_int 0)))
891: (clobber (match_scratch:SI 3 "=r"))]
892: ""
893: "nand. %3,%1,%2"
894: [(set_attr "type" "compare")])
895:
896: (define_insn ""
897: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 898: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 899: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 900: (const_int 0)))
1.1.1.3 ! root 901: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 902: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
903: ""
904: "nand. %0,%1,%2"
905: [(set_attr "type" "compare")])
906:
907: (define_insn ""
1.1.1.3 ! root 908: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 909: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 910: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 911: ""
912: "nor %0,%1,%2")
913:
914: (define_insn ""
915: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 916: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 917: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 918: (const_int 0)))
919: (clobber (match_scratch:SI 3 "=r"))]
920: ""
921: "nor. %3,%1,%2"
922: [(set_attr "type" "compare")])
923:
924: (define_insn ""
925: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 926: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 927: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 928: (const_int 0)))
1.1.1.3 ! root 929: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 930: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
931: ""
932: "nor. %0,%1,%2"
933: [(set_attr "type" "compare")])
934:
935: ;; maskir insn. We need four forms because things might be in arbitrary
936: ;; orders. Don't define forms that only set CR fields because these
937: ;; would modify an input register.
938:
939: (define_insn ""
1.1.1.3 ! root 940: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 941: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 942: (match_operand:SI 2 "gpc_reg_operand" "0"))
1.1 root 943: (and:SI (match_dup 1)
1.1.1.3 ! root 944: (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1.1 root 945: ""
946: "maskir %0,%3,%1")
947:
948: (define_insn ""
949: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.3 ! root 950: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 951: (match_operand:SI 2 "gpc_reg_operand" "0"))
! 952: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1 root 953: (match_dup 1))))]
954: ""
955: "maskir %0,%3,%1")
956:
957: (define_insn ""
1.1.1.3 ! root 958: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 959: (ior:SI (and:SI (match_dup 1)
1.1.1.3 ! root 960: (match_operand:SI 3 "gpc_reg_operand" "r"))
! 961: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 962: (match_operand:SI 2 "gpc_reg_operand" "0"))))]
1.1 root 963: ""
964: "maskir %0,%3,%1")
965:
966: (define_insn ""
1.1.1.3 ! root 967: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 968: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1 root 969: (match_dup 1))
1.1.1.3 ! root 970: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 971: (match_operand:SI 2 "gpc_reg_operand" "0"))))]
1.1 root 972: ""
973: "maskir %0,%3,%1")
974:
975: (define_insn ""
976: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
977: (compare:CC
1.1.1.3 ! root 978: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 979: (match_operand:SI 2 "gpc_reg_operand" "0"))
1.1 root 980: (and:SI (match_dup 1)
1.1.1.3 ! root 981: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 982: (const_int 0)))
1.1.1.3 ! root 983: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 984: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
985: (and:SI (match_dup 1) (match_dup 3))))]
986: ""
987: "maskir. %0,%3,%1"
988: [(set_attr "type" "compare")])
989:
990: (define_insn ""
991: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
992: (compare:CC
1.1.1.3 ! root 993: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 994: (match_operand:SI 2 "gpc_reg_operand" "0"))
! 995: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1 root 996: (match_dup 1)))
997: (const_int 0)))
998: (set (match_operand:SI 0 "register_operand" "=r")
999: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
1000: (and:SI (match_dup 3) (match_dup 1))))]
1001: ""
1002: "maskir. %0,%3,%1"
1003: [(set_attr "type" "compare")])
1004:
1005: (define_insn ""
1006: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1007: (compare:CC
1008: (ior:SI (and:SI (match_dup 1)
1.1.1.3 ! root 1009: (match_operand:SI 3 "gpc_reg_operand" "r"))
! 1010: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1011: (match_operand:SI 2 "gpc_reg_operand" "0")))
1.1 root 1012: (const_int 0)))
1.1.1.3 ! root 1013: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1014: (ior:SI (and:SI (match_dup 1) (match_dup 3))
1015: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1016: ""
1017: "maskir. %0,%3,%1"
1018: [(set_attr "type" "compare")])
1019:
1020: (define_insn ""
1021: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1022: (compare:CC
1.1.1.3 ! root 1023: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1 root 1024: (match_dup 1))
1.1.1.3 ! root 1025: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1026: (match_operand:SI 2 "gpc_reg_operand" "0")))
1.1 root 1027: (const_int 0)))
1.1.1.3 ! root 1028: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1029: (ior:SI (and:SI (match_dup 3) (match_dup 1))
1030: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1031: ""
1032: "maskir. %0,%3,%1"
1033: [(set_attr "type" "compare")])
1034:
1035: ;; Rotate and shift insns, in all their variants. These support shifts,
1036: ;; field inserts and extracts, and various combinations thereof.
1037: (define_insn "insv"
1.1.1.3 ! root 1038: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1039: (match_operand:SI 1 "const_int_operand" "i")
1040: (match_operand:SI 2 "const_int_operand" "i"))
1.1.1.3 ! root 1041: (match_operand:SI 3 "gpc_reg_operand" "r"))]
1.1 root 1042: ""
1043: "*
1044: {
1045: int start = INTVAL (operands[2]) & 31;
1046: int size = INTVAL (operands[1]) & 31;
1047:
1048: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1049: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1050: return \"rlimi %0,%3,%4,%h2,%h1\";
1051: }")
1052:
1053: (define_insn "extzv"
1.1.1.3 ! root 1054: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 1055: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1056: (match_operand:SI 2 "const_int_operand" "i")
1057: (match_operand:SI 3 "const_int_operand" "i")))]
1058: ""
1059: "*
1060: {
1061: int start = INTVAL (operands[3]) & 31;
1062: int size = INTVAL (operands[2]) & 31;
1063:
1064: if (start + size >= 32)
1065: operands[3] = const0_rtx;
1066: else
1067: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1068: return \"rlinm %0,%1,%3,%s2,31\";
1069: }")
1070:
1071: (define_insn ""
1072: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 1073: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1074: (match_operand:SI 2 "const_int_operand" "i")
1075: (match_operand:SI 3 "const_int_operand" "i"))
1076: (const_int 0)))
1077: (clobber (match_scratch:SI 4 "=r"))]
1078: ""
1079: "*
1080: {
1081: int start = INTVAL (operands[3]) & 31;
1082: int size = INTVAL (operands[2]) & 31;
1083:
1.1.1.3 ! root 1084: /* If the bitfield being tested fits in the upper or lower half of a
! 1085: word, it is possible to use andiu. or andil. to test it. This is
! 1086: useful because the condition register set-use delay is smaller for
! 1087: andi[ul]. than for rlinm. This doesn't work when the starting bit
! 1088: position is 0 because the LT and GT bits may be set wrong. */
! 1089:
! 1090: if ((start > 0 && start + size <= 16) || start >= 16)
! 1091: {
! 1092: operands[3] = gen_rtx (CONST_INT, VOIDmode,
! 1093: ((1 << (16 - (start & 15)))
! 1094: - (1 << (16 - (start & 15) - size))));
! 1095: if (start < 16)
! 1096: return \"andiu. %4,%1,%3\";
! 1097: else
! 1098: return \"andil. %4,%1,%3\";
! 1099: }
! 1100:
1.1 root 1101: if (start + size >= 32)
1102: operands[3] = const0_rtx;
1103: else
1104: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1105: return \"rlinm. %4,%1,%3,%s2,31\";
1106: }"
1107: [(set_attr "type" "compare")])
1108:
1109: (define_insn ""
1110: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1.1.1.3 ! root 1111: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1112: (match_operand:SI 2 "const_int_operand" "i")
1113: (match_operand:SI 3 "const_int_operand" "i"))
1114: (const_int 0)))
1.1.1.3 ! root 1115: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1116: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1117: ""
1118: "*
1119: {
1120: int start = INTVAL (operands[3]) & 31;
1121: int size = INTVAL (operands[2]) & 31;
1122:
1.1.1.3 ! root 1123: if (start >= 16 && start + size == 32)
! 1124: {
! 1125: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
! 1126: return \"andil. %0,%1,%3\";
! 1127: }
! 1128:
1.1 root 1129: if (start + size >= 32)
1130: operands[3] = const0_rtx;
1131: else
1132: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1133: return \"rlinm. %0,%1,%3,%s2,31\";
1134: }"
1135: [(set_attr "type" "delayed_compare")])
1136:
1137: (define_insn "rotlsi3"
1.1.1.3 ! root 1138: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 1139: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1140: (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1141: ""
1142: "rl%I2nm %0,%1,%h2,0,31")
1143:
1144: (define_insn ""
1145: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 ! root 1146: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1147: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1148: (const_int 0)))
1149: (clobber (match_scratch:SI 3 "=r"))]
1150: ""
1151: "rl%I2nm. %3,%1,%h2,0,31"
1152: [(set_attr "type" "delayed_compare")])
1153:
1154: (define_insn ""
1155: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 ! root 1156: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1157: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1158: (const_int 0)))
1.1.1.3 ! root 1159: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1160: (rotate:SI (match_dup 1) (match_dup 2)))]
1161: ""
1162: "rl%I2nm. %0,%1,%h2,0,31"
1163: [(set_attr "type" "delayed_compare")])
1164:
1165: (define_insn ""
1.1.1.3 ! root 1166: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 1167: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1168: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1169: (match_operand:SI 3 "mask_operand" "L")))]
1170: ""
1171: "rl%I2nm %0,%1,%h2,%m3,%M3")
1172:
1173: (define_insn ""
1174: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1175: (compare:CC (and:SI
1.1.1.3 ! root 1176: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1177: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1178: (match_operand:SI 3 "mask_operand" "L"))
1179: (const_int 0)))
1180: (clobber (match_scratch:SI 4 "=r"))]
1181: ""
1182: "rl%I2nm. %4,%1,%h2,%m3,%M3"
1183: [(set_attr "type" "delayed_compare")])
1184:
1185: (define_insn ""
1186: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1187: (compare:CC (and:SI
1.1.1.3 ! root 1188: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1189: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1190: (match_operand:SI 3 "mask_operand" "L"))
1191: (const_int 0)))
1.1.1.3 ! root 1192: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1193: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1194: ""
1195: "rl%I2nm. %0,%1,%h2,%m3,%M3"
1196: [(set_attr "type" "delayed_compare")])
1197:
1198: (define_insn ""
1.1.1.3 ! root 1199: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1200: (zero_extend:SI
1201: (subreg:QI
1.1.1.3 ! root 1202: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1203: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1204: ""
1205: "rl%I2nm %0,%1,%h2,24,31")
1206:
1207: (define_insn ""
1208: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1209: (compare:CC (zero_extend:SI
1210: (subreg:QI
1.1.1.3 ! root 1211: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1212: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1213: (const_int 0)))
1214: (clobber (match_scratch:SI 3 "=r"))]
1215: ""
1216: "rl%I2nm. %3,%1,%h2,24,31"
1217: [(set_attr "type" "delayed_compare")])
1218:
1219: (define_insn ""
1220: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1221: (compare:CC (zero_extend:SI
1222: (subreg:QI
1.1.1.3 ! root 1223: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1224: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1225: (const_int 0)))
1.1.1.3 ! root 1226: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1227: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1228: ""
1229: "rl%I2nm. %0,%1,%h2,24,31"
1230: [(set_attr "type" "delayed_compare")])
1231:
1232: (define_insn ""
1.1.1.3 ! root 1233: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1234: (zero_extend:SI
1235: (subreg:HI
1.1.1.3 ! root 1236: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1237: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1238: ""
1239: "rl%I2nm %0,%1,%h2,16,31")
1240:
1241: (define_insn ""
1242: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1243: (compare:CC (zero_extend:SI
1244: (subreg:HI
1.1.1.3 ! root 1245: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1246: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1247: (const_int 0)))
1248: (clobber (match_scratch:SI 3 "=r"))]
1249: ""
1250: "rl%I2nm. %3,%1,%h2,16,31"
1251: [(set_attr "type" "delayed_compare")])
1252:
1253: (define_insn ""
1254: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1255: (compare:CC (zero_extend:SI
1256: (subreg:HI
1.1.1.3 ! root 1257: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1258: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1259: (const_int 0)))
1.1.1.3 ! root 1260: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1261: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1262: ""
1263: "rl%I2nm. %0,%1,%h2,16,31"
1264: [(set_attr "type" "delayed_compare")])
1265:
1266: ;; Note that we use "sle." instead of "sl." so that we can set
1267: ;; SHIFT_COUNT_TRUNCATED.
1268:
1269: (define_insn "ashlsi3"
1.1.1.3 ! root 1270: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 1271: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1272: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1273: (clobber (match_scratch:SI 3 "=q,X"))]
1274: ""
1275: "@
1276: sle %0,%1,%2
1277: sli %0,%1,%h2")
1278:
1279: (define_insn ""
1280: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1281: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1282: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1283: (const_int 0)))
1284: (clobber (match_scratch:SI 3 "=r,r"))
1285: (clobber (match_scratch:SI 4 "=q,X"))]
1286: ""
1287: "@
1288: sle. %3,%1,%2
1289: sli. %3,%1,%h2"
1290: [(set_attr "type" "delayed_compare")])
1291:
1292: (define_insn ""
1293: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1294: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1295: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1296: (const_int 0)))
1.1.1.3 ! root 1297: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1298: (ashift:SI (match_dup 1) (match_dup 2)))
1299: (clobber (match_scratch:SI 4 "=q,X"))]
1300: ""
1301: "@
1302: sle. %0,%1,%2
1303: sli. %0,%1,%h2"
1304: [(set_attr "type" "delayed_compare")])
1305:
1306: (define_insn ""
1.1.1.3 ! root 1307: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 1308: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1309: (match_operand:SI 2 "const_int_operand" "i"))
1310: (match_operand:SI 3 "mask_operand" "L")))]
1311: "includes_lshift_p (operands[2], operands[3])"
1312: "rlinm %0,%h1,%h2,%m3,%M3")
1313:
1314: (define_insn ""
1315: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1316: (compare:CC
1.1.1.3 ! root 1317: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1318: (match_operand:SI 2 "const_int_operand" "i"))
1319: (match_operand:SI 3 "mask_operand" "L"))
1320: (const_int 0)))
1321: (clobber (match_scratch:SI 4 "=r"))]
1322: "includes_lshift_p (operands[2], operands[3])"
1323: "rlinm. %4,%h1,%h2,%m3,%M3"
1324: [(set_attr "type" "delayed_compare")])
1325:
1326: (define_insn ""
1327: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1328: (compare:CC
1.1.1.3 ! root 1329: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1330: (match_operand:SI 2 "const_int_operand" "i"))
1331: (match_operand:SI 3 "mask_operand" "L"))
1332: (const_int 0)))
1.1.1.3 ! root 1333: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1334: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1335: "includes_lshift_p (operands[2], operands[3])"
1336: "rlinm. %0,%h1,%h2,%m3,%M3"
1337: [(set_attr "type" "delayed_compare")])
1338:
1.1.1.2 root 1339: ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
1340: ;; "sli x,x,0".
1.1 root 1341: (define_insn "lshrsi3"
1.1.1.3 ! root 1342: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 1343: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1344: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1345: (clobber (match_scratch:SI 3 "=q,X"))]
1346: ""
1347: "@
1348: sre %0,%1,%2
1.1.1.2 root 1349: s%A2i %0,%1,%h2")
1.1 root 1350:
1351: (define_insn ""
1352: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1353: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1354: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1355: (const_int 0)))
1356: (clobber (match_scratch:SI 3 "=r,r"))
1357: (clobber (match_scratch:SI 4 "=q,X"))]
1358: ""
1359: "@
1360: sre. %3,%1,%2
1.1.1.2 root 1361: s%A2i. %3,%1,%h2"
1.1 root 1362: [(set_attr "type" "delayed_compare")])
1363:
1364: (define_insn ""
1365: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1366: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1367: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1368: (const_int 0)))
1.1.1.3 ! root 1369: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1370: (lshiftrt:SI (match_dup 1) (match_dup 2)))
1371: (clobber (match_scratch:SI 4 "=q,X"))]
1372: ""
1373: "@
1374: sre. %0,%1,%2
1.1.1.2 root 1375: s%A2i. %0,%1,%h2"
1.1 root 1376: [(set_attr "type" "delayed_compare")])
1377:
1378: (define_insn ""
1.1.1.3 ! root 1379: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 1380: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1381: (match_operand:SI 2 "const_int_operand" "i"))
1382: (match_operand:SI 3 "mask_operand" "L")))]
1383: "includes_rshift_p (operands[2], operands[3])"
1384: "rlinm %0,%1,%s2,%m3,%M3")
1385:
1386: (define_insn ""
1387: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1388: (compare:CC
1.1.1.3 ! root 1389: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1390: (match_operand:SI 2 "const_int_operand" "i"))
1391: (match_operand:SI 3 "mask_operand" "L"))
1392: (const_int 0)))
1393: (clobber (match_scratch:SI 4 "=r"))]
1394: "includes_rshift_p (operands[2], operands[3])"
1395: "rlinm. %4,%1,%s2,%m3,%M3"
1396: [(set_attr "type" "delayed_compare")])
1397:
1398: (define_insn ""
1399: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1400: (compare:CC
1.1.1.3 ! root 1401: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1402: (match_operand:SI 2 "const_int_operand" "i"))
1403: (match_operand:SI 3 "mask_operand" "L"))
1404: (const_int 0)))
1.1.1.3 ! root 1405: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1406: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1407: "includes_rshift_p (operands[2], operands[3])"
1408: "rlinm. %0,%1,%s2,%m3,%M3"
1409: [(set_attr "type" "delayed_compare")])
1410:
1411: (define_insn ""
1.1.1.3 ! root 1412: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1413: (zero_extend:SI
1414: (subreg:QI
1.1.1.3 ! root 1415: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1416: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1417: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1418: "rlinm %0,%1,%s2,24,31")
1419:
1420: (define_insn ""
1421: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1422: (compare:CC
1423: (zero_extend:SI
1424: (subreg:QI
1.1.1.3 ! root 1425: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1426: (match_operand:SI 2 "const_int_operand" "i")) 0))
1427: (const_int 0)))
1428: (clobber (match_scratch:SI 3 "=r"))]
1429: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1430: "rlinm. %3,%1,%s2,24,31"
1431: [(set_attr "type" "delayed_compare")])
1432:
1433: (define_insn ""
1434: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1435: (compare:CC
1436: (zero_extend:SI
1437: (subreg:QI
1.1.1.3 ! root 1438: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1439: (match_operand:SI 2 "const_int_operand" "i")) 0))
1440: (const_int 0)))
1.1.1.3 ! root 1441: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1442: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1443: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1444: "rlinm. %0,%1,%s2,24,31"
1445: [(set_attr "type" "delayed_compare")])
1446:
1447: (define_insn ""
1.1.1.3 ! root 1448: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1449: (zero_extend:SI
1450: (subreg:HI
1.1.1.3 ! root 1451: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1452: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1453: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1454: "rlinm %0,%1,%s2,16,31")
1455:
1456: (define_insn ""
1457: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1458: (compare:CC
1459: (zero_extend:SI
1460: (subreg:HI
1.1.1.3 ! root 1461: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1462: (match_operand:SI 2 "const_int_operand" "i")) 0))
1463: (const_int 0)))
1464: (clobber (match_scratch:SI 3 "=r"))]
1465: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1466: "rlinm. %3,%1,%s2,16,31"
1467: [(set_attr "type" "delayed_compare")])
1468:
1469: (define_insn ""
1470: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1471: (compare:CC
1472: (zero_extend:SI
1473: (subreg:HI
1.1.1.3 ! root 1474: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1475: (match_operand:SI 2 "const_int_operand" "i")) 0))
1476: (const_int 0)))
1.1.1.3 ! root 1477: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1478: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1479: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1480: "rlinm. %0,%1,%s2,16,31"
1481: [(set_attr "type" "delayed_compare")])
1482:
1483: (define_insn ""
1.1.1.3 ! root 1484: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1485: (const_int 1)
1.1.1.3 ! root 1486: (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1487: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1488: (const_int 31)))]
1489: ""
1490: "rrib %0,%1,%2")
1491:
1492: (define_insn ""
1.1.1.3 ! root 1493: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1494: (const_int 1)
1.1.1.3 ! root 1495: (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1496: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1497: (const_int 31)))]
1498: ""
1499: "rrib %0,%1,%2")
1500:
1501: (define_insn ""
1.1.1.3 ! root 1502: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1503: (const_int 1)
1.1.1.3 ! root 1504: (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1505: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1506: (const_int 1)
1507: (const_int 0)))]
1508: ""
1509: "rrib %0,%1,%2")
1510:
1511: (define_insn "ashrsi3"
1.1.1.3 ! root 1512: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 1513: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1514: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1515: (clobber (match_scratch:SI 3 "=q,X"))]
1516: ""
1517: "@
1518: srea %0,%1,%2
1519: srai %0,%1,%h2")
1520:
1521: (define_insn ""
1522: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1523: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1524: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1525: (const_int 0)))
1526: (clobber (match_scratch:SI 3 "=r,r"))
1527: (clobber (match_scratch:SI 4 "=q,X"))]
1528: ""
1529: "@
1530: srea. %3,%1,%2
1531: srai. %3,%1,%h2"
1532: [(set_attr "type" "delayed_compare")])
1533:
1534: (define_insn ""
1535: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 ! root 1536: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1537: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1538: (const_int 0)))
1.1.1.3 ! root 1539: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1540: (ashiftrt:SI (match_dup 1) (match_dup 2)))
1541: (clobber (match_scratch:SI 4 "=q,X"))]
1542: ""
1543: "@
1544: srea. %0,%1,%2
1545: srai. %0,%1,%h2"
1546: [(set_attr "type" "delayed_compare")])
1547:
1548: (define_expand "extendqisi2"
1549: [(parallel [(set (match_dup 2)
1.1.1.3 ! root 1550: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1.1 root 1551: (const_int 24)))
1552: (clobber (scratch:SI))])
1.1.1.3 ! root 1553: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 1554: (ashiftrt:SI (match_dup 2)
1555: (const_int 24)))
1556: (clobber (scratch:SI))])]
1557: ""
1558: "
1559: { operands[1] = gen_lowpart (SImode, operands[1]);
1560: operands[2] = gen_reg_rtx (SImode); }")
1561:
1562: (define_expand "extendqihi2"
1563: [(parallel [(set (match_dup 2)
1.1.1.3 ! root 1564: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1.1 root 1565: (const_int 24)))
1566: (clobber (scratch:SI))])
1.1.1.3 ! root 1567: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1.1 root 1568: (ashiftrt:SI (match_dup 2)
1569: (const_int 24)))
1570: (clobber (scratch:SI))])]
1571: ""
1572: "
1573: { operands[0] = gen_lowpart (SImode, operands[0]);
1574: operands[1] = gen_lowpart (SImode, operands[1]);
1575: operands[2] = gen_reg_rtx (SImode); }")
1576:
1577: ;; Floating-point insns, excluding normal data motion.
1578: ;;
1579: ;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1580: ;; all fp insns are actually done in double. The only conversions we will
1581: ;; do will be when storing to memory. In that case, we will use the "frsp"
1582: ;; instruction before storing.
1583: ;;
1584: ;; Note that when we store into a single-precision memory location, we need to
1585: ;; use the frsp insn first. If the register being stored isn't dead, we
1586: ;; need a scratch register for the frsp. But this is difficult when the store
1587: ;; is done by reload. It is not incorrect to do the frsp on the register in
1588: ;; this case, we just lose precision that we would have otherwise gotten but
1589: ;; is not guaranteed. Perhaps this should be tightened up at some point.
1590:
1591: (define_insn "extendsfdf2"
1.1.1.3 ! root 1592: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1593: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1594: ""
1595: "*
1596: {
1597: if (REGNO (operands[0]) == REGNO (operands[1]))
1598: return \"\";
1599: else
1600: return \"fmr %0,%1\";
1601: }"
1602: [(set_attr "type" "fp")])
1603:
1604: (define_insn "truncdfsf2"
1.1.1.3 ! root 1605: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1606: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1607: ""
1608: "*
1609: {
1610: if (REGNO (operands[0]) == REGNO (operands[1]))
1611: return \"\";
1612: else
1613: return \"fmr %0,%1\";
1614: }"
1615: [(set_attr "type" "fp")])
1616:
1617: (define_insn "negsf2"
1.1.1.3 ! root 1618: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1619: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1620: ""
1621: "fneg %0,%1"
1622: [(set_attr "type" "fp")])
1623:
1624: (define_insn "abssf2"
1.1.1.3 ! root 1625: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1626: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1627: ""
1628: "fabs %0,%1"
1629: [(set_attr "type" "fp")])
1630:
1631: (define_insn ""
1.1.1.3 ! root 1632: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1633: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
1.1 root 1634: ""
1635: "fnabs %0,%1"
1636: [(set_attr "type" "fp")])
1637:
1638: (define_insn "addsf3"
1.1.1.3 ! root 1639: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1640: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1641: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1642: ""
1643: "fa %0,%1,%2"
1644: [(set_attr "type" "fp")])
1645:
1646: (define_insn "subsf3"
1.1.1.3 ! root 1647: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1648: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
! 1649: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1650: ""
1651: "fs %0,%1,%2"
1652: [(set_attr "type" "fp")])
1653:
1654: (define_insn "mulsf3"
1.1.1.3 ! root 1655: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1656: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1657: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1658: ""
1659: "fm %0,%1,%2"
1660: [(set_attr "type" "fp")])
1661:
1662: (define_insn "divsf3"
1.1.1.3 ! root 1663: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1664: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
! 1665: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1666: ""
1667: "fd %0,%1,%2"
1668: [(set_attr "type" "fp")])
1669:
1670: (define_insn ""
1.1.1.3 ! root 1671: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1672: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1673: (match_operand:SF 2 "gpc_reg_operand" "f"))
! 1674: (match_operand:SF 3 "gpc_reg_operand" "f")))]
1.1 root 1675: ""
1676: "fma %0,%1,%2,%3"
1677: [(set_attr "type" "fp")])
1678:
1679: (define_insn ""
1.1.1.3 ! root 1680: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1681: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1682: (match_operand:SF 2 "gpc_reg_operand" "f"))
! 1683: (match_operand:SF 3 "gpc_reg_operand" "f")))]
1.1 root 1684: ""
1685: "fms %0,%1,%2,%3"
1686: [(set_attr "type" "fp")])
1687:
1688: (define_insn ""
1.1.1.3 ! root 1689: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1690: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1691: (match_operand:SF 2 "gpc_reg_operand" "f"))
! 1692: (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1.1 root 1693: ""
1694: "fnma %0,%1,%2,%3"
1695: [(set_attr "type" "fp")])
1696:
1697: (define_insn ""
1.1.1.3 ! root 1698: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! 1699: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
! 1700: (match_operand:SF 2 "gpc_reg_operand" "f"))
! 1701: (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1.1 root 1702: ""
1703: "fnms %0,%1,%2,%3"
1704: [(set_attr "type" "fp")])
1705:
1706: (define_insn "negdf2"
1.1.1.3 ! root 1707: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1708: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1709: ""
1710: "fneg %0,%1"
1711: [(set_attr "type" "fp")])
1712:
1713: (define_insn "absdf2"
1.1.1.3 ! root 1714: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1715: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1716: ""
1717: "fabs %0,%1"
1718: [(set_attr "type" "fp")])
1719:
1720: (define_insn ""
1.1.1.3 ! root 1721: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1722: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
1.1 root 1723: ""
1724: "fnabs %0,%1"
1725: [(set_attr "type" "fp")])
1726:
1727: (define_insn "adddf3"
1.1.1.3 ! root 1728: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1729: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1730: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1731: ""
1732: "fa %0,%1,%2"
1733: [(set_attr "type" "fp")])
1734:
1735: (define_insn "subdf3"
1.1.1.3 ! root 1736: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1737: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
! 1738: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1739: ""
1740: "fs %0,%1,%2"
1741: [(set_attr "type" "fp")])
1742:
1743: (define_insn "muldf3"
1.1.1.3 ! root 1744: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1745: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1746: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1747: ""
1748: "fm %0,%1,%2"
1749: [(set_attr "type" "fp")])
1750:
1751: (define_insn "divdf3"
1.1.1.3 ! root 1752: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1753: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
! 1754: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1755: ""
1756: "fd %0,%1,%2"
1757: [(set_attr "type" "fp")])
1758:
1759: (define_insn ""
1.1.1.3 ! root 1760: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1761: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1762: (match_operand:DF 2 "gpc_reg_operand" "f"))
! 1763: (match_operand:DF 3 "gpc_reg_operand" "f")))]
1.1 root 1764: ""
1765: "fma %0,%1,%2,%3"
1766: [(set_attr "type" "fp")])
1767:
1768: (define_insn ""
1.1.1.3 ! root 1769: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1770: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1771: (match_operand:DF 2 "gpc_reg_operand" "f"))
! 1772: (match_operand:DF 3 "gpc_reg_operand" "f")))]
1.1 root 1773: ""
1774: "fms %0,%1,%2,%3"
1775: [(set_attr "type" "fp")])
1776:
1777: (define_insn ""
1.1.1.3 ! root 1778: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1779: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1780: (match_operand:DF 2 "gpc_reg_operand" "f"))
! 1781: (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1.1 root 1782: ""
1783: "fnma %0,%1,%2,%3"
1784: [(set_attr "type" "fp")])
1785:
1786: (define_insn ""
1.1.1.3 ! root 1787: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! 1788: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
! 1789: (match_operand:DF 2 "gpc_reg_operand" "f"))
! 1790: (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1.1 root 1791: ""
1792: "fnms %0,%1,%2,%3"
1793: [(set_attr "type" "fp")])
1794:
1795: ;; Conversions to and from floating-point.
1796: (define_expand "floatsidf2"
1797: [(set (match_dup 2)
1798: (plus:DI (zero_extend:DI
1.1.1.3 ! root 1799: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 1800: (match_dup 3)))
1801: (match_dup 4)))
1.1.1.3 ! root 1802: (set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 1803: (minus:DF (subreg:DF (match_dup 2) 0)
1804: (match_dup 5)))]
1805: ""
1806: "
1807: {
1808: #if HOST_BITS_PER_INT != BITS_PER_WORD
1809: /* Maybe someone can figure out how to do this in that case. I don't
1810: want to right now. */
1811: abort ();
1812: #endif
1813:
1814: operands[2] = gen_reg_rtx (DImode);
1815: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1816: operands[4] = immed_double_const (0, 0x43300000, DImode);
1817: operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1818: 0x80000000, DFmode));
1819: }")
1820:
1821: (define_expand "floatunssidf2"
1822: [(set (match_dup 2)
1.1.1.3 ! root 1823: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1.1 root 1824: (match_dup 3)))
1.1.1.3 ! root 1825: (set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 1826: (minus:DF (subreg:DF (match_dup 2) 0)
1827: (match_dup 4)))]
1828: ""
1829: "
1830: {
1831: #if HOST_BITS_PER_INT != BITS_PER_WORD
1832: /* Maybe someone can figure out how to do this in that case. I don't
1833: want to right now. */
1834: abort ();
1835: #endif
1836:
1837: operands[2] = gen_reg_rtx (DImode);
1838: operands[3] = immed_double_const (0, 0x43300000, DImode);
1839: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1840: }")
1841:
1842: ;; For the above two cases, we always split.
1843: (define_split
1.1.1.3 ! root 1844: [(set (match_operand:DI 0 "gpc_reg_operand" "")
1.1 root 1845: (plus:DI (zero_extend:DI
1.1.1.3 ! root 1846: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 1847: (match_operand:SI 2 "logical_operand" "")))
1848: (match_operand:DI 3 "immediate_operand" "")))]
1849: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1850: && GET_CODE (operands[3]) == CONST_DOUBLE
1851: && CONST_DOUBLE_LOW (operands[3]) == 0"
1852: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1853: (set (match_dup 4) (match_dup 5))]
1854: "
1855: { operands[4] = operand_subword (operands[0], 0, 0, DImode);
1856: operands[5] = operand_subword (operands[3], 0, 0, DImode);
1857: operands[6] = operand_subword (operands[0], 1, 0, DImode);
1858: }")
1859:
1860: (define_insn ""
1.1.1.3 ! root 1861: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1.1 root 1862: (plus:DI (zero_extend:DI
1.1.1.3 ! root 1863: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1.1 root 1864: (match_operand:SI 2 "logical_operand" "rKJ")))
1865: (match_operand:DI 3 "immediate_operand" "n")))]
1866: "HOST_BITS_PER_INT == BITS_PER_WORD
1867: && GET_CODE (operands[3]) == CONST_DOUBLE
1868: && CONST_DOUBLE_LOW (operands[3]) == 0"
1869: "#")
1870:
1871: (define_split
1.1.1.3 ! root 1872: [(set (match_operand:DI 0 "gpc_reg_operand" "=")
! 1873: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1.1 root 1874: (match_operand:DI 2 "immediate_operand" "")))]
1875: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1876: && GET_CODE (operands[2]) == CONST_DOUBLE
1877: && CONST_DOUBLE_LOW (operands[2]) == 0"
1878: [(set (match_dup 3) (match_dup 4))
1879: (set (match_dup 5) (match_dup 1))]
1880: "
1881: { operands[3] = operand_subword (operands[0], 0, 0, DImode);
1882: operands[4] = operand_subword (operands[2], 0, 0, DImode);
1883: operands[5] = operand_subword (operands[0], 1, 0, DImode);
1884:
1885: if (rtx_equal_p (operands[1], operands[5]))
1886: {
1887: emit_move_insn (operands[3], operands[4]);
1888: DONE;
1889: }
1890: }")
1891:
1892: (define_insn ""
1.1.1.3 ! root 1893: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! 1894: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 1895: (match_operand:DI 2 "immediate_operand" "n")))]
1896: "HOST_BITS_PER_INT == BITS_PER_WORD
1897: && GET_CODE (operands[2]) == CONST_DOUBLE
1898: && CONST_DOUBLE_LOW (operands[2]) == 0"
1899: "#")
1900:
1901: (define_expand "fix_truncdfsi2"
1.1.1.3 ! root 1902: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 1903: (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 1904: ""
1905: "
1906: {
1907: emit_insn (gen_trunc_call (operands[0], operands[1],
1908: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1909: DONE;
1910: }")
1911:
1912: (define_expand "fixuns_truncdfsi2"
1.1.1.3 ! root 1913: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 1914: (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 1915: ""
1916: "
1917: {
1918: emit_insn (gen_trunc_call (operands[0], operands[1],
1919: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1920: DONE;
1921: }")
1922:
1923:
1924: (define_expand "trunc_call"
1925: [(parallel [(set (match_operand:SI 0 "" "")
1926: (fix:DF (match_operand:DF 1 "" "")))
1927: (use (match_operand:SI 2 "" ""))])]
1928: ""
1929: "
1930: {
1931: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1932: rtx first = XVECEXP (insns, 0, 0);
1933: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1934:
1935: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1936: REG_NOTES (first));
1937: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1938:
1939: emit_insn (insns);
1940: DONE;
1941: }")
1942:
1943: (define_expand "trunc_call_rtl"
1.1.1.3 ! root 1944: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
1.1 root 1945: (use (reg:DF 33))
1946: (parallel [(set (reg:SI 3)
1947: (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1948: (clobber (scratch:SI))])
1.1.1.3 ! root 1949: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 1950: (reg:SI 3))]
1951: ""
1952: "
1953: {
1954: rs6000_trunc_used = 1;
1955: }")
1956:
1957: ;; Define the DImode operations that can be done in a small number
1958: ;; of instructions.
1959: (define_insn "adddi3"
1.1.1.3 ! root 1960: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! 1961: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
! 1962: (match_operand:DI 2 "gpc_reg_operand" "r")))]
1.1 root 1963: ""
1964: "a %L0,%L1,%L2\;ae %0,%1,%2")
1965:
1966: (define_insn "subdi3"
1.1.1.3 ! root 1967: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! 1968: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! 1969: (match_operand:DI 2 "gpc_reg_operand" "r")))]
1.1 root 1970: ""
1971: "sf %L0,%L2,%L1\;sfe %0,%2,%1")
1972:
1973: (define_insn "negdi3"
1.1.1.3 ! root 1974: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! 1975: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
1.1 root 1976: ""
1977: "sfi %L0,%L1,0\;sfze %0,%1")
1978:
1979: (define_insn "mulsidi3"
1.1.1.3 ! root 1980: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! 1981: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
! 1982: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1.1 root 1983: (clobber (match_scratch:SI 3 "=q"))]
1984: ""
1985: "mul %0,%1,%2\;mfmq %L0")
1986:
1987: ;; If operands 0 and 2 are in the same register, we have a problem. But
1988: ;; operands 0 and 1 (the usual case) can be in the same register. That's
1989: ;; why we have the strange constraints below.
1990: (define_insn "ashldi3"
1.1.1.3 ! root 1991: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
! 1992: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1.1 root 1993: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1994: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1995: ""
1996: "@
1997: sli %0,%L1,%h2\;cal %L0,0(0)
1998: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1999: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1.1.1.2 root 2000: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
1.1 root 2001:
2002: (define_insn "lshrdi3"
1.1.1.3 ! root 2003: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
! 2004: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1.1 root 2005: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2006: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2007: ""
2008: "@
1.1.1.2 root 2009: cal %0,0(0)\;s%A2i %L0,%1,%h2
1.1.1.3 ! root 2010: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
! 2011: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
! 2012: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2")
1.1 root 2013:
2014: ;; Shift by a variable amount is too complex to be worth open-coding. We
2015: ;; just handle shifts by constants.
2016:
2017: (define_expand "ashrdi3"
1.1.1.3 ! root 2018: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
! 2019: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
1.1 root 2020: (match_operand:SI 2 "general_operand" "")))
2021: (clobber (match_scratch:SI 3 ""))])]
2022: ""
2023: "
2024: { if (GET_CODE (operands[2]) != CONST_INT)
2025: FAIL;
2026: }")
2027:
2028: (define_insn ""
1.1.1.3 ! root 2029: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! 2030: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
1.1 root 2031: (match_operand:SI 2 "const_int_operand" "M,i")))
2032: (clobber (match_scratch:SI 3 "=X,q"))]
2033: ""
2034: "@
2035: srai %0,%1,31\;srai %L0,%1,%h2
1.1.1.3 ! root 2036: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2")
1.1 root 2037:
2038: ;; Now define ways of moving data around.
2039: ;;
2040: ;; For SI, we special-case integers that can't be loaded in one insn. We
2041: ;; do the load 16-bits at a time. We could do this by loading from memory,
2042: ;; and this is even supposed to be faster, but it is simpler not to get
2043: ;; integers in the TOC.
2044: (define_expand "movsi"
2045: [(set (match_operand:SI 0 "general_operand" "")
2046: (match_operand:SI 1 "any_operand" ""))]
2047: ""
2048: "
2049: {
2050: if (GET_CODE (operands[0]) != REG)
2051: operands[1] = force_reg (SImode, operands[1]);
2052:
2053: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2054: operands[1] = force_const_mem (SImode, operands[1]);
2055:
2056: if (GET_CODE (operands[1]) == CONST_INT
2057: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2058: && (INTVAL (operands[1]) & 0xffff) != 0)
2059: {
2060: emit_move_insn (operands[0],
2061: gen_rtx (CONST_INT, VOIDmode,
2062: INTVAL (operands[1]) & 0xffff0000));
2063: emit_insn (gen_iorsi3 (operands[0], operands[0],
2064: gen_rtx (CONST_INT, VOIDmode,
2065: INTVAL (operands[1]) & 0xffff)));
2066: DONE;
2067: }
2068: }")
2069:
2070: (define_insn ""
1.1.1.2 root 2071: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
2072: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
1.1.1.3 ! root 2073: "gpc_reg_operand (operands[0], SImode)
! 2074: || gpc_reg_operand (operands[1], SImode)"
1.1 root 2075: "@
2076: ai %0,%1,0
2077: l%U1%X1 %0,%1
2078: st%U0%X0 %1,%0
2079: cal %0,%1(0)
2080: cau %0,0,%u1
2081: mf%1 %0
1.1.1.2 root 2082: mt%0 %1
1.1 root 2083: mt%0 %1"
1.1.1.2 root 2084: [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
1.1 root 2085:
2086: (define_insn ""
2087: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 ! root 2088: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 2089: (const_int 0)))
1.1.1.3 ! root 2090: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
1.1 root 2091: ""
2092: "ai. %0,%1,0"
2093: [(set_attr "type" "compare")])
2094:
2095: (define_expand "movhi"
2096: [(set (match_operand:HI 0 "general_operand" "")
2097: (match_operand:HI 1 "any_operand" ""))]
2098: ""
2099: "
2100: {
2101: if (GET_CODE (operands[0]) != REG)
2102: operands[1] = force_reg (HImode, operands[1]);
2103:
2104: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2105: operands[1] = force_const_mem (HImode, operands[1]);
2106: }")
2107:
2108: (define_insn ""
2109: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2110: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
1.1.1.3 ! root 2111: "gpc_reg_operand (operands[0], HImode)
! 2112: || gpc_reg_operand (operands[1], HImode)"
1.1 root 2113: "@
2114: oril %0,%1,0
2115: lhz%U1%X1 %0,%1
2116: sth%U0%X0 %1,%0
2117: cal %0,%w1(0)
2118: mf%1 %0
2119: mt%0 %1"
2120: [(set_attr "type" "*,load,*,*,*,*")])
2121:
2122: (define_expand "movqi"
2123: [(set (match_operand:QI 0 "general_operand" "")
2124: (match_operand:QI 1 "any_operand" ""))]
2125: ""
2126: "
2127: {
2128: if (GET_CODE (operands[0]) != REG)
2129: operands[1] = force_reg (QImode, operands[1]);
2130:
2131: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2132: operands[1] = force_const_mem (QImode, operands[1]);
2133: }")
2134:
2135: (define_insn ""
2136: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2137: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
1.1.1.3 ! root 2138: "gpc_reg_operand (operands[0], QImode)
! 2139: || gpc_reg_operand (operands[1], QImode)"
1.1 root 2140: "@
2141: oril %0,%1,0
2142: lbz%U1%X1 %0,%1
2143: stb%U0%X0 %1,%0
2144: cal %0,%1(0)
2145: mf%1 %0
2146: mt%0 %1"
2147: [(set_attr "type" "*,load,*,*,*,*")])
2148:
2149: ;; Here is how to move condition codes around. When we store CC data in
2150: ;; an integer register or memory, we store just the high-order 4 bits.
2151: ;; This lets us not shift in the most common case of CR0.
2152: (define_expand "movcc"
2153: [(set (match_operand:CC 0 "nonimmediate_operand" "")
2154: (match_operand:CC 1 "nonimmediate_operand" ""))]
2155: ""
2156: "")
2157:
2158: (define_insn ""
2159: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2160: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2161: "register_operand (operands[0], CCmode)
2162: || register_operand (operands[1], CCmode)"
2163: "@
2164: mcrf %0,%1
2165: mtcrf 128,%1
2166: rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2167: mfcr %0
2168: mfcr %0\;rlinm %0,%0,%f1,0,3
2169: ai %0,%1,0
2170: l%U1%X1 %0,%1
2171: st%U0%U1 %1,%0"
2172: [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2173:
2174: ;; For floating-point, we normally deal with the floating-point registers.
2175: ;; The sole exception is that parameter passing can produce floating-point
2176: ;; values in fixed-point registers. Unless the value is a simple constant
2177: ;; or already in memory, we deal with this by allocating memory and copying
2178: ;; the value explicitly via that memory location.
2179: (define_expand "movsf"
2180: [(set (match_operand:SF 0 "nonimmediate_operand" "")
2181: (match_operand:SF 1 "any_operand" ""))]
2182: ""
2183: "
2184: {
2185: /* If we are called from reload, we might be getting a SUBREG of a hard
2186: reg. So expand it. */
2187: if (GET_CODE (operands[0]) == SUBREG
2188: && GET_CODE (SUBREG_REG (operands[0])) == REG
2189: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2190: operands[0] = alter_subreg (operands[0]);
2191: if (GET_CODE (operands[1]) == SUBREG
2192: && GET_CODE (SUBREG_REG (operands[1])) == REG
2193: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2194: operands[1] = alter_subreg (operands[1]);
2195:
2196: /* If we are being called from reload, it is possible that operands[1]
2197: is a hard non-fp register. So handle those cases. */
2198: if (reload_in_progress && GET_CODE (operands[1]) == REG
2199: && REGNO (operands[1]) < 32)
2200: {
2201: rtx stack_slot;
2202:
2203: /* Remember that we only see a pseudo here if it didn't get a hard
2204: register, so it is memory. */
2205: if (GET_CODE (operands[0]) == MEM
2206: || (GET_CODE (operands[0]) == REG
2207: && (REGNO (operands[0]) < 32
2208: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2209: || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2210: {
2211: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2212: operand_subword (operands[1], 0, 0, SFmode));
2213: DONE;
2214: }
2215:
2216: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2217: emit_move_insn (stack_slot, operands[1]);
2218: emit_move_insn (operands[0], stack_slot);
2219: DONE;
2220: }
2221:
2222: if (GET_CODE (operands[0]) == MEM)
2223: operands[1] = force_reg (SFmode, operands[1]);
2224:
2225: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2226: {
2227: rtx stack_slot;
2228:
2229: if (GET_CODE (operands[1]) == MEM
2230: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2231: || GET_CODE (operands[1]) == CONST_DOUBLE
2232: #endif
2233: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2234: || (reload_in_progress && GET_CODE (operands[1]) == REG
2235: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2236: {
2237: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2238: operand_subword (operands[1], 0, 0, SFmode));
2239: DONE;
2240: }
2241:
2242: if (reload_in_progress)
2243: stack_slot = gen_rtx (MEM, SFmode,
2244: plus_constant (stack_pointer_rtx, 4));
2245: else
2246: stack_slot = assign_stack_temp (SFmode, 4, 0);
2247: emit_move_insn (stack_slot, operands[1]);
2248: emit_move_insn (operands[0], stack_slot);
2249: DONE;
2250: }
2251:
2252: if (CONSTANT_P (operands[1]))
2253: {
2254: operands[1] = force_const_mem (SFmode, operands[1]);
2255: if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2256: && ! reload_in_progress)
2257: operands[1] = change_address (operands[1], SFmode,
2258: XEXP (operands[1], 0));
2259: }
2260: }")
2261:
2262: (define_insn ""
1.1.1.3 ! root 2263: [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
1.1 root 2264: (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2265: "REGNO (operands[0]) <= 31"
2266: "@
2267: #
2268: l%U1%X1 %0,%1"
2269: [(set_attr "type" "*,load")])
2270:
2271: (define_split
1.1.1.3 ! root 2272: [(set (match_operand:SF 0 "gpc_reg_operand" "")
1.1 root 2273: (match_operand:SF 1 "easy_fp_constant" ""))]
2274: "reload_completed && REGNO (operands[0]) <= 31"
2275: [(set (match_dup 2) (match_dup 3))]
2276: "
2277: { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2278: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2279:
2280: (define_insn ""
2281: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2282: (match_operand:SF 1 "input_operand" "f,m,f"))]
1.1.1.3 ! root 2283: "gpc_reg_operand (operands[0], SFmode)
! 2284: || gpc_reg_operand (operands[1], SFmode)"
1.1 root 2285: "@
2286: fmr %0,%1
2287: lfs%U1%X1 %0,%1
2288: frsp %1,%1\;stfs%U0%X0 %1,%0"
2289: [(set_attr "type" "fp,load,*")])
2290:
2291: (define_expand "movdf"
2292: [(set (match_operand:DF 0 "nonimmediate_operand" "")
2293: (match_operand:DF 1 "any_operand" ""))]
2294: ""
2295: "
2296: {
2297: /* If we are called from reload, we might be getting a SUBREG of a hard
2298: reg. So expand it. */
2299: if (GET_CODE (operands[0]) == SUBREG
2300: && GET_CODE (SUBREG_REG (operands[0])) == REG
2301: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2302: operands[0] = alter_subreg (operands[0]);
2303: if (GET_CODE (operands[1]) == SUBREG
2304: && GET_CODE (SUBREG_REG (operands[1])) == REG
2305: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2306: operands[1] = alter_subreg (operands[1]);
2307:
2308: /* If we are being called from reload, it is possible that operands[1]
2309: is a hard non-fp register. So handle those cases. */
2310: if (reload_in_progress && GET_CODE (operands[1]) == REG
2311: && REGNO (operands[1]) < 32)
2312: {
2313: rtx stack_slot;
2314:
2315: /* Remember that we only see a pseudo here if it didn't get a hard
2316: register, so it is memory. */
2317: if (GET_CODE (operands[0]) == MEM
2318: || (GET_CODE (operands[0]) == REG
2319: && (REGNO (operands[0]) < 32
2320: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2321: {
2322: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2323: operand_subword (operands[1], 0, 0, DFmode));
2324: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2325: operand_subword (operands[1], 1, 0, DFmode));
2326: DONE;
2327: }
2328:
2329: stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2330: emit_move_insn (stack_slot, operands[1]);
2331: emit_move_insn (operands[0], stack_slot);
2332: DONE;
2333: }
2334:
2335: if (GET_CODE (operands[0]) == MEM)
2336: {
2337: if (GET_CODE (operands[1]) == MEM)
2338: {
2339: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2340: operand_subword (operands[1], 0, 0, DFmode));
2341: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2342: operand_subword (operands[1], 1, 0, DFmode));
2343: DONE;
2344: }
2345:
2346: operands[1] = force_reg (DFmode, operands[1]);
2347: }
2348:
2349: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2350: {
2351: rtx stack_slot;
2352:
2353: if (GET_CODE (operands[1]) == MEM
2354: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2355: || GET_CODE (operands[1]) == CONST_DOUBLE
2356: #endif
2357: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2358: || (reload_in_progress && GET_CODE (operands[1]) == REG
2359: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2360: {
2361: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2362: operand_subword (operands[1], 0, 0, DFmode));
2363: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2364: operand_subword (operands[1], 1, 0, DFmode));
2365: DONE;
2366: }
2367:
2368: if (reload_in_progress)
2369: stack_slot = gen_rtx (MEM, DFmode,
2370: plus_constant (stack_pointer_rtx, 8));
2371: else
2372: stack_slot = assign_stack_temp (DFmode, 8, 0);
2373: emit_move_insn (stack_slot, operands[1]);
2374: emit_move_insn (operands[0], stack_slot);
2375: DONE;
2376: }
2377:
2378: if (CONSTANT_P (operands[1]))
2379: {
2380: operands[1] = force_const_mem (DFmode, operands[1]);
2381: if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2382: && ! reload_in_progress)
2383: operands[1] = change_address (operands[1], DFmode,
2384: XEXP (operands[1], 0));
2385: }
2386: }")
2387:
2388: (define_insn ""
1.1.1.3 ! root 2389: [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r")
1.1 root 2390: (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2391: "REGNO (operands[0]) <= 31"
2392: "@
2393: #
2394: l %0,%1\;l %L0,%L1"
2395: [(set_attr "type" "*,load")])
2396:
2397: (define_split
1.1.1.3 ! root 2398: [(set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 2399: (match_operand:DF 1 "easy_fp_constant" ""))]
2400: "reload_completed && REGNO (operands[0]) <= 31"
2401: [(set (match_dup 2) (match_dup 3))
2402: (set (match_dup 4) (match_dup 5))]
2403: "
2404: { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2405: operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2406: operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2407: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2408:
2409: (define_insn ""
2410: [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2411: (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
1.1.1.3 ! root 2412: "gpc_reg_operand (operands[0], DFmode)
! 2413: || gpc_reg_operand (operands[1], DFmode)"
1.1 root 2414: "@
2415: fmr %0,%1
2416: lfd%U1%X1 %0,%1
2417: stfd%U0%X0 %1,%0"
2418: [(set_attr "type" "fp,load,*")])
2419:
2420: ;; Next come the multi-word integer load and store and the load and store
2421: ;; multiple insns.
2422: (define_expand "movdi"
2423: [(set (match_operand:DI 0 "general_operand" "")
2424: (match_operand:DI 1 "general_operand" ""))]
2425: ""
2426: "
2427: {
2428: if (GET_CODE (operands[0]) == MEM)
2429: operands[1] = force_reg (DImode, operands[1]);
2430:
2431: else if (GET_CODE (operands[1]) == CONST_DOUBLE
2432: || GET_CODE (operands[1]) == CONST_INT)
2433: {
2434: emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2435: operand_subword (operands[1], 0, 0, DImode));
2436: emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2437: operand_subword (operands[1], 1, 0, DImode));
2438: DONE;
2439: }
2440: }")
2441:
2442: (define_insn ""
2443: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2444: (match_operand:DI 1 "input_operand" "r,m,r"))]
1.1.1.3 ! root 2445: "gpc_reg_operand (operands[0], DImode)
! 2446: || gpc_reg_operand (operands[1], DImode)"
1.1 root 2447: "*
2448: {
2449: switch (which_alternative)
2450: {
2451: case 0:
2452: /* We normally copy the low-numbered register first. However, if
2453: the first register operand 0 is the same as the second register of
2454: operand 1, we must copy in the opposite order. */
2455: if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2456: return \"oril %L0,%L1,0\;oril %0,%1,0\";
2457: else
2458: return \"oril %0,%1,0\;oril %L0,%L1,0\";
2459: case 1:
2460: /* If the low-address word is used in the address, we must load it
2461: last. Otherwise, load it first. Note that we cannot have
2462: auto-increment in that case since the address register is known to be
2463: dead. */
2464: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2465: operands [1], 0))
2466: return \"l %L0,%L1\;l %0,%1\";
2467: else
2468: return \"l%U1 %0,%1\;l %L0,%L1\";
2469: case 2:
2470: return \"st%U0 %1,%0\;st %L1,%L0\";
2471: }
2472: }"
2473: [(set_attr "type" "*,load,*")])
2474:
2475: ;; TImode is similar, except that we usually want to compute the address into
2476: ;; a register and use lsi/stsi (the exception is during reload). MQ is also
2477: ;; clobbered in stsi, so we need a SCRATCH for it.
2478: (define_expand "movti"
2479: [(parallel [(set (match_operand:TI 0 "general_operand" "")
2480: (match_operand:TI 1 "general_operand" ""))
2481: (clobber (scratch:SI))])]
2482: ""
2483: "
2484: {
2485: if (GET_CODE (operands[0]) == MEM)
2486: operands[1] = force_reg (TImode, operands[1]);
2487:
2488: if (GET_CODE (operands[0]) == MEM
2489: && GET_CODE (XEXP (operands[0], 0)) != REG
2490: && ! reload_in_progress)
2491: operands[0] = change_address (operands[0], TImode,
2492: copy_addr_to_reg (XEXP (operands[0], 0)));
2493:
2494: if (GET_CODE (operands[1]) == MEM
2495: && GET_CODE (XEXP (operands[1], 0)) != REG
2496: && ! reload_in_progress)
2497: operands[1] = change_address (operands[1], TImode,
2498: copy_addr_to_reg (XEXP (operands[1], 0)));
2499: }")
2500:
2501: ;; We say that MQ is clobbered in the last alternative because the first
2502: ;; alternative would never get used otherwise since it would need a reload
2503: ;; while the 2nd alternative would not. We put memory cases first so they
2504: ;; are preferred. Otherwise, we'd try to reload the output instead of
2505: ;; giving the SCRATCH mq.
2506: (define_insn ""
2507: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2508: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2509: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
1.1.1.3 ! root 2510: "gpc_reg_operand (operands[0], TImode)
! 2511: || gpc_reg_operand (operands[1], TImode)"
1.1 root 2512: "*
2513: {
2514: switch (which_alternative)
2515: {
2516: case 0:
2517: return \"stsi %1,%P0,16\";
2518:
2519: case 1:
2520: return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2521:
2522: case 2:
2523: /* Normally copy registers with lowest numbered register copied first.
2524: But copy in the other order if the first register of the output
2525: is the second, third, or fourth register in the input. */
2526: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2527: && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2528: return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2529: else
2530: return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2531: case 3:
2532: /* If the address is not used in the output, we can use lsi. Otherwise,
2533: fall through to generating four loads. */
2534: if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2535: return \"lsi %0,%P1,16\";
2536: /* ... fall through ... */
2537: case 4:
2538: /* If the address register is the same as the register for the lowest-
2539: addressed word, load it last. Similarly for the next two words.
2540: Otherwise load lowest address to highest. */
2541: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2542: operands[1], 0))
2543: return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2544: else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2545: REGNO (operands[0]) + 2, operands[1], 0))
2546: return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2547: else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2548: REGNO (operands[0]) + 3, operands[1], 0))
2549: return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2550: else
2551: return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2552: }
2553: }"
2554: [(set_attr "type" "*,load,load,*,*")])
2555:
2556: (define_expand "load_multiple"
2557: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2558: (match_operand:SI 1 "" ""))
2559: (use (match_operand:SI 2 "" ""))])]
2560: ""
2561: "
2562: {
2563: int regno;
2564: int count;
2565: rtx from;
2566: int i;
2567:
2568: /* Support only loading a constant number of fixed-point registers from
2569: memory and only bother with this if more than two; the machine
2570: doesn't support more than eight. */
2571: if (GET_CODE (operands[2]) != CONST_INT
2572: || INTVAL (operands[2]) <= 2
2573: || INTVAL (operands[2]) > 8
2574: || GET_CODE (operands[1]) != MEM
2575: || GET_CODE (operands[0]) != REG
2576: || REGNO (operands[0]) >= 32)
2577: FAIL;
2578:
2579: count = INTVAL (operands[2]);
2580: regno = REGNO (operands[0]);
2581:
2582: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2583: from = force_reg (SImode, XEXP (operands[1], 0));
2584:
2585: for (i = 0; i < count; i++)
2586: XVECEXP (operands[3], 0, i)
2587: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2588: gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2589: }")
2590:
2591: (define_insn ""
2592: [(match_parallel 0 "load_multiple_operation"
1.1.1.3 ! root 2593: [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
1.1 root 2594: (match_operand:SI 2 "indirect_operand" "Q"))])]
2595: ""
2596: "*
2597: {
2598: /* We have to handle the case where the pseudo used to contain the address
2599: is assigned to one of the output registers. In that case, do the
2600: lsi, but then load the correct value. This is a bit of a mess, but is
2601: the best we can do. */
2602: static char result[100];
2603: char newload[40];
2604: int i;
2605:
2606: strcpy (result, \"lsi %1,%P2,%N0\");
2607: for (i = 0; i < XVECLEN (operands[0], 0); i++)
2608: if (refers_to_regno_p (REGNO (operands[1]) + i,
2609: REGNO (operands[1]) + i + 1, operands[2], 0))
2610: {
2611: sprintf (newload, \"\;l %d,%d(%d)\",
2612: REGNO (operands[1]) + i,
2613: i * 4, REGNO (XEXP (operands[2], 0)));
2614: strcat (result, newload);
2615: }
2616:
2617: return result;
2618: }"
2619: [(set_attr "type" "load")])
2620:
2621: (define_expand "store_multiple"
2622: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2623: (match_operand:SI 1 "" ""))
2624: (clobber (scratch:SI))
2625: (use (match_operand:SI 2 "" ""))])]
2626: ""
2627: "
2628: {
2629: int regno;
2630: int count;
2631: rtx to;
2632: int i;
2633:
2634: /* Support only storing a constant number of fixed-point registers to
2635: memory and only bother with this if more than two; the machine
2636: doesn't support more than eight. */
2637: if (GET_CODE (operands[2]) != CONST_INT
2638: || INTVAL (operands[2]) <= 2
2639: || INTVAL (operands[2]) > 8
2640: || GET_CODE (operands[0]) != MEM
2641: || GET_CODE (operands[1]) != REG
2642: || REGNO (operands[1]) >= 32)
2643: FAIL;
2644:
2645: count = INTVAL (operands[2]);
2646: regno = REGNO (operands[1]);
2647:
2648: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2649: to = force_reg (SImode, XEXP (operands[0], 0));
2650:
2651: XVECEXP (operands[3], 0, 0)
2652: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2653: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2654: gen_rtx (SCRATCH, SImode));
2655:
2656: for (i = 1; i < count; i++)
2657: XVECEXP (operands[3], 0, i + 1)
2658: = gen_rtx (SET, VOIDmode,
2659: gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2660: gen_rtx (REG, SImode, regno + i));
2661: }")
2662:
2663: (define_insn ""
2664: [(match_parallel 0 "store_multiple_operation"
2665: [(set (match_operand:SI 1 "indirect_operand" "=Q")
1.1.1.3 ! root 2666: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 2667: (clobber (match_scratch:SI 3 "=q"))])]
2668: ""
2669: "stsi %2,%P1,%O0")
2670:
2671: ;; Define insns that do load or store with update. Some of these we can
2672: ;; get by using pre-decrement or pre-increment, but the hardware can also
2673: ;; do cases where the increment is not the size of the object.
2674: ;;
2675: ;; In all these cases, we use operands 0 and 1 for the register being
2676: ;; incremented because those are the operands that local-alloc will
2677: ;; tie and these are the pair most likely to be tieable (and the ones
2678: ;; that will benefit the most).
2679:
2680: (define_insn ""
1.1.1.3 ! root 2681: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
! 2682: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2683: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 ! root 2684: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2685: (plus:SI (match_dup 1) (match_dup 2)))]
2686: ""
2687: "@
2688: lux %3,%1,%2
2689: lu %3,%2(%1)"
2690: [(set_attr "type" "load,load")])
2691:
2692: (define_insn ""
1.1.1.3 ! root 2693: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2694: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 ! root 2695: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
! 2696: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2697: (plus:SI (match_dup 1) (match_dup 2)))]
2698: ""
2699: "@
2700: stux %3,%1,%2
2701: stu %3,%2(%1)")
2702:
2703: (define_insn ""
1.1.1.3 ! root 2704: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
! 2705: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2706: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 ! root 2707: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2708: (plus:SI (match_dup 1) (match_dup 2)))]
2709: ""
2710: "@
2711: lhzux %3,%1,%2
2712: lhzu %3,%2(%1)"
2713: [(set_attr "type" "load,load")])
2714:
2715: (define_insn ""
1.1.1.3 ! root 2716: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2717: (zero_extend:SI
1.1.1.3 ! root 2718: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2719: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 ! root 2720: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2721: (plus:SI (match_dup 1) (match_dup 2)))]
2722: ""
2723: "@
2724: lhzux %3,%1,%2
2725: lhzu %3,%2(%1)"
2726: [(set_attr "type" "load,load")])
2727:
2728: (define_insn ""
1.1.1.3 ! root 2729: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2730: (sign_extend:SI
1.1.1.3 ! root 2731: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2732: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 ! root 2733: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2734: (plus:SI (match_dup 1) (match_dup 2)))]
2735: ""
2736: "@
2737: lhaux %3,%1,%2
2738: lhau %3,%2(%1)"
2739: [(set_attr "type" "load,load")])
2740:
2741: (define_insn ""
1.1.1.3 ! root 2742: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2743: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 ! root 2744: (match_operand:HI 3 "gpc_reg_operand" "r,r"))
! 2745: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2746: (plus:SI (match_dup 1) (match_dup 2)))]
2747: ""
2748: "@
2749: sthux %3,%1,%2
2750: sthu %3,%2(%1)"
2751: [(set_attr "type" "load,load")])
2752:
2753: (define_insn ""
1.1.1.3 ! root 2754: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
! 2755: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2756: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 ! root 2757: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2758: (plus:SI (match_dup 1) (match_dup 2)))]
2759: ""
2760: "@
2761: lbzux %3,%1,%2
2762: lbzu %3,%2(%1)"
2763: [(set_attr "type" "load,load")])
2764:
2765: (define_insn ""
1.1.1.3 ! root 2766: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2767: (zero_extend:SI
1.1.1.3 ! root 2768: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2769: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 ! root 2770: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2771: (plus:SI (match_dup 1) (match_dup 2)))]
2772: ""
2773: "@
2774: lbzux %3,%1,%2
2775: lbzu %3,%2(%1)"
2776: [(set_attr "type" "load,load")])
2777:
2778: (define_insn ""
1.1.1.3 ! root 2779: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2780: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 ! root 2781: (match_operand:QI 3 "gpc_reg_operand" "r,r"))
! 2782: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2783: (plus:SI (match_dup 1) (match_dup 2)))]
2784: ""
2785: "@
2786: stbux %3,%1,%2
2787: stbu %3,%2(%1)")
2788:
2789: (define_insn ""
1.1.1.3 ! root 2790: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
! 2791: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2792: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 ! root 2793: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2794: (plus:SI (match_dup 1) (match_dup 2)))]
2795: ""
2796: "@
2797: lfsux %3,%1,%2
2798: lfsu %3,%2(%1)"
2799: [(set_attr "type" "load,load")])
2800:
2801: (define_insn ""
1.1.1.3 ! root 2802: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2803: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 ! root 2804: (match_operand:SF 3 "gpc_reg_operand" "f,f"))
! 2805: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2806: (plus:SI (match_dup 1) (match_dup 2)))]
2807: ""
2808: "@
2809: frsp %3,%3\;stfsux %3,%1,%2
2810: frsp %3,%3\;stfsu %3,%2(%1)")
2811:
2812: (define_insn ""
1.1.1.3 ! root 2813: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
! 2814: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2815: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 ! root 2816: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2817: (plus:SI (match_dup 1) (match_dup 2)))]
2818: ""
2819: "@
2820: lfdux %3,%1,%2
2821: lfdu %3,%2(%1)"
2822: [(set_attr "type" "load,load")])
2823:
2824: (define_insn ""
1.1.1.3 ! root 2825: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2826: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 ! root 2827: (match_operand:DF 3 "gpc_reg_operand" "f,f"))
! 2828: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2829: (plus:SI (match_dup 1) (match_dup 2)))]
2830: ""
2831: "@
2832: stfdux %3,%1,%2
2833: stfdu %3,%2(%1)")
2834:
2835: ;; Next come insns related to the calling sequence.
2836: ;;
2837: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
1.1.1.3 ! root 2838: ;; We move the back-chain and decrement the stack pointer.
1.1 root 2839:
2840: (define_expand "allocate_stack"
2841: [(set (reg:SI 1)
2842: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
2843: ""
2844: "
2845: { rtx chain = gen_reg_rtx (SImode);
2846: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2847:
2848: emit_move_insn (chain, stack_bot);
2849: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2850: emit_move_insn (stack_bot, chain);
2851: DONE;
2852: }")
1.1.1.3 ! root 2853:
! 2854: ;; These patterns say how to save and restore the stack pointer. We need not
! 2855: ;; save the stack pointer at function level since we are careful to
! 2856: ;; preserve the backchain. At block level, we have to restore the backchain
! 2857: ;; when we restore the stack pointer.
! 2858: ;;
! 2859: ;; For nonlocal gotos, we must save both the stack pointer and its
! 2860: ;; backchain and restore both. Note that in the nonlocal case, the
! 2861: ;; save area is a memory location.
! 2862:
! 2863: (define_expand "save_stack_function"
! 2864: [(use (const_int 0))]
! 2865: ""
! 2866: "")
! 2867:
! 2868: (define_expand "restore_stack_function"
! 2869: [(use (const_int 0))]
! 2870: ""
! 2871: "")
! 2872:
! 2873: (define_expand "restore_stack_block"
! 2874: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
! 2875: (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
! 2876: (set (mem:SI (match_dup 0)) (match_dup 2))]
! 2877: ""
! 2878: "
! 2879: { operands[2] = gen_reg_rtx (SImode); }")
! 2880:
! 2881: (define_expand "save_stack_nonlocal"
! 2882: [(match_operand:DI 0 "memory_operand" "")
! 2883: (match_operand:SI 1 "register_operand" "")]
! 2884: ""
! 2885: "
! 2886: {
! 2887: rtx temp = gen_reg_rtx (SImode);
! 2888:
! 2889: /* Copy the backchain to the first word, sp to the second. */
! 2890: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
! 2891: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
! 2892: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
! 2893: DONE;
! 2894: }")
! 2895:
! 2896: (define_expand "restore_stack_nonlocal"
! 2897: [(match_operand:SI 0 "register_operand" "")
! 2898: (match_operand:DI 1 "memory_operand" "")]
! 2899: ""
! 2900: "
! 2901: {
! 2902: rtx temp = gen_reg_rtx (SImode);
! 2903:
! 2904: /* Restore the backchain from the first word, sp from the second. */
! 2905: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
! 2906: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
! 2907: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
! 2908: DONE;
! 2909: }")
1.1 root 2910:
2911: ;; A function pointer is a pointer to a data area whose first word contains
2912: ;; the actual address of the function, whose second word contains a pointer
2913: ;; to its TOC, and whose third word contains a value to place in the static
2914: ;; chain register (r11). Note that if we load the static chain, our
2915: ;; "trampoline" need not have any executable code.
2916: ;;
2917: ;; operands[0] is an SImode pseudo in which we place the address of the
2918: ;; function.
2919: ;; operands[1] is the address of data area of the function to call
2920:
2921: (define_expand "call_via_ptr"
1.1.1.3 ! root 2922: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 2923: (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
1.1 root 2924: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2925: (reg:SI 2))
2926: (set (reg:SI 2)
2927: (mem:SI (plus:SI (match_dup 1)
2928: (const_int 4))))
2929: (set (reg:SI 11)
2930: (mem:SI (plus:SI (match_dup 1)
2931: (const_int 8))))
2932: (use (reg:SI 2))
2933: (use (reg:SI 11))]
2934: ""
2935: "")
2936:
2937: (define_expand "call"
2938: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2939: (match_operand 1 "" ""))
2940: (clobber (scratch:SI))])]
2941: ""
2942: "
2943: {
2944: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
2945: abort ();
2946:
2947: operands[0] = XEXP (operands[0], 0);
2948: if (GET_CODE (operands[0]) != SYMBOL_REF)
2949: {
2950: rtx temp = gen_reg_rtx (SImode);
2951:
2952: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
2953: operands[0] = temp;
2954: }
2955: }")
2956:
2957: (define_expand "call_value"
2958: [(parallel [(set (match_operand 0 "" "")
2959: (call (mem:SI (match_operand:SI 1 "address_operand" ""))
2960: (match_operand 2 "" "")))
2961: (clobber (scratch:SI))])]
2962: ""
2963: "
2964: {
2965: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
2966: abort ();
2967:
2968: operands[1] = XEXP (operands[1], 0);
2969: if (GET_CODE (operands[1]) != SYMBOL_REF)
2970: {
2971: rtx temp = gen_reg_rtx (SImode);
2972:
2973: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
2974: operands[1] = temp;
2975: }
2976: }")
2977:
2978: (define_insn ""
2979: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
2980: (match_operand 1 "" "fg,fg"))
1.1.1.3 ! root 2981: (clobber (match_scratch:SI 2 "=l,l"))]
1.1 root 2982: ""
2983: "@
2984: brl\;l 2,20(1)
2985: bl %z0\;cror 15,15,15")
2986:
2987: (define_insn ""
2988: [(set (match_operand 0 "" "fg,fg")
2989: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
2990: (match_operand 2 "" "fg,fg")))
2991: (clobber (match_scratch:SI 3 "=l,l"))]
2992: ""
2993: "@
2994: brl\;l 2,20(1)
2995: bl %z1\;cror 15,15,15")
2996:
2997: ;; Compare insns are next. Note that the RS/6000 has two types of compares,
2998: ;; signed & unsigned, and one type of branch.
2999: ;;
3000: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3001: ;; insns, and branches. We store the operands of compares until we see
3002: ;; how it is used.
3003: (define_expand "cmpsi"
3004: [(set (cc0)
1.1.1.3 ! root 3005: (compare (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3006: (match_operand:SI 1 "reg_or_short_operand" "")))]
3007: ""
3008: "
3009: {
3010: /* Take care of the possibility that operands[1] might be negative but
3011: this might be a logical operation. That insn doesn't exist. */
3012: if (GET_CODE (operands[1]) == CONST_INT
3013: && INTVAL (operands[1]) < 0)
3014: operands[1] = force_reg (SImode, operands[1]);
3015:
3016: rs6000_compare_op0 = operands[0];
3017: rs6000_compare_op1 = operands[1];
3018: rs6000_compare_fp_p = 0;
3019: DONE;
3020: }")
3021:
3022: (define_expand "cmpsf"
1.1.1.3 ! root 3023: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
! 3024: (match_operand:SF 1 "gpc_reg_operand" "")))]
1.1 root 3025: ""
3026: "
3027: {
3028: rs6000_compare_op0 = operands[0];
3029: rs6000_compare_op1 = operands[1];
3030: rs6000_compare_fp_p = 1;
3031: DONE;
3032: }")
3033:
3034: (define_expand "cmpdf"
1.1.1.3 ! root 3035: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
! 3036: (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 3037: ""
3038: "
3039: {
3040: rs6000_compare_op0 = operands[0];
3041: rs6000_compare_op1 = operands[1];
3042: rs6000_compare_fp_p = 1;
3043: DONE;
3044: }")
3045:
3046: (define_expand "beq"
3047: [(set (match_dup 2) (match_dup 1))
3048: (set (pc)
3049: (if_then_else (eq (match_dup 2)
3050: (const_int 0))
3051: (label_ref (match_operand 0 "" ""))
3052: (pc)))]
3053: ""
3054: "
3055: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3056: operands[1] = gen_rtx (COMPARE, mode,
3057: rs6000_compare_op0, rs6000_compare_op1);
3058: operands[2] = gen_reg_rtx (mode);
3059: }")
3060:
3061: (define_expand "bne"
3062: [(set (match_dup 2) (match_dup 1))
3063: (set (pc)
3064: (if_then_else (ne (match_dup 2)
3065: (const_int 0))
3066: (label_ref (match_operand 0 "" ""))
3067: (pc)))]
3068: ""
3069: "
3070: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3071: operands[1] = gen_rtx (COMPARE, mode,
3072: rs6000_compare_op0, rs6000_compare_op1);
3073: operands[2] = gen_reg_rtx (mode);
3074: }")
3075:
3076: (define_expand "blt"
3077: [(set (match_dup 2) (match_dup 1))
3078: (set (pc)
3079: (if_then_else (lt (match_dup 2)
3080: (const_int 0))
3081: (label_ref (match_operand 0 "" ""))
3082: (pc)))]
3083: ""
3084: "
3085: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3086: operands[1] = gen_rtx (COMPARE, mode,
3087: rs6000_compare_op0, rs6000_compare_op1);
3088: operands[2] = gen_reg_rtx (mode);
3089: }")
3090:
3091: (define_expand "bgt"
3092: [(set (match_dup 2) (match_dup 1))
3093: (set (pc)
3094: (if_then_else (gt (match_dup 2)
3095: (const_int 0))
3096: (label_ref (match_operand 0 "" ""))
3097: (pc)))]
3098: ""
3099: "
3100: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3101: operands[1] = gen_rtx (COMPARE, mode,
3102: rs6000_compare_op0, rs6000_compare_op1);
3103: operands[2] = gen_reg_rtx (mode);
3104: }")
3105:
3106: (define_expand "ble"
3107: [(set (match_dup 2) (match_dup 1))
3108: (set (pc)
3109: (if_then_else (le (match_dup 2)
3110: (const_int 0))
3111: (label_ref (match_operand 0 "" ""))
3112: (pc)))]
3113: ""
3114: "
3115: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3116: operands[1] = gen_rtx (COMPARE, mode,
3117: rs6000_compare_op0, rs6000_compare_op1);
3118: operands[2] = gen_reg_rtx (mode);
3119: }")
3120:
3121: (define_expand "bge"
3122: [(set (match_dup 2) (match_dup 1))
3123: (set (pc)
3124: (if_then_else (ge (match_dup 2)
3125: (const_int 0))
3126: (label_ref (match_operand 0 "" ""))
3127: (pc)))]
3128: ""
3129: "
3130: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3131: operands[1] = gen_rtx (COMPARE, mode,
3132: rs6000_compare_op0, rs6000_compare_op1);
3133: operands[2] = gen_reg_rtx (mode);
3134: }")
3135:
3136: (define_expand "bgtu"
3137: [(set (match_dup 2) (match_dup 1))
3138: (set (pc)
3139: (if_then_else (gtu (match_dup 2)
3140: (const_int 0))
3141: (label_ref (match_operand 0 "" ""))
3142: (pc)))]
3143: ""
3144: "
3145: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3146: rs6000_compare_op0, rs6000_compare_op1);
3147: operands[2] = gen_reg_rtx (CCUNSmode);
3148: }")
3149:
3150: (define_expand "bltu"
3151: [(set (match_dup 2) (match_dup 1))
3152: (set (pc)
3153: (if_then_else (ltu (match_dup 2)
3154: (const_int 0))
3155: (label_ref (match_operand 0 "" ""))
3156: (pc)))]
3157: ""
3158: "
3159: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3160: rs6000_compare_op0, rs6000_compare_op1);
3161: operands[2] = gen_reg_rtx (CCUNSmode);
3162: }")
3163:
3164: (define_expand "bgeu"
3165: [(set (match_dup 2) (match_dup 1))
3166: (set (pc)
3167: (if_then_else (geu (match_dup 2)
3168: (const_int 0))
3169: (label_ref (match_operand 0 "" ""))
3170: (pc)))]
3171: ""
3172: "
3173: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3174: rs6000_compare_op0, rs6000_compare_op1);
3175: operands[2] = gen_reg_rtx (CCUNSmode);
3176: }")
3177:
3178: (define_expand "bleu"
3179: [(set (match_dup 2) (match_dup 1))
3180: (set (pc)
3181: (if_then_else (leu (match_dup 2)
3182: (const_int 0))
3183: (label_ref (match_operand 0 "" ""))
3184: (pc)))]
3185: ""
3186: "
3187: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3188: rs6000_compare_op0, rs6000_compare_op1);
3189: operands[2] = gen_reg_rtx (CCUNSmode);
3190: }")
3191:
3192: ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3193: ;; For SEQ, likewise, except that comparisons with zero should be done
3194: ;; with an scc insns. However, due to the order that combine see the
3195: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3196: ;; the cases we don't want to handle.
3197: (define_expand "seq"
3198: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3199: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3200: (eq:SI (match_dup 2) (const_int 0)))]
3201: ""
3202: "
3203: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3204: operands[1] = gen_rtx (COMPARE, mode,
3205: rs6000_compare_op0, rs6000_compare_op1);
3206: operands[2] = gen_reg_rtx (mode);
3207: }")
3208:
3209: (define_expand "sne"
3210: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3211: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3212: (ne:SI (match_dup 2) (const_int 0)))]
3213: ""
3214: "
3215: { if (! rs6000_compare_fp_p)
3216: FAIL;
3217:
3218: operands[1] = gen_rtx (COMPARE, CCFPmode,
3219: rs6000_compare_op0, rs6000_compare_op1);
3220: operands[2] = gen_reg_rtx (CCFPmode);
3221: }")
3222:
3223: ;; A > 0 is best done using the portable sequence, so fail in that case.
3224: (define_expand "sgt"
3225: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3226: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3227: (gt:SI (match_dup 2) (const_int 0)))]
3228: ""
3229: "
3230: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3231:
3232: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3233: FAIL;
3234:
3235: operands[1] = gen_rtx (COMPARE, mode,
3236: rs6000_compare_op0, rs6000_compare_op1);
3237: operands[2] = gen_reg_rtx (mode);
3238: }")
3239:
3240: ;; A < 0 is best done in the portable way for A an integer.
3241: (define_expand "slt"
3242: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3243: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3244: (lt:SI (match_dup 2) (const_int 0)))]
3245: ""
3246: "
3247: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3248:
3249: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3250: FAIL;
3251:
3252: operands[1] = gen_rtx (COMPARE, mode,
3253: rs6000_compare_op0, rs6000_compare_op1);
3254: operands[2] = gen_reg_rtx (mode);
3255: }")
3256:
3257: (define_expand "sge"
3258: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3259: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3260: (ge:SI (match_dup 2) (const_int 0)))]
3261: ""
3262: "
3263: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3264: operands[1] = gen_rtx (COMPARE, mode,
3265: rs6000_compare_op0, rs6000_compare_op1);
3266: operands[2] = gen_reg_rtx (mode);
3267: }")
3268:
3269: ;; A <= 0 is best done the portable way for A an integer.
3270: (define_expand "sle"
3271: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3272: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3273: (le:SI (match_dup 2) (const_int 0)))]
3274: ""
3275: "
3276: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3277:
3278: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3279: FAIL;
3280:
3281: operands[1] = gen_rtx (COMPARE, mode,
3282: rs6000_compare_op0, rs6000_compare_op1);
3283: operands[2] = gen_reg_rtx (mode);
3284: }")
3285:
3286: (define_expand "sgtu"
3287: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3288: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3289: (gtu:SI (match_dup 2) (const_int 0)))]
3290: ""
3291: "
3292: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3293: rs6000_compare_op0, rs6000_compare_op1);
3294: operands[2] = gen_reg_rtx (CCUNSmode);
3295: }")
3296:
3297: (define_expand "sltu"
3298: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3299: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3300: (ltu:SI (match_dup 2) (const_int 0)))]
3301: ""
3302: "
3303: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3304: rs6000_compare_op0, rs6000_compare_op1);
3305: operands[2] = gen_reg_rtx (CCUNSmode);
3306: }")
3307:
3308: (define_expand "sgeu"
3309: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3310: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3311: (geu:SI (match_dup 2) (const_int 0)))]
3312: ""
3313: "
3314: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3315: rs6000_compare_op0, rs6000_compare_op1);
3316: operands[2] = gen_reg_rtx (CCUNSmode);
3317: }")
3318:
3319: (define_expand "sleu"
3320: [(set (match_dup 2) (match_dup 1))
1.1.1.3 ! root 3321: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3322: (leu:SI (match_dup 2) (const_int 0)))]
3323: ""
3324: "
3325: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3326: rs6000_compare_op0, rs6000_compare_op1);
3327: operands[2] = gen_reg_rtx (CCUNSmode);
3328: }")
3329:
3330: ;; Here are the actual compare insns.
3331: (define_insn ""
3332: [(set (match_operand:CC 0 "cc_reg_operand" "=y")
1.1.1.3 ! root 3333: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3334: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3335: ""
3336: "cmp%I2 %0,%1,%2"
3337: [(set_attr "type" "compare")])
3338:
1.1.1.3 ! root 3339: ;; If we are comparing a register for equality with a large constant,
! 3340: ;; we can do this with an XOR followed by a compare. But we need a scratch
! 3341: ;; register for the result of the XOR.
! 3342:
! 3343: (define_split
! 3344: [(set (match_operand:CC 0 "cc_reg_operand" "")
! 3345: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
! 3346: (match_operand:SI 2 "non_short_cint_operand" "")))
! 3347: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
! 3348: "find_single_use (operands[0], insn, 0)
! 3349: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
! 3350: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
! 3351: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
! 3352: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
! 3353: "
! 3354: {
! 3355: /* Get the constant we are comparing against, C, and see what it looks like
! 3356: sign-extended to 16 bits. Then see what constant could be XOR'ed
! 3357: with C to get the sign-extended value. */
! 3358:
! 3359: int c = INTVAL (operands[2]);
! 3360: int sextc = (c << 16) >> 16;
! 3361: int xorv = c ^ sextc;
! 3362:
! 3363: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
! 3364: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
! 3365: }")
! 3366:
1.1 root 3367: (define_insn ""
3368: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
1.1.1.3 ! root 3369: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3370: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3371: ""
3372: "cmpl%I2 %0,%1,%W2"
3373: [(set_attr "type" "compare")])
3374:
3375: ;; The following two insns don't exist as single insns, but if we provide
3376: ;; them, we can swap an add and compare, which will enable us to overlap more
3377: ;; of the required delay between a compare and branch. We generate code for
3378: ;; them by splitting.
3379:
3380: (define_insn ""
3381: [(set (match_operand:CC 3 "cc_reg_operand" "=y")
1.1.1.3 ! root 3382: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3383: (match_operand:SI 2 "short_cint_operand" "i")))
1.1.1.3 ! root 3384: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3385: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3386: ""
3387: "#")
3388:
3389: (define_insn ""
3390: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
1.1.1.3 ! root 3391: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3392: (match_operand:SI 2 "u_short_cint_operand" "i")))
1.1.1.3 ! root 3393: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3394: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3395: ""
3396: "#")
3397:
3398: (define_split
3399: [(set (match_operand:CC 3 "cc_reg_operand" "")
1.1.1.3 ! root 3400: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 3401: (match_operand:SI 2 "short_cint_operand" "")))
1.1.1.3 ! root 3402: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3403: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3404: ""
3405: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3406: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3407:
3408: (define_split
3409: [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
1.1.1.3 ! root 3410: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 3411: (match_operand:SI 2 "u_short_cint_operand" "")))
1.1.1.3 ! root 3412: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3413: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3414: ""
3415: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3416: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3417:
3418: (define_insn ""
3419: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
1.1.1.3 ! root 3420: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
! 3421: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 3422: ""
3423: "fcmpu %0,%1,%2"
3424: [(set_attr "type" "fpcompare")])
3425:
3426: (define_insn ""
3427: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
1.1.1.3 ! root 3428: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
! 3429: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 3430: ""
3431: "fcmpu %0,%1,%2"
3432: [(set_attr "type" "fpcompare")])
3433:
3434: ;; Now we have the scc insns. We can do some combinations because of the
3435: ;; way the machine works.
3436: ;;
3437: ;; Note that this is probably faster if we can put an insn between the
1.1.1.3 ! root 3438: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
! 3439: ;; cases the insns below which don't use an intermediate CR field will
! 3440: ;; be used instead.
1.1 root 3441: (define_insn ""
1.1.1.3 ! root 3442: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3443: (match_operator:SI 1 "scc_comparison_operator"
3444: [(match_operand 2 "cc_reg_operand" "y")
3445: (const_int 0)]))]
3446: ""
3447: "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3448:
3449: (define_insn ""
3450: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3451: (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3452: [(match_operand 2 "cc_reg_operand" "y")
3453: (const_int 0)])
3454: (const_int 0)))
1.1.1.3 ! root 3455: (set (match_operand:SI 3 "gpc_reg_operand" "=r")
1.1 root 3456: (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3457: ""
3458: "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3459: [(set_attr "type" "delayed_compare")])
3460:
3461: (define_insn ""
1.1.1.3 ! root 3462: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3463: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3464: [(match_operand 2 "cc_reg_operand" "y")
3465: (const_int 0)])
3466: (match_operand:SI 3 "const_int_operand" "n")))]
3467: ""
3468: "*
3469: {
3470: int is_bit = ccr_bit (operands[1], 1);
3471: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3472: int count;
3473:
3474: if (is_bit >= put_bit)
3475: count = is_bit - put_bit;
3476: else
3477: count = 32 - (put_bit - is_bit);
3478:
3479: operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3480: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3481:
3482: return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3483: }")
3484:
3485: (define_insn ""
3486: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3487: (compare:CC
3488: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3489: [(match_operand 2 "cc_reg_operand" "y")
3490: (const_int 0)])
3491: (match_operand:SI 3 "const_int_operand" "n"))
3492: (const_int 0)))
1.1.1.3 ! root 3493: (set (match_operand:SI 4 "gpc_reg_operand" "=r")
1.1 root 3494: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3495: (match_dup 3)))]
3496: ""
3497: "*
3498: {
3499: int is_bit = ccr_bit (operands[1], 1);
3500: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3501: int count;
3502:
3503: if (is_bit >= put_bit)
3504: count = is_bit - put_bit;
3505: else
3506: count = 32 - (put_bit - is_bit);
3507:
3508: operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3509: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3510:
3511: return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3512: }"
3513: [(set_attr "type" "delayed_compare")])
3514:
1.1.1.3 ! root 3515: ;; If we are comparing the result of two comparisons, this can be done
! 3516: ;; using creqv or crxor.
! 3517:
! 3518: (define_insn ""
! 3519: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
! 3520: (compare:CCEQ (match_operator 1 "scc_comparison_operator"
! 3521: [(match_operand 2 "cc_reg_operand" "y")
! 3522: (const_int 0)])
! 3523: (match_operator 3 "scc_comparison_operator"
! 3524: [(match_operand 4 "cc_reg_operand" "y")
! 3525: (const_int 0)])))]
! 3526: "REGNO (operands[2]) != REGNO (operands[4])"
! 3527: "*
! 3528: {
! 3529: enum rtx_code code1, code2;
! 3530:
! 3531: code1 = GET_CODE (operands[1]);
! 3532: code2 = GET_CODE (operands[3]);
! 3533:
! 3534: if ((code1 == EQ || code1 == LT || code1 == GT
! 3535: || code1 == LTU || code1 == GTU
! 3536: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
! 3537: !=
! 3538: (code2 == EQ || code2 == LT || code2 == GT
! 3539: || code2 == LTU || code2 == GTU
! 3540: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
! 3541: return \"%C1%C3crxor %E0,%j1,%j3\";
! 3542: else
! 3543: return \"%C1%C3creqv %E0,%j1,%j3\";
! 3544: }")
! 3545:
! 3546: ;; There is a 3 cycle delay between consecutive mfcr instructions
! 3547: ;; so it is useful to combine 2 scc instructions to use only one mfcr.
! 3548:
! 3549: (define_peephole
! 3550: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3551: (match_operator:SI 1 "scc_comparison_operator"
! 3552: [(match_operand 2 "cc_reg_operand" "y")
! 3553: (const_int 0)]))
! 3554: (set (match_operand:SI 3 "gpc_reg_operand" "=r")
! 3555: (match_operator:SI 4 "scc_comparison_operator"
! 3556: [(match_operand 5 "cc_reg_operand" "y")
! 3557: (const_int 0)]))]
! 3558: "REGNO (operands[2]) != REGNO (operands[5])"
! 3559: "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
! 3560:
1.1 root 3561: ;; There are some scc insns that can be done directly, without a compare.
3562: ;; These are faster because they don't involve the communications between
3563: ;; the FXU and branch units. In fact, we will be replacing all of the
3564: ;; integer scc insns here or in the portable methods in emit_store_flag.
3565: ;;
3566: ;; Also support (neg (scc ..)) since that construct is used to replace
3567: ;; branches, (plus (scc ..) ..) since that construct is common and
3568: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3569: ;; cases where it is no more expensive than (neg (scc ..)).
3570:
3571: ;; Have reload force a constant into a register for the simple insns that
3572: ;; otherwise won't accept constants. We do this because it is faster than
3573: ;; the cmp/mfcr sequence we would otherwise generate.
3574:
3575: (define_insn ""
1.1.1.3 ! root 3576: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
! 3577: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3578: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3579: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3580: ""
3581: "@
3582: xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3583: sfi %3,%1,0\;ae %0,%3,%1
3584: xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3585: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3586: sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3587:
3588: (define_insn ""
3589: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3590: (compare:CC
1.1.1.3 ! root 3591: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3592: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3593: (const_int 0)))
1.1.1.3 ! root 3594: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1.1 root 3595: (eq:SI (match_dup 1) (match_dup 2)))
3596: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3597: ""
3598: "@
3599: xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3600: sfi %3,%1,0\;ae. %0,%3,%1
3601: xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3602: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3603: sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3604: [(set_attr "type" "compare")])
3605:
3606: (define_insn ""
1.1.1.3 ! root 3607: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
! 3608: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3609: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 ! root 3610: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
1.1 root 3611: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3612: ""
3613: "@
3614: xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3615: sfi %4,%1,0\;aze %0,%3
3616: xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3617: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3618: sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3619:
3620: (define_insn ""
3621: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3622: (compare:CC
3623: (plus:SI
1.1.1.3 ! root 3624: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3625: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 ! root 3626: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1.1 root 3627: (const_int 0)))
3628: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3629: ""
3630: "@
3631: xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3632: sfi %4,%1,0\;aze. %0,%3
3633: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3634: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3635: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3636: [(set_attr "type" "compare")])
3637:
3638: (define_insn ""
3639: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3640: (compare:CC
3641: (plus:SI
1.1.1.3 ! root 3642: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3643: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 ! root 3644: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1.1 root 3645: (const_int 0)))
1.1.1.3 ! root 3646: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1.1 root 3647: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3648: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3649: ""
3650: "@
3651: xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3652: sfi %4,%1,0\;aze. %4,%3
3653: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3654: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3655: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3656: [(set_attr "type" "compare")])
3657:
3658: (define_insn ""
1.1.1.3 ! root 3659: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
! 3660: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
1.1 root 3661: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3662: ""
3663: "@
3664: xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3665: ai %0,%1,-1\;sfe %0,%0,%0
3666: xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3667: xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3668: sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3669:
3670: ;; This is what (plus (ne X (const_int 0)) Y) looks like.
3671: (define_insn ""
1.1.1.3 ! root 3672: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3673: (plus:SI (lshiftrt:SI
1.1.1.3 ! root 3674: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3675: (const_int 31))
1.1.1.3 ! root 3676: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 3677: (clobber (match_scratch:SI 3 "=&r"))]
3678: ""
3679: "ai %3,%1,-1\;aze %0,%2")
3680:
3681: (define_insn ""
3682: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3683: (compare:CC
3684: (plus:SI (lshiftrt:SI
1.1.1.3 ! root 3685: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3686: (const_int 31))
1.1.1.3 ! root 3687: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 3688: (const_int 0)))
3689: (clobber (match_scratch:SI 3 "=&r"))]
3690: ""
3691: "ai %3,%1,-1\;aze. %3,%2"
3692: [(set_attr "type" "compare")])
3693:
3694: (define_insn ""
3695: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3696: (compare:CC
3697: (plus:SI (lshiftrt:SI
1.1.1.3 ! root 3698: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3699: (const_int 31))
1.1.1.3 ! root 3700: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 3701: (const_int 0)))
1.1.1.3 ! root 3702: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3703: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3704: (match_dup 2)))
3705: (clobber (match_scratch:SI 3 "=&r"))]
3706: ""
3707: "ai %3,%1,-1\;aze. %0,%2"
3708: [(set_attr "type" "compare")])
3709:
3710: (define_insn ""
1.1.1.3 ! root 3711: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 3712: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3713: (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3714: (clobber (match_scratch:SI 3 "=r,X"))]
3715: ""
3716: "@
3717: doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3718: ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3719:
3720: (define_insn ""
3721: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3722: (compare:CC
1.1.1.3 ! root 3723: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3724: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3725: (const_int 0)))
1.1.1.3 ! root 3726: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 3727: (le:SI (match_dup 1) (match_dup 2)))
3728: (clobber (match_scratch:SI 3 "=r,X"))]
3729: ""
3730: "@
3731: doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3732: ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3733: [(set_attr "type" "delayed_compare,compare")])
3734:
3735: (define_insn ""
1.1.1.3 ! root 3736: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 3737: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3738: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 ! root 3739: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 3740: (clobber (match_scratch:SI 4 "=&r,&r"))]
3741: ""
3742: "@
3743: doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3744: srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3745:
3746: (define_insn ""
3747: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3748: (compare:CC
1.1.1.3 ! root 3749: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3750: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 ! root 3751: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 3752: (const_int 0)))
3753: (clobber (match_scratch:SI 4 "=&r,&r"))]
3754: ""
3755: "@
3756: doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3757: srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3758: [(set_attr "type" "compare")])
3759:
3760: (define_insn ""
3761: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3762: (compare:CC
1.1.1.3 ! root 3763: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3764: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 ! root 3765: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 3766: (const_int 0)))
1.1.1.3 ! root 3767: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 3768: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3769: (clobber (match_scratch:SI 4 "=&r,&r"))]
3770: ""
3771: "@
3772: doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3773: srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3774: [(set_attr "type" "compare")])
3775:
3776: (define_insn ""
1.1.1.3 ! root 3777: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 3778: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3779: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3780: ""
3781: "@
3782: doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3783: ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3784:
3785: (define_insn ""
1.1.1.3 ! root 3786: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3787: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3788: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3789: ""
3790: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3791:
3792: (define_insn ""
3793: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3794: (compare:CC
1.1.1.3 ! root 3795: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3796: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3797: (const_int 0)))
1.1.1.3 ! root 3798: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3799: (leu:SI (match_dup 1) (match_dup 2)))]
3800: ""
3801: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3802: [(set_attr "type" "compare")])
3803:
3804: (define_insn ""
1.1.1.3 ! root 3805: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3806: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3807: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3808: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3809: (clobber (match_scratch:SI 4 "=&r"))]
3810: ""
3811: "sf%I2 %4,%1,%2\;aze %0,%3")
3812:
3813: (define_insn ""
3814: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3815: (compare:CC
1.1.1.3 ! root 3816: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3817: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3818: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3819: (const_int 0)))
3820: (clobber (match_scratch:SI 4 "=&r"))]
3821: ""
3822: "sf%I2 %4,%1,%2\;aze. %4,%3"
3823: [(set_attr "type" "compare")])
3824:
3825: (define_insn ""
3826: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3827: (compare:CC
1.1.1.3 ! root 3828: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3829: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3830: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3831: (const_int 0)))
1.1.1.3 ! root 3832: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3833: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3834: (clobber (match_scratch:SI 4 "=&r"))]
3835: ""
3836: "sf%I2 %4,%1,%2\;aze. %0,%3"
3837: [(set_attr "type" "compare")])
3838:
3839: (define_insn ""
1.1.1.3 ! root 3840: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3841: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3842: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3843: ""
3844: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3845:
3846: (define_insn ""
1.1.1.3 ! root 3847: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3848: (and:SI (neg:SI
1.1.1.3 ! root 3849: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3850: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 ! root 3851: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3852: (clobber (match_scratch:SI 4 "=&r"))]
3853: ""
3854: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3855:
3856: (define_insn ""
3857: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3858: (compare:CC
3859: (and:SI (neg:SI
1.1.1.3 ! root 3860: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3861: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 ! root 3862: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3863: (const_int 0)))
3864: (clobber (match_scratch:SI 4 "=&r"))]
3865: ""
3866: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3867: [(set_attr "type" "compare")])
3868:
3869: (define_insn ""
3870: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3871: (compare:CC
3872: (and:SI (neg:SI
1.1.1.3 ! root 3873: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3874: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 ! root 3875: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3876: (const_int 0)))
1.1.1.3 ! root 3877: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3878: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3879: (clobber (match_scratch:SI 4 "=&r"))]
3880: ""
3881: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3882: [(set_attr "type" "compare")])
3883:
3884: (define_insn ""
1.1.1.3 ! root 3885: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3886: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3887: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3888: ""
3889: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3890:
3891: (define_insn ""
3892: [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3893: (compare:CC
1.1.1.3 ! root 3894: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3895: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3896: (const_int 0)))
1.1.1.3 ! root 3897: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3898: (lt:SI (match_dup 1) (match_dup 2)))]
3899: ""
3900: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3901: [(set_attr "type" "delayed_compare")])
3902:
3903: (define_insn ""
1.1.1.3 ! root 3904: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3905: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3906: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3907: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3908: (clobber (match_scratch:SI 4 "=&r"))]
3909: ""
3910: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3911:
3912: (define_insn ""
3913: [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3914: (compare:CC
1.1.1.3 ! root 3915: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3916: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3917: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3918: (const_int 0)))
3919: (clobber (match_scratch:SI 4 "=&r"))]
3920: ""
3921: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3922: [(set_attr "type" "compare")])
3923:
3924: (define_insn ""
3925: [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3926: (compare:CC
1.1.1.3 ! root 3927: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3928: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 3929: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3930: (const_int 0)))
1.1.1.3 ! root 3931: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3932: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3933: (clobber (match_scratch:SI 4 "=&r"))]
3934: ""
3935: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3936: [(set_attr "type" "compare")])
3937:
3938: (define_insn ""
1.1.1.3 ! root 3939: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 3940: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3941: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3942: ""
3943: "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3944:
3945: (define_insn ""
1.1.1.3 ! root 3946: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 3947: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3948: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3949: ""
3950: "@
3951: sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
3952: ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
3953:
3954: (define_insn ""
3955: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3956: (compare:CC
1.1.1.3 ! root 3957: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3958: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3959: (const_int 0)))
1.1.1.3 ! root 3960: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 3961: (ltu:SI (match_dup 1) (match_dup 2)))]
3962: ""
3963: "@
3964: sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
3965: ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
3966: [(set_attr "type" "compare")])
3967:
3968: (define_insn ""
1.1.1.3 ! root 3969: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
! 3970: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 3971: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3972: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
3973: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3974: ""
3975: "@
3976: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3977: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3978: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3979: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
3980:
3981: (define_insn ""
3982: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
3983: (compare:CC
1.1.1.3 ! root 3984: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 3985: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3986: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3987: (const_int 0)))
3988: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3989: ""
3990: "@
3991: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3992: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3993: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3994: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
3995: [(set_attr "type" "compare")])
3996:
3997: (define_insn ""
3998: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
3999: (compare:CC
1.1.1.3 ! root 4000: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 4001: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4002: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
4003: (const_int 0)))
1.1.1.3 ! root 4004: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1.1 root 4005: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4006: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4007: ""
4008: "@
4009: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4010: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4011: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4012: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4013: [(set_attr "type" "compare")])
4014:
4015: (define_insn ""
1.1.1.3 ! root 4016: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 4017: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4018: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
4019: ""
4020: "@
4021: sf %0,%2,%1\;sfe %0,%0,%0
4022: ai %0,%1,%n2\;sfe %0,%0,%0")
4023:
4024: (define_insn ""
1.1.1.3 ! root 4025: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4026: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4027: (match_operand:SI 2 "reg_or_short_operand" "rI")))
4028: (clobber (match_scratch:SI 3 "=r"))]
4029: ""
4030: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
4031:
4032: (define_insn ""
4033: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4034: (compare:CC
1.1.1.3 ! root 4035: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4036: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4037: (const_int 0)))
1.1.1.3 ! root 4038: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4039: (ge:SI (match_dup 1) (match_dup 2)))
4040: (clobber (match_scratch:SI 3 "=r"))]
4041: ""
4042: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
4043: [(set_attr "type" "compare")])
4044:
4045: (define_insn ""
1.1.1.3 ! root 4046: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4047: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4048: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 4049: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 4050: (clobber (match_scratch:SI 4 "=&r"))]
4051: ""
4052: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
4053:
4054: (define_insn ""
4055: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4056: (compare:CC
1.1.1.3 ! root 4057: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4058: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 4059: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4060: (const_int 0)))
4061: (clobber (match_scratch:SI 4 "=&r"))]
4062: ""
4063: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
4064: [(set_attr "type" "compare")])
4065:
4066: (define_insn ""
4067: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4068: (compare:CC
1.1.1.3 ! root 4069: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4070: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 ! root 4071: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4072: (const_int 0)))
1.1.1.3 ! root 4073: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4074: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4075: (clobber (match_scratch:SI 4 "=&r"))]
4076: ""
4077: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
4078: [(set_attr "type" "compare")])
4079:
4080: (define_insn ""
1.1.1.3 ! root 4081: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4082: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4083: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4084: ""
4085: "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
4086:
4087: ;; This is (and (neg (ge X (const_int 0))) Y).
4088: (define_insn ""
1.1.1.3 ! root 4089: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4090: (and:SI (neg:SI
4091: (lshiftrt:SI
1.1.1.3 ! root 4092: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4093: (const_int 31)))
1.1.1.3 ! root 4094: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 4095: (clobber (match_scratch:SI 3 "=&r"))]
4096: ""
4097: "srai %3,%1,31\;andc %0,%2,%3")
4098:
4099: (define_insn ""
4100: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4101: (compare:CC
4102: (and:SI (neg:SI
4103: (lshiftrt:SI
1.1.1.3 ! root 4104: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4105: (const_int 31)))
1.1.1.3 ! root 4106: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4107: (const_int 0)))
4108: (clobber (match_scratch:SI 3 "=&r"))]
4109: ""
4110: "srai %3,%1,31\;andc. %3,%2,%3"
4111: [(set_attr "type" "compare")])
4112:
4113: (define_insn ""
4114: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4115: (compare:CC
4116: (and:SI (neg:SI
4117: (lshiftrt:SI
1.1.1.3 ! root 4118: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4119: (const_int 31)))
1.1.1.3 ! root 4120: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4121: (const_int 0)))
1.1.1.3 ! root 4122: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4123: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
4124: (const_int 31)))
4125: (match_dup 2)))
4126: (clobber (match_scratch:SI 3 "=&r"))]
4127: ""
4128: "srai %3,%1,31\;andc. %0,%2,%3"
4129: [(set_attr "type" "compare")])
4130:
4131: (define_insn ""
1.1.1.3 ! root 4132: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 4133: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4134: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4135: ""
4136: "@
4137: sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
4138: ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
4139:
4140: (define_insn ""
4141: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4142: (compare:CC
1.1.1.3 ! root 4143: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4144: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4145: (const_int 0)))
1.1.1.3 ! root 4146: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4147: (geu:SI (match_dup 1) (match_dup 2)))]
4148: ""
4149: "@
4150: sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
4151: ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
4152: [(set_attr "type" "compare")])
4153:
4154: (define_insn ""
1.1.1.3 ! root 4155: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 4156: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4157: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 ! root 4158: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 4159: (clobber (match_scratch:SI 4 "=&r,&r"))]
4160: ""
4161: "@
4162: sf %4,%2,%1\;aze %0,%3
4163: ai %4,%1,%n2\;aze %0,%3")
4164:
4165: (define_insn ""
4166: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4167: (compare:CC
1.1.1.3 ! root 4168: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4169: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 ! root 4170: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4171: (const_int 0)))
4172: (clobber (match_scratch:SI 4 "=&r,&r"))]
4173: ""
4174: "@
4175: sf %4,%2,%1\;aze. %4,%3
4176: ai %4,%1,%n2\;aze. %4,%3"
4177: [(set_attr "type" "compare")])
4178:
4179: (define_insn ""
4180: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4181: (compare:CC
1.1.1.3 ! root 4182: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4183: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 ! root 4184: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4185: (const_int 0)))
1.1.1.3 ! root 4186: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4187: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4188: (clobber (match_scratch:SI 4 "=&r,&r"))]
4189: ""
4190: "@
4191: sf %4,%2,%1\;aze. %0,%3
4192: ai %4,%1,%n2\;aze. %4,%3"
4193: [(set_attr "type" "compare")])
4194:
4195: (define_insn ""
1.1.1.3 ! root 4196: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 4197: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4198: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4199: ""
4200: "@
4201: sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4202: sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4203:
4204: (define_insn ""
1.1.1.3 ! root 4205: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4206: (and:SI (neg:SI
1.1.1.3 ! root 4207: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4208: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 ! root 4209: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 4210: (clobber (match_scratch:SI 4 "=&r,&r"))]
4211: ""
4212: "@
4213: sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4214: ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4215:
4216: (define_insn ""
4217: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4218: (compare:CC
4219: (and:SI (neg:SI
1.1.1.3 ! root 4220: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4221: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 ! root 4222: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4223: (const_int 0)))
4224: (clobber (match_scratch:SI 4 "=&r,&r"))]
4225: ""
4226: "@
4227: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4228: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4229: [(set_attr "type" "compare")])
4230:
4231: (define_insn ""
4232: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4233: (compare:CC
4234: (and:SI (neg:SI
1.1.1.3 ! root 4235: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4236: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 ! root 4237: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4238: (const_int 0)))
1.1.1.3 ! root 4239: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4240: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4241: (clobber (match_scratch:SI 4 "=&r,&r"))]
4242: ""
4243: "@
4244: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4245: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4246: [(set_attr "type" "compare")])
4247:
4248: (define_insn ""
1.1.1.3 ! root 4249: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4250: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4251: (const_int 0)))]
4252: ""
4253: "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4254:
4255: (define_insn ""
4256: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4257: (compare:CC
1.1.1.3 ! root 4258: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4259: (const_int 0))
4260: (const_int 0)))
1.1.1.3 ! root 4261: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4262: (gt:SI (match_dup 1) (const_int 0)))]
4263: ""
4264: "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4265: [(set_attr "type" "delayed_compare")])
4266:
4267: (define_insn ""
1.1.1.3 ! root 4268: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4269: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4270: (match_operand:SI 2 "reg_or_short_operand" "r")))]
4271: ""
4272: "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4273:
4274: (define_insn ""
4275: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4276: (compare:CC
1.1.1.3 ! root 4277: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4278: (match_operand:SI 2 "reg_or_short_operand" "r"))
4279: (const_int 0)))
1.1.1.3 ! root 4280: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4281: (gt:SI (match_dup 1) (match_dup 2)))]
4282: ""
4283: "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4284: [(set_attr "type" "delayed_compare")])
4285:
4286: (define_insn ""
1.1.1.3 ! root 4287: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4288: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4289: (const_int 0))
1.1.1.3 ! root 4290: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 4291: (clobber (match_scratch:SI 3 "=&r"))]
4292: ""
4293: "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4294:
4295: (define_insn ""
4296: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4297: (compare:CC
1.1.1.3 ! root 4298: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4299: (const_int 0))
1.1.1.3 ! root 4300: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4301: (const_int 0)))
4302: (clobber (match_scratch:SI 3 "=&r"))]
4303: ""
4304: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4305: [(set_attr "type" "compare")])
4306:
4307: (define_insn ""
4308: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4309: (compare:CC
1.1.1.3 ! root 4310: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4311: (const_int 0))
1.1.1.3 ! root 4312: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4313: (const_int 0)))
1.1.1.3 ! root 4314: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4315: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4316: (clobber (match_scratch:SI 3 "=&r"))]
4317: ""
4318: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4319: [(set_attr "type" "compare")])
4320:
4321: (define_insn ""
1.1.1.3 ! root 4322: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4323: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4324: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 ! root 4325: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 4326: (clobber (match_scratch:SI 4 "=&r"))]
4327: ""
4328: "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4329:
4330: (define_insn ""
4331: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4332: (compare:CC
1.1.1.3 ! root 4333: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4334: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 ! root 4335: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4336: (const_int 0)))
4337: (clobber (match_scratch:SI 4 "=&r"))]
4338: ""
4339: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4340: [(set_attr "type" "compare")])
4341:
4342: (define_insn ""
4343: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4344: (compare:CC
1.1.1.3 ! root 4345: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4346: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 ! root 4347: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4348: (const_int 0)))
1.1.1.3 ! root 4349: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4350: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4351: (clobber (match_scratch:SI 4 "=&r"))]
4352: ""
4353: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4354: [(set_attr "type" "compare")])
4355:
4356: (define_insn ""
1.1.1.3 ! root 4357: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4358: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4359: (const_int 0))))]
4360: ""
4361: "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4362:
4363: (define_insn ""
1.1.1.3 ! root 4364: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4365: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4366: (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4367: ""
4368: "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4369:
4370: (define_insn ""
1.1.1.3 ! root 4371: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4372: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4373: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4374: ""
4375: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4376:
4377: (define_insn ""
4378: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4379: (compare:CC
1.1.1.3 ! root 4380: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4381: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4382: (const_int 0)))
1.1.1.3 ! root 4383: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4384: (gtu:SI (match_dup 1) (match_dup 2)))]
4385: ""
4386: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4387: [(set_attr "type" "compare")])
4388:
4389: (define_insn ""
1.1.1.3 ! root 4390: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! 4391: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4392: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4393: (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4394: (clobber (match_scratch:SI 4 "=&r,&r"))]
4395: ""
4396: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4397:
4398: (define_insn ""
4399: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4400: (compare:CC
1.1.1.3 ! root 4401: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4402: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4403: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4404: (const_int 0)))
4405: (clobber (match_scratch:SI 4 "=&r,&r"))]
4406: ""
4407: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4408: [(set_attr "type" "compare")])
4409:
4410: (define_insn ""
4411: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4412: (compare:CC
1.1.1.3 ! root 4413: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4414: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4415: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4416: (const_int 0)))
1.1.1.3 ! root 4417: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4418: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4419: (clobber (match_scratch:SI 4 "=&r,&r"))]
4420: ""
4421: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4422: [(set_attr "type" "compare")])
4423:
4424: (define_insn ""
1.1.1.3 ! root 4425: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! 4426: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4427: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4428: ""
4429: "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4430:
4431: ;; Define both directions of branch and return. If we need a reload
4432: ;; register, we'd rather use CR0 since it is much easier to copy a
4433: ;; register CC value to there.
4434:
4435: (define_insn ""
4436: [(set (pc)
4437: (if_then_else (match_operator 1 "branch_comparison_operator"
4438: [(match_operand 2
4439: "cc_reg_operand" "x,?y")
4440: (const_int 0)])
4441: (label_ref (match_operand 0 "" ""))
4442: (pc)))]
4443: ""
4444: "%C1bc %t1,%j1,%0")
4445:
4446: (define_insn ""
4447: [(set (pc)
4448: (if_then_else (match_operator 0 "branch_comparison_operator"
4449: [(match_operand 1
4450: "cc_reg_operand" "x,?y")
4451: (const_int 0)])
4452: (return)
4453: (pc)))]
4454: "direct_return ()"
4455: "%C0bcr %t0,%j0")
4456:
4457: (define_insn ""
4458: [(set (pc)
4459: (if_then_else (match_operator 1 "branch_comparison_operator"
4460: [(match_operand 2
4461: "cc_reg_operand" "x,?y")
4462: (const_int 0)])
4463: (pc)
4464: (label_ref (match_operand 0 "" ""))))]
4465: ""
4466: "%C1bc %T1,%j1,%0")
4467:
4468: (define_insn ""
4469: [(set (pc)
4470: (if_then_else (match_operator 0 "branch_comparison_operator"
4471: [(match_operand 1
4472: "cc_reg_operand" "x,?y")
4473: (const_int 0)])
4474: (pc)
4475: (return)))]
4476: "direct_return ()"
4477: "%C0bcr %T0,%j0")
4478:
4479: ;; Unconditional branch and return.
4480:
4481: (define_insn "jump"
4482: [(set (pc)
4483: (label_ref (match_operand 0 "" "")))]
4484: ""
4485: "b %l0")
4486:
4487: (define_insn "return"
4488: [(return)]
4489: "direct_return ()"
4490: "br")
4491:
4492: (define_insn "indirect_jump"
4493: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4494: ""
4495: "@
4496: bctr
4497: br")
4498:
4499: ;; Table jump for switch statements:
4500: (define_expand "tablejump"
4501: [(set (match_dup 3)
4502: (plus:SI (match_operand:SI 0 "" "")
4503: (match_dup 2)))
4504: (parallel [(set (pc) (match_dup 3))
4505: (use (label_ref (match_operand 1 "" "")))])]
4506: ""
4507: "
4508: { operands[0] = force_reg (SImode, operands[0]);
4509: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4510: operands[3] = gen_reg_rtx (SImode);
4511: }")
4512:
4513: (define_insn ""
4514: [(set (pc)
4515: (match_operand:SI 0 "register_operand" "c,r"))
4516: (use (label_ref (match_operand 1 "" "")))]
4517: ""
4518: "@
4519: bctr
4520: br")
4521:
4522: (define_insn "nop"
4523: [(const_int 0)]
4524: ""
4525: "cror 0,0,0")
4526:
4527: ;; Define the subtract-one-and-jump insns.
4528: ;; We need to be able to do this for any operand, including MEM, or we
4529: ;; will cause reload to blow up since we don't allow output reloads on
4530: ;; JUMP_INSNs.
4531: (define_insn ""
4532: [(set (pc)
4533: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4534: (const_int 1))
4535: (label_ref (match_operand 2 "" ""))
4536: (pc)))
4537: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4538: (plus:SI (match_dup 1) (const_int -1)))
4539: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4540: (clobber (match_scratch:SI 4 "=X,X,r"))]
4541: ""
4542: "@
4543: bdn %l2
4544: #
4545: #")
4546:
4547: ;; Similar, but we can use GE since we have a REG_NOTES.
4548: (define_insn ""
4549: [(set (pc)
4550: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4551: (const_int 0))
4552: (label_ref (match_operand 2 "" ""))
4553: (pc)))
4554: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4555: (plus:SI (match_dup 1) (const_int -1)))
4556: (clobber (match_scratch:CC 3 "=X,&x,&X"))
4557: (clobber (match_scratch:SI 4 "=X,X,r"))]
4558: "find_reg_note (insn, REG_NONNEG, 0)"
4559: "@
4560: bdn %l2
4561: #
4562: #")
4563:
4564: (define_insn ""
4565: [(set (pc)
4566: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4567: (const_int 1))
4568: (label_ref (match_operand 2 "" ""))
4569: (pc)))
4570: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4571: (plus:SI (match_dup 1) (const_int -1)))
4572: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4573: (clobber (match_scratch:SI 4 "=X,X,r"))]
4574: ""
4575: "@
4576: bdz %l2
4577: #
4578: #")
4579:
4580: (define_split
4581: [(set (pc)
4582: (if_then_else (match_operator 2 "comparison_operator"
1.1.1.3 ! root 4583: [(match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 4584: (const_int 1)])
4585: (match_operand 5 "" "")
4586: (match_operand 6 "" "")))
1.1.1.3 ! root 4587: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 4588: (plus:SI (match_dup 1) (const_int -1)))
4589: (clobber (match_scratch:CC 3 ""))
4590: (clobber (match_scratch:SI 4 ""))]
4591: "reload_completed"
4592: [(parallel [(set (match_dup 3)
4593: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4594: (const_int 0)))
4595: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4596: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4597: "
4598: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4599: const0_rtx); }")
4600:
4601: (define_split
4602: [(set (pc)
4603: (if_then_else (match_operator 2 "comparison_operator"
1.1.1.3 ! root 4604: [(match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 4605: (const_int 1)])
4606: (match_operand 5 "" "")
4607: (match_operand 6 "" "")))
4608: (set (match_operand:SI 0 "general_operand" "")
4609: (plus:SI (match_dup 1) (const_int -1)))
4610: (clobber (match_scratch:CC 3 ""))
4611: (clobber (match_scratch:SI 4 ""))]
1.1.1.3 ! root 4612: "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
1.1 root 4613: [(parallel [(set (match_dup 3)
4614: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4615: (const_int 0)))
4616: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4617: (set (match_dup 0) (match_dup 4))
4618: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4619: "
4620: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4621: const0_rtx); }")
4622:
4623: ;;- Local variables:
4624: ;;- mode:emacs-lisp
4625: ;;- comment-start: ";;- "
4626: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4627: ;;- eval: (modify-syntax-entry ?[ "(]")
4628: ;;- eval: (modify-syntax-entry ?] ")[")
4629: ;;- eval: (modify-syntax-entry ?{ "(}")
4630: ;;- eval: (modify-syntax-entry ?} "){")
4631: ;;- End:
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