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1.1 root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2: ;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3: ;; Contributed by Richard Kenner ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23: ;; Define an insn type attribute. This is used in function unit delay
24: ;; computations.
1.1.1.2 root 25: (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
1.1 root 26: (const_string "integer"))
27:
28: ;; Memory delivers its result in two cycles.
29: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30:
31: ;; We consider floating-point insns to deliver their result in two cycles
32: ;; to try to intersperse integer and FP operations.
33: (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34:
35: ;; Most integer comparisons are ready in four cycles (a stall of three).
36: (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37:
38: ;; Some integer comparisons aren't ready for five cycles (a stall of four).
39: (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40:
41: ;; Floating-point comparisons take eight cycles.
42: (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
1.1.1.2 root 43:
44: ;; Branches on LR cannot be done until five cycles after LR is set.
45: (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
1.1 root 46:
47: ;; Start with fixed-point load and store insns. Here we put only the more
48: ;; complex forms. Basic data transfer is done later.
49:
50: (define_expand "zero_extendqisi2"
1.1.1.3 root 51: [(set (match_operand:SI 0 "gpc_reg_operand" "")
52: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1.1 root 53: ""
54: "")
55:
56: (define_insn ""
1.1.1.3 root 57: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 58: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
59: ""
60: "@
61: lbz%U1%X1 %0,%1
62: rlinm %0,%1,0,24,31"
63: [(set_attr "type" "load,*")])
64:
65: (define_insn ""
66: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 67: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1.1 root 68: (const_int 0)))
69: (clobber (match_scratch:SI 2 "=r"))]
70: ""
71: "andil. %2,%1,255"
72: [(set_attr "type" "compare")])
73:
74: (define_insn ""
75: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 root 76: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1.1 root 77: (const_int 0)))
1.1.1.3 root 78: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 79: (zero_extend:SI (match_dup 1)))]
80: ""
81: "andil. %0,%1,255"
82: [(set_attr "type" "compare")])
83:
84: (define_expand "zero_extendqihi2"
1.1.1.3 root 85: [(set (match_operand:HI 0 "gpc_reg_operand" "")
86: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1.1 root 87: ""
88: "")
89:
90: (define_insn ""
1.1.1.3 root 91: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1.1 root 92: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
93: ""
94: "@
95: lbz%U1%X1 %0,%1
96: rlinm %0,%1,0,24,31"
97: [(set_attr "type" "load,*")])
98:
99: (define_expand "zero_extendhisi2"
1.1.1.4 ! root 100: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1.1.1.3 root 101: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1.1 root 102: ""
103: "")
104:
105: (define_insn ""
1.1.1.3 root 106: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 107: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
108: ""
109: "@
110: lhz%U1%X1 %0,%1
111: rlinm %0,%1,0,16,31"
112: [(set_attr "type" "load,*")])
113:
114: (define_insn ""
115: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 116: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 117: (const_int 0)))
118: (clobber (match_scratch:SI 2 "=r"))]
119: ""
120: "andil. %2,%1,65535"
121: [(set_attr "type" "compare")])
122:
123: (define_insn ""
124: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 root 125: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 126: (const_int 0)))
1.1.1.3 root 127: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 128: (zero_extend:SI (match_dup 1)))]
129: ""
130: "andil. %0,%1,65535"
131: [(set_attr "type" "compare")])
132:
133: (define_expand "extendhisi2"
1.1.1.3 root 134: [(set (match_operand:SI 0 "gpc_reg_operand" "")
135: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1.1 root 136: ""
137: "")
138:
139: (define_insn ""
1.1.1.3 root 140: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 141: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
142: ""
143: "@
144: lha%U1%X1 %0,%1
145: exts %0,%1"
146: [(set_attr "type" "load,*")])
147:
148: (define_insn ""
149: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 150: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 151: (const_int 0)))
152: (clobber (match_scratch:SI 2 "=r"))]
153: ""
154: "exts. %2,%1"
155: [(set_attr "type" "compare")])
156:
157: (define_insn ""
158: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 root 159: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1.1 root 160: (const_int 0)))
1.1.1.3 root 161: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 162: (sign_extend:SI (match_dup 1)))]
163: ""
164: "exts. %0,%1"
165: [(set_attr "type" "compare")])
166:
167: ;; Fixed-point arithmetic insns.
1.1.1.3 root 168: (define_insn "addsi3"
169: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
170: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
1.1 root 171: (match_operand:SI 2 "add_operand" "rI,J")))]
172: ""
173: "@
174: a%I2 %0,%1,%2
175: cau %0,%1,%u2")
176:
177: (define_insn ""
178: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 179: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 180: (match_operand:SI 2 "reg_or_short_operand" "rI"))
181: (const_int 0)))
182: (clobber (match_scratch:SI 3 "=r"))]
183: ""
184: "a%I2. %3,%1,%2"
185: [(set_attr "type" "compare")])
186:
187: (define_insn ""
188: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 189: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 190: (match_operand:SI 2 "reg_or_short_operand" "rI"))
191: (const_int 0)))
1.1.1.3 root 192: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 193: (plus:SI (match_dup 1) (match_dup 2)))]
194: ""
195: "a%I2. %0,%1,%2"
196: [(set_attr "type" "compare")])
197:
1.1.1.3 root 198: ;; Split an add that we can't do in one insn into two insns, each of which
199: ;; does one 16-bit part. This is used by combine. Note that the low-order
200: ;; add should be last in case the result gets used in an address.
201:
202: (define_split
203: [(set (match_operand:SI 0 "gpc_reg_operand" "")
204: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
205: (match_operand:SI 2 "non_add_cint_operand" "")))]
206: ""
207: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
208: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
209: "
1.1 root 210: {
1.1.1.3 root 211: int low = INTVAL (operands[2]) & 0xffff;
212: int high = (unsigned) INTVAL (operands[2]) >> 16;
1.1 root 213:
1.1.1.3 root 214: if (low & 0x8000)
215: high++, low |= 0xffff0000;
1.1 root 216:
1.1.1.3 root 217: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
218: operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
1.1 root 219: }")
220:
221: (define_insn "one_cmplsi2"
1.1.1.3 root 222: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
223: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 224: ""
225: "sfi %0,%1,-1")
226:
227: (define_insn ""
1.1.1.3 root 228: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 229: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1.1.1.3 root 230: (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1.1 root 231: ""
232: "@
233: sf %0,%2,%1
234: sfi %0,%2,%1")
235:
236: (define_insn ""
237: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 238: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
239: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 240: (const_int 0)))
241: (clobber (match_scratch:SI 3 "=r"))]
242: ""
243: "sf. %3,%2,%1"
244: [(set_attr "type" "compare")])
245:
246: (define_insn ""
247: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 248: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
249: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 250: (const_int 0)))
1.1.1.3 root 251: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 252: (minus:SI (match_dup 1) (match_dup 2)))]
253: ""
254: "sf. %0,%2,%1"
255: [(set_attr "type" "compare")])
256:
257: (define_expand "subsi3"
1.1.1.3 root 258: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 259: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
260: (match_operand:SI 2 "reg_or_cint_operand" "")))]
261: ""
262: "
263: {
264: if (GET_CODE (operands[2]) == CONST_INT)
265: {
266: emit_insn (gen_addsi3 (operands[0], operands[1],
267: negate_rtx (SImode, operands[2])));
268: DONE;
269: }
270: }")
271:
272: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
273: ;; instruction and some auxiliary computations. Then we just have a single
1.1.1.4 ! root 274: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
! 275: ;; combine.
1.1 root 276:
277: (define_expand "sminsi3"
278: [(set (match_dup 3)
1.1.1.3 root 279: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 280: (match_operand:SI 2 "reg_or_short_operand" ""))
281: (const_int 0)
282: (minus:SI (match_dup 2) (match_dup 1))))
1.1.1.3 root 283: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 284: (minus:SI (match_dup 2) (match_dup 3)))]
285: ""
286: "
287: { operands[3] = gen_reg_rtx (SImode); }")
288:
1.1.1.4 ! root 289: (define_split
! 290: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 291: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 292: (match_operand:SI 2 "reg_or_short_operand" "")))
! 293: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
! 294: ""
! 295: [(set (match_dup 3)
! 296: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
! 297: (const_int 0)
! 298: (minus:SI (match_dup 2) (match_dup 1))))
! 299: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
! 300: "")
! 301:
1.1 root 302: (define_expand "smaxsi3"
303: [(set (match_dup 3)
1.1.1.3 root 304: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 305: (match_operand:SI 2 "reg_or_short_operand" ""))
306: (const_int 0)
307: (minus:SI (match_dup 2) (match_dup 1))))
1.1.1.3 root 308: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 309: (plus:SI (match_dup 3) (match_dup 1)))]
310: ""
311: "
312: { operands[3] = gen_reg_rtx (SImode); }")
313:
1.1.1.4 ! root 314: (define_split
! 315: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 316: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 317: (match_operand:SI 2 "reg_or_short_operand" "")))
! 318: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
! 319: ""
! 320: [(set (match_dup 3)
! 321: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
! 322: (const_int 0)
! 323: (minus:SI (match_dup 2) (match_dup 1))))
! 324: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
! 325: "")
! 326:
1.1 root 327: (define_expand "uminsi3"
1.1.1.3 root 328: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 329: (const_int -2147483648)))
1.1.1.3 root 330: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1.1 root 331: (const_int -2147483648)))
332: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
333: (const_int 0)
334: (minus:SI (match_dup 4) (match_dup 3))))
1.1.1.3 root 335: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 336: (minus:SI (match_dup 2) (match_dup 3)))]
337: ""
338: "
339: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
340:
341: (define_expand "umaxsi3"
1.1.1.3 root 342: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 343: (const_int -2147483648)))
1.1.1.3 root 344: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1.1 root 345: (const_int -2147483648)))
346: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
347: (const_int 0)
348: (minus:SI (match_dup 4) (match_dup 3))))
1.1.1.3 root 349: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 350: (plus:SI (match_dup 3) (match_dup 1)))]
351: ""
352: "
353: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
354:
355: (define_insn ""
1.1.1.3 root 356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
357: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 358: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 359: (const_int 0)
360: (minus:SI (match_dup 2) (match_dup 1))))]
361: ""
362: "doz%I2 %0,%1,%2")
363:
364: (define_insn ""
365: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
366: (compare:CC
1.1.1.3 root 367: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 368: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 369: (const_int 0)
370: (minus:SI (match_dup 2) (match_dup 1)))
371: (const_int 0)))
372: (clobber (match_scratch:SI 3 "=r"))]
373: ""
374: "doz%I2. %3,%1,%2"
375: [(set_attr "type" "delayed_compare")])
376:
377: (define_insn ""
378: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
379: (compare:CC
1.1.1.3 root 380: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1.1.1.2 root 381: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 382: (const_int 0)
383: (minus:SI (match_dup 2) (match_dup 1)))
384: (const_int 0)))
1.1.1.3 root 385: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 386: (if_then_else:SI (gt (match_dup 1) (match_dup 2))
387: (const_int 0)
388: (minus:SI (match_dup 2) (match_dup 1))))]
389: ""
390: "doz%I2. %0,%1,%2"
391: [(set_attr "type" "delayed_compare")])
392:
393: ;; We don't need abs with condition code because such comparisons should
394: ;; never be done.
395: (define_insn "abssi2"
1.1.1.3 root 396: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
397: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 398: ""
399: "abs %0,%1")
400:
401: (define_insn ""
1.1.1.3 root 402: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
403: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1.1 root 404: ""
405: "nabs %0,%1")
406:
407: (define_insn "negsi2"
1.1.1.3 root 408: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
409: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1.1 root 410: ""
411: "neg %0,%1")
412:
413: (define_insn ""
414: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 415: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 416: (const_int 0)))
417: (clobber (match_scratch:SI 2 "=r"))]
418: ""
419: "neg. %2,%1"
420: [(set_attr "type" "compare")])
421:
422: (define_insn ""
423: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 root 424: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 425: (const_int 0)))
1.1.1.3 root 426: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 427: (neg:SI (match_dup 1)))]
428: ""
429: "neg. %0,%1"
430: [(set_attr "type" "compare")])
431:
432: (define_insn "ffssi2"
433: [(set (match_operand:SI 0 "register_operand" "=&r")
434: (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
435: ""
436: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
437:
438: ;; There is no need for (set (condition) (compare (ffs) 0)) because that
439: ;; can be simplified to an ordinary comparison. A parallel set and compare
440: ;; might be used, so include it.
441:
442: (define_insn ""
443: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
444: (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
445: (const_int 0)))
446: (set (match_operand:SI 0 "register_operand" "=&r")
447: (ffs:SI (match_dup 1)))]
448: ""
449: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
450: [(set_attr "type" "compare")])
451:
452: (define_insn "mulsi3"
1.1.1.3 root 453: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
454: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1.1 root 455: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
456: (clobber (match_scratch:SI 3 "=q,q"))]
457: ""
458: "@
459: muls %0,%1,%2
460: muli %0,%1,%2")
461:
462: (define_insn ""
463: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 464: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
465: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 466: (const_int 0)))
467: (clobber (match_scratch:SI 3 "=r"))
468: (clobber (match_scratch:SI 4 "=q"))]
469: ""
470: "muls. %3,%1,%2"
471: [(set_attr "type" "delayed_compare")])
472:
473: (define_insn ""
474: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 475: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
476: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 477: (const_int 0)))
1.1.1.3 root 478: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 479: (mult:SI (match_dup 1) (match_dup 2)))
480: (clobber (match_scratch:SI 4 "=q"))]
481: ""
482: "muls. %0,%1,%2"
483: [(set_attr "type" "delayed_compare")])
484:
485: ;; Operand 1 is divided by operand 2; quotient goes to operand
486: ;; 0 and remainder to operand 3.
487: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
488:
489: (define_insn "divmodsi4"
1.1.1.3 root 490: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
491: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
492: (match_operand:SI 2 "gpc_reg_operand" "r")))
493: (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1.1 root 494: (mod:SI (match_dup 1) (match_dup 2)))]
495: ""
496: "divs %0,%1,%2")
497:
498: ;; For powers of two we can do srai/aze for divide and then adjust for
499: ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
500: (define_expand "divsi3"
1.1.1.3 root 501: [(set (match_operand:SI 0 "gpc_reg_operand" "")
502: (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 503: (match_operand:SI 2 "reg_or_cint_operand" "")))]
504: ""
505: "
506: {
507: if (GET_CODE (operands[2]) != CONST_INT
508: || exact_log2 (INTVAL (operands[2])) < 0)
509: FAIL;
510: }")
511:
512: (define_expand "modsi3"
513: [(set (match_dup 3)
1.1.1.3 root 514: (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 515: (match_operand:SI 2 "reg_or_cint_operand" "")))
516: (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
517: (clobber (scratch:SI))])
1.1.1.3 root 518: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 519: (minus:SI (match_dup 1) (match_dup 4)))]
520: ""
521: "
522: {
523: int i = exact_log2 (INTVAL (operands[2]));
524:
525: if (GET_CODE (operands[2]) != CONST_INT || i < 0)
526: FAIL;
527:
528: operands[3] = gen_reg_rtx (SImode);
529: operands[4] = gen_reg_rtx (SImode);
530: operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
531: }")
532:
533: (define_insn ""
1.1.1.3 root 534: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
535: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 536: (match_operand:SI 2 "const_int_operand" "N")))]
537: "exact_log2 (INTVAL (operands[2])) >= 0"
538: "srai %0,%1,%p2\;aze %0,%0")
539:
540: (define_insn ""
541: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 542: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 543: (match_operand:SI 2 "const_int_operand" "N")))
544: (clobber (match_scratch:SI 3 "=r"))]
545: "exact_log2 (INTVAL (operands[2])) >= 0"
546: "srai %3,%1,%p2\;aze. %3,%3"
547: [(set_attr "type" "compare")])
548:
549: (define_insn ""
550: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 551: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 552: (match_operand:SI 2 "const_int_operand" "N")))
1.1.1.3 root 553: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 554: (div:SI (match_dup 1) (match_dup 2)))]
555: "exact_log2 (INTVAL (operands[2])) >= 0"
556: "srai %0,%1,%p2\;aze. %0,%0"
557: [(set_attr "type" "compare")])
558:
559: (define_insn ""
1.1.1.3 root 560: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 561: (udiv:SI
562: (plus:DI (lshift:DI
1.1.1.3 root 563: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 564: (const_int 32))
1.1.1.4 ! root 565: (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1.1.1.3 root 566: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1.1.4 ! root 567: (set (match_operand:SI 2 "register_operand" "=*q")
1.1 root 568: (umod:SI
569: (plus:DI (lshift:DI
570: (zero_extend:DI (match_dup 1)) (const_int 32))
1.1.1.4 ! root 571: (zero_extend:DI (match_dup 4)))
1.1 root 572: (match_dup 3)))]
573:
574: ""
575: "div %0,%1,%3")
576:
577: ;; To do unsigned divide we handle the cases of the divisor looking like a
578: ;; negative number. If it is a constant that is less than 2**31, we don't
579: ;; have to worry about the branches. So make a few subroutines here.
580: ;;
581: ;; First comes the normal case.
582: (define_expand "udivmodsi4_normal"
583: [(set (match_dup 4) (const_int 0))
584: (parallel [(set (match_operand:SI 0 "" "")
585: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
586: (const_int 32))
587: (zero_extend:DI (match_operand:SI 1 "" "")))
588: (match_operand:SI 2 "" "")))
589: (set (match_operand:SI 3 "" "")
590: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
591: (const_int 32))
592: (zero_extend:DI (match_dup 1)))
593: (match_dup 2)))])]
594: ""
595: "
596: { operands[4] = gen_reg_rtx (SImode); }")
597:
598: ;; This handles the branches.
599: (define_expand "udivmodsi4_tests"
600: [(set (match_operand:SI 0 "" "") (const_int 0))
601: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
602: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
603: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
604: (label_ref (match_operand:SI 4 "" "")) (pc)))
605: (set (match_dup 0) (const_int 1))
606: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
607: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
608: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
609: (label_ref (match_dup 4)) (pc)))]
610: ""
611: "
612: { operands[5] = gen_reg_rtx (CCUNSmode);
613: operands[6] = gen_reg_rtx (CCmode);
614: }")
615:
616: (define_expand "udivmodsi4"
1.1.1.3 root 617: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
618: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 619: (match_operand:SI 2 "reg_or_cint_operand" "")))
1.1.1.3 root 620: (set (match_operand:SI 3 "gpc_reg_operand" "")
1.1 root 621: (umod:SI (match_dup 1) (match_dup 2)))])]
622: ""
623: "
624: {
625: rtx label = 0;
626:
627: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
628: {
629: operands[2] = force_reg (SImode, operands[2]);
630: label = gen_label_rtx ();
631: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
632: operands[3], label));
633: }
634: else
635: operands[2] = force_reg (SImode, operands[2]);
636:
637: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
638: operands[3]));
639: if (label)
640: emit_label (label);
641:
642: DONE;
643: }")
644:
645: (define_insn "andsi3"
1.1.1.3 root 646: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
647: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 648: (match_operand:SI 2 "and_operand" "?r,L,K,J")))
649: (clobber (match_scratch:CC 3 "=X,X,x,x"))]
650: ""
651: "@
652: and %0,%1,%2
653: rlinm %0,%1,0,%m2,%M2
654: andil. %0,%1,%b2
655: andiu. %0,%1,%u2")
656:
657: (define_insn ""
658: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1.1.1.3 root 659: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 660: (match_operand:SI 2 "and_operand" "r,K,J,L"))
661: (const_int 0)))
662: (clobber (match_scratch:SI 3 "=r,r,r,r"))]
663: ""
664: "@
665: and. %3,%1,%2
666: andil. %3,%1,%b2
667: andiu. %3,%1,%u2
668: rlinm. %3,%1,0,%m2,%M2"
669: [(set_attr "type" "compare,compare,compare,delayed_compare")])
670:
671: (define_insn ""
672: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1.1.1.3 root 673: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1.1 root 674: (match_operand:SI 2 "and_operand" "r,K,J,L"))
675: (const_int 0)))
1.1.1.3 root 676: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1.1 root 677: (and:SI (match_dup 1) (match_dup 2)))]
678: ""
679: "@
680: and. %0,%1,%2
681: andil. %0,%1,%b2
682: andiu. %0,%1,%u2
683: rlinm. %0,%1,0,%m2,%M2"
684: [(set_attr "type" "compare,compare,compare,delayed_compare")])
685:
1.1.1.3 root 686: ;; Take a AND with a constant that cannot be done in a single insn and try to
687: ;; split it into two insns. This does not verify that the insns are valid
688: ;; since this need not be done as combine will do it.
689:
690: (define_split
691: [(set (match_operand:SI 0 "gpc_reg_operand" "")
692: (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
693: (match_operand:SI 2 "non_and_cint_operand" "")))]
694: ""
695: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
696: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
697: "
698: {
699: int maskval = INTVAL (operands[2]);
700: int i, transitions, last_bit_value;
701: int orig = maskval, first_c = maskval, second_c;
702:
703: /* We know that MASKVAL must have more than 2 bit-transitions. Start at
704: the low-order bit and count for the third transition. When we get there,
705: make a first mask that has everything to the left of that position
706: a one. Then make the second mask to turn off whatever else is needed. */
707:
708: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
709: {
710: if (((maskval >>= 1) & 1) != last_bit_value)
711: last_bit_value ^= 1, transitions++;
712:
713: if (transitions > 2)
714: {
715: first_c |= (~0) << i;
716: break;
717: }
718: }
719:
720: second_c = orig | ~ first_c;
721:
722: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
723: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
724: }")
725:
726: (define_insn "iorsi3"
727: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
728: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1.1 root 729: (match_operand:SI 2 "logical_operand" "r,K,J")))]
730: ""
731: "@
732: or %0,%1,%2
733: oril %0,%1,%b2
734: oriu %0,%1,%u2")
735:
736: (define_insn ""
737: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 738: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
739: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 740: (const_int 0)))
741: (clobber (match_scratch:SI 3 "=r"))]
742: ""
743: "or. %3,%1,%2"
744: [(set_attr "type" "compare")])
745:
746: (define_insn ""
747: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 748: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
749: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 750: (const_int 0)))
1.1.1.3 root 751: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 752: (ior:SI (match_dup 1) (match_dup 2)))]
753: ""
754: "or. %0,%1,%2"
755: [(set_attr "type" "compare")])
756:
1.1.1.3 root 757: ;; Split an IOR that we can't do in one insn into two insns, each of which
758: ;; does one 16-bit part. This is used by combine.
759:
760: (define_split
761: [(set (match_operand:SI 0 "gpc_reg_operand" "")
762: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
763: (match_operand:SI 2 "non_logical_cint_operand" "")))]
764: ""
765: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
766: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
767: "
1.1 root 768: {
1.1.1.3 root 769: operands[3] = gen_rtx (CONST_INT, VOIDmode,
770: INTVAL (operands[2]) & 0xffff0000);
771: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1.1 root 772: }")
773:
1.1.1.3 root 774: (define_insn "xorsi3"
775: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
776: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1.1 root 777: (match_operand:SI 2 "logical_operand" "r,K,J")))]
778: ""
779: "@
780: xor %0,%1,%2
781: xoril %0,%1,%b2
782: xoriu %0,%1,%u2")
783:
784: (define_insn ""
785: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 786: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
787: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 788: (const_int 0)))
789: (clobber (match_scratch:SI 3 "=r"))]
790: ""
791: "xor. %3,%1,%2"
792: [(set_attr "type" "compare")])
793:
794: (define_insn ""
795: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 796: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
797: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 798: (const_int 0)))
1.1.1.3 root 799: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 800: (xor:SI (match_dup 1) (match_dup 2)))]
801: ""
802: "xor. %0,%1,%2"
803: [(set_attr "type" "compare")])
804:
1.1.1.3 root 805: ;; Split an XOR that we can't do in one insn into two insns, each of which
806: ;; does one 16-bit part. This is used by combine.
807:
808: (define_split
809: [(set (match_operand:SI 0 "gpc_reg_operand" "")
810: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
811: (match_operand:SI 2 "non_logical_cint_operand" "")))]
812: ""
813: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
814: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
815: "
1.1 root 816: {
1.1.1.3 root 817: operands[3] = gen_rtx (CONST_INT, VOIDmode,
818: INTVAL (operands[2]) & 0xffff0000);
819: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1.1 root 820: }")
821:
822: (define_insn ""
1.1.1.3 root 823: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
824: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
825: (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 826: ""
827: "eqv %0,%1,%2")
828:
829: (define_insn ""
830: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 831: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
832: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 833: (const_int 0)))
834: (clobber (match_scratch:SI 3 "=r"))]
835: ""
836: "eqv. %3,%1,%2"
837: [(set_attr "type" "compare")])
838:
839: (define_insn ""
840: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 841: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
842: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 843: (const_int 0)))
1.1.1.3 root 844: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 845: (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
846: ""
847: "eqv. %0,%1,%2"
848: [(set_attr "type" "compare")])
849:
850: (define_insn ""
1.1.1.3 root 851: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
852: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
853: (match_operand:SI 2 "gpc_reg_operand" "r")))]
1.1 root 854: ""
855: "andc %0,%2,%1")
856:
857: (define_insn ""
858: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 859: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
860: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 861: (const_int 0)))
862: (clobber (match_scratch:SI 3 "=r"))]
863: ""
864: "andc. %3,%2,%1"
865: [(set_attr "type" "compare")])
866:
867: (define_insn ""
868: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 869: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
870: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 871: (const_int 0)))
1.1.1.3 root 872: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 873: (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
874: ""
875: "andc. %0,%2,%1"
876: [(set_attr "type" "compare")])
877:
878: (define_insn ""
1.1.1.3 root 879: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
880: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
881: (match_operand:SI 2 "gpc_reg_operand" "r")))]
1.1 root 882: ""
883: "orc %0,%2,%1")
884:
885: (define_insn ""
886: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 887: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
888: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 889: (const_int 0)))
890: (clobber (match_scratch:SI 3 "=r"))]
891: ""
892: "orc. %3,%2,%1"
893: [(set_attr "type" "compare")])
894:
895: (define_insn ""
896: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 897: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
898: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 899: (const_int 0)))
1.1.1.3 root 900: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 901: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
902: ""
903: "orc. %0,%2,%1"
904: [(set_attr "type" "compare")])
905:
906: (define_insn ""
1.1.1.3 root 907: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
908: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
909: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 910: ""
911: "nand %0,%1,%2")
912:
913: (define_insn ""
914: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 915: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
916: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 917: (const_int 0)))
918: (clobber (match_scratch:SI 3 "=r"))]
919: ""
920: "nand. %3,%1,%2"
921: [(set_attr "type" "compare")])
922:
923: (define_insn ""
924: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 925: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
926: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 927: (const_int 0)))
1.1.1.3 root 928: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 929: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
930: ""
931: "nand. %0,%1,%2"
932: [(set_attr "type" "compare")])
933:
934: (define_insn ""
1.1.1.3 root 935: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
936: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
937: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1.1 root 938: ""
939: "nor %0,%1,%2")
940:
941: (define_insn ""
942: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 943: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
944: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 945: (const_int 0)))
946: (clobber (match_scratch:SI 3 "=r"))]
947: ""
948: "nor. %3,%1,%2"
949: [(set_attr "type" "compare")])
950:
951: (define_insn ""
952: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 953: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
954: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 955: (const_int 0)))
1.1.1.3 root 956: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 957: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
958: ""
959: "nor. %0,%1,%2"
960: [(set_attr "type" "compare")])
961:
962: ;; maskir insn. We need four forms because things might be in arbitrary
963: ;; orders. Don't define forms that only set CR fields because these
964: ;; would modify an input register.
965:
966: (define_insn ""
1.1.1.3 root 967: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1.1.4 ! root 968: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
! 969: (match_operand:SI 1 "gpc_reg_operand" "0"))
! 970: (and:SI (match_dup 2)
1.1.1.3 root 971: (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1.1 root 972: ""
1.1.1.4 ! root 973: "maskir %0,%3,%2")
1.1 root 974:
975: (define_insn ""
976: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.4 ! root 977: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
! 978: (match_operand:SI 1 "gpc_reg_operand" "0"))
1.1.1.3 root 979: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1.1.4 ! root 980: (match_dup 2))))]
1.1 root 981: ""
1.1.1.4 ! root 982: "maskir %0,%3,%2")
1.1 root 983:
984: (define_insn ""
1.1.1.3 root 985: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1.1.4 ! root 986: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1.1.3 root 987: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1.1.4 ! root 988: (and:SI (not:SI (match_dup 2))
! 989: (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1.1 root 990: ""
1.1.1.4 ! root 991: "maskir %0,%3,%2")
1.1 root 992:
993: (define_insn ""
1.1.1.3 root 994: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
995: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1.1.4 ! root 996: (match_operand:SI 2 "gpc_reg_operand" "r"))
! 997: (and:SI (not:SI (match_dup 2))
! 998: (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1.1 root 999: ""
1.1.1.4 ! root 1000: "maskir %0,%3,%2")
1.1 root 1001:
1002: (define_insn ""
1003: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1004: (compare:CC
1.1.1.4 ! root 1005: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
! 1006: (match_operand:SI 1 "gpc_reg_operand" "0"))
! 1007: (and:SI (match_dup 2)
1.1.1.3 root 1008: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 1009: (const_int 0)))
1.1.1.3 root 1010: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1.1.4 ! root 1011: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
! 1012: (and:SI (match_dup 2) (match_dup 3))))]
1.1 root 1013: ""
1.1.1.4 ! root 1014: "maskir. %0,%3,%2"
1.1 root 1015: [(set_attr "type" "compare")])
1016:
1017: (define_insn ""
1018: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1019: (compare:CC
1.1.1.4 ! root 1020: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
! 1021: (match_operand:SI 1 "gpc_reg_operand" "0"))
1.1.1.3 root 1022: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1.1.4 ! root 1023: (match_dup 2)))
1.1 root 1024: (const_int 0)))
1025: (set (match_operand:SI 0 "register_operand" "=r")
1.1.1.4 ! root 1026: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
! 1027: (and:SI (match_dup 3) (match_dup 2))))]
1.1 root 1028: ""
1.1.1.4 ! root 1029: "maskir. %0,%3,%2"
1.1 root 1030: [(set_attr "type" "compare")])
1031:
1032: (define_insn ""
1033: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1034: (compare:CC
1.1.1.4 ! root 1035: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1.1.3 root 1036: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1.1.4 ! root 1037: (and:SI (not:SI (match_dup 2))
! 1038: (match_operand:SI 1 "gpc_reg_operand" "0")))
1.1 root 1039: (const_int 0)))
1.1.1.3 root 1040: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1.1.4 ! root 1041: (ior:SI (and:SI (match_dup 2) (match_dup 3))
! 1042: (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1.1 root 1043: ""
1.1.1.4 ! root 1044: "maskir. %0,%3,%2"
1.1 root 1045: [(set_attr "type" "compare")])
1046:
1047: (define_insn ""
1048: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1049: (compare:CC
1.1.1.3 root 1050: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1.1.1.4 ! root 1051: (match_operand:SI 2 "gpc_reg_operand" "r"))
! 1052: (and:SI (not:SI (match_dup 2))
! 1053: (match_operand:SI 1 "gpc_reg_operand" "0")))
1.1 root 1054: (const_int 0)))
1.1.1.3 root 1055: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1.1.4 ! root 1056: (ior:SI (and:SI (match_dup 3) (match_dup 2))
! 1057: (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1.1 root 1058: ""
1.1.1.4 ! root 1059: "maskir. %0,%3,%2"
1.1 root 1060: [(set_attr "type" "compare")])
1061:
1062: ;; Rotate and shift insns, in all their variants. These support shifts,
1063: ;; field inserts and extracts, and various combinations thereof.
1064: (define_insn "insv"
1.1.1.3 root 1065: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1066: (match_operand:SI 1 "const_int_operand" "i")
1067: (match_operand:SI 2 "const_int_operand" "i"))
1.1.1.3 root 1068: (match_operand:SI 3 "gpc_reg_operand" "r"))]
1.1 root 1069: ""
1070: "*
1071: {
1072: int start = INTVAL (operands[2]) & 31;
1073: int size = INTVAL (operands[1]) & 31;
1074:
1075: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1076: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1077: return \"rlimi %0,%3,%4,%h2,%h1\";
1078: }")
1079:
1080: (define_insn "extzv"
1.1.1.3 root 1081: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1083: (match_operand:SI 2 "const_int_operand" "i")
1084: (match_operand:SI 3 "const_int_operand" "i")))]
1085: ""
1086: "*
1087: {
1088: int start = INTVAL (operands[3]) & 31;
1089: int size = INTVAL (operands[2]) & 31;
1090:
1091: if (start + size >= 32)
1092: operands[3] = const0_rtx;
1093: else
1094: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1095: return \"rlinm %0,%1,%3,%s2,31\";
1096: }")
1097:
1098: (define_insn ""
1099: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 1100: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1101: (match_operand:SI 2 "const_int_operand" "i")
1102: (match_operand:SI 3 "const_int_operand" "i"))
1103: (const_int 0)))
1104: (clobber (match_scratch:SI 4 "=r"))]
1105: ""
1106: "*
1107: {
1108: int start = INTVAL (operands[3]) & 31;
1109: int size = INTVAL (operands[2]) & 31;
1110:
1.1.1.3 root 1111: /* If the bitfield being tested fits in the upper or lower half of a
1112: word, it is possible to use andiu. or andil. to test it. This is
1113: useful because the condition register set-use delay is smaller for
1114: andi[ul]. than for rlinm. This doesn't work when the starting bit
1115: position is 0 because the LT and GT bits may be set wrong. */
1116:
1117: if ((start > 0 && start + size <= 16) || start >= 16)
1118: {
1119: operands[3] = gen_rtx (CONST_INT, VOIDmode,
1120: ((1 << (16 - (start & 15)))
1121: - (1 << (16 - (start & 15) - size))));
1122: if (start < 16)
1123: return \"andiu. %4,%1,%3\";
1124: else
1125: return \"andil. %4,%1,%3\";
1126: }
1127:
1.1 root 1128: if (start + size >= 32)
1129: operands[3] = const0_rtx;
1130: else
1131: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1132: return \"rlinm. %4,%1,%3,%s2,31\";
1133: }"
1134: [(set_attr "type" "compare")])
1135:
1136: (define_insn ""
1137: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1.1.1.3 root 1138: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1139: (match_operand:SI 2 "const_int_operand" "i")
1140: (match_operand:SI 3 "const_int_operand" "i"))
1141: (const_int 0)))
1.1.1.3 root 1142: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1143: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1144: ""
1145: "*
1146: {
1147: int start = INTVAL (operands[3]) & 31;
1148: int size = INTVAL (operands[2]) & 31;
1149:
1.1.1.3 root 1150: if (start >= 16 && start + size == 32)
1151: {
1152: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
1153: return \"andil. %0,%1,%3\";
1154: }
1155:
1.1 root 1156: if (start + size >= 32)
1157: operands[3] = const0_rtx;
1158: else
1159: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1160: return \"rlinm. %0,%1,%3,%s2,31\";
1161: }"
1162: [(set_attr "type" "delayed_compare")])
1163:
1164: (define_insn "rotlsi3"
1.1.1.3 root 1165: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1167: (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1168: ""
1169: "rl%I2nm %0,%1,%h2,0,31")
1170:
1171: (define_insn ""
1172: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1.1.1.3 root 1173: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1174: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1175: (const_int 0)))
1176: (clobber (match_scratch:SI 3 "=r"))]
1177: ""
1178: "rl%I2nm. %3,%1,%h2,0,31"
1179: [(set_attr "type" "delayed_compare")])
1180:
1181: (define_insn ""
1182: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1.1.1.3 root 1183: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1184: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1185: (const_int 0)))
1.1.1.3 root 1186: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1187: (rotate:SI (match_dup 1) (match_dup 2)))]
1188: ""
1189: "rl%I2nm. %0,%1,%h2,0,31"
1190: [(set_attr "type" "delayed_compare")])
1191:
1192: (define_insn ""
1.1.1.3 root 1193: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1194: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1195: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1196: (match_operand:SI 3 "mask_operand" "L")))]
1197: ""
1198: "rl%I2nm %0,%1,%h2,%m3,%M3")
1199:
1200: (define_insn ""
1201: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1202: (compare:CC (and:SI
1.1.1.3 root 1203: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1204: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1205: (match_operand:SI 3 "mask_operand" "L"))
1206: (const_int 0)))
1207: (clobber (match_scratch:SI 4 "=r"))]
1208: ""
1209: "rl%I2nm. %4,%1,%h2,%m3,%M3"
1210: [(set_attr "type" "delayed_compare")])
1211:
1212: (define_insn ""
1213: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1214: (compare:CC (and:SI
1.1.1.3 root 1215: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1216: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1217: (match_operand:SI 3 "mask_operand" "L"))
1218: (const_int 0)))
1.1.1.3 root 1219: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1220: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1221: ""
1222: "rl%I2nm. %0,%1,%h2,%m3,%M3"
1223: [(set_attr "type" "delayed_compare")])
1224:
1225: (define_insn ""
1.1.1.3 root 1226: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1227: (zero_extend:SI
1228: (subreg:QI
1.1.1.3 root 1229: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1230: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1231: ""
1232: "rl%I2nm %0,%1,%h2,24,31")
1233:
1234: (define_insn ""
1235: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1236: (compare:CC (zero_extend:SI
1237: (subreg:QI
1.1.1.3 root 1238: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1239: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1240: (const_int 0)))
1241: (clobber (match_scratch:SI 3 "=r"))]
1242: ""
1243: "rl%I2nm. %3,%1,%h2,24,31"
1244: [(set_attr "type" "delayed_compare")])
1245:
1246: (define_insn ""
1247: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248: (compare:CC (zero_extend:SI
1249: (subreg:QI
1.1.1.3 root 1250: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1251: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1252: (const_int 0)))
1.1.1.3 root 1253: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1254: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1255: ""
1256: "rl%I2nm. %0,%1,%h2,24,31"
1257: [(set_attr "type" "delayed_compare")])
1258:
1259: (define_insn ""
1.1.1.3 root 1260: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1261: (zero_extend:SI
1262: (subreg:HI
1.1.1.3 root 1263: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1264: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1265: ""
1266: "rl%I2nm %0,%1,%h2,16,31")
1267:
1268: (define_insn ""
1269: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1270: (compare:CC (zero_extend:SI
1271: (subreg:HI
1.1.1.3 root 1272: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1273: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1274: (const_int 0)))
1275: (clobber (match_scratch:SI 3 "=r"))]
1276: ""
1277: "rl%I2nm. %3,%1,%h2,16,31"
1278: [(set_attr "type" "delayed_compare")])
1279:
1280: (define_insn ""
1281: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1282: (compare:CC (zero_extend:SI
1283: (subreg:HI
1.1.1.3 root 1284: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1285: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1286: (const_int 0)))
1.1.1.3 root 1287: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1288: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1289: ""
1290: "rl%I2nm. %0,%1,%h2,16,31"
1291: [(set_attr "type" "delayed_compare")])
1292:
1293: ;; Note that we use "sle." instead of "sl." so that we can set
1294: ;; SHIFT_COUNT_TRUNCATED.
1295:
1296: (define_insn "ashlsi3"
1.1.1.3 root 1297: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1298: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1299: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1300: (clobber (match_scratch:SI 3 "=q,X"))]
1301: ""
1302: "@
1303: sle %0,%1,%2
1304: sli %0,%1,%h2")
1305:
1306: (define_insn ""
1307: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 root 1308: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1309: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1310: (const_int 0)))
1311: (clobber (match_scratch:SI 3 "=r,r"))
1312: (clobber (match_scratch:SI 4 "=q,X"))]
1313: ""
1314: "@
1315: sle. %3,%1,%2
1316: sli. %3,%1,%h2"
1317: [(set_attr "type" "delayed_compare")])
1318:
1319: (define_insn ""
1320: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 root 1321: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1322: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1323: (const_int 0)))
1.1.1.3 root 1324: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1325: (ashift:SI (match_dup 1) (match_dup 2)))
1326: (clobber (match_scratch:SI 4 "=q,X"))]
1327: ""
1328: "@
1329: sle. %0,%1,%2
1330: sli. %0,%1,%h2"
1331: [(set_attr "type" "delayed_compare")])
1332:
1333: (define_insn ""
1.1.1.3 root 1334: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1335: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1336: (match_operand:SI 2 "const_int_operand" "i"))
1337: (match_operand:SI 3 "mask_operand" "L")))]
1338: "includes_lshift_p (operands[2], operands[3])"
1339: "rlinm %0,%h1,%h2,%m3,%M3")
1340:
1341: (define_insn ""
1342: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1343: (compare:CC
1.1.1.3 root 1344: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1345: (match_operand:SI 2 "const_int_operand" "i"))
1346: (match_operand:SI 3 "mask_operand" "L"))
1347: (const_int 0)))
1348: (clobber (match_scratch:SI 4 "=r"))]
1349: "includes_lshift_p (operands[2], operands[3])"
1350: "rlinm. %4,%h1,%h2,%m3,%M3"
1351: [(set_attr "type" "delayed_compare")])
1352:
1353: (define_insn ""
1354: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1355: (compare:CC
1.1.1.3 root 1356: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1357: (match_operand:SI 2 "const_int_operand" "i"))
1358: (match_operand:SI 3 "mask_operand" "L"))
1359: (const_int 0)))
1.1.1.3 root 1360: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1361: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1362: "includes_lshift_p (operands[2], operands[3])"
1363: "rlinm. %0,%h1,%h2,%m3,%M3"
1364: [(set_attr "type" "delayed_compare")])
1365:
1.1.1.2 root 1366: ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
1367: ;; "sli x,x,0".
1.1 root 1368: (define_insn "lshrsi3"
1.1.1.3 root 1369: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1370: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1371: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1372: (clobber (match_scratch:SI 3 "=q,X"))]
1373: ""
1374: "@
1375: sre %0,%1,%2
1.1.1.2 root 1376: s%A2i %0,%1,%h2")
1.1 root 1377:
1378: (define_insn ""
1379: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 root 1380: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1381: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1382: (const_int 0)))
1383: (clobber (match_scratch:SI 3 "=r,r"))
1384: (clobber (match_scratch:SI 4 "=q,X"))]
1385: ""
1386: "@
1387: sre. %3,%1,%2
1.1.1.2 root 1388: s%A2i. %3,%1,%h2"
1.1 root 1389: [(set_attr "type" "delayed_compare")])
1390:
1391: (define_insn ""
1392: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 root 1393: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1394: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1395: (const_int 0)))
1.1.1.3 root 1396: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1397: (lshiftrt:SI (match_dup 1) (match_dup 2)))
1398: (clobber (match_scratch:SI 4 "=q,X"))]
1399: ""
1400: "@
1401: sre. %0,%1,%2
1.1.1.2 root 1402: s%A2i. %0,%1,%h2"
1.1 root 1403: [(set_attr "type" "delayed_compare")])
1404:
1405: (define_insn ""
1.1.1.3 root 1406: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1408: (match_operand:SI 2 "const_int_operand" "i"))
1409: (match_operand:SI 3 "mask_operand" "L")))]
1410: "includes_rshift_p (operands[2], operands[3])"
1411: "rlinm %0,%1,%s2,%m3,%M3")
1412:
1413: (define_insn ""
1414: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1415: (compare:CC
1.1.1.3 root 1416: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1417: (match_operand:SI 2 "const_int_operand" "i"))
1418: (match_operand:SI 3 "mask_operand" "L"))
1419: (const_int 0)))
1420: (clobber (match_scratch:SI 4 "=r"))]
1421: "includes_rshift_p (operands[2], operands[3])"
1422: "rlinm. %4,%1,%s2,%m3,%M3"
1423: [(set_attr "type" "delayed_compare")])
1424:
1425: (define_insn ""
1426: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1427: (compare:CC
1.1.1.3 root 1428: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1429: (match_operand:SI 2 "const_int_operand" "i"))
1430: (match_operand:SI 3 "mask_operand" "L"))
1431: (const_int 0)))
1.1.1.3 root 1432: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1433: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1434: "includes_rshift_p (operands[2], operands[3])"
1435: "rlinm. %0,%1,%s2,%m3,%M3"
1436: [(set_attr "type" "delayed_compare")])
1437:
1438: (define_insn ""
1.1.1.3 root 1439: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1440: (zero_extend:SI
1441: (subreg:QI
1.1.1.3 root 1442: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1443: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1444: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1445: "rlinm %0,%1,%s2,24,31")
1446:
1447: (define_insn ""
1448: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1449: (compare:CC
1450: (zero_extend:SI
1451: (subreg:QI
1.1.1.3 root 1452: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1453: (match_operand:SI 2 "const_int_operand" "i")) 0))
1454: (const_int 0)))
1455: (clobber (match_scratch:SI 3 "=r"))]
1456: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1457: "rlinm. %3,%1,%s2,24,31"
1458: [(set_attr "type" "delayed_compare")])
1459:
1460: (define_insn ""
1461: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1462: (compare:CC
1463: (zero_extend:SI
1464: (subreg:QI
1.1.1.3 root 1465: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1466: (match_operand:SI 2 "const_int_operand" "i")) 0))
1467: (const_int 0)))
1.1.1.3 root 1468: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1469: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1470: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1471: "rlinm. %0,%1,%s2,24,31"
1472: [(set_attr "type" "delayed_compare")])
1473:
1474: (define_insn ""
1.1.1.3 root 1475: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1476: (zero_extend:SI
1477: (subreg:HI
1.1.1.3 root 1478: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1479: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1480: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1481: "rlinm %0,%1,%s2,16,31")
1482:
1483: (define_insn ""
1484: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1485: (compare:CC
1486: (zero_extend:SI
1487: (subreg:HI
1.1.1.3 root 1488: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1489: (match_operand:SI 2 "const_int_operand" "i")) 0))
1490: (const_int 0)))
1491: (clobber (match_scratch:SI 3 "=r"))]
1492: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1493: "rlinm. %3,%1,%s2,16,31"
1494: [(set_attr "type" "delayed_compare")])
1495:
1496: (define_insn ""
1497: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1498: (compare:CC
1499: (zero_extend:SI
1500: (subreg:HI
1.1.1.3 root 1501: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 1502: (match_operand:SI 2 "const_int_operand" "i")) 0))
1503: (const_int 0)))
1.1.1.3 root 1504: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 1505: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1506: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1507: "rlinm. %0,%1,%s2,16,31"
1508: [(set_attr "type" "delayed_compare")])
1509:
1510: (define_insn ""
1.1.1.3 root 1511: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1512: (const_int 1)
1.1.1.3 root 1513: (match_operand:SI 1 "gpc_reg_operand" "r"))
1514: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1515: (const_int 31)))]
1516: ""
1517: "rrib %0,%1,%2")
1518:
1519: (define_insn ""
1.1.1.3 root 1520: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1521: (const_int 1)
1.1.1.3 root 1522: (match_operand:SI 1 "gpc_reg_operand" "r"))
1523: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1524: (const_int 31)))]
1525: ""
1526: "rrib %0,%1,%2")
1527:
1528: (define_insn ""
1.1.1.3 root 1529: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1.1 root 1530: (const_int 1)
1.1.1.3 root 1531: (match_operand:SI 1 "gpc_reg_operand" "r"))
1532: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1.1 root 1533: (const_int 1)
1534: (const_int 0)))]
1535: ""
1536: "rrib %0,%1,%2")
1537:
1538: (define_insn "ashrsi3"
1.1.1.3 root 1539: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1540: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1541: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1542: (clobber (match_scratch:SI 3 "=q,X"))]
1543: ""
1544: "@
1545: srea %0,%1,%2
1546: srai %0,%1,%h2")
1547:
1548: (define_insn ""
1549: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1.1.1.3 root 1550: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1551: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1552: (const_int 0)))
1553: (clobber (match_scratch:SI 3 "=r,r"))
1554: (clobber (match_scratch:SI 4 "=q,X"))]
1555: ""
1556: "@
1557: srea. %3,%1,%2
1558: srai. %3,%1,%h2"
1559: [(set_attr "type" "delayed_compare")])
1560:
1561: (define_insn ""
1562: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1.1.1.3 root 1563: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 1564: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1565: (const_int 0)))
1.1.1.3 root 1566: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 1567: (ashiftrt:SI (match_dup 1) (match_dup 2)))
1568: (clobber (match_scratch:SI 4 "=q,X"))]
1569: ""
1570: "@
1571: srea. %0,%1,%2
1572: srai. %0,%1,%h2"
1573: [(set_attr "type" "delayed_compare")])
1574:
1575: (define_expand "extendqisi2"
1576: [(parallel [(set (match_dup 2)
1.1.1.3 root 1577: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1.1 root 1578: (const_int 24)))
1579: (clobber (scratch:SI))])
1.1.1.3 root 1580: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 1581: (ashiftrt:SI (match_dup 2)
1582: (const_int 24)))
1583: (clobber (scratch:SI))])]
1584: ""
1585: "
1586: { operands[1] = gen_lowpart (SImode, operands[1]);
1587: operands[2] = gen_reg_rtx (SImode); }")
1588:
1589: (define_expand "extendqihi2"
1590: [(parallel [(set (match_dup 2)
1.1.1.3 root 1591: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1.1 root 1592: (const_int 24)))
1593: (clobber (scratch:SI))])
1.1.1.3 root 1594: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1.1 root 1595: (ashiftrt:SI (match_dup 2)
1596: (const_int 24)))
1597: (clobber (scratch:SI))])]
1598: ""
1599: "
1600: { operands[0] = gen_lowpart (SImode, operands[0]);
1601: operands[1] = gen_lowpart (SImode, operands[1]);
1602: operands[2] = gen_reg_rtx (SImode); }")
1603:
1604: ;; Floating-point insns, excluding normal data motion.
1605: ;;
1606: ;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1607: ;; all fp insns are actually done in double. The only conversions we will
1608: ;; do will be when storing to memory. In that case, we will use the "frsp"
1609: ;; instruction before storing.
1610: ;;
1611: ;; Note that when we store into a single-precision memory location, we need to
1612: ;; use the frsp insn first. If the register being stored isn't dead, we
1613: ;; need a scratch register for the frsp. But this is difficult when the store
1614: ;; is done by reload. It is not incorrect to do the frsp on the register in
1615: ;; this case, we just lose precision that we would have otherwise gotten but
1616: ;; is not guaranteed. Perhaps this should be tightened up at some point.
1617:
1618: (define_insn "extendsfdf2"
1.1.1.3 root 1619: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1620: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1621: ""
1622: "*
1623: {
1624: if (REGNO (operands[0]) == REGNO (operands[1]))
1625: return \"\";
1626: else
1627: return \"fmr %0,%1\";
1628: }"
1629: [(set_attr "type" "fp")])
1630:
1631: (define_insn "truncdfsf2"
1.1.1.3 root 1632: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1633: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1634: ""
1635: "*
1636: {
1637: if (REGNO (operands[0]) == REGNO (operands[1]))
1638: return \"\";
1639: else
1640: return \"fmr %0,%1\";
1641: }"
1642: [(set_attr "type" "fp")])
1643:
1644: (define_insn "negsf2"
1.1.1.3 root 1645: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1646: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1647: ""
1648: "fneg %0,%1"
1649: [(set_attr "type" "fp")])
1650:
1651: (define_insn "abssf2"
1.1.1.3 root 1652: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1653: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1.1 root 1654: ""
1655: "fabs %0,%1"
1656: [(set_attr "type" "fp")])
1657:
1658: (define_insn ""
1.1.1.3 root 1659: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1660: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
1.1 root 1661: ""
1662: "fnabs %0,%1"
1663: [(set_attr "type" "fp")])
1664:
1665: (define_insn "addsf3"
1.1.1.3 root 1666: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1667: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1668: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1669: ""
1670: "fa %0,%1,%2"
1671: [(set_attr "type" "fp")])
1672:
1673: (define_insn "subsf3"
1.1.1.3 root 1674: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1675: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
1676: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1677: ""
1678: "fs %0,%1,%2"
1679: [(set_attr "type" "fp")])
1680:
1681: (define_insn "mulsf3"
1.1.1.3 root 1682: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1683: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1684: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1685: ""
1686: "fm %0,%1,%2"
1687: [(set_attr "type" "fp")])
1688:
1689: (define_insn "divsf3"
1.1.1.3 root 1690: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1691: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
1692: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 1693: ""
1694: "fd %0,%1,%2"
1695: [(set_attr "type" "fp")])
1696:
1697: (define_insn ""
1.1.1.3 root 1698: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1699: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1700: (match_operand:SF 2 "gpc_reg_operand" "f"))
1701: (match_operand:SF 3 "gpc_reg_operand" "f")))]
1.1 root 1702: ""
1703: "fma %0,%1,%2,%3"
1704: [(set_attr "type" "fp")])
1705:
1706: (define_insn ""
1.1.1.3 root 1707: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1708: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1709: (match_operand:SF 2 "gpc_reg_operand" "f"))
1710: (match_operand:SF 3 "gpc_reg_operand" "f")))]
1.1 root 1711: ""
1712: "fms %0,%1,%2,%3"
1713: [(set_attr "type" "fp")])
1714:
1715: (define_insn ""
1.1.1.3 root 1716: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1717: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1718: (match_operand:SF 2 "gpc_reg_operand" "f"))
1719: (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1.1 root 1720: ""
1721: "fnma %0,%1,%2,%3"
1722: [(set_attr "type" "fp")])
1723:
1724: (define_insn ""
1.1.1.3 root 1725: [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
1726: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
1727: (match_operand:SF 2 "gpc_reg_operand" "f"))
1728: (match_operand:SF 3 "gpc_reg_operand" "f"))))]
1.1 root 1729: ""
1730: "fnms %0,%1,%2,%3"
1731: [(set_attr "type" "fp")])
1732:
1733: (define_insn "negdf2"
1.1.1.3 root 1734: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1735: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1736: ""
1737: "fneg %0,%1"
1738: [(set_attr "type" "fp")])
1739:
1740: (define_insn "absdf2"
1.1.1.3 root 1741: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1742: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1.1 root 1743: ""
1744: "fabs %0,%1"
1745: [(set_attr "type" "fp")])
1746:
1747: (define_insn ""
1.1.1.3 root 1748: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1749: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
1.1 root 1750: ""
1751: "fnabs %0,%1"
1752: [(set_attr "type" "fp")])
1753:
1754: (define_insn "adddf3"
1.1.1.3 root 1755: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1756: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1757: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1758: ""
1759: "fa %0,%1,%2"
1760: [(set_attr "type" "fp")])
1761:
1762: (define_insn "subdf3"
1.1.1.3 root 1763: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1764: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
1765: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1766: ""
1767: "fs %0,%1,%2"
1768: [(set_attr "type" "fp")])
1769:
1770: (define_insn "muldf3"
1.1.1.3 root 1771: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1772: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1773: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1774: ""
1775: "fm %0,%1,%2"
1776: [(set_attr "type" "fp")])
1777:
1778: (define_insn "divdf3"
1.1.1.3 root 1779: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1780: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
1781: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 1782: ""
1783: "fd %0,%1,%2"
1784: [(set_attr "type" "fp")])
1785:
1786: (define_insn ""
1.1.1.3 root 1787: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1788: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1789: (match_operand:DF 2 "gpc_reg_operand" "f"))
1790: (match_operand:DF 3 "gpc_reg_operand" "f")))]
1.1 root 1791: ""
1792: "fma %0,%1,%2,%3"
1793: [(set_attr "type" "fp")])
1794:
1795: (define_insn ""
1.1.1.3 root 1796: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1797: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1798: (match_operand:DF 2 "gpc_reg_operand" "f"))
1799: (match_operand:DF 3 "gpc_reg_operand" "f")))]
1.1 root 1800: ""
1801: "fms %0,%1,%2,%3"
1802: [(set_attr "type" "fp")])
1803:
1804: (define_insn ""
1.1.1.3 root 1805: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1806: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1807: (match_operand:DF 2 "gpc_reg_operand" "f"))
1808: (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1.1 root 1809: ""
1810: "fnma %0,%1,%2,%3"
1811: [(set_attr "type" "fp")])
1812:
1813: (define_insn ""
1.1.1.3 root 1814: [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
1815: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
1816: (match_operand:DF 2 "gpc_reg_operand" "f"))
1817: (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1.1 root 1818: ""
1819: "fnms %0,%1,%2,%3"
1820: [(set_attr "type" "fp")])
1821:
1822: ;; Conversions to and from floating-point.
1823: (define_expand "floatsidf2"
1824: [(set (match_dup 2)
1825: (plus:DI (zero_extend:DI
1.1.1.3 root 1826: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 1827: (match_dup 3)))
1828: (match_dup 4)))
1.1.1.3 root 1829: (set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 1830: (minus:DF (subreg:DF (match_dup 2) 0)
1831: (match_dup 5)))]
1832: ""
1833: "
1834: {
1835: #if HOST_BITS_PER_INT != BITS_PER_WORD
1836: /* Maybe someone can figure out how to do this in that case. I don't
1837: want to right now. */
1838: abort ();
1839: #endif
1840:
1841: operands[2] = gen_reg_rtx (DImode);
1842: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1843: operands[4] = immed_double_const (0, 0x43300000, DImode);
1844: operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1845: 0x80000000, DFmode));
1846: }")
1847:
1848: (define_expand "floatunssidf2"
1849: [(set (match_dup 2)
1.1.1.3 root 1850: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1.1 root 1851: (match_dup 3)))
1.1.1.3 root 1852: (set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 1853: (minus:DF (subreg:DF (match_dup 2) 0)
1854: (match_dup 4)))]
1855: ""
1856: "
1857: {
1858: #if HOST_BITS_PER_INT != BITS_PER_WORD
1859: /* Maybe someone can figure out how to do this in that case. I don't
1860: want to right now. */
1861: abort ();
1862: #endif
1863:
1864: operands[2] = gen_reg_rtx (DImode);
1865: operands[3] = immed_double_const (0, 0x43300000, DImode);
1866: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1867: }")
1868:
1869: ;; For the above two cases, we always split.
1870: (define_split
1.1.1.3 root 1871: [(set (match_operand:DI 0 "gpc_reg_operand" "")
1.1 root 1872: (plus:DI (zero_extend:DI
1.1.1.3 root 1873: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 1874: (match_operand:SI 2 "logical_operand" "")))
1875: (match_operand:DI 3 "immediate_operand" "")))]
1876: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1877: && GET_CODE (operands[3]) == CONST_DOUBLE
1878: && CONST_DOUBLE_LOW (operands[3]) == 0"
1879: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1880: (set (match_dup 4) (match_dup 5))]
1881: "
1882: { operands[4] = operand_subword (operands[0], 0, 0, DImode);
1883: operands[5] = operand_subword (operands[3], 0, 0, DImode);
1884: operands[6] = operand_subword (operands[0], 1, 0, DImode);
1885: }")
1886:
1887: (define_insn ""
1.1.1.3 root 1888: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1.1 root 1889: (plus:DI (zero_extend:DI
1.1.1.3 root 1890: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1.1 root 1891: (match_operand:SI 2 "logical_operand" "rKJ")))
1892: (match_operand:DI 3 "immediate_operand" "n")))]
1893: "HOST_BITS_PER_INT == BITS_PER_WORD
1894: && GET_CODE (operands[3]) == CONST_DOUBLE
1895: && CONST_DOUBLE_LOW (operands[3]) == 0"
1896: "#")
1897:
1898: (define_split
1.1.1.3 root 1899: [(set (match_operand:DI 0 "gpc_reg_operand" "=")
1900: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1.1 root 1901: (match_operand:DI 2 "immediate_operand" "")))]
1902: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1903: && GET_CODE (operands[2]) == CONST_DOUBLE
1904: && CONST_DOUBLE_LOW (operands[2]) == 0"
1905: [(set (match_dup 3) (match_dup 4))
1906: (set (match_dup 5) (match_dup 1))]
1907: "
1908: { operands[3] = operand_subword (operands[0], 0, 0, DImode);
1909: operands[4] = operand_subword (operands[2], 0, 0, DImode);
1910: operands[5] = operand_subword (operands[0], 1, 0, DImode);
1911:
1912: if (rtx_equal_p (operands[1], operands[5]))
1913: {
1914: emit_move_insn (operands[3], operands[4]);
1915: DONE;
1916: }
1.1.1.4 ! root 1917:
! 1918: if (rtx_equal_p (operands[1], operands[3]))
! 1919: {
! 1920: rtx temp;
! 1921:
! 1922: temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
! 1923: temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
! 1924: }
1.1 root 1925: }")
1926:
1927: (define_insn ""
1.1.1.3 root 1928: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1929: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 1930: (match_operand:DI 2 "immediate_operand" "n")))]
1931: "HOST_BITS_PER_INT == BITS_PER_WORD
1932: && GET_CODE (operands[2]) == CONST_DOUBLE
1933: && CONST_DOUBLE_LOW (operands[2]) == 0"
1934: "#")
1935:
1936: (define_expand "fix_truncdfsi2"
1.1.1.3 root 1937: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1938: (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 1939: ""
1940: "
1941: {
1942: emit_insn (gen_trunc_call (operands[0], operands[1],
1943: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1944: DONE;
1945: }")
1946:
1947: (define_expand "fixuns_truncdfsi2"
1.1.1.3 root 1948: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1949: (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 1950: ""
1951: "
1952: {
1953: emit_insn (gen_trunc_call (operands[0], operands[1],
1954: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1955: DONE;
1956: }")
1957:
1958:
1959: (define_expand "trunc_call"
1960: [(parallel [(set (match_operand:SI 0 "" "")
1961: (fix:DF (match_operand:DF 1 "" "")))
1962: (use (match_operand:SI 2 "" ""))])]
1963: ""
1964: "
1965: {
1966: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1967: rtx first = XVECEXP (insns, 0, 0);
1968: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1969:
1970: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1971: REG_NOTES (first));
1972: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1973:
1974: emit_insn (insns);
1975: DONE;
1976: }")
1977:
1978: (define_expand "trunc_call_rtl"
1.1.1.3 root 1979: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
1.1 root 1980: (use (reg:DF 33))
1981: (parallel [(set (reg:SI 3)
1982: (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1983: (clobber (scratch:SI))])
1.1.1.3 root 1984: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 1985: (reg:SI 3))]
1986: ""
1987: "
1988: {
1989: rs6000_trunc_used = 1;
1990: }")
1991:
1992: ;; Define the DImode operations that can be done in a small number
1993: ;; of instructions.
1994: (define_insn "adddi3"
1.1.1.3 root 1995: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1996: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
1997: (match_operand:DI 2 "gpc_reg_operand" "r")))]
1.1 root 1998: ""
1999: "a %L0,%L1,%L2\;ae %0,%1,%2")
2000:
2001: (define_insn "subdi3"
1.1.1.3 root 2002: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2003: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2004: (match_operand:DI 2 "gpc_reg_operand" "r")))]
1.1 root 2005: ""
2006: "sf %L0,%L2,%L1\;sfe %0,%2,%1")
2007:
1.1.1.4 ! root 2008: (define_insn "negdi2"
1.1.1.3 root 2009: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2010: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
1.1 root 2011: ""
2012: "sfi %L0,%L1,0\;sfze %0,%1")
2013:
2014: (define_insn "mulsidi3"
1.1.1.3 root 2015: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2016: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2017: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1.1 root 2018: (clobber (match_scratch:SI 3 "=q"))]
2019: ""
2020: "mul %0,%1,%2\;mfmq %L0")
2021:
2022: ;; If operands 0 and 2 are in the same register, we have a problem. But
2023: ;; operands 0 and 1 (the usual case) can be in the same register. That's
2024: ;; why we have the strange constraints below.
2025: (define_insn "ashldi3"
1.1.1.3 root 2026: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
2027: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1.1 root 2028: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2029: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2030: ""
2031: "@
2032: sli %0,%L1,%h2\;cal %L0,0(0)
2033: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
2034: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1.1.1.2 root 2035: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
1.1 root 2036:
2037: (define_insn "lshrdi3"
1.1.1.3 root 2038: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
2039: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1.1 root 2040: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2041: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2042: ""
2043: "@
1.1.1.2 root 2044: cal %0,0(0)\;s%A2i %L0,%1,%h2
1.1.1.3 root 2045: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2046: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2047: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2")
1.1 root 2048:
2049: ;; Shift by a variable amount is too complex to be worth open-coding. We
2050: ;; just handle shifts by constants.
2051:
2052: (define_expand "ashrdi3"
1.1.1.3 root 2053: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
2054: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
1.1 root 2055: (match_operand:SI 2 "general_operand" "")))
2056: (clobber (match_scratch:SI 3 ""))])]
2057: ""
2058: "
2059: { if (GET_CODE (operands[2]) != CONST_INT)
2060: FAIL;
2061: }")
2062:
2063: (define_insn ""
1.1.1.3 root 2064: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2065: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
1.1 root 2066: (match_operand:SI 2 "const_int_operand" "M,i")))
2067: (clobber (match_scratch:SI 3 "=X,q"))]
2068: ""
2069: "@
2070: srai %0,%1,31\;srai %L0,%1,%h2
1.1.1.3 root 2071: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2")
1.1 root 2072:
2073: ;; Now define ways of moving data around.
2074: ;;
2075: ;; For SI, we special-case integers that can't be loaded in one insn. We
2076: ;; do the load 16-bits at a time. We could do this by loading from memory,
2077: ;; and this is even supposed to be faster, but it is simpler not to get
2078: ;; integers in the TOC.
2079: (define_expand "movsi"
2080: [(set (match_operand:SI 0 "general_operand" "")
2081: (match_operand:SI 1 "any_operand" ""))]
2082: ""
2083: "
2084: {
2085: if (GET_CODE (operands[0]) != REG)
2086: operands[1] = force_reg (SImode, operands[1]);
2087:
2088: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2089: operands[1] = force_const_mem (SImode, operands[1]);
2090:
2091: if (GET_CODE (operands[1]) == CONST_INT
2092: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2093: && (INTVAL (operands[1]) & 0xffff) != 0)
2094: {
2095: emit_move_insn (operands[0],
2096: gen_rtx (CONST_INT, VOIDmode,
2097: INTVAL (operands[1]) & 0xffff0000));
2098: emit_insn (gen_iorsi3 (operands[0], operands[0],
2099: gen_rtx (CONST_INT, VOIDmode,
2100: INTVAL (operands[1]) & 0xffff)));
2101: DONE;
2102: }
2103: }")
2104:
2105: (define_insn ""
1.1.1.2 root 2106: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
2107: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
1.1.1.3 root 2108: "gpc_reg_operand (operands[0], SImode)
2109: || gpc_reg_operand (operands[1], SImode)"
1.1 root 2110: "@
2111: ai %0,%1,0
2112: l%U1%X1 %0,%1
2113: st%U0%X0 %1,%0
2114: cal %0,%1(0)
2115: cau %0,0,%u1
2116: mf%1 %0
1.1.1.2 root 2117: mt%0 %1
1.1 root 2118: mt%0 %1"
1.1.1.2 root 2119: [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
1.1 root 2120:
1.1.1.4 ! root 2121: ;; Split a load of a large constant into the appropriate two-insn
! 2122: ;; sequence.
! 2123:
! 2124: (define_split
! 2125: [(set (match_operand:SI 0 "gpc_reg_operand" "")
! 2126: (match_operand:SI 1 "const_int_operand" ""))]
! 2127: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
! 2128: && (INTVAL (operands[1]) & 0xffff) != 0"
! 2129: [(set (match_dup 0)
! 2130: (match_dup 2))
! 2131: (set (match_dup 0)
! 2132: (ior:SI (match_dup 0)
! 2133: (match_dup 3)))]
! 2134: "
! 2135: {
! 2136: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 2137: INTVAL (operands[1]) & 0xffff0000);
! 2138: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
! 2139: }")
! 2140:
1.1 root 2141: (define_insn ""
2142: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1.1.1.3 root 2143: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 2144: (const_int 0)))
1.1.1.3 root 2145: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
1.1 root 2146: ""
2147: "ai. %0,%1,0"
2148: [(set_attr "type" "compare")])
2149:
2150: (define_expand "movhi"
2151: [(set (match_operand:HI 0 "general_operand" "")
2152: (match_operand:HI 1 "any_operand" ""))]
2153: ""
2154: "
2155: {
2156: if (GET_CODE (operands[0]) != REG)
2157: operands[1] = force_reg (HImode, operands[1]);
2158:
2159: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2160: operands[1] = force_const_mem (HImode, operands[1]);
2161: }")
2162:
2163: (define_insn ""
2164: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2165: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
1.1.1.3 root 2166: "gpc_reg_operand (operands[0], HImode)
2167: || gpc_reg_operand (operands[1], HImode)"
1.1 root 2168: "@
2169: oril %0,%1,0
2170: lhz%U1%X1 %0,%1
2171: sth%U0%X0 %1,%0
2172: cal %0,%w1(0)
2173: mf%1 %0
2174: mt%0 %1"
2175: [(set_attr "type" "*,load,*,*,*,*")])
2176:
2177: (define_expand "movqi"
2178: [(set (match_operand:QI 0 "general_operand" "")
2179: (match_operand:QI 1 "any_operand" ""))]
2180: ""
2181: "
2182: {
2183: if (GET_CODE (operands[0]) != REG)
2184: operands[1] = force_reg (QImode, operands[1]);
2185:
2186: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2187: operands[1] = force_const_mem (QImode, operands[1]);
2188: }")
2189:
2190: (define_insn ""
2191: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2192: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
1.1.1.3 root 2193: "gpc_reg_operand (operands[0], QImode)
2194: || gpc_reg_operand (operands[1], QImode)"
1.1 root 2195: "@
2196: oril %0,%1,0
2197: lbz%U1%X1 %0,%1
2198: stb%U0%X0 %1,%0
2199: cal %0,%1(0)
2200: mf%1 %0
2201: mt%0 %1"
2202: [(set_attr "type" "*,load,*,*,*,*")])
2203:
2204: ;; Here is how to move condition codes around. When we store CC data in
2205: ;; an integer register or memory, we store just the high-order 4 bits.
2206: ;; This lets us not shift in the most common case of CR0.
2207: (define_expand "movcc"
2208: [(set (match_operand:CC 0 "nonimmediate_operand" "")
2209: (match_operand:CC 1 "nonimmediate_operand" ""))]
2210: ""
2211: "")
2212:
2213: (define_insn ""
2214: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2215: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2216: "register_operand (operands[0], CCmode)
2217: || register_operand (operands[1], CCmode)"
2218: "@
2219: mcrf %0,%1
2220: mtcrf 128,%1
2221: rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2222: mfcr %0
2223: mfcr %0\;rlinm %0,%0,%f1,0,3
2224: ai %0,%1,0
2225: l%U1%X1 %0,%1
2226: st%U0%U1 %1,%0"
2227: [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2228:
2229: ;; For floating-point, we normally deal with the floating-point registers.
2230: ;; The sole exception is that parameter passing can produce floating-point
2231: ;; values in fixed-point registers. Unless the value is a simple constant
2232: ;; or already in memory, we deal with this by allocating memory and copying
2233: ;; the value explicitly via that memory location.
2234: (define_expand "movsf"
2235: [(set (match_operand:SF 0 "nonimmediate_operand" "")
2236: (match_operand:SF 1 "any_operand" ""))]
2237: ""
2238: "
2239: {
2240: /* If we are called from reload, we might be getting a SUBREG of a hard
2241: reg. So expand it. */
2242: if (GET_CODE (operands[0]) == SUBREG
2243: && GET_CODE (SUBREG_REG (operands[0])) == REG
2244: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2245: operands[0] = alter_subreg (operands[0]);
2246: if (GET_CODE (operands[1]) == SUBREG
2247: && GET_CODE (SUBREG_REG (operands[1])) == REG
2248: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2249: operands[1] = alter_subreg (operands[1]);
2250:
2251: /* If we are being called from reload, it is possible that operands[1]
2252: is a hard non-fp register. So handle those cases. */
2253: if (reload_in_progress && GET_CODE (operands[1]) == REG
2254: && REGNO (operands[1]) < 32)
2255: {
2256: rtx stack_slot;
2257:
2258: /* Remember that we only see a pseudo here if it didn't get a hard
2259: register, so it is memory. */
2260: if (GET_CODE (operands[0]) == MEM
2261: || (GET_CODE (operands[0]) == REG
2262: && (REGNO (operands[0]) < 32
2263: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2264: || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2265: {
2266: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2267: operand_subword (operands[1], 0, 0, SFmode));
2268: DONE;
2269: }
2270:
2271: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2272: emit_move_insn (stack_slot, operands[1]);
2273: emit_move_insn (operands[0], stack_slot);
2274: DONE;
2275: }
2276:
2277: if (GET_CODE (operands[0]) == MEM)
2278: operands[1] = force_reg (SFmode, operands[1]);
2279:
2280: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2281: {
2282: rtx stack_slot;
2283:
2284: if (GET_CODE (operands[1]) == MEM
2285: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2286: || GET_CODE (operands[1]) == CONST_DOUBLE
2287: #endif
2288: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2289: || (reload_in_progress && GET_CODE (operands[1]) == REG
2290: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2291: {
2292: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2293: operand_subword (operands[1], 0, 0, SFmode));
2294: DONE;
2295: }
2296:
2297: if (reload_in_progress)
2298: stack_slot = gen_rtx (MEM, SFmode,
2299: plus_constant (stack_pointer_rtx, 4));
2300: else
2301: stack_slot = assign_stack_temp (SFmode, 4, 0);
2302: emit_move_insn (stack_slot, operands[1]);
2303: emit_move_insn (operands[0], stack_slot);
2304: DONE;
2305: }
2306:
2307: if (CONSTANT_P (operands[1]))
2308: {
2309: operands[1] = force_const_mem (SFmode, operands[1]);
2310: if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2311: && ! reload_in_progress)
2312: operands[1] = change_address (operands[1], SFmode,
2313: XEXP (operands[1], 0));
2314: }
2315: }")
2316:
2317: (define_insn ""
1.1.1.3 root 2318: [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
1.1 root 2319: (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2320: "REGNO (operands[0]) <= 31"
2321: "@
2322: #
2323: l%U1%X1 %0,%1"
2324: [(set_attr "type" "*,load")])
2325:
2326: (define_split
1.1.1.3 root 2327: [(set (match_operand:SF 0 "gpc_reg_operand" "")
1.1 root 2328: (match_operand:SF 1 "easy_fp_constant" ""))]
2329: "reload_completed && REGNO (operands[0]) <= 31"
2330: [(set (match_dup 2) (match_dup 3))]
2331: "
2332: { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2333: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2334:
2335: (define_insn ""
2336: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2337: (match_operand:SF 1 "input_operand" "f,m,f"))]
1.1.1.3 root 2338: "gpc_reg_operand (operands[0], SFmode)
2339: || gpc_reg_operand (operands[1], SFmode)"
1.1 root 2340: "@
2341: fmr %0,%1
2342: lfs%U1%X1 %0,%1
2343: frsp %1,%1\;stfs%U0%X0 %1,%0"
2344: [(set_attr "type" "fp,load,*")])
2345:
2346: (define_expand "movdf"
2347: [(set (match_operand:DF 0 "nonimmediate_operand" "")
2348: (match_operand:DF 1 "any_operand" ""))]
2349: ""
2350: "
2351: {
2352: /* If we are called from reload, we might be getting a SUBREG of a hard
2353: reg. So expand it. */
2354: if (GET_CODE (operands[0]) == SUBREG
2355: && GET_CODE (SUBREG_REG (operands[0])) == REG
2356: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2357: operands[0] = alter_subreg (operands[0]);
2358: if (GET_CODE (operands[1]) == SUBREG
2359: && GET_CODE (SUBREG_REG (operands[1])) == REG
2360: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2361: operands[1] = alter_subreg (operands[1]);
2362:
2363: /* If we are being called from reload, it is possible that operands[1]
2364: is a hard non-fp register. So handle those cases. */
2365: if (reload_in_progress && GET_CODE (operands[1]) == REG
2366: && REGNO (operands[1]) < 32)
2367: {
2368: rtx stack_slot;
2369:
2370: /* Remember that we only see a pseudo here if it didn't get a hard
2371: register, so it is memory. */
2372: if (GET_CODE (operands[0]) == MEM
2373: || (GET_CODE (operands[0]) == REG
2374: && (REGNO (operands[0]) < 32
2375: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2376: {
2377: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2378: operand_subword (operands[1], 0, 0, DFmode));
2379: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2380: operand_subword (operands[1], 1, 0, DFmode));
2381: DONE;
2382: }
2383:
2384: stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2385: emit_move_insn (stack_slot, operands[1]);
2386: emit_move_insn (operands[0], stack_slot);
2387: DONE;
2388: }
2389:
2390: if (GET_CODE (operands[0]) == MEM)
2391: {
2392: if (GET_CODE (operands[1]) == MEM)
2393: {
2394: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2395: operand_subword (operands[1], 0, 0, DFmode));
2396: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2397: operand_subword (operands[1], 1, 0, DFmode));
2398: DONE;
2399: }
2400:
2401: operands[1] = force_reg (DFmode, operands[1]);
2402: }
2403:
2404: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2405: {
2406: rtx stack_slot;
2407:
2408: if (GET_CODE (operands[1]) == MEM
2409: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2410: || GET_CODE (operands[1]) == CONST_DOUBLE
2411: #endif
2412: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2413: || (reload_in_progress && GET_CODE (operands[1]) == REG
2414: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2415: {
2416: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2417: operand_subword (operands[1], 0, 0, DFmode));
2418: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2419: operand_subword (operands[1], 1, 0, DFmode));
2420: DONE;
2421: }
2422:
2423: if (reload_in_progress)
2424: stack_slot = gen_rtx (MEM, DFmode,
2425: plus_constant (stack_pointer_rtx, 8));
2426: else
2427: stack_slot = assign_stack_temp (DFmode, 8, 0);
2428: emit_move_insn (stack_slot, operands[1]);
2429: emit_move_insn (operands[0], stack_slot);
2430: DONE;
2431: }
2432:
2433: if (CONSTANT_P (operands[1]))
2434: {
2435: operands[1] = force_const_mem (DFmode, operands[1]);
2436: if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2437: && ! reload_in_progress)
2438: operands[1] = change_address (operands[1], DFmode,
2439: XEXP (operands[1], 0));
2440: }
2441: }")
2442:
2443: (define_insn ""
1.1.1.3 root 2444: [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r")
1.1 root 2445: (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2446: "REGNO (operands[0]) <= 31"
2447: "@
2448: #
2449: l %0,%1\;l %L0,%L1"
2450: [(set_attr "type" "*,load")])
2451:
2452: (define_split
1.1.1.3 root 2453: [(set (match_operand:DF 0 "gpc_reg_operand" "")
1.1 root 2454: (match_operand:DF 1 "easy_fp_constant" ""))]
2455: "reload_completed && REGNO (operands[0]) <= 31"
2456: [(set (match_dup 2) (match_dup 3))
2457: (set (match_dup 4) (match_dup 5))]
2458: "
2459: { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2460: operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2461: operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2462: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2463:
2464: (define_insn ""
2465: [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2466: (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
1.1.1.3 root 2467: "gpc_reg_operand (operands[0], DFmode)
2468: || gpc_reg_operand (operands[1], DFmode)"
1.1 root 2469: "@
2470: fmr %0,%1
2471: lfd%U1%X1 %0,%1
2472: stfd%U0%X0 %1,%0"
2473: [(set_attr "type" "fp,load,*")])
2474:
2475: ;; Next come the multi-word integer load and store and the load and store
2476: ;; multiple insns.
2477: (define_expand "movdi"
2478: [(set (match_operand:DI 0 "general_operand" "")
2479: (match_operand:DI 1 "general_operand" ""))]
2480: ""
2481: "
2482: {
1.1.1.4 ! root 2483: if (GET_CODE (operands[1]) == CONST_DOUBLE
! 2484: || GET_CODE (operands[1]) == CONST_INT)
1.1 root 2485: {
2486: emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2487: operand_subword (operands[1], 0, 0, DImode));
2488: emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2489: operand_subword (operands[1], 1, 0, DImode));
2490: DONE;
2491: }
1.1.1.4 ! root 2492:
! 2493: if (GET_CODE (operands[0]) == MEM)
! 2494: operands[1] = force_reg (DImode, operands[1]);
1.1 root 2495: }")
2496:
2497: (define_insn ""
2498: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2499: (match_operand:DI 1 "input_operand" "r,m,r"))]
1.1.1.3 root 2500: "gpc_reg_operand (operands[0], DImode)
2501: || gpc_reg_operand (operands[1], DImode)"
1.1 root 2502: "*
2503: {
2504: switch (which_alternative)
2505: {
2506: case 0:
2507: /* We normally copy the low-numbered register first. However, if
2508: the first register operand 0 is the same as the second register of
2509: operand 1, we must copy in the opposite order. */
2510: if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2511: return \"oril %L0,%L1,0\;oril %0,%1,0\";
2512: else
2513: return \"oril %0,%1,0\;oril %L0,%L1,0\";
2514: case 1:
2515: /* If the low-address word is used in the address, we must load it
2516: last. Otherwise, load it first. Note that we cannot have
2517: auto-increment in that case since the address register is known to be
2518: dead. */
2519: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2520: operands [1], 0))
2521: return \"l %L0,%L1\;l %0,%1\";
2522: else
2523: return \"l%U1 %0,%1\;l %L0,%L1\";
2524: case 2:
2525: return \"st%U0 %1,%0\;st %L1,%L0\";
2526: }
2527: }"
2528: [(set_attr "type" "*,load,*")])
2529:
2530: ;; TImode is similar, except that we usually want to compute the address into
2531: ;; a register and use lsi/stsi (the exception is during reload). MQ is also
2532: ;; clobbered in stsi, so we need a SCRATCH for it.
2533: (define_expand "movti"
2534: [(parallel [(set (match_operand:TI 0 "general_operand" "")
2535: (match_operand:TI 1 "general_operand" ""))
2536: (clobber (scratch:SI))])]
2537: ""
2538: "
2539: {
2540: if (GET_CODE (operands[0]) == MEM)
2541: operands[1] = force_reg (TImode, operands[1]);
2542:
2543: if (GET_CODE (operands[0]) == MEM
2544: && GET_CODE (XEXP (operands[0], 0)) != REG
2545: && ! reload_in_progress)
2546: operands[0] = change_address (operands[0], TImode,
2547: copy_addr_to_reg (XEXP (operands[0], 0)));
2548:
2549: if (GET_CODE (operands[1]) == MEM
2550: && GET_CODE (XEXP (operands[1], 0)) != REG
2551: && ! reload_in_progress)
2552: operands[1] = change_address (operands[1], TImode,
2553: copy_addr_to_reg (XEXP (operands[1], 0)));
2554: }")
2555:
2556: ;; We say that MQ is clobbered in the last alternative because the first
2557: ;; alternative would never get used otherwise since it would need a reload
2558: ;; while the 2nd alternative would not. We put memory cases first so they
2559: ;; are preferred. Otherwise, we'd try to reload the output instead of
2560: ;; giving the SCRATCH mq.
2561: (define_insn ""
2562: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2563: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2564: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
1.1.1.3 root 2565: "gpc_reg_operand (operands[0], TImode)
2566: || gpc_reg_operand (operands[1], TImode)"
1.1 root 2567: "*
2568: {
2569: switch (which_alternative)
2570: {
2571: case 0:
2572: return \"stsi %1,%P0,16\";
2573:
2574: case 1:
2575: return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2576:
2577: case 2:
2578: /* Normally copy registers with lowest numbered register copied first.
2579: But copy in the other order if the first register of the output
2580: is the second, third, or fourth register in the input. */
2581: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2582: && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2583: return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2584: else
2585: return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2586: case 3:
2587: /* If the address is not used in the output, we can use lsi. Otherwise,
2588: fall through to generating four loads. */
2589: if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2590: return \"lsi %0,%P1,16\";
2591: /* ... fall through ... */
2592: case 4:
2593: /* If the address register is the same as the register for the lowest-
2594: addressed word, load it last. Similarly for the next two words.
2595: Otherwise load lowest address to highest. */
2596: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2597: operands[1], 0))
2598: return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2599: else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2600: REGNO (operands[0]) + 2, operands[1], 0))
2601: return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2602: else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2603: REGNO (operands[0]) + 3, operands[1], 0))
2604: return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2605: else
2606: return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2607: }
2608: }"
2609: [(set_attr "type" "*,load,load,*,*")])
2610:
2611: (define_expand "load_multiple"
1.1.1.4 ! root 2612: [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
! 2613: (match_operand:SI 1 "" ""))
! 2614: (use (match_operand:SI 2 "" ""))])]
1.1 root 2615: ""
2616: "
2617: {
2618: int regno;
2619: int count;
2620: rtx from;
2621: int i;
2622:
2623: /* Support only loading a constant number of fixed-point registers from
2624: memory and only bother with this if more than two; the machine
2625: doesn't support more than eight. */
2626: if (GET_CODE (operands[2]) != CONST_INT
2627: || INTVAL (operands[2]) <= 2
2628: || INTVAL (operands[2]) > 8
2629: || GET_CODE (operands[1]) != MEM
2630: || GET_CODE (operands[0]) != REG
2631: || REGNO (operands[0]) >= 32)
2632: FAIL;
2633:
2634: count = INTVAL (operands[2]);
2635: regno = REGNO (operands[0]);
2636:
2637: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2638: from = force_reg (SImode, XEXP (operands[1], 0));
2639:
2640: for (i = 0; i < count; i++)
2641: XVECEXP (operands[3], 0, i)
2642: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2643: gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2644: }")
2645:
2646: (define_insn ""
2647: [(match_parallel 0 "load_multiple_operation"
1.1.1.3 root 2648: [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
1.1 root 2649: (match_operand:SI 2 "indirect_operand" "Q"))])]
2650: ""
2651: "*
2652: {
2653: /* We have to handle the case where the pseudo used to contain the address
2654: is assigned to one of the output registers. In that case, do the
2655: lsi, but then load the correct value. This is a bit of a mess, but is
2656: the best we can do. */
2657: static char result[100];
2658: char newload[40];
2659: int i;
2660:
2661: strcpy (result, \"lsi %1,%P2,%N0\");
2662: for (i = 0; i < XVECLEN (operands[0], 0); i++)
2663: if (refers_to_regno_p (REGNO (operands[1]) + i,
2664: REGNO (operands[1]) + i + 1, operands[2], 0))
2665: {
2666: sprintf (newload, \"\;l %d,%d(%d)\",
2667: REGNO (operands[1]) + i,
2668: i * 4, REGNO (XEXP (operands[2], 0)));
2669: strcat (result, newload);
2670: }
2671:
2672: return result;
2673: }"
2674: [(set_attr "type" "load")])
2675:
2676: (define_expand "store_multiple"
1.1.1.4 ! root 2677: [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
! 2678: (match_operand:SI 1 "" ""))
! 2679: (clobber (scratch:SI))
! 2680: (use (match_operand:SI 2 "" ""))])]
1.1 root 2681: ""
2682: "
2683: {
2684: int regno;
2685: int count;
2686: rtx to;
2687: int i;
2688:
2689: /* Support only storing a constant number of fixed-point registers to
2690: memory and only bother with this if more than two; the machine
2691: doesn't support more than eight. */
2692: if (GET_CODE (operands[2]) != CONST_INT
2693: || INTVAL (operands[2]) <= 2
2694: || INTVAL (operands[2]) > 8
2695: || GET_CODE (operands[0]) != MEM
2696: || GET_CODE (operands[1]) != REG
2697: || REGNO (operands[1]) >= 32)
2698: FAIL;
2699:
2700: count = INTVAL (operands[2]);
2701: regno = REGNO (operands[1]);
2702:
2703: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2704: to = force_reg (SImode, XEXP (operands[0], 0));
2705:
2706: XVECEXP (operands[3], 0, 0)
2707: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2708: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2709: gen_rtx (SCRATCH, SImode));
2710:
2711: for (i = 1; i < count; i++)
2712: XVECEXP (operands[3], 0, i + 1)
2713: = gen_rtx (SET, VOIDmode,
2714: gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2715: gen_rtx (REG, SImode, regno + i));
2716: }")
2717:
2718: (define_insn ""
2719: [(match_parallel 0 "store_multiple_operation"
2720: [(set (match_operand:SI 1 "indirect_operand" "=Q")
1.1.1.3 root 2721: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 2722: (clobber (match_scratch:SI 3 "=q"))])]
2723: ""
2724: "stsi %2,%P1,%O0")
2725:
2726: ;; Define insns that do load or store with update. Some of these we can
2727: ;; get by using pre-decrement or pre-increment, but the hardware can also
2728: ;; do cases where the increment is not the size of the object.
2729: ;;
2730: ;; In all these cases, we use operands 0 and 1 for the register being
2731: ;; incremented because those are the operands that local-alloc will
2732: ;; tie and these are the pair most likely to be tieable (and the ones
2733: ;; that will benefit the most).
2734:
2735: (define_insn ""
1.1.1.3 root 2736: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
2737: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2738: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 root 2739: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2740: (plus:SI (match_dup 1) (match_dup 2)))]
2741: ""
2742: "@
1.1.1.4 ! root 2743: lux %3,%0,%2
! 2744: lu %3,%2(%0)"
1.1 root 2745: [(set_attr "type" "load,load")])
2746:
2747: (define_insn ""
1.1.1.3 root 2748: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2749: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 root 2750: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2751: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2752: (plus:SI (match_dup 1) (match_dup 2)))]
2753: ""
2754: "@
1.1.1.4 ! root 2755: stux %3,%0,%2
! 2756: stu %3,%2(%0)")
1.1 root 2757:
2758: (define_insn ""
1.1.1.3 root 2759: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
2760: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2761: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 root 2762: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2763: (plus:SI (match_dup 1) (match_dup 2)))]
2764: ""
2765: "@
1.1.1.4 ! root 2766: lhzux %3,%0,%2
! 2767: lhzu %3,%2(%0)"
1.1 root 2768: [(set_attr "type" "load,load")])
2769:
2770: (define_insn ""
1.1.1.3 root 2771: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2772: (zero_extend:SI
1.1.1.3 root 2773: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2774: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 root 2775: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2776: (plus:SI (match_dup 1) (match_dup 2)))]
2777: ""
2778: "@
1.1.1.4 ! root 2779: lhzux %3,%0,%2
! 2780: lhzu %3,%2(%0)"
1.1 root 2781: [(set_attr "type" "load,load")])
2782:
2783: (define_insn ""
1.1.1.3 root 2784: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2785: (sign_extend:SI
1.1.1.3 root 2786: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2787: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 root 2788: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2789: (plus:SI (match_dup 1) (match_dup 2)))]
2790: ""
2791: "@
1.1.1.4 ! root 2792: lhaux %3,%0,%2
! 2793: lhau %3,%2(%0)"
1.1 root 2794: [(set_attr "type" "load,load")])
2795:
2796: (define_insn ""
1.1.1.3 root 2797: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2798: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 root 2799: (match_operand:HI 3 "gpc_reg_operand" "r,r"))
2800: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2801: (plus:SI (match_dup 1) (match_dup 2)))]
2802: ""
2803: "@
1.1.1.4 ! root 2804: sthux %3,%0,%2
! 2805: sthu %3,%2(%0)"
1.1 root 2806: [(set_attr "type" "load,load")])
2807:
2808: (define_insn ""
1.1.1.3 root 2809: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
2810: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2811: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 root 2812: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2813: (plus:SI (match_dup 1) (match_dup 2)))]
2814: ""
2815: "@
1.1.1.4 ! root 2816: lbzux %3,%0,%2
! 2817: lbzu %3,%2(%0)"
1.1 root 2818: [(set_attr "type" "load,load")])
2819:
2820: (define_insn ""
1.1.1.3 root 2821: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1.1 root 2822: (zero_extend:SI
1.1.1.3 root 2823: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2824: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
1.1.1.3 root 2825: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2826: (plus:SI (match_dup 1) (match_dup 2)))]
2827: ""
2828: "@
1.1.1.4 ! root 2829: lbzux %3,%0,%2
! 2830: lbzu %3,%2(%0)"
1.1 root 2831: [(set_attr "type" "load,load")])
2832:
2833: (define_insn ""
1.1.1.3 root 2834: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2835: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 root 2836: (match_operand:QI 3 "gpc_reg_operand" "r,r"))
2837: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2838: (plus:SI (match_dup 1) (match_dup 2)))]
2839: ""
2840: "@
1.1.1.4 ! root 2841: stbux %3,%0,%2
! 2842: stbu %3,%2(%0)")
1.1 root 2843:
2844: (define_insn ""
1.1.1.3 root 2845: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
2846: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2847: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 root 2848: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2849: (plus:SI (match_dup 1) (match_dup 2)))]
2850: ""
2851: "@
1.1.1.4 ! root 2852: lfsux %3,%0,%2
! 2853: lfsu %3,%2(%0)"
1.1 root 2854: [(set_attr "type" "load,load")])
2855:
2856: (define_insn ""
1.1.1.3 root 2857: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2858: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 root 2859: (match_operand:SF 3 "gpc_reg_operand" "f,f"))
2860: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2861: (plus:SI (match_dup 1) (match_dup 2)))]
2862: ""
2863: "@
1.1.1.4 ! root 2864: frsp %3,%3\;stfsux %3,%0,%2
! 2865: frsp %3,%3\;stfsu %3,%2(%0)")
1.1 root 2866:
2867: (define_insn ""
1.1.1.3 root 2868: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
2869: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2870: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
1.1.1.3 root 2871: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2872: (plus:SI (match_dup 1) (match_dup 2)))]
2873: ""
2874: "@
1.1.1.4 ! root 2875: lfdux %3,%0,%2
! 2876: lfdu %3,%2(%0)"
1.1 root 2877: [(set_attr "type" "load,load")])
2878:
2879: (define_insn ""
1.1.1.3 root 2880: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1.1 root 2881: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1.1.1.3 root 2882: (match_operand:DF 3 "gpc_reg_operand" "f,f"))
2883: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1.1 root 2884: (plus:SI (match_dup 1) (match_dup 2)))]
2885: ""
2886: "@
1.1.1.4 ! root 2887: stfdux %3,%0,%2
! 2888: stfdu %3,%2(%0)")
1.1 root 2889:
2890: ;; Next come insns related to the calling sequence.
2891: ;;
2892: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
1.1.1.3 root 2893: ;; We move the back-chain and decrement the stack pointer.
1.1 root 2894:
2895: (define_expand "allocate_stack"
2896: [(set (reg:SI 1)
1.1.1.4 ! root 2897: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
1.1 root 2898: ""
2899: "
2900: { rtx chain = gen_reg_rtx (SImode);
2901: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2902:
2903: emit_move_insn (chain, stack_bot);
2904: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2905: emit_move_insn (stack_bot, chain);
2906: DONE;
2907: }")
1.1.1.3 root 2908:
2909: ;; These patterns say how to save and restore the stack pointer. We need not
2910: ;; save the stack pointer at function level since we are careful to
2911: ;; preserve the backchain. At block level, we have to restore the backchain
2912: ;; when we restore the stack pointer.
2913: ;;
2914: ;; For nonlocal gotos, we must save both the stack pointer and its
2915: ;; backchain and restore both. Note that in the nonlocal case, the
2916: ;; save area is a memory location.
2917:
2918: (define_expand "save_stack_function"
2919: [(use (const_int 0))]
2920: ""
2921: "")
2922:
2923: (define_expand "restore_stack_function"
2924: [(use (const_int 0))]
2925: ""
2926: "")
2927:
2928: (define_expand "restore_stack_block"
2929: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
2930: (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
2931: (set (mem:SI (match_dup 0)) (match_dup 2))]
2932: ""
2933: "
2934: { operands[2] = gen_reg_rtx (SImode); }")
2935:
2936: (define_expand "save_stack_nonlocal"
2937: [(match_operand:DI 0 "memory_operand" "")
2938: (match_operand:SI 1 "register_operand" "")]
2939: ""
2940: "
2941: {
2942: rtx temp = gen_reg_rtx (SImode);
2943:
2944: /* Copy the backchain to the first word, sp to the second. */
2945: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
2946: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
2947: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
2948: DONE;
2949: }")
2950:
2951: (define_expand "restore_stack_nonlocal"
2952: [(match_operand:SI 0 "register_operand" "")
2953: (match_operand:DI 1 "memory_operand" "")]
2954: ""
2955: "
2956: {
2957: rtx temp = gen_reg_rtx (SImode);
2958:
2959: /* Restore the backchain from the first word, sp from the second. */
2960: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
2961: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
2962: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
2963: DONE;
2964: }")
1.1 root 2965:
2966: ;; A function pointer is a pointer to a data area whose first word contains
2967: ;; the actual address of the function, whose second word contains a pointer
2968: ;; to its TOC, and whose third word contains a value to place in the static
2969: ;; chain register (r11). Note that if we load the static chain, our
2970: ;; "trampoline" need not have any executable code.
2971: ;;
2972: ;; operands[0] is an SImode pseudo in which we place the address of the
2973: ;; function.
2974: ;; operands[1] is the address of data area of the function to call
2975:
2976: (define_expand "call_via_ptr"
1.1.1.3 root 2977: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2978: (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
1.1 root 2979: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2980: (reg:SI 2))
2981: (set (reg:SI 2)
2982: (mem:SI (plus:SI (match_dup 1)
2983: (const_int 4))))
2984: (set (reg:SI 11)
2985: (mem:SI (plus:SI (match_dup 1)
2986: (const_int 8))))
2987: (use (reg:SI 2))
2988: (use (reg:SI 11))]
2989: ""
2990: "")
2991:
2992: (define_expand "call"
2993: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2994: (match_operand 1 "" ""))
2995: (clobber (scratch:SI))])]
2996: ""
2997: "
2998: {
2999: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
3000: abort ();
3001:
3002: operands[0] = XEXP (operands[0], 0);
3003: if (GET_CODE (operands[0]) != SYMBOL_REF)
3004: {
3005: rtx temp = gen_reg_rtx (SImode);
3006:
3007: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
3008: operands[0] = temp;
3009: }
3010: }")
3011:
3012: (define_expand "call_value"
3013: [(parallel [(set (match_operand 0 "" "")
3014: (call (mem:SI (match_operand:SI 1 "address_operand" ""))
3015: (match_operand 2 "" "")))
3016: (clobber (scratch:SI))])]
3017: ""
3018: "
3019: {
3020: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
3021: abort ();
3022:
3023: operands[1] = XEXP (operands[1], 0);
3024: if (GET_CODE (operands[1]) != SYMBOL_REF)
3025: {
3026: rtx temp = gen_reg_rtx (SImode);
3027:
3028: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
3029: operands[1] = temp;
3030: }
3031: }")
3032:
3033: (define_insn ""
3034: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
3035: (match_operand 1 "" "fg,fg"))
1.1.1.3 root 3036: (clobber (match_scratch:SI 2 "=l,l"))]
1.1 root 3037: ""
3038: "@
3039: brl\;l 2,20(1)
3040: bl %z0\;cror 15,15,15")
3041:
3042: (define_insn ""
1.1.1.4 ! root 3043: [(set (match_operand 0 "" "=fg,fg")
1.1 root 3044: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
3045: (match_operand 2 "" "fg,fg")))
3046: (clobber (match_scratch:SI 3 "=l,l"))]
3047: ""
3048: "@
3049: brl\;l 2,20(1)
3050: bl %z1\;cror 15,15,15")
3051:
3052: ;; Compare insns are next. Note that the RS/6000 has two types of compares,
3053: ;; signed & unsigned, and one type of branch.
3054: ;;
3055: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3056: ;; insns, and branches. We store the operands of compares until we see
3057: ;; how it is used.
3058: (define_expand "cmpsi"
3059: [(set (cc0)
1.1.1.3 root 3060: (compare (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3061: (match_operand:SI 1 "reg_or_short_operand" "")))]
3062: ""
3063: "
3064: {
3065: /* Take care of the possibility that operands[1] might be negative but
3066: this might be a logical operation. That insn doesn't exist. */
3067: if (GET_CODE (operands[1]) == CONST_INT
3068: && INTVAL (operands[1]) < 0)
3069: operands[1] = force_reg (SImode, operands[1]);
3070:
3071: rs6000_compare_op0 = operands[0];
3072: rs6000_compare_op1 = operands[1];
3073: rs6000_compare_fp_p = 0;
3074: DONE;
3075: }")
3076:
3077: (define_expand "cmpsf"
1.1.1.3 root 3078: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
3079: (match_operand:SF 1 "gpc_reg_operand" "")))]
1.1 root 3080: ""
3081: "
3082: {
3083: rs6000_compare_op0 = operands[0];
3084: rs6000_compare_op1 = operands[1];
3085: rs6000_compare_fp_p = 1;
3086: DONE;
3087: }")
3088:
3089: (define_expand "cmpdf"
1.1.1.3 root 3090: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
3091: (match_operand:DF 1 "gpc_reg_operand" "")))]
1.1 root 3092: ""
3093: "
3094: {
3095: rs6000_compare_op0 = operands[0];
3096: rs6000_compare_op1 = operands[1];
3097: rs6000_compare_fp_p = 1;
3098: DONE;
3099: }")
3100:
3101: (define_expand "beq"
3102: [(set (match_dup 2) (match_dup 1))
3103: (set (pc)
3104: (if_then_else (eq (match_dup 2)
3105: (const_int 0))
3106: (label_ref (match_operand 0 "" ""))
3107: (pc)))]
3108: ""
3109: "
3110: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3111: operands[1] = gen_rtx (COMPARE, mode,
3112: rs6000_compare_op0, rs6000_compare_op1);
3113: operands[2] = gen_reg_rtx (mode);
3114: }")
3115:
3116: (define_expand "bne"
3117: [(set (match_dup 2) (match_dup 1))
3118: (set (pc)
3119: (if_then_else (ne (match_dup 2)
3120: (const_int 0))
3121: (label_ref (match_operand 0 "" ""))
3122: (pc)))]
3123: ""
3124: "
3125: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3126: operands[1] = gen_rtx (COMPARE, mode,
3127: rs6000_compare_op0, rs6000_compare_op1);
3128: operands[2] = gen_reg_rtx (mode);
3129: }")
3130:
3131: (define_expand "blt"
3132: [(set (match_dup 2) (match_dup 1))
3133: (set (pc)
3134: (if_then_else (lt (match_dup 2)
3135: (const_int 0))
3136: (label_ref (match_operand 0 "" ""))
3137: (pc)))]
3138: ""
3139: "
3140: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3141: operands[1] = gen_rtx (COMPARE, mode,
3142: rs6000_compare_op0, rs6000_compare_op1);
3143: operands[2] = gen_reg_rtx (mode);
3144: }")
3145:
3146: (define_expand "bgt"
3147: [(set (match_dup 2) (match_dup 1))
3148: (set (pc)
3149: (if_then_else (gt (match_dup 2)
3150: (const_int 0))
3151: (label_ref (match_operand 0 "" ""))
3152: (pc)))]
3153: ""
3154: "
3155: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3156: operands[1] = gen_rtx (COMPARE, mode,
3157: rs6000_compare_op0, rs6000_compare_op1);
3158: operands[2] = gen_reg_rtx (mode);
3159: }")
3160:
3161: (define_expand "ble"
3162: [(set (match_dup 2) (match_dup 1))
3163: (set (pc)
3164: (if_then_else (le (match_dup 2)
3165: (const_int 0))
3166: (label_ref (match_operand 0 "" ""))
3167: (pc)))]
3168: ""
3169: "
3170: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3171: operands[1] = gen_rtx (COMPARE, mode,
3172: rs6000_compare_op0, rs6000_compare_op1);
3173: operands[2] = gen_reg_rtx (mode);
3174: }")
3175:
3176: (define_expand "bge"
3177: [(set (match_dup 2) (match_dup 1))
3178: (set (pc)
3179: (if_then_else (ge (match_dup 2)
3180: (const_int 0))
3181: (label_ref (match_operand 0 "" ""))
3182: (pc)))]
3183: ""
3184: "
3185: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3186: operands[1] = gen_rtx (COMPARE, mode,
3187: rs6000_compare_op0, rs6000_compare_op1);
3188: operands[2] = gen_reg_rtx (mode);
3189: }")
3190:
3191: (define_expand "bgtu"
3192: [(set (match_dup 2) (match_dup 1))
3193: (set (pc)
3194: (if_then_else (gtu (match_dup 2)
3195: (const_int 0))
3196: (label_ref (match_operand 0 "" ""))
3197: (pc)))]
3198: ""
3199: "
3200: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3201: rs6000_compare_op0, rs6000_compare_op1);
3202: operands[2] = gen_reg_rtx (CCUNSmode);
3203: }")
3204:
3205: (define_expand "bltu"
3206: [(set (match_dup 2) (match_dup 1))
3207: (set (pc)
3208: (if_then_else (ltu (match_dup 2)
3209: (const_int 0))
3210: (label_ref (match_operand 0 "" ""))
3211: (pc)))]
3212: ""
3213: "
3214: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3215: rs6000_compare_op0, rs6000_compare_op1);
3216: operands[2] = gen_reg_rtx (CCUNSmode);
3217: }")
3218:
3219: (define_expand "bgeu"
3220: [(set (match_dup 2) (match_dup 1))
3221: (set (pc)
3222: (if_then_else (geu (match_dup 2)
3223: (const_int 0))
3224: (label_ref (match_operand 0 "" ""))
3225: (pc)))]
3226: ""
3227: "
3228: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3229: rs6000_compare_op0, rs6000_compare_op1);
3230: operands[2] = gen_reg_rtx (CCUNSmode);
3231: }")
3232:
3233: (define_expand "bleu"
3234: [(set (match_dup 2) (match_dup 1))
3235: (set (pc)
3236: (if_then_else (leu (match_dup 2)
3237: (const_int 0))
3238: (label_ref (match_operand 0 "" ""))
3239: (pc)))]
3240: ""
3241: "
3242: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3243: rs6000_compare_op0, rs6000_compare_op1);
3244: operands[2] = gen_reg_rtx (CCUNSmode);
3245: }")
3246:
3247: ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3248: ;; For SEQ, likewise, except that comparisons with zero should be done
3249: ;; with an scc insns. However, due to the order that combine see the
3250: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3251: ;; the cases we don't want to handle.
3252: (define_expand "seq"
3253: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3254: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3255: (eq:SI (match_dup 2) (const_int 0)))]
3256: ""
3257: "
3258: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3259: operands[1] = gen_rtx (COMPARE, mode,
3260: rs6000_compare_op0, rs6000_compare_op1);
3261: operands[2] = gen_reg_rtx (mode);
3262: }")
3263:
3264: (define_expand "sne"
3265: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3266: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3267: (ne:SI (match_dup 2) (const_int 0)))]
3268: ""
3269: "
3270: { if (! rs6000_compare_fp_p)
3271: FAIL;
3272:
3273: operands[1] = gen_rtx (COMPARE, CCFPmode,
3274: rs6000_compare_op0, rs6000_compare_op1);
3275: operands[2] = gen_reg_rtx (CCFPmode);
3276: }")
3277:
3278: ;; A > 0 is best done using the portable sequence, so fail in that case.
3279: (define_expand "sgt"
3280: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3281: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3282: (gt:SI (match_dup 2) (const_int 0)))]
3283: ""
3284: "
3285: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3286:
3287: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3288: FAIL;
3289:
3290: operands[1] = gen_rtx (COMPARE, mode,
3291: rs6000_compare_op0, rs6000_compare_op1);
3292: operands[2] = gen_reg_rtx (mode);
3293: }")
3294:
3295: ;; A < 0 is best done in the portable way for A an integer.
3296: (define_expand "slt"
3297: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3298: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3299: (lt:SI (match_dup 2) (const_int 0)))]
3300: ""
3301: "
3302: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3303:
3304: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3305: FAIL;
3306:
3307: operands[1] = gen_rtx (COMPARE, mode,
3308: rs6000_compare_op0, rs6000_compare_op1);
3309: operands[2] = gen_reg_rtx (mode);
3310: }")
3311:
3312: (define_expand "sge"
3313: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3314: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3315: (ge:SI (match_dup 2) (const_int 0)))]
3316: ""
3317: "
3318: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3319: operands[1] = gen_rtx (COMPARE, mode,
3320: rs6000_compare_op0, rs6000_compare_op1);
3321: operands[2] = gen_reg_rtx (mode);
3322: }")
3323:
3324: ;; A <= 0 is best done the portable way for A an integer.
3325: (define_expand "sle"
3326: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3327: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3328: (le:SI (match_dup 2) (const_int 0)))]
3329: ""
3330: "
3331: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3332:
3333: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3334: FAIL;
3335:
3336: operands[1] = gen_rtx (COMPARE, mode,
3337: rs6000_compare_op0, rs6000_compare_op1);
3338: operands[2] = gen_reg_rtx (mode);
3339: }")
3340:
3341: (define_expand "sgtu"
3342: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3343: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3344: (gtu:SI (match_dup 2) (const_int 0)))]
3345: ""
3346: "
3347: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3348: rs6000_compare_op0, rs6000_compare_op1);
3349: operands[2] = gen_reg_rtx (CCUNSmode);
3350: }")
3351:
3352: (define_expand "sltu"
3353: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3354: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3355: (ltu:SI (match_dup 2) (const_int 0)))]
3356: ""
3357: "
3358: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3359: rs6000_compare_op0, rs6000_compare_op1);
3360: operands[2] = gen_reg_rtx (CCUNSmode);
3361: }")
3362:
3363: (define_expand "sgeu"
3364: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3365: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3366: (geu:SI (match_dup 2) (const_int 0)))]
3367: ""
3368: "
3369: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3370: rs6000_compare_op0, rs6000_compare_op1);
3371: operands[2] = gen_reg_rtx (CCUNSmode);
3372: }")
3373:
3374: (define_expand "sleu"
3375: [(set (match_dup 2) (match_dup 1))
1.1.1.3 root 3376: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3377: (leu:SI (match_dup 2) (const_int 0)))]
3378: ""
3379: "
3380: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3381: rs6000_compare_op0, rs6000_compare_op1);
3382: operands[2] = gen_reg_rtx (CCUNSmode);
3383: }")
3384:
3385: ;; Here are the actual compare insns.
3386: (define_insn ""
3387: [(set (match_operand:CC 0 "cc_reg_operand" "=y")
1.1.1.3 root 3388: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3389: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3390: ""
3391: "cmp%I2 %0,%1,%2"
3392: [(set_attr "type" "compare")])
3393:
1.1.1.3 root 3394: ;; If we are comparing a register for equality with a large constant,
3395: ;; we can do this with an XOR followed by a compare. But we need a scratch
3396: ;; register for the result of the XOR.
3397:
3398: (define_split
3399: [(set (match_operand:CC 0 "cc_reg_operand" "")
3400: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
3401: (match_operand:SI 2 "non_short_cint_operand" "")))
3402: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
3403: "find_single_use (operands[0], insn, 0)
3404: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3405: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3406: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3407: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3408: "
3409: {
3410: /* Get the constant we are comparing against, C, and see what it looks like
3411: sign-extended to 16 bits. Then see what constant could be XOR'ed
3412: with C to get the sign-extended value. */
3413:
3414: int c = INTVAL (operands[2]);
3415: int sextc = (c << 16) >> 16;
3416: int xorv = c ^ sextc;
3417:
3418: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
3419: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
3420: }")
3421:
1.1 root 3422: (define_insn ""
3423: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
1.1.1.3 root 3424: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3425: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3426: ""
3427: "cmpl%I2 %0,%1,%W2"
3428: [(set_attr "type" "compare")])
3429:
3430: ;; The following two insns don't exist as single insns, but if we provide
3431: ;; them, we can swap an add and compare, which will enable us to overlap more
3432: ;; of the required delay between a compare and branch. We generate code for
3433: ;; them by splitting.
3434:
3435: (define_insn ""
3436: [(set (match_operand:CC 3 "cc_reg_operand" "=y")
1.1.1.3 root 3437: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3438: (match_operand:SI 2 "short_cint_operand" "i")))
1.1.1.3 root 3439: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3440: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3441: ""
3442: "#")
3443:
3444: (define_insn ""
3445: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
1.1.1.3 root 3446: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3447: (match_operand:SI 2 "u_short_cint_operand" "i")))
1.1.1.3 root 3448: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3449: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3450: ""
3451: "#")
3452:
3453: (define_split
3454: [(set (match_operand:CC 3 "cc_reg_operand" "")
1.1.1.3 root 3455: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 3456: (match_operand:SI 2 "short_cint_operand" "")))
1.1.1.3 root 3457: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3458: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3459: ""
3460: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3461: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3462:
3463: (define_split
3464: [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
1.1.1.3 root 3465: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 3466: (match_operand:SI 2 "u_short_cint_operand" "")))
1.1.1.3 root 3467: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 3468: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3469: ""
3470: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3471: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3472:
3473: (define_insn ""
3474: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
1.1.1.3 root 3475: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
3476: (match_operand:SF 2 "gpc_reg_operand" "f")))]
1.1 root 3477: ""
3478: "fcmpu %0,%1,%2"
3479: [(set_attr "type" "fpcompare")])
3480:
3481: (define_insn ""
3482: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
1.1.1.3 root 3483: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
3484: (match_operand:DF 2 "gpc_reg_operand" "f")))]
1.1 root 3485: ""
3486: "fcmpu %0,%1,%2"
3487: [(set_attr "type" "fpcompare")])
3488:
3489: ;; Now we have the scc insns. We can do some combinations because of the
3490: ;; way the machine works.
3491: ;;
3492: ;; Note that this is probably faster if we can put an insn between the
1.1.1.3 root 3493: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
3494: ;; cases the insns below which don't use an intermediate CR field will
3495: ;; be used instead.
1.1 root 3496: (define_insn ""
1.1.1.3 root 3497: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3498: (match_operator:SI 1 "scc_comparison_operator"
3499: [(match_operand 2 "cc_reg_operand" "y")
3500: (const_int 0)]))]
3501: ""
3502: "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3503:
3504: (define_insn ""
3505: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3506: (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3507: [(match_operand 2 "cc_reg_operand" "y")
3508: (const_int 0)])
3509: (const_int 0)))
1.1.1.3 root 3510: (set (match_operand:SI 3 "gpc_reg_operand" "=r")
1.1 root 3511: (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3512: ""
3513: "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3514: [(set_attr "type" "delayed_compare")])
3515:
3516: (define_insn ""
1.1.1.3 root 3517: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3518: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3519: [(match_operand 2 "cc_reg_operand" "y")
3520: (const_int 0)])
3521: (match_operand:SI 3 "const_int_operand" "n")))]
3522: ""
3523: "*
3524: {
3525: int is_bit = ccr_bit (operands[1], 1);
3526: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3527: int count;
3528:
3529: if (is_bit >= put_bit)
3530: count = is_bit - put_bit;
3531: else
3532: count = 32 - (put_bit - is_bit);
3533:
3534: operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3535: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3536:
3537: return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3538: }")
3539:
3540: (define_insn ""
3541: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3542: (compare:CC
3543: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3544: [(match_operand 2 "cc_reg_operand" "y")
3545: (const_int 0)])
3546: (match_operand:SI 3 "const_int_operand" "n"))
3547: (const_int 0)))
1.1.1.3 root 3548: (set (match_operand:SI 4 "gpc_reg_operand" "=r")
1.1 root 3549: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3550: (match_dup 3)))]
3551: ""
3552: "*
3553: {
3554: int is_bit = ccr_bit (operands[1], 1);
3555: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3556: int count;
3557:
3558: if (is_bit >= put_bit)
3559: count = is_bit - put_bit;
3560: else
3561: count = 32 - (put_bit - is_bit);
3562:
3563: operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3564: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3565:
3566: return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3567: }"
3568: [(set_attr "type" "delayed_compare")])
3569:
1.1.1.3 root 3570: ;; If we are comparing the result of two comparisons, this can be done
3571: ;; using creqv or crxor.
3572:
3573: (define_insn ""
3574: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
3575: (compare:CCEQ (match_operator 1 "scc_comparison_operator"
3576: [(match_operand 2 "cc_reg_operand" "y")
3577: (const_int 0)])
3578: (match_operator 3 "scc_comparison_operator"
3579: [(match_operand 4 "cc_reg_operand" "y")
3580: (const_int 0)])))]
3581: "REGNO (operands[2]) != REGNO (operands[4])"
3582: "*
3583: {
3584: enum rtx_code code1, code2;
3585:
3586: code1 = GET_CODE (operands[1]);
3587: code2 = GET_CODE (operands[3]);
3588:
3589: if ((code1 == EQ || code1 == LT || code1 == GT
3590: || code1 == LTU || code1 == GTU
3591: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
3592: !=
3593: (code2 == EQ || code2 == LT || code2 == GT
3594: || code2 == LTU || code2 == GTU
3595: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
3596: return \"%C1%C3crxor %E0,%j1,%j3\";
3597: else
3598: return \"%C1%C3creqv %E0,%j1,%j3\";
3599: }")
3600:
3601: ;; There is a 3 cycle delay between consecutive mfcr instructions
3602: ;; so it is useful to combine 2 scc instructions to use only one mfcr.
3603:
3604: (define_peephole
3605: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3606: (match_operator:SI 1 "scc_comparison_operator"
3607: [(match_operand 2 "cc_reg_operand" "y")
3608: (const_int 0)]))
3609: (set (match_operand:SI 3 "gpc_reg_operand" "=r")
3610: (match_operator:SI 4 "scc_comparison_operator"
3611: [(match_operand 5 "cc_reg_operand" "y")
3612: (const_int 0)]))]
3613: "REGNO (operands[2]) != REGNO (operands[5])"
3614: "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
3615:
1.1 root 3616: ;; There are some scc insns that can be done directly, without a compare.
3617: ;; These are faster because they don't involve the communications between
3618: ;; the FXU and branch units. In fact, we will be replacing all of the
3619: ;; integer scc insns here or in the portable methods in emit_store_flag.
3620: ;;
3621: ;; Also support (neg (scc ..)) since that construct is used to replace
3622: ;; branches, (plus (scc ..) ..) since that construct is common and
3623: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3624: ;; cases where it is no more expensive than (neg (scc ..)).
3625:
3626: ;; Have reload force a constant into a register for the simple insns that
3627: ;; otherwise won't accept constants. We do this because it is faster than
3628: ;; the cmp/mfcr sequence we would otherwise generate.
3629:
3630: (define_insn ""
1.1.1.3 root 3631: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3632: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3633: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3634: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3635: ""
3636: "@
3637: xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3638: sfi %3,%1,0\;ae %0,%3,%1
3639: xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3640: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3641: sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3642:
3643: (define_insn ""
3644: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3645: (compare:CC
1.1.1.3 root 3646: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3647: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3648: (const_int 0)))
1.1.1.3 root 3649: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1.1 root 3650: (eq:SI (match_dup 1) (match_dup 2)))
3651: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3652: ""
3653: "@
3654: xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3655: sfi %3,%1,0\;ae. %0,%3,%1
3656: xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3657: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3658: sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3659: [(set_attr "type" "compare")])
3660:
3661: (define_insn ""
1.1.1.3 root 3662: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3663: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3664: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 root 3665: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
1.1 root 3666: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3667: ""
3668: "@
3669: xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3670: sfi %4,%1,0\;aze %0,%3
3671: xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3672: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3673: sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3674:
3675: (define_insn ""
3676: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3677: (compare:CC
3678: (plus:SI
1.1.1.3 root 3679: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3680: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 root 3681: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1.1 root 3682: (const_int 0)))
3683: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3684: ""
3685: "@
3686: xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3687: sfi %4,%1,0\;aze. %0,%3
3688: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3689: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3690: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3691: [(set_attr "type" "compare")])
3692:
3693: (define_insn ""
3694: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3695: (compare:CC
3696: (plus:SI
1.1.1.3 root 3697: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1.1 root 3698: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
1.1.1.3 root 3699: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1.1 root 3700: (const_int 0)))
1.1.1.3 root 3701: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1.1 root 3702: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3703: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3704: ""
3705: "@
3706: xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3707: sfi %4,%1,0\;aze. %4,%3
3708: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3709: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3710: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3711: [(set_attr "type" "compare")])
3712:
3713: (define_insn ""
1.1.1.3 root 3714: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3715: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
1.1 root 3716: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3717: ""
3718: "@
3719: xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3720: ai %0,%1,-1\;sfe %0,%0,%0
3721: xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3722: xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3723: sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3724:
3725: ;; This is what (plus (ne X (const_int 0)) Y) looks like.
3726: (define_insn ""
1.1.1.3 root 3727: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3728: (plus:SI (lshiftrt:SI
1.1.1.3 root 3729: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3730: (const_int 31))
1.1.1.3 root 3731: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 3732: (clobber (match_scratch:SI 3 "=&r"))]
3733: ""
3734: "ai %3,%1,-1\;aze %0,%2")
3735:
3736: (define_insn ""
3737: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3738: (compare:CC
3739: (plus:SI (lshiftrt:SI
1.1.1.3 root 3740: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3741: (const_int 31))
1.1.1.3 root 3742: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 3743: (const_int 0)))
3744: (clobber (match_scratch:SI 3 "=&r"))]
3745: ""
3746: "ai %3,%1,-1\;aze. %3,%2"
3747: [(set_attr "type" "compare")])
3748:
3749: (define_insn ""
3750: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3751: (compare:CC
3752: (plus:SI (lshiftrt:SI
1.1.1.3 root 3753: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1.1 root 3754: (const_int 31))
1.1.1.3 root 3755: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 3756: (const_int 0)))
1.1.1.3 root 3757: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3758: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3759: (match_dup 2)))
3760: (clobber (match_scratch:SI 3 "=&r"))]
3761: ""
3762: "ai %3,%1,-1\;aze. %0,%2"
3763: [(set_attr "type" "compare")])
3764:
3765: (define_insn ""
1.1.1.3 root 3766: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3767: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3768: (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3769: (clobber (match_scratch:SI 3 "=r,X"))]
3770: ""
3771: "@
3772: doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3773: ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3774:
3775: (define_insn ""
3776: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3777: (compare:CC
1.1.1.3 root 3778: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3779: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3780: (const_int 0)))
1.1.1.3 root 3781: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 3782: (le:SI (match_dup 1) (match_dup 2)))
3783: (clobber (match_scratch:SI 3 "=r,X"))]
3784: ""
3785: "@
3786: doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3787: ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3788: [(set_attr "type" "delayed_compare,compare")])
3789:
3790: (define_insn ""
1.1.1.3 root 3791: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3792: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3793: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 root 3794: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 3795: (clobber (match_scratch:SI 4 "=&r,&r"))]
3796: ""
3797: "@
3798: doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3799: srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3800:
3801: (define_insn ""
3802: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3803: (compare:CC
1.1.1.3 root 3804: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3805: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 root 3806: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 3807: (const_int 0)))
3808: (clobber (match_scratch:SI 4 "=&r,&r"))]
3809: ""
3810: "@
3811: doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3812: srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3813: [(set_attr "type" "compare")])
3814:
3815: (define_insn ""
3816: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3817: (compare:CC
1.1.1.3 root 3818: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3819: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
1.1.1.3 root 3820: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 3821: (const_int 0)))
1.1.1.3 root 3822: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 3823: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3824: (clobber (match_scratch:SI 4 "=&r,&r"))]
3825: ""
3826: "@
3827: doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3828: srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3829: [(set_attr "type" "compare")])
3830:
3831: (define_insn ""
1.1.1.3 root 3832: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3833: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 3834: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3835: ""
3836: "@
3837: doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3838: ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3839:
3840: (define_insn ""
1.1.1.3 root 3841: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3842: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3843: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3844: ""
3845: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3846:
3847: (define_insn ""
3848: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3849: (compare:CC
1.1.1.3 root 3850: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3851: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3852: (const_int 0)))
1.1.1.3 root 3853: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3854: (leu:SI (match_dup 1) (match_dup 2)))]
3855: ""
3856: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3857: [(set_attr "type" "compare")])
3858:
3859: (define_insn ""
1.1.1.3 root 3860: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3861: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3862: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3863: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3864: (clobber (match_scratch:SI 4 "=&r"))]
3865: ""
3866: "sf%I2 %4,%1,%2\;aze %0,%3")
3867:
3868: (define_insn ""
3869: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3870: (compare:CC
1.1.1.3 root 3871: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3872: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3873: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3874: (const_int 0)))
3875: (clobber (match_scratch:SI 4 "=&r"))]
3876: ""
3877: "sf%I2 %4,%1,%2\;aze. %4,%3"
3878: [(set_attr "type" "compare")])
3879:
3880: (define_insn ""
3881: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3882: (compare:CC
1.1.1.3 root 3883: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3884: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3885: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3886: (const_int 0)))
1.1.1.3 root 3887: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3888: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3889: (clobber (match_scratch:SI 4 "=&r"))]
3890: ""
3891: "sf%I2 %4,%1,%2\;aze. %0,%3"
3892: [(set_attr "type" "compare")])
3893:
3894: (define_insn ""
1.1.1.3 root 3895: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3896: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3897: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3898: ""
3899: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3900:
3901: (define_insn ""
1.1.1.3 root 3902: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3903: (and:SI (neg:SI
1.1.1.3 root 3904: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3905: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 root 3906: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3907: (clobber (match_scratch:SI 4 "=&r"))]
3908: ""
3909: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3910:
3911: (define_insn ""
3912: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3913: (compare:CC
3914: (and:SI (neg:SI
1.1.1.3 root 3915: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3916: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 root 3917: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3918: (const_int 0)))
3919: (clobber (match_scratch:SI 4 "=&r"))]
3920: ""
3921: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3922: [(set_attr "type" "compare")])
3923:
3924: (define_insn ""
3925: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3926: (compare:CC
3927: (and:SI (neg:SI
1.1.1.3 root 3928: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3929: (match_operand:SI 2 "reg_or_short_operand" "rI")))
1.1.1.3 root 3930: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3931: (const_int 0)))
1.1.1.3 root 3932: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3933: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3934: (clobber (match_scratch:SI 4 "=&r"))]
3935: ""
3936: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3937: [(set_attr "type" "compare")])
3938:
3939: (define_insn ""
1.1.1.3 root 3940: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3941: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3942: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3943: ""
3944: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3945:
3946: (define_insn ""
3947: [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3948: (compare:CC
1.1.1.3 root 3949: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3950: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3951: (const_int 0)))
1.1.1.3 root 3952: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3953: (lt:SI (match_dup 1) (match_dup 2)))]
3954: ""
3955: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3956: [(set_attr "type" "delayed_compare")])
3957:
3958: (define_insn ""
1.1.1.3 root 3959: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3960: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3961: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3962: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 3963: (clobber (match_scratch:SI 4 "=&r"))]
3964: ""
3965: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3966:
3967: (define_insn ""
3968: [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3969: (compare:CC
1.1.1.3 root 3970: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3971: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3972: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3973: (const_int 0)))
3974: (clobber (match_scratch:SI 4 "=&r"))]
3975: ""
3976: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3977: [(set_attr "type" "compare")])
3978:
3979: (define_insn ""
3980: [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3981: (compare:CC
1.1.1.3 root 3982: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3983: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 3984: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 3985: (const_int 0)))
1.1.1.3 root 3986: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 3987: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3988: (clobber (match_scratch:SI 4 "=&r"))]
3989: ""
3990: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3991: [(set_attr "type" "compare")])
3992:
3993: (define_insn ""
1.1.1.3 root 3994: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3995: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 3996: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3997: ""
3998: "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3999:
4000: (define_insn ""
1.1.1.3 root 4001: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4002: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4003: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4004: ""
4005: "@
4006: sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
4007: ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
4008:
4009: (define_insn ""
4010: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4011: (compare:CC
1.1.1.3 root 4012: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4013: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4014: (const_int 0)))
1.1.1.3 root 4015: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4016: (ltu:SI (match_dup 1) (match_dup 2)))]
4017: ""
4018: "@
4019: sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
4020: ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
4021: [(set_attr "type" "compare")])
4022:
4023: (define_insn ""
1.1.1.3 root 4024: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4025: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 4026: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4027: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
4028: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4029: ""
4030: "@
4031: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4032: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4033: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
4034: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4035:
4036: (define_insn ""
4037: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
4038: (compare:CC
1.1.1.3 root 4039: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 4040: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4041: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
4042: (const_int 0)))
4043: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4044: ""
4045: "@
4046: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
4047: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
4048: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
4049: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4050: [(set_attr "type" "compare")])
4051:
4052: (define_insn ""
4053: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
4054: (compare:CC
1.1.1.3 root 4055: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1.1 root 4056: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4057: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
4058: (const_int 0)))
1.1.1.3 root 4059: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1.1 root 4060: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4061: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4062: ""
4063: "@
4064: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4065: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4066: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
4067: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4068: [(set_attr "type" "compare")])
4069:
4070: (define_insn ""
1.1.1.3 root 4071: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4072: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4073: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
4074: ""
4075: "@
4076: sf %0,%2,%1\;sfe %0,%0,%0
4077: ai %0,%1,%n2\;sfe %0,%0,%0")
4078:
4079: (define_insn ""
1.1.1.3 root 4080: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4081: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4082: (match_operand:SI 2 "reg_or_short_operand" "rI")))
4083: (clobber (match_scratch:SI 3 "=r"))]
4084: ""
4085: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
4086:
4087: (define_insn ""
4088: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4089: (compare:CC
1.1.1.3 root 4090: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4091: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4092: (const_int 0)))
1.1.1.3 root 4093: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4094: (ge:SI (match_dup 1) (match_dup 2)))
4095: (clobber (match_scratch:SI 3 "=r"))]
4096: ""
4097: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
4098: [(set_attr "type" "compare")])
4099:
4100: (define_insn ""
1.1.1.3 root 4101: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4102: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4103: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 4104: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 4105: (clobber (match_scratch:SI 4 "=&r"))]
4106: ""
4107: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
4108:
4109: (define_insn ""
4110: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4111: (compare:CC
1.1.1.3 root 4112: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4113: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 4114: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4115: (const_int 0)))
4116: (clobber (match_scratch:SI 4 "=&r"))]
4117: ""
4118: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
4119: [(set_attr "type" "compare")])
4120:
4121: (define_insn ""
4122: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4123: (compare:CC
1.1.1.3 root 4124: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4125: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1.1.3 root 4126: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4127: (const_int 0)))
1.1.1.3 root 4128: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4129: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4130: (clobber (match_scratch:SI 4 "=&r"))]
4131: ""
4132: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
4133: [(set_attr "type" "compare")])
4134:
4135: (define_insn ""
1.1.1.3 root 4136: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4137: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4138: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4139: ""
4140: "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
4141:
4142: ;; This is (and (neg (ge X (const_int 0))) Y).
4143: (define_insn ""
1.1.1.3 root 4144: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4145: (and:SI (neg:SI
4146: (lshiftrt:SI
1.1.1.3 root 4147: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4148: (const_int 31)))
1.1.1.3 root 4149: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 4150: (clobber (match_scratch:SI 3 "=&r"))]
4151: ""
4152: "srai %3,%1,31\;andc %0,%2,%3")
4153:
4154: (define_insn ""
4155: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4156: (compare:CC
4157: (and:SI (neg:SI
4158: (lshiftrt:SI
1.1.1.3 root 4159: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4160: (const_int 31)))
1.1.1.3 root 4161: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4162: (const_int 0)))
4163: (clobber (match_scratch:SI 3 "=&r"))]
4164: ""
4165: "srai %3,%1,31\;andc. %3,%2,%3"
4166: [(set_attr "type" "compare")])
4167:
4168: (define_insn ""
4169: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4170: (compare:CC
4171: (and:SI (neg:SI
4172: (lshiftrt:SI
1.1.1.3 root 4173: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1.1 root 4174: (const_int 31)))
1.1.1.3 root 4175: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4176: (const_int 0)))
1.1.1.3 root 4177: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4178: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
4179: (const_int 31)))
4180: (match_dup 2)))
4181: (clobber (match_scratch:SI 3 "=&r"))]
4182: ""
4183: "srai %3,%1,31\;andc. %0,%2,%3"
4184: [(set_attr "type" "compare")])
4185:
4186: (define_insn ""
1.1.1.3 root 4187: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4188: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4189: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4190: ""
4191: "@
4192: sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
4193: ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
4194:
4195: (define_insn ""
4196: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4197: (compare:CC
1.1.1.3 root 4198: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4199: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4200: (const_int 0)))
1.1.1.3 root 4201: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4202: (geu:SI (match_dup 1) (match_dup 2)))]
4203: ""
4204: "@
4205: sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
4206: ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
4207: [(set_attr "type" "compare")])
4208:
4209: (define_insn ""
1.1.1.3 root 4210: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4211: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4212: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 root 4213: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 4214: (clobber (match_scratch:SI 4 "=&r,&r"))]
4215: ""
4216: "@
4217: sf %4,%2,%1\;aze %0,%3
4218: ai %4,%1,%n2\;aze %0,%3")
4219:
4220: (define_insn ""
4221: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4222: (compare:CC
1.1.1.3 root 4223: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4224: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 root 4225: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4226: (const_int 0)))
4227: (clobber (match_scratch:SI 4 "=&r,&r"))]
4228: ""
4229: "@
4230: sf %4,%2,%1\;aze. %4,%3
4231: ai %4,%1,%n2\;aze. %4,%3"
4232: [(set_attr "type" "compare")])
4233:
4234: (define_insn ""
4235: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4236: (compare:CC
1.1.1.3 root 4237: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4238: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
1.1.1.3 root 4239: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4240: (const_int 0)))
1.1.1.3 root 4241: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4242: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4243: (clobber (match_scratch:SI 4 "=&r,&r"))]
4244: ""
4245: "@
4246: sf %4,%2,%1\;aze. %0,%3
4247: ai %4,%1,%n2\;aze. %4,%3"
4248: [(set_attr "type" "compare")])
4249:
4250: (define_insn ""
1.1.1.3 root 4251: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4252: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4253: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4254: ""
4255: "@
4256: sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4257: sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4258:
4259: (define_insn ""
1.1.1.3 root 4260: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4261: (and:SI (neg:SI
1.1.1.3 root 4262: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4263: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 root 4264: (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1.1 root 4265: (clobber (match_scratch:SI 4 "=&r,&r"))]
4266: ""
4267: "@
4268: sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4269: ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4270:
4271: (define_insn ""
4272: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4273: (compare:CC
4274: (and:SI (neg:SI
1.1.1.3 root 4275: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4276: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 root 4277: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4278: (const_int 0)))
4279: (clobber (match_scratch:SI 4 "=&r,&r"))]
4280: ""
4281: "@
4282: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4283: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4284: [(set_attr "type" "compare")])
4285:
4286: (define_insn ""
4287: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4288: (compare:CC
4289: (and:SI (neg:SI
1.1.1.3 root 4290: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4291: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
1.1.1.3 root 4292: (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1.1 root 4293: (const_int 0)))
1.1.1.3 root 4294: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4295: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4296: (clobber (match_scratch:SI 4 "=&r,&r"))]
4297: ""
4298: "@
4299: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4300: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4301: [(set_attr "type" "compare")])
4302:
4303: (define_insn ""
1.1.1.3 root 4304: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4305: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4306: (const_int 0)))]
4307: ""
4308: "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4309:
4310: (define_insn ""
4311: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4312: (compare:CC
1.1.1.3 root 4313: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4314: (const_int 0))
4315: (const_int 0)))
1.1.1.3 root 4316: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4317: (gt:SI (match_dup 1) (const_int 0)))]
4318: ""
4319: "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4320: [(set_attr "type" "delayed_compare")])
4321:
4322: (define_insn ""
1.1.1.3 root 4323: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4324: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4325: (match_operand:SI 2 "reg_or_short_operand" "r")))]
4326: ""
4327: "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4328:
4329: (define_insn ""
4330: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4331: (compare:CC
1.1.1.3 root 4332: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4333: (match_operand:SI 2 "reg_or_short_operand" "r"))
4334: (const_int 0)))
1.1.1.3 root 4335: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4336: (gt:SI (match_dup 1) (match_dup 2)))]
4337: ""
4338: "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4339: [(set_attr "type" "delayed_compare")])
4340:
4341: (define_insn ""
1.1.1.3 root 4342: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4343: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4344: (const_int 0))
1.1.1.3 root 4345: (match_operand:SI 2 "gpc_reg_operand" "r")))
1.1 root 4346: (clobber (match_scratch:SI 3 "=&r"))]
4347: ""
4348: "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4349:
4350: (define_insn ""
4351: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4352: (compare:CC
1.1.1.3 root 4353: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4354: (const_int 0))
1.1.1.3 root 4355: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4356: (const_int 0)))
4357: (clobber (match_scratch:SI 3 "=&r"))]
4358: ""
4359: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4360: [(set_attr "type" "compare")])
4361:
4362: (define_insn ""
4363: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4364: (compare:CC
1.1.1.3 root 4365: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4366: (const_int 0))
1.1.1.3 root 4367: (match_operand:SI 2 "gpc_reg_operand" "r"))
1.1 root 4368: (const_int 0)))
1.1.1.3 root 4369: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4370: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4371: (clobber (match_scratch:SI 3 "=&r"))]
4372: ""
4373: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4374: [(set_attr "type" "compare")])
4375:
4376: (define_insn ""
1.1.1.3 root 4377: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4378: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4379: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 root 4380: (match_operand:SI 3 "gpc_reg_operand" "r")))
1.1 root 4381: (clobber (match_scratch:SI 4 "=&r"))]
4382: ""
4383: "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4384:
4385: (define_insn ""
4386: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4387: (compare:CC
1.1.1.3 root 4388: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4389: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 root 4390: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4391: (const_int 0)))
4392: (clobber (match_scratch:SI 4 "=&r"))]
4393: ""
4394: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4395: [(set_attr "type" "compare")])
4396:
4397: (define_insn ""
4398: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4399: (compare:CC
1.1.1.3 root 4400: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4401: (match_operand:SI 2 "reg_or_short_operand" "r"))
1.1.1.3 root 4402: (match_operand:SI 3 "gpc_reg_operand" "r"))
1.1 root 4403: (const_int 0)))
1.1.1.3 root 4404: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4405: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4406: (clobber (match_scratch:SI 4 "=&r"))]
4407: ""
4408: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4409: [(set_attr "type" "compare")])
4410:
4411: (define_insn ""
1.1.1.3 root 4412: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4413: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4414: (const_int 0))))]
4415: ""
4416: "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4417:
4418: (define_insn ""
1.1.1.3 root 4419: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4420: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4421: (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4422: ""
4423: "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4424:
4425: (define_insn ""
1.1.1.3 root 4426: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4427: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4428: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4429: ""
4430: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4431:
4432: (define_insn ""
4433: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4434: (compare:CC
1.1.1.3 root 4435: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4436: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4437: (const_int 0)))
1.1.1.3 root 4438: (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1.1 root 4439: (gtu:SI (match_dup 1) (match_dup 2)))]
4440: ""
4441: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4442: [(set_attr "type" "compare")])
4443:
4444: (define_insn ""
1.1.1.3 root 4445: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4446: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4447: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4448: (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4449: (clobber (match_scratch:SI 4 "=&r,&r"))]
4450: ""
4451: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4452:
4453: (define_insn ""
4454: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4455: (compare:CC
1.1.1.3 root 4456: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4457: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4458: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4459: (const_int 0)))
4460: (clobber (match_scratch:SI 4 "=&r,&r"))]
4461: ""
4462: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4463: [(set_attr "type" "compare")])
4464:
4465: (define_insn ""
4466: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4467: (compare:CC
1.1.1.3 root 4468: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1.1 root 4469: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4470: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4471: (const_int 0)))
1.1.1.3 root 4472: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1.1 root 4473: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4474: (clobber (match_scratch:SI 4 "=&r,&r"))]
4475: ""
4476: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4477: [(set_attr "type" "compare")])
4478:
4479: (define_insn ""
1.1.1.3 root 4480: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4481: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1.1 root 4482: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4483: ""
4484: "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4485:
4486: ;; Define both directions of branch and return. If we need a reload
4487: ;; register, we'd rather use CR0 since it is much easier to copy a
4488: ;; register CC value to there.
4489:
4490: (define_insn ""
4491: [(set (pc)
4492: (if_then_else (match_operator 1 "branch_comparison_operator"
4493: [(match_operand 2
4494: "cc_reg_operand" "x,?y")
4495: (const_int 0)])
4496: (label_ref (match_operand 0 "" ""))
4497: (pc)))]
4498: ""
4499: "%C1bc %t1,%j1,%0")
4500:
4501: (define_insn ""
4502: [(set (pc)
4503: (if_then_else (match_operator 0 "branch_comparison_operator"
4504: [(match_operand 1
4505: "cc_reg_operand" "x,?y")
4506: (const_int 0)])
4507: (return)
4508: (pc)))]
4509: "direct_return ()"
4510: "%C0bcr %t0,%j0")
4511:
4512: (define_insn ""
4513: [(set (pc)
4514: (if_then_else (match_operator 1 "branch_comparison_operator"
4515: [(match_operand 2
4516: "cc_reg_operand" "x,?y")
4517: (const_int 0)])
4518: (pc)
4519: (label_ref (match_operand 0 "" ""))))]
4520: ""
4521: "%C1bc %T1,%j1,%0")
4522:
4523: (define_insn ""
4524: [(set (pc)
4525: (if_then_else (match_operator 0 "branch_comparison_operator"
4526: [(match_operand 1
4527: "cc_reg_operand" "x,?y")
4528: (const_int 0)])
4529: (pc)
4530: (return)))]
4531: "direct_return ()"
4532: "%C0bcr %T0,%j0")
4533:
4534: ;; Unconditional branch and return.
4535:
4536: (define_insn "jump"
4537: [(set (pc)
4538: (label_ref (match_operand 0 "" "")))]
4539: ""
4540: "b %l0")
4541:
4542: (define_insn "return"
4543: [(return)]
4544: "direct_return ()"
4545: "br")
4546:
4547: (define_insn "indirect_jump"
4548: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4549: ""
4550: "@
4551: bctr
4552: br")
4553:
4554: ;; Table jump for switch statements:
4555: (define_expand "tablejump"
4556: [(set (match_dup 3)
4557: (plus:SI (match_operand:SI 0 "" "")
4558: (match_dup 2)))
4559: (parallel [(set (pc) (match_dup 3))
4560: (use (label_ref (match_operand 1 "" "")))])]
4561: ""
4562: "
4563: { operands[0] = force_reg (SImode, operands[0]);
4564: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4565: operands[3] = gen_reg_rtx (SImode);
4566: }")
4567:
4568: (define_insn ""
4569: [(set (pc)
1.1.1.4 ! root 4570: (match_operand:SI 0 "register_operand" "c,l"))
1.1 root 4571: (use (label_ref (match_operand 1 "" "")))]
4572: ""
4573: "@
4574: bctr
4575: br")
4576:
4577: (define_insn "nop"
4578: [(const_int 0)]
4579: ""
4580: "cror 0,0,0")
4581:
4582: ;; Define the subtract-one-and-jump insns.
4583: ;; We need to be able to do this for any operand, including MEM, or we
4584: ;; will cause reload to blow up since we don't allow output reloads on
4585: ;; JUMP_INSNs.
4586: (define_insn ""
4587: [(set (pc)
4588: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4589: (const_int 1))
4590: (label_ref (match_operand 2 "" ""))
4591: (pc)))
4592: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4593: (plus:SI (match_dup 1) (const_int -1)))
4594: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4595: (clobber (match_scratch:SI 4 "=X,X,r"))]
4596: ""
4597: "@
4598: bdn %l2
4599: #
4600: #")
4601:
4602: ;; Similar, but we can use GE since we have a REG_NOTES.
4603: (define_insn ""
4604: [(set (pc)
4605: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4606: (const_int 0))
4607: (label_ref (match_operand 2 "" ""))
4608: (pc)))
4609: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4610: (plus:SI (match_dup 1) (const_int -1)))
4611: (clobber (match_scratch:CC 3 "=X,&x,&X"))
4612: (clobber (match_scratch:SI 4 "=X,X,r"))]
4613: "find_reg_note (insn, REG_NONNEG, 0)"
4614: "@
4615: bdn %l2
4616: #
4617: #")
4618:
4619: (define_insn ""
4620: [(set (pc)
4621: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4622: (const_int 1))
4623: (label_ref (match_operand 2 "" ""))
4624: (pc)))
4625: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4626: (plus:SI (match_dup 1) (const_int -1)))
4627: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4628: (clobber (match_scratch:SI 4 "=X,X,r"))]
4629: ""
4630: "@
4631: bdz %l2
4632: #
4633: #")
4634:
4635: (define_split
4636: [(set (pc)
4637: (if_then_else (match_operator 2 "comparison_operator"
1.1.1.3 root 4638: [(match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 4639: (const_int 1)])
4640: (match_operand 5 "" "")
4641: (match_operand 6 "" "")))
1.1.1.3 root 4642: (set (match_operand:SI 0 "gpc_reg_operand" "")
1.1 root 4643: (plus:SI (match_dup 1) (const_int -1)))
4644: (clobber (match_scratch:CC 3 ""))
4645: (clobber (match_scratch:SI 4 ""))]
4646: "reload_completed"
4647: [(parallel [(set (match_dup 3)
4648: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4649: (const_int 0)))
4650: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4651: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4652: "
4653: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4654: const0_rtx); }")
4655:
4656: (define_split
4657: [(set (pc)
4658: (if_then_else (match_operator 2 "comparison_operator"
1.1.1.3 root 4659: [(match_operand:SI 1 "gpc_reg_operand" "")
1.1 root 4660: (const_int 1)])
4661: (match_operand 5 "" "")
4662: (match_operand 6 "" "")))
4663: (set (match_operand:SI 0 "general_operand" "")
4664: (plus:SI (match_dup 1) (const_int -1)))
4665: (clobber (match_scratch:CC 3 ""))
4666: (clobber (match_scratch:SI 4 ""))]
1.1.1.3 root 4667: "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
1.1 root 4668: [(parallel [(set (match_dup 3)
4669: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4670: (const_int 0)))
4671: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4672: (set (match_dup 0) (match_dup 4))
4673: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4674: "
4675: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4676: const0_rtx); }")
4677:
4678: ;;- Local variables:
4679: ;;- mode:emacs-lisp
4680: ;;- comment-start: ";;- "
4681: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4682: ;;- eval: (modify-syntax-entry ?[ "(]")
4683: ;;- eval: (modify-syntax-entry ?] ")[")
4684: ;;- eval: (modify-syntax-entry ?{ "(}")
4685: ;;- eval: (modify-syntax-entry ?} "){")
4686: ;;- End:
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