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1.1 root 1: /* Subroutines used for code generation on IBM RS/6000. 1.1.1.4 root 2: Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1.1.3 root 3: Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: This file is part of GNU CC. 6: 7: GNU CC is free software; you can redistribute it and/or modify 8: it under the terms of the GNU General Public License as published by 9: the Free Software Foundation; either version 2, or (at your option) 10: any later version. 11: 12: GNU CC is distributed in the hope that it will be useful, 13: but WITHOUT ANY WARRANTY; without even the implied warranty of 14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: GNU General Public License for more details. 16: 17: You should have received a copy of the GNU General Public License 18: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 root 19: the Free Software Foundation, 59 Temple Place - Suite 330, 20: Boston, MA 02111-1307, USA. */ 1.1 root 21: 22: #include <stdio.h> 1.1.1.3 root 23: #include <ctype.h> 1.1 root 24: #include "config.h" 25: #include "rtl.h" 26: #include "regs.h" 27: #include "hard-reg-set.h" 28: #include "real.h" 29: #include "insn-config.h" 30: #include "conditions.h" 31: #include "insn-flags.h" 32: #include "output.h" 33: #include "insn-attr.h" 34: #include "flags.h" 35: #include "recog.h" 36: #include "expr.h" 37: #include "obstack.h" 38: #include "tree.h" 39: 40: extern char *language_string; 1.1.1.2 root 41: extern int profile_block_flag; 1.1 root 42: 43: #define min(A,B) ((A) < (B) ? (A) : (B)) 44: #define max(A,B) ((A) > (B) ? (A) : (B)) 45: 1.1.1.2 root 46: /* Target cpu type */ 47: 48: enum processor_type rs6000_cpu; 49: char *rs6000_cpu_string; 50: 1.1 root 51: /* Set to non-zero by "fix" operation to indicate that itrunc and 52: uitrunc must be defined. */ 53: 54: int rs6000_trunc_used; 55: 56: /* Set to non-zero once they have been defined. */ 57: 58: static int trunc_defined; 59: 1.1.1.3 root 60: /* Set to non-zero once AIX common-mode calls have been defined. */ 61: static int common_mode_defined; 1.1 root 62: /* Save information from a "cmpxx" operation until the branch or scc is 63: emitted. */ 64: 65: rtx rs6000_compare_op0, rs6000_compare_op1; 66: int rs6000_compare_fp_p; 1.1.1.4 root 67: 68: #ifdef USING_SVR4_H 69: /* Label number of label created for -mrelocatable, to call to so we can 70: get the address of the GOT section */ 71: int rs6000_pic_labelno; 72: #endif 73: 74: /* Whether a System V.4 varargs area was created. */ 75: int rs6000_sysv_varargs_p; 76: 77: /* Temporary memory used to convert integer -> float */ 78: static rtx stack_temps[NUM_MACHINE_MODES]; 79: 80: 81: /* Print the options used in the assembly file. */ 82: 83: extern char *version_string, *language_string; 84: 85: struct asm_option 86: { 87: char *string; 88: int *variable; 89: int on_value; 90: }; 91: 92: #define MAX_LINE 79 93: 94: static int 95: output_option (file, type, name, pos) 96: FILE *file; 97: char *type; 98: char *name; 99: int pos; 100: { 101: int type_len = strlen (type); 102: int name_len = strlen (name); 103: 104: if (1 + type_len + name_len + pos > MAX_LINE) 105: { 106: fprintf (file, "\n # %s%s", type, name); 107: return 3 + type_len + name_len; 108: } 109: fprintf (file, " %s%s", type, name); 110: return pos + 1 + type_len + name_len; 111: } 112: 113: static struct { char *name; int value; } m_options[] = TARGET_SWITCHES; 114: 115: void 116: output_options (file, f_options, f_len, W_options, W_len) 117: FILE *file; 118: struct asm_option *f_options; 119: int f_len; 120: struct asm_option *W_options; 121: int W_len; 122: { 123: int j; 124: int flags = target_flags; 125: int pos = 32767; 126: 127: fprintf (file, " # %s %s", language_string, version_string); 128: 129: if (optimize) 130: { 131: char opt_string[20]; 132: sprintf (opt_string, "%d", optimize); 133: pos = output_option (file, "-O", opt_string, pos); 134: } 135: 136: if (profile_flag) 137: pos = output_option (file, "-p", "", pos); 138: 139: if (profile_block_flag) 140: pos = output_option (file, "-a", "", pos); 141: 142: if (inhibit_warnings) 143: pos = output_option (file, "-w", "", pos); 144: 145: for (j = 0; j < f_len; j++) 146: { 147: if (*f_options[j].variable == f_options[j].on_value) 148: pos = output_option (file, "-f", f_options[j].string, pos); 149: } 150: 151: for (j = 0; j < W_len; j++) 152: { 153: if (*W_options[j].variable == W_options[j].on_value) 154: pos = output_option (file, "-W", W_options[j].string, pos); 155: } 156: 157: for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++) 158: { 159: if (m_options[j].name[0] != '\0' 160: && m_options[j].value > 0 161: && ((m_options[j].value & flags) == m_options[j].value)) 162: { 163: pos = output_option (file, "-m", m_options[j].name, pos); 164: flags &= ~ m_options[j].value; 165: } 166: } 167: 168: if (rs6000_cpu_string != (char *)0) 169: pos = output_option (file, "-mcpu=", rs6000_cpu_string, pos); 170: 171: fputs ("\n\n", file); 172: } 173: 1.1 root 174: 1.1.1.2 root 175: /* Override command line options. Mostly we process the processor 176: type and sometimes adjust other TARGET_ options. */ 177: 178: void 179: rs6000_override_options () 180: { 181: int i; 182: 183: /* Simplify the entries below by making a mask for any POWER 184: variant and any PowerPC variant. */ 185: 1.1.1.4 root 186: #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) 1.1.1.3 root 187: #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ 188: | MASK_PPC_GFXOPT | MASK_POWERPC64) 189: #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) 1.1.1.2 root 190: 191: static struct ptt 192: { 193: char *name; /* Canonical processor name. */ 194: enum processor_type processor; /* Processor type enum value. */ 195: int target_enable; /* Target flags to enable. */ 196: int target_disable; /* Target flags to disable. */ 197: } processor_target_table[] 1.1.1.3 root 198: = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS}, 199: {"power", PROCESSOR_POWER, 1.1.1.4 root 200: MASK_POWER | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 201: MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, 202: {"powerpc", PROCESSOR_POWERPC, 203: MASK_POWERPC | MASK_NEW_MNEMONICS, 204: POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, 205: {"rios", PROCESSOR_RIOS1, 1.1.1.4 root 206: MASK_POWER | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 207: MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, 208: {"rios1", PROCESSOR_RIOS1, 1.1.1.4 root 209: MASK_POWER | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 210: MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, 211: {"rsc", PROCESSOR_PPC601, 1.1.1.4 root 212: MASK_POWER | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 213: MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, 214: {"rsc1", PROCESSOR_PPC601, 1.1.1.4 root 215: MASK_POWER | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 216: MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, 217: {"rios2", PROCESSOR_RIOS2, 1.1.1.4 root 218: MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, 1.1.1.3 root 219: POWERPC_MASKS | MASK_NEW_MNEMONICS}, 1.1.1.4 root 220: {"403", PROCESSOR_PPC403, 221: MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, 222: POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, 1.1.1.2 root 223: {"601", PROCESSOR_PPC601, 1.1.1.4 root 224: MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, 1.1.1.3 root 225: MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, 1.1.1.2 root 226: {"603", PROCESSOR_PPC603, 1.1.1.3 root 227: MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, 228: POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, 1.1.1.2 root 229: {"604", PROCESSOR_PPC604, 1.1.1.3 root 230: MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, 1.1.1.4 root 231: POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}}; 1.1.1.2 root 232: 233: int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); 234: 1.1.1.4 root 235: int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ 236: int string = TARGET_STRING; /* save current -mstring/-mno-string status */ 237: 1.1.1.2 root 238: profile_block_flag = 0; 239: 240: /* Identify the processor type */ 241: if (rs6000_cpu_string == 0) 242: rs6000_cpu = PROCESSOR_DEFAULT; 243: else 244: { 245: for (i = 0; i < ptt_size; i++) 246: if (! strcmp (rs6000_cpu_string, processor_target_table[i].name)) 247: { 248: rs6000_cpu = processor_target_table[i].processor; 249: target_flags |= processor_target_table[i].target_enable; 250: target_flags &= ~processor_target_table[i].target_disable; 251: break; 252: } 253: 254: if (i == ptt_size) 255: { 256: error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string); 257: rs6000_cpu_string = "default"; 258: rs6000_cpu = PROCESSOR_DEFAULT; 259: } 260: } 1.1.1.4 root 261: 262: /* If -mmultiple or -mno-multiple was explicitly used, don't 263: override with the processor default */ 264: if (TARGET_MULTIPLE_SET) 265: target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; 266: 267: /* If -mstring or -mno-string was explicitly used, don't 268: override with the processor default */ 269: if (TARGET_STRING_SET) 270: target_flags = (target_flags & ~MASK_STRING) | string; 271: 272: /* Don't allow -mmultiple or -mstring on little endian systems, because the 273: hardware doesn't support the instructions used in little endian mode */ 274: if (!BYTES_BIG_ENDIAN) 275: { 276: if (TARGET_MULTIPLE) 277: { 278: target_flags &= ~MASK_MULTIPLE; 279: if (TARGET_MULTIPLE_SET) 280: warning ("-mmultiple is not supported on little endian systems"); 281: } 282: 283: if (TARGET_STRING) 284: { 285: target_flags &= ~MASK_STRING; 286: if (TARGET_STRING_SET) 287: warning ("-mstring is not supported on little endian systems"); 288: } 289: } 290: 291: #ifdef SUBTARGET_OVERRIDE_OPTIONS 292: SUBTARGET_OVERRIDE_OPTIONS; 293: #endif 294: } 295: 296: /* Create a CONST_DOUBLE from a string. */ 297: 298: struct rtx_def * 299: rs6000_float_const (string, mode) 300: char *string; 301: enum machine_mode mode; 302: { 303: REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode); 304: return immed_real_const_1 (value, mode); 1.1.1.2 root 305: } 1.1.1.4 root 306: 307: 308: /* Create a CONST_DOUBLE like immed_double_const, except reverse the 309: two parts of the constant if the target is little endian. */ 310: 311: struct rtx_def * 312: rs6000_immed_double_const (i0, i1, mode) 313: HOST_WIDE_INT i0, i1; 314: enum machine_mode mode; 315: { 316: if (! WORDS_BIG_ENDIAN) 317: return immed_double_const (i1, i0, mode); 318: 319: return immed_double_const (i0, i1, mode); 320: } 321: 1.1.1.2 root 322: 1.1 root 323: /* Return non-zero if this function is known to have a null epilogue. */ 324: 325: int 326: direct_return () 327: { 1.1.1.4 root 328: if (reload_completed) 329: { 330: rs6000_stack_t *info = rs6000_stack_info (); 331: 332: if (info->first_gp_reg_save == 32 333: && info->first_fp_reg_save == 64 334: && !info->lr_save_p 335: && !info->cr_save_p 336: && !info->push_p) 337: return 1; 338: } 339: 340: return 0; 1.1 root 341: } 342: 343: /* Returns 1 always. */ 344: 345: int 346: any_operand (op, mode) 347: register rtx op; 348: enum machine_mode mode; 349: { 350: return 1; 351: } 352: 353: /* Return 1 if OP is a constant that can fit in a D field. */ 354: 355: int 356: short_cint_operand (op, mode) 357: register rtx op; 358: enum machine_mode mode; 359: { 360: return (GET_CODE (op) == CONST_INT 361: && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); 362: } 363: 364: /* Similar for a unsigned D field. */ 365: 366: int 367: u_short_cint_operand (op, mode) 368: register rtx op; 369: enum machine_mode mode; 370: { 371: return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); 372: } 373: 374: /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ 375: 376: int 377: non_short_cint_operand (op, mode) 378: register rtx op; 379: enum machine_mode mode; 380: { 381: return (GET_CODE (op) == CONST_INT 382: && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); 383: } 384: 385: /* Returns 1 if OP is a register that is not special (i.e., not MQ, 386: ctr, or lr). */ 387: 388: int 389: gpc_reg_operand (op, mode) 390: register rtx op; 391: enum machine_mode mode; 392: { 393: return (register_operand (op, mode) 394: && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64)); 395: } 396: 397: /* Returns 1 if OP is either a pseudo-register or a register denoting a 398: CR field. */ 399: 400: int 401: cc_reg_operand (op, mode) 402: register rtx op; 403: enum machine_mode mode; 404: { 405: return (register_operand (op, mode) 406: && (GET_CODE (op) != REG 407: || REGNO (op) >= FIRST_PSEUDO_REGISTER 408: || CR_REGNO_P (REGNO (op)))); 409: } 410: 411: /* Returns 1 if OP is either a constant integer valid for a D-field or a 412: non-special register. If a register, it must be in the proper mode unless 413: MODE is VOIDmode. */ 414: 415: int 416: reg_or_short_operand (op, mode) 417: register rtx op; 418: enum machine_mode mode; 419: { 1.1.1.2 root 420: return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); 1.1 root 421: } 422: 423: /* Similar, except check if the negation of the constant would be valid for 424: a D-field. */ 425: 426: int 427: reg_or_neg_short_operand (op, mode) 428: register rtx op; 429: enum machine_mode mode; 430: { 431: if (GET_CODE (op) == CONST_INT) 432: return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); 433: 434: return gpc_reg_operand (op, mode); 435: } 436: 437: /* Return 1 if the operand is either a register or an integer whose high-order 438: 16 bits are zero. */ 439: 440: int 441: reg_or_u_short_operand (op, mode) 442: register rtx op; 443: enum machine_mode mode; 444: { 445: if (GET_CODE (op) == CONST_INT 446: && (INTVAL (op) & 0xffff0000) == 0) 447: return 1; 448: 449: return gpc_reg_operand (op, mode); 450: } 451: 452: /* Return 1 is the operand is either a non-special register or ANY 453: constant integer. */ 454: 455: int 456: reg_or_cint_operand (op, mode) 457: register rtx op; 458: enum machine_mode mode; 459: { 460: return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); 461: } 462: 1.1.1.2 root 463: /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register 464: with one instruction per word. We only do this if we can safely read 465: CONST_DOUBLE_{LOW,HIGH}. */ 1.1 root 466: 467: int 468: easy_fp_constant (op, mode) 469: register rtx op; 470: register enum machine_mode mode; 471: { 472: rtx low, high; 473: 474: if (GET_CODE (op) != CONST_DOUBLE 475: || GET_MODE (op) != mode 476: || GET_MODE_CLASS (mode) != MODE_FLOAT) 477: return 0; 478: 479: high = operand_subword (op, 0, 0, mode); 480: low = operand_subword (op, 1, 0, mode); 481: 1.1.1.2 root 482: if (high == 0 || ! input_operand (high, word_mode)) 1.1 root 483: return 0; 484: 485: return (mode == SFmode 1.1.1.2 root 486: || (low != 0 && input_operand (low, word_mode))); 1.1 root 487: } 1.1.1.4 root 488: 489: /* Return 1 if the operand is an offsettable memory address. */ 490: 491: int 492: offsettable_addr_operand (op, mode) 493: register rtx op; 494: enum machine_mode mode; 495: { 496: return offsettable_address_p (reload_completed | reload_in_progress, 497: mode, op); 498: } 499: 1.1 root 500: /* Return 1 if the operand is either a floating-point register, a pseudo 501: register, or memory. */ 502: 503: int 504: fp_reg_or_mem_operand (op, mode) 505: register rtx op; 506: enum machine_mode mode; 507: { 508: return (memory_operand (op, mode) 509: || (register_operand (op, mode) 510: && (GET_CODE (op) != REG 511: || REGNO (op) >= FIRST_PSEUDO_REGISTER 512: || FP_REGNO_P (REGNO (op))))); 513: } 514: 515: /* Return 1 if the operand is either an easy FP constant (see above) or 516: memory. */ 517: 518: int 519: mem_or_easy_const_operand (op, mode) 520: register rtx op; 521: enum machine_mode mode; 522: { 523: return memory_operand (op, mode) || easy_fp_constant (op, mode); 524: } 525: 526: /* Return 1 if the operand is either a non-special register or an item 527: that can be used as the operand of an SI add insn. */ 528: 529: int 530: add_operand (op, mode) 531: register rtx op; 532: enum machine_mode mode; 533: { 534: return (reg_or_short_operand (op, mode) 535: || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); 536: } 537: 538: /* Return 1 if OP is a constant but not a valid add_operand. */ 539: 540: int 541: non_add_cint_operand (op, mode) 542: register rtx op; 543: enum machine_mode mode; 544: { 545: return (GET_CODE (op) == CONST_INT 546: && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 547: && (INTVAL (op) & 0xffff) != 0); 548: } 549: 550: /* Return 1 if the operand is a non-special register or a constant that 551: can be used as the operand of an OR or XOR insn on the RS/6000. */ 552: 553: int 554: logical_operand (op, mode) 555: register rtx op; 556: enum machine_mode mode; 557: { 558: return (gpc_reg_operand (op, mode) 559: || (GET_CODE (op) == CONST_INT 560: && ((INTVAL (op) & 0xffff0000) == 0 561: || (INTVAL (op) & 0xffff) == 0))); 562: } 563: 564: /* Return 1 if C is a constant that is not a logical operand (as 565: above). */ 566: 567: int 568: non_logical_cint_operand (op, mode) 569: register rtx op; 570: enum machine_mode mode; 571: { 572: return (GET_CODE (op) == CONST_INT 573: && (INTVAL (op) & 0xffff0000) != 0 574: && (INTVAL (op) & 0xffff) != 0); 575: } 576: 577: /* Return 1 if C is a constant that can be encoded in a mask on the 578: RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. 579: Reject all ones and all zeros, since these should have been optimized 580: away and confuse the making of MB and ME. */ 581: 582: int 583: mask_constant (c) 584: register int c; 585: { 586: int i; 587: int last_bit_value; 588: int transitions = 0; 589: 590: if (c == 0 || c == ~0) 591: return 0; 592: 593: last_bit_value = c & 1; 594: 595: for (i = 1; i < 32; i++) 596: if (((c >>= 1) & 1) != last_bit_value) 597: last_bit_value ^= 1, transitions++; 598: 599: return transitions <= 2; 600: } 601: 602: /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ 603: 604: int 605: mask_operand (op, mode) 606: register rtx op; 607: enum machine_mode mode; 608: { 609: return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); 610: } 611: 612: /* Return 1 if the operand is either a non-special register or a 613: constant that can be used as the operand of an RS/6000 logical AND insn. */ 614: 615: int 616: and_operand (op, mode) 617: register rtx op; 618: enum machine_mode mode; 619: { 620: return (reg_or_short_operand (op, mode) 621: || logical_operand (op, mode) 622: || mask_operand (op, mode)); 623: } 624: 625: /* Return 1 if the operand is a constant but not a valid operand for an AND 626: insn. */ 627: 628: int 629: non_and_cint_operand (op, mode) 630: register rtx op; 631: enum machine_mode mode; 632: { 633: return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); 634: } 635: 636: /* Return 1 if the operand is a general register or memory operand. */ 637: 638: int 639: reg_or_mem_operand (op, mode) 640: register rtx op; 641: register enum machine_mode mode; 642: { 643: return gpc_reg_operand (op, mode) || memory_operand (op, mode); 644: } 645: 1.1.1.4 root 646: /* Return 1 if the operand is a general register or memory operand without 647: pre-inc or pre_dec which produces invalid form of PowerPC lwa 648: instruction. */ 649: 650: int 651: lwa_operand (op, mode) 652: register rtx op; 653: register enum machine_mode mode; 654: { 655: rtx inner = op; 656: 657: if (reload_completed && GET_CODE (inner) == SUBREG) 658: inner = SUBREG_REG (inner); 659: 660: return gpc_reg_operand (inner, mode) 661: || (memory_operand (inner, mode) 662: && GET_CODE (XEXP (inner, 0)) != PRE_INC 663: && GET_CODE (XEXP (inner, 0)) != PRE_DEC); 664: } 665: 1.1 root 666: /* Return 1 if the operand, used inside a MEM, is a valid first argument 667: to CALL. This is a SYMBOL_REF or a pseudo-register, which will be 668: forced to lr. */ 669: 670: int 671: call_operand (op, mode) 672: register rtx op; 673: enum machine_mode mode; 674: { 675: if (mode != VOIDmode && GET_MODE (op) != mode) 676: return 0; 677: 678: return (GET_CODE (op) == SYMBOL_REF 679: || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); 680: } 681: 1.1.1.2 root 682: 683: /* Return 1 if the operand is a SYMBOL_REF for a function known to be in 684: this file. */ 685: 686: int 687: current_file_function_operand (op, mode) 688: register rtx op; 689: enum machine_mode mode; 690: { 691: return (GET_CODE (op) == SYMBOL_REF 692: && (SYMBOL_REF_FLAG (op) 693: || op == XEXP (DECL_RTL (current_function_decl), 0))); 694: } 695: 696: 1.1 root 697: /* Return 1 if this operand is a valid input for a move insn. */ 698: 699: int 700: input_operand (op, mode) 701: register rtx op; 702: enum machine_mode mode; 703: { 1.1.1.2 root 704: /* Memory is always valid. */ 1.1 root 705: if (memory_operand (op, mode)) 706: return 1; 707: 1.1.1.2 root 708: /* For floating-point, easy constants are valid. */ 709: if (GET_MODE_CLASS (mode) == MODE_FLOAT 710: && CONSTANT_P (op) 711: && easy_fp_constant (op, mode)) 712: return 1; 713: 714: /* For floating-point or multi-word mode, the only remaining valid type 715: is a register. */ 1.1 root 716: if (GET_MODE_CLASS (mode) == MODE_FLOAT 717: || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1.1.1.2 root 718: return register_operand (op, mode); 1.1 root 719: 720: /* The only cases left are integral modes one word or smaller (we 721: do not get called for MODE_CC values). These can be in any 722: register. */ 723: if (register_operand (op, mode)) 1.1.1.2 root 724: return 1; 1.1 root 725: 726: /* For HImode and QImode, any constant is valid. */ 727: if ((mode == HImode || mode == QImode) 728: && GET_CODE (op) == CONST_INT) 729: return 1; 730: 1.1.1.3 root 731: /* A SYMBOL_REF referring to the TOC is valid. */ 1.1.1.4 root 732: if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) 1.1.1.3 root 733: return 1; 734: 1.1 root 735: /* Otherwise, we will be doing this SET with an add, so anything valid 736: for an add will be valid. */ 737: return add_operand (op, mode); 738: } 739: 1.1.1.4 root 740: /* Initialize a variable CUM of type CUMULATIVE_ARGS 741: for a call to a function whose data type is FNTYPE. 742: For a library call, FNTYPE is 0. 743: 744: For incoming args we set the number of arguments in the prototype large 745: so we never return an EXPR_LIST. */ 746: 747: void 748: init_cumulative_args (cum, fntype, libname, incoming) 749: CUMULATIVE_ARGS *cum; 750: tree fntype; 751: rtx libname; 752: int incoming; 753: { 754: static CUMULATIVE_ARGS zero_cumulative; 755: 756: *cum = zero_cumulative; 757: cum->words = 0; 758: cum->fregno = FP_ARG_MIN_REG; 759: cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); 760: 761: if (incoming) 762: { 763: cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */ 764: #ifdef TARGET_V4_CALLS 765: if (TARGET_V4_CALLS) 766: cum->varargs_offset = RS6000_VARARGS_OFFSET; 767: #endif 768: } 769: 770: else if (cum->prototype) 771: cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 772: + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode 773: || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); 774: 775: else 776: cum->nargs_prototype = 0; 777: 778: cum->orig_nargs = cum->nargs_prototype; 779: if (TARGET_DEBUG_ARG) 780: { 781: fprintf (stderr, "\ninit_cumulative_args:"); 782: if (fntype) 783: { 784: tree ret_type = TREE_TYPE (fntype); 785: fprintf (stderr, " ret code = %s,", 786: tree_code_name[ (int)TREE_CODE (ret_type) ]); 787: } 788: 789: #ifdef TARGET_V4_CALLS 790: if (TARGET_V4_CALLS && incoming) 791: fprintf (stderr, " varargs = %d, ", cum->varargs_offset); 792: #endif 793: 794: fprintf (stderr, " proto = %d, nargs = %d\n", 795: cum->prototype, cum->nargs_prototype); 796: } 797: } 798: 799: /* Update the data in CUM to advance over an argument 800: of mode MODE and data type TYPE. 801: (TYPE is null for libcalls where that information may not be available.) */ 802: 803: void 804: function_arg_advance (cum, mode, type, named) 805: CUMULATIVE_ARGS *cum; 806: enum machine_mode mode; 807: tree type; 808: int named; 809: { 810: cum->nargs_prototype--; 811: 812: #ifdef TARGET_V4_CALLS 813: if (TARGET_V4_CALLS) 814: { 815: /* Long longs must not be split between registers and stack */ 816: if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT) 817: && type && !AGGREGATE_TYPE_P (type) 818: && cum->words < GP_ARG_NUM_REG 819: && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) 820: { 821: cum->words = GP_ARG_NUM_REG; 822: } 823: 824: /* Aggregates get passed as pointers */ 825: if (type && AGGREGATE_TYPE_P (type)) 826: cum->words++; 827: 828: /* Floats go in registers, & don't occupy space in the GP registers 829: like they do for AIX unless software floating point. */ 830: else if (GET_MODE_CLASS (mode) == MODE_FLOAT 831: && TARGET_HARD_FLOAT 832: && cum->fregno <= FP_ARG_V4_MAX_REG) 833: cum->fregno++; 834: 835: else 836: cum->words += RS6000_ARG_SIZE (mode, type, 1); 837: } 838: else 839: #endif 840: if (named) 841: { 842: cum->words += RS6000_ARG_SIZE (mode, type, named); 843: if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) 844: cum->fregno++; 845: } 846: 847: if (TARGET_DEBUG_ARG) 848: fprintf (stderr, 849: "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n", 850: cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named); 851: } 852: 853: /* Determine where to put an argument to a function. 854: Value is zero to push the argument on the stack, 855: or a hard register in which to store the argument. 856: 857: MODE is the argument's machine mode. 858: TYPE is the data type of the argument (as a tree). 859: This is null for libcalls where that information may 860: not be available. 861: CUM is a variable of type CUMULATIVE_ARGS which gives info about 862: the preceding args and about the function being called. 863: NAMED is nonzero if this argument is a named parameter 864: (otherwise it is an extra parameter matching an ellipsis). 865: 866: On RS/6000 the first eight words of non-FP are normally in registers 867: and the rest are pushed. Under AIX, the first 13 FP args are in registers. 868: Under V.4, the first 8 FP args are in registers. 869: 870: If this is floating-point and no prototype is specified, we use 871: both an FP and integer register (or possibly FP reg and stack). Library 872: functions (when TYPE is zero) always have the proper types for args, 873: so we can pass the FP value just in one register. emit_library_function 874: doesn't support EXPR_LIST anyway. */ 875: 876: struct rtx_def * 877: function_arg (cum, mode, type, named) 878: CUMULATIVE_ARGS *cum; 879: enum machine_mode mode; 880: tree type; 881: int named; 882: { 883: if (TARGET_DEBUG_ARG) 884: fprintf (stderr, 885: "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n", 886: cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named); 887: 888: /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 889: uses to say fp args were passed in registers. Assume that we don't need the 890: marker for software floating point, or compiler generated library calls. */ 891: if (mode == VOIDmode) 892: { 893: #ifdef TARGET_V4_CALLS 894: if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && cum->nargs_prototype < 0 895: && type && (cum->prototype || TARGET_NO_PROTOTYPE)) 896: return GEN_INT ((cum->fregno == FP_ARG_MIN_REG) ? -1 : 1); 897: #endif 898: 899: return GEN_INT (0); 900: } 901: 902: if (!named) 903: { 904: #ifdef TARGET_V4_CALLS 905: if (!TARGET_V4_CALLS) 906: #endif 907: return NULL_RTX; 908: } 909: 910: if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) 911: return NULL_RTX; 912: 913: if (USE_FP_FOR_ARG_P (*cum, mode, type)) 914: { 915: if ((cum->nargs_prototype > 0) 916: #ifdef TARGET_V4_CALLS 917: || TARGET_V4_CALLS /* V.4 never passes FP values in GP registers */ 918: #endif 919: || !type) 920: return gen_rtx (REG, mode, cum->fregno); 921: 922: return gen_rtx (EXPR_LIST, VOIDmode, 923: ((cum->words < GP_ARG_NUM_REG) 924: ? gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words) 925: : NULL_RTX), 926: gen_rtx (REG, mode, cum->fregno)); 927: } 928: 929: #ifdef TARGET_V4_CALLS 930: /* Long longs won't be split between register and stack */ 931: else if (TARGET_V4_CALLS && 932: cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) 933: { 934: return NULL_RTX; 935: } 936: #endif 937: 938: else if (cum->words < GP_ARG_NUM_REG) 939: return gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words); 940: 941: return NULL_RTX; 942: } 943: 944: /* For an arg passed partly in registers and partly in memory, 945: this is the number of registers used. 946: For args passed entirely in registers or entirely in memory, zero. */ 947: 948: int 949: function_arg_partial_nregs (cum, mode, type, named) 950: CUMULATIVE_ARGS *cum; 951: enum machine_mode mode; 952: tree type; 953: int named; 954: { 955: if (! named) 956: return 0; 957: 958: #ifdef TARGET_V4_CALLS 959: if (TARGET_V4_CALLS) 960: return 0; 961: #endif 962: 963: if (USE_FP_FOR_ARG_P (*cum, mode, type)) 964: { 965: if (cum->nargs_prototype >= 0) 966: return 0; 967: } 968: 969: if (cum->words < GP_ARG_NUM_REG 970: && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named))) 971: { 972: int ret = GP_ARG_NUM_REG - cum->words; 973: if (ret && TARGET_DEBUG_ARG) 974: fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); 975: 976: return ret; 977: } 978: 979: return 0; 980: } 981: 982: /* A C expression that indicates when an argument must be passed by 983: reference. If nonzero for an argument, a copy of that argument is 984: made in memory and a pointer to the argument is passed instead of 985: the argument itself. The pointer is passed in whatever way is 986: appropriate for passing a pointer to that type. 987: 988: Under V.4, structures and unions are passed by reference. */ 989: 990: int 991: function_arg_pass_by_reference (cum, mode, type, named) 992: CUMULATIVE_ARGS *cum; 993: enum machine_mode mode; 994: tree type; 995: int named; 996: { 997: #ifdef TARGET_V4_CALLS 998: if (TARGET_V4_CALLS && type && AGGREGATE_TYPE_P (type)) 999: { 1000: if (TARGET_DEBUG_ARG) 1001: fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); 1002: 1003: return 1; 1004: } 1005: #endif 1006: 1007: return 0; 1008: } 1009: 1010: 1011: /* Perform any needed actions needed for a function that is receiving a 1012: variable number of arguments. 1013: 1014: CUM is as above. 1015: 1016: MODE and TYPE are the mode and type of the current parameter. 1017: 1018: PRETEND_SIZE is a variable that should be set to the amount of stack 1019: that must be pushed by the prolog to pretend that our caller pushed 1020: it. 1021: 1022: Normally, this macro will push all remaining incoming registers on the 1023: stack and set PRETEND_SIZE to the length of the registers pushed. */ 1024: 1025: void 1026: setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) 1027: CUMULATIVE_ARGS *cum; 1028: enum machine_mode mode; 1029: tree type; 1030: int *pretend_size; 1031: int no_rtl; 1032: 1033: { 1034: rtx save_area = virtual_incoming_args_rtx; 1035: int reg_size = (TARGET_64BIT) ? 8 : 4; 1036: 1037: if (TARGET_DEBUG_ARG) 1038: fprintf (stderr, 1039: "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n", 1040: cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl); 1041: 1042: #ifdef TARGET_V4_CALLS 1043: if (TARGET_V4_CALLS && !no_rtl) 1044: { 1045: rs6000_sysv_varargs_p = 1; 1046: save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET); 1047: } 1048: #endif 1049: 1050: if (cum->words < 8) 1051: { 1052: int first_reg_offset = cum->words; 1053: 1054: if (MUST_PASS_IN_STACK (mode, type)) 1055: first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1); 1056: 1057: if (first_reg_offset > GP_ARG_NUM_REG) 1058: first_reg_offset = GP_ARG_NUM_REG; 1059: 1060: if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG) 1061: move_block_from_reg 1062: (GP_ARG_MIN_REG + first_reg_offset, 1063: gen_rtx (MEM, BLKmode, 1064: plus_constant (save_area, first_reg_offset * reg_size)), 1065: GP_ARG_NUM_REG - first_reg_offset, 1066: (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); 1067: 1068: *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; 1069: } 1070: 1071: #ifdef TARGET_V4_CALLS 1072: /* Save FP registers if needed. */ 1073: if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && !no_rtl) 1074: { 1075: int fregno = cum->fregno; 1076: int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno; 1077: 1078: if (num_fp_reg >= 0) 1079: { 1080: rtx cr1 = gen_rtx (REG, CCmode, 69); 1081: rtx lab = gen_label_rtx (); 1082: int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); 1083: 1084: emit_jump_insn (gen_rtx (SET, VOIDmode, 1085: pc_rtx, 1086: gen_rtx (IF_THEN_ELSE, VOIDmode, 1087: gen_rtx (NE, VOIDmode, cr1, const0_rtx), 1088: gen_rtx (LABEL_REF, VOIDmode, lab), 1089: pc_rtx))); 1090: 1091: while ( num_fp_reg-- >= 0) 1092: { 1093: emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)), 1094: gen_rtx (REG, DFmode, fregno++)); 1095: off += 8; 1096: } 1097: 1098: emit_label (lab); 1099: } 1100: } 1101: #endif 1102: } 1103: 1104: /* If defined, is a C expression that produces the machine-specific 1105: code for a call to `__builtin_saveregs'. This code will be moved 1106: to the very beginning of the function, before any parameter access 1107: are made. The return value of this function should be an RTX that 1108: contains the value to use as the return of `__builtin_saveregs'. 1109: 1110: The argument ARGS is a `tree_list' containing the arguments that 1111: were passed to `__builtin_saveregs'. 1112: 1113: If this macro is not defined, the compiler will output an ordinary 1114: call to the library function `__builtin_saveregs'. 1115: 1116: On the Power/PowerPC return the address of the area on the stack 1117: used to hold arguments. Under AIX, this includes the 8 word register 1118: save area. Under V.4 this does not. */ 1119: 1120: struct rtx_def * 1121: expand_builtin_saveregs (args) 1122: tree args; 1123: { 1124: return virtual_incoming_args_rtx; 1125: } 1126: 1127: 1128: /* Allocate a stack temp. Only allocate one stack temp per type for a 1129: function. */ 1130: 1131: struct rtx_def * 1132: rs6000_stack_temp (mode, size) 1133: enum machine_mode mode; 1134: int size; 1135: { 1136: rtx temp = stack_temps[ (int)mode ]; 1137: rtx addr; 1138: 1139: if (temp == NULL_RTX) 1140: { 1141: temp = assign_stack_local (mode, size, 0); 1142: addr = XEXP (temp, 0); 1143: 1144: if ((size > 4 && !offsettable_address_p (0, mode, addr)) 1145: || (size <= 4 && !memory_address_p (mode, addr))) 1146: { 1147: XEXP (temp, 0) = copy_addr_to_reg (addr); 1148: } 1149: 1150: stack_temps[ (int)mode ] = temp; 1151: } 1152: 1153: return temp; 1154: } 1155: 1156: 1157: /* Generate a memory reference for expand_block_move, copying volatile, 1158: and other bits from an original memory reference. */ 1159: 1160: static rtx 1161: expand_block_move_mem (mode, addr, orig_mem) 1162: enum machine_mode mode; 1163: rtx addr; 1164: rtx orig_mem; 1165: { 1166: rtx mem = gen_rtx (MEM, mode, addr); 1.1.1.5 ! root 1167: RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem); 1.1.1.4 root 1168: MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem); 1169: MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem); 1170: return mem; 1171: } 1172: 1173: /* Expand a block move operation, and return 1 if successful. Return 0 1174: if we should let the compiler generate normal code. 1175: 1176: operands[0] is the destination 1177: operands[1] is the source 1178: operands[2] is the length 1179: operands[3] is the alignment */ 1180: 1181: #define MAX_MOVE_REG 4 1182: 1183: int 1184: expand_block_move (operands) 1185: rtx operands[]; 1186: { 1.1.1.5 ! root 1187: rtx orig_dest = operands[0]; ! 1188: rtx orig_src = operands[1]; 1.1.1.4 root 1189: rtx bytes_rtx = operands[2]; 1190: rtx align_rtx = operands[3]; 1191: int constp = (GET_CODE (bytes_rtx) == CONST_INT); 1192: int align = XINT (align_rtx, 0); 1193: int bytes; 1194: int offset; 1195: int num_reg; 1196: int i; 1197: rtx src_reg; 1198: rtx dest_reg; 1199: rtx src_addr; 1200: rtx dest_addr; 1201: rtx tmp_reg; 1202: rtx stores[MAX_MOVE_REG]; 1203: int move_bytes; 1204: 1205: /* If this is not a fixed size move, just call memcpy */ 1206: if (!constp) 1207: return 0; 1208: 1209: /* Anything to move? */ 1210: bytes = INTVAL (bytes_rtx); 1211: if (bytes <= 0) 1212: return 1; 1213: 1214: /* Don't support real large moves. If string instructions are not used, 1215: then don't generate more than 8 loads. */ 1216: if (TARGET_STRING) 1217: { 1218: if (bytes > 4*8) 1219: return 0; 1220: } 1221: else if (!STRICT_ALIGNMENT) 1222: { 1223: if (bytes > 4*8) 1224: return 0; 1225: } 1226: else if (bytes > 8*align) 1227: return 0; 1228: 1229: /* Move the address into scratch registers. */ 1.1.1.5 ! root 1230: dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); ! 1231: src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); 1.1.1.4 root 1232: 1233: if (TARGET_STRING) /* string instructions are available */ 1234: { 1235: for ( ; bytes > 0; bytes -= move_bytes) 1236: { 1237: if (bytes > 24 /* move up to 32 bytes at a time */ 1238: && !fixed_regs[5] 1239: && !fixed_regs[6] 1240: && !fixed_regs[7] 1241: && !fixed_regs[8] 1242: && !fixed_regs[9] 1243: && !fixed_regs[10] 1244: && !fixed_regs[11] 1245: && !fixed_regs[12]) 1246: { 1247: move_bytes = (bytes > 32) ? 32 : bytes; 1.1.1.5 ! root 1248: emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), ! 1249: expand_block_move_mem (BLKmode, src_reg, orig_src), 1.1.1.4 root 1250: GEN_INT ((move_bytes == 32) ? 0 : move_bytes), 1251: align_rtx)); 1252: } 1253: else if (bytes > 16 /* move up to 24 bytes at a time */ 1254: && !fixed_regs[7] 1255: && !fixed_regs[8] 1256: && !fixed_regs[9] 1257: && !fixed_regs[10] 1258: && !fixed_regs[11] 1259: && !fixed_regs[12]) 1260: { 1261: move_bytes = (bytes > 24) ? 24 : bytes; 1.1.1.5 ! root 1262: emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), ! 1263: expand_block_move_mem (BLKmode, src_reg, orig_src), 1.1.1.4 root 1264: GEN_INT (move_bytes), 1265: align_rtx)); 1266: } 1267: else if (bytes > 8 /* move up to 16 bytes at a time */ 1268: && !fixed_regs[9] 1269: && !fixed_regs[10] 1270: && !fixed_regs[11] 1271: && !fixed_regs[12]) 1272: { 1273: move_bytes = (bytes > 16) ? 16 : bytes; 1.1.1.5 ! root 1274: emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), ! 1275: expand_block_move_mem (BLKmode, src_reg, orig_src), 1.1.1.4 root 1276: GEN_INT (move_bytes), 1277: align_rtx)); 1278: } 1279: else if (bytes > 4 && !TARGET_64BIT) 1280: { /* move up to 8 bytes at a time */ 1281: move_bytes = (bytes > 8) ? 8 : bytes; 1.1.1.5 ! root 1282: emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), ! 1283: expand_block_move_mem (BLKmode, src_reg, orig_src), 1.1.1.4 root 1284: GEN_INT (move_bytes), 1285: align_rtx)); 1286: } 1287: else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) 1288: { /* move 4 bytes */ 1289: move_bytes = 4; 1290: tmp_reg = gen_reg_rtx (SImode); 1.1.1.5 ! root 1291: emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src)); ! 1292: emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg); 1.1.1.4 root 1293: } 1294: else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT)) 1295: { /* move 2 bytes */ 1296: move_bytes = 2; 1297: tmp_reg = gen_reg_rtx (HImode); 1.1.1.5 ! root 1298: emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src)); ! 1299: emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg); 1.1.1.4 root 1300: } 1301: else if (bytes == 1) /* move 1 byte */ 1302: { 1303: move_bytes = 1; 1304: tmp_reg = gen_reg_rtx (QImode); 1.1.1.5 ! root 1305: emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src)); ! 1306: emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg); 1.1.1.4 root 1307: } 1308: else 1309: { /* move up to 4 bytes at a time */ 1310: move_bytes = (bytes > 4) ? 4 : bytes; 1.1.1.5 ! root 1311: emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), ! 1312: expand_block_move_mem (BLKmode, src_reg, orig_src), 1.1.1.4 root 1313: GEN_INT (move_bytes), 1314: align_rtx)); 1315: } 1316: 1317: if (bytes > move_bytes) 1318: { 1319: emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes))); 1320: emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes))); 1321: } 1322: } 1323: } 1324: 1325: else /* string instructions not available */ 1326: { 1327: num_reg = offset = 0; 1328: for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) 1329: { 1330: /* Calculate the correct offset for src/dest */ 1331: if (offset == 0) 1332: { 1333: src_addr = src_reg; 1334: dest_addr = dest_reg; 1335: } 1336: else 1337: { 1338: src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset)); 1339: dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset)); 1340: } 1341: 1342: /* Generate the appropriate load and store, saving the stores for later */ 1.1.1.5 ! root 1343: if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT)) ! 1344: { ! 1345: move_bytes = 8; ! 1346: tmp_reg = gen_reg_rtx (DImode); ! 1347: emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src))); ! 1348: stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg); ! 1349: } ! 1350: else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) 1.1.1.4 root 1351: { 1352: move_bytes = 4; 1353: tmp_reg = gen_reg_rtx (SImode); 1.1.1.5 ! root 1354: emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src))); ! 1355: stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg); 1.1.1.4 root 1356: } 1357: else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT)) 1358: { 1359: move_bytes = 2; 1360: tmp_reg = gen_reg_rtx (HImode); 1.1.1.5 ! root 1361: emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src))); ! 1362: stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg); 1.1.1.4 root 1363: } 1364: else 1365: { 1366: move_bytes = 1; 1367: tmp_reg = gen_reg_rtx (QImode); 1.1.1.5 ! root 1368: emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src))); ! 1369: stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg); 1.1.1.4 root 1370: } 1371: 1372: if (num_reg >= MAX_MOVE_REG) 1373: { 1374: for (i = 0; i < num_reg; i++) 1375: emit_insn (stores[i]); 1376: num_reg = 0; 1377: } 1378: } 1379: 1.1.1.5 ! root 1380: for (i = 0; i < num_reg; i++) ! 1381: emit_insn (stores[i]); 1.1.1.4 root 1382: } 1383: 1384: return 1; 1385: } 1386: 1387: 1.1 root 1388: /* Return 1 if OP is a load multiple operation. It is known to be a 1389: PARALLEL and the first section will be tested. */ 1390: 1391: int 1392: load_multiple_operation (op, mode) 1393: rtx op; 1394: enum machine_mode mode; 1395: { 1396: int count = XVECLEN (op, 0); 1397: int dest_regno; 1398: rtx src_addr; 1399: int i; 1400: 1401: /* Perform a quick check so we don't blow up below. */ 1402: if (count <= 1 1403: || GET_CODE (XVECEXP (op, 0, 0)) != SET 1404: || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1405: || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1406: return 0; 1407: 1408: dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1409: src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1410: 1411: for (i = 1; i < count; i++) 1412: { 1413: rtx elt = XVECEXP (op, 0, i); 1414: 1415: if (GET_CODE (elt) != SET 1416: || GET_CODE (SET_DEST (elt)) != REG 1417: || GET_MODE (SET_DEST (elt)) != SImode 1418: || REGNO (SET_DEST (elt)) != dest_regno + i 1419: || GET_CODE (SET_SRC (elt)) != MEM 1420: || GET_MODE (SET_SRC (elt)) != SImode 1421: || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 1422: || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 1423: || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 1424: || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) 1425: return 0; 1426: } 1427: 1428: return 1; 1429: } 1430: 1431: /* Similar, but tests for store multiple. Here, the second vector element 1432: is a CLOBBER. It will be tested later. */ 1433: 1434: int 1435: store_multiple_operation (op, mode) 1436: rtx op; 1437: enum machine_mode mode; 1438: { 1439: int count = XVECLEN (op, 0) - 1; 1440: int src_regno; 1441: rtx dest_addr; 1442: int i; 1443: 1444: /* Perform a quick check so we don't blow up below. */ 1445: if (count <= 1 1446: || GET_CODE (XVECEXP (op, 0, 0)) != SET 1447: || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1448: || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1449: return 0; 1450: 1451: src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1452: dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1453: 1454: for (i = 1; i < count; i++) 1455: { 1456: rtx elt = XVECEXP (op, 0, i + 1); 1457: 1458: if (GET_CODE (elt) != SET 1459: || GET_CODE (SET_SRC (elt)) != REG 1460: || GET_MODE (SET_SRC (elt)) != SImode 1461: || REGNO (SET_SRC (elt)) != src_regno + i 1462: || GET_CODE (SET_DEST (elt)) != MEM 1463: || GET_MODE (SET_DEST (elt)) != SImode 1464: || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 1465: || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 1466: || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 1467: || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) 1468: return 0; 1469: } 1470: 1471: return 1; 1472: } 1473: 1474: /* Return 1 if OP is a comparison operation that is valid for a branch insn. 1475: We only check the opcode against the mode of the CC value here. */ 1476: 1477: int 1478: branch_comparison_operator (op, mode) 1479: register rtx op; 1480: enum machine_mode mode; 1481: { 1482: enum rtx_code code = GET_CODE (op); 1483: enum machine_mode cc_mode; 1484: 1485: if (GET_RTX_CLASS (code) != '<') 1486: return 0; 1487: 1488: cc_mode = GET_MODE (XEXP (op, 0)); 1489: if (GET_MODE_CLASS (cc_mode) != MODE_CC) 1490: return 0; 1491: 1492: if ((code == GT || code == LT || code == GE || code == LE) 1493: && cc_mode == CCUNSmode) 1494: return 0; 1495: 1496: if ((code == GTU || code == LTU || code == GEU || code == LEU) 1497: && (cc_mode != CCUNSmode)) 1498: return 0; 1499: 1500: return 1; 1501: } 1502: 1503: /* Return 1 if OP is a comparison operation that is valid for an scc insn. 1504: We check the opcode against the mode of the CC value and disallow EQ or 1505: NE comparisons for integers. */ 1506: 1507: int 1508: scc_comparison_operator (op, mode) 1509: register rtx op; 1510: enum machine_mode mode; 1511: { 1512: enum rtx_code code = GET_CODE (op); 1513: enum machine_mode cc_mode; 1514: 1515: if (GET_MODE (op) != mode && mode != VOIDmode) 1516: return 0; 1517: 1518: if (GET_RTX_CLASS (code) != '<') 1519: return 0; 1520: 1521: cc_mode = GET_MODE (XEXP (op, 0)); 1522: if (GET_MODE_CLASS (cc_mode) != MODE_CC) 1523: return 0; 1524: 1525: if (code == NE && cc_mode != CCFPmode) 1526: return 0; 1527: 1528: if ((code == GT || code == LT || code == GE || code == LE) 1529: && cc_mode == CCUNSmode) 1530: return 0; 1531: 1532: if ((code == GTU || code == LTU || code == GEU || code == LEU) 1533: && (cc_mode != CCUNSmode)) 1534: return 0; 1535: 1536: if (cc_mode == CCEQmode && code != EQ && code != NE) 1537: return 0; 1538: 1539: return 1; 1540: } 1541: 1542: /* Return 1 if ANDOP is a mask that has no bits on that are not in the 1543: mask required to convert the result of a rotate insn into a shift 1544: left insn of SHIFTOP bits. Both are known to be CONST_INT. */ 1545: 1546: int 1547: includes_lshift_p (shiftop, andop) 1548: register rtx shiftop; 1549: register rtx andop; 1550: { 1551: int shift_mask = (~0 << INTVAL (shiftop)); 1552: 1553: return (INTVAL (andop) & ~shift_mask) == 0; 1554: } 1555: 1556: /* Similar, but for right shift. */ 1557: 1558: int 1559: includes_rshift_p (shiftop, andop) 1560: register rtx shiftop; 1561: register rtx andop; 1562: { 1563: unsigned shift_mask = ~0; 1564: 1565: shift_mask >>= INTVAL (shiftop); 1566: 1567: return (INTVAL (andop) & ~ shift_mask) == 0; 1568: } 1.1.1.4 root 1569: 1570: /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates 1571: for lfq and stfq insns. 1572: 1573: Note reg1 and reg2 *must* be hard registers. To be sure we will 1574: abort if we are passed pseudo registers. */ 1575: 1576: int 1577: registers_ok_for_quad_peep (reg1, reg2) 1578: rtx reg1, reg2; 1579: { 1580: /* We might have been passed a SUBREG. */ 1581: if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 1582: return 0; 1583: 1584: return (REGNO (reg1) == REGNO (reg2) - 1); 1585: } 1586: 1587: /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and 1588: addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ 1589: 1590: int 1591: addrs_ok_for_quad_peep (addr1, addr2) 1592: register rtx addr1; 1593: register rtx addr2; 1594: { 1595: int reg1; 1596: int offset1; 1597: 1598: /* Extract an offset (if used) from the first addr. */ 1599: if (GET_CODE (addr1) == PLUS) 1600: { 1601: /* If not a REG, return zero. */ 1602: if (GET_CODE (XEXP (addr1, 0)) != REG) 1603: return 0; 1604: else 1605: { 1606: reg1 = REGNO (XEXP (addr1, 0)); 1607: /* The offset must be constant! */ 1608: if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 1609: return 0; 1610: offset1 = INTVAL (XEXP (addr1, 1)); 1611: } 1612: } 1613: else if (GET_CODE (addr1) != REG) 1614: return 0; 1615: else 1616: { 1617: reg1 = REGNO (addr1); 1618: /* This was a simple (mem (reg)) expression. Offset is 0. */ 1619: offset1 = 0; 1620: } 1621: 1622: /* Make sure the second address is a (mem (plus (reg) (const_int). */ 1623: if (GET_CODE (addr2) != PLUS) 1624: return 0; 1625: 1626: if (GET_CODE (XEXP (addr2, 0)) != REG 1627: || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 1628: return 0; 1629: 1630: if (reg1 != REGNO (XEXP (addr2, 0))) 1631: return 0; 1632: 1633: /* The offset for the second addr must be 8 more than the first addr. */ 1634: if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) 1635: return 0; 1636: 1637: /* All the tests passed. addr1 and addr2 are valid for lfq or stfq 1638: instructions. */ 1639: return 1; 1640: } 1.1 root 1641: 1642: /* Return the register class of a scratch register needed to copy IN into 1643: or out of a register in CLASS in MODE. If it can be done directly, 1644: NO_REGS is returned. */ 1645: 1646: enum reg_class 1647: secondary_reload_class (class, mode, in) 1648: enum reg_class class; 1649: enum machine_mode mode; 1650: rtx in; 1651: { 1652: int regno = true_regnum (in); 1653: 1654: if (regno >= FIRST_PSEUDO_REGISTER) 1655: regno = -1; 1656: 1657: /* We can place anything into GENERAL_REGS and can put GENERAL_REGS 1658: into anything. */ 1659: if (class == GENERAL_REGS || class == BASE_REGS 1660: || (regno >= 0 && INT_REGNO_P (regno))) 1661: return NO_REGS; 1662: 1663: /* Constants, memory, and FP registers can go into FP registers. */ 1664: if ((regno == -1 || FP_REGNO_P (regno)) 1665: && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) 1666: return NO_REGS; 1667: 1668: /* We can copy among the CR registers. */ 1669: if ((class == CR_REGS || class == CR0_REGS) 1670: && regno >= 0 && CR_REGNO_P (regno)) 1671: return NO_REGS; 1672: 1673: /* Otherwise, we need GENERAL_REGS. */ 1674: return GENERAL_REGS; 1675: } 1676: 1677: /* Given a comparison operation, return the bit number in CCR to test. We 1678: know this is a valid comparison. 1679: 1680: SCC_P is 1 if this is for an scc. That means that %D will have been 1681: used instead of %C, so the bits will be in different places. 1682: 1683: Return -1 if OP isn't a valid comparison for some reason. */ 1684: 1685: int 1686: ccr_bit (op, scc_p) 1687: register rtx op; 1688: int scc_p; 1689: { 1690: enum rtx_code code = GET_CODE (op); 1691: enum machine_mode cc_mode; 1692: int cc_regnum; 1693: int base_bit; 1694: 1695: if (GET_RTX_CLASS (code) != '<') 1696: return -1; 1697: 1698: cc_mode = GET_MODE (XEXP (op, 0)); 1699: cc_regnum = REGNO (XEXP (op, 0)); 1700: base_bit = 4 * (cc_regnum - 68); 1701: 1702: /* In CCEQmode cases we have made sure that the result is always in the 1703: third bit of the CR field. */ 1704: 1705: if (cc_mode == CCEQmode) 1706: return base_bit + 3; 1707: 1708: switch (code) 1709: { 1710: case NE: 1711: return scc_p ? base_bit + 3 : base_bit + 2; 1712: case EQ: 1713: return base_bit + 2; 1714: case GT: case GTU: 1715: return base_bit + 1; 1716: case LT: case LTU: 1717: return base_bit; 1718: 1719: case GE: case GEU: 1720: /* If floating-point, we will have done a cror to put the bit in the 1721: unordered position. So test that bit. For integer, this is ! LT 1722: unless this is an scc insn. */ 1723: return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; 1724: 1725: case LE: case LEU: 1726: return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; 1727: 1728: default: 1729: abort (); 1730: } 1731: } 1732: 1733: /* Print an operand. Recognize special options, documented below. */ 1734: 1735: void 1736: print_operand (file, x, code) 1737: FILE *file; 1738: rtx x; 1739: char code; 1740: { 1741: int i; 1742: int val; 1743: 1744: /* These macros test for integers and extract the low-order bits. */ 1745: #define INT_P(X) \ 1746: ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ 1747: && GET_MODE (X) == VOIDmode) 1748: 1749: #define INT_LOWPART(X) \ 1750: (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) 1751: 1752: switch (code) 1753: { 1.1.1.2 root 1754: case '.': 1755: /* Write out an instruction after the call which may be replaced 1756: with glue code by the loader. This depends on the AIX version. */ 1757: asm_fprintf (file, RS6000_CALL_GLUE); 1758: return; 1759: 1.1.1.3 root 1760: case '*': 1761: /* Write the register number of the TOC register. */ 1.1.1.4 root 1762: fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file); 1.1.1.3 root 1763: return; 1764: 1.1 root 1765: case 'A': 1766: /* If X is a constant integer whose low-order 5 bits are zero, 1767: write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug 1.1.1.2 root 1768: in the AIX assembler where "sri" with a zero shift count 1.1 root 1769: write a trash instruction. */ 1770: if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) 1.1.1.2 root 1771: putc ('l', file); 1.1 root 1772: else 1.1.1.2 root 1773: putc ('r', file); 1.1 root 1774: return; 1775: 1776: case 'b': 1777: /* Low-order 16 bits of constant, unsigned. */ 1778: if (! INT_P (x)) 1779: output_operand_lossage ("invalid %%b value"); 1780: 1781: fprintf (file, "%d", INT_LOWPART (x) & 0xffff); 1782: return; 1783: 1784: case 'C': 1785: /* This is an optional cror needed for LE or GE floating-point 1786: comparisons. Otherwise write nothing. */ 1787: if ((GET_CODE (x) == LE || GET_CODE (x) == GE) 1788: && GET_MODE (XEXP (x, 0)) == CCFPmode) 1789: { 1790: int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); 1791: 1792: fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, 1793: base_bit + 2, base_bit + (GET_CODE (x) == GE)); 1794: } 1795: return; 1796: 1797: case 'D': 1798: /* Similar, except that this is for an scc, so we must be able to 1799: encode the test in a single bit that is one. We do the above 1800: for any LE, GE, GEU, or LEU and invert the bit for NE. */ 1801: if (GET_CODE (x) == LE || GET_CODE (x) == GE 1802: || GET_CODE (x) == LEU || GET_CODE (x) == GEU) 1803: { 1804: int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); 1805: 1806: fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, 1807: base_bit + 2, 1808: base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); 1809: } 1810: 1811: else if (GET_CODE (x) == NE) 1812: { 1813: int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); 1814: 1815: fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, 1816: base_bit + 2, base_bit + 2); 1817: } 1818: return; 1819: 1820: case 'E': 1821: /* X is a CR register. Print the number of the third bit of the CR */ 1822: if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 1823: output_operand_lossage ("invalid %%E value"); 1824: 1825: fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); 1.1.1.2 root 1826: return; 1.1 root 1827: 1828: case 'f': 1829: /* X is a CR register. Print the shift count needed to move it 1830: to the high-order four bits. */ 1831: if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 1832: output_operand_lossage ("invalid %%f value"); 1833: else 1834: fprintf (file, "%d", 4 * (REGNO (x) - 68)); 1835: return; 1836: 1837: case 'F': 1838: /* Similar, but print the count for the rotate in the opposite 1839: direction. */ 1840: if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 1841: output_operand_lossage ("invalid %%F value"); 1842: else 1843: fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); 1844: return; 1845: 1846: case 'G': 1847: /* X is a constant integer. If it is negative, print "m", 1848: otherwise print "z". This is to make a aze or ame insn. */ 1849: if (GET_CODE (x) != CONST_INT) 1850: output_operand_lossage ("invalid %%G value"); 1851: else if (INTVAL (x) >= 0) 1.1.1.2 root 1852: putc ('z', file); 1.1 root 1853: else 1.1.1.2 root 1854: putc ('m', file); 1.1 root 1855: return; 1856: 1857: case 'h': 1858: /* If constant, output low-order five bits. Otherwise, 1859: write normally. */ 1860: if (INT_P (x)) 1861: fprintf (file, "%d", INT_LOWPART (x) & 31); 1862: else 1863: print_operand (file, x, 0); 1864: return; 1865: 1866: case 'I': 1867: /* Print `i' if this is a constant, else nothing. */ 1868: if (INT_P (x)) 1.1.1.2 root 1869: putc ('i', file); 1.1 root 1870: return; 1871: 1872: case 'j': 1873: /* Write the bit number in CCR for jump. */ 1874: i = ccr_bit (x, 0); 1875: if (i == -1) 1876: output_operand_lossage ("invalid %%j code"); 1877: else 1878: fprintf (file, "%d", i); 1879: return; 1880: 1881: case 'J': 1882: /* Similar, but add one for shift count in rlinm for scc and pass 1883: scc flag to `ccr_bit'. */ 1884: i = ccr_bit (x, 1); 1885: if (i == -1) 1886: output_operand_lossage ("invalid %%J code"); 1887: else 1.1.1.2 root 1888: /* If we want bit 31, write a shift count of zero, not 32. */ 1889: fprintf (file, "%d", i == 31 ? 0 : i + 1); 1.1 root 1890: return; 1891: 1892: case 'k': 1893: /* X must be a constant. Write the 1's complement of the 1894: constant. */ 1895: if (! INT_P (x)) 1896: output_operand_lossage ("invalid %%k value"); 1897: 1898: fprintf (file, "%d", ~ INT_LOWPART (x)); 1899: return; 1900: 1901: case 'L': 1902: /* Write second word of DImode or DFmode reference. Works on register 1903: or non-indexed memory only. */ 1904: if (GET_CODE (x) == REG) 1905: fprintf (file, "%d", REGNO (x) + 1); 1906: else if (GET_CODE (x) == MEM) 1907: { 1908: /* Handle possible auto-increment. Since it is pre-increment and 1909: we have already done it, we can just use an offset of four. */ 1910: if (GET_CODE (XEXP (x, 0)) == PRE_INC 1911: || GET_CODE (XEXP (x, 0)) == PRE_DEC) 1912: output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); 1913: else 1914: output_address (plus_constant (XEXP (x, 0), 4)); 1915: } 1916: return; 1917: 1918: case 'm': 1919: /* MB value for a mask operand. */ 1920: if (! mask_operand (x, VOIDmode)) 1921: output_operand_lossage ("invalid %%m value"); 1922: 1923: val = INT_LOWPART (x); 1924: 1925: /* If the high bit is set and the low bit is not, the value is zero. 1926: If the high bit is zero, the value is the first 1 bit we find from 1927: the left. */ 1928: if (val < 0 && (val & 1) == 0) 1929: { 1930: fprintf (file, "0"); 1931: return; 1932: } 1933: else if (val >= 0) 1934: { 1935: for (i = 1; i < 32; i++) 1936: if ((val <<= 1) < 0) 1937: break; 1938: fprintf (file, "%d", i); 1939: return; 1940: } 1941: 1942: /* Otherwise, look for the first 0 bit from the right. The result is its 1943: number plus 1. We know the low-order bit is one. */ 1944: for (i = 0; i < 32; i++) 1945: if (((val >>= 1) & 1) == 0) 1946: break; 1947: 1948: /* If we ended in ...01, I would be 0. The correct value is 31, so 1949: we want 31 - i. */ 1950: fprintf (file, "%d", 31 - i); 1951: return; 1952: 1953: case 'M': 1954: /* ME value for a mask operand. */ 1955: if (! mask_operand (x, VOIDmode)) 1956: output_operand_lossage ("invalid %%m value"); 1957: 1958: val = INT_LOWPART (x); 1959: 1960: /* If the low bit is set and the high bit is not, the value is 31. 1961: If the low bit is zero, the value is the first 1 bit we find from 1962: the right. */ 1963: if ((val & 1) && val >= 0) 1964: { 1.1.1.2 root 1965: fputs ("31", file); 1.1 root 1966: return; 1967: } 1968: else if ((val & 1) == 0) 1969: { 1970: for (i = 0; i < 32; i++) 1971: if ((val >>= 1) & 1) 1972: break; 1973: 1974: /* If we had ....10, I would be 0. The result should be 1975: 30, so we need 30 - i. */ 1976: fprintf (file, "%d", 30 - i); 1977: return; 1978: } 1979: 1980: /* Otherwise, look for the first 0 bit from the left. The result is its 1981: number minus 1. We know the high-order bit is one. */ 1982: for (i = 0; i < 32; i++) 1983: if ((val <<= 1) >= 0) 1984: break; 1985: 1986: fprintf (file, "%d", i); 1987: return; 1988: 1989: case 'N': 1990: /* Write the number of elements in the vector times 4. */ 1991: if (GET_CODE (x) != PARALLEL) 1992: output_operand_lossage ("invalid %%N value"); 1993: 1994: fprintf (file, "%d", XVECLEN (x, 0) * 4); 1995: return; 1996: 1997: case 'O': 1998: /* Similar, but subtract 1 first. */ 1999: if (GET_CODE (x) != PARALLEL) 2000: output_operand_lossage ("invalid %%N value"); 2001: 2002: fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); 2003: return; 2004: 2005: case 'p': 2006: /* X is a CONST_INT that is a power of two. Output the logarithm. */ 2007: if (! INT_P (x) 2008: || (i = exact_log2 (INT_LOWPART (x))) < 0) 2009: output_operand_lossage ("invalid %%p value"); 2010: 2011: fprintf (file, "%d", i); 2012: return; 2013: 2014: case 'P': 2015: /* The operand must be an indirect memory reference. The result 2016: is the register number. */ 2017: if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG 2018: || REGNO (XEXP (x, 0)) >= 32) 2019: output_operand_lossage ("invalid %%P value"); 2020: 2021: fprintf (file, "%d", REGNO (XEXP (x, 0))); 2022: return; 2023: 2024: case 'R': 2025: /* X is a CR register. Print the mask for `mtcrf'. */ 2026: if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) 2027: output_operand_lossage ("invalid %%R value"); 2028: else 2029: fprintf (file, "%d", 128 >> (REGNO (x) - 68)); 2030: return; 2031: 2032: case 's': 2033: /* Low 5 bits of 32 - value */ 2034: if (! INT_P (x)) 2035: output_operand_lossage ("invalid %%s value"); 2036: 2037: fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); 2038: return; 2039: 2040: case 't': 2041: /* Write 12 if this jump operation will branch if true, 4 otherwise. 2042: All floating-point operations except NE branch true and integer 2043: EQ, LT, GT, LTU and GTU also branch true. */ 2044: if (GET_RTX_CLASS (GET_CODE (x)) != '<') 2045: output_operand_lossage ("invalid %%t value"); 2046: 2047: else if ((GET_MODE (XEXP (x, 0)) == CCFPmode 2048: && GET_CODE (x) != NE) 2049: || GET_CODE (x) == EQ 2050: || GET_CODE (x) == LT || GET_CODE (x) == GT 2051: || GET_CODE (x) == LTU || GET_CODE (x) == GTU) 1.1.1.2 root 2052: fputs ("12", file); 1.1 root 2053: else 1.1.1.2 root 2054: putc ('4', file); 1.1 root 2055: return; 2056: 2057: case 'T': 2058: /* Opposite of 't': write 4 if this jump operation will branch if true, 2059: 12 otherwise. */ 2060: if (GET_RTX_CLASS (GET_CODE (x)) != '<') 2061: output_operand_lossage ("invalid %%t value"); 2062: 2063: else if ((GET_MODE (XEXP (x, 0)) == CCFPmode 2064: && GET_CODE (x) != NE) 2065: || GET_CODE (x) == EQ 2066: || GET_CODE (x) == LT || GET_CODE (x) == GT 2067: || GET_CODE (x) == LTU || GET_CODE (x) == GTU) 1.1.1.2 root 2068: putc ('4', file); 1.1 root 2069: else 1.1.1.2 root 2070: fputs ("12", file); 1.1 root 2071: return; 2072: 2073: case 'u': 2074: /* High-order 16 bits of constant. */ 2075: if (! INT_P (x)) 2076: output_operand_lossage ("invalid %%u value"); 2077: 1.1.1.2 root 2078: fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); 1.1 root 2079: return; 2080: 2081: case 'U': 2082: /* Print `u' if this has an auto-increment or auto-decrement. */ 2083: if (GET_CODE (x) == MEM 2084: && (GET_CODE (XEXP (x, 0)) == PRE_INC 2085: || GET_CODE (XEXP (x, 0)) == PRE_DEC)) 1.1.1.2 root 2086: putc ('u', file); 1.1 root 2087: return; 2088: 2089: case 'w': 2090: /* If constant, low-order 16 bits of constant, signed. Otherwise, write 2091: normally. */ 2092: if (INT_P (x)) 2093: fprintf (file, "%d", 2094: (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); 2095: else 2096: print_operand (file, x, 0); 2097: return; 2098: 2099: case 'W': 2100: /* If constant, low-order 16 bits of constant, unsigned. 2101: Otherwise, write normally. */ 2102: if (INT_P (x)) 2103: fprintf (file, "%d", INT_LOWPART (x) & 0xffff); 2104: else 2105: print_operand (file, x, 0); 2106: return; 2107: 2108: case 'X': 2109: if (GET_CODE (x) == MEM 2110: && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) 1.1.1.2 root 2111: putc ('x', file); 1.1 root 2112: return; 2113: 2114: case 'Y': 2115: /* Like 'L', for third word of TImode */ 2116: if (GET_CODE (x) == REG) 2117: fprintf (file, "%d", REGNO (x) + 2); 2118: else if (GET_CODE (x) == MEM) 2119: { 2120: if (GET_CODE (XEXP (x, 0)) == PRE_INC 2121: || GET_CODE (XEXP (x, 0)) == PRE_DEC) 2122: output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); 2123: else 2124: output_address (plus_constant (XEXP (x, 0), 8)); 2125: } 2126: return; 2127: 2128: case 'z': 2129: /* X is a SYMBOL_REF. Write out the name preceded by a 2130: period and without any trailing data in brackets. Used for function 1.1.1.4 root 2131: names. If we are configured for System V (or the embedded ABI) on 2132: the PowerPC, do not emit the period, since those systems do not use 2133: TOCs and the like. */ 1.1 root 2134: if (GET_CODE (x) != SYMBOL_REF) 2135: abort (); 2136: 1.1.1.4 root 2137: #ifndef USING_SVR4_H 1.1.1.2 root 2138: putc ('.', file); 1.1.1.4 root 2139: #endif 1.1 root 2140: RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); 2141: return; 2142: 2143: case 'Z': 2144: /* Like 'L', for last word of TImode. */ 2145: if (GET_CODE (x) == REG) 2146: fprintf (file, "%d", REGNO (x) + 3); 2147: else if (GET_CODE (x) == MEM) 2148: { 2149: if (GET_CODE (XEXP (x, 0)) == PRE_INC 2150: || GET_CODE (XEXP (x, 0)) == PRE_DEC) 2151: output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); 2152: else 2153: output_address (plus_constant (XEXP (x, 0), 12)); 2154: } 2155: return; 2156: 2157: case 0: 2158: if (GET_CODE (x) == REG) 2159: fprintf (file, "%s", reg_names[REGNO (x)]); 2160: else if (GET_CODE (x) == MEM) 2161: { 2162: /* We need to handle PRE_INC and PRE_DEC here, since we need to 2163: know the width from the mode. */ 2164: if (GET_CODE (XEXP (x, 0)) == PRE_INC) 2165: fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), 2166: REGNO (XEXP (XEXP (x, 0), 0))); 2167: else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) 2168: fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), 2169: REGNO (XEXP (XEXP (x, 0), 0))); 2170: else 2171: output_address (XEXP (x, 0)); 2172: } 2173: else 2174: output_addr_const (file, x); 1.1.1.2 root 2175: return; 1.1 root 2176: 2177: default: 2178: output_operand_lossage ("invalid %%xn code"); 2179: } 2180: } 2181: 2182: /* Print the address of an operand. */ 2183: 2184: void 2185: print_operand_address (file, x) 2186: FILE *file; 2187: register rtx x; 2188: { 2189: if (GET_CODE (x) == REG) 1.1.1.4 root 2190: fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); 1.1 root 2191: else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) 2192: { 2193: output_addr_const (file, x); 1.1.1.2 root 2194: /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead 2195: of the toc pointer. */ 1.1.1.4 root 2196: #ifdef TARGET_NO_TOC 2197: if (TARGET_NO_TOC) 2198: ; 1.1.1.2 root 2199: else 1.1.1.4 root 2200: #endif 2201: fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]); 1.1 root 2202: } 2203: else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) 2204: { 2205: if (REGNO (XEXP (x, 0)) == 0) 1.1.1.4 root 2206: fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], 2207: reg_names[ REGNO (XEXP (x, 0)) ]); 1.1 root 2208: else 1.1.1.4 root 2209: fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], 2210: reg_names[ REGNO (XEXP (x, 1)) ]); 1.1 root 2211: } 2212: else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 1.1.1.4 root 2213: fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); 2214: else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM 2215: && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1))) 2216: { 2217: output_addr_const (file, XEXP (x, 1)); 2218: fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); 2219: } 1.1 root 2220: else 2221: abort (); 2222: } 2223: 2224: /* This page contains routines that are used to determine what the function 2225: prologue and epilogue code will do and write them out. */ 2226: 2227: /* Return the first fixed-point register that is required to be saved. 32 if 2228: none. */ 2229: 2230: int 2231: first_reg_to_save () 2232: { 2233: int first_reg; 2234: 2235: /* Find lowest numbered live register. */ 2236: for (first_reg = 13; first_reg <= 31; first_reg++) 2237: if (regs_ever_live[first_reg]) 2238: break; 2239: 2240: /* If profiling, then we must save/restore every register that contains 2241: a parameter before/after the .mcount call. Use registers from 30 down 2242: to 23 to do this. Don't use the frame pointer in reg 31. 2243: 2244: For now, save enough room for all of the parameter registers. */ 1.1.1.4 root 2245: #ifndef USING_SVR4_H 1.1 root 2246: if (profile_flag) 2247: if (first_reg > 23) 2248: first_reg = 23; 1.1.1.4 root 2249: #endif 1.1 root 2250: 2251: return first_reg; 2252: } 2253: 2254: /* Similar, for FP regs. */ 2255: 2256: int 2257: first_fp_reg_to_save () 2258: { 2259: int first_reg; 2260: 2261: /* Find lowest numbered live register. */ 2262: for (first_reg = 14 + 32; first_reg <= 63; first_reg++) 2263: if (regs_ever_live[first_reg]) 2264: break; 2265: 2266: return first_reg; 2267: } 2268: 2269: /* Return non-zero if this function makes calls. */ 2270: 2271: int 2272: rs6000_makes_calls () 2273: { 2274: rtx insn; 2275: 2276: /* If we are profiling, we will be making a call to mcount. */ 2277: if (profile_flag) 2278: return 1; 2279: 2280: for (insn = get_insns (); insn; insn = next_insn (insn)) 2281: if (GET_CODE (insn) == CALL_INSN) 2282: return 1; 2283: 2284: return 0; 2285: } 2286: 1.1.1.4 root 2287: 2288: /* Calculate the stack information for the current function. This is 2289: complicated by having two separate calling sequences, the AIX calling 2290: sequence and the V.4 calling sequence. 2291: 2292: AIX stack frames look like: 2293: 2294: SP----> +---------------------------------------+ 2295: | back chain to caller | 0 2296: +---------------------------------------+ 2297: | saved CR | 4 2298: +---------------------------------------+ 2299: | saved LR | 8 2300: +---------------------------------------+ 2301: | reserved for compilers | 12 2302: +---------------------------------------+ 2303: | reserved for binders | 16 2304: +---------------------------------------+ 2305: | saved TOC pointer | 20 2306: +---------------------------------------+ 2307: | Parameter save area (P) | 24 2308: +---------------------------------------+ 2309: | Alloca space (A) | 24+P 2310: +---------------------------------------+ 2311: | Local variable space (L) | 24+P+A 2312: +---------------------------------------+ 2313: | Save area for GP registers (G) | 24+P+A+L 2314: +---------------------------------------+ 2315: | Save area for FP registers (F) | 24+P+A+L+G 2316: +---------------------------------------+ 2317: old SP->| back chain to caller's caller | 2318: +---------------------------------------+ 2319: 2320: V.4 stack frames look like: 2321: 2322: SP----> +---------------------------------------+ 2323: | back chain to caller | 0 2324: +---------------------------------------+ 2325: | caller's saved LR | 4 2326: +---------------------------------------+ 2327: | Parameter save area (P) | 8 2328: +---------------------------------------+ 2329: | Alloca space (A) | 8+P 2330: +---------------------------------------+ 2331: | Varargs save area (V) | 8+P+A 2332: +---------------------------------------+ 2333: | Local variable space (L) | 8+P+A+V 2334: +---------------------------------------+ 2335: | saved CR (C) | 8+P+A+V+L 2336: +---------------------------------------+ 2337: | Save area for GP registers (G) | 8+P+A+V+L+C 2338: +---------------------------------------+ 2339: | Save area for FP registers (F) | 8+P+A+V+L+C+G 2340: +---------------------------------------+ 2341: old SP->| back chain to caller's caller | 2342: +---------------------------------------+ 2343: */ 2344: 2345: rs6000_stack_t * 2346: rs6000_stack_info () 2347: { 2348: static rs6000_stack_t info, zero_info; 2349: rs6000_stack_t *info_ptr = &info; 2350: int reg_size = TARGET_64BIT ? 8 : 4; 2351: enum rs6000_abi abi; 2352: 2353: /* Zero all fields portably */ 2354: info = zero_info; 2355: 2356: /* Select which calling sequence */ 2357: #ifdef TARGET_V4_CALLS 2358: if (TARGET_V4_CALLS) 2359: abi = ABI_V4; 2360: else 2361: #endif 2362: abi = ABI_AIX; 1.1 root 2363: 1.1.1.4 root 2364: info_ptr->abi = abi; 2365: 2366: /* Calculate which registers need to be saved & save area size */ 2367: info_ptr->first_gp_reg_save = first_reg_to_save (); 2368: info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); 2369: 2370: info_ptr->first_fp_reg_save = first_fp_reg_to_save (); 2371: info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); 2372: 2373: /* Does this function call anything? */ 2374: info_ptr->calls_p = rs6000_makes_calls (); 2375: 2376: /* Determine if we need to save the link register */ 2377: if (regs_ever_live[65] || profile_flag 2378: #ifdef TARGET_RELOCATABLE 2379: || (TARGET_RELOCATABLE && (get_pool_size () != 0)) 2380: #endif 2381: || (info_ptr->first_fp_reg_save != 64 2382: && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) 2383: || (abi == ABI_V4 && current_function_calls_alloca) 2384: || info_ptr->calls_p) 2385: { 2386: info_ptr->lr_save_p = 1; 2387: regs_ever_live[65] = 1; 2388: } 2389: 2390: /* Determine if we need to save the condition code registers */ 2391: if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]) 2392: { 2393: info_ptr->cr_save_p = 1; 2394: if (abi == ABI_V4) 2395: info_ptr->cr_size = reg_size; 2396: } 2397: 2398: /* Determine various sizes */ 2399: info_ptr->reg_size = reg_size; 2400: info_ptr->fixed_size = RS6000_SAVE_AREA; 2401: info_ptr->varargs_size = RS6000_VARARGS_AREA; 2402: info_ptr->vars_size = ALIGN (get_frame_size (), 8); 2403: info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8); 2404: info_ptr->save_size = ALIGN (info_ptr->fp_size + info_ptr->gp_size + info_ptr->cr_size, 8); 2405: info_ptr->total_size = ALIGN (info_ptr->vars_size 2406: + info_ptr->parm_size 2407: + info_ptr->save_size 2408: + info_ptr->varargs_size 2409: + info_ptr->fixed_size, STACK_BOUNDARY / BITS_PER_UNIT); 2410: 2411: /* Determine if we need to allocate any stack frame. 2412: For AIX We need to push the stack if a frame pointer is needed (because 2413: the stack might be dynamically adjusted), if we are debugging, if the 2414: total stack size is more than 220 bytes, or if we make calls. 2415: 2416: For V.4 we don't have the stack cushion that AIX uses, but assume that 2417: the debugger can handle stackless frames. */ 2418: 2419: if (info_ptr->calls_p) 2420: info_ptr->push_p = 1; 2421: 2422: else if (abi == ABI_V4) 2423: info_ptr->push_p = (info_ptr->total_size > info_ptr->fixed_size 2424: || info_ptr->lr_save_p); 2425: 2426: else 2427: info_ptr->push_p = (frame_pointer_needed 2428: || write_symbols != NO_DEBUG 2429: || info_ptr->total_size > 220); 2430: 2431: /* Calculate the offsets */ 2432: info_ptr->fp_save_offset = - info_ptr->fp_size; 2433: info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; 2434: switch (abi) 2435: { 2436: default: 2437: info_ptr->cr_save_offset = 4; 2438: info_ptr->lr_save_offset = 8; 2439: break; 2440: 2441: case ABI_V4: 2442: info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size; 2443: info_ptr->lr_save_offset = reg_size; 2444: break; 2445: } 2446: 2447: /* Zero offsets if we're not saving those registers */ 2448: if (!info_ptr->fp_size) 2449: info_ptr->fp_save_offset = 0; 2450: 2451: if (!info_ptr->gp_size) 2452: info_ptr->gp_save_offset = 0; 2453: 2454: if (!info_ptr->lr_save_p) 2455: info_ptr->lr_save_offset = 0; 2456: 2457: if (!info_ptr->cr_save_p) 2458: info_ptr->cr_save_offset = 0; 2459: 2460: return info_ptr; 2461: } 2462: 2463: void 2464: debug_stack_info (info) 2465: rs6000_stack_t *info; 1.1 root 2466: { 1.1.1.4 root 2467: char *abi_string; 2468: 2469: if (!info) 2470: info = rs6000_stack_info (); 2471: 2472: fprintf (stderr, "\nStack information for function %s:\n", 2473: ((current_function_decl && DECL_NAME (current_function_decl)) 2474: ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) 2475: : "<unknown>")); 2476: 2477: switch (info->abi) 2478: { 2479: default: abi_string = "Unknown"; break; 2480: case ABI_NONE: abi_string = "NONE"; break; 2481: case ABI_AIX: abi_string = "AIX"; break; 2482: case ABI_V4: abi_string = "V.4"; break; 2483: } 2484: 2485: fprintf (stderr, "\tABI = %5s\n", abi_string); 2486: 2487: if (info->first_gp_reg_save != 32) 2488: fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); 2489: 2490: if (info->first_fp_reg_save != 64) 2491: fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); 2492: 2493: if (info->lr_save_p) 2494: fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); 2495: 2496: if (info->cr_save_p) 2497: fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); 2498: 2499: if (info->push_p) 2500: fprintf (stderr, "\tpush_p = %5d\n", info->push_p); 2501: 2502: if (info->calls_p) 2503: fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); 2504: 2505: if (info->gp_save_offset) 2506: fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); 1.1 root 2507: 1.1.1.4 root 2508: if (info->fp_save_offset) 2509: fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); 1.1 root 2510: 1.1.1.4 root 2511: if (info->lr_save_offset) 2512: fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); 2513: 2514: if (info->cr_save_offset) 2515: fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); 2516: 2517: if (info->varargs_save_offset) 2518: fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); 2519: 2520: if (info->total_size) 2521: fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); 2522: 2523: if (info->varargs_size) 2524: fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); 2525: 2526: if (info->vars_size) 2527: fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); 2528: 2529: if (info->parm_size) 2530: fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); 2531: 2532: if (info->fixed_size) 2533: fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); 2534: 2535: if (info->gp_size) 2536: fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); 2537: 2538: if (info->fp_size) 2539: fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); 2540: 2541: if (info->cr_size) 2542: fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); 2543: 2544: if (info->save_size) 2545: fprintf (stderr, "\tsave_size = %5d\n", info->save_size); 2546: 2547: if (info->reg_size != 4) 2548: fprintf (stderr, "\treg_size = %5d\n", info->reg_size); 2549: 2550: fprintf (stderr, "\n"); 1.1 root 2551: } 2552: 1.1.1.4 root 2553: 2554: 2555: #ifdef USING_SVR4_H 2556: /* Write out a System V.4 style traceback table before the prologue 2557: 2558: At present, only emit the basic tag table (ie, do not emit tag_types other 2559: than 0, which might use more than 1 tag word). 2560: 2561: The first tag word looks like: 2562: 2563: 0 1 2 3 2564: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2565: +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2566: | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f| 2567: +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2568: 2569: */ 2570: 2571: void 2572: svr4_traceback (file, name, decl) 2573: FILE *file; 2574: tree name, decl; 2575: { 2576: rs6000_stack_t *info = rs6000_stack_info (); 2577: long tag; 2578: long version = 0; /* version number */ 2579: long tag_type = 0; /* function type */ 2580: long extended_tag = 0; /* additional tag words needed */ 2581: long spare = 0; /* reserved for future use */ 2582: long fpscr_max = 0; /* 1 if the function has a FPSCR save word */ 2583: long fpr_max = 64 - info->first_fp_reg_save; /* # of floating point registers saved */ 2584: long gpr_max = 32 - info->first_gp_reg_save; /* # of general purpose registers saved */ 2585: long alloca_reg; /* stack/frame register */ 2586: 2587: if (frame_pointer_needed) 2588: alloca_reg = 31; 2589: 2590: else if (info->push_p != 0) 2591: alloca_reg = 1; 2592: 2593: else 2594: alloca_reg = 0; 1.1 root 2595: 1.1.1.4 root 2596: tag = ((version << 24) 2597: | (tag_type << 21) 2598: | (extended_tag << 20) 2599: | (spare << 19) 2600: | (alloca_reg << 14) 2601: | (fpr_max << 9) 2602: | (gpr_max << 4) 2603: | (info->push_p << 3) 2604: | (info->lr_save_p << 2) 2605: | (info->cr_save_p << 1) 2606: | (fpscr_max << 0)); 2607: 2608: fprintf (file, "\t.long 0x%lx\n", tag); 2609: } 2610: 2611: #endif /* USING_SVR4_H */ 2612: 2613: /* Write function prologue. */ 1.1 root 2614: void 2615: output_prolog (file, size) 2616: FILE *file; 2617: int size; 2618: { 1.1.1.4 root 2619: rs6000_stack_t *info = rs6000_stack_info (); 2620: char *store_reg = (TARGET_64BIT) ? "\tstd %s,%d(%s)" : "\t{st|stw} %s,%d(%s)\n"; 1.1.1.5 ! root 2621: int reg_size = info->reg_size; ! 2622: int sp_reg = 1; ! 2623: int sp_offset = 0; 1.1 root 2624: 1.1.1.4 root 2625: if (TARGET_DEBUG_STACK) 2626: debug_stack_info (info); 1.1 root 2627: 2628: /* Write .extern for any function we will call to save and restore fp 2629: values. */ 1.1.1.4 root 2630: #ifndef USING_SVR4_H 2631: if (info->first_fp_reg_save < 62) 2632: fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", 2633: SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, 2634: RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); 2635: #endif 1.1 root 2636: 2637: /* Write .extern for truncation routines, if needed. */ 2638: if (rs6000_trunc_used && ! trunc_defined) 2639: { 1.1.1.3 root 2640: fprintf (file, "\t.extern .%s\n\t.extern .%s\n", 2641: RS6000_ITRUNC, RS6000_UITRUNC); 1.1 root 2642: trunc_defined = 1; 2643: } 1.1.1.4 root 2644: 1.1.1.3 root 2645: /* Write .extern for AIX common mode routines, if needed. */ 2646: if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) 2647: { 2648: fputs ("\t.extern __mulh\n", file); 2649: fputs ("\t.extern __mull\n", file); 2650: fputs ("\t.extern __divss\n", file); 2651: fputs ("\t.extern __divus\n", file); 2652: fputs ("\t.extern __quoss\n", file); 2653: fputs ("\t.extern __quous\n", file); 2654: common_mode_defined = 1; 2655: } 1.1 root 2656: 1.1.1.5 ! root 2657: /* For V.4, update stack before we do any saving and set back pointer. */ ! 2658: #ifdef USING_SVR4_H ! 2659: if (info->push_p && TARGET_V4_CALLS) ! 2660: { ! 2661: if (info->total_size < 32767) ! 2662: { ! 2663: asm_fprintf (file, ! 2664: (!TARGET_64BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n", ! 2665: reg_names[1], - info->total_size, reg_names[1]); ! 2666: sp_offset = info->total_size; ! 2667: } ! 2668: else ! 2669: { ! 2670: int neg_size = - info->total_size; ! 2671: sp_reg = 12; ! 2672: asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]); ! 2673: asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", ! 2674: reg_names[0], (neg_size >> 16) & 0xffff, ! 2675: reg_names[0], reg_names[0], neg_size & 0xffff); ! 2676: asm_fprintf (file, ! 2677: (!TARGET_64BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n", ! 2678: reg_names[1], reg_names[1], reg_names[0]); ! 2679: } ! 2680: } ! 2681: #endif ! 2682: 1.1 root 2683: /* If we use the link register, get it into r0. */ 1.1.1.4 root 2684: if (info->lr_save_p) 2685: asm_fprintf (file, "\tmflr %s\n", reg_names[0]); 1.1 root 2686: 2687: /* If we need to save CR, put it into r12. */ 1.1.1.5 ! root 2688: if (info->cr_save_p && sp_reg != 12) 1.1.1.4 root 2689: asm_fprintf (file, "\tmfcr %s\n", reg_names[12]); 1.1 root 2690: 2691: /* Do any required saving of fpr's. If only one or two to save, do it 1.1.1.2 root 2692: ourself. Otherwise, call function. Note that since they are statically 2693: linked, we do not need a nop following them. */ 1.1.1.4 root 2694: if (FP_SAVE_INLINE (info->first_fp_reg_save)) 2695: { 2696: int regno = info->first_fp_reg_save; 1.1.1.5 ! root 2697: int loc = info->fp_save_offset + sp_offset; 1.1.1.4 root 2698: 2699: for ( ; regno < 64; regno++, loc += 8) 1.1.1.5 ! root 2700: asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); 1.1.1.4 root 2701: } 2702: else if (info->first_fp_reg_save != 64) 2703: asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, 2704: info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); 1.1 root 2705: 2706: /* Now save gpr's. */ 1.1.1.4 root 2707: if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) 1.1.1.2 root 2708: { 1.1.1.4 root 2709: int regno = info->first_gp_reg_save; 1.1.1.5 ! root 2710: int loc = info->gp_save_offset + sp_offset; 1.1.1.2 root 2711: 1.1.1.4 root 2712: for ( ; regno < 32; regno++, loc += reg_size) 1.1.1.5 ! root 2713: asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]); 1.1.1.2 root 2714: } 2715: 1.1.1.4 root 2716: else if (info->first_gp_reg_save != 32) 2717: asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n", 2718: reg_names[info->first_gp_reg_save], 1.1.1.5 ! root 2719: info->gp_save_offset + sp_offset, ! 2720: reg_names[sp_reg]); 1.1 root 2721: 2722: /* Save lr if we used it. */ 1.1.1.4 root 2723: if (info->lr_save_p) 1.1.1.5 ! root 2724: asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset, ! 2725: reg_names[sp_reg]); 1.1 root 2726: 2727: /* Save CR if we use any that must be preserved. */ 1.1.1.4 root 2728: if (info->cr_save_p) 1.1.1.5 ! root 2729: { ! 2730: if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */ ! 2731: { ! 2732: asm_fprintf (file, "\tmfcr %s\n", reg_names[0]); ! 2733: asm_fprintf (file, store_reg, reg_names[0], ! 2734: info->cr_save_offset + sp_offset, ! 2735: reg_names[sp_reg]); ! 2736: } ! 2737: else ! 2738: asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset, ! 2739: reg_names[sp_reg]); ! 2740: } 1.1 root 2741: 1.1.1.5 ! root 2742: /* Update stack and set back pointer and we have already done so for V.4. */ ! 2743: if (info->push_p ! 2744: #ifdef USING_SVR4_H ! 2745: && TARGET_AIX_CALLS ! 2746: #endif ! 2747: ) 1.1 root 2748: { 1.1.1.4 root 2749: if (info->total_size < 32767) 2750: asm_fprintf (file, 2751: (TARGET_64BIT) ? "\tstdu %s,%d(%s)\n" : "\t{stu|stwu} %s,%d(%s)\n", 2752: reg_names[1], - info->total_size, reg_names[1]); 1.1 root 2753: else 2754: { 1.1.1.4 root 2755: int neg_size = - info->total_size; 2756: asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", 2757: reg_names[0], (neg_size >> 16) & 0xffff, 2758: reg_names[0], reg_names[0], neg_size & 0xffff); 2759: asm_fprintf (file, 2760: (TARGET_64BIT) ? "\tstdux %s,%s,%s\n" : "\t{stux|stwux} %s,%s,%s\n", 2761: reg_names[1], reg_names[1], reg_names[0]); 1.1 root 2762: } 2763: } 2764: 2765: /* Set frame pointer, if needed. */ 2766: if (frame_pointer_needed) 1.1.1.4 root 2767: asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]); 1.1.1.2 root 2768: 2769: /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the 2770: TOC_TABLE address into register 30. */ 1.1.1.4 root 2771: if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) 1.1.1.3 root 2772: { 1.1.1.4 root 2773: char buf[256]; 1.1.1.3 root 2774: 1.1.1.4 root 2775: #ifdef USING_SVR4_H 2776: if (TARGET_RELOCATABLE) 2777: { 2778: ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); 2779: fprintf (file, "\tbl "); 2780: assemble_name (file, buf); 2781: fprintf (file, "\n"); 2782: 2783: ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno); 2784: fprintf (file, "\tmflr %s\n", reg_names[30]); 2785: 2786: if (TARGET_POWERPC64) 2787: fprintf (file, "\tld"); 2788: else if (TARGET_NEW_MNEMONICS) 2789: fprintf (file, "\tlwz"); 2790: else 2791: fprintf (file, "\tl"); 2792: 2793: fprintf (file, " %s,(", reg_names[0]); 2794: ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); 2795: assemble_name (file, buf); 2796: fprintf (file, "-"); 2797: ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); 2798: assemble_name (file, buf); 2799: fprintf (file, ")(%s)\n", reg_names[30]); 2800: asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", 2801: reg_names[30], reg_names[0], reg_names[30]); 2802: rs6000_pic_labelno++; 2803: } 2804: else if (!TARGET_64BIT) 2805: { 2806: ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); 2807: asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]); 2808: assemble_name (file, buf); 2809: asm_fprintf (file, "@ha\n"); 2810: if (TARGET_NEW_MNEMONICS) 2811: { 2812: asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]); 2813: assemble_name (file, buf); 2814: asm_fprintf (file, "@l\n"); 2815: } 2816: else 2817: { 2818: asm_fprintf (file, "\tcal %s,", reg_names[30]); 2819: assemble_name (file, buf); 2820: asm_fprintf (file, "@l(%s)\n", reg_names[30]); 2821: } 2822: } 2823: else 2824: abort (); 2825: 2826: #else /* !USING_SVR4_H */ 1.1.1.3 root 2827: ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); 1.1.1.4 root 2828: asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]); 1.1.1.3 root 2829: assemble_name (file, buf); 1.1.1.4 root 2830: asm_fprintf (file, "(%s)\n", reg_names[2]); 2831: #endif /* USING_SVR4_H */ 1.1.1.3 root 2832: } 1.1 root 2833: } 2834: 2835: /* Write function epilogue. */ 2836: 2837: void 2838: output_epilog (file, size) 2839: FILE *file; 2840: int size; 2841: { 1.1.1.4 root 2842: rs6000_stack_t *info = rs6000_stack_info (); 2843: char *load_reg = (TARGET_64BIT) ? "\tld %s,%d(%s)" : "\t{l|lwz} %s,%d(%s)\n"; 1.1 root 2844: rtx insn = get_last_insn (); 1.1.1.5 ! root 2845: int sp_reg = 1; ! 2846: int sp_offset = 0; 1.1.1.4 root 2847: int i; 1.1 root 2848: 1.1.1.4 root 2849: /* Forget about any temporaries created */ 2850: for (i = 0; i < NUM_MACHINE_MODES; i++) 2851: stack_temps[i] = NULL_RTX; 1.1 root 2852: 2853: /* If the last insn was a BARRIER, we don't have to write anything except 2854: the trace table. */ 2855: if (GET_CODE (insn) == NOTE) 2856: insn = prev_nonnote_insn (insn); 2857: if (insn == 0 || GET_CODE (insn) != BARRIER) 2858: { 2859: /* If we have a frame pointer, a call to alloca, or a large stack 2860: frame, restore the old stack pointer using the backchain. Otherwise, 2861: we know what size to update it with. */ 2862: if (frame_pointer_needed || current_function_calls_alloca 1.1.1.4 root 2863: || info->total_size > 32767) 1.1.1.5 ! root 2864: { ! 2865: /* Under V.4, don't reset the stack pointer until after we're done ! 2866: loading the saved registers. */ ! 2867: #ifdef USING_SVR4_H ! 2868: if (TARGET_V4_CALLS) ! 2869: sp_reg = 11; ! 2870: #endif ! 2871: ! 2872: asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]); ! 2873: } 1.1.1.4 root 2874: else if (info->push_p) 2875: { 1.1.1.5 ! root 2876: #ifdef USING_SVR4_H ! 2877: if (TARGET_V4_CALLS) ! 2878: sp_offset = info->total_size; ! 2879: else ! 2880: #endif 1.1.1.4 root 2881: if (TARGET_NEW_MNEMONICS) 2882: asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size); 2883: else 2884: asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]); 2885: } 1.1 root 2886: 2887: /* Get the old lr if we saved it. */ 1.1.1.4 root 2888: if (info->lr_save_p) 1.1.1.5 ! root 2889: asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]); 1.1 root 2890: 2891: /* Get the old cr if we saved it. */ 1.1.1.4 root 2892: if (info->cr_save_p) 1.1.1.5 ! root 2893: asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]); 1.1 root 2894: 2895: /* Set LR here to try to overlap restores below. */ 1.1.1.4 root 2896: if (info->lr_save_p) 2897: asm_fprintf (file, "\tmtlr %s\n", reg_names[0]); 1.1 root 2898: 2899: /* Restore gpr's. */ 1.1.1.4 root 2900: if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) 1.1.1.2 root 2901: { 1.1.1.4 root 2902: int regno = info->first_gp_reg_save; 1.1.1.5 ! root 2903: int loc = info->gp_save_offset + sp_offset; 1.1.1.4 root 2904: int reg_size = (TARGET_64BIT) ? 8 : 4; 1.1.1.2 root 2905: 1.1.1.4 root 2906: for ( ; regno < 32; regno++, loc += reg_size) 1.1.1.5 ! root 2907: asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]); 1.1.1.2 root 2908: } 2909: 1.1.1.4 root 2910: else if (info->first_gp_reg_save != 32) 2911: asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n", 2912: reg_names[info->first_gp_reg_save], 1.1.1.5 ! root 2913: info->gp_save_offset + sp_offset, ! 2914: reg_names[sp_reg]); 1.1 root 2915: 2916: /* Restore fpr's if we can do it without calling a function. */ 1.1.1.4 root 2917: if (FP_SAVE_INLINE (info->first_fp_reg_save)) 2918: { 2919: int regno = info->first_fp_reg_save; 1.1.1.5 ! root 2920: int loc = info->fp_save_offset + sp_offset; 1.1.1.4 root 2921: 2922: for ( ; regno < 64; regno++, loc += 8) 1.1.1.5 ! root 2923: asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); 1.1.1.4 root 2924: } 1.1 root 2925: 2926: /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 2927: that were used. */ 1.1.1.4 root 2928: if (info->cr_save_p) 2929: asm_fprintf (file, "\tmtcrf %d,%s\n", 1.1.1.2 root 2930: (regs_ever_live[70] != 0) * 0x20 2931: + (regs_ever_live[71] != 0) * 0x10 1.1.1.4 root 2932: + (regs_ever_live[72] != 0) * 0x8, reg_names[12]); 1.1 root 2933: 1.1.1.5 ! root 2934: /* If this is V.4, unwind the stack pointer after all of the loads have been done */ ! 2935: #ifdef USING_SVR4_H ! 2936: if (sp_offset) ! 2937: { ! 2938: if (TARGET_NEW_MNEMONICS) ! 2939: asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset); ! 2940: else ! 2941: asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]); ! 2942: } ! 2943: else if (sp_reg != 1) ! 2944: asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]); ! 2945: #endif ! 2946: 1.1 root 2947: /* If we have to restore more than two FP registers, branch to the 2948: restore function. It will return to our caller. */ 1.1.1.4 root 2949: if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) 2950: asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, 2951: info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); 1.1 root 2952: else 1.1.1.2 root 2953: asm_fprintf (file, "\t{br|blr}\n"); 1.1 root 2954: } 2955: 2956: /* Output a traceback table here. See /usr/include/sys/debug.h for info 1.1.1.3 root 2957: on its format. 1.1 root 2958: 1.1.1.3 root 2959: We don't output a traceback table if -finhibit-size-directive was 2960: used. The documentation for -finhibit-size-directive reads 2961: ``don't output a @code{.size} assembler directive, or anything 2962: else that would cause trouble if the function is split in the 2963: middle, and the two halves are placed at locations far apart in 2964: memory.'' The traceback table has this property, since it 2965: includes the offset from the start of the function to the 1.1.1.4 root 2966: traceback table itself. 2967: 2968: System V.4 Powerpc's (and the embedded ABI derived from it) use a 2969: different traceback table located before the prologue. */ 2970: #ifndef USING_SVR4_H 1.1.1.3 root 2971: if (! flag_inhibit_size_directive) 2972: { 2973: char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 2974: int fixed_parms, float_parms, parm_info; 2975: int i; 2976: 2977: /* Need label immediately before tbtab, so we can compute its offset 2978: from the function start. */ 2979: if (*fname == '*') 2980: ++fname; 2981: ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); 2982: ASM_OUTPUT_LABEL (file, fname); 2983: 2984: /* The .tbtab pseudo-op can only be used for the first eight 2985: expressions, since it can't handle the possibly variable 2986: length fields that follow. However, if you omit the optional 2987: fields, the assembler outputs zeros for all optional fields 2988: anyways, giving each variable length field is minimum length 2989: (as defined in sys/debug.h). Thus we can not use the .tbtab 2990: pseudo-op at all. */ 2991: 2992: /* An all-zero word flags the start of the tbtab, for debuggers 2993: that have to find it by searching forward from the entry 2994: point or from the current pc. */ 2995: fprintf (file, "\t.long 0\n"); 2996: 2997: /* Tbtab format type. Use format type 0. */ 2998: fprintf (file, "\t.byte 0,"); 2999: 3000: /* Language type. Unfortunately, there doesn't seem to be any 3001: official way to get this info, so we use language_string. C 3002: is 0. C++ is 9. No number defined for Obj-C, so use the 3003: value for C for now. */ 3004: if (! strcmp (language_string, "GNU C") 3005: || ! strcmp (language_string, "GNU Obj-C")) 3006: i = 0; 3007: else if (! strcmp (language_string, "GNU F77")) 3008: i = 1; 3009: else if (! strcmp (language_string, "GNU Ada")) 3010: i = 3; 3011: else if (! strcmp (language_string, "GNU PASCAL")) 3012: i = 2; 3013: else if (! strcmp (language_string, "GNU C++")) 3014: i = 9; 3015: else 3016: abort (); 3017: fprintf (file, "%d,", i); 1.1 root 3018: 1.1.1.3 root 3019: /* 8 single bit fields: global linkage (not set for C extern linkage, 3020: apparently a PL/I convention?), out-of-line epilogue/prologue, offset 3021: from start of procedure stored in tbtab, internal function, function 3022: has controlled storage, function has no toc, function uses fp, 3023: function logs/aborts fp operations. */ 3024: /* Assume that fp operations are used if any fp reg must be saved. */ 1.1.1.4 root 3025: fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); 1.1.1.3 root 3026: 3027: /* 6 bitfields: function is interrupt handler, name present in 3028: proc table, function calls alloca, on condition directives 3029: (controls stack walks, 3 bits), saves condition reg, saves 3030: link reg. */ 3031: /* The `function calls alloca' bit seems to be set whenever reg 31 is 3032: set up as a frame pointer, even when there is no alloca call. */ 3033: fprintf (file, "%d,", 3034: ((1 << 6) | (frame_pointer_needed << 5) 1.1.1.4 root 3035: | (info->cr_save_p << 1) | (info->lr_save_p))); 1.1.1.3 root 3036: 3037: /* 3 bitfields: saves backchain, spare bit, number of fpr saved 3038: (6 bits). */ 3039: fprintf (file, "%d,", 1.1.1.4 root 3040: (info->push_p << 7) | (64 - info->first_fp_reg_save)); 1.1.1.3 root 3041: 3042: /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ 3043: fprintf (file, "%d,", (32 - first_reg_to_save ())); 3044: 3045: { 3046: /* Compute the parameter info from the function decl argument 3047: list. */ 3048: tree decl; 3049: int next_parm_info_bit; 3050: 3051: next_parm_info_bit = 31; 3052: parm_info = 0; 3053: fixed_parms = 0; 3054: float_parms = 0; 1.1 root 3055: 1.1.1.3 root 3056: for (decl = DECL_ARGUMENTS (current_function_decl); 3057: decl; decl = TREE_CHAIN (decl)) 3058: { 3059: rtx parameter = DECL_INCOMING_RTL (decl); 3060: enum machine_mode mode = GET_MODE (parameter); 3061: 3062: if (GET_CODE (parameter) == REG) 3063: { 3064: if (GET_MODE_CLASS (mode) == MODE_FLOAT) 3065: { 3066: int bits; 3067: 3068: float_parms++; 3069: 3070: if (mode == SFmode) 3071: bits = 0x2; 3072: else if (mode == DFmode) 3073: bits = 0x3; 3074: else 3075: abort (); 3076: 3077: /* If only one bit will fit, don't or in this entry. */ 3078: if (next_parm_info_bit > 0) 3079: parm_info |= (bits << (next_parm_info_bit - 1)); 3080: next_parm_info_bit -= 2; 3081: } 3082: else 3083: { 3084: fixed_parms += ((GET_MODE_SIZE (mode) 3085: + (UNITS_PER_WORD - 1)) 3086: / UNITS_PER_WORD); 3087: next_parm_info_bit -= 1; 3088: } 3089: } 3090: } 3091: } 1.1 root 3092: 1.1.1.3 root 3093: /* Number of fixed point parameters. */ 3094: /* This is actually the number of words of fixed point parameters; thus 3095: an 8 byte struct counts as 2; and thus the maximum value is 8. */ 3096: fprintf (file, "%d,", fixed_parms); 3097: 3098: /* 2 bitfields: number of floating point parameters (7 bits), parameters 3099: all on stack. */ 3100: /* This is actually the number of fp registers that hold parameters; 3101: and thus the maximum value is 13. */ 3102: /* Set parameters on stack bit if parameters are not in their original 3103: registers, regardless of whether they are on the stack? Xlc 3104: seems to set the bit when not optimizing. */ 3105: fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); 3106: 3107: /* Optional fields follow. Some are variable length. */ 3108: 3109: /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, 3110: 11 double float. */ 3111: /* There is an entry for each parameter in a register, in the order that 3112: they occur in the parameter list. Any intervening arguments on the 3113: stack are ignored. If the list overflows a long (max possible length 3114: 34 bits) then completely leave off all elements that don't fit. */ 3115: /* Only emit this long if there was at least one parameter. */ 3116: if (fixed_parms || float_parms) 3117: fprintf (file, "\t.long %d\n", parm_info); 3118: 3119: /* Offset from start of code to tb table. */ 3120: fprintf (file, "\t.long "); 3121: ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); 3122: RS6000_OUTPUT_BASENAME (file, fname); 3123: fprintf (file, "-."); 3124: RS6000_OUTPUT_BASENAME (file, fname); 3125: fprintf (file, "\n"); 3126: 3127: /* Interrupt handler mask. */ 3128: /* Omit this long, since we never set the interrupt handler bit 3129: above. */ 3130: 3131: /* Number of CTL (controlled storage) anchors. */ 3132: /* Omit this long, since the has_ctl bit is never set above. */ 3133: 3134: /* Displacement into stack of each CTL anchor. */ 3135: /* Omit this list of longs, because there are no CTL anchors. */ 3136: 3137: /* Length of function name. */ 3138: fprintf (file, "\t.short %d\n", strlen (fname)); 3139: 3140: /* Function name. */ 3141: assemble_string (fname, strlen (fname)); 3142: 3143: /* Register for alloca automatic storage; this is always reg 31. 3144: Only emit this if the alloca bit was set above. */ 3145: if (frame_pointer_needed) 3146: fprintf (file, "\t.byte 31\n"); 3147: } 1.1.1.4 root 3148: #endif /* !USING_SVR4_H */ 3149: 3150: /* Reset varargs indicator */ 3151: rs6000_sysv_varargs_p = 0; 1.1 root 3152: } 3153: 3154: /* Output a TOC entry. We derive the entry name from what is 3155: being written. */ 3156: 3157: void 3158: output_toc (file, x, labelno) 3159: FILE *file; 3160: rtx x; 3161: int labelno; 3162: { 3163: char buf[256]; 3164: char *name = buf; 3165: rtx base = x; 3166: int offset = 0; 3167: 1.1.1.4 root 3168: if (TARGET_NO_TOC) 3169: abort (); 3170: 3171: /* if we're going to put a double constant in the TOC, make sure it's 3172: aligned properly when strict alignment is on. */ 3173: if (GET_CODE (x) == CONST_DOUBLE 3174: && STRICT_ALIGNMENT 3175: && GET_MODE (x) == DFmode 3176: && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { 3177: ASM_OUTPUT_ALIGN (file, 3); 3178: } 3179: 3180: 3181: #ifdef USING_SVR4_H 3182: if (TARGET_MINIMAL_TOC) 3183: { 3184: ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); 3185: fprintf (file, "%d = .-", labelno); 3186: ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC"); 3187: fprintf (file, "1\n"); 3188: } 3189: else 3190: #endif /* USING_SVR4_H */ 3191: ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); 1.1 root 3192: 1.1.1.2 root 3193: /* Handle FP constants specially. Note that if we have a minimal 3194: TOC, things we put here aren't actually in the TOC, so we can allow 3195: FP constants. */ 1.1 root 3196: if (GET_CODE (x) == CONST_DOUBLE 3197: && GET_MODE (x) == DFmode 1.1.1.2 root 3198: && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) 1.1 root 3199: { 1.1.1.4 root 3200: REAL_VALUE_TYPE r; 3201: long l[2]; 3202: 3203: REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3204: REAL_VALUE_TO_TARGET_DOUBLE (r, l); 1.1.1.2 root 3205: if (TARGET_MINIMAL_TOC) 1.1.1.4 root 3206: fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]); 1.1.1.2 root 3207: else 1.1.1.4 root 3208: fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n", 3209: l[0], l[1], l[0], l[1]); 1.1 root 3210: return; 3211: } 3212: else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode 1.1.1.2 root 3213: && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) 1.1 root 3214: { 3215: rtx val = operand_subword (x, 0, 0, SFmode); 3216: 3217: if (val == 0 || GET_CODE (val) != CONST_INT) 3218: abort (); 3219: 1.1.1.2 root 3220: if (TARGET_MINIMAL_TOC) 3221: fprintf (file, "\t.long %d\n", INTVAL (val)); 3222: else 3223: fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val)); 1.1 root 3224: return; 3225: } 3226: 3227: if (GET_CODE (x) == CONST) 3228: { 3229: base = XEXP (XEXP (x, 0), 0); 3230: offset = INTVAL (XEXP (XEXP (x, 0), 1)); 3231: } 3232: 3233: if (GET_CODE (base) == SYMBOL_REF) 3234: name = XSTR (base, 0); 3235: else if (GET_CODE (base) == LABEL_REF) 3236: ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); 3237: else if (GET_CODE (base) == CODE_LABEL) 3238: ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); 3239: else 3240: abort (); 3241: 1.1.1.2 root 3242: if (TARGET_MINIMAL_TOC) 3243: fprintf (file, "\t.long "); 3244: else 3245: { 3246: fprintf (file, "\t.tc "); 3247: RS6000_OUTPUT_BASENAME (file, name); 1.1 root 3248: 1.1.1.2 root 3249: if (offset < 0) 3250: fprintf (file, ".N%d", - offset); 3251: else if (offset) 3252: fprintf (file, ".P%d", offset); 1.1 root 3253: 1.1.1.2 root 3254: fprintf (file, "[TC],"); 3255: } 1.1 root 3256: output_addr_const (file, x); 3257: fprintf (file, "\n"); 3258: } 3259: 3260: /* Output an assembler pseudo-op to write an ASCII string of N characters 3261: starting at P to FILE. 3262: 3263: On the RS/6000, we have to do this using the .byte operation and 3264: write out special characters outside the quoted string. 3265: Also, the assembler is broken; very long strings are truncated, 3266: so we must artificially break them up early. */ 3267: 3268: void 3269: output_ascii (file, p, n) 3270: FILE *file; 3271: char *p; 3272: int n; 3273: { 3274: char c; 3275: int i, count_string; 3276: char *for_string = "\t.byte \""; 3277: char *for_decimal = "\t.byte "; 3278: char *to_close = NULL; 3279: 3280: count_string = 0; 3281: for (i = 0; i < n; i++) 3282: { 3283: c = *p++; 3284: if (c >= ' ' && c < 0177) 3285: { 3286: if (for_string) 3287: fputs (for_string, file); 3288: putc (c, file); 3289: 3290: /* Write two quotes to get one. */ 3291: if (c == '"') 3292: { 3293: putc (c, file); 3294: ++count_string; 3295: } 3296: 3297: for_string = NULL; 3298: for_decimal = "\"\n\t.byte "; 3299: to_close = "\"\n"; 3300: ++count_string; 3301: 3302: if (count_string >= 512) 3303: { 3304: fputs (to_close, file); 3305: 3306: for_string = "\t.byte \""; 3307: for_decimal = "\t.byte "; 3308: to_close = NULL; 3309: count_string = 0; 3310: } 3311: } 3312: else 3313: { 3314: if (for_decimal) 3315: fputs (for_decimal, file); 3316: fprintf (file, "%d", c); 3317: 3318: for_string = "\n\t.byte \""; 3319: for_decimal = ", "; 3320: to_close = "\n"; 3321: count_string = 0; 3322: } 3323: } 3324: 3325: /* Now close the string if we have written one. Then end the line. */ 3326: if (to_close) 3327: fprintf (file, to_close); 3328: } 3329: 3330: /* Generate a unique section name for FILENAME for a section type 3331: represented by SECTION_DESC. Output goes into BUF. 3332: 3333: SECTION_DESC can be any string, as long as it is different for each 3334: possible section type. 3335: 3336: We name the section in the same manner as xlc. The name begins with an 3337: underscore followed by the filename (after stripping any leading directory 3338: names) with the last period replaced by the string SECTION_DESC. If 3339: FILENAME does not contain a period, SECTION_DESC is appended to the end of 3340: the name. */ 3341: 3342: void 3343: rs6000_gen_section_name (buf, filename, section_desc) 3344: char **buf; 3345: char *filename; 3346: char *section_desc; 3347: { 3348: char *q, *after_last_slash, *last_period; 3349: char *p; 3350: int len; 3351: 3352: after_last_slash = filename; 3353: for (q = filename; *q; q++) 3354: { 3355: if (*q == '/') 3356: after_last_slash = q + 1; 3357: else if (*q == '.') 3358: last_period = q; 3359: } 3360: 3361: len = strlen (after_last_slash) + strlen (section_desc) + 2; 3362: *buf = (char *) permalloc (len); 3363: 3364: p = *buf; 3365: *p++ = '_'; 3366: 3367: for (q = after_last_slash; *q; q++) 3368: { 3369: if (q == last_period) 3370: { 3371: strcpy (p, section_desc); 3372: p += strlen (section_desc); 3373: } 3374: 3375: else if (isalnum (*q)) 3376: *p++ = *q; 3377: } 3378: 3379: if (last_period == 0) 3380: strcpy (p, section_desc); 3381: else 3382: *p = '\0'; 3383: } 3384: 3385: /* Write function profiler code. */ 3386: 3387: void 3388: output_function_profiler (file, labelno) 3389: FILE *file; 3390: int labelno; 3391: { 1.1.1.4 root 3392: #ifdef USING_SVR4_H 3393: abort (); 3394: #else 1.1 root 3395: /* The last used parameter register. */ 3396: int last_parm_reg; 3397: int i, j; 1.1.1.3 root 3398: char buf[100]; 1.1 root 3399: 3400: /* Set up a TOC entry for the profiler label. */ 3401: toc_section (); 1.1.1.3 root 3402: ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); 3403: ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 1.1.1.2 root 3404: if (TARGET_MINIMAL_TOC) 1.1.1.3 root 3405: { 3406: fprintf (file, "\t.long "); 3407: assemble_name (file, buf); 3408: fprintf (file, "\n"); 3409: } 1.1.1.2 root 3410: else 1.1.1.3 root 3411: { 3412: fprintf (file, "\t.tc\t"); 3413: assemble_name (file, buf); 3414: fprintf (file, "[TC],"); 3415: assemble_name (file, buf); 3416: fprintf (file, "\n"); 3417: } 1.1 root 3418: text_section (); 3419: 3420: /* Figure out last used parameter register. The proper thing to do is 3421: to walk incoming args of the function. A function might have live 3422: parameter registers even if it has no incoming args. */ 3423: 3424: for (last_parm_reg = 10; 3425: last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; 3426: last_parm_reg--) 3427: ; 3428: 3429: /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since 3430: it might be set up as the frame pointer. */ 3431: 3432: for (i = 3, j = 30; i <= last_parm_reg; i++, j--) 3433: fprintf (file, "\tai %d,%d,0\n", j, i); 3434: 3435: /* Load location address into r3, and call mcount. */ 3436: 1.1.1.3 root 3437: ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); 3438: fprintf (file, "\tl 3,"); 3439: assemble_name (file, buf); 3440: fprintf (file, "(2)\n\tbl .mcount\n"); 1.1 root 3441: 3442: /* Restore parameter registers. */ 3443: 3444: for (i = 3, j = 30; i <= last_parm_reg; i++, j--) 3445: fprintf (file, "\tai %d,%d,0\n", i, j); 1.1.1.4 root 3446: #endif 1.1 root 3447: } 1.1.1.3 root 3448: 3449: /* Adjust the cost of a scheduling dependency. Return the new cost of 3450: a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 3451: 3452: int 3453: rs6000_adjust_cost (insn, link, dep_insn, cost) 3454: rtx insn; 3455: rtx link; 3456: rtx dep_insn; 3457: int cost; 3458: { 3459: if (! recog_memoized (insn)) 3460: return 0; 3461: 3462: if (REG_NOTE_KIND (link) != 0) 3463: return 0; 3464: 3465: if (REG_NOTE_KIND (link) == 0) 3466: { 3467: /* Data dependency; DEP_INSN writes a register that INSN reads some 3468: cycles later. */ 3469: 3470: /* Tell the first scheduling pass about the latency between a mtctr 3471: and bctr (and mtlr and br/blr). The first scheduling pass will not 3472: know about this latency since the mtctr instruction, which has the 3473: latency associated to it, will be generated by reload. */ 3474: if (get_attr_type (insn) == TYPE_JMPREG) 3475: return TARGET_POWER ? 5 : 4; 3476: 3477: /* Fall out to return default cost. */ 3478: } 3479: 3480: return cost; 3481: }
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