--- gcc/config/rs6000/rs6000.md	2018/04/24 18:16:38	1.1.1.2
+++ gcc/config/rs6000/rs6000.md	2018/04/24 18:22:51	1.1.1.3
@@ -1,6 +1,6 @@
-;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
-;;   Copyright (C) 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
-;;   Contributed by Richard Kenner (kenner@nyu.edu)
+;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
+;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
+;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 ;; This file is part of GNU CC.
 
@@ -22,7 +22,7 @@
 
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations.
-(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtlr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt"
+(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
   (const_string "integer"))
 
 ;; Length (in bytes).
@@ -45,6 +45,8 @@
 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
 ;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
 
+; Load/Store Unit -- POWER/2 and pure PowerPC only
+; (POWER and 601 use Integer Unit)
 (define_function_unit "lsu" 1 0
   (and (eq_attr "type" "load")
        (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
@@ -65,26 +67,74 @@
        (eq_attr "cpu" "rios1,ppc601"))
   3 0)
 
+; Integer Unit (RIOS1, PPC601, PPC603)
+; Trivial operations take one cycle which need not be listed here.
 (define_function_unit "iu" 1 0
   (and (eq_attr "type" "imul")
        (eq_attr "cpu" "rios1"))
-  3 0)
+  3 3)
 
 (define_function_unit "iu" 1 0
   (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
-  5 0)
+       (eq_attr "cpu" "ppc601,ppc603"))
+  5 5)
 
 (define_function_unit "iu" 1 0
   (and (eq_attr "type" "idiv")
        (eq_attr "cpu" "rios1"))
-  19 0)
+  19 19)
 
 (define_function_unit "iu" 1 0
   (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
-  36 0)
+       (eq_attr "cpu" "ppc601"))
+  36 36)
+
+(define_function_unit "iu" 1 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "ppc603"))
+  37 36)
+
+; RIOS2 has two integer units: a primary one which can perform all
+; operations and a secondary one which is fed in lock step with the first
+; and can perform "simple" integer operations.
+(define_function_unit "iu2" 2 0
+  (and (eq_attr "type" "integer")
+       (eq_attr "cpu" "rios2"))
+  1 0
+  [(eq_attr "type" "imul,idiv")])
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "imul")
+       (eq_attr "cpu" "rios2"))
+  2 2
+  [(eq_attr "type" "integer")])
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "rios2"))
+  13 13
+  [(eq_attr "type" "integer")])
+
+; PPC604 has three integer units: one primary and two secondary.
+(define_function_unit "iu3" 3 0
+  (and (eq_attr "type" "integer")
+       (eq_attr "cpu" "ppc604,ppc620"))
+  1 0
+  [(eq_attr "type" "imul,idiv")])
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "imul")
+       (eq_attr "cpu" "ppc604,ppc620"))
+  4 2
+  [(eq_attr "type" "integer")])
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "ppc604,ppc620"))
+  20 19
+  [(eq_attr "type" "integer")])
 
+; Branch Processing Unit
 (define_function_unit "bpu" 1 0
   (eq_attr "type" "compare")
   4 0)
@@ -104,83 +154,82 @@
   4 0)
 
 (define_function_unit "bpu" 1 0
-  (and (eq_attr "type" "mtlr")
+  (and (eq_attr "type" "mtjmpr")
        (eq_attr "cpu" "rios1,rios2"))
   5 0)
 
 (define_function_unit "bpu" 1 0
-  (and (eq_attr "type" "mtlr")
+  (and (eq_attr "type" "mtjmpr")
        (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
   4 0)
 
+; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604).
 (define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fp")
+  (and (eq_attr "type" "fp,dmul")
        (eq_attr "cpu" "rios1"))
   2 0)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
+       (eq_attr "cpu" "ppc601"))
   4 0)
 
 (define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "fp")
+       (eq_attr "cpu" "ppc603,ppc604,ppc620"))
+  3 0)
+
+(define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "rios1"))
-  2 0)
+       (eq_attr "cpu" "ppc601"))
+  5 5)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
-  5 0)
+       (eq_attr "cpu" "ppc603"))
+  4 2)
 
 (define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "sdiv")
+  (and (eq_attr "type" "dmul")
+       (eq_attr "cpu" "ppc604,ppc620"))
+  3 0)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "sdiv,ddiv")
        (eq_attr "cpu" "rios1"))
-  19 0)
+  19 19)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
-  17 0)
+       (eq_attr "cpu" "ppc601"))
+  17 17)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "sdiv")
+       (eq_attr "cpu" "ppc603,ppc604,ppc620"))
+  18 18)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "rios1"))
-  19 0)
+       (eq_attr "cpu" "ppc601,ppc604,ppc620"))
+  31 31)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
-  31 0)
+       (eq_attr "cpu" "ppc603"))
+  33 33)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "ppc603,ppc604,ppc620"))
-  31 0)
+       (eq_attr "cpu" "ppc620"))
+  31 31)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "ppc603,ppc604,ppc620"))
-  31 0)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "rios2"))
-  1 0
-  [(eq_attr "type" "imul,idiv")])
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "rios2"))
-  2 0
-  [(eq_attr "type" "integer")])
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "rios2"))
-  13 0
-  [(eq_attr "type" "integer")])
+       (eq_attr "cpu" "ppc620"))
+  31 31)
 
+; RIOS2 has two symmetric FPUs.
 (define_function_unit "fpu2" 2 0
   (and (eq_attr "type" "fp")
        (eq_attr "cpu" "rios2"))
@@ -192,28 +241,213 @@
   2 0)
 
 (define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "rios2"))
-  17 0)
-
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "rios2"))
-  17 0)
-
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "ssqrt")
+  (and (eq_attr "type" "sdiv,ddiv")
        (eq_attr "cpu" "rios2"))
-  26 0)
+  17 17)
 
 (define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "dsqrt")
+  (and (eq_attr "type" "ssqrt,dsqrt")
        (eq_attr "cpu" "rios2"))
-  26 0)
+  26 26)
 
 ;; Start with fixed-point load and store insns.  Here we put only the more
 ;; complex forms.  Basic data transfer is done later.
 
+(define_expand "zero_extendqidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
+  "TARGET_POWERPC64"
+  "@
+   lbz%U1%X1 %0,%1
+   rldicl %0,%1,0,56"
+  [(set_attr "type" "load,*")])
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "rldicl. %2,%1,0,56"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(zero_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "rldicl. %0,%1,0,56"
+  [(set_attr "type" "compare")])
+
+(define_insn "extendqidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "extsb %0,%1")
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "extsb. %2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "extsb. %0,%1"
+  [(set_attr "type" "compare")])
+
+(define_expand "zero_extendhidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
+  "TARGET_POWERPC64"
+  "@
+   lhz%U1%X1 %0,%1
+   rldicl %0,%1,0,48"
+  [(set_attr "type" "load,*")])
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "rldicl. %2,%1,0,48"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(zero_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "rldicl. %0,%1,0,48"
+  [(set_attr "type" "compare")])
+
+(define_expand "extendhidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
+  "TARGET_POWERPC64"
+  "@
+   lha%U1%X1 %0,%1
+   extsh %0,%1"
+  [(set_attr "type" "load,*")])
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "extsh. %2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "extsh. %0,%1"
+  [(set_attr "type" "compare")])
+
+(define_expand "zero_extendsidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
+  "TARGET_POWERPC64"
+  "@
+   lwz%U1%X1 %0,%1
+   rldicl %0,%1,0,32"
+  [(set_attr "type" "load,*")])
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "rldicl. %2,%1,0,32"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(zero_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "rldicl. %0,%1,0,32"
+  [(set_attr "type" "compare")])
+
+(define_expand "extendsidi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
+  "TARGET_POWERPC64"
+  "@
+   lwa%U1%X1 %0,%1
+   extsw %0,%1"
+  [(set_attr "type" "load,*")])
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 2 "=r"))]
+  "TARGET_POWERPC64"
+  "extsw. %2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))]
+  "TARGET_POWERPC64"
+  "extsw. %0,%1"
+  [(set_attr "type" "compare")])
+
 (define_expand "zero_extendqisi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
@@ -248,6 +482,72 @@
   "{andil.|andi.} %0,%1,0xff"
   [(set_attr "type" "compare")])
 
+(define_expand "extendqisi2"
+  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
+   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
+  ""
+  "
+{
+  if (TARGET_POWERPC)
+    emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
+  else if (TARGET_POWER)
+    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
+  else
+    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
+  DONE;
+}")
+
+(define_insn "extendqisi2_ppc"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC"
+  "extsb %0,%1")
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:SI 2 "=r"))]
+  "TARGET_POWERPC"
+  "extsb. %2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extend:SI (match_dup 1)))]
+  "TARGET_POWERPC"
+  "extsb. %0,%1"
+  [(set_attr "type" "compare")])
+
+(define_expand "extendqisi2_power"
+  [(parallel [(set (match_dup 2)
+		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+			      (const_int 24)))
+	      (clobber (scratch:SI))])
+   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (ashiftrt:SI (match_dup 2)
+				(const_int 24)))
+	      (clobber (scratch:SI))])]
+  "TARGET_POWER"
+  "
+{ operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "extendqisi2_no_power"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+		   (const_int 24)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "
+{ operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
 (define_expand "zero_extendqihi2"
   [(set (match_operand:HI 0 "gpc_reg_operand" "")
 	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
@@ -263,6 +563,93 @@
    {rlinm|rlwinm} %0,%1,0,0xff"
   [(set_attr "type" "load,*")])
 
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:HI 2 "=r"))]
+  ""
+  "{andil.|andi.} %2,%1,0xff"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(zero_extend:HI (match_dup 1)))]
+  ""
+  "{andil.|andi.} %0,%1,0xff"
+  [(set_attr "type" "compare")])
+
+(define_expand "extendqihi2"
+  [(use (match_operand:HI 0 "gpc_reg_operand" ""))
+   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
+  ""
+  "
+{
+  if (TARGET_POWERPC)
+    emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
+  else if (TARGET_POWER)
+    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
+  else
+    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
+  DONE;
+}")
+
+(define_insn "extendqihi2_ppc"
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC"
+  "extsb %0,%1")
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:HI 2 "=r"))]
+  "TARGET_POWERPC"
+  "extsb. %2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(sign_extend:HI (match_dup 1)))]
+  "TARGET_POWERPC"
+  "extsb. %0,%1"
+  [(set_attr "type" "compare")])
+
+(define_expand "extendqihi2_power"
+  [(parallel [(set (match_dup 2)
+		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+			      (const_int 24)))
+	      (clobber (scratch:SI))])
+   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
+		   (ashiftrt:SI (match_dup 2)
+				(const_int 24)))
+	      (clobber (scratch:SI))])]
+  "TARGET_POWER"
+  "
+{ operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "extendqihi2_no_power"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+		   (const_int 24)))
+   (set (match_operand:HI 0 "gpc_reg_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "
+{ operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
 (define_expand "zero_extendhisi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
@@ -332,34 +719,43 @@
   [(set_attr "type" "compare")])
 
 ;; Fixed-point arithmetic insns.
+
+;; Discourage ai/addic because of carry but provide it in an alternative
+;; allowing register zero as source.
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
-		 (match_operand:SI 2 "add_operand" "rI,J")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
+	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
+		 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
   ""
   "@
-   {a%I2|add%I2c} %0,%1,%2
+   {cax|add} %0,%1,%2
+   {cal %0,%2(%1)|addi %0,%1,%2}
+   {ai|addic} %0,%1,%2
    {cau|addis} %0,%1,%u2")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
+	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+			     (match_operand:SI 2 "reg_or_short_operand" "r,I"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r"))]
+   (clobber (match_scratch:SI 3 "=r,r"))]
   ""
-  "{a%I2.|add%I2c.} %3,%1,%2"
+  "@
+   {cax.|add.} %3,%1,%2
+   {ai.|addic.} %3,%1,%2"
   [(set_attr "type" "compare")])
    
 (define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
+	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+			     (match_operand:SI 2 "reg_or_short_operand" "r,I"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
-  "{a%I2.|add%I2c.} %0,%1,%2"
+  "@
+   {cax.|add.} %0,%1,%2
+   {ai.|addic.} %0,%1,%2"
   [(set_attr "type" "compare")])
    
 ;; Split an add that we can't do in one insn into two insns, each of which
@@ -385,22 +781,10 @@
   operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
 }")
 
-(define_expand "one_cmplsi2"
+(define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "{sfi|subfic} %0,%1,-1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "! TARGET_POWER"
   "nor %0,%1,%1")
 
 (define_insn ""
@@ -413,7 +797,7 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=-x")
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
 	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -426,30 +810,60 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
 		  (match_operand:SI 2 "gpc_reg_operand" "r")))]
-  ""
+  "! TARGET_POWERPC"
   "{sf%I1|subf%I1c} %0,%2,%1")
 
 (define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
+		  (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
+  "TARGET_POWERPC"
+  "@
+   subf %0,%2,%1
+   subfic %0,%2,%1")
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
-  ""
+  "! TARGET_POWERPC"
   "{sf.|subfc.} %3,%2,%1"
   [(set_attr "type" "compare")])
 
 (define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			      (match_operand:SI 2 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (clobber (match_scratch:SI 3 "=r"))]
+  "TARGET_POWERPC"
+  "subf. %3,%2,%1"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(minus:SI (match_dup 1) (match_dup 2)))]
-  ""
+  "! TARGET_POWERPC"
   "{sf.|subfc.} %0,%2,%1"
   [(set_attr "type" "compare")])
 
+(define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			      (match_operand:SI 2 "gpc_reg_operand" "r"))
+		    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(minus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC"
+  "subf. %0,%2,%1"
+  [(set_attr "type" "compare")])
+
 (define_expand "subsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
@@ -669,7 +1083,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))
@@ -680,7 +1094,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -690,7 +1104,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -702,7 +1116,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -715,7 +1129,27 @@
 ;; 0 and remainder to operand 3.
 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
 
-(define_insn "divmodsi4"
+(define_expand "divmodsi4"
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
+			   (match_operand:SI 2 "gpc_reg_operand" "")))
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
+		   (mod:SI (match_dup 1) (match_dup 2)))])]
+  "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
+  "
+{
+  if (! TARGET_POWER && ! TARGET_POWERPC)
+    {
+      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+      emit_insn (gen_divss_call ());
+      emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
+      emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
+      DONE;
+    }
+}")
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "gpc_reg_operand" "r")))
@@ -730,20 +1164,38 @@
         (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC"
-  "divw %0, %1, %2"
+  "divw %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_insn "udivsi3"
+(define_expand "udivsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                 (match_operand:SI 2 "gpc_reg_operand" "")))]
+  "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
+  "
+{
+  if (! TARGET_POWER && ! TARGET_POWERPC)
+    {
+      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+      emit_insn (gen_quous_call ());
+      emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
+      DONE;
+    }
+}")
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC"
-  "divwu %0, %1, %2"
+  "divwu %0,%1,%2"
   [(set_attr "type" "idiv")])
 
 ;; For powers of two we can do srai/aze for divide and then adjust for
 ;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
-;; used; for PowerPC, force operands into register and do a normal divide.
+;; used; for PowerPC, force operands into register and do a normal divide;
+;; for AIX common-mode, use quoss call on register operands.
 (define_expand "divsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(div:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -754,10 +1206,19 @@
   if (GET_CODE (operands[2]) == CONST_INT
       && exact_log2 (INTVAL (operands[2])) >= 0)
     ;
-  else if (! TARGET_POWERPC)
+  else if (TARGET_POWER && ! TARGET_POWERPC)
     FAIL;
   else
     operands[2] = force_reg (SImode, operands[2]);
+
+  if (! TARGET_POWER && ! TARGET_POWERPC)
+    {
+      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+      emit_insn (gen_quoss_call ());
+      emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
+      DONE;
+    }
 }")
 
 (define_expand "modsi3"
@@ -781,7 +1242,6 @@
   emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
   emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
   DONE;
-
 }")
 
 (define_insn ""
@@ -794,8 +1254,9 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "const_int_operand" "N")))
+	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "const_int_operand" "N"))
+		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
   "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
@@ -804,8 +1265,9 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "const_int_operand" "N")))
+	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "const_int_operand" "N"))
+		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(div:SI (match_dup 1) (match_dup 2)))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
@@ -816,18 +1278,17 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(udiv:SI
-	 (plus:DI (lshift:DI
+	 (plus:DI (ashift:DI
 		   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		   (const_int 32))
 		  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
 	 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (set (match_operand:SI 2 "register_operand" "=*q")
 	(umod:SI
-	 (plus:DI (lshift:DI
+	 (plus:DI (ashift:DI
 		   (zero_extend:DI (match_dup 1)) (const_int 32))
 		  (zero_extend:DI (match_dup 4)))
 	 (match_dup 3)))]
-  
   "TARGET_POWER"
   "div %0,%1,%3"
   [(set_attr "type" "idiv")])
@@ -840,12 +1301,12 @@
 (define_expand "udivmodsi4_normal"
   [(set (match_dup 4) (const_int 0))
    (parallel [(set (match_operand:SI 0 "" "")
-		   (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
+		   (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
 						(const_int 32))
 				     (zero_extend:DI (match_operand:SI 1 "" "")))
 			    (match_operand:SI 2 "" "")))
 	      (set (match_operand:SI 3 "" "")
-		   (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
+		   (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
 						(const_int 32))
 				     (zero_extend:DI (match_dup 1)))
 			    (match_dup 2)))])]
@@ -877,11 +1338,24 @@
 			    (match_operand:SI 2 "reg_or_cint_operand" "")))
 	      (set (match_operand:SI 3 "gpc_reg_operand" "")
 		   (umod:SI (match_dup 1) (match_dup 2)))])]
-  "TARGET_POWER"
+  ""
   "
 {
   rtx label = 0;
 
+  if (! TARGET_POWER)
+    if (! TARGET_POWERPC)
+      {
+	emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+	emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+	emit_insn (gen_divus_call ());
+	emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
+	emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
+	DONE;
+      }
+    else
+      FAIL;
+
   if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
     {
       operands[2] = force_reg (SImode, operands[2]);
@@ -899,7 +1373,66 @@
 
   DONE;
 }")
-    
+
+;; AIX architecture-independent common-mode multiply (DImode),
+;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
+;; R4; results in R3 and somtimes R4; link register always clobbered by bla
+;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
+;; assumed unused if generating common-mode, so ignore.
+(define_insn "mulh_call"
+  [(set (reg:SI 3)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
+			       (sign_extend:DI (reg:SI 4)))
+		      (const_int 32))))
+   (clobber (match_scratch:SI 0 "=l"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mulh")
+
+(define_insn "mull_call"
+  [(set (reg:DI 3)
+	(mult:DI (sign_extend:DI (reg:SI 3))
+		 (sign_extend:DI (reg:SI 4))))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mull")
+
+(define_insn "divss_call"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (set (reg:SI 4)
+	(mod:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __divss")
+
+(define_insn "divus_call"
+  [(set (reg:SI 3)
+	(udiv:SI (reg:SI 3) (reg:SI 4)))
+   (set (reg:SI 4)
+	(umod:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __divus")
+
+(define_insn "quoss_call"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quoss")
+
+(define_insn "quous_call"
+  [(set (reg:SI 3)
+	(udiv:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quous")
+
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
@@ -993,7 +1526,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1003,7 +1536,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1041,7 +1574,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1051,7 +1584,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1163,14 +1696,14 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nand %0,%1,%2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1180,7 +1713,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1191,14 +1724,14 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nor %0,%1,%2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1208,7 +1741,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1581,7 +2114,7 @@
 	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "slw%I2 %0,%1,%2"
+  "slw%I2 %0,%1,%h2"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -1603,8 +2136,8 @@
 			       (match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWERPC"
-  "slw%I2. %3,%1,%2"
+  "! TARGET_POWER"
+  "slw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -1628,8 +2161,8 @@
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC"
-  "slw%I2. %0,%1,%2"
+  "! TARGET_POWER"
+  "slw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -1696,7 +2229,7 @@
 	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "srw%I2 %0,%1,%2")
+  "srw%I2 %0,%1,%h2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -1718,7 +2251,7 @@
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "! TARGET_POWER"
-  "srw%I2. %3,%1,%2"
+  "srw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -1743,7 +2276,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
   "! TARGET_POWER"
-  "srw%I2. %0,%1,%2"
+  "srw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -1908,7 +2441,7 @@
 	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "sraw%I2 %0,%1,%2")
+  "sraw%I2 %0,%1,%h2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -1930,7 +2463,7 @@
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "! TARGET_POWER"
-  "sraw%I2. %3,%1,%2"
+  "sraw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -1955,88 +2488,8 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
   "! TARGET_POWER"
-  "sraw%I2. %0,%1,%2"
+  "sraw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
-
-(define_expand "extendqisi2"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
-  else
-    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "extendqisi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqisi2_no_power"
-  [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))]
-  "! TARGET_POWER"
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqihi2"
-  [(use (match_operand:HI 0 "gpc_reg_operand" ""))
-   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
-  else
-    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "extendqihi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqihi2_no_power"
-  [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))]
-  "! TARGET_POWER"
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
 
 ;; Floating-point insns, excluding normal data motion.
 ;;
@@ -2114,7 +2567,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fa|fadd} %0,%1,%2"
   [(set_attr "type" "fp")])
 
@@ -2137,7 +2590,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
 		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fs|fsub} %0,%1,%2"
   [(set_attr "type" "fp")])
 
@@ -2160,7 +2613,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fm|fmul} %0,%1,%2"
   [(set_attr "type" "fp")])
 
@@ -2183,7 +2636,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
 		(match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fd|fdiv} %0,%1,%2"
   [(set_attr "type" "sdiv")])
 
@@ -2201,7 +2654,7 @@
 	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 			  (match_operand:SF 2 "gpc_reg_operand" "f"))
 		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fma|fmadd} %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
@@ -2219,7 +2672,7 @@
 	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 			   (match_operand:SF 2 "gpc_reg_operand" "f"))
 		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fms|fmsub} %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
@@ -2237,7 +2690,7 @@
 	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 				  (match_operand:SF 2 "gpc_reg_operand" "f"))
 			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fnma|fnmadd} %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
@@ -2255,20 +2708,20 @@
 	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
 				   (match_operand:SF 2 "gpc_reg_operand" "f"))
 			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_POWER"
+  "! TARGET_POWERPC"
   "{fnms|fnmsub} %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPCSQR || TARGET_POWER2"
+  "TARGET_PPC_GPOPT || TARGET_POWER2"
   "")
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPCSQR"
+  "TARGET_PPC_GPOPT"
   "fsqrts %0,%1"
   [(set_attr "type" "ssqrt")])
 
@@ -2279,6 +2732,76 @@
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
 
+;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
+;; instruction and some auxiliary computations.  Then we just have a single
+;; DEFINE_INSN for fsel and the define_splits to make them if made by
+;; combine.
+(define_expand "maxsf3"
+  [(set (match_dup 3)
+	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
+		  (match_operand:SF 2 "gpc_reg_operand" "")))
+   (set (match_operand:SF 0 "gpc_reg_operand" "")
+	(if_then_else:SF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "TARGET_PPC_GFXOPT"
+  "
+{ operands[3] = gen_reg_rtx (SFmode); }")
+
+(define_split
+  [(set (match_operand:SF 0 "gpc_reg_operand" "")
+	(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
+		 (match_operand:SF 2 "gpc_reg_operand" "")))
+   (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
+  "TARGET_PPC_GFXOPT"
+  [(set (match_dup 3)
+	(minus:SF (match_dup 1) (match_dup 2)))
+   (set (match_operand:SF 0 "gpc_reg_operand" "")
+	(if_then_else:SF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "")
+
+(define_expand "minsf3"
+  [(set (match_dup 3)
+	(minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
+		  (match_operand:SF 1 "gpc_reg_operand" "")))
+   (set (match_operand:SF 0 "gpc_reg_operand" "")
+	(if_then_else:SF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "TARGET_PPC_GFXOPT"
+  "
+{ operands[3] = gen_reg_rtx (SFmode); }")
+
+(define_split
+  [(set (match_operand:SF 0 "gpc_reg_operand" "")
+	(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
+		 (match_operand:SF 2 "gpc_reg_operand" "")))
+   (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
+  "TARGET_PPC_GFXOPT"
+  [(set (match_dup 3)
+	(minus:SF (match_dup 2) (match_dup 1)))
+   (set (match_operand:SF 0 "gpc_reg_operand" "")
+	(if_then_else:SF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
+			     (const_int 0))
+			 (match_operand:SF 2 "gpc_reg_operand" "f")
+			 (match_operand:SF 3 "gpc_reg_operand" "f")))]
+  "TARGET_PPC_GFXOPT"
+  "fsel %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
@@ -2371,9 +2894,80 @@
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPCSQR || TARGET_POWER2"
+  "TARGET_PPC_GPOPT || TARGET_POWER2"
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
+
+;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
+;; instruction and some auxiliary computations.  Then we just have a single
+;; DEFINE_INSN for fsel and the define_splits to make them if made by
+;; combine.
+
+(define_expand "maxdf3"
+  [(set (match_dup 3)
+	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
+		  (match_operand:DF 2 "gpc_reg_operand" "")))
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
+	(if_then_else:DF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "TARGET_PPC_GFXOPT"
+  "
+{ operands[3] = gen_reg_rtx (DFmode); }")
+
+(define_split
+  [(set (match_operand:DF 0 "gpc_reg_operand" "")
+	(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
+		 (match_operand:DF 2 "gpc_reg_operand" "")))
+   (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
+  "TARGET_PPC_GFXOPT"
+  [(set (match_dup 3)
+	(minus:DF (match_dup 1) (match_dup 2)))
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
+	(if_then_else:DF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "")
+
+(define_expand "mindf3"
+  [(set (match_dup 3)
+	(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
+		  (match_operand:DF 1 "gpc_reg_operand" "")))
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
+	(if_then_else:DF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "TARGET_PPC_GFXOPT"
+  "
+{ operands[3] = gen_reg_rtx (DFmode); }")
+
+(define_split
+  [(set (match_operand:DF 0 "gpc_reg_operand" "")
+	(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
+		 (match_operand:DF 2 "gpc_reg_operand" "")))
+   (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
+  "TARGET_PPC_GFXOPT"
+  [(set (match_dup 3)
+	(minus:DF (match_dup 2) (match_dup 1)))
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
+	(if_then_else:DF (ge (match_dup 3)
+			     (const_int 0))
+			 (match_dup 1)
+			 (match_dup 2)))]
+  "")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
+			     (const_int 0))
+			 (match_operand:DF 2 "gpc_reg_operand" "f")
+			 (match_operand:DF 3 "gpc_reg_operand" "f")))]
+  "TARGET_PPC_GFXOPT"
+  "fsel %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
 
 ;; Conversions to and from floating-point.
 (define_expand "floatsidf2"
@@ -2497,23 +3091,44 @@
   ""
   "
 {
-  emit_insn (gen_trunc_call (operands[0], operands[1],
-			     gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
-  DONE;
+  if (TARGET_POWER2 || TARGET_POWERPC)
+    {
+      rtx stack_slot = assign_stack_temp (DImode, 8, 0),
+	temp = gen_reg_rtx (DImode);
+
+      emit_insn (gen_fpcvtsi (temp, operands[1]));
+      emit_move_insn (stack_slot, temp);
+      emit_move_insn (operands[0],
+		      operand_subword (stack_slot, 1, 0, DImode));
+      DONE;
+    }
+  else
+    {
+      emit_insn (gen_trunc_call (operands[0], operands[1],
+				 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
+      DONE;
+    }
 }")
 
+(define_insn "fpcvtsi"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+	(sign_extend:DI
+	 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
+  "TARGET_POWER2 || TARGET_POWERPC"
+  "{fcirz|fctiwz} %0,%1"
+  [(set_attr "type" "fp")])
+
 (define_expand "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
-  ""
+  "! TARGET_POWER2 && ! TARGET_POWERPC"
   "
 {
   emit_insn (gen_trunc_call (operands[0], operands[1],
-			     gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
+			     gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
   DONE;
 }")
 
-
 (define_expand "trunc_call"
   [(parallel [(set (match_operand:SI 0 "" "")
 		   (fix:SI (match_operand:DF 1 "" "")))
@@ -2546,6 +3161,20 @@
 { 
   rs6000_trunc_used = 1;
 }")
+
+(define_insn "floatdidf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC64"
+  "fcfid %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "fix_truncdfdi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC64"
+  "fctidz %0,%1"
+  [(set_attr "type" "fp")])
 
 ;; Define the DImode operations that can be done in a small number
 ;; of instructions.
@@ -2556,7 +3185,7 @@
   ""
   "
 {
-  if (! TARGET_POWER
+  if (! TARGET_POWER && ! TARGET_POWERPC64
       && short_cint_operand (operands[2], DImode))
     FAIL;
 }")
@@ -2565,7 +3194,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
 		 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
-  "TARGET_POWER"
+  "TARGET_POWER && ! TARGET_POWERPC64"
   "@
    {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
    {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
@@ -2575,7 +3204,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
 		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "! TARGET_POWER"
+  "! TARGET_POWER && ! TARGET_POWERPC64"
   "addc %L0,%L1,%L2\;adde %0,%1,%2"
   [(set_attr "length" "8")])
 
@@ -2586,7 +3215,7 @@
   ""
   "
 {
-  if (! TARGET_POWER
+  if (! TARGET_POWER && ! TARGET_POWERPC64
       && short_cint_operand (operands[1], DImode))
     FAIL;
 }")
@@ -2595,7 +3224,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
 		  (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
-  "TARGET_POWER"
+  "TARGET_POWER && ! TARGET_POWERPC64"
   "@
    {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
    {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
@@ -2605,7 +3234,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "! TARGET_POWER"
+  "! TARGET_POWER && ! TARGET_POWERPC64"
   "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
   [(set_attr "length" "8")])
 
@@ -2618,18 +3247,116 @@
 (define_insn ""
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  ""
+  "! TARGET_POWERPC64"
   "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
   [(set_attr "length" "8")])
 
-(define_insn "mulsidi3"
+(define_expand "mulsidi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+  ""
+  "
+{
+  if (! TARGET_POWER && ! TARGET_POWERPC)
+    {
+      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+      emit_insn (gen_mull_call ());
+      emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
+		      gen_rtx (REG, SImode, 3));
+      emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
+		      gen_rtx (REG, SImode, 4));
+      DONE;
+    }
+  else if (TARGET_POWER)
+    {
+      emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn "mulsidi3_mq"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
    (clobber (match_scratch:SI 3 "=q"))]
   "TARGET_POWER"
   "mul %0,%1,%2\;mfmq %L0"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "imul")
+   (set_attr "length" "8")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  "TARGET_POWERPC && ! TARGET_POWERPC64"
+  "mulhw %0,%1,%2\;mullw %L0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "length" "8")])
+
+(define_expand "smulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))]
+  ""
+  "
+{
+  if (! TARGET_POWER && ! TARGET_POWERPC)
+    {
+      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+      emit_insn (gen_mulh_call ());
+      emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
+      DONE;
+    }
+  else if (TARGET_POWER)
+    {
+      emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn "smulsi3_highpart_mq"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))
+   (clobber (match_scratch:SI 3 "=q"))]
+  "TARGET_POWER"
+  "mul %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))]
+  "TARGET_POWERPC"
+  "mulhw %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "umulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (zero_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (zero_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
+		      (const_int 32))))]
+  "TARGET_POWERPC"
+  "mulhwu %0,%1,%2"
+  [(set_attr "type" "imul")])
 
 ;; If operands 0 and 2 are in the same register, we have a problem.  But
 ;; operands 0 and 1 (the usual case) can be in the same register.  That's
@@ -2664,7 +3391,7 @@
 ;; just handle shifts by constants.
 
 (define_expand "ashrdi3"
-  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
 		   (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:SI 2 "general_operand" "")))
 	      (clobber (match_scratch:SI 3 ""))])]
@@ -2685,6 +3412,91 @@
    sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
   [(set_attr "length" "8")])
 
+;; PowerPC64 DImode operations.
+
+(define_insn "ffsdi2"
+  [(set (match_operand:DI 0 "register_operand" "=&r")
+	(ffs:DI (match_operand:DI 1 "register_operand" "r")))]
+  "TARGET_POWERPC64"
+  "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
+  [(set_attr "length" "16")])
+
+(define_insn "muldi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "mulld %0,%1,%2"
+   [(set_attr "type" "imul")])
+
+(define_insn "smuldi3_highpart"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (sign_extend:TI
+				(match_operand:DI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:TI
+				(match_operand:DI 2 "gpc_reg_operand" "r")))
+		      (const_int 64))))]
+  "TARGET_POWERPC64"
+  "mulhd %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "umuldi3_highpart"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (zero_extend:TI
+				(match_operand:DI 1 "gpc_reg_operand" "%r"))
+			       (zero_extend:TI
+				(match_operand:DI 2 "gpc_reg_operand" "r")))
+		      (const_int 64))))]
+  "TARGET_POWERPC64"
+  "mulhdu %0,%1,%2"
+  [(set_attr "type" "imul")])
+
+(define_insn "divdi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+        (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "divd %0,%1,%2"
+  [(set_attr "type" "idiv")])
+
+(define_insn "udivdi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+        (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64"
+  "divdu %0,%1,%2"
+  [(set_attr "type" "idiv")])
+
+(define_insn "rotldi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		   (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
+  "TARGET_POWERPC64"
+  "rld%I2cl %0,%1,%h2,0")
+
+(define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			       (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+		    (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r"))]
+  "TARGET_POWERPC64"
+  "rld%I2cl. %3,%1,%h2,0"
+  [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			       (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+		    (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(rotate:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "rld%I2cl. %0,%1,%h2,0"
+  [(set_attr "type" "delayed_compare")])
+
 ;; Now define ways of moving data around.
 ;;
 ;; For SI, we special-case integers that can't be loaded in one insn.  We
@@ -2703,6 +3515,25 @@
   if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT
       && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
     {
+      /* If we are to limit the number of things we put in the TOC and
+	 this is a symbol plus a constant we can add in one insn,
+	 just put the sumbol in the TOC and add the constant.  Don't do
+	 this if reload is in progress.  */
+      if (GET_CODE (operands[1]) == CONST
+	  && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
+	  && GET_CODE (XEXP (operands[1], 0)) == PLUS
+	  && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
+	  && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
+	      || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
+	  && ! side_effects_p (operands[0]))
+	{
+	  rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
+	  rtx other = XEXP (XEXP (operands[1], 0), 1);
+
+	  emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
+	  DONE;
+	}
+
       operands[1] = force_const_mem (SImode, operands[1]);
       if (! memory_address_p (SImode, XEXP (operands[1], 0))
 	  && ! reload_in_progress)
@@ -2725,36 +3556,22 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h")
-	(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))]
-  "TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
-   || gpc_reg_operand (operands[1], SImode))"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h")
+	(match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))]
+  "gpc_reg_operand (operands[0], SImode)
+   || gpc_reg_operand (operands[1], SImode)"
   "@
-   {ai|addic} %0,%1,0
+   mr %0,%1
    {l%U1%X1|lwz%U1%X1} %0,%1
    {st%U0%X0|stw%U0%X0} %1,%0
-   {cal %0,%1(0)|li %0,%1}
-   {cau %0,0,%u1|lis %0,%u1}
+   {lil|li} %0,%1
+   {liu|lis} %0,%u1
+   {cal|la} %0,%1(%*)
    mf%1 %0
    mt%0 %1
    mt%0 %1
    cror 0,0,0"
-  [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
-	(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
-  "! TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
-   || gpc_reg_operand (operands[1], SImode))"
-  "@
-   mr %0,%1
-   lwz%U1%X1 %0,%1
-   stw%U0%X0 %1,%0
-   li %0,%1
-   lis %0,%u1
-   mf%1 %0
-   mt%0 %1"
-  [(set_attr "type" "*,load,*,*,*,*,*")])
+  [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")])
 
 ;; Split a load of a large constant into the appropriate two-insn
 ;; sequence.
@@ -2782,7 +3599,7 @@
 		    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
   ""
-  "{ai.|addic.} %0,%1,0"
+  "mr. %0,%1"
   [(set_attr "type" "compare")])
 
 (define_expand "movhi"
@@ -2805,33 +3622,20 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
-	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
-  "TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
-   || gpc_reg_operand (operands[1], HImode))"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
+	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+  "gpc_reg_operand (operands[0], HImode)
+   || gpc_reg_operand (operands[1], HImode)"
   "@
-   {oril|ori} %0,%1,0
+   mr %0,%1
    lhz%U1%X1 %0,%1
    sth%U0%X0 %1,%0
-   {cal %0,%w1(0)|li %0,%w1}
+   {lil|li} %0,%w1
    mf%1 %0
    mt%0 %1
+   mt%0 %1
    cror 0,0,0"
-  [(set_attr "type" "*,load,*,*,*,*,*")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
-	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
-   || gpc_reg_operand (operands[1], HImode))"
-  "@
-   ori %0,%1,0
-   lhz%U1%X1 %0,%1
-   sth%U0%X0 %1,%0
-   li %0,%w1
-   mf%1 %0
-   mt%0 %1"
-  [(set_attr "type" "*,load,*,*,*,*")])
+  [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand" "")
@@ -2853,33 +3657,20 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
-	(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
-  "TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
-   || gpc_reg_operand (operands[1], QImode))"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
+	(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+  "gpc_reg_operand (operands[0], QImode)
+   || gpc_reg_operand (operands[1], QImode)"
   "@
-   {oril|ori} %0,%1,0
+   mr %0,%1
    lbz%U1%X1 %0,%1
    stb%U0%X0 %1,%0
-   {cal %0,%1(0)|li %0,%1}
+   {lil|li} %0,%1
    mf%1 %0
    mt%0 %1
+   mt%0 %1
    cror 0,0,0"
-  [(set_attr "type" "*,load,*,*,*,*,*")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
-	(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "! TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
-   || gpc_reg_operand (operands[1], QImode))"
-  "@
-   mr %0,%1
-   lbz%U1%X1 %0,%1
-   stb%U0%X0 %1,%0
-   li %0,%1
-   mf%1 %0
-   mt%0 %1"
-  [(set_attr "type" "*,load,*,*,*,*")])
+  [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
 
 ;; Here is how to move condition codes around.  When we store CC data in
 ;; an integer register or memory, we store just the high-order 4 bits.
@@ -2901,7 +3692,7 @@
    {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
    mfcr %0
    mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
-   {ai %0,%1,0|mr %0,%1}
+   mr %0,%1
    {l%U1%X1|lwz%U1%X1} %0,%1
    {st%U0%U1|stw%U0%U1} %1,%0"
   [(set_attr "type" "*,*,*,compare,*,*,load,*")
@@ -2931,8 +3722,6 @@
 
   if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
     {
-      rtx stack_slot;
-
       /* If this is a store to memory or another integer register do the
 	 move directly.  Otherwise store to a temporary stack slot and
 	 load from there into a floating point register.  */
@@ -2947,41 +3736,55 @@
 			  operand_subword (operands[1], 0, 0, SFmode));
 	  DONE;
 	}
+      else
+	{
+	  rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
 
-      stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
-      emit_move_insn (stack_slot, operands[1]);
-      emit_move_insn (operands[0], stack_slot);
-      DONE;
+	  emit_move_insn (stack_slot, operands[1]);
+	  emit_move_insn (operands[0], stack_slot);
+	  DONE;
+	}
     }
 
   if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
+    {
+      /* If operands[1] is a register, it may have double-precision data
+	 in it, so truncate it to single precision.  We need not do
+	 this for POWERPC.  */
+      if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
+	{
+	  rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+	  emit_insn (gen_truncdfsf2 (newreg,
+				     gen_rtx (SUBREG, DFmode, operands[1], 0)));
+	  operands[1] = newreg;
+	}
+
+      operands[1] = force_reg (SFmode, operands[1]);
+    }
 
   if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
     {
-      rtx stack_slot;
-
       if (GET_CODE (operands[1]) == MEM
 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
 	  || GET_CODE (operands[1]) == CONST_DOUBLE
 #endif
-	  || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
-	  || (reload_in_progress && GET_CODE (operands[1]) == REG
-	      && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
+	  || (GET_CODE (operands[1]) == REG
+	      && (REGNO (operands[1]) < 32
+		  || (reload_in_progress
+		      && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
 	{
 	  emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
 			  operand_subword (operands[1], 0, 0, SFmode));
 	  DONE;
 	}
-
-      if (reload_in_progress)
-	stack_slot = gen_rtx (MEM, SFmode,
-			      plus_constant (stack_pointer_rtx, 4));
       else
-	stack_slot = assign_stack_temp (SFmode, 4, 0);
-      emit_move_insn (stack_slot, operands[1]);
-      emit_move_insn (operands[0], stack_slot);
-      DONE;
+	{
+	  rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
+
+	  emit_move_insn (stack_slot, operands[1]);
+	  emit_move_insn (operands[0], stack_slot);
+	  DONE;
+	}
     }
 
   if (CONSTANT_P (operands[1]))
@@ -3011,9 +3814,8 @@
   "@
    fmr %0,%1
    lfs%U1%X1 %0,%1
-   frsp %1,%1\;stfs%U0%X0 %1,%0"
-  [(set_attr "type" "fp,fpload,*")
-   (set_attr "length" "*,*,8")])
+   stfs%U0%X0 %1,%0"
+  [(set_attr "type" "fp,fpload,*")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -3064,8 +3866,8 @@
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
 	(match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
-  "register_operand (operands[0], DFmode)
-   || register_operand (operands[1], DFmode)"
+  "! TARGET_POWERPC64 && (register_operand (operands[0], DFmode)
+   || register_operand (operands[1], DFmode))"
   "*
 {
   switch (which_alternative)
@@ -3075,9 +3877,9 @@
 	 the first register operand 0 is the same as the second register of
 	 operand 1, we must copy in the opposite order.  */
       if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
+	return \"mr %L0,%L1\;mr %0,%1\";
       else
-	return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
+	return \"mr %0,%1\;mr %L0,%L1\";
     case 1:
       /* If the low-address word is used in the address, we must load it
 	 last.  Otherwise, load it first.  Note that we cannot have
@@ -3102,6 +3904,21 @@
 }"
   [(set_attr "type" "*,load,*,*,fp,fpload,*")
    (set_attr "length" "8,8,8,8,*,*,*")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
+	(match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
+  "TARGET_POWERPC64 && (register_operand (operands[0], DFmode)
+   || register_operand (operands[1], DFmode))"
+  "@
+   mr %0,%1
+   ld%U1%X1 %0,%1
+   sd%U0%X0 %1,%0
+   #
+   fmr %0,%1
+   lfd%U1%X1 %0,%1
+   stfd%U0%X0 %1,%0"
+  [(set_attr "type" "*,load,*,*,fp,fpload,*")])
 
 ;; Next come the multi-word integer load and store and the load and store
 ;; multiple insns.
@@ -3123,13 +3940,29 @@
 
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (DImode, operands[1]);
+
+      /* Stores between FPR and any non-FPR registers must go through a
+         temporary stack slot.  */
+
+  if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+      && ((FP_REGNO_P (REGNO (operands[0]))
+	   && ! FP_REGNO_P (REGNO (operands[1])))
+	  || (FP_REGNO_P (REGNO (operands[1]))
+	      && ! FP_REGNO_P (REGNO (operands[0])))))
+    {
+      rtx stack_slot = assign_stack_temp (DImode, 8, 0);
+
+      emit_move_insn (stack_slot, operands[1]);
+      emit_move_insn (operands[0], stack_slot);
+      DONE;
+    }
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
-	(match_operand:DI 1 "input_operand" "r,m,r"))]
-  "gpc_reg_operand (operands[0], DImode)
-   || gpc_reg_operand (operands[1], DImode)"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m")
+	(match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))]
+  "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
+   || gpc_reg_operand (operands[1], DImode))"
   "*
 {
   switch (which_alternative)
@@ -3139,9 +3972,9 @@
 	 the first register operand 0 is the same as the second register of
 	 operand 1, we must copy in the opposite order.  */
       if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
+	return \"mr %L0,%L1\;mr %0,%1\";
       else
-	return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
+	return \"mr %0,%1\;mr %L0,%L1\";
     case 1:
       /* If the low-address word is used in the address, we must load it
 	 last.  Otherwise, load it first.  Note that we cannot have
@@ -3154,10 +3987,35 @@
 	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
     case 2:
       return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
+    case 3:
+      return \"fmr %0,%1\";
+    case 4:
+      return \"lfd%U1%X1 %0,%1\";
+    case 5:
+      return \"stfd%U0%X0 %1,%0\";
     }
 }"
-  [(set_attr "type" "*,load,*")
-   (set_attr "length" "8")])
+  [(set_attr "type" "*,load,*,fp,fpload,*")
+   (set_attr "length" "8,8,8,*,*,*")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h")
+	(match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))]
+  "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
+   || gpc_reg_operand (operands[1], DImode))"
+  "@
+   mr %0,%1
+   ld%U1%X1 %0,%1
+   sd%U0%X0 %1,%0
+   li %0,%1
+   lis %0,%u1
+   {cal|la} %0,%1(%*)
+   fmr %0,%1
+   lfd%U1%X1 %0,%1
+   stfd%U0%X0 %1,%0
+   mf%1 %0
+   mt%0 %1"
+  [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")])
 
 ;; TImode is similar, except that we usually want to compute the address into
 ;; a register and use lsi/stsi (the exception is during reload).  MQ is also
@@ -3166,7 +4024,7 @@
   [(parallel [(set (match_operand:TI 0 "general_operand" "")
 		   (match_operand:TI 1 "general_operand" ""))
 	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
+  "TARGET_POWER || TARGET_POWERPC64"
   "
 {
   if (GET_CODE (operands[0]) == MEM)
@@ -3191,10 +4049,10 @@
 ;; are preferred.  Otherwise, we'd try to reload the output instead of
 ;; giving the SCRATCH mq.
 (define_insn ""
-  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
+  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
 	(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
    (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
-  "TARGET_POWER && (gpc_reg_operand (operands[0], TImode)
+  "TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
    || gpc_reg_operand (operands[1], TImode))"
   "*
 {
@@ -3212,9 +4070,9 @@
 	 is the second, third, or fourth register in the input.  */
       if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
 	  && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
-	return \"{oril %Z0,%Z1,0|mr %Z0,%Z1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
+	return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
       else
-	return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %Z0,%Z1,0|mr %Z0,%Z1}\";
+	return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
     case 3:
       /* If the address is not used in the output, we can use lsi.  Otherwise,
 	 fall through to generating four loads.  */
@@ -3240,6 +4098,40 @@
 }"
   [(set_attr "type" "*,load,load,*,*")
    (set_attr "length" "*,16,16,*,16")])
+
+(define_insn ""
+  [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
+	(match_operand:TI 1 "input_operand" "r,m,r"))]
+  "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
+   || gpc_reg_operand (operands[1], TImode))"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+      /* We normally copy the low-numbered register first.  However, if
+	 the first register operand 0 is the same as the second register of
+	 operand 1, we must copy in the opposite order.  */
+      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
+	return \"mr %L0,%L1\;mr %0,%1\";
+      else
+	return \"mr %0,%1\;mr %L0,%L1\";
+    case 1:
+      /* If the low-address word is used in the address, we must load it
+	 last.  Otherwise, load it first.  Note that we cannot have
+	 auto-increment in that case since the address register is known to be
+	 dead.  */
+      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			     operands [1], 0))
+	return \"ld %L0,%L1\;ld %0,%1\";
+      else
+	return \"ld%U1 %0,%1\;ld %L0,%L1\";
+    case 2:
+      return \"std%U0 %1,%0\;std %L1,%L0\";
+    }
+}"
+  [(set_attr "type" "*,load,*")
+   (set_attr "length" "8,8,8")])
 
 (define_expand "load_multiple"
   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
@@ -3369,6 +4261,29 @@
 ;; that will benefit the most).
 
 (define_insn ""
+  [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
+	(mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
+			 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
+	(plus:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "@
+   ldux %3,%0,%2
+   ldu %3,%2(%0)"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
+			 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
+	(match_operand:DI 3 "gpc_reg_operand" "r,r"))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
+	(plus:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "@
+   stdux %3,%0,%2
+   stdu %3,%2(%0)")
+
+(define_insn ""
   [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
 	(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
@@ -3478,7 +4393,7 @@
 
 (define_insn ""
   [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
-	(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
+	(mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
    (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -3496,8 +4411,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   frsp %3,%3\;stfsux %3,%0,%2
-   frsp %3,%3\;stfsu %3,%2(%0)")
+   stfsux %3,%0,%2
+   stfsu %3,%2(%0)")
 
 (define_insn ""
   [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
@@ -4434,7 +5349,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
+	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 		       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
   ""
   "@
@@ -4512,7 +5427,7 @@
   "@
    doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
    {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
-  [(set_attr "type" "delayed_compare,compare")
+  [(set_attr "type" "compare,delayed_compare")
    (set_attr "length" "12")])
 
 (define_insn ""
@@ -4686,7 +5601,7 @@
    [(set_attr "length" "12")])
 
 (define_insn ""
-  [(set (match_operand:SI 3 "cc_reg_operand" "=x")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
 	 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI"))
@@ -4709,7 +5624,7 @@
   [(set_attr "length" "12")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "cc_reg_operand" "=x")
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
@@ -4722,7 +5637,7 @@
    (set_attr "length" "12")])
 
 (define_insn ""
-  [(set (match_operand:SI 5 "cc_reg_operand" "=x")
+  [(set (match_operand:CC 5 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
@@ -5297,7 +6212,6 @@
 }"
   [(set_attr "type" "branch")])
 
-
 (define_insn ""
   [(set (pc)
 	(if_then_else (match_operator 0 "branch_comparison_operator"
@@ -5351,14 +6265,16 @@
 (define_insn "return"
   [(return)]
   "direct_return ()"
-  "{br|blr}")
+  "{br|blr}"
+  [(set_attr "type" "jmpreg")])
 
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
   ""
   "@
    bctr
-   {br|blr}")
+   {br|blr}"
+  [(set_attr "type" "jmpreg")])
 
 ;; Table jump for switch statements:
 (define_expand "tablejump"