--- gcc/config/rs6000/rs6000.md	2018/04/24 18:30:35	1.1.1.4
+++ gcc/config/rs6000/rs6000.md	2018/04/24 18:35:54	1.1.1.5
@@ -814,7 +814,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(not:SI (match_dup 1)))]
   ""
-  "nor. %0,%2,%1"
+  "nor. %0,%1,%1"
   [(set_attr "type" "compare")])
 
 (define_insn ""
@@ -1492,7 +1492,9 @@
    (set (reg:SI 4)
 	(umod:SI (reg:SI 3) (reg:SI 4)))
    (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
+   (clobber (reg:SI 0))
+   (clobber (match_scratch:CC 1 "=x"))
+   (clobber (reg:CC 69))]
   "! TARGET_POWER && ! TARGET_POWERPC"
   "bla __divus")
 
@@ -1507,7 +1509,9 @@
   [(set (reg:SI 3)
 	(udiv:SI (reg:SI 3) (reg:SI 4)))
    (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
+   (clobber (reg:SI 0))
+   (clobber (match_scratch:CC 1 "=x"))
+   (clobber (reg:CC 69))]
   "! TARGET_POWER && ! TARGET_POWERPC"
   "bla __quous")
 
@@ -4823,10 +4827,10 @@
 ;; Argument 3 is the alignment
 
 (define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
-		   (match_operand:BLK 1 "memory_operand" ""))
-	      (use (match_operand:SI 2 "general_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))])]
+  [(parallel [(set (match_operand:BLK 0 "" "")
+		   (match_operand:BLK 1 "" ""))
+	      (use (match_operand:SI 2 "" ""))
+	      (use (match_operand:SI 3 "" ""))])]
   ""
   "
 {
@@ -4839,10 +4843,10 @@
 ;; Move up to 32 bytes at a time.  The fixed registers are needed because the
 ;; register allocator doesn't have a clue about allocating 8 word registers
 (define_expand "movstrsi_8reg"
-  [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-		   (mem:BLK (match_operand:SI 1 "register_operand" "")))
-	      (use (match_operand:SI 2 "immediate_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
+  [(parallel [(set (match_operand 0 "" "")
+		   (match_operand 1 "" ""))
+	      (use (match_operand 2 "" ""))
+	      (use (match_operand 3 "" ""))
 	      (clobber (reg:SI  5))
 	      (clobber (reg:SI  6))
 	      (clobber (reg:SI  7))
@@ -4875,7 +4879,8 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -4897,15 +4902,16 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Move up to 24 bytes at a time.  The fixed registers are needed because the
 ;; register allocator doesn't have a clue about allocating 6 word registers
 (define_expand "movstrsi_6reg"
-  [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-		   (mem:BLK (match_operand:SI 1 "register_operand" "")))
-	      (use (match_operand:SI 2 "immediate_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
+  [(parallel [(set (match_operand 0 "" "")
+		   (match_operand 1 "" ""))
+	      (use (match_operand 2 "" ""))
+	      (use (match_operand 3 "" ""))
 	      (clobber (reg:SI  7))
 	      (clobber (reg:SI  8))
 	      (clobber (reg:SI  9))
@@ -4934,7 +4940,8 @@
    && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 7"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -4954,15 +4961,16 @@
    && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 7"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
 ;; with TImode
 (define_expand "movstrsi_4reg"
-  [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-		   (mem:BLK (match_operand:SI 1 "register_operand" "")))
-	      (use (match_operand:SI 2 "immediate_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
+  [(parallel [(set (match_operand 0 "" "")
+		   (match_operand 1 "" ""))
+	      (use (match_operand 2 "" ""))
+	      (use (match_operand 3 "" ""))
 	      (clobber (reg:SI  9))
 	      (clobber (reg:SI 10))
 	      (clobber (reg:SI 11))
@@ -4987,7 +4995,8 @@
    && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 9"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5005,14 +5014,15 @@
    && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 9"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Move up to 8 bytes at a time.
 (define_expand "movstrsi_2reg"
-  [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-		   (mem:BLK (match_operand:SI 1 "register_operand" "")))
-	      (use (match_operand:SI 2 "immediate_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
+  [(parallel [(set (match_operand 0 "" "")
+		   (match_operand 1 "" ""))
+	      (use (match_operand 2 "" ""))
+	      (use (match_operand 3 "" ""))
 	      (clobber (match_scratch:DI 4 ""))
 	      (clobber (match_scratch:SI 5 ""))])]
   "TARGET_STRING && !TARGET_64BIT"
@@ -5028,7 +5038,8 @@
   "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5040,14 +5051,15 @@
   "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Move up to 4 bytes at a time.
 (define_expand "movstrsi_1reg"
-  [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-		   (mem:BLK (match_operand:SI 1 "register_operand" "")))
-	      (use (match_operand:SI 2 "immediate_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
+  [(parallel [(set (match_operand 0 "" "")
+		   (match_operand 1 "" ""))
+	      (use (match_operand 2 "" ""))
+	      (use (match_operand 3 "" ""))
 	      (clobber (match_scratch:SI 4 ""))
 	      (clobber (match_scratch:SI 5 ""))])]
   "TARGET_STRING"
@@ -5063,7 +5075,8 @@
   "TARGET_STRING && TARGET_POWER
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5075,7 +5088,8 @@
   "TARGET_STRING && !TARGET_POWER
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "length" "8")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 
 ;; Define insns that do load or store with update.  Some of these we can