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1.1 ! root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler ! 2: ;; Copyright (C) 1990, 1991, 1992, 1993 Free Software Foundation, Inc. ! 3: ;; Contributed by Richard Kenner ([email protected]) ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 2, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 22: ! 23: ;; Define an insn type attribute. This is used in function unit delay ! 24: ;; computations. ! 25: (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr" ! 26: (const_string "integer")) ! 27: ! 28: ;; Memory delivers its result in two cycles. ! 29: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0) ! 30: ! 31: ;; We consider floating-point insns to deliver their result in two cycles ! 32: ;; to try to intersperse integer and FP operations. ! 33: (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0) ! 34: ! 35: ;; Most integer comparisons are ready in four cycles (a stall of three). ! 36: (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0) ! 37: ! 38: ;; Some integer comparisons aren't ready for five cycles (a stall of four). ! 39: (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0) ! 40: ! 41: ;; Floating-point comparisons take eight cycles. ! 42: (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0) ! 43: ! 44: ;; Branches on LR cannot be done until five cycles after LR is set. ! 45: (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0) ! 46: ! 47: ;; Start with fixed-point load and store insns. Here we put only the more ! 48: ;; complex forms. Basic data transfer is done later. ! 49: ! 50: (define_expand "zero_extendqisi2" ! 51: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 52: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] ! 53: "" ! 54: "") ! 55: ! 56: (define_insn "" ! 57: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 58: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] ! 59: "" ! 60: "@ ! 61: lbz%U1%X1 %0,%1 ! 62: rlinm %0,%1,0,24,31" ! 63: [(set_attr "type" "load,*")]) ! 64: ! 65: (define_insn "" ! 66: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 67: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 68: (const_int 0))) ! 69: (clobber (match_scratch:SI 2 "=r"))] ! 70: "" ! 71: "andil. %2,%1,255" ! 72: [(set_attr "type" "compare")]) ! 73: ! 74: (define_insn "" ! 75: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 76: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 77: (const_int 0))) ! 78: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 79: (zero_extend:SI (match_dup 1)))] ! 80: "" ! 81: "andil. %0,%1,255" ! 82: [(set_attr "type" "compare")]) ! 83: ! 84: (define_expand "zero_extendqihi2" ! 85: [(set (match_operand:HI 0 "gpc_reg_operand" "") ! 86: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] ! 87: "" ! 88: "") ! 89: ! 90: (define_insn "" ! 91: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") ! 92: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] ! 93: "" ! 94: "@ ! 95: lbz%U1%X1 %0,%1 ! 96: rlinm %0,%1,0,24,31" ! 97: [(set_attr "type" "load,*")]) ! 98: ! 99: (define_expand "zero_extendhisi2" ! 100: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 101: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 102: "" ! 103: "") ! 104: ! 105: (define_insn "" ! 106: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 107: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 108: "" ! 109: "@ ! 110: lhz%U1%X1 %0,%1 ! 111: rlinm %0,%1,0,16,31" ! 112: [(set_attr "type" "load,*")]) ! 113: ! 114: (define_insn "" ! 115: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 116: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 117: (const_int 0))) ! 118: (clobber (match_scratch:SI 2 "=r"))] ! 119: "" ! 120: "andil. %2,%1,65535" ! 121: [(set_attr "type" "compare")]) ! 122: ! 123: (define_insn "" ! 124: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 125: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 126: (const_int 0))) ! 127: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 128: (zero_extend:SI (match_dup 1)))] ! 129: "" ! 130: "andil. %0,%1,65535" ! 131: [(set_attr "type" "compare")]) ! 132: ! 133: (define_expand "extendhisi2" ! 134: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 135: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 136: "" ! 137: "") ! 138: ! 139: (define_insn "" ! 140: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 141: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 142: "" ! 143: "@ ! 144: lha%U1%X1 %0,%1 ! 145: exts %0,%1" ! 146: [(set_attr "type" "load,*")]) ! 147: ! 148: (define_insn "" ! 149: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 150: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 151: (const_int 0))) ! 152: (clobber (match_scratch:SI 2 "=r"))] ! 153: "" ! 154: "exts. %2,%1" ! 155: [(set_attr "type" "compare")]) ! 156: ! 157: (define_insn "" ! 158: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 159: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 160: (const_int 0))) ! 161: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 162: (sign_extend:SI (match_dup 1)))] ! 163: "" ! 164: "exts. %0,%1" ! 165: [(set_attr "type" "compare")]) ! 166: ! 167: ;; Fixed-point arithmetic insns. ! 168: (define_insn "addsi3" ! 169: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 170: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") ! 171: (match_operand:SI 2 "add_operand" "rI,J")))] ! 172: "" ! 173: "@ ! 174: a%I2 %0,%1,%2 ! 175: cau %0,%1,%u2") ! 176: ! 177: (define_insn "" ! 178: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 179: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 180: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 181: (const_int 0))) ! 182: (clobber (match_scratch:SI 3 "=r"))] ! 183: "" ! 184: "a%I2. %3,%1,%2" ! 185: [(set_attr "type" "compare")]) ! 186: ! 187: (define_insn "" ! 188: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 189: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 190: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 191: (const_int 0))) ! 192: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 193: (plus:SI (match_dup 1) (match_dup 2)))] ! 194: "" ! 195: "a%I2. %0,%1,%2" ! 196: [(set_attr "type" "compare")]) ! 197: ! 198: ;; Split an add that we can't do in one insn into two insns, each of which ! 199: ;; does one 16-bit part. This is used by combine. Note that the low-order ! 200: ;; add should be last in case the result gets used in an address. ! 201: ! 202: (define_split ! 203: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 204: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 205: (match_operand:SI 2 "non_add_cint_operand" "")))] ! 206: "" ! 207: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) ! 208: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] ! 209: " ! 210: { ! 211: int low = INTVAL (operands[2]) & 0xffff; ! 212: int high = (unsigned) INTVAL (operands[2]) >> 16; ! 213: ! 214: if (low & 0x8000) ! 215: high++, low |= 0xffff0000; ! 216: ! 217: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); ! 218: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); ! 219: }") ! 220: ! 221: (define_insn "one_cmplsi2" ! 222: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 223: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 224: "" ! 225: "sfi %0,%1,-1") ! 226: ! 227: (define_insn "" ! 228: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 229: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") ! 230: (match_operand:SI 2 "gpc_reg_operand" "r,r")))] ! 231: "" ! 232: "@ ! 233: sf %0,%2,%1 ! 234: sfi %0,%2,%1") ! 235: ! 236: (define_insn "" ! 237: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 238: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 239: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 240: (const_int 0))) ! 241: (clobber (match_scratch:SI 3 "=r"))] ! 242: "" ! 243: "sf. %3,%2,%1" ! 244: [(set_attr "type" "compare")]) ! 245: ! 246: (define_insn "" ! 247: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 248: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 249: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 250: (const_int 0))) ! 251: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 252: (minus:SI (match_dup 1) (match_dup 2)))] ! 253: "" ! 254: "sf. %0,%2,%1" ! 255: [(set_attr "type" "compare")]) ! 256: ! 257: (define_expand "subsi3" ! 258: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 259: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") ! 260: (match_operand:SI 2 "reg_or_cint_operand" "")))] ! 261: "" ! 262: " ! 263: { ! 264: if (GET_CODE (operands[2]) == CONST_INT) ! 265: { ! 266: emit_insn (gen_addsi3 (operands[0], operands[1], ! 267: negate_rtx (SImode, operands[2]))); ! 268: DONE; ! 269: } ! 270: }") ! 271: ! 272: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] ! 273: ;; instruction and some auxiliary computations. Then we just have a single ! 274: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by ! 275: ;; combine. ! 276: ! 277: (define_expand "sminsi3" ! 278: [(set (match_dup 3) ! 279: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 280: (match_operand:SI 2 "reg_or_short_operand" "")) ! 281: (const_int 0) ! 282: (minus:SI (match_dup 2) (match_dup 1)))) ! 283: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 284: (minus:SI (match_dup 2) (match_dup 3)))] ! 285: "" ! 286: " ! 287: { operands[3] = gen_reg_rtx (SImode); }") ! 288: ! 289: (define_split ! 290: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 291: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 292: (match_operand:SI 2 "reg_or_short_operand" ""))) ! 293: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 294: "" ! 295: [(set (match_dup 3) ! 296: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) ! 297: (const_int 0) ! 298: (minus:SI (match_dup 2) (match_dup 1)))) ! 299: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] ! 300: "") ! 301: ! 302: (define_expand "smaxsi3" ! 303: [(set (match_dup 3) ! 304: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 305: (match_operand:SI 2 "reg_or_short_operand" "")) ! 306: (const_int 0) ! 307: (minus:SI (match_dup 2) (match_dup 1)))) ! 308: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 309: (plus:SI (match_dup 3) (match_dup 1)))] ! 310: "" ! 311: " ! 312: { operands[3] = gen_reg_rtx (SImode); }") ! 313: ! 314: (define_split ! 315: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 316: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 317: (match_operand:SI 2 "reg_or_short_operand" ""))) ! 318: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 319: "" ! 320: [(set (match_dup 3) ! 321: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) ! 322: (const_int 0) ! 323: (minus:SI (match_dup 2) (match_dup 1)))) ! 324: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] ! 325: "") ! 326: ! 327: (define_expand "uminsi3" ! 328: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 329: (const_int -2147483648))) ! 330: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") ! 331: (const_int -2147483648))) ! 332: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) ! 333: (const_int 0) ! 334: (minus:SI (match_dup 4) (match_dup 3)))) ! 335: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 336: (minus:SI (match_dup 2) (match_dup 3)))] ! 337: "" ! 338: " ! 339: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") ! 340: ! 341: (define_expand "umaxsi3" ! 342: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 343: (const_int -2147483648))) ! 344: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") ! 345: (const_int -2147483648))) ! 346: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) ! 347: (const_int 0) ! 348: (minus:SI (match_dup 4) (match_dup 3)))) ! 349: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 350: (plus:SI (match_dup 3) (match_dup 1)))] ! 351: "" ! 352: " ! 353: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") ! 354: ! 355: (define_insn "" ! 356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 357: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 358: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 359: (const_int 0) ! 360: (minus:SI (match_dup 2) (match_dup 1))))] ! 361: "" ! 362: "doz%I2 %0,%1,%2") ! 363: ! 364: (define_insn "" ! 365: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 366: (compare:CC ! 367: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 368: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 369: (const_int 0) ! 370: (minus:SI (match_dup 2) (match_dup 1))) ! 371: (const_int 0))) ! 372: (clobber (match_scratch:SI 3 "=r"))] ! 373: "" ! 374: "doz%I2. %3,%1,%2" ! 375: [(set_attr "type" "delayed_compare")]) ! 376: ! 377: (define_insn "" ! 378: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 379: (compare:CC ! 380: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 381: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 382: (const_int 0) ! 383: (minus:SI (match_dup 2) (match_dup 1))) ! 384: (const_int 0))) ! 385: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 386: (if_then_else:SI (gt (match_dup 1) (match_dup 2)) ! 387: (const_int 0) ! 388: (minus:SI (match_dup 2) (match_dup 1))))] ! 389: "" ! 390: "doz%I2. %0,%1,%2" ! 391: [(set_attr "type" "delayed_compare")]) ! 392: ! 393: ;; We don't need abs with condition code because such comparisons should ! 394: ;; never be done. ! 395: (define_insn "abssi2" ! 396: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 397: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 398: "" ! 399: "abs %0,%1") ! 400: ! 401: (define_insn "" ! 402: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 403: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] ! 404: "" ! 405: "nabs %0,%1") ! 406: ! 407: (define_insn "negsi2" ! 408: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 409: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 410: "" ! 411: "neg %0,%1") ! 412: ! 413: (define_insn "" ! 414: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 415: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 416: (const_int 0))) ! 417: (clobber (match_scratch:SI 2 "=r"))] ! 418: "" ! 419: "neg. %2,%1" ! 420: [(set_attr "type" "compare")]) ! 421: ! 422: (define_insn "" ! 423: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 424: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 425: (const_int 0))) ! 426: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 427: (neg:SI (match_dup 1)))] ! 428: "" ! 429: "neg. %0,%1" ! 430: [(set_attr "type" "compare")]) ! 431: ! 432: (define_insn "ffssi2" ! 433: [(set (match_operand:SI 0 "register_operand" "=&r") ! 434: (ffs:SI (match_operand:SI 1 "register_operand" "r")))] ! 435: "" ! 436: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32") ! 437: ! 438: (define_insn "mulsi3" ! 439: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 440: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 441: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 442: (clobber (match_scratch:SI 3 "=q,q"))] ! 443: "" ! 444: "@ ! 445: muls %0,%1,%2 ! 446: muli %0,%1,%2") ! 447: ! 448: (define_insn "" ! 449: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 450: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 451: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 452: (const_int 0))) ! 453: (clobber (match_scratch:SI 3 "=r")) ! 454: (clobber (match_scratch:SI 4 "=q"))] ! 455: "" ! 456: "muls. %3,%1,%2" ! 457: [(set_attr "type" "delayed_compare")]) ! 458: ! 459: (define_insn "" ! 460: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 461: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 462: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 463: (const_int 0))) ! 464: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 465: (mult:SI (match_dup 1) (match_dup 2))) ! 466: (clobber (match_scratch:SI 4 "=q"))] ! 467: "" ! 468: "muls. %0,%1,%2" ! 469: [(set_attr "type" "delayed_compare")]) ! 470: ! 471: ;; Operand 1 is divided by operand 2; quotient goes to operand ! 472: ;; 0 and remainder to operand 3. ! 473: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). ! 474: ! 475: (define_insn "divmodsi4" ! 476: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 477: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 478: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 479: (set (match_operand:SI 3 "gpc_reg_operand" "=q") ! 480: (mod:SI (match_dup 1) (match_dup 2)))] ! 481: "" ! 482: "divs %0,%1,%2") ! 483: ! 484: ;; For powers of two we can do srai/aze for divide and then adjust for ! 485: ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used. ! 486: (define_expand "divsi3" ! 487: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 488: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 489: (match_operand:SI 2 "reg_or_cint_operand" "")))] ! 490: "" ! 491: " ! 492: { ! 493: if (GET_CODE (operands[2]) != CONST_INT ! 494: || exact_log2 (INTVAL (operands[2])) < 0) ! 495: FAIL; ! 496: }") ! 497: ! 498: (define_expand "modsi3" ! 499: [(set (match_dup 3) ! 500: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 501: (match_operand:SI 2 "reg_or_cint_operand" ""))) ! 502: (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5))) ! 503: (clobber (scratch:SI))]) ! 504: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 505: (minus:SI (match_dup 1) (match_dup 4)))] ! 506: "" ! 507: " ! 508: { ! 509: int i = exact_log2 (INTVAL (operands[2])); ! 510: ! 511: if (GET_CODE (operands[2]) != CONST_INT || i < 0) ! 512: FAIL; ! 513: ! 514: operands[3] = gen_reg_rtx (SImode); ! 515: operands[4] = gen_reg_rtx (SImode); ! 516: operands[5] = gen_rtx (CONST_INT, VOIDmode, i); ! 517: }") ! 518: ! 519: (define_insn "" ! 520: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 521: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 522: (match_operand:SI 2 "const_int_operand" "N")))] ! 523: "exact_log2 (INTVAL (operands[2])) >= 0" ! 524: "srai %0,%1,%p2\;aze %0,%0") ! 525: ! 526: (define_insn "" ! 527: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 528: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 529: (match_operand:SI 2 "const_int_operand" "N"))) ! 530: (clobber (match_scratch:SI 3 "=r"))] ! 531: "exact_log2 (INTVAL (operands[2])) >= 0" ! 532: "srai %3,%1,%p2\;aze. %3,%3" ! 533: [(set_attr "type" "compare")]) ! 534: ! 535: (define_insn "" ! 536: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 537: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 538: (match_operand:SI 2 "const_int_operand" "N"))) ! 539: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 540: (div:SI (match_dup 1) (match_dup 2)))] ! 541: "exact_log2 (INTVAL (operands[2])) >= 0" ! 542: "srai %0,%1,%p2\;aze. %0,%0" ! 543: [(set_attr "type" "compare")]) ! 544: ! 545: (define_insn "" ! 546: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 547: (udiv:SI ! 548: (plus:DI (lshift:DI ! 549: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 550: (const_int 32)) ! 551: (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) ! 552: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 553: (set (match_operand:SI 2 "register_operand" "=*q") ! 554: (umod:SI ! 555: (plus:DI (lshift:DI ! 556: (zero_extend:DI (match_dup 1)) (const_int 32)) ! 557: (zero_extend:DI (match_dup 4))) ! 558: (match_dup 3)))] ! 559: ! 560: "" ! 561: "div %0,%1,%3") ! 562: ! 563: ;; To do unsigned divide we handle the cases of the divisor looking like a ! 564: ;; negative number. If it is a constant that is less than 2**31, we don't ! 565: ;; have to worry about the branches. So make a few subroutines here. ! 566: ;; ! 567: ;; First comes the normal case. ! 568: (define_expand "udivmodsi4_normal" ! 569: [(set (match_dup 4) (const_int 0)) ! 570: (parallel [(set (match_operand:SI 0 "" "") ! 571: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) ! 572: (const_int 32)) ! 573: (zero_extend:DI (match_operand:SI 1 "" ""))) ! 574: (match_operand:SI 2 "" ""))) ! 575: (set (match_operand:SI 3 "" "") ! 576: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) ! 577: (const_int 32)) ! 578: (zero_extend:DI (match_dup 1))) ! 579: (match_dup 2)))])] ! 580: "" ! 581: " ! 582: { operands[4] = gen_reg_rtx (SImode); }") ! 583: ! 584: ;; This handles the branches. ! 585: (define_expand "udivmodsi4_tests" ! 586: [(set (match_operand:SI 0 "" "") (const_int 0)) ! 587: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) ! 588: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) ! 589: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) ! 590: (label_ref (match_operand:SI 4 "" "")) (pc))) ! 591: (set (match_dup 0) (const_int 1)) ! 592: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) ! 593: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) ! 594: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) ! 595: (label_ref (match_dup 4)) (pc)))] ! 596: "" ! 597: " ! 598: { operands[5] = gen_reg_rtx (CCUNSmode); ! 599: operands[6] = gen_reg_rtx (CCmode); ! 600: }") ! 601: ! 602: (define_expand "udivmodsi4" ! 603: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 604: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 605: (match_operand:SI 2 "reg_or_cint_operand" ""))) ! 606: (set (match_operand:SI 3 "gpc_reg_operand" "") ! 607: (umod:SI (match_dup 1) (match_dup 2)))])] ! 608: "" ! 609: " ! 610: { ! 611: rtx label = 0; ! 612: ! 613: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) ! 614: { ! 615: operands[2] = force_reg (SImode, operands[2]); ! 616: label = gen_label_rtx (); ! 617: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], ! 618: operands[3], label)); ! 619: } ! 620: else ! 621: operands[2] = force_reg (SImode, operands[2]); ! 622: ! 623: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], ! 624: operands[3])); ! 625: if (label) ! 626: emit_label (label); ! 627: ! 628: DONE; ! 629: }") ! 630: ! 631: (define_insn "andsi3" ! 632: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 633: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 634: (match_operand:SI 2 "and_operand" "?r,L,K,J"))) ! 635: (clobber (match_scratch:CC 3 "=X,X,x,x"))] ! 636: "" ! 637: "@ ! 638: and %0,%1,%2 ! 639: rlinm %0,%1,0,%m2,%M2 ! 640: andil. %0,%1,%b2 ! 641: andiu. %0,%1,%u2") ! 642: ! 643: (define_insn "" ! 644: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") ! 645: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 646: (match_operand:SI 2 "and_operand" "r,K,J,L")) ! 647: (const_int 0))) ! 648: (clobber (match_scratch:SI 3 "=r,r,r,r"))] ! 649: "" ! 650: "@ ! 651: and. %3,%1,%2 ! 652: andil. %3,%1,%b2 ! 653: andiu. %3,%1,%u2 ! 654: rlinm. %3,%1,0,%m2,%M2" ! 655: [(set_attr "type" "compare,compare,compare,delayed_compare")]) ! 656: ! 657: (define_insn "" ! 658: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") ! 659: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 660: (match_operand:SI 2 "and_operand" "r,K,J,L")) ! 661: (const_int 0))) ! 662: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 663: (and:SI (match_dup 1) (match_dup 2)))] ! 664: "" ! 665: "@ ! 666: and. %0,%1,%2 ! 667: andil. %0,%1,%b2 ! 668: andiu. %0,%1,%u2 ! 669: rlinm. %0,%1,0,%m2,%M2" ! 670: [(set_attr "type" "compare,compare,compare,delayed_compare")]) ! 671: ! 672: ;; Take a AND with a constant that cannot be done in a single insn and try to ! 673: ;; split it into two insns. This does not verify that the insns are valid ! 674: ;; since this need not be done as combine will do it. ! 675: ! 676: (define_split ! 677: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 678: (and:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 679: (match_operand:SI 2 "non_and_cint_operand" "")))] ! 680: "" ! 681: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) ! 682: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] ! 683: " ! 684: { ! 685: int maskval = INTVAL (operands[2]); ! 686: int i, transitions, last_bit_value; ! 687: int orig = maskval, first_c = maskval, second_c; ! 688: ! 689: /* We know that MASKVAL must have more than 2 bit-transitions. Start at ! 690: the low-order bit and count for the third transition. When we get there, ! 691: make a first mask that has everything to the left of that position ! 692: a one. Then make the second mask to turn off whatever else is needed. */ ! 693: ! 694: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) ! 695: { ! 696: if (((maskval >>= 1) & 1) != last_bit_value) ! 697: last_bit_value ^= 1, transitions++; ! 698: ! 699: if (transitions > 2) ! 700: { ! 701: first_c |= (~0) << i; ! 702: break; ! 703: } ! 704: } ! 705: ! 706: second_c = orig | ~ first_c; ! 707: ! 708: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); ! 709: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); ! 710: }") ! 711: ! 712: (define_insn "iorsi3" ! 713: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 714: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") ! 715: (match_operand:SI 2 "logical_operand" "r,K,J")))] ! 716: "" ! 717: "@ ! 718: or %0,%1,%2 ! 719: oril %0,%1,%b2 ! 720: oriu %0,%1,%u2") ! 721: ! 722: (define_insn "" ! 723: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 724: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 725: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 726: (const_int 0))) ! 727: (clobber (match_scratch:SI 3 "=r"))] ! 728: "" ! 729: "or. %3,%1,%2" ! 730: [(set_attr "type" "compare")]) ! 731: ! 732: (define_insn "" ! 733: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 734: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 735: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 736: (const_int 0))) ! 737: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 738: (ior:SI (match_dup 1) (match_dup 2)))] ! 739: "" ! 740: "or. %0,%1,%2" ! 741: [(set_attr "type" "compare")]) ! 742: ! 743: ;; Split an IOR that we can't do in one insn into two insns, each of which ! 744: ;; does one 16-bit part. This is used by combine. ! 745: ! 746: (define_split ! 747: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 748: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 749: (match_operand:SI 2 "non_logical_cint_operand" "")))] ! 750: "" ! 751: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) ! 752: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] ! 753: " ! 754: { ! 755: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 756: INTVAL (operands[2]) & 0xffff0000); ! 757: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); ! 758: }") ! 759: ! 760: (define_insn "xorsi3" ! 761: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 762: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") ! 763: (match_operand:SI 2 "logical_operand" "r,K,J")))] ! 764: "" ! 765: "@ ! 766: xor %0,%1,%2 ! 767: xoril %0,%1,%b2 ! 768: xoriu %0,%1,%u2") ! 769: ! 770: (define_insn "" ! 771: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 772: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 773: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 774: (const_int 0))) ! 775: (clobber (match_scratch:SI 3 "=r"))] ! 776: "" ! 777: "xor. %3,%1,%2" ! 778: [(set_attr "type" "compare")]) ! 779: ! 780: (define_insn "" ! 781: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 782: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 783: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 784: (const_int 0))) ! 785: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 786: (xor:SI (match_dup 1) (match_dup 2)))] ! 787: "" ! 788: "xor. %0,%1,%2" ! 789: [(set_attr "type" "compare")]) ! 790: ! 791: ;; Split an XOR that we can't do in one insn into two insns, each of which ! 792: ;; does one 16-bit part. This is used by combine. ! 793: ! 794: (define_split ! 795: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 796: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 797: (match_operand:SI 2 "non_logical_cint_operand" "")))] ! 798: "" ! 799: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) ! 800: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] ! 801: " ! 802: { ! 803: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 804: INTVAL (operands[2]) & 0xffff0000); ! 805: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); ! 806: }") ! 807: ! 808: (define_insn "" ! 809: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 810: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 811: (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 812: "" ! 813: "eqv %0,%1,%2") ! 814: ! 815: (define_insn "" ! 816: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 817: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 818: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 819: (const_int 0))) ! 820: (clobber (match_scratch:SI 3 "=r"))] ! 821: "" ! 822: "eqv. %3,%1,%2" ! 823: [(set_attr "type" "compare")]) ! 824: ! 825: (define_insn "" ! 826: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 827: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 828: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 829: (const_int 0))) ! 830: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 831: (not:SI (xor:SI (match_dup 1) (match_dup 2))))] ! 832: "" ! 833: "eqv. %0,%1,%2" ! 834: [(set_attr "type" "compare")]) ! 835: ! 836: (define_insn "" ! 837: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 838: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 839: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 840: "" ! 841: "andc %0,%2,%1") ! 842: ! 843: (define_insn "" ! 844: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 845: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 846: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 847: (const_int 0))) ! 848: (clobber (match_scratch:SI 3 "=r"))] ! 849: "" ! 850: "andc. %3,%2,%1" ! 851: [(set_attr "type" "compare")]) ! 852: ! 853: (define_insn "" ! 854: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 855: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 856: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 857: (const_int 0))) ! 858: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 859: (and:SI (not:SI (match_dup 1)) (match_dup 2)))] ! 860: "" ! 861: "andc. %0,%2,%1" ! 862: [(set_attr "type" "compare")]) ! 863: ! 864: (define_insn "" ! 865: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 866: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 867: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 868: "" ! 869: "orc %0,%2,%1") ! 870: ! 871: (define_insn "" ! 872: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 873: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 874: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 875: (const_int 0))) ! 876: (clobber (match_scratch:SI 3 "=r"))] ! 877: "" ! 878: "orc. %3,%2,%1" ! 879: [(set_attr "type" "compare")]) ! 880: ! 881: (define_insn "" ! 882: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 883: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 884: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 885: (const_int 0))) ! 886: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 887: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] ! 888: "" ! 889: "orc. %0,%2,%1" ! 890: [(set_attr "type" "compare")]) ! 891: ! 892: (define_insn "" ! 893: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 894: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 895: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 896: "" ! 897: "nand %0,%1,%2") ! 898: ! 899: (define_insn "" ! 900: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 901: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 902: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 903: (const_int 0))) ! 904: (clobber (match_scratch:SI 3 "=r"))] ! 905: "" ! 906: "nand. %3,%1,%2" ! 907: [(set_attr "type" "compare")]) ! 908: ! 909: (define_insn "" ! 910: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 911: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 912: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 913: (const_int 0))) ! 914: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 915: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] ! 916: "" ! 917: "nand. %0,%1,%2" ! 918: [(set_attr "type" "compare")]) ! 919: ! 920: (define_insn "" ! 921: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 922: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 923: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 924: "" ! 925: "nor %0,%1,%2") ! 926: ! 927: (define_insn "" ! 928: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 929: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 930: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 931: (const_int 0))) ! 932: (clobber (match_scratch:SI 3 "=r"))] ! 933: "" ! 934: "nor. %3,%1,%2" ! 935: [(set_attr "type" "compare")]) ! 936: ! 937: (define_insn "" ! 938: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 939: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 940: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 941: (const_int 0))) ! 942: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 943: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] ! 944: "" ! 945: "nor. %0,%1,%2" ! 946: [(set_attr "type" "compare")]) ! 947: ! 948: ;; maskir insn. We need four forms because things might be in arbitrary ! 949: ;; orders. Don't define forms that only set CR fields because these ! 950: ;; would modify an input register. ! 951: ! 952: (define_insn "" ! 953: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 954: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 955: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 956: (and:SI (match_dup 2) ! 957: (match_operand:SI 3 "gpc_reg_operand" "r"))))] ! 958: "" ! 959: "maskir %0,%3,%2") ! 960: ! 961: (define_insn "" ! 962: [(set (match_operand:SI 0 "register_operand" "=r") ! 963: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 964: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 965: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 966: (match_dup 2))))] ! 967: "" ! 968: "maskir %0,%3,%2") ! 969: ! 970: (define_insn "" ! 971: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 972: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 973: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 974: (and:SI (not:SI (match_dup 2)) ! 975: (match_operand:SI 1 "gpc_reg_operand" "0"))))] ! 976: "" ! 977: "maskir %0,%3,%2") ! 978: ! 979: (define_insn "" ! 980: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 981: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 982: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 983: (and:SI (not:SI (match_dup 2)) ! 984: (match_operand:SI 1 "gpc_reg_operand" "0"))))] ! 985: "" ! 986: "maskir %0,%3,%2") ! 987: ! 988: (define_insn "" ! 989: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 990: (compare:CC ! 991: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 992: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 993: (and:SI (match_dup 2) ! 994: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 995: (const_int 0))) ! 996: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 997: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) ! 998: (and:SI (match_dup 2) (match_dup 3))))] ! 999: "" ! 1000: "maskir. %0,%3,%2" ! 1001: [(set_attr "type" "compare")]) ! 1002: ! 1003: (define_insn "" ! 1004: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1005: (compare:CC ! 1006: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1007: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 1008: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1009: (match_dup 2))) ! 1010: (const_int 0))) ! 1011: (set (match_operand:SI 0 "register_operand" "=r") ! 1012: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) ! 1013: (and:SI (match_dup 3) (match_dup 2))))] ! 1014: "" ! 1015: "maskir. %0,%3,%2" ! 1016: [(set_attr "type" "compare")]) ! 1017: ! 1018: (define_insn "" ! 1019: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1020: (compare:CC ! 1021: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1022: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 1023: (and:SI (not:SI (match_dup 2)) ! 1024: (match_operand:SI 1 "gpc_reg_operand" "0"))) ! 1025: (const_int 0))) ! 1026: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1027: (ior:SI (and:SI (match_dup 2) (match_dup 3)) ! 1028: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] ! 1029: "" ! 1030: "maskir. %0,%3,%2" ! 1031: [(set_attr "type" "compare")]) ! 1032: ! 1033: (define_insn "" ! 1034: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1035: (compare:CC ! 1036: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1037: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1038: (and:SI (not:SI (match_dup 2)) ! 1039: (match_operand:SI 1 "gpc_reg_operand" "0"))) ! 1040: (const_int 0))) ! 1041: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1042: (ior:SI (and:SI (match_dup 3) (match_dup 2)) ! 1043: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] ! 1044: "" ! 1045: "maskir. %0,%3,%2" ! 1046: [(set_attr "type" "compare")]) ! 1047: ! 1048: ;; Rotate and shift insns, in all their variants. These support shifts, ! 1049: ;; field inserts and extracts, and various combinations thereof. ! 1050: (define_insn "insv" ! 1051: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1052: (match_operand:SI 1 "const_int_operand" "i") ! 1053: (match_operand:SI 2 "const_int_operand" "i")) ! 1054: (match_operand:SI 3 "gpc_reg_operand" "r"))] ! 1055: "" ! 1056: "* ! 1057: { ! 1058: int start = INTVAL (operands[2]) & 31; ! 1059: int size = INTVAL (operands[1]) & 31; ! 1060: ! 1061: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); ! 1062: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); ! 1063: return \"rlimi %0,%3,%4,%h2,%h1\"; ! 1064: }") ! 1065: ! 1066: (define_insn "extzv" ! 1067: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1068: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1069: (match_operand:SI 2 "const_int_operand" "i") ! 1070: (match_operand:SI 3 "const_int_operand" "i")))] ! 1071: "" ! 1072: "* ! 1073: { ! 1074: int start = INTVAL (operands[3]) & 31; ! 1075: int size = INTVAL (operands[2]) & 31; ! 1076: ! 1077: if (start + size >= 32) ! 1078: operands[3] = const0_rtx; ! 1079: else ! 1080: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1081: return \"rlinm %0,%1,%3,%s2,31\"; ! 1082: }") ! 1083: ! 1084: (define_insn "" ! 1085: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1086: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1087: (match_operand:SI 2 "const_int_operand" "i") ! 1088: (match_operand:SI 3 "const_int_operand" "i")) ! 1089: (const_int 0))) ! 1090: (clobber (match_scratch:SI 4 "=r"))] ! 1091: "" ! 1092: "* ! 1093: { ! 1094: int start = INTVAL (operands[3]) & 31; ! 1095: int size = INTVAL (operands[2]) & 31; ! 1096: ! 1097: /* If the bitfield being tested fits in the upper or lower half of a ! 1098: word, it is possible to use andiu. or andil. to test it. This is ! 1099: useful because the condition register set-use delay is smaller for ! 1100: andi[ul]. than for rlinm. This doesn't work when the starting bit ! 1101: position is 0 because the LT and GT bits may be set wrong. */ ! 1102: ! 1103: if ((start > 0 && start + size <= 16) || start >= 16) ! 1104: { ! 1105: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 1106: ((1 << (16 - (start & 15))) ! 1107: - (1 << (16 - (start & 15) - size)))); ! 1108: if (start < 16) ! 1109: return \"andiu. %4,%1,%3\"; ! 1110: else ! 1111: return \"andil. %4,%1,%3\"; ! 1112: } ! 1113: ! 1114: if (start + size >= 32) ! 1115: operands[3] = const0_rtx; ! 1116: else ! 1117: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1118: return \"rlinm. %4,%1,%3,%s2,31\"; ! 1119: }" ! 1120: [(set_attr "type" "compare")]) ! 1121: ! 1122: (define_insn "" ! 1123: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1124: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1125: (match_operand:SI 2 "const_int_operand" "i") ! 1126: (match_operand:SI 3 "const_int_operand" "i")) ! 1127: (const_int 0))) ! 1128: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1129: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] ! 1130: "" ! 1131: "* ! 1132: { ! 1133: int start = INTVAL (operands[3]) & 31; ! 1134: int size = INTVAL (operands[2]) & 31; ! 1135: ! 1136: if (start >= 16 && start + size == 32) ! 1137: { ! 1138: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); ! 1139: return \"andil. %0,%1,%3\"; ! 1140: } ! 1141: ! 1142: if (start + size >= 32) ! 1143: operands[3] = const0_rtx; ! 1144: else ! 1145: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1146: return \"rlinm. %0,%1,%3,%s2,31\"; ! 1147: }" ! 1148: [(set_attr "type" "delayed_compare")]) ! 1149: ! 1150: (define_insn "rotlsi3" ! 1151: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1152: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1153: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] ! 1154: "" ! 1155: "rl%I2nm %0,%1,%h2,0,31") ! 1156: ! 1157: (define_insn "" ! 1158: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1159: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1160: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1161: (const_int 0))) ! 1162: (clobber (match_scratch:SI 3 "=r"))] ! 1163: "" ! 1164: "rl%I2nm. %3,%1,%h2,0,31" ! 1165: [(set_attr "type" "delayed_compare")]) ! 1166: ! 1167: (define_insn "" ! 1168: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1169: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1170: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1171: (const_int 0))) ! 1172: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1173: (rotate:SI (match_dup 1) (match_dup 2)))] ! 1174: "" ! 1175: "rl%I2nm. %0,%1,%h2,0,31" ! 1176: [(set_attr "type" "delayed_compare")]) ! 1177: ! 1178: (define_insn "" ! 1179: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1180: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1181: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1182: (match_operand:SI 3 "mask_operand" "L")))] ! 1183: "" ! 1184: "rl%I2nm %0,%1,%h2,%m3,%M3") ! 1185: ! 1186: (define_insn "" ! 1187: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1188: (compare:CC (and:SI ! 1189: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1190: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1191: (match_operand:SI 3 "mask_operand" "L")) ! 1192: (const_int 0))) ! 1193: (clobber (match_scratch:SI 4 "=r"))] ! 1194: "" ! 1195: "rl%I2nm. %4,%1,%h2,%m3,%M3" ! 1196: [(set_attr "type" "delayed_compare")]) ! 1197: ! 1198: (define_insn "" ! 1199: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1200: (compare:CC (and:SI ! 1201: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1202: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1203: (match_operand:SI 3 "mask_operand" "L")) ! 1204: (const_int 0))) ! 1205: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1206: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1207: "" ! 1208: "rl%I2nm. %0,%1,%h2,%m3,%M3" ! 1209: [(set_attr "type" "delayed_compare")]) ! 1210: ! 1211: (define_insn "" ! 1212: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1213: (zero_extend:SI ! 1214: (subreg:QI ! 1215: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1216: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] ! 1217: "" ! 1218: "rl%I2nm %0,%1,%h2,24,31") ! 1219: ! 1220: (define_insn "" ! 1221: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1222: (compare:CC (zero_extend:SI ! 1223: (subreg:QI ! 1224: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1225: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1226: (const_int 0))) ! 1227: (clobber (match_scratch:SI 3 "=r"))] ! 1228: "" ! 1229: "rl%I2nm. %3,%1,%h2,24,31" ! 1230: [(set_attr "type" "delayed_compare")]) ! 1231: ! 1232: (define_insn "" ! 1233: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1234: (compare:CC (zero_extend:SI ! 1235: (subreg:QI ! 1236: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1237: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1238: (const_int 0))) ! 1239: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1240: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] ! 1241: "" ! 1242: "rl%I2nm. %0,%1,%h2,24,31" ! 1243: [(set_attr "type" "delayed_compare")]) ! 1244: ! 1245: (define_insn "" ! 1246: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1247: (zero_extend:SI ! 1248: (subreg:HI ! 1249: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1250: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] ! 1251: "" ! 1252: "rl%I2nm %0,%1,%h2,16,31") ! 1253: ! 1254: (define_insn "" ! 1255: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1256: (compare:CC (zero_extend:SI ! 1257: (subreg:HI ! 1258: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1259: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1260: (const_int 0))) ! 1261: (clobber (match_scratch:SI 3 "=r"))] ! 1262: "" ! 1263: "rl%I2nm. %3,%1,%h2,16,31" ! 1264: [(set_attr "type" "delayed_compare")]) ! 1265: ! 1266: (define_insn "" ! 1267: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1268: (compare:CC (zero_extend:SI ! 1269: (subreg:HI ! 1270: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1271: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1272: (const_int 0))) ! 1273: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1274: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] ! 1275: "" ! 1276: "rl%I2nm. %0,%1,%h2,16,31" ! 1277: [(set_attr "type" "delayed_compare")]) ! 1278: ! 1279: ;; Note that we use "sle." instead of "sl." so that we can set ! 1280: ;; SHIFT_COUNT_TRUNCATED. ! 1281: ! 1282: (define_insn "ashlsi3" ! 1283: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1284: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1285: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1286: (clobber (match_scratch:SI 3 "=q,X"))] ! 1287: "" ! 1288: "@ ! 1289: sle %0,%1,%2 ! 1290: sli %0,%1,%h2") ! 1291: ! 1292: (define_insn "" ! 1293: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1294: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1295: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1296: (const_int 0))) ! 1297: (clobber (match_scratch:SI 3 "=r,r")) ! 1298: (clobber (match_scratch:SI 4 "=q,X"))] ! 1299: "" ! 1300: "@ ! 1301: sle. %3,%1,%2 ! 1302: sli. %3,%1,%h2" ! 1303: [(set_attr "type" "delayed_compare")]) ! 1304: ! 1305: (define_insn "" ! 1306: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1307: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1308: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1309: (const_int 0))) ! 1310: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1311: (ashift:SI (match_dup 1) (match_dup 2))) ! 1312: (clobber (match_scratch:SI 4 "=q,X"))] ! 1313: "" ! 1314: "@ ! 1315: sle. %0,%1,%2 ! 1316: sli. %0,%1,%h2" ! 1317: [(set_attr "type" "delayed_compare")]) ! 1318: ! 1319: (define_insn "" ! 1320: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1321: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1322: (match_operand:SI 2 "const_int_operand" "i")) ! 1323: (match_operand:SI 3 "mask_operand" "L")))] ! 1324: "includes_lshift_p (operands[2], operands[3])" ! 1325: "rlinm %0,%h1,%h2,%m3,%M3") ! 1326: ! 1327: (define_insn "" ! 1328: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1329: (compare:CC ! 1330: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1331: (match_operand:SI 2 "const_int_operand" "i")) ! 1332: (match_operand:SI 3 "mask_operand" "L")) ! 1333: (const_int 0))) ! 1334: (clobber (match_scratch:SI 4 "=r"))] ! 1335: "includes_lshift_p (operands[2], operands[3])" ! 1336: "rlinm. %4,%h1,%h2,%m3,%M3" ! 1337: [(set_attr "type" "delayed_compare")]) ! 1338: ! 1339: (define_insn "" ! 1340: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1341: (compare:CC ! 1342: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1343: (match_operand:SI 2 "const_int_operand" "i")) ! 1344: (match_operand:SI 3 "mask_operand" "L")) ! 1345: (const_int 0))) ! 1346: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1347: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1348: "includes_lshift_p (operands[2], operands[3])" ! 1349: "rlinm. %0,%h1,%h2,%m3,%M3" ! 1350: [(set_attr "type" "delayed_compare")]) ! 1351: ! 1352: ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as ! 1353: ;; "sli x,x,0". ! 1354: (define_insn "lshrsi3" ! 1355: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1356: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1357: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1358: (clobber (match_scratch:SI 3 "=q,X"))] ! 1359: "" ! 1360: "@ ! 1361: sre %0,%1,%2 ! 1362: s%A2i %0,%1,%h2") ! 1363: ! 1364: (define_insn "" ! 1365: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1366: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1367: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1368: (const_int 0))) ! 1369: (clobber (match_scratch:SI 3 "=r,r")) ! 1370: (clobber (match_scratch:SI 4 "=q,X"))] ! 1371: "" ! 1372: "@ ! 1373: sre. %3,%1,%2 ! 1374: s%A2i. %3,%1,%h2" ! 1375: [(set_attr "type" "delayed_compare")]) ! 1376: ! 1377: (define_insn "" ! 1378: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1379: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1380: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1381: (const_int 0))) ! 1382: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1383: (lshiftrt:SI (match_dup 1) (match_dup 2))) ! 1384: (clobber (match_scratch:SI 4 "=q,X"))] ! 1385: "" ! 1386: "@ ! 1387: sre. %0,%1,%2 ! 1388: s%A2i. %0,%1,%h2" ! 1389: [(set_attr "type" "delayed_compare")]) ! 1390: ! 1391: (define_insn "" ! 1392: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1393: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1394: (match_operand:SI 2 "const_int_operand" "i")) ! 1395: (match_operand:SI 3 "mask_operand" "L")))] ! 1396: "includes_rshift_p (operands[2], operands[3])" ! 1397: "rlinm %0,%1,%s2,%m3,%M3") ! 1398: ! 1399: (define_insn "" ! 1400: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1401: (compare:CC ! 1402: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1403: (match_operand:SI 2 "const_int_operand" "i")) ! 1404: (match_operand:SI 3 "mask_operand" "L")) ! 1405: (const_int 0))) ! 1406: (clobber (match_scratch:SI 4 "=r"))] ! 1407: "includes_rshift_p (operands[2], operands[3])" ! 1408: "rlinm. %4,%1,%s2,%m3,%M3" ! 1409: [(set_attr "type" "delayed_compare")]) ! 1410: ! 1411: (define_insn "" ! 1412: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1413: (compare:CC ! 1414: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1415: (match_operand:SI 2 "const_int_operand" "i")) ! 1416: (match_operand:SI 3 "mask_operand" "L")) ! 1417: (const_int 0))) ! 1418: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1419: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1420: "includes_rshift_p (operands[2], operands[3])" ! 1421: "rlinm. %0,%1,%s2,%m3,%M3" ! 1422: [(set_attr "type" "delayed_compare")]) ! 1423: ! 1424: (define_insn "" ! 1425: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1426: (zero_extend:SI ! 1427: (subreg:QI ! 1428: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1429: (match_operand:SI 2 "const_int_operand" "i")) 0)))] ! 1430: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1431: "rlinm %0,%1,%s2,24,31") ! 1432: ! 1433: (define_insn "" ! 1434: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1435: (compare:CC ! 1436: (zero_extend:SI ! 1437: (subreg:QI ! 1438: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1439: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1440: (const_int 0))) ! 1441: (clobber (match_scratch:SI 3 "=r"))] ! 1442: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1443: "rlinm. %3,%1,%s2,24,31" ! 1444: [(set_attr "type" "delayed_compare")]) ! 1445: ! 1446: (define_insn "" ! 1447: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1448: (compare:CC ! 1449: (zero_extend:SI ! 1450: (subreg:QI ! 1451: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1452: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1453: (const_int 0))) ! 1454: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1455: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] ! 1456: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1457: "rlinm. %0,%1,%s2,24,31" ! 1458: [(set_attr "type" "delayed_compare")]) ! 1459: ! 1460: (define_insn "" ! 1461: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1462: (zero_extend:SI ! 1463: (subreg:HI ! 1464: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1465: (match_operand:SI 2 "const_int_operand" "i")) 0)))] ! 1466: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1467: "rlinm %0,%1,%s2,16,31") ! 1468: ! 1469: (define_insn "" ! 1470: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1471: (compare:CC ! 1472: (zero_extend:SI ! 1473: (subreg:HI ! 1474: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1475: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1476: (const_int 0))) ! 1477: (clobber (match_scratch:SI 3 "=r"))] ! 1478: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1479: "rlinm. %3,%1,%s2,16,31" ! 1480: [(set_attr "type" "delayed_compare")]) ! 1481: ! 1482: (define_insn "" ! 1483: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1484: (compare:CC ! 1485: (zero_extend:SI ! 1486: (subreg:HI ! 1487: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1488: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1489: (const_int 0))) ! 1490: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1491: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] ! 1492: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1493: "rlinm. %0,%1,%s2,16,31" ! 1494: [(set_attr "type" "delayed_compare")]) ! 1495: ! 1496: (define_insn "" ! 1497: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1498: (const_int 1) ! 1499: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1500: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1501: (const_int 31)))] ! 1502: "" ! 1503: "rrib %0,%1,%2") ! 1504: ! 1505: (define_insn "" ! 1506: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1507: (const_int 1) ! 1508: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1509: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1510: (const_int 31)))] ! 1511: "" ! 1512: "rrib %0,%1,%2") ! 1513: ! 1514: (define_insn "" ! 1515: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1516: (const_int 1) ! 1517: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1518: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1519: (const_int 1) ! 1520: (const_int 0)))] ! 1521: "" ! 1522: "rrib %0,%1,%2") ! 1523: ! 1524: (define_insn "ashrsi3" ! 1525: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1526: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1527: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1528: (clobber (match_scratch:SI 3 "=q,X"))] ! 1529: "" ! 1530: "@ ! 1531: srea %0,%1,%2 ! 1532: srai %0,%1,%h2") ! 1533: ! 1534: (define_insn "" ! 1535: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1536: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1537: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1538: (const_int 0))) ! 1539: (clobber (match_scratch:SI 3 "=r,r")) ! 1540: (clobber (match_scratch:SI 4 "=q,X"))] ! 1541: "" ! 1542: "@ ! 1543: srea. %3,%1,%2 ! 1544: srai. %3,%1,%h2" ! 1545: [(set_attr "type" "delayed_compare")]) ! 1546: ! 1547: (define_insn "" ! 1548: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1549: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1550: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1551: (const_int 0))) ! 1552: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1553: (ashiftrt:SI (match_dup 1) (match_dup 2))) ! 1554: (clobber (match_scratch:SI 4 "=q,X"))] ! 1555: "" ! 1556: "@ ! 1557: srea. %0,%1,%2 ! 1558: srai. %0,%1,%h2" ! 1559: [(set_attr "type" "delayed_compare")]) ! 1560: ! 1561: (define_expand "extendqisi2" ! 1562: [(parallel [(set (match_dup 2) ! 1563: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 1564: (const_int 24))) ! 1565: (clobber (scratch:SI))]) ! 1566: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1567: (ashiftrt:SI (match_dup 2) ! 1568: (const_int 24))) ! 1569: (clobber (scratch:SI))])] ! 1570: "" ! 1571: " ! 1572: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1573: operands[2] = gen_reg_rtx (SImode); }") ! 1574: ! 1575: (define_expand "extendqihi2" ! 1576: [(parallel [(set (match_dup 2) ! 1577: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 1578: (const_int 24))) ! 1579: (clobber (scratch:SI))]) ! 1580: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") ! 1581: (ashiftrt:SI (match_dup 2) ! 1582: (const_int 24))) ! 1583: (clobber (scratch:SI))])] ! 1584: "" ! 1585: " ! 1586: { operands[0] = gen_lowpart (SImode, operands[0]); ! 1587: operands[1] = gen_lowpart (SImode, operands[1]); ! 1588: operands[2] = gen_reg_rtx (SImode); }") ! 1589: ! 1590: ;; Floating-point insns, excluding normal data motion. ! 1591: ;; ! 1592: ;; We pretend that we have both SFmode and DFmode insns, while, in fact, ! 1593: ;; all fp insns are actually done in double. The only conversions we will ! 1594: ;; do will be when storing to memory. In that case, we will use the "frsp" ! 1595: ;; instruction before storing. ! 1596: ;; ! 1597: ;; Note that when we store into a single-precision memory location, we need to ! 1598: ;; use the frsp insn first. If the register being stored isn't dead, we ! 1599: ;; need a scratch register for the frsp. But this is difficult when the store ! 1600: ;; is done by reload. It is not incorrect to do the frsp on the register in ! 1601: ;; this case, we just lose precision that we would have otherwise gotten but ! 1602: ;; is not guaranteed. Perhaps this should be tightened up at some point. ! 1603: ! 1604: (define_insn "extendsfdf2" ! 1605: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1606: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 1607: "" ! 1608: "* ! 1609: { ! 1610: if (REGNO (operands[0]) == REGNO (operands[1])) ! 1611: return \"\"; ! 1612: else ! 1613: return \"fmr %0,%1\"; ! 1614: }" ! 1615: [(set_attr "type" "fp")]) ! 1616: ! 1617: (define_insn "truncdfsf2" ! 1618: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1619: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 1620: "" ! 1621: "* ! 1622: { ! 1623: if (REGNO (operands[0]) == REGNO (operands[1])) ! 1624: return \"\"; ! 1625: else ! 1626: return \"fmr %0,%1\"; ! 1627: }" ! 1628: [(set_attr "type" "fp")]) ! 1629: ! 1630: (define_insn "negsf2" ! 1631: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1632: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 1633: "" ! 1634: "fneg %0,%1" ! 1635: [(set_attr "type" "fp")]) ! 1636: ! 1637: (define_insn "abssf2" ! 1638: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1639: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 1640: "" ! 1641: "fabs %0,%1" ! 1642: [(set_attr "type" "fp")]) ! 1643: ! 1644: (define_insn "" ! 1645: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1646: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] ! 1647: "" ! 1648: "fnabs %0,%1" ! 1649: [(set_attr "type" "fp")]) ! 1650: ! 1651: (define_insn "addsf3" ! 1652: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1653: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1654: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 1655: "" ! 1656: "fa %0,%1,%2" ! 1657: [(set_attr "type" "fp")]) ! 1658: ! 1659: (define_insn "subsf3" ! 1660: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1661: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 1662: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 1663: "" ! 1664: "fs %0,%1,%2" ! 1665: [(set_attr "type" "fp")]) ! 1666: ! 1667: (define_insn "mulsf3" ! 1668: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1669: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1670: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 1671: "" ! 1672: "fm %0,%1,%2" ! 1673: [(set_attr "type" "fp")]) ! 1674: ! 1675: (define_insn "divsf3" ! 1676: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1677: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 1678: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 1679: "" ! 1680: "fd %0,%1,%2" ! 1681: [(set_attr "type" "fp")]) ! 1682: ! 1683: (define_insn "" ! 1684: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1685: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1686: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 1687: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 1688: "" ! 1689: "fma %0,%1,%2,%3" ! 1690: [(set_attr "type" "fp")]) ! 1691: ! 1692: (define_insn "" ! 1693: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1694: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1695: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 1696: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 1697: "" ! 1698: "fms %0,%1,%2,%3" ! 1699: [(set_attr "type" "fp")]) ! 1700: ! 1701: (define_insn "" ! 1702: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1703: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1704: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 1705: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 1706: "" ! 1707: "fnma %0,%1,%2,%3" ! 1708: [(set_attr "type" "fp")]) ! 1709: ! 1710: (define_insn "" ! 1711: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 1712: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 1713: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 1714: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 1715: "" ! 1716: "fnms %0,%1,%2,%3" ! 1717: [(set_attr "type" "fp")]) ! 1718: ! 1719: (define_insn "negdf2" ! 1720: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1721: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 1722: "" ! 1723: "fneg %0,%1" ! 1724: [(set_attr "type" "fp")]) ! 1725: ! 1726: (define_insn "absdf2" ! 1727: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1728: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 1729: "" ! 1730: "fabs %0,%1" ! 1731: [(set_attr "type" "fp")]) ! 1732: ! 1733: (define_insn "" ! 1734: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1735: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] ! 1736: "" ! 1737: "fnabs %0,%1" ! 1738: [(set_attr "type" "fp")]) ! 1739: ! 1740: (define_insn "adddf3" ! 1741: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1742: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1743: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 1744: "" ! 1745: "fa %0,%1,%2" ! 1746: [(set_attr "type" "fp")]) ! 1747: ! 1748: (define_insn "subdf3" ! 1749: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1750: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") ! 1751: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 1752: "" ! 1753: "fs %0,%1,%2" ! 1754: [(set_attr "type" "fp")]) ! 1755: ! 1756: (define_insn "muldf3" ! 1757: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1758: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1759: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 1760: "" ! 1761: "fm %0,%1,%2" ! 1762: [(set_attr "type" "fp")]) ! 1763: ! 1764: (define_insn "divdf3" ! 1765: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1766: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") ! 1767: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 1768: "" ! 1769: "fd %0,%1,%2" ! 1770: [(set_attr "type" "fp")]) ! 1771: ! 1772: (define_insn "" ! 1773: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1774: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1775: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 1776: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 1777: "" ! 1778: "fma %0,%1,%2,%3" ! 1779: [(set_attr "type" "fp")]) ! 1780: ! 1781: (define_insn "" ! 1782: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1783: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1784: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 1785: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 1786: "" ! 1787: "fms %0,%1,%2,%3" ! 1788: [(set_attr "type" "fp")]) ! 1789: ! 1790: (define_insn "" ! 1791: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1792: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1793: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 1794: (match_operand:DF 3 "gpc_reg_operand" "f"))))] ! 1795: "" ! 1796: "fnma %0,%1,%2,%3" ! 1797: [(set_attr "type" "fp")]) ! 1798: ! 1799: (define_insn "" ! 1800: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 1801: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 1802: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 1803: (match_operand:DF 3 "gpc_reg_operand" "f"))))] ! 1804: "" ! 1805: "fnms %0,%1,%2,%3" ! 1806: [(set_attr "type" "fp")]) ! 1807: ! 1808: ;; Conversions to and from floating-point. ! 1809: (define_expand "floatsidf2" ! 1810: [(set (match_dup 2) ! 1811: (plus:DI (zero_extend:DI ! 1812: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1813: (match_dup 3))) ! 1814: (match_dup 4))) ! 1815: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 1816: (minus:DF (subreg:DF (match_dup 2) 0) ! 1817: (match_dup 5)))] ! 1818: "" ! 1819: " ! 1820: { ! 1821: #if HOST_BITS_PER_INT != BITS_PER_WORD ! 1822: /* Maybe someone can figure out how to do this in that case. I don't ! 1823: want to right now. */ ! 1824: abort (); ! 1825: #endif ! 1826: ! 1827: operands[2] = gen_reg_rtx (DImode); ! 1828: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); ! 1829: operands[4] = immed_double_const (0, 0x43300000, DImode); ! 1830: operands[5] = force_reg (DFmode, immed_double_const (0x43300000, ! 1831: 0x80000000, DFmode)); ! 1832: }") ! 1833: ! 1834: (define_expand "floatunssidf2" ! 1835: [(set (match_dup 2) ! 1836: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! 1837: (match_dup 3))) ! 1838: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 1839: (minus:DF (subreg:DF (match_dup 2) 0) ! 1840: (match_dup 4)))] ! 1841: "" ! 1842: " ! 1843: { ! 1844: #if HOST_BITS_PER_INT != BITS_PER_WORD ! 1845: /* Maybe someone can figure out how to do this in that case. I don't ! 1846: want to right now. */ ! 1847: abort (); ! 1848: #endif ! 1849: ! 1850: operands[2] = gen_reg_rtx (DImode); ! 1851: operands[3] = immed_double_const (0, 0x43300000, DImode); ! 1852: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode)); ! 1853: }") ! 1854: ! 1855: ;; For the above two cases, we always split. ! 1856: (define_split ! 1857: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 1858: (plus:DI (zero_extend:DI ! 1859: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1860: (match_operand:SI 2 "logical_operand" ""))) ! 1861: (match_operand:DI 3 "immediate_operand" "")))] ! 1862: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD ! 1863: && GET_CODE (operands[3]) == CONST_DOUBLE ! 1864: && CONST_DOUBLE_LOW (operands[3]) == 0" ! 1865: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2))) ! 1866: (set (match_dup 4) (match_dup 5))] ! 1867: " ! 1868: { operands[4] = operand_subword (operands[0], 0, 0, DImode); ! 1869: operands[5] = operand_subword (operands[3], 0, 0, DImode); ! 1870: operands[6] = operand_subword (operands[0], 1, 0, DImode); ! 1871: }") ! 1872: ! 1873: (define_insn "" ! 1874: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 1875: (plus:DI (zero_extend:DI ! 1876: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 1877: (match_operand:SI 2 "logical_operand" "rKJ"))) ! 1878: (match_operand:DI 3 "immediate_operand" "n")))] ! 1879: "HOST_BITS_PER_INT == BITS_PER_WORD ! 1880: && GET_CODE (operands[3]) == CONST_DOUBLE ! 1881: && CONST_DOUBLE_LOW (operands[3]) == 0" ! 1882: "#") ! 1883: ! 1884: (define_split ! 1885: [(set (match_operand:DI 0 "gpc_reg_operand" "=") ! 1886: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! 1887: (match_operand:DI 2 "immediate_operand" "")))] ! 1888: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD ! 1889: && GET_CODE (operands[2]) == CONST_DOUBLE ! 1890: && CONST_DOUBLE_LOW (operands[2]) == 0" ! 1891: [(set (match_dup 3) (match_dup 4)) ! 1892: (set (match_dup 5) (match_dup 1))] ! 1893: " ! 1894: { operands[3] = operand_subword (operands[0], 0, 0, DImode); ! 1895: operands[4] = operand_subword (operands[2], 0, 0, DImode); ! 1896: operands[5] = operand_subword (operands[0], 1, 0, DImode); ! 1897: ! 1898: if (rtx_equal_p (operands[1], operands[5])) ! 1899: { ! 1900: emit_move_insn (operands[3], operands[4]); ! 1901: DONE; ! 1902: } ! 1903: ! 1904: if (rtx_equal_p (operands[1], operands[3])) ! 1905: { ! 1906: rtx temp; ! 1907: ! 1908: temp = operands[3]; operands[3] = operands[5]; operands[5] = temp; ! 1909: temp = operands[4]; operands[4] = operands[1]; operands[1] = temp; ! 1910: } ! 1911: }") ! 1912: ! 1913: (define_insn "" ! 1914: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 1915: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1916: (match_operand:DI 2 "immediate_operand" "n")))] ! 1917: "HOST_BITS_PER_INT == BITS_PER_WORD ! 1918: && GET_CODE (operands[2]) == CONST_DOUBLE ! 1919: && CONST_DOUBLE_LOW (operands[2]) == 0" ! 1920: "#") ! 1921: ! 1922: (define_expand "fix_truncdfsi2" ! 1923: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1924: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] ! 1925: "" ! 1926: " ! 1927: { ! 1928: emit_insn (gen_trunc_call (operands[0], operands[1], ! 1929: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\"))); ! 1930: DONE; ! 1931: }") ! 1932: ! 1933: (define_expand "fixuns_truncdfsi2" ! 1934: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1935: (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] ! 1936: "" ! 1937: " ! 1938: { ! 1939: emit_insn (gen_trunc_call (operands[0], operands[1], ! 1940: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\"))); ! 1941: DONE; ! 1942: }") ! 1943: ! 1944: ! 1945: (define_expand "trunc_call" ! 1946: [(parallel [(set (match_operand:SI 0 "" "") ! 1947: (fix:SI (match_operand:DF 1 "" ""))) ! 1948: (use (match_operand:SI 2 "" ""))])] ! 1949: "" ! 1950: " ! 1951: { ! 1952: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); ! 1953: rtx first = XVECEXP (insns, 0, 0); ! 1954: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); ! 1955: ! 1956: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, ! 1957: REG_NOTES (first)); ! 1958: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); ! 1959: ! 1960: emit_insn (insns); ! 1961: DONE; ! 1962: }") ! 1963: ! 1964: (define_expand "trunc_call_rtl" ! 1965: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) ! 1966: (use (reg:DF 33)) ! 1967: (parallel [(set (reg:SI 3) ! 1968: (call (mem:SI (match_operand 2 "" "")) (const_int 0))) ! 1969: (clobber (scratch:SI))]) ! 1970: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 1971: (reg:SI 3))] ! 1972: "" ! 1973: " ! 1974: { ! 1975: rs6000_trunc_used = 1; ! 1976: }") ! 1977: ! 1978: ;; Define the DImode operations that can be done in a small number ! 1979: ;; of instructions. ! 1980: (define_insn "adddi3" ! 1981: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 1982: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") ! 1983: (match_operand:DI 2 "reg_or_short_operand" "r,I")))] ! 1984: "" ! 1985: "@ ! 1986: a %L0,%L1,%L2\;ae %0,%1,%2 ! 1987: ai %L0,%L1,%2\;a%G2e %0,%1") ! 1988: ! 1989: (define_insn "subdi3" ! 1990: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 1991: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") ! 1992: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] ! 1993: "" ! 1994: "@ ! 1995: sf %L0,%L2,%L1\;sfe %0,%2,%1 ! 1996: sfi %L0,%L2,%1\;sf%G1e %0,%2") ! 1997: ! 1998: (define_insn "negdi2" ! 1999: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2000: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] ! 2001: "" ! 2002: "sfi %L0,%L1,0\;sfze %0,%1") ! 2003: ! 2004: (define_insn "mulsidi3" ! 2005: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2006: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 2007: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) ! 2008: (clobber (match_scratch:SI 3 "=q"))] ! 2009: "" ! 2010: "mul %0,%1,%2\;mfmq %L0") ! 2011: ! 2012: ;; If operands 0 and 2 are in the same register, we have a problem. But ! 2013: ;; operands 0 and 1 (the usual case) can be in the same register. That's ! 2014: ;; why we have the strange constraints below. ! 2015: (define_insn "ashldi3" ! 2016: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") ! 2017: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") ! 2018: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) ! 2019: (clobber (match_scratch:SI 3 "=X,q,q,q"))] ! 2020: "" ! 2021: "@ ! 2022: sli %0,%L1,%h2\;cal %L0,0(0) ! 2023: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ! 2024: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ! 2025: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2") ! 2026: ! 2027: (define_insn "lshrdi3" ! 2028: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") ! 2029: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") ! 2030: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) ! 2031: (clobber (match_scratch:SI 3 "=X,q,q,q"))] ! 2032: "" ! 2033: "@ ! 2034: cal %0,0(0)\;s%A2i %L0,%1,%h2 ! 2035: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 ! 2036: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 ! 2037: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2") ! 2038: ! 2039: ;; Shift by a variable amount is too complex to be worth open-coding. We ! 2040: ;; just handle shifts by constants. ! 2041: ! 2042: (define_expand "ashrdi3" ! 2043: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=") ! 2044: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") ! 2045: (match_operand:SI 2 "general_operand" ""))) ! 2046: (clobber (match_scratch:SI 3 ""))])] ! 2047: "" ! 2048: " ! 2049: { if (GET_CODE (operands[2]) != CONST_INT) ! 2050: FAIL; ! 2051: }") ! 2052: ! 2053: (define_insn "" ! 2054: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 2055: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") ! 2056: (match_operand:SI 2 "const_int_operand" "M,i"))) ! 2057: (clobber (match_scratch:SI 3 "=X,q"))] ! 2058: "" ! 2059: "@ ! 2060: srai %0,%1,31\;srai %L0,%1,%h2 ! 2061: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2") ! 2062: ! 2063: ;; Now define ways of moving data around. ! 2064: ;; ! 2065: ;; For SI, we special-case integers that can't be loaded in one insn. We ! 2066: ;; do the load 16-bits at a time. We could do this by loading from memory, ! 2067: ;; and this is even supposed to be faster, but it is simpler not to get ! 2068: ;; integers in the TOC. ! 2069: (define_expand "movsi" ! 2070: [(set (match_operand:SI 0 "general_operand" "") ! 2071: (match_operand:SI 1 "any_operand" ""))] ! 2072: "" ! 2073: " ! 2074: { ! 2075: if (GET_CODE (operands[0]) != REG) ! 2076: operands[1] = force_reg (SImode, operands[1]); ! 2077: ! 2078: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) ! 2079: { ! 2080: operands[1] = force_const_mem (SImode, operands[1]); ! 2081: if (! memory_address_p (SImode, XEXP (operands[1], 0)) ! 2082: && ! reload_in_progress) ! 2083: operands[1] = change_address (operands[1], SImode, ! 2084: XEXP (operands[1], 0)); ! 2085: } ! 2086: ! 2087: if (GET_CODE (operands[1]) == CONST_INT ! 2088: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 ! 2089: && (INTVAL (operands[1]) & 0xffff) != 0) ! 2090: { ! 2091: emit_move_insn (operands[0], ! 2092: gen_rtx (CONST_INT, VOIDmode, ! 2093: INTVAL (operands[1]) & 0xffff0000)); ! 2094: emit_insn (gen_iorsi3 (operands[0], operands[0], ! 2095: gen_rtx (CONST_INT, VOIDmode, ! 2096: INTVAL (operands[1]) & 0xffff))); ! 2097: DONE; ! 2098: } ! 2099: }") ! 2100: ! 2101: (define_insn "" ! 2102: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h") ! 2103: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))] ! 2104: "gpc_reg_operand (operands[0], SImode) ! 2105: || gpc_reg_operand (operands[1], SImode)" ! 2106: "@ ! 2107: ai %0,%1,0 ! 2108: l%U1%X1 %0,%1 ! 2109: st%U0%X0 %1,%0 ! 2110: cal %0,%1(0) ! 2111: cau %0,0,%u1 ! 2112: mf%1 %0 ! 2113: mt%0 %1 ! 2114: mt%0 %1 ! 2115: cror 0,0,0" ! 2116: [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")]) ! 2117: ! 2118: ;; Split a load of a large constant into the appropriate two-insn ! 2119: ;; sequence. ! 2120: ! 2121: (define_split ! 2122: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 2123: (match_operand:SI 1 "const_int_operand" ""))] ! 2124: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 ! 2125: && (INTVAL (operands[1]) & 0xffff) != 0" ! 2126: [(set (match_dup 0) ! 2127: (match_dup 2)) ! 2128: (set (match_dup 0) ! 2129: (ior:SI (match_dup 0) ! 2130: (match_dup 3)))] ! 2131: " ! 2132: { ! 2133: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 2134: INTVAL (operands[1]) & 0xffff0000); ! 2135: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); ! 2136: }") ! 2137: ! 2138: (define_insn "" ! 2139: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 2140: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 2141: (const_int 0))) ! 2142: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] ! 2143: "" ! 2144: "ai. %0,%1,0" ! 2145: [(set_attr "type" "compare")]) ! 2146: ! 2147: (define_expand "movhi" ! 2148: [(set (match_operand:HI 0 "general_operand" "") ! 2149: (match_operand:HI 1 "any_operand" ""))] ! 2150: "" ! 2151: " ! 2152: { ! 2153: if (GET_CODE (operands[0]) != REG) ! 2154: operands[1] = force_reg (HImode, operands[1]); ! 2155: ! 2156: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) ! 2157: { ! 2158: operands[1] = force_const_mem (HImode, operands[1]); ! 2159: if (! memory_address_p (HImode, XEXP (operands[1], 0)) ! 2160: && ! reload_in_progress) ! 2161: operands[1] = change_address (operands[1], HImode, ! 2162: XEXP (operands[1], 0)); ! 2163: } ! 2164: }") ! 2165: ! 2166: (define_insn "" ! 2167: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") ! 2168: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] ! 2169: "gpc_reg_operand (operands[0], HImode) ! 2170: || gpc_reg_operand (operands[1], HImode)" ! 2171: "@ ! 2172: oril %0,%1,0 ! 2173: lhz%U1%X1 %0,%1 ! 2174: sth%U0%X0 %1,%0 ! 2175: cal %0,%w1(0) ! 2176: mf%1 %0 ! 2177: mt%0 %1 ! 2178: cror 0,0,0" ! 2179: [(set_attr "type" "*,load,*,*,*,*,*")]) ! 2180: ! 2181: (define_expand "movqi" ! 2182: [(set (match_operand:QI 0 "general_operand" "") ! 2183: (match_operand:QI 1 "any_operand" ""))] ! 2184: "" ! 2185: " ! 2186: { ! 2187: if (GET_CODE (operands[0]) != REG) ! 2188: operands[1] = force_reg (QImode, operands[1]); ! 2189: ! 2190: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) ! 2191: { ! 2192: operands[1] = force_const_mem (QImode, operands[1]); ! 2193: if (! memory_address_p (QImode, XEXP (operands[1], 0)) ! 2194: && ! reload_in_progress) ! 2195: operands[1] = change_address (operands[1], QImode, ! 2196: XEXP (operands[1], 0)); ! 2197: } ! 2198: }") ! 2199: ! 2200: (define_insn "" ! 2201: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") ! 2202: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] ! 2203: "gpc_reg_operand (operands[0], QImode) ! 2204: || gpc_reg_operand (operands[1], QImode)" ! 2205: "@ ! 2206: oril %0,%1,0 ! 2207: lbz%U1%X1 %0,%1 ! 2208: stb%U0%X0 %1,%0 ! 2209: cal %0,%1(0) ! 2210: mf%1 %0 ! 2211: mt%0 %1 ! 2212: cror 0,0,0" ! 2213: [(set_attr "type" "*,load,*,*,*,*,*")]) ! 2214: ! 2215: ;; Here is how to move condition codes around. When we store CC data in ! 2216: ;; an integer register or memory, we store just the high-order 4 bits. ! 2217: ;; This lets us not shift in the most common case of CR0. ! 2218: (define_expand "movcc" ! 2219: [(set (match_operand:CC 0 "nonimmediate_operand" "") ! 2220: (match_operand:CC 1 "nonimmediate_operand" ""))] ! 2221: "" ! 2222: "") ! 2223: ! 2224: (define_insn "" ! 2225: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") ! 2226: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] ! 2227: "register_operand (operands[0], CCmode) ! 2228: || register_operand (operands[1], CCmode)" ! 2229: "@ ! 2230: mcrf %0,%1 ! 2231: mtcrf 128,%1 ! 2232: rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31 ! 2233: mfcr %0 ! 2234: mfcr %0\;rlinm %0,%0,%f1,0,3 ! 2235: ai %0,%1,0 ! 2236: l%U1%X1 %0,%1 ! 2237: st%U0%U1 %1,%0" ! 2238: [(set_attr "type" "*,*,*,compare,*,*,load,*")]) ! 2239: ! 2240: ;; For floating-point, we normally deal with the floating-point registers. ! 2241: ;; The sole exception is that parameter passing can produce floating-point ! 2242: ;; values in fixed-point registers. Unless the value is a simple constant ! 2243: ;; or already in memory, we deal with this by allocating memory and copying ! 2244: ;; the value explicitly via that memory location. ! 2245: (define_expand "movsf" ! 2246: [(set (match_operand:SF 0 "nonimmediate_operand" "") ! 2247: (match_operand:SF 1 "any_operand" ""))] ! 2248: "" ! 2249: " ! 2250: { ! 2251: /* If we are called from reload, we might be getting a SUBREG of a hard ! 2252: reg. So expand it. */ ! 2253: if (GET_CODE (operands[0]) == SUBREG ! 2254: && GET_CODE (SUBREG_REG (operands[0])) == REG ! 2255: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) ! 2256: operands[0] = alter_subreg (operands[0]); ! 2257: if (GET_CODE (operands[1]) == SUBREG ! 2258: && GET_CODE (SUBREG_REG (operands[1])) == REG ! 2259: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) ! 2260: operands[1] = alter_subreg (operands[1]); ! 2261: ! 2262: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2263: { ! 2264: rtx stack_slot; ! 2265: ! 2266: /* If this is a store to memory or another integer register do the ! 2267: move directly. Otherwise store to a temporary stack slot and ! 2268: load from there into a floating point register. */ ! 2269: ! 2270: if (GET_CODE (operands[0]) == MEM ! 2271: || (GET_CODE (operands[0]) == REG ! 2272: && (REGNO (operands[0]) < 32 ! 2273: || (reload_in_progress ! 2274: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) ! 2275: { ! 2276: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 2277: operand_subword (operands[1], 0, 0, SFmode)); ! 2278: DONE; ! 2279: } ! 2280: ! 2281: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4)); ! 2282: emit_move_insn (stack_slot, operands[1]); ! 2283: emit_move_insn (operands[0], stack_slot); ! 2284: DONE; ! 2285: } ! 2286: ! 2287: if (GET_CODE (operands[0]) == MEM) ! 2288: operands[1] = force_reg (SFmode, operands[1]); ! 2289: ! 2290: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) ! 2291: { ! 2292: rtx stack_slot; ! 2293: ! 2294: if (GET_CODE (operands[1]) == MEM ! 2295: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) ! 2296: || GET_CODE (operands[1]) == CONST_DOUBLE ! 2297: #endif ! 2298: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2299: || (reload_in_progress && GET_CODE (operands[1]) == REG ! 2300: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) ! 2301: { ! 2302: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 2303: operand_subword (operands[1], 0, 0, SFmode)); ! 2304: DONE; ! 2305: } ! 2306: ! 2307: if (reload_in_progress) ! 2308: stack_slot = gen_rtx (MEM, SFmode, ! 2309: plus_constant (stack_pointer_rtx, 4)); ! 2310: else ! 2311: stack_slot = assign_stack_temp (SFmode, 4, 0); ! 2312: emit_move_insn (stack_slot, operands[1]); ! 2313: emit_move_insn (operands[0], stack_slot); ! 2314: DONE; ! 2315: } ! 2316: ! 2317: if (CONSTANT_P (operands[1])) ! 2318: { ! 2319: operands[1] = force_const_mem (SFmode, operands[1]); ! 2320: if (! memory_address_p (SFmode, XEXP (operands[1], 0)) ! 2321: && ! reload_in_progress) ! 2322: operands[1] = change_address (operands[1], SFmode, ! 2323: XEXP (operands[1], 0)); ! 2324: } ! 2325: }") ! 2326: ! 2327: (define_insn "" ! 2328: [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r") ! 2329: (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))] ! 2330: "REGNO (operands[0]) <= 31" ! 2331: "@ ! 2332: # ! 2333: l%U1%X1 %0,%1" ! 2334: [(set_attr "type" "*,load")]) ! 2335: ! 2336: (define_split ! 2337: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2338: (match_operand:SF 1 "easy_fp_constant" ""))] ! 2339: "reload_completed && REGNO (operands[0]) <= 31" ! 2340: [(set (match_dup 2) (match_dup 3))] ! 2341: " ! 2342: { operands[2] = operand_subword (operands[0], 0, 0, SFmode); ! 2343: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") ! 2344: ! 2345: (define_insn "" ! 2346: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") ! 2347: (match_operand:SF 1 "input_operand" "f,m,f"))] ! 2348: "gpc_reg_operand (operands[0], SFmode) ! 2349: || gpc_reg_operand (operands[1], SFmode)" ! 2350: "@ ! 2351: fmr %0,%1 ! 2352: lfs%U1%X1 %0,%1 ! 2353: frsp %1,%1\;stfs%U0%X0 %1,%0" ! 2354: [(set_attr "type" "fp,load,*")]) ! 2355: ! 2356: (define_expand "movdf" ! 2357: [(set (match_operand:DF 0 "nonimmediate_operand" "") ! 2358: (match_operand:DF 1 "any_operand" ""))] ! 2359: "" ! 2360: " ! 2361: { ! 2362: /* If we are called from reload, we might be getting a SUBREG of a hard ! 2363: reg. So expand it. */ ! 2364: if (GET_CODE (operands[0]) == SUBREG ! 2365: && GET_CODE (SUBREG_REG (operands[0])) == REG ! 2366: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) ! 2367: operands[0] = alter_subreg (operands[0]); ! 2368: if (GET_CODE (operands[1]) == SUBREG ! 2369: && GET_CODE (SUBREG_REG (operands[1])) == REG ! 2370: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) ! 2371: operands[1] = alter_subreg (operands[1]); ! 2372: ! 2373: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2374: { ! 2375: rtx stack_slot; ! 2376: ! 2377: /* If this is a store to memory or another integer register do the ! 2378: move directly. Otherwise store to a temporary stack slot and ! 2379: load from there into a floating point register. */ ! 2380: ! 2381: if (GET_CODE (operands[0]) == MEM ! 2382: || (GET_CODE (operands[0]) == REG ! 2383: && (REGNO (operands[0]) < 32 ! 2384: || (reload_in_progress ! 2385: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) ! 2386: { ! 2387: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), ! 2388: operand_subword (operands[1], 0, 0, DFmode)); ! 2389: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), ! 2390: operand_subword (operands[1], 1, 0, DFmode)); ! 2391: DONE; ! 2392: } ! 2393: ! 2394: stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8)); ! 2395: emit_move_insn (stack_slot, operands[1]); ! 2396: emit_move_insn (operands[0], stack_slot); ! 2397: DONE; ! 2398: } ! 2399: ! 2400: if (GET_CODE (operands[0]) == MEM) ! 2401: { ! 2402: if (GET_CODE (operands[1]) == MEM) ! 2403: { ! 2404: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), ! 2405: operand_subword (operands[1], 0, 0, DFmode)); ! 2406: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), ! 2407: operand_subword (operands[1], 1, 0, DFmode)); ! 2408: DONE; ! 2409: } ! 2410: ! 2411: operands[1] = force_reg (DFmode, operands[1]); ! 2412: } ! 2413: ! 2414: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) ! 2415: { ! 2416: rtx stack_slot; ! 2417: ! 2418: if (GET_CODE (operands[1]) == MEM ! 2419: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) ! 2420: || GET_CODE (operands[1]) == CONST_DOUBLE ! 2421: #endif ! 2422: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2423: || (reload_in_progress && GET_CODE (operands[1]) == REG ! 2424: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) ! 2425: { ! 2426: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), ! 2427: operand_subword (operands[1], 0, 0, DFmode)); ! 2428: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), ! 2429: operand_subword (operands[1], 1, 0, DFmode)); ! 2430: DONE; ! 2431: } ! 2432: ! 2433: if (reload_in_progress) ! 2434: stack_slot = gen_rtx (MEM, DFmode, ! 2435: plus_constant (stack_pointer_rtx, 8)); ! 2436: else ! 2437: stack_slot = assign_stack_temp (DFmode, 8, 0); ! 2438: emit_move_insn (stack_slot, operands[1]); ! 2439: emit_move_insn (operands[0], stack_slot); ! 2440: DONE; ! 2441: } ! 2442: ! 2443: if (CONSTANT_P (operands[1])) ! 2444: { ! 2445: operands[1] = force_const_mem (DFmode, operands[1]); ! 2446: if (! memory_address_p (DFmode, XEXP (operands[1], 0)) ! 2447: && ! reload_in_progress) ! 2448: operands[1] = change_address (operands[1], DFmode, ! 2449: XEXP (operands[1], 0)); ! 2450: } ! 2451: }") ! 2452: ! 2453: (define_insn "" ! 2454: [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r") ! 2455: (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))] ! 2456: "REGNO (operands[0]) <= 31" ! 2457: "@ ! 2458: # ! 2459: l %0,%1\;l %L0,%L1" ! 2460: [(set_attr "type" "*,load")]) ! 2461: ! 2462: (define_split ! 2463: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 2464: (match_operand:DF 1 "easy_fp_constant" ""))] ! 2465: "reload_completed && REGNO (operands[0]) <= 31" ! 2466: [(set (match_dup 2) (match_dup 3)) ! 2467: (set (match_dup 4) (match_dup 5))] ! 2468: " ! 2469: { operands[2] = operand_subword (operands[0], 0, 0, DFmode); ! 2470: operands[3] = operand_subword (operands[1], 0, 0, DFmode); ! 2471: operands[4] = operand_subword (operands[0], 1, 0, DFmode); ! 2472: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") ! 2473: ! 2474: (define_insn "" ! 2475: [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m") ! 2476: (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))] ! 2477: "gpc_reg_operand (operands[0], DFmode) ! 2478: || gpc_reg_operand (operands[1], DFmode)" ! 2479: "@ ! 2480: fmr %0,%1 ! 2481: lfd%U1%X1 %0,%1 ! 2482: stfd%U0%X0 %1,%0" ! 2483: [(set_attr "type" "fp,load,*")]) ! 2484: ! 2485: ;; Next come the multi-word integer load and store and the load and store ! 2486: ;; multiple insns. ! 2487: (define_expand "movdi" ! 2488: [(set (match_operand:DI 0 "general_operand" "") ! 2489: (match_operand:DI 1 "general_operand" ""))] ! 2490: "" ! 2491: " ! 2492: { ! 2493: if (GET_CODE (operands[1]) == CONST_DOUBLE ! 2494: || GET_CODE (operands[1]) == CONST_INT) ! 2495: { ! 2496: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), ! 2497: operand_subword (operands[1], 0, 0, DImode)); ! 2498: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), ! 2499: operand_subword (operands[1], 1, 0, DImode)); ! 2500: DONE; ! 2501: } ! 2502: ! 2503: if (GET_CODE (operands[0]) == MEM) ! 2504: operands[1] = force_reg (DImode, operands[1]); ! 2505: }") ! 2506: ! 2507: (define_insn "" ! 2508: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") ! 2509: (match_operand:DI 1 "input_operand" "r,m,r"))] ! 2510: "gpc_reg_operand (operands[0], DImode) ! 2511: || gpc_reg_operand (operands[1], DImode)" ! 2512: "* ! 2513: { ! 2514: switch (which_alternative) ! 2515: { ! 2516: case 0: ! 2517: /* We normally copy the low-numbered register first. However, if ! 2518: the first register operand 0 is the same as the second register of ! 2519: operand 1, we must copy in the opposite order. */ ! 2520: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 2521: return \"oril %L0,%L1,0\;oril %0,%1,0\"; ! 2522: else ! 2523: return \"oril %0,%1,0\;oril %L0,%L1,0\"; ! 2524: case 1: ! 2525: /* If the low-address word is used in the address, we must load it ! 2526: last. Otherwise, load it first. Note that we cannot have ! 2527: auto-increment in that case since the address register is known to be ! 2528: dead. */ ! 2529: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 2530: operands [1], 0)) ! 2531: return \"l %L0,%L1\;l %0,%1\"; ! 2532: else ! 2533: return \"l%U1 %0,%1\;l %L0,%L1\"; ! 2534: case 2: ! 2535: return \"st%U0 %1,%0\;st %L1,%L0\"; ! 2536: } ! 2537: }" ! 2538: [(set_attr "type" "*,load,*")]) ! 2539: ! 2540: ;; TImode is similar, except that we usually want to compute the address into ! 2541: ;; a register and use lsi/stsi (the exception is during reload). MQ is also ! 2542: ;; clobbered in stsi, so we need a SCRATCH for it. ! 2543: (define_expand "movti" ! 2544: [(parallel [(set (match_operand:TI 0 "general_operand" "") ! 2545: (match_operand:TI 1 "general_operand" "")) ! 2546: (clobber (scratch:SI))])] ! 2547: "" ! 2548: " ! 2549: { ! 2550: if (GET_CODE (operands[0]) == MEM) ! 2551: operands[1] = force_reg (TImode, operands[1]); ! 2552: ! 2553: if (GET_CODE (operands[0]) == MEM ! 2554: && GET_CODE (XEXP (operands[0], 0)) != REG ! 2555: && ! reload_in_progress) ! 2556: operands[0] = change_address (operands[0], TImode, ! 2557: copy_addr_to_reg (XEXP (operands[0], 0))); ! 2558: ! 2559: if (GET_CODE (operands[1]) == MEM ! 2560: && GET_CODE (XEXP (operands[1], 0)) != REG ! 2561: && ! reload_in_progress) ! 2562: operands[1] = change_address (operands[1], TImode, ! 2563: copy_addr_to_reg (XEXP (operands[1], 0))); ! 2564: }") ! 2565: ! 2566: ;; We say that MQ is clobbered in the last alternative because the first ! 2567: ;; alternative would never get used otherwise since it would need a reload ! 2568: ;; while the 2nd alternative would not. We put memory cases first so they ! 2569: ;; are preferred. Otherwise, we'd try to reload the output instead of ! 2570: ;; giving the SCRATCH mq. ! 2571: (define_insn "" ! 2572: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") ! 2573: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) ! 2574: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] ! 2575: "gpc_reg_operand (operands[0], TImode) ! 2576: || gpc_reg_operand (operands[1], TImode)" ! 2577: "* ! 2578: { ! 2579: switch (which_alternative) ! 2580: { ! 2581: case 0: ! 2582: return \"stsi %1,%P0,16\"; ! 2583: ! 2584: case 1: ! 2585: return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\"; ! 2586: ! 2587: case 2: ! 2588: /* Normally copy registers with lowest numbered register copied first. ! 2589: But copy in the other order if the first register of the output ! 2590: is the second, third, or fourth register in the input. */ ! 2591: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 ! 2592: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) ! 2593: return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\"; ! 2594: else ! 2595: return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\"; ! 2596: case 3: ! 2597: /* If the address is not used in the output, we can use lsi. Otherwise, ! 2598: fall through to generating four loads. */ ! 2599: if (! reg_overlap_mentioned_p (operands[0], operands[1])) ! 2600: return \"lsi %0,%P1,16\"; ! 2601: /* ... fall through ... */ ! 2602: case 4: ! 2603: /* If the address register is the same as the register for the lowest- ! 2604: addressed word, load it last. Similarly for the next two words. ! 2605: Otherwise load lowest address to highest. */ ! 2606: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 2607: operands[1], 0)) ! 2608: return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\"; ! 2609: else if (refers_to_regno_p (REGNO (operands[0]) + 1, ! 2610: REGNO (operands[0]) + 2, operands[1], 0)) ! 2611: return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\"; ! 2612: else if (refers_to_regno_p (REGNO (operands[0]) + 2, ! 2613: REGNO (operands[0]) + 3, operands[1], 0)) ! 2614: return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\"; ! 2615: else ! 2616: return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\"; ! 2617: } ! 2618: }" ! 2619: [(set_attr "type" "*,load,load,*,*")]) ! 2620: ! 2621: (define_expand "load_multiple" ! 2622: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 2623: (match_operand:SI 1 "" "")) ! 2624: (use (match_operand:SI 2 "" ""))])] ! 2625: "" ! 2626: " ! 2627: { ! 2628: int regno; ! 2629: int count; ! 2630: rtx from; ! 2631: int i; ! 2632: ! 2633: /* Support only loading a constant number of fixed-point registers from ! 2634: memory and only bother with this if more than two; the machine ! 2635: doesn't support more than eight. */ ! 2636: if (GET_CODE (operands[2]) != CONST_INT ! 2637: || INTVAL (operands[2]) <= 2 ! 2638: || INTVAL (operands[2]) > 8 ! 2639: || GET_CODE (operands[1]) != MEM ! 2640: || GET_CODE (operands[0]) != REG ! 2641: || REGNO (operands[0]) >= 32) ! 2642: FAIL; ! 2643: ! 2644: count = INTVAL (operands[2]); ! 2645: regno = REGNO (operands[0]); ! 2646: ! 2647: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); ! 2648: from = force_reg (SImode, XEXP (operands[1], 0)); ! 2649: ! 2650: for (i = 0; i < count; i++) ! 2651: XVECEXP (operands[3], 0, i) ! 2652: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), ! 2653: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); ! 2654: }") ! 2655: ! 2656: (define_insn "" ! 2657: [(match_parallel 0 "load_multiple_operation" ! 2658: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") ! 2659: (match_operand:SI 2 "indirect_operand" "Q"))])] ! 2660: "" ! 2661: "* ! 2662: { ! 2663: /* We have to handle the case where the pseudo used to contain the address ! 2664: is assigned to one of the output registers. In that case, do the ! 2665: lsi, but then load the correct value. This is a bit of a mess, but is ! 2666: the best we can do. */ ! 2667: static char result[100]; ! 2668: char newload[40]; ! 2669: int i; ! 2670: ! 2671: strcpy (result, \"lsi %1,%P2,%N0\"); ! 2672: for (i = 0; i < XVECLEN (operands[0], 0); i++) ! 2673: if (refers_to_regno_p (REGNO (operands[1]) + i, ! 2674: REGNO (operands[1]) + i + 1, operands[2], 0)) ! 2675: { ! 2676: sprintf (newload, \"\;l %d,%d(%d)\", ! 2677: REGNO (operands[1]) + i, ! 2678: i * 4, REGNO (XEXP (operands[2], 0))); ! 2679: strcat (result, newload); ! 2680: } ! 2681: ! 2682: return result; ! 2683: }" ! 2684: [(set_attr "type" "load")]) ! 2685: ! 2686: (define_expand "store_multiple" ! 2687: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 2688: (match_operand:SI 1 "" "")) ! 2689: (clobber (scratch:SI)) ! 2690: (use (match_operand:SI 2 "" ""))])] ! 2691: "" ! 2692: " ! 2693: { ! 2694: int regno; ! 2695: int count; ! 2696: rtx to; ! 2697: int i; ! 2698: ! 2699: /* Support only storing a constant number of fixed-point registers to ! 2700: memory and only bother with this if more than two; the machine ! 2701: doesn't support more than eight. */ ! 2702: if (GET_CODE (operands[2]) != CONST_INT ! 2703: || INTVAL (operands[2]) <= 2 ! 2704: || INTVAL (operands[2]) > 8 ! 2705: || GET_CODE (operands[0]) != MEM ! 2706: || GET_CODE (operands[1]) != REG ! 2707: || REGNO (operands[1]) >= 32) ! 2708: FAIL; ! 2709: ! 2710: count = INTVAL (operands[2]); ! 2711: regno = REGNO (operands[1]); ! 2712: ! 2713: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); ! 2714: to = force_reg (SImode, XEXP (operands[0], 0)); ! 2715: ! 2716: XVECEXP (operands[3], 0, 0) ! 2717: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); ! 2718: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, ! 2719: gen_rtx (SCRATCH, SImode)); ! 2720: ! 2721: for (i = 1; i < count; i++) ! 2722: XVECEXP (operands[3], 0, i + 1) ! 2723: = gen_rtx (SET, VOIDmode, ! 2724: gen_rtx (MEM, SImode, plus_constant (to, i * 4)), ! 2725: gen_rtx (REG, SImode, regno + i)); ! 2726: }") ! 2727: ! 2728: (define_insn "" ! 2729: [(match_parallel 0 "store_multiple_operation" ! 2730: [(set (match_operand:SI 1 "indirect_operand" "=Q") ! 2731: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 2732: (clobber (match_scratch:SI 3 "=q"))])] ! 2733: "" ! 2734: "stsi %2,%P1,%O0") ! 2735: ! 2736: ;; Define insns that do load or store with update. Some of these we can ! 2737: ;; get by using pre-decrement or pre-increment, but the hardware can also ! 2738: ;; do cases where the increment is not the size of the object. ! 2739: ;; ! 2740: ;; In all these cases, we use operands 0 and 1 for the register being ! 2741: ;; incremented because those are the operands that local-alloc will ! 2742: ;; tie and these are the pair most likely to be tieable (and the ones ! 2743: ;; that will benefit the most). ! 2744: ! 2745: (define_insn "" ! 2746: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 2747: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2748: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 2749: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2750: (plus:SI (match_dup 1) (match_dup 2)))] ! 2751: "" ! 2752: "@ ! 2753: lux %3,%0,%2 ! 2754: lu %3,%2(%0)" ! 2755: [(set_attr "type" "load,load")]) ! 2756: ! 2757: (define_insn "" ! 2758: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2759: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 2760: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 2761: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2762: (plus:SI (match_dup 1) (match_dup 2)))] ! 2763: "" ! 2764: "@ ! 2765: stux %3,%0,%2 ! 2766: stu %3,%2(%0)") ! 2767: ! 2768: (define_insn "" ! 2769: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") ! 2770: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2771: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 2772: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2773: (plus:SI (match_dup 1) (match_dup 2)))] ! 2774: "" ! 2775: "@ ! 2776: lhzux %3,%0,%2 ! 2777: lhzu %3,%2(%0)" ! 2778: [(set_attr "type" "load,load")]) ! 2779: ! 2780: (define_insn "" ! 2781: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 2782: (zero_extend:SI ! 2783: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2784: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 2785: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2786: (plus:SI (match_dup 1) (match_dup 2)))] ! 2787: "" ! 2788: "@ ! 2789: lhzux %3,%0,%2 ! 2790: lhzu %3,%2(%0)" ! 2791: [(set_attr "type" "load,load")]) ! 2792: ! 2793: (define_insn "" ! 2794: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 2795: (sign_extend:SI ! 2796: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2797: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 2798: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2799: (plus:SI (match_dup 1) (match_dup 2)))] ! 2800: "" ! 2801: "@ ! 2802: lhaux %3,%0,%2 ! 2803: lhau %3,%2(%0)" ! 2804: [(set_attr "type" "load,load")]) ! 2805: ! 2806: (define_insn "" ! 2807: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2808: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 2809: (match_operand:HI 3 "gpc_reg_operand" "r,r")) ! 2810: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2811: (plus:SI (match_dup 1) (match_dup 2)))] ! 2812: "" ! 2813: "@ ! 2814: sthux %3,%0,%2 ! 2815: sthu %3,%2(%0)" ! 2816: [(set_attr "type" "load,load")]) ! 2817: ! 2818: (define_insn "" ! 2819: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") ! 2820: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2821: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 2822: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2823: (plus:SI (match_dup 1) (match_dup 2)))] ! 2824: "" ! 2825: "@ ! 2826: lbzux %3,%0,%2 ! 2827: lbzu %3,%2(%0)" ! 2828: [(set_attr "type" "load,load")]) ! 2829: ! 2830: (define_insn "" ! 2831: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 2832: (zero_extend:SI ! 2833: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2834: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 2835: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2836: (plus:SI (match_dup 1) (match_dup 2)))] ! 2837: "" ! 2838: "@ ! 2839: lbzux %3,%0,%2 ! 2840: lbzu %3,%2(%0)" ! 2841: [(set_attr "type" "load,load")]) ! 2842: ! 2843: (define_insn "" ! 2844: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2845: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 2846: (match_operand:QI 3 "gpc_reg_operand" "r,r")) ! 2847: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2848: (plus:SI (match_dup 1) (match_dup 2)))] ! 2849: "" ! 2850: "@ ! 2851: stbux %3,%0,%2 ! 2852: stbu %3,%2(%0)") ! 2853: ! 2854: (define_insn "" ! 2855: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") ! 2856: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2857: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 2858: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2859: (plus:SI (match_dup 1) (match_dup 2)))] ! 2860: "" ! 2861: "@ ! 2862: lfsux %3,%0,%2 ! 2863: lfsu %3,%2(%0)" ! 2864: [(set_attr "type" "load,load")]) ! 2865: ! 2866: (define_insn "" ! 2867: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2868: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 2869: (match_operand:SF 3 "gpc_reg_operand" "f,f")) ! 2870: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2871: (plus:SI (match_dup 1) (match_dup 2)))] ! 2872: "" ! 2873: "@ ! 2874: frsp %3,%3\;stfsux %3,%0,%2 ! 2875: frsp %3,%3\;stfsu %3,%2(%0)") ! 2876: ! 2877: (define_insn "" ! 2878: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") ! 2879: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2880: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 2881: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2882: (plus:SI (match_dup 1) (match_dup 2)))] ! 2883: "" ! 2884: "@ ! 2885: lfdux %3,%0,%2 ! 2886: lfdu %3,%2(%0)" ! 2887: [(set_attr "type" "load,load")]) ! 2888: ! 2889: (define_insn "" ! 2890: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 2891: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 2892: (match_operand:DF 3 "gpc_reg_operand" "f,f")) ! 2893: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 2894: (plus:SI (match_dup 1) (match_dup 2)))] ! 2895: "" ! 2896: "@ ! 2897: stfdux %3,%0,%2 ! 2898: stfdu %3,%2(%0)") ! 2899: ! 2900: ;; Next come insns related to the calling sequence. ! 2901: ;; ! 2902: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). ! 2903: ;; We move the back-chain and decrement the stack pointer. ! 2904: ! 2905: (define_expand "allocate_stack" ! 2906: [(set (reg:SI 1) ! 2907: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] ! 2908: "" ! 2909: " ! 2910: { rtx chain = gen_reg_rtx (SImode); ! 2911: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); ! 2912: ! 2913: emit_move_insn (chain, stack_bot); ! 2914: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); ! 2915: emit_move_insn (stack_bot, chain); ! 2916: DONE; ! 2917: }") ! 2918: ! 2919: ;; These patterns say how to save and restore the stack pointer. We need not ! 2920: ;; save the stack pointer at function level since we are careful to ! 2921: ;; preserve the backchain. At block level, we have to restore the backchain ! 2922: ;; when we restore the stack pointer. ! 2923: ;; ! 2924: ;; For nonlocal gotos, we must save both the stack pointer and its ! 2925: ;; backchain and restore both. Note that in the nonlocal case, the ! 2926: ;; save area is a memory location. ! 2927: ! 2928: (define_expand "save_stack_function" ! 2929: [(use (const_int 0))] ! 2930: "" ! 2931: "") ! 2932: ! 2933: (define_expand "restore_stack_function" ! 2934: [(use (const_int 0))] ! 2935: "" ! 2936: "") ! 2937: ! 2938: (define_expand "restore_stack_block" ! 2939: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) ! 2940: (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) ! 2941: (set (mem:SI (match_dup 0)) (match_dup 2))] ! 2942: "" ! 2943: " ! 2944: { operands[2] = gen_reg_rtx (SImode); }") ! 2945: ! 2946: (define_expand "save_stack_nonlocal" ! 2947: [(match_operand:DI 0 "memory_operand" "") ! 2948: (match_operand:SI 1 "register_operand" "")] ! 2949: "" ! 2950: " ! 2951: { ! 2952: rtx temp = gen_reg_rtx (SImode); ! 2953: ! 2954: /* Copy the backchain to the first word, sp to the second. */ ! 2955: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); ! 2956: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); ! 2957: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); ! 2958: DONE; ! 2959: }") ! 2960: ! 2961: (define_expand "restore_stack_nonlocal" ! 2962: [(match_operand:SI 0 "register_operand" "") ! 2963: (match_operand:DI 1 "memory_operand" "")] ! 2964: "" ! 2965: " ! 2966: { ! 2967: rtx temp = gen_reg_rtx (SImode); ! 2968: ! 2969: /* Restore the backchain from the first word, sp from the second. */ ! 2970: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); ! 2971: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); ! 2972: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); ! 2973: DONE; ! 2974: }") ! 2975: ! 2976: ;; A function pointer is a pointer to a data area whose first word contains ! 2977: ;; the actual address of the function, whose second word contains a pointer ! 2978: ;; to its TOC, and whose third word contains a value to place in the static ! 2979: ;; chain register (r11). Note that if we load the static chain, our ! 2980: ;; "trampoline" need not have any executable code. ! 2981: ;; ! 2982: ;; operands[0] is an SImode pseudo in which we place the address of the ! 2983: ;; function. ! 2984: ;; operands[1] is the address of data area of the function to call ! 2985: ! 2986: (define_expand "call_via_ptr" ! 2987: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 2988: (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) ! 2989: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) ! 2990: (reg:SI 2)) ! 2991: (set (reg:SI 2) ! 2992: (mem:SI (plus:SI (match_dup 1) ! 2993: (const_int 4)))) ! 2994: (set (reg:SI 11) ! 2995: (mem:SI (plus:SI (match_dup 1) ! 2996: (const_int 8)))) ! 2997: (use (reg:SI 2)) ! 2998: (use (reg:SI 11))] ! 2999: "" ! 3000: "") ! 3001: ! 3002: (define_expand "call" ! 3003: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) ! 3004: (match_operand 1 "" "")) ! 3005: (clobber (scratch:SI))])] ! 3006: "" ! 3007: " ! 3008: { ! 3009: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) ! 3010: abort (); ! 3011: ! 3012: operands[0] = XEXP (operands[0], 0); ! 3013: if (GET_CODE (operands[0]) != SYMBOL_REF) ! 3014: { ! 3015: rtx temp = gen_reg_rtx (SImode); ! 3016: ! 3017: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); ! 3018: operands[0] = temp; ! 3019: } ! 3020: }") ! 3021: ! 3022: (define_expand "call_value" ! 3023: [(parallel [(set (match_operand 0 "" "") ! 3024: (call (mem:SI (match_operand:SI 1 "address_operand" "")) ! 3025: (match_operand 2 "" ""))) ! 3026: (clobber (scratch:SI))])] ! 3027: "" ! 3028: " ! 3029: { ! 3030: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) ! 3031: abort (); ! 3032: ! 3033: operands[1] = XEXP (operands[1], 0); ! 3034: if (GET_CODE (operands[1]) != SYMBOL_REF) ! 3035: { ! 3036: rtx temp = gen_reg_rtx (SImode); ! 3037: ! 3038: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); ! 3039: operands[1] = temp; ! 3040: } ! 3041: }") ! 3042: ! 3043: (define_insn "" ! 3044: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) ! 3045: (match_operand 1 "" "fg,fg")) ! 3046: (clobber (match_scratch:SI 2 "=l,l"))] ! 3047: "" ! 3048: "@ ! 3049: brl\;l 2,20(1) ! 3050: bl %z0\;cror 15,15,15") ! 3051: ! 3052: (define_insn "" ! 3053: [(set (match_operand 0 "" "=fg,fg") ! 3054: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) ! 3055: (match_operand 2 "" "fg,fg"))) ! 3056: (clobber (match_scratch:SI 3 "=l,l"))] ! 3057: "" ! 3058: "@ ! 3059: brl\;l 2,20(1) ! 3060: bl %z1\;cror 15,15,15") ! 3061: ! 3062: ;; Call subroutine returning any type. ! 3063: ! 3064: (define_expand "untyped_call" ! 3065: [(parallel [(call (match_operand 0 "" "") ! 3066: (const_int 0)) ! 3067: (match_operand 1 "" "") ! 3068: (match_operand 2 "" "")])] ! 3069: "" ! 3070: " ! 3071: { ! 3072: int i; ! 3073: ! 3074: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); ! 3075: ! 3076: for (i = 0; i < XVECLEN (operands[2], 0); i++) ! 3077: { ! 3078: rtx set = XVECEXP (operands[2], 0, i); ! 3079: emit_move_insn (SET_DEST (set), SET_SRC (set)); ! 3080: } ! 3081: ! 3082: /* The optimizer does not know that the call sets the function value ! 3083: registers we stored in the result block. We avoid problems by ! 3084: claiming that all hard registers are used and clobbered at this ! 3085: point. */ ! 3086: emit_insn (gen_blockage ()); ! 3087: ! 3088: DONE; ! 3089: }") ! 3090: ! 3091: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ! 3092: ;; all of memory. This blocks insns from being moved across this point. ! 3093: ! 3094: (define_insn "blockage" ! 3095: [(unspec_volatile [(const_int 0)] 0)] ! 3096: "" ! 3097: "") ! 3098: ! 3099: ;; Compare insns are next. Note that the RS/6000 has two types of compares, ! 3100: ;; signed & unsigned, and one type of branch. ! 3101: ;; ! 3102: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc ! 3103: ;; insns, and branches. We store the operands of compares until we see ! 3104: ;; how it is used. ! 3105: (define_expand "cmpsi" ! 3106: [(set (cc0) ! 3107: (compare (match_operand:SI 0 "gpc_reg_operand" "") ! 3108: (match_operand:SI 1 "reg_or_short_operand" "")))] ! 3109: "" ! 3110: " ! 3111: { ! 3112: /* Take care of the possibility that operands[1] might be negative but ! 3113: this might be a logical operation. That insn doesn't exist. */ ! 3114: if (GET_CODE (operands[1]) == CONST_INT ! 3115: && INTVAL (operands[1]) < 0) ! 3116: operands[1] = force_reg (SImode, operands[1]); ! 3117: ! 3118: rs6000_compare_op0 = operands[0]; ! 3119: rs6000_compare_op1 = operands[1]; ! 3120: rs6000_compare_fp_p = 0; ! 3121: DONE; ! 3122: }") ! 3123: ! 3124: (define_expand "cmpsf" ! 3125: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") ! 3126: (match_operand:SF 1 "gpc_reg_operand" "")))] ! 3127: "" ! 3128: " ! 3129: { ! 3130: rs6000_compare_op0 = operands[0]; ! 3131: rs6000_compare_op1 = operands[1]; ! 3132: rs6000_compare_fp_p = 1; ! 3133: DONE; ! 3134: }") ! 3135: ! 3136: (define_expand "cmpdf" ! 3137: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") ! 3138: (match_operand:DF 1 "gpc_reg_operand" "")))] ! 3139: "" ! 3140: " ! 3141: { ! 3142: rs6000_compare_op0 = operands[0]; ! 3143: rs6000_compare_op1 = operands[1]; ! 3144: rs6000_compare_fp_p = 1; ! 3145: DONE; ! 3146: }") ! 3147: ! 3148: (define_expand "beq" ! 3149: [(set (match_dup 2) (match_dup 1)) ! 3150: (set (pc) ! 3151: (if_then_else (eq (match_dup 2) ! 3152: (const_int 0)) ! 3153: (label_ref (match_operand 0 "" "")) ! 3154: (pc)))] ! 3155: "" ! 3156: " ! 3157: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3158: operands[1] = gen_rtx (COMPARE, mode, ! 3159: rs6000_compare_op0, rs6000_compare_op1); ! 3160: operands[2] = gen_reg_rtx (mode); ! 3161: }") ! 3162: ! 3163: (define_expand "bne" ! 3164: [(set (match_dup 2) (match_dup 1)) ! 3165: (set (pc) ! 3166: (if_then_else (ne (match_dup 2) ! 3167: (const_int 0)) ! 3168: (label_ref (match_operand 0 "" "")) ! 3169: (pc)))] ! 3170: "" ! 3171: " ! 3172: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3173: operands[1] = gen_rtx (COMPARE, mode, ! 3174: rs6000_compare_op0, rs6000_compare_op1); ! 3175: operands[2] = gen_reg_rtx (mode); ! 3176: }") ! 3177: ! 3178: (define_expand "blt" ! 3179: [(set (match_dup 2) (match_dup 1)) ! 3180: (set (pc) ! 3181: (if_then_else (lt (match_dup 2) ! 3182: (const_int 0)) ! 3183: (label_ref (match_operand 0 "" "")) ! 3184: (pc)))] ! 3185: "" ! 3186: " ! 3187: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3188: operands[1] = gen_rtx (COMPARE, mode, ! 3189: rs6000_compare_op0, rs6000_compare_op1); ! 3190: operands[2] = gen_reg_rtx (mode); ! 3191: }") ! 3192: ! 3193: (define_expand "bgt" ! 3194: [(set (match_dup 2) (match_dup 1)) ! 3195: (set (pc) ! 3196: (if_then_else (gt (match_dup 2) ! 3197: (const_int 0)) ! 3198: (label_ref (match_operand 0 "" "")) ! 3199: (pc)))] ! 3200: "" ! 3201: " ! 3202: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3203: operands[1] = gen_rtx (COMPARE, mode, ! 3204: rs6000_compare_op0, rs6000_compare_op1); ! 3205: operands[2] = gen_reg_rtx (mode); ! 3206: }") ! 3207: ! 3208: (define_expand "ble" ! 3209: [(set (match_dup 2) (match_dup 1)) ! 3210: (set (pc) ! 3211: (if_then_else (le (match_dup 2) ! 3212: (const_int 0)) ! 3213: (label_ref (match_operand 0 "" "")) ! 3214: (pc)))] ! 3215: "" ! 3216: " ! 3217: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3218: operands[1] = gen_rtx (COMPARE, mode, ! 3219: rs6000_compare_op0, rs6000_compare_op1); ! 3220: operands[2] = gen_reg_rtx (mode); ! 3221: }") ! 3222: ! 3223: (define_expand "bge" ! 3224: [(set (match_dup 2) (match_dup 1)) ! 3225: (set (pc) ! 3226: (if_then_else (ge (match_dup 2) ! 3227: (const_int 0)) ! 3228: (label_ref (match_operand 0 "" "")) ! 3229: (pc)))] ! 3230: "" ! 3231: " ! 3232: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3233: operands[1] = gen_rtx (COMPARE, mode, ! 3234: rs6000_compare_op0, rs6000_compare_op1); ! 3235: operands[2] = gen_reg_rtx (mode); ! 3236: }") ! 3237: ! 3238: (define_expand "bgtu" ! 3239: [(set (match_dup 2) (match_dup 1)) ! 3240: (set (pc) ! 3241: (if_then_else (gtu (match_dup 2) ! 3242: (const_int 0)) ! 3243: (label_ref (match_operand 0 "" "")) ! 3244: (pc)))] ! 3245: "" ! 3246: " ! 3247: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3248: rs6000_compare_op0, rs6000_compare_op1); ! 3249: operands[2] = gen_reg_rtx (CCUNSmode); ! 3250: }") ! 3251: ! 3252: (define_expand "bltu" ! 3253: [(set (match_dup 2) (match_dup 1)) ! 3254: (set (pc) ! 3255: (if_then_else (ltu (match_dup 2) ! 3256: (const_int 0)) ! 3257: (label_ref (match_operand 0 "" "")) ! 3258: (pc)))] ! 3259: "" ! 3260: " ! 3261: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3262: rs6000_compare_op0, rs6000_compare_op1); ! 3263: operands[2] = gen_reg_rtx (CCUNSmode); ! 3264: }") ! 3265: ! 3266: (define_expand "bgeu" ! 3267: [(set (match_dup 2) (match_dup 1)) ! 3268: (set (pc) ! 3269: (if_then_else (geu (match_dup 2) ! 3270: (const_int 0)) ! 3271: (label_ref (match_operand 0 "" "")) ! 3272: (pc)))] ! 3273: "" ! 3274: " ! 3275: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3276: rs6000_compare_op0, rs6000_compare_op1); ! 3277: operands[2] = gen_reg_rtx (CCUNSmode); ! 3278: }") ! 3279: ! 3280: (define_expand "bleu" ! 3281: [(set (match_dup 2) (match_dup 1)) ! 3282: (set (pc) ! 3283: (if_then_else (leu (match_dup 2) ! 3284: (const_int 0)) ! 3285: (label_ref (match_operand 0 "" "")) ! 3286: (pc)))] ! 3287: "" ! 3288: " ! 3289: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3290: rs6000_compare_op0, rs6000_compare_op1); ! 3291: operands[2] = gen_reg_rtx (CCUNSmode); ! 3292: }") ! 3293: ! 3294: ;; For SNE, we would prefer that the xor/abs sequence be used for integers. ! 3295: ;; For SEQ, likewise, except that comparisons with zero should be done ! 3296: ;; with an scc insns. However, due to the order that combine see the ! 3297: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in ! 3298: ;; the cases we don't want to handle. ! 3299: (define_expand "seq" ! 3300: [(set (match_dup 2) (match_dup 1)) ! 3301: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3302: (eq:SI (match_dup 2) (const_int 0)))] ! 3303: "" ! 3304: " ! 3305: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3306: operands[1] = gen_rtx (COMPARE, mode, ! 3307: rs6000_compare_op0, rs6000_compare_op1); ! 3308: operands[2] = gen_reg_rtx (mode); ! 3309: }") ! 3310: ! 3311: (define_expand "sne" ! 3312: [(set (match_dup 2) (match_dup 1)) ! 3313: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3314: (ne:SI (match_dup 2) (const_int 0)))] ! 3315: "" ! 3316: " ! 3317: { if (! rs6000_compare_fp_p) ! 3318: FAIL; ! 3319: ! 3320: operands[1] = gen_rtx (COMPARE, CCFPmode, ! 3321: rs6000_compare_op0, rs6000_compare_op1); ! 3322: operands[2] = gen_reg_rtx (CCFPmode); ! 3323: }") ! 3324: ! 3325: ;; A > 0 is best done using the portable sequence, so fail in that case. ! 3326: (define_expand "sgt" ! 3327: [(set (match_dup 2) (match_dup 1)) ! 3328: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3329: (gt:SI (match_dup 2) (const_int 0)))] ! 3330: "" ! 3331: " ! 3332: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3333: ! 3334: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 3335: FAIL; ! 3336: ! 3337: operands[1] = gen_rtx (COMPARE, mode, ! 3338: rs6000_compare_op0, rs6000_compare_op1); ! 3339: operands[2] = gen_reg_rtx (mode); ! 3340: }") ! 3341: ! 3342: ;; A < 0 is best done in the portable way for A an integer. ! 3343: (define_expand "slt" ! 3344: [(set (match_dup 2) (match_dup 1)) ! 3345: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3346: (lt:SI (match_dup 2) (const_int 0)))] ! 3347: "" ! 3348: " ! 3349: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3350: ! 3351: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 3352: FAIL; ! 3353: ! 3354: operands[1] = gen_rtx (COMPARE, mode, ! 3355: rs6000_compare_op0, rs6000_compare_op1); ! 3356: operands[2] = gen_reg_rtx (mode); ! 3357: }") ! 3358: ! 3359: (define_expand "sge" ! 3360: [(set (match_dup 2) (match_dup 1)) ! 3361: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3362: (ge:SI (match_dup 2) (const_int 0)))] ! 3363: "" ! 3364: " ! 3365: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3366: operands[1] = gen_rtx (COMPARE, mode, ! 3367: rs6000_compare_op0, rs6000_compare_op1); ! 3368: operands[2] = gen_reg_rtx (mode); ! 3369: }") ! 3370: ! 3371: ;; A <= 0 is best done the portable way for A an integer. ! 3372: (define_expand "sle" ! 3373: [(set (match_dup 2) (match_dup 1)) ! 3374: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3375: (le:SI (match_dup 2) (const_int 0)))] ! 3376: "" ! 3377: " ! 3378: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3379: ! 3380: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 3381: FAIL; ! 3382: ! 3383: operands[1] = gen_rtx (COMPARE, mode, ! 3384: rs6000_compare_op0, rs6000_compare_op1); ! 3385: operands[2] = gen_reg_rtx (mode); ! 3386: }") ! 3387: ! 3388: (define_expand "sgtu" ! 3389: [(set (match_dup 2) (match_dup 1)) ! 3390: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3391: (gtu:SI (match_dup 2) (const_int 0)))] ! 3392: "" ! 3393: " ! 3394: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3395: rs6000_compare_op0, rs6000_compare_op1); ! 3396: operands[2] = gen_reg_rtx (CCUNSmode); ! 3397: }") ! 3398: ! 3399: (define_expand "sltu" ! 3400: [(set (match_dup 2) (match_dup 1)) ! 3401: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3402: (ltu:SI (match_dup 2) (const_int 0)))] ! 3403: "" ! 3404: " ! 3405: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3406: rs6000_compare_op0, rs6000_compare_op1); ! 3407: operands[2] = gen_reg_rtx (CCUNSmode); ! 3408: }") ! 3409: ! 3410: (define_expand "sgeu" ! 3411: [(set (match_dup 2) (match_dup 1)) ! 3412: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3413: (geu:SI (match_dup 2) (const_int 0)))] ! 3414: "" ! 3415: " ! 3416: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3417: rs6000_compare_op0, rs6000_compare_op1); ! 3418: operands[2] = gen_reg_rtx (CCUNSmode); ! 3419: }") ! 3420: ! 3421: (define_expand "sleu" ! 3422: [(set (match_dup 2) (match_dup 1)) ! 3423: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3424: (leu:SI (match_dup 2) (const_int 0)))] ! 3425: "" ! 3426: " ! 3427: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3428: rs6000_compare_op0, rs6000_compare_op1); ! 3429: operands[2] = gen_reg_rtx (CCUNSmode); ! 3430: }") ! 3431: ! 3432: ;; Here are the actual compare insns. ! 3433: (define_insn "" ! 3434: [(set (match_operand:CC 0 "cc_reg_operand" "=y") ! 3435: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 3436: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 3437: "" ! 3438: "cmp%I2 %0,%1,%2" ! 3439: [(set_attr "type" "compare")]) ! 3440: ! 3441: ;; If we are comparing a register for equality with a large constant, ! 3442: ;; we can do this with an XOR followed by a compare. But we need a scratch ! 3443: ;; register for the result of the XOR. ! 3444: ! 3445: (define_split ! 3446: [(set (match_operand:CC 0 "cc_reg_operand" "") ! 3447: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") ! 3448: (match_operand:SI 2 "non_short_cint_operand" ""))) ! 3449: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 3450: "find_single_use (operands[0], insn, 0) ! 3451: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ ! 3452: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" ! 3453: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) ! 3454: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] ! 3455: " ! 3456: { ! 3457: /* Get the constant we are comparing against, C, and see what it looks like ! 3458: sign-extended to 16 bits. Then see what constant could be XOR'ed ! 3459: with C to get the sign-extended value. */ ! 3460: ! 3461: int c = INTVAL (operands[2]); ! 3462: int sextc = (c << 16) >> 16; ! 3463: int xorv = c ^ sextc; ! 3464: ! 3465: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); ! 3466: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); ! 3467: }") ! 3468: ! 3469: (define_insn "" ! 3470: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") ! 3471: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") ! 3472: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] ! 3473: "" ! 3474: "cmpl%I2 %0,%1,%W2" ! 3475: [(set_attr "type" "compare")]) ! 3476: ! 3477: ;; The following two insns don't exist as single insns, but if we provide ! 3478: ;; them, we can swap an add and compare, which will enable us to overlap more ! 3479: ;; of the required delay between a compare and branch. We generate code for ! 3480: ;; them by splitting. ! 3481: ! 3482: (define_insn "" ! 3483: [(set (match_operand:CC 3 "cc_reg_operand" "=y") ! 3484: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 3485: (match_operand:SI 2 "short_cint_operand" "i"))) ! 3486: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3487: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] ! 3488: "" ! 3489: "#") ! 3490: ! 3491: (define_insn "" ! 3492: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") ! 3493: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") ! 3494: (match_operand:SI 2 "u_short_cint_operand" "i"))) ! 3495: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3496: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] ! 3497: "" ! 3498: "#") ! 3499: ! 3500: (define_split ! 3501: [(set (match_operand:CC 3 "cc_reg_operand" "") ! 3502: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") ! 3503: (match_operand:SI 2 "short_cint_operand" ""))) ! 3504: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3505: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] ! 3506: "" ! 3507: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) ! 3508: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) ! 3509: ! 3510: (define_split ! 3511: [(set (match_operand:CCUNS 3 "cc_reg_operand" "") ! 3512: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") ! 3513: (match_operand:SI 2 "u_short_cint_operand" ""))) ! 3514: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3515: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] ! 3516: "" ! 3517: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) ! 3518: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) ! 3519: ! 3520: (define_insn "" ! 3521: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") ! 3522: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") ! 3523: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 3524: "" ! 3525: "fcmpu %0,%1,%2" ! 3526: [(set_attr "type" "fpcompare")]) ! 3527: ! 3528: (define_insn "" ! 3529: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") ! 3530: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") ! 3531: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 3532: "" ! 3533: "fcmpu %0,%1,%2" ! 3534: [(set_attr "type" "fpcompare")]) ! 3535: ! 3536: ;; Now we have the scc insns. We can do some combinations because of the ! 3537: ;; way the machine works. ! 3538: ;; ! 3539: ;; Note that this is probably faster if we can put an insn between the ! 3540: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most ! 3541: ;; cases the insns below which don't use an intermediate CR field will ! 3542: ;; be used instead. ! 3543: (define_insn "" ! 3544: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3545: (match_operator:SI 1 "scc_comparison_operator" ! 3546: [(match_operand 2 "cc_reg_operand" "y") ! 3547: (const_int 0)]))] ! 3548: "" ! 3549: "%D1mfcr %0\;rlinm %0,%0,%J1,31,31") ! 3550: ! 3551: (define_insn "" ! 3552: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3553: (compare:CC (match_operator:SI 1 "scc_comparison_operator" ! 3554: [(match_operand 2 "cc_reg_operand" "y") ! 3555: (const_int 0)]) ! 3556: (const_int 0))) ! 3557: (set (match_operand:SI 3 "gpc_reg_operand" "=r") ! 3558: (match_op_dup 1 [(match_dup 2) (const_int 0)]))] ! 3559: "" ! 3560: "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31" ! 3561: [(set_attr "type" "delayed_compare")]) ! 3562: ! 3563: (define_insn "" ! 3564: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3565: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" ! 3566: [(match_operand 2 "cc_reg_operand" "y") ! 3567: (const_int 0)]) ! 3568: (match_operand:SI 3 "const_int_operand" "n")))] ! 3569: "" ! 3570: "* ! 3571: { ! 3572: int is_bit = ccr_bit (operands[1], 1); ! 3573: int put_bit = 31 - (INTVAL (operands[3]) & 31); ! 3574: int count; ! 3575: ! 3576: if (is_bit >= put_bit) ! 3577: count = is_bit - put_bit; ! 3578: else ! 3579: count = 32 - (put_bit - is_bit); ! 3580: ! 3581: operands[4] = gen_rtx (CONST_INT, VOIDmode, count); ! 3582: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); ! 3583: ! 3584: return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\"; ! 3585: }") ! 3586: ! 3587: (define_insn "" ! 3588: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3589: (compare:CC ! 3590: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" ! 3591: [(match_operand 2 "cc_reg_operand" "y") ! 3592: (const_int 0)]) ! 3593: (match_operand:SI 3 "const_int_operand" "n")) ! 3594: (const_int 0))) ! 3595: (set (match_operand:SI 4 "gpc_reg_operand" "=r") ! 3596: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) ! 3597: (match_dup 3)))] ! 3598: "" ! 3599: "* ! 3600: { ! 3601: int is_bit = ccr_bit (operands[1], 1); ! 3602: int put_bit = 31 - (INTVAL (operands[3]) & 31); ! 3603: int count; ! 3604: ! 3605: if (is_bit >= put_bit) ! 3606: count = is_bit - put_bit; ! 3607: else ! 3608: count = 32 - (put_bit - is_bit); ! 3609: ! 3610: operands[5] = gen_rtx (CONST_INT, VOIDmode, count); ! 3611: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); ! 3612: ! 3613: return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\"; ! 3614: }" ! 3615: [(set_attr "type" "delayed_compare")]) ! 3616: ! 3617: ;; If we are comparing the result of two comparisons, this can be done ! 3618: ;; using creqv or crxor. ! 3619: ! 3620: (define_insn "" ! 3621: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") ! 3622: (compare:CCEQ (match_operator 1 "scc_comparison_operator" ! 3623: [(match_operand 2 "cc_reg_operand" "y") ! 3624: (const_int 0)]) ! 3625: (match_operator 3 "scc_comparison_operator" ! 3626: [(match_operand 4 "cc_reg_operand" "y") ! 3627: (const_int 0)])))] ! 3628: "REGNO (operands[2]) != REGNO (operands[4])" ! 3629: "* ! 3630: { ! 3631: enum rtx_code code1, code2; ! 3632: ! 3633: code1 = GET_CODE (operands[1]); ! 3634: code2 = GET_CODE (operands[3]); ! 3635: ! 3636: if ((code1 == EQ || code1 == LT || code1 == GT ! 3637: || code1 == LTU || code1 == GTU ! 3638: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) ! 3639: != ! 3640: (code2 == EQ || code2 == LT || code2 == GT ! 3641: || code2 == LTU || code2 == GTU ! 3642: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) ! 3643: return \"%C1%C3crxor %E0,%j1,%j3\"; ! 3644: else ! 3645: return \"%C1%C3creqv %E0,%j1,%j3\"; ! 3646: }") ! 3647: ! 3648: ;; There is a 3 cycle delay between consecutive mfcr instructions ! 3649: ;; so it is useful to combine 2 scc instructions to use only one mfcr. ! 3650: ! 3651: (define_peephole ! 3652: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3653: (match_operator:SI 1 "scc_comparison_operator" ! 3654: [(match_operand 2 "cc_reg_operand" "y") ! 3655: (const_int 0)])) ! 3656: (set (match_operand:SI 3 "gpc_reg_operand" "=r") ! 3657: (match_operator:SI 4 "scc_comparison_operator" ! 3658: [(match_operand 5 "cc_reg_operand" "y") ! 3659: (const_int 0)]))] ! 3660: "REGNO (operands[2]) != REGNO (operands[5])" ! 3661: "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31") ! 3662: ! 3663: ;; There are some scc insns that can be done directly, without a compare. ! 3664: ;; These are faster because they don't involve the communications between ! 3665: ;; the FXU and branch units. In fact, we will be replacing all of the ! 3666: ;; integer scc insns here or in the portable methods in emit_store_flag. ! 3667: ;; ! 3668: ;; Also support (neg (scc ..)) since that construct is used to replace ! 3669: ;; branches, (plus (scc ..) ..) since that construct is common and ! 3670: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the ! 3671: ;; cases where it is no more expensive than (neg (scc ..)). ! 3672: ! 3673: ;; Have reload force a constant into a register for the simple insns that ! 3674: ;; otherwise won't accept constants. We do this because it is faster than ! 3675: ;; the cmp/mfcr sequence we would otherwise generate. ! 3676: ! 3677: (define_insn "" ! 3678: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 3679: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 3680: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) ! 3681: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] ! 3682: "" ! 3683: "@ ! 3684: xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0 ! 3685: sfi %3,%1,0\;ae %0,%3,%1 ! 3686: xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0 ! 3687: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0 ! 3688: sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0") ! 3689: ! 3690: (define_insn "" ! 3691: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") ! 3692: (compare:CC ! 3693: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 3694: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 3695: (const_int 0))) ! 3696: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 3697: (eq:SI (match_dup 1) (match_dup 2))) ! 3698: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] ! 3699: "" ! 3700: "@ ! 3701: xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0 ! 3702: sfi %3,%1,0\;ae. %0,%3,%1 ! 3703: xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0 ! 3704: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0 ! 3705: sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0" ! 3706: [(set_attr "type" "compare")]) ! 3707: ! 3708: (define_insn "" ! 3709: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 3710: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 3711: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 3712: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) ! 3713: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 3714: "" ! 3715: "@ ! 3716: xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3 ! 3717: sfi %4,%1,0\;aze %0,%3 ! 3718: xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3 ! 3719: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3 ! 3720: sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") ! 3721: ! 3722: (define_insn "" ! 3723: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") ! 3724: (compare:CC ! 3725: (plus:SI ! 3726: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 3727: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 3728: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) ! 3729: (const_int 0))) ! 3730: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 3731: "" ! 3732: "@ ! 3733: xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3 ! 3734: sfi %4,%1,0\;aze. %0,%3 ! 3735: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3 ! 3736: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3 ! 3737: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" ! 3738: [(set_attr "type" "compare")]) ! 3739: ! 3740: (define_insn "" ! 3741: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") ! 3742: (compare:CC ! 3743: (plus:SI ! 3744: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 3745: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 3746: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) ! 3747: (const_int 0))) ! 3748: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 3749: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 3750: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 3751: "" ! 3752: "@ ! 3753: xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3 ! 3754: sfi %4,%1,0\;aze. %4,%3 ! 3755: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3 ! 3756: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3 ! 3757: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" ! 3758: [(set_attr "type" "compare")]) ! 3759: ! 3760: (define_insn "" ! 3761: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 3762: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") ! 3763: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] ! 3764: "" ! 3765: "@ ! 3766: xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0 ! 3767: ai %0,%1,-1\;sfe %0,%0,%0 ! 3768: xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0 ! 3769: xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0 ! 3770: sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") ! 3771: ! 3772: ;; This is what (plus (ne X (const_int 0)) Y) looks like. ! 3773: (define_insn "" ! 3774: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3775: (plus:SI (lshiftrt:SI ! 3776: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 3777: (const_int 31)) ! 3778: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 3779: (clobber (match_scratch:SI 3 "=&r"))] ! 3780: "" ! 3781: "ai %3,%1,-1\;aze %0,%2") ! 3782: ! 3783: (define_insn "" ! 3784: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3785: (compare:CC ! 3786: (plus:SI (lshiftrt:SI ! 3787: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 3788: (const_int 31)) ! 3789: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 3790: (const_int 0))) ! 3791: (clobber (match_scratch:SI 3 "=&r"))] ! 3792: "" ! 3793: "ai %3,%1,-1\;aze. %3,%2" ! 3794: [(set_attr "type" "compare")]) ! 3795: ! 3796: (define_insn "" ! 3797: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 3798: (compare:CC ! 3799: (plus:SI (lshiftrt:SI ! 3800: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 3801: (const_int 31)) ! 3802: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 3803: (const_int 0))) ! 3804: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3805: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) ! 3806: (match_dup 2))) ! 3807: (clobber (match_scratch:SI 3 "=&r"))] ! 3808: "" ! 3809: "ai %3,%1,-1\;aze. %0,%2" ! 3810: [(set_attr "type" "compare")]) ! 3811: ! 3812: (define_insn "" ! 3813: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 3814: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3815: (match_operand:SI 2 "reg_or_short_operand" "r,O"))) ! 3816: (clobber (match_scratch:SI 3 "=r,X"))] ! 3817: "" ! 3818: "@ ! 3819: doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3 ! 3820: ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31") ! 3821: ! 3822: (define_insn "" ! 3823: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") ! 3824: (compare:CC ! 3825: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3826: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 3827: (const_int 0))) ! 3828: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 3829: (le:SI (match_dup 1) (match_dup 2))) ! 3830: (clobber (match_scratch:SI 3 "=r,X"))] ! 3831: "" ! 3832: "@ ! 3833: doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3 ! 3834: ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31" ! 3835: [(set_attr "type" "delayed_compare,compare")]) ! 3836: ! 3837: (define_insn "" ! 3838: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 3839: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3840: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 3841: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 3842: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 3843: "" ! 3844: "@ ! 3845: doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3 ! 3846: srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3") ! 3847: ! 3848: (define_insn "" ! 3849: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 3850: (compare:CC ! 3851: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3852: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 3853: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 3854: (const_int 0))) ! 3855: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 3856: "" ! 3857: "@ ! 3858: doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3 ! 3859: srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3" ! 3860: [(set_attr "type" "compare")]) ! 3861: ! 3862: (define_insn "" ! 3863: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 3864: (compare:CC ! 3865: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3866: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 3867: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 3868: (const_int 0))) ! 3869: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 3870: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 3871: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 3872: "" ! 3873: "@ ! 3874: doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3 ! 3875: srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3" ! 3876: [(set_attr "type" "compare")]) ! 3877: ! 3878: (define_insn "" ! 3879: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 3880: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 3881: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] ! 3882: "" ! 3883: "@ ! 3884: doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0 ! 3885: ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31") ! 3886: ! 3887: (define_insn "" ! 3888: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3889: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3890: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 3891: "" ! 3892: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0") ! 3893: ! 3894: (define_insn "" ! 3895: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 3896: (compare:CC ! 3897: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3898: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 3899: (const_int 0))) ! 3900: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3901: (leu:SI (match_dup 1) (match_dup 2)))] ! 3902: "" ! 3903: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0" ! 3904: [(set_attr "type" "compare")]) ! 3905: ! 3906: (define_insn "" ! 3907: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3908: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3909: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 3910: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 3911: (clobber (match_scratch:SI 4 "=&r"))] ! 3912: "" ! 3913: "sf%I2 %4,%1,%2\;aze %0,%3") ! 3914: ! 3915: (define_insn "" ! 3916: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3917: (compare:CC ! 3918: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3919: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 3920: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 3921: (const_int 0))) ! 3922: (clobber (match_scratch:SI 4 "=&r"))] ! 3923: "" ! 3924: "sf%I2 %4,%1,%2\;aze. %4,%3" ! 3925: [(set_attr "type" "compare")]) ! 3926: ! 3927: (define_insn "" ! 3928: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 3929: (compare:CC ! 3930: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3931: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 3932: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 3933: (const_int 0))) ! 3934: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3935: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 3936: (clobber (match_scratch:SI 4 "=&r"))] ! 3937: "" ! 3938: "sf%I2 %4,%1,%2\;aze. %0,%3" ! 3939: [(set_attr "type" "compare")]) ! 3940: ! 3941: (define_insn "" ! 3942: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3943: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3944: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 3945: "" ! 3946: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0") ! 3947: ! 3948: (define_insn "" ! 3949: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3950: (and:SI (neg:SI ! 3951: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3952: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 3953: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 3954: (clobber (match_scratch:SI 4 "=&r"))] ! 3955: "" ! 3956: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4") ! 3957: ! 3958: (define_insn "" ! 3959: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3960: (compare:CC ! 3961: (and:SI (neg:SI ! 3962: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3963: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 3964: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 3965: (const_int 0))) ! 3966: (clobber (match_scratch:SI 4 "=&r"))] ! 3967: "" ! 3968: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4" ! 3969: [(set_attr "type" "compare")]) ! 3970: ! 3971: (define_insn "" ! 3972: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 3973: (compare:CC ! 3974: (and:SI (neg:SI ! 3975: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3976: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 3977: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 3978: (const_int 0))) ! 3979: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3980: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) ! 3981: (clobber (match_scratch:SI 4 "=&r"))] ! 3982: "" ! 3983: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4" ! 3984: [(set_attr "type" "compare")]) ! 3985: ! 3986: (define_insn "" ! 3987: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3988: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3989: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 3990: "" ! 3991: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31") ! 3992: ! 3993: (define_insn "" ! 3994: [(set (match_operand:SI 3 "cc_reg_operand" "=x") ! 3995: (compare:CC ! 3996: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 3997: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 3998: (const_int 0))) ! 3999: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4000: (lt:SI (match_dup 1) (match_dup 2)))] ! 4001: "" ! 4002: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31" ! 4003: [(set_attr "type" "delayed_compare")]) ! 4004: ! 4005: (define_insn "" ! 4006: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4007: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4008: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4009: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4010: (clobber (match_scratch:SI 4 "=&r"))] ! 4011: "" ! 4012: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3") ! 4013: ! 4014: (define_insn "" ! 4015: [(set (match_operand:SI 0 "cc_reg_operand" "=x") ! 4016: (compare:CC ! 4017: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4018: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4019: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4020: (const_int 0))) ! 4021: (clobber (match_scratch:SI 4 "=&r"))] ! 4022: "" ! 4023: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3" ! 4024: [(set_attr "type" "compare")]) ! 4025: ! 4026: (define_insn "" ! 4027: [(set (match_operand:SI 5 "cc_reg_operand" "=x") ! 4028: (compare:CC ! 4029: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4030: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4031: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4032: (const_int 0))) ! 4033: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4034: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4035: (clobber (match_scratch:SI 4 "=&r"))] ! 4036: "" ! 4037: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3" ! 4038: [(set_attr "type" "compare")]) ! 4039: ! 4040: (define_insn "" ! 4041: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4042: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4043: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4044: "" ! 4045: "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31") ! 4046: ! 4047: (define_insn "" ! 4048: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4049: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4050: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] ! 4051: "" ! 4052: "@ ! 4053: sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0 ! 4054: ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0") ! 4055: ! 4056: (define_insn "" ! 4057: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 4058: (compare:CC ! 4059: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4060: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4061: (const_int 0))) ! 4062: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4063: (ltu:SI (match_dup 1) (match_dup 2)))] ! 4064: "" ! 4065: "@ ! 4066: sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0 ! 4067: ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0" ! 4068: [(set_attr "type" "compare")]) ! 4069: ! 4070: (define_insn "" ! 4071: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 4072: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") ! 4073: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) ! 4074: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) ! 4075: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] ! 4076: "" ! 4077: "@ ! 4078: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 ! 4079: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 ! 4080: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 ! 4081: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3") ! 4082: ! 4083: (define_insn "" ! 4084: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") ! 4085: (compare:CC ! 4086: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") ! 4087: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) ! 4088: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) ! 4089: (const_int 0))) ! 4090: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] ! 4091: "" ! 4092: "@ ! 4093: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 ! 4094: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 ! 4095: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 ! 4096: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3" ! 4097: [(set_attr "type" "compare")]) ! 4098: ! 4099: (define_insn "" ! 4100: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x") ! 4101: (compare:CC ! 4102: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") ! 4103: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) ! 4104: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) ! 4105: (const_int 0))) ! 4106: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 4107: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4108: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] ! 4109: "" ! 4110: "@ ! 4111: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 ! 4112: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 ! 4113: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 ! 4114: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3" ! 4115: [(set_attr "type" "compare")]) ! 4116: ! 4117: (define_insn "" ! 4118: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4119: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4120: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] ! 4121: "" ! 4122: "@ ! 4123: sf %0,%2,%1\;sfe %0,%0,%0 ! 4124: ai %0,%1,%n2\;sfe %0,%0,%0") ! 4125: ! 4126: (define_insn "" ! 4127: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4128: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4129: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 4130: (clobber (match_scratch:SI 3 "=r"))] ! 4131: "" ! 4132: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3") ! 4133: ! 4134: (define_insn "" ! 4135: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4136: (compare:CC ! 4137: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4138: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4139: (const_int 0))) ! 4140: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4141: (ge:SI (match_dup 1) (match_dup 2))) ! 4142: (clobber (match_scratch:SI 3 "=r"))] ! 4143: "" ! 4144: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3" ! 4145: [(set_attr "type" "compare")]) ! 4146: ! 4147: (define_insn "" ! 4148: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4149: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4150: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4151: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4152: (clobber (match_scratch:SI 4 "=&r"))] ! 4153: "" ! 4154: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") ! 4155: ! 4156: (define_insn "" ! 4157: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4158: (compare:CC ! 4159: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4160: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4161: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4162: (const_int 0))) ! 4163: (clobber (match_scratch:SI 4 "=&r"))] ! 4164: "" ! 4165: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" ! 4166: [(set_attr "type" "compare")]) ! 4167: ! 4168: (define_insn "" ! 4169: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 4170: (compare:CC ! 4171: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4172: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4173: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4174: (const_int 0))) ! 4175: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4176: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4177: (clobber (match_scratch:SI 4 "=&r"))] ! 4178: "" ! 4179: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" ! 4180: [(set_attr "type" "compare")]) ! 4181: ! 4182: (define_insn "" ! 4183: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4184: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4185: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4186: "" ! 4187: "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") ! 4188: ! 4189: ;; This is (and (neg (ge X (const_int 0))) Y). ! 4190: (define_insn "" ! 4191: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4192: (and:SI (neg:SI ! 4193: (lshiftrt:SI ! 4194: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4195: (const_int 31))) ! 4196: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 4197: (clobber (match_scratch:SI 3 "=&r"))] ! 4198: "" ! 4199: "srai %3,%1,31\;andc %0,%2,%3") ! 4200: ! 4201: (define_insn "" ! 4202: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4203: (compare:CC ! 4204: (and:SI (neg:SI ! 4205: (lshiftrt:SI ! 4206: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4207: (const_int 31))) ! 4208: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4209: (const_int 0))) ! 4210: (clobber (match_scratch:SI 3 "=&r"))] ! 4211: "" ! 4212: "srai %3,%1,31\;andc. %3,%2,%3" ! 4213: [(set_attr "type" "compare")]) ! 4214: ! 4215: (define_insn "" ! 4216: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4217: (compare:CC ! 4218: (and:SI (neg:SI ! 4219: (lshiftrt:SI ! 4220: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4221: (const_int 31))) ! 4222: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4223: (const_int 0))) ! 4224: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4225: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) ! 4226: (const_int 31))) ! 4227: (match_dup 2))) ! 4228: (clobber (match_scratch:SI 3 "=&r"))] ! 4229: "" ! 4230: "srai %3,%1,31\;andc. %0,%2,%3" ! 4231: [(set_attr "type" "compare")]) ! 4232: ! 4233: (define_insn "" ! 4234: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4235: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4236: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] ! 4237: "" ! 4238: "@ ! 4239: sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0 ! 4240: ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0") ! 4241: ! 4242: (define_insn "" ! 4243: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 4244: (compare:CC ! 4245: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4246: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4247: (const_int 0))) ! 4248: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4249: (geu:SI (match_dup 1) (match_dup 2)))] ! 4250: "" ! 4251: "@ ! 4252: sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0 ! 4253: ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0" ! 4254: [(set_attr "type" "compare")]) ! 4255: ! 4256: (define_insn "" ! 4257: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4258: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4259: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4260: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 4261: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4262: "" ! 4263: "@ ! 4264: sf %4,%2,%1\;aze %0,%3 ! 4265: ai %4,%1,%n2\;aze %0,%3") ! 4266: ! 4267: (define_insn "" ! 4268: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 4269: (compare:CC ! 4270: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4271: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4272: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4273: (const_int 0))) ! 4274: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4275: "" ! 4276: "@ ! 4277: sf %4,%2,%1\;aze. %4,%3 ! 4278: ai %4,%1,%n2\;aze. %4,%3" ! 4279: [(set_attr "type" "compare")]) ! 4280: ! 4281: (define_insn "" ! 4282: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 4283: (compare:CC ! 4284: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4285: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4286: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4287: (const_int 0))) ! 4288: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4289: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4290: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4291: "" ! 4292: "@ ! 4293: sf %4,%2,%1\;aze. %0,%3 ! 4294: ai %4,%1,%n2\;aze. %4,%3" ! 4295: [(set_attr "type" "compare")]) ! 4296: ! 4297: (define_insn "" ! 4298: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4299: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4300: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] ! 4301: "" ! 4302: "@ ! 4303: sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0 ! 4304: sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0") ! 4305: ! 4306: (define_insn "" ! 4307: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4308: (and:SI (neg:SI ! 4309: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4310: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 4311: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 4312: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4313: "" ! 4314: "@ ! 4315: sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4 ! 4316: ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4") ! 4317: ! 4318: (define_insn "" ! 4319: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 4320: (compare:CC ! 4321: (and:SI (neg:SI ! 4322: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4323: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 4324: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4325: (const_int 0))) ! 4326: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4327: "" ! 4328: "@ ! 4329: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4 ! 4330: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4" ! 4331: [(set_attr "type" "compare")]) ! 4332: ! 4333: (define_insn "" ! 4334: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 4335: (compare:CC ! 4336: (and:SI (neg:SI ! 4337: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4338: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 4339: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4340: (const_int 0))) ! 4341: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4342: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) ! 4343: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4344: "" ! 4345: "@ ! 4346: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4 ! 4347: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4" ! 4348: [(set_attr "type" "compare")]) ! 4349: ! 4350: (define_insn "" ! 4351: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4352: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4353: (const_int 0)))] ! 4354: "" ! 4355: "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31") ! 4356: ! 4357: (define_insn "" ! 4358: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 4359: (compare:CC ! 4360: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4361: (const_int 0)) ! 4362: (const_int 0))) ! 4363: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4364: (gt:SI (match_dup 1) (const_int 0)))] ! 4365: "" ! 4366: "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31" ! 4367: [(set_attr "type" "delayed_compare")]) ! 4368: ! 4369: (define_insn "" ! 4370: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4371: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4372: (match_operand:SI 2 "reg_or_short_operand" "r")))] ! 4373: "" ! 4374: "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31") ! 4375: ! 4376: (define_insn "" ! 4377: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 4378: (compare:CC ! 4379: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4380: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 4381: (const_int 0))) ! 4382: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4383: (gt:SI (match_dup 1) (match_dup 2)))] ! 4384: "" ! 4385: "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31" ! 4386: [(set_attr "type" "delayed_compare")]) ! 4387: ! 4388: (define_insn "" ! 4389: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4390: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4391: (const_int 0)) ! 4392: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 4393: (clobber (match_scratch:SI 3 "=&r"))] ! 4394: "" ! 4395: "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2") ! 4396: ! 4397: (define_insn "" ! 4398: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4399: (compare:CC ! 4400: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4401: (const_int 0)) ! 4402: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4403: (const_int 0))) ! 4404: (clobber (match_scratch:SI 3 "=&r"))] ! 4405: "" ! 4406: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2" ! 4407: [(set_attr "type" "compare")]) ! 4408: ! 4409: (define_insn "" ! 4410: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4411: (compare:CC ! 4412: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4413: (const_int 0)) ! 4414: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4415: (const_int 0))) ! 4416: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4417: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) ! 4418: (clobber (match_scratch:SI 3 "=&r"))] ! 4419: "" ! 4420: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2" ! 4421: [(set_attr "type" "compare")]) ! 4422: ! 4423: (define_insn "" ! 4424: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4425: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4426: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 4427: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4428: (clobber (match_scratch:SI 4 "=&r"))] ! 4429: "" ! 4430: "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3") ! 4431: ! 4432: (define_insn "" ! 4433: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4434: (compare:CC ! 4435: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4436: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 4437: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4438: (const_int 0))) ! 4439: (clobber (match_scratch:SI 4 "=&r"))] ! 4440: "" ! 4441: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3" ! 4442: [(set_attr "type" "compare")]) ! 4443: ! 4444: (define_insn "" ! 4445: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 4446: (compare:CC ! 4447: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4448: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 4449: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4450: (const_int 0))) ! 4451: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4452: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4453: (clobber (match_scratch:SI 4 "=&r"))] ! 4454: "" ! 4455: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3" ! 4456: [(set_attr "type" "compare")]) ! 4457: ! 4458: (define_insn "" ! 4459: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4460: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4461: (const_int 0))))] ! 4462: "" ! 4463: "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31") ! 4464: ! 4465: (define_insn "" ! 4466: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4467: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4468: (match_operand:SI 2 "reg_or_short_operand" "r"))))] ! 4469: "" ! 4470: "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31") ! 4471: ! 4472: (define_insn "" ! 4473: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4474: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4475: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 4476: "" ! 4477: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0") ! 4478: ! 4479: (define_insn "" ! 4480: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 4481: (compare:CC ! 4482: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4483: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4484: (const_int 0))) ! 4485: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4486: (gtu:SI (match_dup 1) (match_dup 2)))] ! 4487: "" ! 4488: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0" ! 4489: [(set_attr "type" "compare")]) ! 4490: ! 4491: (define_insn "" ! 4492: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 4493: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") ! 4494: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) ! 4495: (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) ! 4496: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] ! 4497: "" ! 4498: "@ ! 4499: ai %4,%1,%k2\;aze %0,%3 ! 4500: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 ! 4501: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3") ! 4502: ! 4503: (define_insn "" ! 4504: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x") ! 4505: (compare:CC ! 4506: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") ! 4507: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) ! 4508: (match_operand:SI 3 "reg_or_short_operand" "r,r,I")) ! 4509: (const_int 0))) ! 4510: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] ! 4511: "" ! 4512: "@ ! 4513: ai %4,%1,%k2\;aze. %0,%3 ! 4514: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 ! 4515: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3" ! 4516: [(set_attr "type" "compare")]) ! 4517: ! 4518: (define_insn "" ! 4519: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x") ! 4520: (compare:CC ! 4521: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") ! 4522: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) ! 4523: (match_operand:SI 3 "reg_or_short_operand" "r,r,I")) ! 4524: (const_int 0))) ! 4525: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 4526: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4527: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] ! 4528: "" ! 4529: "@ ! 4530: ai %4,%1,%k2\;aze. %0,%3 ! 4531: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 ! 4532: sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3" ! 4533: [(set_attr "type" "compare")]) ! 4534: ! 4535: (define_insn "" ! 4536: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4537: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4538: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4539: "" ! 4540: "sf%I2 %0,%1,%2\;sfe %0,%0,%0") ! 4541: ! 4542: ;; Define both directions of branch and return. If we need a reload ! 4543: ;; register, we'd rather use CR0 since it is much easier to copy a ! 4544: ;; register CC value to there. ! 4545: ! 4546: (define_insn "" ! 4547: [(set (pc) ! 4548: (if_then_else (match_operator 1 "branch_comparison_operator" ! 4549: [(match_operand 2 ! 4550: "cc_reg_operand" "x,?y") ! 4551: (const_int 0)]) ! 4552: (label_ref (match_operand 0 "" "")) ! 4553: (pc)))] ! 4554: "" ! 4555: "%C1bc %t1,%j1,%0") ! 4556: ! 4557: (define_insn "" ! 4558: [(set (pc) ! 4559: (if_then_else (match_operator 0 "branch_comparison_operator" ! 4560: [(match_operand 1 ! 4561: "cc_reg_operand" "x,?y") ! 4562: (const_int 0)]) ! 4563: (return) ! 4564: (pc)))] ! 4565: "direct_return ()" ! 4566: "%C0bcr %t0,%j0") ! 4567: ! 4568: (define_insn "" ! 4569: [(set (pc) ! 4570: (if_then_else (match_operator 1 "branch_comparison_operator" ! 4571: [(match_operand 2 ! 4572: "cc_reg_operand" "x,?y") ! 4573: (const_int 0)]) ! 4574: (pc) ! 4575: (label_ref (match_operand 0 "" ""))))] ! 4576: "" ! 4577: "%C1bc %T1,%j1,%0") ! 4578: ! 4579: (define_insn "" ! 4580: [(set (pc) ! 4581: (if_then_else (match_operator 0 "branch_comparison_operator" ! 4582: [(match_operand 1 ! 4583: "cc_reg_operand" "x,?y") ! 4584: (const_int 0)]) ! 4585: (pc) ! 4586: (return)))] ! 4587: "direct_return ()" ! 4588: "%C0bcr %T0,%j0") ! 4589: ! 4590: ;; Unconditional branch and return. ! 4591: ! 4592: (define_insn "jump" ! 4593: [(set (pc) ! 4594: (label_ref (match_operand 0 "" "")))] ! 4595: "" ! 4596: "b %l0") ! 4597: ! 4598: (define_insn "return" ! 4599: [(return)] ! 4600: "direct_return ()" ! 4601: "br") ! 4602: ! 4603: (define_insn "indirect_jump" ! 4604: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] ! 4605: "" ! 4606: "@ ! 4607: bctr ! 4608: br") ! 4609: ! 4610: ;; Table jump for switch statements: ! 4611: (define_expand "tablejump" ! 4612: [(set (match_dup 3) ! 4613: (plus:SI (match_operand:SI 0 "" "") ! 4614: (match_dup 2))) ! 4615: (parallel [(set (pc) (match_dup 3)) ! 4616: (use (label_ref (match_operand 1 "" "")))])] ! 4617: "" ! 4618: " ! 4619: { operands[0] = force_reg (SImode, operands[0]); ! 4620: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); ! 4621: operands[3] = gen_reg_rtx (SImode); ! 4622: }") ! 4623: ! 4624: (define_insn "" ! 4625: [(set (pc) ! 4626: (match_operand:SI 0 "register_operand" "c,l")) ! 4627: (use (label_ref (match_operand 1 "" "")))] ! 4628: "" ! 4629: "@ ! 4630: bctr ! 4631: br") ! 4632: ! 4633: (define_insn "nop" ! 4634: [(const_int 0)] ! 4635: "" ! 4636: "cror 0,0,0") ! 4637: ! 4638: ;; Define the subtract-one-and-jump insns, starting with the template ! 4639: ;; so loop.c knows what to generate. ! 4640: ! 4641: (define_expand "decrement_and_branchsi" ! 4642: [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c") ! 4643: (const_int 1)) ! 4644: (label_ref (match_operand 1 "" "")) ! 4645: (pc))) ! 4646: (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] ! 4647: "" ! 4648: "") ! 4649: ! 4650: ;; We need to be able to do this for any operand, including MEM, or we ! 4651: ;; will cause reload to blow up since we don't allow output reloads on ! 4652: ;; JUMP_INSNs. ! 4653: (define_insn "" ! 4654: [(set (pc) ! 4655: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r") ! 4656: (const_int 1)) ! 4657: (label_ref (match_operand 2 "" "")) ! 4658: (pc))) ! 4659: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 4660: (plus:SI (match_dup 1) (const_int -1))) ! 4661: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 4662: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 4663: "" ! 4664: "@ ! 4665: bdn %l2 ! 4666: # ! 4667: #") ! 4668: ! 4669: ;; Similar, but we can use GE since we have a REG_NONNEG. ! 4670: (define_insn "" ! 4671: [(set (pc) ! 4672: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r") ! 4673: (const_int 0)) ! 4674: (label_ref (match_operand 2 "" "")) ! 4675: (pc))) ! 4676: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 4677: (plus:SI (match_dup 1) (const_int -1))) ! 4678: (clobber (match_scratch:CC 3 "=X,&x,&X")) ! 4679: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 4680: "find_reg_note (insn, REG_NONNEG, 0)" ! 4681: "@ ! 4682: bdn %l2 ! 4683: # ! 4684: #") ! 4685: ! 4686: (define_insn "" ! 4687: [(set (pc) ! 4688: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r") ! 4689: (const_int 1)) ! 4690: (label_ref (match_operand 2 "" "")) ! 4691: (pc))) ! 4692: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 4693: (plus:SI (match_dup 1) (const_int -1))) ! 4694: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 4695: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 4696: "" ! 4697: "@ ! 4698: bdz %l2 ! 4699: # ! 4700: #") ! 4701: ! 4702: (define_split ! 4703: [(set (pc) ! 4704: (if_then_else (match_operator 2 "comparison_operator" ! 4705: [(match_operand:SI 1 "gpc_reg_operand" "") ! 4706: (const_int 1)]) ! 4707: (match_operand 5 "" "") ! 4708: (match_operand 6 "" ""))) ! 4709: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4710: (plus:SI (match_dup 1) (const_int -1))) ! 4711: (clobber (match_scratch:CC 3 "")) ! 4712: (clobber (match_scratch:SI 4 ""))] ! 4713: "reload_completed" ! 4714: [(parallel [(set (match_dup 3) ! 4715: (compare:CC (plus:SI (match_dup 1) (const_int -1)) ! 4716: (const_int 0))) ! 4717: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) ! 4718: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] ! 4719: " ! 4720: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], ! 4721: const0_rtx); }") ! 4722: ! 4723: (define_split ! 4724: [(set (pc) ! 4725: (if_then_else (match_operator 2 "comparison_operator" ! 4726: [(match_operand:SI 1 "gpc_reg_operand" "") ! 4727: (const_int 1)]) ! 4728: (match_operand 5 "" "") ! 4729: (match_operand 6 "" ""))) ! 4730: (set (match_operand:SI 0 "general_operand" "") ! 4731: (plus:SI (match_dup 1) (const_int -1))) ! 4732: (clobber (match_scratch:CC 3 "")) ! 4733: (clobber (match_scratch:SI 4 ""))] ! 4734: "reload_completed && ! gpc_reg_operand (operands[0], SImode)" ! 4735: [(parallel [(set (match_dup 3) ! 4736: (compare:CC (plus:SI (match_dup 1) (const_int -1)) ! 4737: (const_int 0))) ! 4738: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))]) ! 4739: (set (match_dup 0) (match_dup 4)) ! 4740: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] ! 4741: " ! 4742: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], ! 4743: const0_rtx); }")
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