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1.1.1.3 ! root 1: ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler ! 2: ;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22: 23: ;; Define an insn type attribute. This is used in function unit delay 24: ;; computations. 1.1.1.3 ! root 25: (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" 1.1 root 26: (const_string "integer")) 27: 1.1.1.2 root 28: ;; Length (in bytes). 29: (define_attr "length" "" 30: (if_then_else (eq_attr "type" "branch") 31: (if_then_else (and (ge (minus (pc) (match_dup 0)) 32: (const_int -32768)) 33: (lt (minus (pc) (match_dup 0)) 34: (const_int 32767))) 35: (const_int 8) 36: (const_int 12)) 37: (const_int 4))) 38: 39: ;; Processor type -- this attribute must exactly match the processor_type 40: ;; enumeration in rs6000.h. 41: 42: (define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620" 43: (const (symbol_ref "rs6000_cpu_attr"))) 44: 45: ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY 46: ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) 47: 1.1.1.3 ! root 48: ; Load/Store Unit -- POWER/2 and pure PowerPC only ! 49: ; (POWER and 601 use Integer Unit) 1.1.1.2 root 50: (define_function_unit "lsu" 1 0 51: (and (eq_attr "type" "load") 52: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 53: 2 0) 54: 55: (define_function_unit "lsu" 1 0 56: (and (eq_attr "type" "fpload") 57: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 58: 2 0) 59: 60: (define_function_unit "iu" 1 0 61: (and (eq_attr "type" "load") 62: (eq_attr "cpu" "rios1,ppc601")) 63: 2 0) 64: 65: (define_function_unit "iu" 1 0 66: (and (eq_attr "type" "fpload") 67: (eq_attr "cpu" "rios1,ppc601")) 68: 3 0) 69: 1.1.1.3 ! root 70: ; Integer Unit (RIOS1, PPC601, PPC603) ! 71: ; Trivial operations take one cycle which need not be listed here. 1.1.1.2 root 72: (define_function_unit "iu" 1 0 73: (and (eq_attr "type" "imul") 74: (eq_attr "cpu" "rios1")) 1.1.1.3 ! root 75: 3 3) 1.1.1.2 root 76: 77: (define_function_unit "iu" 1 0 78: (and (eq_attr "type" "imul") 1.1.1.3 ! root 79: (eq_attr "cpu" "ppc601,ppc603")) ! 80: 5 5) 1.1.1.2 root 81: 82: (define_function_unit "iu" 1 0 83: (and (eq_attr "type" "idiv") 84: (eq_attr "cpu" "rios1")) 1.1.1.3 ! root 85: 19 19) 1.1.1.2 root 86: 87: (define_function_unit "iu" 1 0 88: (and (eq_attr "type" "idiv") 1.1.1.3 ! root 89: (eq_attr "cpu" "ppc601")) ! 90: 36 36) ! 91: ! 92: (define_function_unit "iu" 1 0 ! 93: (and (eq_attr "type" "idiv") ! 94: (eq_attr "cpu" "ppc603")) ! 95: 37 36) ! 96: ! 97: ; RIOS2 has two integer units: a primary one which can perform all ! 98: ; operations and a secondary one which is fed in lock step with the first ! 99: ; and can perform "simple" integer operations. ! 100: (define_function_unit "iu2" 2 0 ! 101: (and (eq_attr "type" "integer") ! 102: (eq_attr "cpu" "rios2")) ! 103: 1 0 ! 104: [(eq_attr "type" "imul,idiv")]) ! 105: ! 106: (define_function_unit "imuldiv" 1 0 ! 107: (and (eq_attr "type" "imul") ! 108: (eq_attr "cpu" "rios2")) ! 109: 2 2 ! 110: [(eq_attr "type" "integer")]) ! 111: ! 112: (define_function_unit "imuldiv" 1 0 ! 113: (and (eq_attr "type" "idiv") ! 114: (eq_attr "cpu" "rios2")) ! 115: 13 13 ! 116: [(eq_attr "type" "integer")]) ! 117: ! 118: ; PPC604 has three integer units: one primary and two secondary. ! 119: (define_function_unit "iu3" 3 0 ! 120: (and (eq_attr "type" "integer") ! 121: (eq_attr "cpu" "ppc604,ppc620")) ! 122: 1 0 ! 123: [(eq_attr "type" "imul,idiv")]) ! 124: ! 125: (define_function_unit "imuldiv" 1 0 ! 126: (and (eq_attr "type" "imul") ! 127: (eq_attr "cpu" "ppc604,ppc620")) ! 128: 4 2 ! 129: [(eq_attr "type" "integer")]) ! 130: ! 131: (define_function_unit "imuldiv" 1 0 ! 132: (and (eq_attr "type" "idiv") ! 133: (eq_attr "cpu" "ppc604,ppc620")) ! 134: 20 19 ! 135: [(eq_attr "type" "integer")]) 1.1.1.2 root 136: 1.1.1.3 ! root 137: ; Branch Processing Unit 1.1.1.2 root 138: (define_function_unit "bpu" 1 0 139: (eq_attr "type" "compare") 140: 4 0) 141: 142: (define_function_unit "bpu" 1 0 143: (eq_attr "type" "delayed_compare") 144: 5 0) 145: 146: (define_function_unit "bpu" 1 0 147: (and (eq_attr "type" "fpcompare") 148: (eq_attr "cpu" "rios1,rios2")) 149: 8 0) 150: 151: (define_function_unit "bpu" 1 0 152: (and (eq_attr "type" "fpcompare") 153: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) 154: 4 0) 155: 156: (define_function_unit "bpu" 1 0 1.1.1.3 ! root 157: (and (eq_attr "type" "mtjmpr") 1.1.1.2 root 158: (eq_attr "cpu" "rios1,rios2")) 159: 5 0) 160: 161: (define_function_unit "bpu" 1 0 1.1.1.3 ! root 162: (and (eq_attr "type" "mtjmpr") 1.1.1.2 root 163: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) 164: 4 0) 165: 1.1.1.3 ! root 166: ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604). 1.1.1.2 root 167: (define_function_unit "fpu" 1 0 1.1.1.3 ! root 168: (and (eq_attr "type" "fp,dmul") 1.1.1.2 root 169: (eq_attr "cpu" "rios1")) 170: 2 0) 171: 172: (define_function_unit "fpu" 1 0 173: (and (eq_attr "type" "fp") 1.1.1.3 ! root 174: (eq_attr "cpu" "ppc601")) 1.1.1.2 root 175: 4 0) 176: 177: (define_function_unit "fpu" 1 0 1.1.1.3 ! root 178: (and (eq_attr "type" "fp") ! 179: (eq_attr "cpu" "ppc603,ppc604,ppc620")) ! 180: 3 0) ! 181: ! 182: (define_function_unit "fpu" 1 0 1.1.1.2 root 183: (and (eq_attr "type" "dmul") 1.1.1.3 ! root 184: (eq_attr "cpu" "ppc601")) ! 185: 5 5) 1.1.1.2 root 186: 187: (define_function_unit "fpu" 1 0 188: (and (eq_attr "type" "dmul") 1.1.1.3 ! root 189: (eq_attr "cpu" "ppc603")) ! 190: 4 2) 1.1.1.2 root 191: 192: (define_function_unit "fpu" 1 0 1.1.1.3 ! root 193: (and (eq_attr "type" "dmul") ! 194: (eq_attr "cpu" "ppc604,ppc620")) ! 195: 3 0) ! 196: ! 197: (define_function_unit "fpu" 1 0 ! 198: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 199: (eq_attr "cpu" "rios1")) 1.1.1.3 ! root 200: 19 19) 1.1.1.2 root 201: 202: (define_function_unit "fpu" 1 0 203: (and (eq_attr "type" "sdiv") 1.1.1.3 ! root 204: (eq_attr "cpu" "ppc601")) ! 205: 17 17) ! 206: ! 207: (define_function_unit "fpu" 1 0 ! 208: (and (eq_attr "type" "sdiv") ! 209: (eq_attr "cpu" "ppc603,ppc604,ppc620")) ! 210: 18 18) 1.1.1.2 root 211: 212: (define_function_unit "fpu" 1 0 213: (and (eq_attr "type" "ddiv") 1.1.1.3 ! root 214: (eq_attr "cpu" "ppc601,ppc604,ppc620")) ! 215: 31 31) 1.1.1.2 root 216: 217: (define_function_unit "fpu" 1 0 218: (and (eq_attr "type" "ddiv") 1.1.1.3 ! root 219: (eq_attr "cpu" "ppc603")) ! 220: 33 33) 1.1.1.2 root 221: 222: (define_function_unit "fpu" 1 0 223: (and (eq_attr "type" "ssqrt") 1.1.1.3 ! root 224: (eq_attr "cpu" "ppc620")) ! 225: 31 31) 1.1.1.2 root 226: 227: (define_function_unit "fpu" 1 0 228: (and (eq_attr "type" "dsqrt") 1.1.1.3 ! root 229: (eq_attr "cpu" "ppc620")) ! 230: 31 31) 1.1.1.2 root 231: 1.1.1.3 ! root 232: ; RIOS2 has two symmetric FPUs. 1.1.1.2 root 233: (define_function_unit "fpu2" 2 0 234: (and (eq_attr "type" "fp") 235: (eq_attr "cpu" "rios2")) 236: 2 0) 237: 238: (define_function_unit "fpu2" 2 0 239: (and (eq_attr "type" "dmul") 240: (eq_attr "cpu" "rios2")) 241: 2 0) 242: 243: (define_function_unit "fpu2" 2 0 1.1.1.3 ! root 244: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 245: (eq_attr "cpu" "rios2")) 1.1.1.3 ! root 246: 17 17) 1.1.1.2 root 247: 248: (define_function_unit "fpu2" 2 0 1.1.1.3 ! root 249: (and (eq_attr "type" "ssqrt,dsqrt") 1.1.1.2 root 250: (eq_attr "cpu" "rios2")) 1.1.1.3 ! root 251: 26 26) 1.1 root 252: 253: ;; Start with fixed-point load and store insns. Here we put only the more 254: ;; complex forms. Basic data transfer is done later. 255: 1.1.1.3 ! root 256: (define_expand "zero_extendqidi2" ! 257: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 258: (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] ! 259: "TARGET_POWERPC64" ! 260: "") ! 261: ! 262: (define_insn "" ! 263: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 264: (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] ! 265: "TARGET_POWERPC64" ! 266: "@ ! 267: lbz%U1%X1 %0,%1 ! 268: rldicl %0,%1,0,56" ! 269: [(set_attr "type" "load,*")]) ! 270: ! 271: (define_insn "" ! 272: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 273: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 274: (const_int 0))) ! 275: (clobber (match_scratch:DI 2 "=r"))] ! 276: "TARGET_POWERPC64" ! 277: "rldicl. %2,%1,0,56" ! 278: [(set_attr "type" "compare")]) ! 279: ! 280: (define_insn "" ! 281: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 282: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 283: (const_int 0))) ! 284: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 285: (zero_extend:DI (match_dup 1)))] ! 286: "TARGET_POWERPC64" ! 287: "rldicl. %0,%1,0,56" ! 288: [(set_attr "type" "compare")]) ! 289: ! 290: (define_insn "extendqidi2" ! 291: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 292: (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] ! 293: "TARGET_POWERPC64" ! 294: "extsb %0,%1") ! 295: ! 296: (define_insn "" ! 297: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 298: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 299: (const_int 0))) ! 300: (clobber (match_scratch:DI 2 "=r"))] ! 301: "TARGET_POWERPC64" ! 302: "extsb. %2,%1" ! 303: [(set_attr "type" "compare")]) ! 304: ! 305: (define_insn "" ! 306: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 307: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 308: (const_int 0))) ! 309: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 310: (sign_extend:DI (match_dup 1)))] ! 311: "TARGET_POWERPC64" ! 312: "extsb. %0,%1" ! 313: [(set_attr "type" "compare")]) ! 314: ! 315: (define_expand "zero_extendhidi2" ! 316: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 317: (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 318: "TARGET_POWERPC64" ! 319: "") ! 320: ! 321: (define_insn "" ! 322: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 323: (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 324: "TARGET_POWERPC64" ! 325: "@ ! 326: lhz%U1%X1 %0,%1 ! 327: rldicl %0,%1,0,48" ! 328: [(set_attr "type" "load,*")]) ! 329: ! 330: (define_insn "" ! 331: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 332: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 333: (const_int 0))) ! 334: (clobber (match_scratch:DI 2 "=r"))] ! 335: "TARGET_POWERPC64" ! 336: "rldicl. %2,%1,0,48" ! 337: [(set_attr "type" "compare")]) ! 338: ! 339: (define_insn "" ! 340: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 341: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 342: (const_int 0))) ! 343: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 344: (zero_extend:DI (match_dup 1)))] ! 345: "TARGET_POWERPC64" ! 346: "rldicl. %0,%1,0,48" ! 347: [(set_attr "type" "compare")]) ! 348: ! 349: (define_expand "extendhidi2" ! 350: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 351: (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 352: "TARGET_POWERPC64" ! 353: "") ! 354: ! 355: (define_insn "" ! 356: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 357: (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 358: "TARGET_POWERPC64" ! 359: "@ ! 360: lha%U1%X1 %0,%1 ! 361: extsh %0,%1" ! 362: [(set_attr "type" "load,*")]) ! 363: ! 364: (define_insn "" ! 365: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 366: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 367: (const_int 0))) ! 368: (clobber (match_scratch:DI 2 "=r"))] ! 369: "TARGET_POWERPC64" ! 370: "extsh. %2,%1" ! 371: [(set_attr "type" "compare")]) ! 372: ! 373: (define_insn "" ! 374: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 375: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 376: (const_int 0))) ! 377: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 378: (sign_extend:DI (match_dup 1)))] ! 379: "TARGET_POWERPC64" ! 380: "extsh. %0,%1" ! 381: [(set_attr "type" "compare")]) ! 382: ! 383: (define_expand "zero_extendsidi2" ! 384: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 385: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] ! 386: "TARGET_POWERPC64" ! 387: "") ! 388: ! 389: (define_insn "" ! 390: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 391: (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] ! 392: "TARGET_POWERPC64" ! 393: "@ ! 394: lwz%U1%X1 %0,%1 ! 395: rldicl %0,%1,0,32" ! 396: [(set_attr "type" "load,*")]) ! 397: ! 398: (define_insn "" ! 399: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 400: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 401: (const_int 0))) ! 402: (clobber (match_scratch:DI 2 "=r"))] ! 403: "TARGET_POWERPC64" ! 404: "rldicl. %2,%1,0,32" ! 405: [(set_attr "type" "compare")]) ! 406: ! 407: (define_insn "" ! 408: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 409: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 410: (const_int 0))) ! 411: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 412: (zero_extend:DI (match_dup 1)))] ! 413: "TARGET_POWERPC64" ! 414: "rldicl. %0,%1,0,32" ! 415: [(set_attr "type" "compare")]) ! 416: ! 417: (define_expand "extendsidi2" ! 418: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 419: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] ! 420: "TARGET_POWERPC64" ! 421: "") ! 422: ! 423: (define_insn "" ! 424: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 425: (sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] ! 426: "TARGET_POWERPC64" ! 427: "@ ! 428: lwa%U1%X1 %0,%1 ! 429: extsw %0,%1" ! 430: [(set_attr "type" "load,*")]) ! 431: ! 432: (define_insn "" ! 433: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 434: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 435: (const_int 0))) ! 436: (clobber (match_scratch:DI 2 "=r"))] ! 437: "TARGET_POWERPC64" ! 438: "extsw. %2,%1" ! 439: [(set_attr "type" "compare")]) ! 440: ! 441: (define_insn "" ! 442: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 443: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 444: (const_int 0))) ! 445: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 446: (sign_extend:DI (match_dup 1)))] ! 447: "TARGET_POWERPC64" ! 448: "extsw. %0,%1" ! 449: [(set_attr "type" "compare")]) ! 450: 1.1 root 451: (define_expand "zero_extendqisi2" 452: [(set (match_operand:SI 0 "gpc_reg_operand" "") 453: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 454: "" 455: "") 456: 457: (define_insn "" 458: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 459: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 460: "" 461: "@ 462: lbz%U1%X1 %0,%1 1.1.1.2 root 463: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 464: [(set_attr "type" "load,*")]) 465: 466: (define_insn "" 467: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 468: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 469: (const_int 0))) 470: (clobber (match_scratch:SI 2 "=r"))] 471: "" 1.1.1.2 root 472: "{andil.|andi.} %2,%1,0xff" 1.1 root 473: [(set_attr "type" "compare")]) 474: 475: (define_insn "" 476: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 477: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 478: (const_int 0))) 479: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 480: (zero_extend:SI (match_dup 1)))] 481: "" 1.1.1.2 root 482: "{andil.|andi.} %0,%1,0xff" 1.1 root 483: [(set_attr "type" "compare")]) 484: 1.1.1.3 ! root 485: (define_expand "extendqisi2" ! 486: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 487: (use (match_operand:QI 1 "gpc_reg_operand" ""))] ! 488: "" ! 489: " ! 490: { ! 491: if (TARGET_POWERPC) ! 492: emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); ! 493: else if (TARGET_POWER) ! 494: emit_insn (gen_extendqisi2_power (operands[0], operands[1])); ! 495: else ! 496: emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); ! 497: DONE; ! 498: }") ! 499: ! 500: (define_insn "extendqisi2_ppc" ! 501: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 502: (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] ! 503: "TARGET_POWERPC" ! 504: "extsb %0,%1") ! 505: ! 506: (define_insn "" ! 507: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 508: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 509: (const_int 0))) ! 510: (clobber (match_scratch:SI 2 "=r"))] ! 511: "TARGET_POWERPC" ! 512: "extsb. %2,%1" ! 513: [(set_attr "type" "compare")]) ! 514: ! 515: (define_insn "" ! 516: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 517: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 518: (const_int 0))) ! 519: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 520: (sign_extend:SI (match_dup 1)))] ! 521: "TARGET_POWERPC" ! 522: "extsb. %0,%1" ! 523: [(set_attr "type" "compare")]) ! 524: ! 525: (define_expand "extendqisi2_power" ! 526: [(parallel [(set (match_dup 2) ! 527: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 528: (const_int 24))) ! 529: (clobber (scratch:SI))]) ! 530: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 531: (ashiftrt:SI (match_dup 2) ! 532: (const_int 24))) ! 533: (clobber (scratch:SI))])] ! 534: "TARGET_POWER" ! 535: " ! 536: { operands[1] = gen_lowpart (SImode, operands[1]); ! 537: operands[2] = gen_reg_rtx (SImode); }") ! 538: ! 539: (define_expand "extendqisi2_no_power" ! 540: [(set (match_dup 2) ! 541: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 542: (const_int 24))) ! 543: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 544: (ashiftrt:SI (match_dup 2) ! 545: (const_int 24)))] ! 546: "! TARGET_POWER && ! TARGET_POWERPC" ! 547: " ! 548: { operands[1] = gen_lowpart (SImode, operands[1]); ! 549: operands[2] = gen_reg_rtx (SImode); }") ! 550: 1.1 root 551: (define_expand "zero_extendqihi2" 552: [(set (match_operand:HI 0 "gpc_reg_operand" "") 553: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 554: "" 555: "") 556: 557: (define_insn "" 558: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 559: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 560: "" 561: "@ 562: lbz%U1%X1 %0,%1 1.1.1.2 root 563: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 564: [(set_attr "type" "load,*")]) 565: 1.1.1.3 ! root 566: (define_insn "" ! 567: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 568: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 569: (const_int 0))) ! 570: (clobber (match_scratch:HI 2 "=r"))] ! 571: "" ! 572: "{andil.|andi.} %2,%1,0xff" ! 573: [(set_attr "type" "compare")]) ! 574: ! 575: (define_insn "" ! 576: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 577: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 578: (const_int 0))) ! 579: (set (match_operand:HI 0 "gpc_reg_operand" "=r") ! 580: (zero_extend:HI (match_dup 1)))] ! 581: "" ! 582: "{andil.|andi.} %0,%1,0xff" ! 583: [(set_attr "type" "compare")]) ! 584: ! 585: (define_expand "extendqihi2" ! 586: [(use (match_operand:HI 0 "gpc_reg_operand" "")) ! 587: (use (match_operand:QI 1 "gpc_reg_operand" ""))] ! 588: "" ! 589: " ! 590: { ! 591: if (TARGET_POWERPC) ! 592: emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); ! 593: else if (TARGET_POWER) ! 594: emit_insn (gen_extendqihi2_power (operands[0], operands[1])); ! 595: else ! 596: emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); ! 597: DONE; ! 598: }") ! 599: ! 600: (define_insn "extendqihi2_ppc" ! 601: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") ! 602: (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] ! 603: "TARGET_POWERPC" ! 604: "extsb %0,%1") ! 605: ! 606: (define_insn "" ! 607: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 608: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 609: (const_int 0))) ! 610: (clobber (match_scratch:HI 2 "=r"))] ! 611: "TARGET_POWERPC" ! 612: "extsb. %2,%1" ! 613: [(set_attr "type" "compare")]) ! 614: ! 615: (define_insn "" ! 616: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 617: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 618: (const_int 0))) ! 619: (set (match_operand:HI 0 "gpc_reg_operand" "=r") ! 620: (sign_extend:HI (match_dup 1)))] ! 621: "TARGET_POWERPC" ! 622: "extsb. %0,%1" ! 623: [(set_attr "type" "compare")]) ! 624: ! 625: (define_expand "extendqihi2_power" ! 626: [(parallel [(set (match_dup 2) ! 627: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 628: (const_int 24))) ! 629: (clobber (scratch:SI))]) ! 630: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") ! 631: (ashiftrt:SI (match_dup 2) ! 632: (const_int 24))) ! 633: (clobber (scratch:SI))])] ! 634: "TARGET_POWER" ! 635: " ! 636: { operands[0] = gen_lowpart (SImode, operands[0]); ! 637: operands[1] = gen_lowpart (SImode, operands[1]); ! 638: operands[2] = gen_reg_rtx (SImode); }") ! 639: ! 640: (define_expand "extendqihi2_no_power" ! 641: [(set (match_dup 2) ! 642: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 643: (const_int 24))) ! 644: (set (match_operand:HI 0 "gpc_reg_operand" "") ! 645: (ashiftrt:SI (match_dup 2) ! 646: (const_int 24)))] ! 647: "! TARGET_POWER && ! TARGET_POWERPC" ! 648: " ! 649: { operands[0] = gen_lowpart (SImode, operands[0]); ! 650: operands[1] = gen_lowpart (SImode, operands[1]); ! 651: operands[2] = gen_reg_rtx (SImode); }") ! 652: 1.1 root 653: (define_expand "zero_extendhisi2" 654: [(set (match_operand:SI 0 "gpc_reg_operand" "") 655: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 656: "" 657: "") 658: 659: (define_insn "" 660: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 661: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 662: "" 663: "@ 664: lhz%U1%X1 %0,%1 1.1.1.2 root 665: {rlinm|rlwinm} %0,%1,0,0xffff" 1.1 root 666: [(set_attr "type" "load,*")]) 667: 668: (define_insn "" 669: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 670: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 671: (const_int 0))) 672: (clobber (match_scratch:SI 2 "=r"))] 673: "" 1.1.1.2 root 674: "{andil.|andi.} %2,%1,0xffff" 1.1 root 675: [(set_attr "type" "compare")]) 676: 677: (define_insn "" 678: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 679: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 680: (const_int 0))) 681: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 682: (zero_extend:SI (match_dup 1)))] 683: "" 1.1.1.2 root 684: "{andil.|andi.} %0,%1,0xffff" 1.1 root 685: [(set_attr "type" "compare")]) 686: 687: (define_expand "extendhisi2" 688: [(set (match_operand:SI 0 "gpc_reg_operand" "") 689: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 690: "" 691: "") 692: 693: (define_insn "" 694: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 695: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 696: "" 697: "@ 698: lha%U1%X1 %0,%1 1.1.1.2 root 699: {exts|extsh} %0,%1" 1.1 root 700: [(set_attr "type" "load,*")]) 701: 702: (define_insn "" 703: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 704: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 705: (const_int 0))) 706: (clobber (match_scratch:SI 2 "=r"))] 707: "" 1.1.1.2 root 708: "{exts.|extsh.} %2,%1" 1.1 root 709: [(set_attr "type" "compare")]) 710: 711: (define_insn "" 712: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 713: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 714: (const_int 0))) 715: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 716: (sign_extend:SI (match_dup 1)))] 717: "" 1.1.1.2 root 718: "{exts.|extsh.} %0,%1" 1.1 root 719: [(set_attr "type" "compare")]) 720: 721: ;; Fixed-point arithmetic insns. 1.1.1.3 ! root 722: ! 723: ;; Discourage ai/addic because of carry but provide it in an alternative ! 724: ;; allowing register zero as source. 1.1 root 725: (define_insn "addsi3" 1.1.1.3 ! root 726: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") ! 727: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") ! 728: (match_operand:SI 2 "add_operand" "r,I,I,J")))] 1.1 root 729: "" 730: "@ 1.1.1.3 ! root 731: {cax|add} %0,%1,%2 ! 732: {cal %0,%2(%1)|addi %0,%1,%2} ! 733: {ai|addic} %0,%1,%2 1.1.1.2 root 734: {cau|addis} %0,%1,%u2") 1.1 root 735: 736: (define_insn "" 1.1.1.3 ! root 737: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 738: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 739: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 740: (const_int 0))) 1.1.1.3 ! root 741: (clobber (match_scratch:SI 3 "=r,r"))] 1.1 root 742: "" 1.1.1.3 ! root 743: "@ ! 744: {cax.|add.} %3,%1,%2 ! 745: {ai.|addic.} %3,%1,%2" 1.1 root 746: [(set_attr "type" "compare")]) 747: 748: (define_insn "" 1.1.1.3 ! root 749: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 750: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 751: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 752: (const_int 0))) 1.1.1.3 ! root 753: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 754: (plus:SI (match_dup 1) (match_dup 2)))] 755: "" 1.1.1.3 ! root 756: "@ ! 757: {cax.|add.} %0,%1,%2 ! 758: {ai.|addic.} %0,%1,%2" 1.1 root 759: [(set_attr "type" "compare")]) 760: 761: ;; Split an add that we can't do in one insn into two insns, each of which 762: ;; does one 16-bit part. This is used by combine. Note that the low-order 763: ;; add should be last in case the result gets used in an address. 764: 765: (define_split 766: [(set (match_operand:SI 0 "gpc_reg_operand" "") 767: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 768: (match_operand:SI 2 "non_add_cint_operand" "")))] 769: "" 770: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 771: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 772: " 773: { 774: int low = INTVAL (operands[2]) & 0xffff; 775: int high = (unsigned) INTVAL (operands[2]) >> 16; 776: 777: if (low & 0x8000) 778: high++, low |= 0xffff0000; 779: 780: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); 781: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); 782: }") 783: 1.1.1.3 ! root 784: (define_insn "one_cmplsi2" 1.1 root 785: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 786: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 787: "" 1.1.1.2 root 788: "nor %0,%1,%1") 789: 790: (define_insn "" 791: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 792: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 793: (const_int 0))) 794: (clobber (match_scratch:SI 2 "=r"))] 1.1 root 795: "" 1.1.1.2 root 796: "nor. %2,%1,%1" 797: [(set_attr "type" "compare")]) 798: 799: (define_insn "" 1.1.1.3 ! root 800: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1.1.1.2 root 801: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 802: (const_int 0))) 803: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 804: (not:SI (match_dup 1)))] 805: "" 806: "nor. %0,%2,%1" 807: [(set_attr "type" "compare")]) 808: 809: (define_insn "" 810: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 811: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 812: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 813: "! TARGET_POWERPC" 1.1.1.2 root 814: "{sf%I1|subf%I1c} %0,%2,%1") 1.1 root 815: 816: (define_insn "" 1.1.1.3 ! root 817: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 818: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") ! 819: (match_operand:SI 2 "gpc_reg_operand" "r,r")))] ! 820: "TARGET_POWERPC" ! 821: "@ ! 822: subf %0,%2,%1 ! 823: subfic %0,%2,%1") ! 824: ! 825: (define_insn "" 1.1 root 826: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 827: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 828: (match_operand:SI 2 "gpc_reg_operand" "r")) 829: (const_int 0))) 830: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 ! root 831: "! TARGET_POWERPC" 1.1.1.2 root 832: "{sf.|subfc.} %3,%2,%1" 1.1 root 833: [(set_attr "type" "compare")]) 834: 835: (define_insn "" 1.1.1.3 ! root 836: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 837: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 838: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 839: (const_int 0))) ! 840: (clobber (match_scratch:SI 3 "=r"))] ! 841: "TARGET_POWERPC" ! 842: "subf. %3,%2,%1" ! 843: [(set_attr "type" "compare")]) ! 844: ! 845: (define_insn "" 1.1 root 846: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 847: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 848: (match_operand:SI 2 "gpc_reg_operand" "r")) 849: (const_int 0))) 850: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 851: (minus:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 ! root 852: "! TARGET_POWERPC" 1.1.1.2 root 853: "{sf.|subfc.} %0,%2,%1" 1.1 root 854: [(set_attr "type" "compare")]) 855: 1.1.1.3 ! root 856: (define_insn "" ! 857: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 858: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 859: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 860: (const_int 0))) ! 861: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 862: (minus:SI (match_dup 1) (match_dup 2)))] ! 863: "TARGET_POWERPC" ! 864: "subf. %0,%2,%1" ! 865: [(set_attr "type" "compare")]) ! 866: 1.1 root 867: (define_expand "subsi3" 868: [(set (match_operand:SI 0 "gpc_reg_operand" "") 869: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") 870: (match_operand:SI 2 "reg_or_cint_operand" "")))] 871: "" 872: " 873: { 874: if (GET_CODE (operands[2]) == CONST_INT) 875: { 876: emit_insn (gen_addsi3 (operands[0], operands[1], 877: negate_rtx (SImode, operands[2]))); 878: DONE; 879: } 880: }") 881: 882: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 883: ;; instruction and some auxiliary computations. Then we just have a single 884: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 885: ;; combine. 886: 887: (define_expand "sminsi3" 888: [(set (match_dup 3) 889: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 890: (match_operand:SI 2 "reg_or_short_operand" "")) 891: (const_int 0) 892: (minus:SI (match_dup 2) (match_dup 1)))) 893: (set (match_operand:SI 0 "gpc_reg_operand" "") 894: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 895: "TARGET_POWER" 1.1 root 896: " 897: { operands[3] = gen_reg_rtx (SImode); }") 898: 899: (define_split 900: [(set (match_operand:SI 0 "gpc_reg_operand" "") 901: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 902: (match_operand:SI 2 "reg_or_short_operand" ""))) 903: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 904: "TARGET_POWER" 1.1 root 905: [(set (match_dup 3) 906: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 907: (const_int 0) 908: (minus:SI (match_dup 2) (match_dup 1)))) 909: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 910: "") 911: 912: (define_expand "smaxsi3" 913: [(set (match_dup 3) 914: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 915: (match_operand:SI 2 "reg_or_short_operand" "")) 916: (const_int 0) 917: (minus:SI (match_dup 2) (match_dup 1)))) 918: (set (match_operand:SI 0 "gpc_reg_operand" "") 919: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 920: "TARGET_POWER" 1.1 root 921: " 922: { operands[3] = gen_reg_rtx (SImode); }") 923: 924: (define_split 925: [(set (match_operand:SI 0 "gpc_reg_operand" "") 926: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 927: (match_operand:SI 2 "reg_or_short_operand" ""))) 928: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 929: "TARGET_POWER" 1.1 root 930: [(set (match_dup 3) 931: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 932: (const_int 0) 933: (minus:SI (match_dup 2) (match_dup 1)))) 934: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 935: "") 936: 937: (define_expand "uminsi3" 938: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 939: (const_int -2147483648))) 940: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 941: (const_int -2147483648))) 942: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 943: (const_int 0) 944: (minus:SI (match_dup 4) (match_dup 3)))) 945: (set (match_operand:SI 0 "gpc_reg_operand" "") 946: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 947: "TARGET_POWER" 1.1 root 948: " 949: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") 950: 951: (define_expand "umaxsi3" 952: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 953: (const_int -2147483648))) 954: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 955: (const_int -2147483648))) 956: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 957: (const_int 0) 958: (minus:SI (match_dup 4) (match_dup 3)))) 959: (set (match_operand:SI 0 "gpc_reg_operand" "") 960: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 961: "TARGET_POWER" 1.1 root 962: " 963: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") 964: 965: (define_insn "" 966: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 967: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 968: (match_operand:SI 2 "reg_or_short_operand" "rI")) 969: (const_int 0) 970: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 971: "TARGET_POWER" 1.1 root 972: "doz%I2 %0,%1,%2") 973: 974: (define_insn "" 975: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 976: (compare:CC 977: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 978: (match_operand:SI 2 "reg_or_short_operand" "rI")) 979: (const_int 0) 980: (minus:SI (match_dup 2) (match_dup 1))) 981: (const_int 0))) 982: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 983: "TARGET_POWER" 1.1 root 984: "doz%I2. %3,%1,%2" 985: [(set_attr "type" "delayed_compare")]) 986: 987: (define_insn "" 988: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 989: (compare:CC 990: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 991: (match_operand:SI 2 "reg_or_short_operand" "rI")) 992: (const_int 0) 993: (minus:SI (match_dup 2) (match_dup 1))) 994: (const_int 0))) 995: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 996: (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 997: (const_int 0) 998: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 999: "TARGET_POWER" 1.1 root 1000: "doz%I2. %0,%1,%2" 1001: [(set_attr "type" "delayed_compare")]) 1002: 1003: ;; We don't need abs with condition code because such comparisons should 1004: ;; never be done. 1005: (define_insn "abssi2" 1006: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1007: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.2 root 1008: "TARGET_POWER" 1.1 root 1009: "abs %0,%1") 1010: 1011: (define_insn "" 1012: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1013: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1014: "TARGET_POWER" 1.1 root 1015: "nabs %0,%1") 1016: 1017: (define_insn "negsi2" 1018: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1019: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1020: "" 1021: "neg %0,%1") 1022: 1023: (define_insn "" 1024: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1025: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1026: (const_int 0))) 1027: (clobber (match_scratch:SI 2 "=r"))] 1028: "" 1029: "neg. %2,%1" 1030: [(set_attr "type" "compare")]) 1031: 1032: (define_insn "" 1033: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1034: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1035: (const_int 0))) 1036: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1037: (neg:SI (match_dup 1)))] 1038: "" 1039: "neg. %0,%1" 1040: [(set_attr "type" "compare")]) 1041: 1042: (define_insn "ffssi2" 1043: [(set (match_operand:SI 0 "register_operand" "=&r") 1044: (ffs:SI (match_operand:SI 1 "register_operand" "r")))] 1045: "" 1.1.1.2 root 1046: "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" 1047: [(set_attr "length" "16")]) 1048: 1049: (define_expand "mulsi3" 1050: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1051: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1052: (use (match_operand:SI 2 "reg_or_short_operand" ""))] 1053: "" 1054: " 1055: { 1056: if (TARGET_POWER) 1057: emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 1058: else 1059: emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 1060: DONE; 1061: }") 1.1 root 1062: 1.1.1.2 root 1063: (define_insn "mulsi3_mq" 1.1 root 1064: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1065: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1066: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 1067: (clobber (match_scratch:SI 3 "=q,q"))] 1.1.1.2 root 1068: "TARGET_POWER" 1.1 root 1069: "@ 1.1.1.2 root 1070: {muls|mullw} %0,%1,%2 1071: {muli|mulli} %0,%1,%2" 1072: [(set_attr "type" "imul")]) 1073: 1074: (define_insn "mulsi3_no_mq" 1075: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1076: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1077: (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 1078: "! TARGET_POWER" 1079: "@ 1080: mullw %0,%1,%2 1081: mulli %0,%1,%2" 1082: [(set_attr "type" "imul")]) 1.1 root 1083: 1084: (define_insn "" 1085: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1086: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1087: (match_operand:SI 2 "gpc_reg_operand" "r")) 1088: (const_int 0))) 1089: (clobber (match_scratch:SI 3 "=r")) 1090: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1091: "TARGET_POWER" 1092: "{muls.|mullw.} %3,%1,%2" 1093: [(set_attr "type" "delayed_compare")]) 1094: 1095: (define_insn "" 1096: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1097: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1098: (match_operand:SI 2 "gpc_reg_operand" "r")) 1099: (const_int 0))) 1100: (clobber (match_scratch:SI 3 "=r"))] 1101: "! TARGET_POWER" 1102: "mullw. %3,%1,%2" 1.1 root 1103: [(set_attr "type" "delayed_compare")]) 1104: 1105: (define_insn "" 1106: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1107: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1108: (match_operand:SI 2 "gpc_reg_operand" "r")) 1109: (const_int 0))) 1110: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1111: (mult:SI (match_dup 1) (match_dup 2))) 1112: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1113: "TARGET_POWER" 1114: "{muls.|mullw.} %0,%1,%2" 1115: [(set_attr "type" "delayed_compare")]) 1116: 1117: (define_insn "" 1118: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1119: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1120: (match_operand:SI 2 "gpc_reg_operand" "r")) 1121: (const_int 0))) 1122: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1123: (mult:SI (match_dup 1) (match_dup 2)))] 1124: "! TARGET_POWER" 1125: "mullw. %0,%1,%2" 1.1 root 1126: [(set_attr "type" "delayed_compare")]) 1127: 1128: ;; Operand 1 is divided by operand 2; quotient goes to operand 1129: ;; 0 and remainder to operand 3. 1130: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 1131: 1.1.1.3 ! root 1132: (define_expand "divmodsi4" ! 1133: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1134: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1135: (match_operand:SI 2 "gpc_reg_operand" ""))) ! 1136: (set (match_operand:SI 3 "gpc_reg_operand" "") ! 1137: (mod:SI (match_dup 1) (match_dup 2)))])] ! 1138: "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" ! 1139: " ! 1140: { ! 1141: if (! TARGET_POWER && ! TARGET_POWERPC) ! 1142: { ! 1143: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 1144: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 1145: emit_insn (gen_divss_call ()); ! 1146: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); ! 1147: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); ! 1148: DONE; ! 1149: } ! 1150: }") ! 1151: ! 1152: (define_insn "" 1.1 root 1153: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1154: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1155: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1156: (set (match_operand:SI 3 "gpc_reg_operand" "=q") 1157: (mod:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 1158: "TARGET_POWER" 1159: "divs %0,%1,%2" 1160: [(set_attr "type" "idiv")]) 1161: 1162: (define_insn "" 1163: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1164: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1165: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1166: "TARGET_POWERPC" 1.1.1.3 ! root 1167: "divw %0,%1,%2" 1.1.1.2 root 1168: [(set_attr "type" "idiv")]) 1169: 1.1.1.3 ! root 1170: (define_expand "udivsi3" ! 1171: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1172: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1173: (match_operand:SI 2 "gpc_reg_operand" "")))] ! 1174: "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" ! 1175: " ! 1176: { ! 1177: if (! TARGET_POWER && ! TARGET_POWERPC) ! 1178: { ! 1179: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 1180: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 1181: emit_insn (gen_quous_call ()); ! 1182: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); ! 1183: DONE; ! 1184: } ! 1185: }") ! 1186: ! 1187: (define_insn "" 1.1.1.2 root 1188: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1189: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1190: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1191: "TARGET_POWERPC" 1.1.1.3 ! root 1192: "divwu %0,%1,%2" 1.1.1.2 root 1193: [(set_attr "type" "idiv")]) 1.1 root 1194: 1195: ;; For powers of two we can do srai/aze for divide and then adjust for 1.1.1.2 root 1196: ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 1.1.1.3 ! root 1197: ;; used; for PowerPC, force operands into register and do a normal divide; ! 1198: ;; for AIX common-mode, use quoss call on register operands. 1.1 root 1199: (define_expand "divsi3" 1200: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1201: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1202: (match_operand:SI 2 "reg_or_cint_operand" "")))] 1203: "" 1204: " 1205: { 1.1.1.2 root 1206: if (GET_CODE (operands[2]) == CONST_INT 1207: && exact_log2 (INTVAL (operands[2])) >= 0) 1208: ; 1.1.1.3 ! root 1209: else if (TARGET_POWER && ! TARGET_POWERPC) 1.1 root 1210: FAIL; 1.1.1.2 root 1211: else 1212: operands[2] = force_reg (SImode, operands[2]); 1.1.1.3 ! root 1213: ! 1214: if (! TARGET_POWER && ! TARGET_POWERPC) ! 1215: { ! 1216: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 1217: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 1218: emit_insn (gen_quoss_call ()); ! 1219: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); ! 1220: DONE; ! 1221: } 1.1 root 1222: }") 1223: 1224: (define_expand "modsi3" 1.1.1.2 root 1225: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1226: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1227: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 1.1 root 1228: "" 1229: " 1230: { 1231: int i = exact_log2 (INTVAL (operands[2])); 1.1.1.2 root 1232: rtx temp1; 1233: rtx temp2; 1.1 root 1234: 1235: if (GET_CODE (operands[2]) != CONST_INT || i < 0) 1236: FAIL; 1237: 1.1.1.2 root 1238: temp1 = gen_reg_rtx (SImode); 1239: temp2 = gen_reg_rtx (SImode); 1240: 1241: emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); 1242: emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); 1243: emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); 1244: DONE; 1.1 root 1245: }") 1246: 1247: (define_insn "" 1248: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1249: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1250: (match_operand:SI 2 "const_int_operand" "N")))] 1251: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1252: "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" 1253: [(set_attr "length" "8")]) 1.1 root 1254: 1255: (define_insn "" 1256: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1257: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1258: (match_operand:SI 2 "const_int_operand" "N")) ! 1259: (const_int 0))) 1.1 root 1260: (clobber (match_scratch:SI 3 "=r"))] 1261: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1262: "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" 1263: [(set_attr "type" "compare") 1264: (set_attr "length" "8")]) 1.1 root 1265: 1266: (define_insn "" 1267: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1268: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1269: (match_operand:SI 2 "const_int_operand" "N")) ! 1270: (const_int 0))) 1.1 root 1271: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1272: (div:SI (match_dup 1) (match_dup 2)))] 1273: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1274: "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" 1275: [(set_attr "type" "compare") 1276: (set_attr "length" "8")]) 1.1 root 1277: 1278: (define_insn "" 1279: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1280: (udiv:SI 1.1.1.3 ! root 1281: (plus:DI (ashift:DI 1.1 root 1282: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1283: (const_int 32)) 1284: (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 1285: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1286: (set (match_operand:SI 2 "register_operand" "=*q") 1287: (umod:SI 1.1.1.3 ! root 1288: (plus:DI (ashift:DI 1.1 root 1289: (zero_extend:DI (match_dup 1)) (const_int 32)) 1290: (zero_extend:DI (match_dup 4))) 1291: (match_dup 3)))] 1.1.1.2 root 1292: "TARGET_POWER" 1293: "div %0,%1,%3" 1294: [(set_attr "type" "idiv")]) 1.1 root 1295: 1296: ;; To do unsigned divide we handle the cases of the divisor looking like a 1297: ;; negative number. If it is a constant that is less than 2**31, we don't 1298: ;; have to worry about the branches. So make a few subroutines here. 1299: ;; 1300: ;; First comes the normal case. 1301: (define_expand "udivmodsi4_normal" 1302: [(set (match_dup 4) (const_int 0)) 1303: (parallel [(set (match_operand:SI 0 "" "") 1.1.1.3 ! root 1304: (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1305: (const_int 32)) 1306: (zero_extend:DI (match_operand:SI 1 "" ""))) 1307: (match_operand:SI 2 "" ""))) 1308: (set (match_operand:SI 3 "" "") 1.1.1.3 ! root 1309: (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1310: (const_int 32)) 1311: (zero_extend:DI (match_dup 1))) 1312: (match_dup 2)))])] 1.1.1.2 root 1313: "TARGET_POWER" 1.1 root 1314: " 1315: { operands[4] = gen_reg_rtx (SImode); }") 1316: 1317: ;; This handles the branches. 1318: (define_expand "udivmodsi4_tests" 1319: [(set (match_operand:SI 0 "" "") (const_int 0)) 1320: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 1321: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 1322: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 1323: (label_ref (match_operand:SI 4 "" "")) (pc))) 1324: (set (match_dup 0) (const_int 1)) 1325: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 1326: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 1327: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 1328: (label_ref (match_dup 4)) (pc)))] 1.1.1.2 root 1329: "TARGET_POWER" 1.1 root 1330: " 1331: { operands[5] = gen_reg_rtx (CCUNSmode); 1332: operands[6] = gen_reg_rtx (CCmode); 1333: }") 1334: 1335: (define_expand "udivmodsi4" 1336: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1337: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1338: (match_operand:SI 2 "reg_or_cint_operand" ""))) 1339: (set (match_operand:SI 3 "gpc_reg_operand" "") 1340: (umod:SI (match_dup 1) (match_dup 2)))])] 1.1.1.3 ! root 1341: "" 1.1 root 1342: " 1343: { 1344: rtx label = 0; 1345: 1.1.1.3 ! root 1346: if (! TARGET_POWER) ! 1347: if (! TARGET_POWERPC) ! 1348: { ! 1349: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 1350: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 1351: emit_insn (gen_divus_call ()); ! 1352: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); ! 1353: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); ! 1354: DONE; ! 1355: } ! 1356: else ! 1357: FAIL; ! 1358: 1.1 root 1359: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 1360: { 1361: operands[2] = force_reg (SImode, operands[2]); 1362: label = gen_label_rtx (); 1363: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 1364: operands[3], label)); 1365: } 1366: else 1367: operands[2] = force_reg (SImode, operands[2]); 1368: 1369: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 1370: operands[3])); 1371: if (label) 1372: emit_label (label); 1373: 1374: DONE; 1375: }") 1.1.1.3 ! root 1376: ! 1377: ;; AIX architecture-independent common-mode multiply (DImode), ! 1378: ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and ! 1379: ;; R4; results in R3 and somtimes R4; link register always clobbered by bla ! 1380: ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but ! 1381: ;; assumed unused if generating common-mode, so ignore. ! 1382: (define_insn "mulh_call" ! 1383: [(set (reg:SI 3) ! 1384: (truncate:SI ! 1385: (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) ! 1386: (sign_extend:DI (reg:SI 4))) ! 1387: (const_int 32)))) ! 1388: (clobber (match_scratch:SI 0 "=l"))] ! 1389: "! TARGET_POWER && ! TARGET_POWERPC" ! 1390: "bla __mulh") ! 1391: ! 1392: (define_insn "mull_call" ! 1393: [(set (reg:DI 3) ! 1394: (mult:DI (sign_extend:DI (reg:SI 3)) ! 1395: (sign_extend:DI (reg:SI 4)))) ! 1396: (clobber (match_scratch:SI 0 "=l")) ! 1397: (clobber (reg:SI 0))] ! 1398: "! TARGET_POWER && ! TARGET_POWERPC" ! 1399: "bla __mull") ! 1400: ! 1401: (define_insn "divss_call" ! 1402: [(set (reg:SI 3) ! 1403: (div:SI (reg:SI 3) (reg:SI 4))) ! 1404: (set (reg:SI 4) ! 1405: (mod:SI (reg:SI 3) (reg:SI 4))) ! 1406: (clobber (match_scratch:SI 0 "=l")) ! 1407: (clobber (reg:SI 0))] ! 1408: "! TARGET_POWER && ! TARGET_POWERPC" ! 1409: "bla __divss") ! 1410: ! 1411: (define_insn "divus_call" ! 1412: [(set (reg:SI 3) ! 1413: (udiv:SI (reg:SI 3) (reg:SI 4))) ! 1414: (set (reg:SI 4) ! 1415: (umod:SI (reg:SI 3) (reg:SI 4))) ! 1416: (clobber (match_scratch:SI 0 "=l")) ! 1417: (clobber (reg:SI 0))] ! 1418: "! TARGET_POWER && ! TARGET_POWERPC" ! 1419: "bla __divus") ! 1420: ! 1421: (define_insn "quoss_call" ! 1422: [(set (reg:SI 3) ! 1423: (div:SI (reg:SI 3) (reg:SI 4))) ! 1424: (clobber (match_scratch:SI 0 "=l"))] ! 1425: "! TARGET_POWER && ! TARGET_POWERPC" ! 1426: "bla __quoss") ! 1427: ! 1428: (define_insn "quous_call" ! 1429: [(set (reg:SI 3) ! 1430: (udiv:SI (reg:SI 3) (reg:SI 4))) ! 1431: (clobber (match_scratch:SI 0 "=l")) ! 1432: (clobber (reg:SI 0))] ! 1433: "! TARGET_POWER && ! TARGET_POWERPC" ! 1434: "bla __quous") ! 1435: 1.1 root 1436: (define_insn "andsi3" 1437: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1438: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1439: (match_operand:SI 2 "and_operand" "?r,L,K,J"))) 1440: (clobber (match_scratch:CC 3 "=X,X,x,x"))] 1441: "" 1442: "@ 1443: and %0,%1,%2 1.1.1.2 root 1444: {rlinm|rlwinm} %0,%1,0,%m2,%M2 1445: {andil.|andi.} %0,%1,%b2 1446: {andiu.|andis.} %0,%1,%u2") 1.1 root 1447: 1448: (define_insn "" 1449: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") 1450: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1451: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1452: (const_int 0))) 1453: (clobber (match_scratch:SI 3 "=r,r,r,r"))] 1454: "" 1455: "@ 1456: and. %3,%1,%2 1.1.1.2 root 1457: {andil.|andi.} %3,%1,%b2 1458: {andiu.|andis.} %3,%1,%u2 1459: {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" 1.1 root 1460: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1461: 1462: (define_insn "" 1463: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") 1464: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1465: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1466: (const_int 0))) 1467: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1468: (and:SI (match_dup 1) (match_dup 2)))] 1469: "" 1470: "@ 1471: and. %0,%1,%2 1.1.1.2 root 1472: {andil.|andi.} %0,%1,%b2 1473: {andiu.|andis.} %0,%1,%u2 1474: {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" 1475: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1.1 root 1476: 1477: ;; Take a AND with a constant that cannot be done in a single insn and try to 1478: ;; split it into two insns. This does not verify that the insns are valid 1479: ;; since this need not be done as combine will do it. 1480: 1481: (define_split 1482: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1483: (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1484: (match_operand:SI 2 "non_and_cint_operand" "")))] 1485: "" 1486: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) 1487: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] 1488: " 1489: { 1490: int maskval = INTVAL (operands[2]); 1491: int i, transitions, last_bit_value; 1492: int orig = maskval, first_c = maskval, second_c; 1493: 1494: /* We know that MASKVAL must have more than 2 bit-transitions. Start at 1495: the low-order bit and count for the third transition. When we get there, 1496: make a first mask that has everything to the left of that position 1497: a one. Then make the second mask to turn off whatever else is needed. */ 1498: 1499: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) 1500: { 1501: if (((maskval >>= 1) & 1) != last_bit_value) 1502: last_bit_value ^= 1, transitions++; 1503: 1504: if (transitions > 2) 1505: { 1506: first_c |= (~0) << i; 1507: break; 1508: } 1509: } 1510: 1511: second_c = orig | ~ first_c; 1512: 1513: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); 1514: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); 1515: }") 1516: 1517: (define_insn "iorsi3" 1518: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1519: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1520: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1521: "" 1522: "@ 1523: or %0,%1,%2 1.1.1.2 root 1524: {oril|ori} %0,%1,%b2 1525: {oriu|oris} %0,%1,%u2") 1.1 root 1526: 1527: (define_insn "" 1528: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1529: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1530: (match_operand:SI 2 "gpc_reg_operand" "r")) 1531: (const_int 0))) 1532: (clobber (match_scratch:SI 3 "=r"))] 1533: "" 1534: "or. %3,%1,%2" 1535: [(set_attr "type" "compare")]) 1536: 1537: (define_insn "" 1538: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1539: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1540: (match_operand:SI 2 "gpc_reg_operand" "r")) 1541: (const_int 0))) 1542: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1543: (ior:SI (match_dup 1) (match_dup 2)))] 1544: "" 1545: "or. %0,%1,%2" 1546: [(set_attr "type" "compare")]) 1547: 1548: ;; Split an IOR that we can't do in one insn into two insns, each of which 1549: ;; does one 16-bit part. This is used by combine. 1550: 1551: (define_split 1552: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1553: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 1554: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1555: "" 1556: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) 1557: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] 1558: " 1559: { 1560: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1561: INTVAL (operands[2]) & 0xffff0000); 1562: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1563: }") 1564: 1565: (define_insn "xorsi3" 1566: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1567: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1568: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1569: "" 1570: "@ 1571: xor %0,%1,%2 1.1.1.2 root 1572: {xoril|xori} %0,%1,%b2 1573: {xoriu|xoris} %0,%1,%u2") 1.1 root 1574: 1575: (define_insn "" 1576: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1577: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1578: (match_operand:SI 2 "gpc_reg_operand" "r")) 1579: (const_int 0))) 1580: (clobber (match_scratch:SI 3 "=r"))] 1581: "" 1582: "xor. %3,%1,%2" 1583: [(set_attr "type" "compare")]) 1584: 1585: (define_insn "" 1586: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1587: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1588: (match_operand:SI 2 "gpc_reg_operand" "r")) 1589: (const_int 0))) 1590: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1591: (xor:SI (match_dup 1) (match_dup 2)))] 1592: "" 1593: "xor. %0,%1,%2" 1594: [(set_attr "type" "compare")]) 1595: 1596: ;; Split an XOR that we can't do in one insn into two insns, each of which 1597: ;; does one 16-bit part. This is used by combine. 1598: 1599: (define_split 1600: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1601: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1602: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1603: "" 1604: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) 1605: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] 1606: " 1607: { 1608: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1609: INTVAL (operands[2]) & 0xffff0000); 1610: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1611: }") 1612: 1613: (define_insn "" 1614: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1615: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1616: (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1617: "" 1618: "eqv %0,%1,%2") 1619: 1620: (define_insn "" 1621: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1622: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1623: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1624: (const_int 0))) 1625: (clobber (match_scratch:SI 3 "=r"))] 1626: "" 1627: "eqv. %3,%1,%2" 1628: [(set_attr "type" "compare")]) 1629: 1630: (define_insn "" 1631: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1632: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1633: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1634: (const_int 0))) 1635: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1636: (not:SI (xor:SI (match_dup 1) (match_dup 2))))] 1637: "" 1638: "eqv. %0,%1,%2" 1639: [(set_attr "type" "compare")]) 1640: 1641: (define_insn "" 1642: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1643: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1644: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1645: "" 1646: "andc %0,%2,%1") 1647: 1648: (define_insn "" 1649: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1650: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1651: (match_operand:SI 2 "gpc_reg_operand" "r")) 1652: (const_int 0))) 1653: (clobber (match_scratch:SI 3 "=r"))] 1654: "" 1655: "andc. %3,%2,%1" 1656: [(set_attr "type" "compare")]) 1657: 1658: (define_insn "" 1659: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1660: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1661: (match_operand:SI 2 "gpc_reg_operand" "r")) 1662: (const_int 0))) 1663: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1664: (and:SI (not:SI (match_dup 1)) (match_dup 2)))] 1665: "" 1666: "andc. %0,%2,%1" 1667: [(set_attr "type" "compare")]) 1668: 1669: (define_insn "" 1670: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1671: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1672: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1673: "" 1674: "orc %0,%2,%1") 1675: 1676: (define_insn "" 1677: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1678: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1679: (match_operand:SI 2 "gpc_reg_operand" "r")) 1680: (const_int 0))) 1681: (clobber (match_scratch:SI 3 "=r"))] 1682: "" 1683: "orc. %3,%2,%1" 1684: [(set_attr "type" "compare")]) 1685: 1686: (define_insn "" 1687: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1688: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1689: (match_operand:SI 2 "gpc_reg_operand" "r")) 1690: (const_int 0))) 1691: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1692: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] 1693: "" 1694: "orc. %0,%2,%1" 1695: [(set_attr "type" "compare")]) 1696: 1697: (define_insn "" 1698: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 ! root 1699: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1700: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1701: "" 1702: "nand %0,%1,%2") 1703: 1704: (define_insn "" 1705: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1706: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1707: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1708: (const_int 0))) 1709: (clobber (match_scratch:SI 3 "=r"))] 1710: "" 1711: "nand. %3,%1,%2" 1712: [(set_attr "type" "compare")]) 1713: 1714: (define_insn "" 1715: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1716: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1717: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1718: (const_int 0))) 1719: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1720: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1721: "" 1722: "nand. %0,%1,%2" 1723: [(set_attr "type" "compare")]) 1724: 1725: (define_insn "" 1726: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 ! root 1727: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1728: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1729: "" 1730: "nor %0,%1,%2") 1731: 1732: (define_insn "" 1733: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 ! root 1734: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1735: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1736: (const_int 0))) 1737: (clobber (match_scratch:SI 3 "=r"))] 1738: "" 1739: "nor. %3,%1,%2" 1740: [(set_attr "type" "compare")]) 1741: 1742: (define_insn "" 1743: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 ! root 1744: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1745: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1746: (const_int 0))) 1747: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1748: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1749: "" 1750: "nor. %0,%1,%2" 1751: [(set_attr "type" "compare")]) 1752: 1753: ;; maskir insn. We need four forms because things might be in arbitrary 1754: ;; orders. Don't define forms that only set CR fields because these 1755: ;; would modify an input register. 1756: 1757: (define_insn "" 1758: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1759: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1760: (match_operand:SI 1 "gpc_reg_operand" "0")) 1761: (and:SI (match_dup 2) 1762: (match_operand:SI 3 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1763: "TARGET_POWER" 1.1 root 1764: "maskir %0,%3,%2") 1765: 1766: (define_insn "" 1767: [(set (match_operand:SI 0 "register_operand" "=r") 1768: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1769: (match_operand:SI 1 "gpc_reg_operand" "0")) 1770: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1771: (match_dup 2))))] 1.1.1.2 root 1772: "TARGET_POWER" 1.1 root 1773: "maskir %0,%3,%2") 1774: 1775: (define_insn "" 1776: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1777: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1778: (match_operand:SI 3 "gpc_reg_operand" "r")) 1779: (and:SI (not:SI (match_dup 2)) 1780: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1781: "TARGET_POWER" 1.1 root 1782: "maskir %0,%3,%2") 1783: 1784: (define_insn "" 1785: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1786: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1787: (match_operand:SI 2 "gpc_reg_operand" "r")) 1788: (and:SI (not:SI (match_dup 2)) 1789: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1790: "TARGET_POWER" 1.1 root 1791: "maskir %0,%3,%2") 1792: 1793: (define_insn "" 1794: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1795: (compare:CC 1796: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1797: (match_operand:SI 1 "gpc_reg_operand" "0")) 1798: (and:SI (match_dup 2) 1799: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1800: (const_int 0))) 1801: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1802: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1803: (and:SI (match_dup 2) (match_dup 3))))] 1.1.1.2 root 1804: "TARGET_POWER" 1.1 root 1805: "maskir. %0,%3,%2" 1806: [(set_attr "type" "compare")]) 1807: 1808: (define_insn "" 1809: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1810: (compare:CC 1811: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1812: (match_operand:SI 1 "gpc_reg_operand" "0")) 1813: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1814: (match_dup 2))) 1815: (const_int 0))) 1816: (set (match_operand:SI 0 "register_operand" "=r") 1817: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1818: (and:SI (match_dup 3) (match_dup 2))))] 1.1.1.2 root 1819: "TARGET_POWER" 1.1 root 1820: "maskir. %0,%3,%2" 1821: [(set_attr "type" "compare")]) 1822: 1823: (define_insn "" 1824: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1825: (compare:CC 1826: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1827: (match_operand:SI 3 "gpc_reg_operand" "r")) 1828: (and:SI (not:SI (match_dup 2)) 1829: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1830: (const_int 0))) 1831: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1832: (ior:SI (and:SI (match_dup 2) (match_dup 3)) 1833: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1834: "TARGET_POWER" 1.1 root 1835: "maskir. %0,%3,%2" 1836: [(set_attr "type" "compare")]) 1837: 1838: (define_insn "" 1839: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1840: (compare:CC 1841: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1842: (match_operand:SI 2 "gpc_reg_operand" "r")) 1843: (and:SI (not:SI (match_dup 2)) 1844: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1845: (const_int 0))) 1846: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1847: (ior:SI (and:SI (match_dup 3) (match_dup 2)) 1848: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1849: "TARGET_POWER" 1.1 root 1850: "maskir. %0,%3,%2" 1851: [(set_attr "type" "compare")]) 1852: 1853: ;; Rotate and shift insns, in all their variants. These support shifts, 1854: ;; field inserts and extracts, and various combinations thereof. 1855: (define_insn "insv" 1856: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1857: (match_operand:SI 1 "const_int_operand" "i") 1858: (match_operand:SI 2 "const_int_operand" "i")) 1859: (match_operand:SI 3 "gpc_reg_operand" "r"))] 1860: "" 1861: "* 1862: { 1863: int start = INTVAL (operands[2]) & 31; 1864: int size = INTVAL (operands[1]) & 31; 1865: 1866: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); 1867: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 1.1.1.2 root 1868: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 1.1 root 1869: }") 1870: 1871: (define_insn "extzv" 1872: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1873: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1874: (match_operand:SI 2 "const_int_operand" "i") 1875: (match_operand:SI 3 "const_int_operand" "i")))] 1876: "" 1877: "* 1878: { 1879: int start = INTVAL (operands[3]) & 31; 1880: int size = INTVAL (operands[2]) & 31; 1881: 1882: if (start + size >= 32) 1883: operands[3] = const0_rtx; 1884: else 1885: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 1886: return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 1.1 root 1887: }") 1888: 1889: (define_insn "" 1890: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1891: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1892: (match_operand:SI 2 "const_int_operand" "i") 1893: (match_operand:SI 3 "const_int_operand" "i")) 1894: (const_int 0))) 1895: (clobber (match_scratch:SI 4 "=r"))] 1896: "" 1897: "* 1898: { 1899: int start = INTVAL (operands[3]) & 31; 1900: int size = INTVAL (operands[2]) & 31; 1901: 1902: /* If the bitfield being tested fits in the upper or lower half of a 1903: word, it is possible to use andiu. or andil. to test it. This is 1904: useful because the condition register set-use delay is smaller for 1905: andi[ul]. than for rlinm. This doesn't work when the starting bit 1906: position is 0 because the LT and GT bits may be set wrong. */ 1907: 1908: if ((start > 0 && start + size <= 16) || start >= 16) 1909: { 1910: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1911: ((1 << (16 - (start & 15))) 1912: - (1 << (16 - (start & 15) - size)))); 1913: if (start < 16) 1.1.1.2 root 1914: return \"{andiu.|andis.} %4,%1,%3\"; 1.1 root 1915: else 1.1.1.2 root 1916: return \"{andil.|andi.} %4,%1,%3\"; 1.1 root 1917: } 1918: 1919: if (start + size >= 32) 1920: operands[3] = const0_rtx; 1921: else 1922: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 1923: return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 1.1 root 1924: }" 1925: [(set_attr "type" "compare")]) 1926: 1927: (define_insn "" 1928: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1929: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1930: (match_operand:SI 2 "const_int_operand" "i") 1931: (match_operand:SI 3 "const_int_operand" "i")) 1932: (const_int 0))) 1933: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1934: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 1935: "" 1936: "* 1937: { 1938: int start = INTVAL (operands[3]) & 31; 1939: int size = INTVAL (operands[2]) & 31; 1940: 1941: if (start >= 16 && start + size == 32) 1942: { 1943: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); 1.1.1.2 root 1944: return \"{andil.|andi.} %0,%1,%3\"; 1.1 root 1945: } 1946: 1947: if (start + size >= 32) 1948: operands[3] = const0_rtx; 1949: else 1950: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 1951: return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 1.1 root 1952: }" 1953: [(set_attr "type" "delayed_compare")]) 1954: 1955: (define_insn "rotlsi3" 1956: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1957: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1958: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 1959: "" 1.1.1.2 root 1960: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 1.1 root 1961: 1962: (define_insn "" 1963: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1964: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1965: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 1966: (const_int 0))) 1967: (clobber (match_scratch:SI 3 "=r"))] 1968: "" 1.1.1.2 root 1969: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" 1.1 root 1970: [(set_attr "type" "delayed_compare")]) 1971: 1972: (define_insn "" 1973: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1974: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1975: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 1976: (const_int 0))) 1977: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1978: (rotate:SI (match_dup 1) (match_dup 2)))] 1979: "" 1.1.1.2 root 1980: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" 1.1 root 1981: [(set_attr "type" "delayed_compare")]) 1982: 1983: (define_insn "" 1984: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1985: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1986: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 1987: (match_operand:SI 3 "mask_operand" "L")))] 1988: "" 1.1.1.2 root 1989: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 1.1 root 1990: 1991: (define_insn "" 1992: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1993: (compare:CC (and:SI 1994: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1995: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 1996: (match_operand:SI 3 "mask_operand" "L")) 1997: (const_int 0))) 1998: (clobber (match_scratch:SI 4 "=r"))] 1999: "" 1.1.1.2 root 2000: "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" 1.1 root 2001: [(set_attr "type" "delayed_compare")]) 2002: 2003: (define_insn "" 2004: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2005: (compare:CC (and:SI 2006: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2007: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2008: (match_operand:SI 3 "mask_operand" "L")) 2009: (const_int 0))) 2010: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2011: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2012: "" 1.1.1.2 root 2013: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" 1.1 root 2014: [(set_attr "type" "delayed_compare")]) 2015: 2016: (define_insn "" 2017: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2018: (zero_extend:SI 2019: (subreg:QI 2020: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2021: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2022: "" 1.1.1.2 root 2023: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 1.1 root 2024: 2025: (define_insn "" 2026: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2027: (compare:CC (zero_extend:SI 2028: (subreg:QI 2029: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2030: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2031: (const_int 0))) 2032: (clobber (match_scratch:SI 3 "=r"))] 2033: "" 1.1.1.2 root 2034: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" 1.1 root 2035: [(set_attr "type" "delayed_compare")]) 2036: 2037: (define_insn "" 2038: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2039: (compare:CC (zero_extend:SI 2040: (subreg:QI 2041: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2042: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2043: (const_int 0))) 2044: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2045: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2046: "" 1.1.1.2 root 2047: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" 1.1 root 2048: [(set_attr "type" "delayed_compare")]) 2049: 2050: (define_insn "" 2051: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2052: (zero_extend:SI 2053: (subreg:HI 2054: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2055: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2056: "" 1.1.1.2 root 2057: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 1.1 root 2058: 2059: (define_insn "" 2060: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2061: (compare:CC (zero_extend:SI 2062: (subreg:HI 2063: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2064: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2065: (const_int 0))) 2066: (clobber (match_scratch:SI 3 "=r"))] 2067: "" 1.1.1.2 root 2068: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" 1.1 root 2069: [(set_attr "type" "delayed_compare")]) 2070: 2071: (define_insn "" 2072: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2073: (compare:CC (zero_extend:SI 2074: (subreg:HI 2075: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2076: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2077: (const_int 0))) 2078: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2079: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2080: "" 1.1.1.2 root 2081: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" 1.1 root 2082: [(set_attr "type" "delayed_compare")]) 2083: 2084: ;; Note that we use "sle." instead of "sl." so that we can set 2085: ;; SHIFT_COUNT_TRUNCATED. 2086: 1.1.1.2 root 2087: (define_expand "ashlsi3" 2088: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2089: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2090: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2091: "" 2092: " 2093: { 2094: if (TARGET_POWER) 2095: emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 2096: else 2097: emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 2098: DONE; 2099: }") 2100: 2101: (define_insn "ashlsi3_power" 1.1 root 2102: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2103: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2104: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2105: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2106: "TARGET_POWER" 1.1 root 2107: "@ 2108: sle %0,%1,%2 1.1.1.2 root 2109: {sli|slwi} %0,%1,%h2" 2110: [(set_attr "length" "8")]) 2111: 2112: (define_insn "ashlsi3_no_power" 2113: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2114: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2115: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2116: "! TARGET_POWER" 1.1.1.3 ! root 2117: "slw%I2 %0,%1,%h2" 1.1.1.2 root 2118: [(set_attr "length" "8")]) 1.1 root 2119: 2120: (define_insn "" 2121: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2122: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2123: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2124: (const_int 0))) 2125: (clobber (match_scratch:SI 3 "=r,r")) 2126: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2127: "TARGET_POWER" 1.1 root 2128: "@ 2129: sle. %3,%1,%2 1.1.1.2 root 2130: {sli.|slwi.} %3,%1,%h2" 2131: [(set_attr "type" "delayed_compare")]) 2132: 2133: (define_insn "" 2134: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2135: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2136: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2137: (const_int 0))) 2138: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 ! root 2139: "! TARGET_POWER" ! 2140: "slw%I2. %3,%1,%h2" 1.1 root 2141: [(set_attr "type" "delayed_compare")]) 2142: 2143: (define_insn "" 2144: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2145: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2146: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2147: (const_int 0))) 2148: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2149: (ashift:SI (match_dup 1) (match_dup 2))) 2150: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2151: "TARGET_POWER" 1.1 root 2152: "@ 2153: sle. %0,%1,%2 1.1.1.2 root 2154: {sli.|slwi.} %0,%1,%h2" 2155: [(set_attr "type" "delayed_compare")]) 2156: 2157: (define_insn "" 2158: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2159: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2160: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2161: (const_int 0))) 2162: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2163: (ashift:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 ! root 2164: "! TARGET_POWER" ! 2165: "slw%I2. %0,%1,%h2" 1.1 root 2166: [(set_attr "type" "delayed_compare")]) 2167: 2168: (define_insn "" 2169: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2170: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2171: (match_operand:SI 2 "const_int_operand" "i")) 2172: (match_operand:SI 3 "mask_operand" "L")))] 2173: "includes_lshift_p (operands[2], operands[3])" 1.1.1.2 root 2174: "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3") 1.1 root 2175: 2176: (define_insn "" 2177: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2178: (compare:CC 2179: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2180: (match_operand:SI 2 "const_int_operand" "i")) 2181: (match_operand:SI 3 "mask_operand" "L")) 2182: (const_int 0))) 2183: (clobber (match_scratch:SI 4 "=r"))] 2184: "includes_lshift_p (operands[2], operands[3])" 1.1.1.2 root 2185: "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3" 1.1 root 2186: [(set_attr "type" "delayed_compare")]) 2187: 2188: (define_insn "" 2189: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2190: (compare:CC 2191: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2192: (match_operand:SI 2 "const_int_operand" "i")) 2193: (match_operand:SI 3 "mask_operand" "L")) 2194: (const_int 0))) 2195: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2196: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2197: "includes_lshift_p (operands[2], operands[3])" 1.1.1.2 root 2198: "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3" 1.1 root 2199: [(set_attr "type" "delayed_compare")]) 2200: 1.1.1.2 root 2201: ;; The AIX assembler mis-handles "sri x,x,0", so write that case as 1.1 root 2202: ;; "sli x,x,0". 1.1.1.2 root 2203: (define_expand "lshrsi3" 2204: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2205: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2206: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2207: "" 2208: " 2209: { 2210: if (TARGET_POWER) 2211: emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 2212: else 2213: emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 2214: DONE; 2215: }") 2216: 2217: (define_insn "lshrsi3_power" 1.1 root 2218: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2219: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2220: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2221: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2222: "TARGET_POWER" 1.1 root 2223: "@ 2224: sre %0,%1,%2 1.1.1.2 root 2225: {s%A2i|s%A2wi} %0,%1,%h2") 2226: 2227: (define_insn "lshrsi3_no_power" 2228: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2229: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2230: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2231: "! TARGET_POWER" 1.1.1.3 ! root 2232: "srw%I2 %0,%1,%h2") 1.1 root 2233: 2234: (define_insn "" 2235: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2236: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2237: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2238: (const_int 0))) 2239: (clobber (match_scratch:SI 3 "=r,r")) 2240: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2241: "TARGET_POWER" 1.1 root 2242: "@ 2243: sre. %3,%1,%2 1.1.1.2 root 2244: {s%A2i.|s%A2wi.} %3,%1,%h2" 2245: [(set_attr "type" "delayed_compare")]) 2246: 2247: (define_insn "" 2248: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2249: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2250: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2251: (const_int 0))) 2252: (clobber (match_scratch:SI 3 "=r"))] 2253: "! TARGET_POWER" 1.1.1.3 ! root 2254: "srw%I2. %3,%1,%h2" 1.1 root 2255: [(set_attr "type" "delayed_compare")]) 2256: 2257: (define_insn "" 2258: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2259: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2260: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2261: (const_int 0))) 2262: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2263: (lshiftrt:SI (match_dup 1) (match_dup 2))) 2264: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2265: "TARGET_POWER" 1.1 root 2266: "@ 2267: sre. %0,%1,%2 1.1.1.2 root 2268: {s%A2i.|s%A2wi.} %0,%1,%h2" 2269: [(set_attr "type" "delayed_compare")]) 2270: 2271: (define_insn "" 2272: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2273: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2274: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2275: (const_int 0))) 2276: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2277: (lshiftrt:SI (match_dup 1) (match_dup 2)))] 2278: "! TARGET_POWER" 1.1.1.3 ! root 2279: "srw%I2. %0,%1,%h2" 1.1 root 2280: [(set_attr "type" "delayed_compare")]) 2281: 2282: (define_insn "" 2283: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2284: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2285: (match_operand:SI 2 "const_int_operand" "i")) 2286: (match_operand:SI 3 "mask_operand" "L")))] 2287: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2288: "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 1.1 root 2289: 2290: (define_insn "" 2291: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2292: (compare:CC 2293: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2294: (match_operand:SI 2 "const_int_operand" "i")) 2295: (match_operand:SI 3 "mask_operand" "L")) 2296: (const_int 0))) 2297: (clobber (match_scratch:SI 4 "=r"))] 2298: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2299: "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" 1.1 root 2300: [(set_attr "type" "delayed_compare")]) 2301: 2302: (define_insn "" 2303: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2304: (compare:CC 2305: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2306: (match_operand:SI 2 "const_int_operand" "i")) 2307: (match_operand:SI 3 "mask_operand" "L")) 2308: (const_int 0))) 2309: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2310: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2311: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2312: "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" 1.1 root 2313: [(set_attr "type" "delayed_compare")]) 2314: 2315: (define_insn "" 2316: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2317: (zero_extend:SI 2318: (subreg:QI 2319: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2320: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2321: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2322: "{rlinm|rlwinm} %0,%1,%s2,0xff") 1.1 root 2323: 2324: (define_insn "" 2325: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2326: (compare:CC 2327: (zero_extend:SI 2328: (subreg:QI 2329: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2330: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2331: (const_int 0))) 2332: (clobber (match_scratch:SI 3 "=r"))] 2333: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2334: "{rlinm.|rlwinm.} %3,%1,%s2,0xff" 1.1 root 2335: [(set_attr "type" "delayed_compare")]) 2336: 2337: (define_insn "" 2338: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2339: (compare:CC 2340: (zero_extend:SI 2341: (subreg:QI 2342: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2343: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2344: (const_int 0))) 2345: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2346: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2347: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2348: "{rlinm.|rlwinm.} %0,%1,%s2,0xff" 1.1 root 2349: [(set_attr "type" "delayed_compare")]) 2350: 2351: (define_insn "" 2352: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2353: (zero_extend:SI 2354: (subreg:HI 2355: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2356: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2357: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2358: "{rlinm|rlwinm} %0,%1,%s2,0xffff") 1.1 root 2359: 2360: (define_insn "" 2361: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2362: (compare:CC 2363: (zero_extend:SI 2364: (subreg:HI 2365: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2366: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2367: (const_int 0))) 2368: (clobber (match_scratch:SI 3 "=r"))] 2369: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2370: "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" 1.1 root 2371: [(set_attr "type" "delayed_compare")]) 2372: 2373: (define_insn "" 2374: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2375: (compare:CC 2376: (zero_extend:SI 2377: (subreg:HI 2378: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2379: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2380: (const_int 0))) 2381: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2382: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2383: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2384: "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" 1.1 root 2385: [(set_attr "type" "delayed_compare")]) 2386: 2387: (define_insn "" 2388: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2389: (const_int 1) 2390: (match_operand:SI 1 "gpc_reg_operand" "r")) 2391: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2392: (const_int 31)))] 1.1.1.2 root 2393: "TARGET_POWER" 1.1 root 2394: "rrib %0,%1,%2") 2395: 2396: (define_insn "" 2397: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2398: (const_int 1) 2399: (match_operand:SI 1 "gpc_reg_operand" "r")) 2400: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2401: (const_int 31)))] 1.1.1.2 root 2402: "TARGET_POWER" 1.1 root 2403: "rrib %0,%1,%2") 2404: 2405: (define_insn "" 2406: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2407: (const_int 1) 2408: (match_operand:SI 1 "gpc_reg_operand" "r")) 2409: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2410: (const_int 1) 2411: (const_int 0)))] 1.1.1.2 root 2412: "TARGET_POWER" 1.1 root 2413: "rrib %0,%1,%2") 2414: 1.1.1.2 root 2415: (define_expand "ashrsi3" 2416: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2417: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 2418: (match_operand:SI 2 "reg_or_cint_operand" "")))] 2419: "" 2420: " 2421: { 2422: if (TARGET_POWER) 2423: emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 2424: else 2425: emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 2426: DONE; 2427: }") 2428: 2429: (define_insn "ashrsi3_power" 1.1 root 2430: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2431: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2432: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2433: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2434: "TARGET_POWER" 1.1 root 2435: "@ 2436: srea %0,%1,%2 1.1.1.2 root 2437: {srai|srawi} %0,%1,%h2") 2438: 2439: (define_insn "ashrsi3_no_power" 2440: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2441: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2442: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2443: "! TARGET_POWER" 1.1.1.3 ! root 2444: "sraw%I2 %0,%1,%h2") 1.1 root 2445: 2446: (define_insn "" 2447: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2448: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2449: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2450: (const_int 0))) 2451: (clobber (match_scratch:SI 3 "=r,r")) 2452: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2453: "TARGET_POWER" 1.1 root 2454: "@ 2455: srea. %3,%1,%2 1.1.1.2 root 2456: {srai.|srawi.} %3,%1,%h2" 2457: [(set_attr "type" "delayed_compare")]) 2458: 2459: (define_insn "" 2460: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2461: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2462: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2463: (const_int 0))) 2464: (clobber (match_scratch:SI 3 "=r"))] 2465: "! TARGET_POWER" 1.1.1.3 ! root 2466: "sraw%I2. %3,%1,%h2" 1.1 root 2467: [(set_attr "type" "delayed_compare")]) 2468: 2469: (define_insn "" 2470: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2471: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2472: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2473: (const_int 0))) 2474: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2475: (ashiftrt:SI (match_dup 1) (match_dup 2))) 2476: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2477: "TARGET_POWER" 1.1 root 2478: "@ 2479: srea. %0,%1,%2 1.1.1.2 root 2480: {srai.|srawi.} %0,%1,%h2" 2481: [(set_attr "type" "delayed_compare")]) 2482: 2483: (define_insn "" 2484: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2485: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2486: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2487: (const_int 0))) 2488: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2489: (ashiftrt:SI (match_dup 1) (match_dup 2)))] 2490: "! TARGET_POWER" 1.1.1.3 ! root 2491: "sraw%I2. %0,%1,%h2" 1.1 root 2492: [(set_attr "type" "delayed_compare")]) 2493: 2494: ;; Floating-point insns, excluding normal data motion. 2495: ;; 1.1.1.2 root 2496: ;; PowerPC has a full set of single-precision floating point instructions. 2497: ;; 2498: ;; For the POWER architecture, we pretend that we have both SFmode and 2499: ;; DFmode insns, while, in fact, all fp insns are actually done in double. 2500: ;; The only conversions we will do will be when storing to memory. In that 2501: ;; case, we will use the "frsp" instruction before storing. 1.1 root 2502: ;; 2503: ;; Note that when we store into a single-precision memory location, we need to 2504: ;; use the frsp insn first. If the register being stored isn't dead, we 2505: ;; need a scratch register for the frsp. But this is difficult when the store 2506: ;; is done by reload. It is not incorrect to do the frsp on the register in 2507: ;; this case, we just lose precision that we would have otherwise gotten but 2508: ;; is not guaranteed. Perhaps this should be tightened up at some point. 2509: 2510: (define_insn "extendsfdf2" 2511: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2512: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] 2513: "" 2514: "* 2515: { 2516: if (REGNO (operands[0]) == REGNO (operands[1])) 2517: return \"\"; 2518: else 2519: return \"fmr %0,%1\"; 2520: }" 2521: [(set_attr "type" "fp")]) 2522: 2523: (define_insn "truncdfsf2" 2524: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2525: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 2526: "" 1.1.1.2 root 2527: "frsp %0,%1" 1.1 root 2528: [(set_attr "type" "fp")]) 2529: 2530: (define_insn "negsf2" 2531: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2532: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 2533: "" 2534: "fneg %0,%1" 2535: [(set_attr "type" "fp")]) 2536: 2537: (define_insn "abssf2" 2538: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2539: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 2540: "" 2541: "fabs %0,%1" 2542: [(set_attr "type" "fp")]) 2543: 2544: (define_insn "" 2545: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2546: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 2547: "" 2548: "fnabs %0,%1" 2549: [(set_attr "type" "fp")]) 2550: 1.1.1.2 root 2551: (define_expand "addsf3" 2552: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2553: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2554: (match_operand:SF 2 "gpc_reg_operand" "")))] 2555: "" 2556: "") 2557: 2558: (define_insn "" 2559: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2560: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2561: (match_operand:SF 2 "gpc_reg_operand" "f")))] 2562: "TARGET_POWERPC" 2563: "fadds %0,%1,%2" 2564: [(set_attr "type" "fp")]) 2565: 2566: (define_insn "" 1.1 root 2567: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2568: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2569: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2570: "! TARGET_POWERPC" 1.1.1.2 root 2571: "{fa|fadd} %0,%1,%2" 2572: [(set_attr "type" "fp")]) 2573: 2574: (define_expand "subsf3" 2575: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2576: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2577: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1 root 2578: "" 1.1.1.2 root 2579: "") 2580: 2581: (define_insn "" 2582: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2583: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2584: (match_operand:SF 2 "gpc_reg_operand" "f")))] 2585: "TARGET_POWERPC" 2586: "fsubs %0,%1,%2" 1.1 root 2587: [(set_attr "type" "fp")]) 2588: 1.1.1.2 root 2589: (define_insn "" 1.1 root 2590: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2591: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2592: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2593: "! TARGET_POWERPC" 1.1.1.2 root 2594: "{fs|fsub} %0,%1,%2" 2595: [(set_attr "type" "fp")]) 2596: 2597: (define_expand "mulsf3" 2598: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2599: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 2600: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1 root 2601: "" 1.1.1.2 root 2602: "") 2603: 2604: (define_insn "" 2605: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2606: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2607: (match_operand:SF 2 "gpc_reg_operand" "f")))] 2608: "TARGET_POWERPC" 2609: "fmuls %0,%1,%2" 1.1 root 2610: [(set_attr "type" "fp")]) 2611: 1.1.1.2 root 2612: (define_insn "" 1.1 root 2613: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2614: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2615: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2616: "! TARGET_POWERPC" 1.1.1.2 root 2617: "{fm|fmul} %0,%1,%2" 1.1 root 2618: [(set_attr "type" "fp")]) 2619: 1.1.1.2 root 2620: (define_expand "divsf3" 2621: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2622: (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 2623: (match_operand:SF 2 "gpc_reg_operand" "")))] 2624: "" 2625: "") 2626: 2627: (define_insn "" 1.1 root 2628: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2629: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2630: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.2 root 2631: "TARGET_POWERPC" 2632: "fdivs %0,%1,%2" 2633: [(set_attr "type" "sdiv")]) 2634: 2635: (define_insn "" 2636: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2637: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2638: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2639: "! TARGET_POWERPC" 1.1.1.2 root 2640: "{fd|fdiv} %0,%1,%2" 2641: [(set_attr "type" "sdiv")]) 2642: 2643: (define_insn "" 2644: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2645: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2646: (match_operand:SF 2 "gpc_reg_operand" "f")) 2647: (match_operand:SF 3 "gpc_reg_operand" "f")))] 2648: "TARGET_POWERPC" 2649: "fmadds %0,%1,%2,%3" 1.1 root 2650: [(set_attr "type" "fp")]) 2651: 2652: (define_insn "" 2653: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2654: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2655: (match_operand:SF 2 "gpc_reg_operand" "f")) 2656: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2657: "! TARGET_POWERPC" 1.1.1.2 root 2658: "{fma|fmadd} %0,%1,%2,%3" 1.1 root 2659: [(set_attr "type" "fp")]) 2660: 2661: (define_insn "" 2662: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2663: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2664: (match_operand:SF 2 "gpc_reg_operand" "f")) 2665: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.2 root 2666: "TARGET_POWERPC" 2667: "fmsubs %0,%1,%2,%3" 2668: [(set_attr "type" "fp")]) 2669: 2670: (define_insn "" 2671: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2672: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2673: (match_operand:SF 2 "gpc_reg_operand" "f")) 2674: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2675: "! TARGET_POWERPC" 1.1.1.2 root 2676: "{fms|fmsub} %0,%1,%2,%3" 1.1 root 2677: [(set_attr "type" "fp")]) 2678: 2679: (define_insn "" 2680: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2681: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2682: (match_operand:SF 2 "gpc_reg_operand" "f")) 2683: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.2 root 2684: "TARGET_POWERPC" 2685: "fnmadds %0,%1,%2,%3" 2686: [(set_attr "type" "fp")]) 2687: 2688: (define_insn "" 2689: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2690: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2691: (match_operand:SF 2 "gpc_reg_operand" "f")) 2692: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.3 ! root 2693: "! TARGET_POWERPC" 1.1.1.2 root 2694: "{fnma|fnmadd} %0,%1,%2,%3" 1.1 root 2695: [(set_attr "type" "fp")]) 2696: 2697: (define_insn "" 2698: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2699: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2700: (match_operand:SF 2 "gpc_reg_operand" "f")) 2701: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.2 root 2702: "TARGET_POWERPC" 2703: "fnmsubs %0,%1,%2,%3" 2704: [(set_attr "type" "fp")]) 2705: 2706: (define_insn "" 2707: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2708: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2709: (match_operand:SF 2 "gpc_reg_operand" "f")) 2710: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.3 ! root 2711: "! TARGET_POWERPC" 1.1.1.2 root 2712: "{fnms|fnmsub} %0,%1,%2,%3" 1.1 root 2713: [(set_attr "type" "fp")]) 2714: 1.1.1.2 root 2715: (define_expand "sqrtsf2" 2716: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2717: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.3 ! root 2718: "TARGET_PPC_GPOPT || TARGET_POWER2" 1.1.1.2 root 2719: "") 2720: 2721: (define_insn "" 2722: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2723: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2724: "TARGET_PPC_GPOPT" 1.1.1.2 root 2725: "fsqrts %0,%1" 2726: [(set_attr "type" "ssqrt")]) 2727: 2728: (define_insn "" 2729: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2730: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 2731: "TARGET_POWER2" 2732: "fsqrt %0,%1" 2733: [(set_attr "type" "dsqrt")]) 2734: 1.1.1.3 ! root 2735: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel ! 2736: ;; instruction and some auxiliary computations. Then we just have a single ! 2737: ;; DEFINE_INSN for fsel and the define_splits to make them if made by ! 2738: ;; combine. ! 2739: (define_expand "maxsf3" ! 2740: [(set (match_dup 3) ! 2741: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2742: (match_operand:SF 2 "gpc_reg_operand" ""))) ! 2743: (set (match_operand:SF 0 "gpc_reg_operand" "") ! 2744: (if_then_else:SF (ge (match_dup 3) ! 2745: (const_int 0)) ! 2746: (match_dup 1) ! 2747: (match_dup 2)))] ! 2748: "TARGET_PPC_GFXOPT" ! 2749: " ! 2750: { operands[3] = gen_reg_rtx (SFmode); }") ! 2751: ! 2752: (define_split ! 2753: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2754: (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2755: (match_operand:SF 2 "gpc_reg_operand" ""))) ! 2756: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] ! 2757: "TARGET_PPC_GFXOPT" ! 2758: [(set (match_dup 3) ! 2759: (minus:SF (match_dup 1) (match_dup 2))) ! 2760: (set (match_operand:SF 0 "gpc_reg_operand" "") ! 2761: (if_then_else:SF (ge (match_dup 3) ! 2762: (const_int 0)) ! 2763: (match_dup 1) ! 2764: (match_dup 2)))] ! 2765: "") ! 2766: ! 2767: (define_expand "minsf3" ! 2768: [(set (match_dup 3) ! 2769: (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") ! 2770: (match_operand:SF 1 "gpc_reg_operand" ""))) ! 2771: (set (match_operand:SF 0 "gpc_reg_operand" "") ! 2772: (if_then_else:SF (ge (match_dup 3) ! 2773: (const_int 0)) ! 2774: (match_dup 1) ! 2775: (match_dup 2)))] ! 2776: "TARGET_PPC_GFXOPT" ! 2777: " ! 2778: { operands[3] = gen_reg_rtx (SFmode); }") ! 2779: ! 2780: (define_split ! 2781: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2782: (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2783: (match_operand:SF 2 "gpc_reg_operand" ""))) ! 2784: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] ! 2785: "TARGET_PPC_GFXOPT" ! 2786: [(set (match_dup 3) ! 2787: (minus:SF (match_dup 2) (match_dup 1))) ! 2788: (set (match_operand:SF 0 "gpc_reg_operand" "") ! 2789: (if_then_else:SF (ge (match_dup 3) ! 2790: (const_int 0)) ! 2791: (match_dup 1) ! 2792: (match_dup 2)))] ! 2793: "") ! 2794: ! 2795: (define_insn "" ! 2796: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2797: (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") ! 2798: (const_int 0)) ! 2799: (match_operand:SF 2 "gpc_reg_operand" "f") ! 2800: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2801: "TARGET_PPC_GFXOPT" ! 2802: "fsel %0,%1,%2,%3" ! 2803: [(set_attr "type" "fp")]) ! 2804: 1.1 root 2805: (define_insn "negdf2" 2806: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2807: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 2808: "" 2809: "fneg %0,%1" 2810: [(set_attr "type" "fp")]) 2811: 2812: (define_insn "absdf2" 2813: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2814: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 2815: "" 2816: "fabs %0,%1" 2817: [(set_attr "type" "fp")]) 2818: 2819: (define_insn "" 2820: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2821: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 2822: "" 2823: "fnabs %0,%1" 2824: [(set_attr "type" "fp")]) 2825: 2826: (define_insn "adddf3" 2827: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2828: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2829: (match_operand:DF 2 "gpc_reg_operand" "f")))] 2830: "" 1.1.1.2 root 2831: "{fa|fadd} %0,%1,%2" 1.1 root 2832: [(set_attr "type" "fp")]) 2833: 2834: (define_insn "subdf3" 2835: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2836: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 2837: (match_operand:DF 2 "gpc_reg_operand" "f")))] 2838: "" 1.1.1.2 root 2839: "{fs|fsub} %0,%1,%2" 1.1 root 2840: [(set_attr "type" "fp")]) 2841: 2842: (define_insn "muldf3" 2843: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2844: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2845: (match_operand:DF 2 "gpc_reg_operand" "f")))] 2846: "" 1.1.1.2 root 2847: "{fm|fmul} %0,%1,%2" 2848: [(set_attr "type" "dmul")]) 1.1 root 2849: 2850: (define_insn "divdf3" 2851: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2852: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 2853: (match_operand:DF 2 "gpc_reg_operand" "f")))] 2854: "" 1.1.1.2 root 2855: "{fd|fdiv} %0,%1,%2" 2856: [(set_attr "type" "ddiv")]) 1.1 root 2857: 2858: (define_insn "" 2859: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2860: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2861: (match_operand:DF 2 "gpc_reg_operand" "f")) 2862: (match_operand:DF 3 "gpc_reg_operand" "f")))] 2863: "" 1.1.1.2 root 2864: "{fma|fmadd} %0,%1,%2,%3" 2865: [(set_attr "type" "dmul")]) 1.1 root 2866: 2867: (define_insn "" 2868: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2869: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2870: (match_operand:DF 2 "gpc_reg_operand" "f")) 2871: (match_operand:DF 3 "gpc_reg_operand" "f")))] 2872: "" 1.1.1.2 root 2873: "{fms|fmsub} %0,%1,%2,%3" 2874: [(set_attr "type" "dmul")]) 1.1 root 2875: 2876: (define_insn "" 2877: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2878: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2879: (match_operand:DF 2 "gpc_reg_operand" "f")) 2880: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 2881: "" 1.1.1.2 root 2882: "{fnma|fnmadd} %0,%1,%2,%3" 2883: [(set_attr "type" "dmul")]) 1.1 root 2884: 2885: (define_insn "" 2886: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2887: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 2888: (match_operand:DF 2 "gpc_reg_operand" "f")) 2889: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 2890: "" 1.1.1.2 root 2891: "{fnms|fnmsub} %0,%1,%2,%3" 2892: [(set_attr "type" "dmul")]) 2893: 2894: (define_insn "sqrtdf2" 2895: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2896: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.3 ! root 2897: "TARGET_PPC_GPOPT || TARGET_POWER2" 1.1.1.2 root 2898: "fsqrt %0,%1" 2899: [(set_attr "type" "dsqrt")]) 1.1.1.3 ! root 2900: ! 2901: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel ! 2902: ;; instruction and some auxiliary computations. Then we just have a single ! 2903: ;; DEFINE_INSN for fsel and the define_splits to make them if made by ! 2904: ;; combine. ! 2905: ! 2906: (define_expand "maxdf3" ! 2907: [(set (match_dup 3) ! 2908: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") ! 2909: (match_operand:DF 2 "gpc_reg_operand" ""))) ! 2910: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2911: (if_then_else:DF (ge (match_dup 3) ! 2912: (const_int 0)) ! 2913: (match_dup 1) ! 2914: (match_dup 2)))] ! 2915: "TARGET_PPC_GFXOPT" ! 2916: " ! 2917: { operands[3] = gen_reg_rtx (DFmode); }") ! 2918: ! 2919: (define_split ! 2920: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 2921: (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") ! 2922: (match_operand:DF 2 "gpc_reg_operand" ""))) ! 2923: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] ! 2924: "TARGET_PPC_GFXOPT" ! 2925: [(set (match_dup 3) ! 2926: (minus:DF (match_dup 1) (match_dup 2))) ! 2927: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2928: (if_then_else:DF (ge (match_dup 3) ! 2929: (const_int 0)) ! 2930: (match_dup 1) ! 2931: (match_dup 2)))] ! 2932: "") ! 2933: ! 2934: (define_expand "mindf3" ! 2935: [(set (match_dup 3) ! 2936: (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") ! 2937: (match_operand:DF 1 "gpc_reg_operand" ""))) ! 2938: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2939: (if_then_else:DF (ge (match_dup 3) ! 2940: (const_int 0)) ! 2941: (match_dup 1) ! 2942: (match_dup 2)))] ! 2943: "TARGET_PPC_GFXOPT" ! 2944: " ! 2945: { operands[3] = gen_reg_rtx (DFmode); }") ! 2946: ! 2947: (define_split ! 2948: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 2949: (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") ! 2950: (match_operand:DF 2 "gpc_reg_operand" ""))) ! 2951: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] ! 2952: "TARGET_PPC_GFXOPT" ! 2953: [(set (match_dup 3) ! 2954: (minus:DF (match_dup 2) (match_dup 1))) ! 2955: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2956: (if_then_else:DF (ge (match_dup 3) ! 2957: (const_int 0)) ! 2958: (match_dup 1) ! 2959: (match_dup 2)))] ! 2960: "") ! 2961: ! 2962: (define_insn "" ! 2963: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2964: (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") ! 2965: (const_int 0)) ! 2966: (match_operand:DF 2 "gpc_reg_operand" "f") ! 2967: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 2968: "TARGET_PPC_GFXOPT" ! 2969: "fsel %0,%1,%2,%3" ! 2970: [(set_attr "type" "fp")]) 1.1 root 2971: 2972: ;; Conversions to and from floating-point. 2973: (define_expand "floatsidf2" 2974: [(set (match_dup 2) 2975: (plus:DI (zero_extend:DI 2976: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 2977: (match_dup 3))) 2978: (match_dup 4))) 2979: (set (match_operand:DF 0 "gpc_reg_operand" "") 2980: (minus:DF (subreg:DF (match_dup 2) 0) 2981: (match_dup 5)))] 2982: "" 2983: " 2984: { 2985: #if HOST_BITS_PER_INT != BITS_PER_WORD 2986: /* Maybe someone can figure out how to do this in that case. I don't 2987: want to right now. */ 2988: abort (); 2989: #endif 2990: 2991: operands[2] = gen_reg_rtx (DImode); 2992: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); 2993: operands[4] = immed_double_const (0, 0x43300000, DImode); 2994: operands[5] = force_reg (DFmode, immed_double_const (0x43300000, 2995: 0x80000000, DFmode)); 2996: }") 2997: 2998: (define_expand "floatunssidf2" 2999: [(set (match_dup 2) 3000: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 3001: (match_dup 3))) 3002: (set (match_operand:DF 0 "gpc_reg_operand" "") 3003: (minus:DF (subreg:DF (match_dup 2) 0) 3004: (match_dup 4)))] 3005: "" 3006: " 3007: { 3008: #if HOST_BITS_PER_INT != BITS_PER_WORD 3009: /* Maybe someone can figure out how to do this in that case. I don't 3010: want to right now. */ 3011: abort (); 3012: #endif 3013: 3014: operands[2] = gen_reg_rtx (DImode); 3015: operands[3] = immed_double_const (0, 0x43300000, DImode); 3016: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode)); 3017: }") 3018: 3019: ;; For the above two cases, we always split. 3020: (define_split 3021: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3022: (plus:DI (zero_extend:DI 3023: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 3024: (match_operand:SI 2 "logical_operand" ""))) 3025: (match_operand:DI 3 "immediate_operand" "")))] 3026: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD 3027: && GET_CODE (operands[3]) == CONST_DOUBLE 3028: && CONST_DOUBLE_LOW (operands[3]) == 0" 3029: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2))) 3030: (set (match_dup 4) (match_dup 5))] 3031: " 3032: { operands[4] = operand_subword (operands[0], 0, 0, DImode); 3033: operands[5] = operand_subword (operands[3], 0, 0, DImode); 3034: operands[6] = operand_subword (operands[0], 1, 0, DImode); 3035: }") 3036: 3037: (define_insn "" 3038: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3039: (plus:DI (zero_extend:DI 3040: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 3041: (match_operand:SI 2 "logical_operand" "rKJ"))) 3042: (match_operand:DI 3 "immediate_operand" "n")))] 3043: "HOST_BITS_PER_INT == BITS_PER_WORD 3044: && GET_CODE (operands[3]) == CONST_DOUBLE 3045: && CONST_DOUBLE_LOW (operands[3]) == 0" 1.1.1.2 root 3046: "#" 3047: [(set_attr "length" "8")]) 1.1 root 3048: 3049: (define_split 3050: [(set (match_operand:DI 0 "gpc_reg_operand" "=") 3051: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 3052: (match_operand:DI 2 "immediate_operand" "")))] 3053: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD 3054: && GET_CODE (operands[2]) == CONST_DOUBLE 3055: && CONST_DOUBLE_LOW (operands[2]) == 0" 3056: [(set (match_dup 3) (match_dup 4)) 3057: (set (match_dup 5) (match_dup 1))] 3058: " 3059: { operands[3] = operand_subword (operands[0], 0, 0, DImode); 3060: operands[4] = operand_subword (operands[2], 0, 0, DImode); 3061: operands[5] = operand_subword (operands[0], 1, 0, DImode); 3062: 3063: if (rtx_equal_p (operands[1], operands[5])) 3064: { 3065: emit_move_insn (operands[3], operands[4]); 3066: DONE; 3067: } 3068: 3069: if (rtx_equal_p (operands[1], operands[3])) 3070: { 3071: rtx temp; 3072: 3073: temp = operands[3]; operands[3] = operands[5]; operands[5] = temp; 3074: temp = operands[4]; operands[4] = operands[1]; operands[1] = temp; 3075: } 3076: }") 3077: 3078: (define_insn "" 3079: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3080: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 3081: (match_operand:DI 2 "immediate_operand" "n")))] 3082: "HOST_BITS_PER_INT == BITS_PER_WORD 3083: && GET_CODE (operands[2]) == CONST_DOUBLE 3084: && CONST_DOUBLE_LOW (operands[2]) == 0" 1.1.1.2 root 3085: "#" 3086: [(set_attr "length" "8")]) 1.1 root 3087: 3088: (define_expand "fix_truncdfsi2" 3089: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3090: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 3091: "" 3092: " 3093: { 1.1.1.3 ! root 3094: if (TARGET_POWER2 || TARGET_POWERPC) ! 3095: { ! 3096: rtx stack_slot = assign_stack_temp (DImode, 8, 0), ! 3097: temp = gen_reg_rtx (DImode); ! 3098: ! 3099: emit_insn (gen_fpcvtsi (temp, operands[1])); ! 3100: emit_move_insn (stack_slot, temp); ! 3101: emit_move_insn (operands[0], ! 3102: operand_subword (stack_slot, 1, 0, DImode)); ! 3103: DONE; ! 3104: } ! 3105: else ! 3106: { ! 3107: emit_insn (gen_trunc_call (operands[0], operands[1], ! 3108: gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC))); ! 3109: DONE; ! 3110: } 1.1 root 3111: }") 3112: 1.1.1.3 ! root 3113: (define_insn "fpcvtsi" ! 3114: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") ! 3115: (sign_extend:DI ! 3116: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] ! 3117: "TARGET_POWER2 || TARGET_POWERPC" ! 3118: "{fcirz|fctiwz} %0,%1" ! 3119: [(set_attr "type" "fp")]) ! 3120: 1.1 root 3121: (define_expand "fixuns_truncdfsi2" 3122: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3123: (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.3 ! root 3124: "! TARGET_POWER2 && ! TARGET_POWERPC" 1.1 root 3125: " 3126: { 3127: emit_insn (gen_trunc_call (operands[0], operands[1], 1.1.1.3 ! root 3128: gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC))); 1.1 root 3129: DONE; 3130: }") 3131: 3132: (define_expand "trunc_call" 3133: [(parallel [(set (match_operand:SI 0 "" "") 3134: (fix:SI (match_operand:DF 1 "" ""))) 3135: (use (match_operand:SI 2 "" ""))])] 3136: "" 3137: " 3138: { 3139: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); 3140: rtx first = XVECEXP (insns, 0, 0); 3141: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); 3142: 3143: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, 3144: REG_NOTES (first)); 3145: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); 3146: 3147: emit_insn (insns); 3148: DONE; 3149: }") 3150: 3151: (define_expand "trunc_call_rtl" 3152: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) 3153: (use (reg:DF 33)) 3154: (parallel [(set (reg:SI 3) 3155: (call (mem:SI (match_operand 2 "" "")) (const_int 0))) 3156: (clobber (scratch:SI))]) 3157: (set (match_operand:SI 0 "gpc_reg_operand" "") 3158: (reg:SI 3))] 3159: "" 3160: " 3161: { 3162: rs6000_trunc_used = 1; 3163: }") 1.1.1.3 ! root 3164: ! 3165: (define_insn "floatdidf2" ! 3166: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 3167: (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] ! 3168: "TARGET_POWERPC64" ! 3169: "fcfid %0,%1" ! 3170: [(set_attr "type" "fp")]) ! 3171: ! 3172: (define_insn "fix_truncdfdi2" ! 3173: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") ! 3174: (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 3175: "TARGET_POWERPC64" ! 3176: "fctidz %0,%1" ! 3177: [(set_attr "type" "fp")]) 1.1 root 3178: 3179: ;; Define the DImode operations that can be done in a small number 3180: ;; of instructions. 1.1.1.2 root 3181: (define_expand "adddi3" 3182: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3183: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 3184: (match_operand:DI 2 "reg_or_short_operand" "")))] 3185: "" 3186: " 3187: { 1.1.1.3 ! root 3188: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3189: && short_cint_operand (operands[2], DImode)) 3190: FAIL; 3191: }") 3192: 3193: (define_insn "" 1.1 root 3194: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3195: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 3196: (match_operand:DI 2 "reg_or_short_operand" "r,I")))] 1.1.1.3 ! root 3197: "TARGET_POWER && ! TARGET_POWERPC64" 1.1 root 3198: "@ 1.1.1.2 root 3199: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 3200: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" 3201: [(set_attr "length" "8")]) 1.1 root 3202: 1.1.1.2 root 3203: (define_insn "" 3204: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3205: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 3206: (match_operand:DI 2 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 3207: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.2 root 3208: "addc %L0,%L1,%L2\;adde %0,%1,%2" 3209: [(set_attr "length" "8")]) 3210: 3211: (define_expand "subdi3" 1.1 root 3212: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3213: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") 3214: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 3215: "" 1.1.1.2 root 3216: " 3217: { 1.1.1.3 ! root 3218: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3219: && short_cint_operand (operands[1], DImode)) 3220: FAIL; 3221: }") 3222: 3223: (define_insn "" 3224: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3225: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") 3226: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 1.1.1.3 ! root 3227: "TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.2 root 3228: "@ 3229: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 3230: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" 3231: [(set_attr "length" "8")]) 3232: 3233: (define_insn "" 3234: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3235: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3236: (match_operand:DI 2 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 3237: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.2 root 3238: "subfc %L0,%L2,%L1\;subfe %0,%2,%1" 3239: [(set_attr "length" "8")]) 3240: 3241: (define_expand "negdi2" 3242: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3243: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 3244: "" 3245: "") 1.1 root 3246: 1.1.1.2 root 3247: (define_insn "" 1.1 root 3248: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3249: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 3250: "! TARGET_POWERPC64" 1.1.1.2 root 3251: "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1" 3252: [(set_attr "length" "8")]) 1.1 root 3253: 1.1.1.3 ! root 3254: (define_expand "mulsidi3" ! 3255: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 3256: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! 3257: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] ! 3258: "" ! 3259: " ! 3260: { ! 3261: if (! TARGET_POWER && ! TARGET_POWERPC) ! 3262: { ! 3263: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 3264: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 3265: emit_insn (gen_mull_call ()); ! 3266: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), ! 3267: gen_rtx (REG, SImode, 3)); ! 3268: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), ! 3269: gen_rtx (REG, SImode, 4)); ! 3270: DONE; ! 3271: } ! 3272: else if (TARGET_POWER) ! 3273: { ! 3274: emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); ! 3275: DONE; ! 3276: } ! 3277: }") ! 3278: ! 3279: (define_insn "mulsidi3_mq" 1.1 root 3280: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1.1.1.3 ! root 3281: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 3282: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 3283: (clobber (match_scratch:SI 3 "=q"))] 1.1.1.2 root 3284: "TARGET_POWER" 3285: "mul %0,%1,%2\;mfmq %L0" 1.1.1.3 ! root 3286: [(set_attr "type" "imul") ! 3287: (set_attr "length" "8")]) ! 3288: ! 3289: (define_insn "" ! 3290: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") ! 3291: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 3292: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 3293: "TARGET_POWERPC && ! TARGET_POWERPC64" ! 3294: "mulhw %0,%1,%2\;mullw %L0,%1,%2" ! 3295: [(set_attr "type" "imul") ! 3296: (set_attr "length" "8")]) ! 3297: ! 3298: (define_expand "smulsi3_highpart" ! 3299: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 3300: (truncate:SI ! 3301: (lshiftrt:DI (mult:DI (sign_extend:DI ! 3302: (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 3303: (sign_extend:DI ! 3304: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 3305: (const_int 32))))] ! 3306: "" ! 3307: " ! 3308: { ! 3309: if (! TARGET_POWER && ! TARGET_POWERPC) ! 3310: { ! 3311: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); ! 3312: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); ! 3313: emit_insn (gen_mulh_call ()); ! 3314: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); ! 3315: DONE; ! 3316: } ! 3317: else if (TARGET_POWER) ! 3318: { ! 3319: emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); ! 3320: DONE; ! 3321: } ! 3322: }") ! 3323: ! 3324: (define_insn "smulsi3_highpart_mq" ! 3325: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3326: (truncate:SI ! 3327: (lshiftrt:DI (mult:DI (sign_extend:DI ! 3328: (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 3329: (sign_extend:DI ! 3330: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 3331: (const_int 32)))) ! 3332: (clobber (match_scratch:SI 3 "=q"))] ! 3333: "TARGET_POWER" ! 3334: "mul %0,%1,%2" ! 3335: [(set_attr "type" "imul")]) ! 3336: ! 3337: (define_insn "" ! 3338: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3339: (truncate:SI ! 3340: (lshiftrt:DI (mult:DI (sign_extend:DI ! 3341: (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 3342: (sign_extend:DI ! 3343: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 3344: (const_int 32))))] ! 3345: "TARGET_POWERPC" ! 3346: "mulhw %0,%1,%2" ! 3347: [(set_attr "type" "imul")]) ! 3348: ! 3349: (define_insn "umulsi3_highpart" ! 3350: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 3351: (truncate:SI ! 3352: (lshiftrt:DI (mult:DI (zero_extend:DI ! 3353: (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 3354: (zero_extend:DI ! 3355: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 3356: (const_int 32))))] ! 3357: "TARGET_POWERPC" ! 3358: "mulhwu %0,%1,%2" ! 3359: [(set_attr "type" "imul")]) 1.1 root 3360: 3361: ;; If operands 0 and 2 are in the same register, we have a problem. But 3362: ;; operands 0 and 1 (the usual case) can be in the same register. That's 3363: ;; why we have the strange constraints below. 3364: (define_insn "ashldi3" 3365: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 3366: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3367: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3368: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3369: "TARGET_POWER" 1.1 root 3370: "@ 1.1.1.2 root 3371: {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 1.1 root 3372: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 3373: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 1.1.1.2 root 3374: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 3375: [(set_attr "length" "8")]) 1.1 root 3376: 3377: (define_insn "lshrdi3" 3378: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") 3379: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3380: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3381: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3382: "TARGET_POWER" 1.1 root 3383: "@ 1.1.1.2 root 3384: {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2 1.1 root 3385: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 3386: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 1.1.1.2 root 3387: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 3388: [(set_attr "length" "8")]) 1.1 root 3389: 3390: ;; Shift by a variable amount is too complex to be worth open-coding. We 3391: ;; just handle shifts by constants. 3392: 3393: (define_expand "ashrdi3" 1.1.1.3 ! root 3394: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") 1.1 root 3395: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 3396: (match_operand:SI 2 "general_operand" ""))) 3397: (clobber (match_scratch:SI 3 ""))])] 1.1.1.2 root 3398: "TARGET_POWER" 1.1 root 3399: " 3400: { if (GET_CODE (operands[2]) != CONST_INT) 3401: FAIL; 3402: }") 3403: 3404: (define_insn "" 3405: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3406: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 3407: (match_operand:SI 2 "const_int_operand" "M,i"))) 3408: (clobber (match_scratch:SI 3 "=X,q"))] 1.1.1.2 root 3409: "TARGET_POWER" 1.1 root 3410: "@ 1.1.1.2 root 3411: {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 3412: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 3413: [(set_attr "length" "8")]) 1.1 root 3414: 1.1.1.3 ! root 3415: ;; PowerPC64 DImode operations. ! 3416: ! 3417: (define_insn "ffsdi2" ! 3418: [(set (match_operand:DI 0 "register_operand" "=&r") ! 3419: (ffs:DI (match_operand:DI 1 "register_operand" "r")))] ! 3420: "TARGET_POWERPC64" ! 3421: "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" ! 3422: [(set_attr "length" "16")]) ! 3423: ! 3424: (define_insn "muldi3" ! 3425: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3426: (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") ! 3427: (match_operand:DI 2 "gpc_reg_operand" "r")))] ! 3428: "TARGET_POWERPC64" ! 3429: "mulld %0,%1,%2" ! 3430: [(set_attr "type" "imul")]) ! 3431: ! 3432: (define_insn "smuldi3_highpart" ! 3433: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3434: (truncate:DI ! 3435: (lshiftrt:TI (mult:TI (sign_extend:TI ! 3436: (match_operand:DI 1 "gpc_reg_operand" "%r")) ! 3437: (sign_extend:TI ! 3438: (match_operand:DI 2 "gpc_reg_operand" "r"))) ! 3439: (const_int 64))))] ! 3440: "TARGET_POWERPC64" ! 3441: "mulhd %0,%1,%2" ! 3442: [(set_attr "type" "imul")]) ! 3443: ! 3444: (define_insn "umuldi3_highpart" ! 3445: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3446: (truncate:DI ! 3447: (lshiftrt:TI (mult:TI (zero_extend:TI ! 3448: (match_operand:DI 1 "gpc_reg_operand" "%r")) ! 3449: (zero_extend:TI ! 3450: (match_operand:DI 2 "gpc_reg_operand" "r"))) ! 3451: (const_int 64))))] ! 3452: "TARGET_POWERPC64" ! 3453: "mulhdu %0,%1,%2" ! 3454: [(set_attr "type" "imul")]) ! 3455: ! 3456: (define_insn "divdi3" ! 3457: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3458: (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 3459: (match_operand:DI 2 "gpc_reg_operand" "r")))] ! 3460: "TARGET_POWERPC64" ! 3461: "divd %0,%1,%2" ! 3462: [(set_attr "type" "idiv")]) ! 3463: ! 3464: (define_insn "udivdi3" ! 3465: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3466: (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 3467: (match_operand:DI 2 "gpc_reg_operand" "r")))] ! 3468: "TARGET_POWERPC64" ! 3469: "divdu %0,%1,%2" ! 3470: [(set_attr "type" "idiv")]) ! 3471: ! 3472: (define_insn "rotldi3" ! 3473: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3474: (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 3475: (match_operand:DI 2 "reg_or_cint_operand" "ri")))] ! 3476: "TARGET_POWERPC64" ! 3477: "rld%I2cl %0,%1,%h2,0") ! 3478: ! 3479: (define_insn "" ! 3480: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 3481: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 3482: (match_operand:DI 2 "reg_or_cint_operand" "ri")) ! 3483: (const_int 0))) ! 3484: (clobber (match_scratch:DI 3 "=r"))] ! 3485: "TARGET_POWERPC64" ! 3486: "rld%I2cl. %3,%1,%h2,0" ! 3487: [(set_attr "type" "delayed_compare")]) ! 3488: ! 3489: (define_insn "" ! 3490: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 3491: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 3492: (match_operand:DI 2 "reg_or_cint_operand" "ri")) ! 3493: (const_int 0))) ! 3494: (set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 3495: (rotate:DI (match_dup 1) (match_dup 2)))] ! 3496: "TARGET_POWERPC64" ! 3497: "rld%I2cl. %0,%1,%h2,0" ! 3498: [(set_attr "type" "delayed_compare")]) ! 3499: 1.1 root 3500: ;; Now define ways of moving data around. 3501: ;; 3502: ;; For SI, we special-case integers that can't be loaded in one insn. We 3503: ;; do the load 16-bits at a time. We could do this by loading from memory, 3504: ;; and this is even supposed to be faster, but it is simpler not to get 3505: ;; integers in the TOC. 3506: (define_expand "movsi" 3507: [(set (match_operand:SI 0 "general_operand" "") 3508: (match_operand:SI 1 "any_operand" ""))] 3509: "" 3510: " 3511: { 3512: if (GET_CODE (operands[0]) != REG) 3513: operands[1] = force_reg (SImode, operands[1]); 3514: 1.1.1.2 root 3515: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT 3516: && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) 1.1 root 3517: { 1.1.1.3 ! root 3518: /* If we are to limit the number of things we put in the TOC and ! 3519: this is a symbol plus a constant we can add in one insn, ! 3520: just put the sumbol in the TOC and add the constant. Don't do ! 3521: this if reload is in progress. */ ! 3522: if (GET_CODE (operands[1]) == CONST ! 3523: && TARGET_NO_SUM_IN_TOC && ! reload_in_progress ! 3524: && GET_CODE (XEXP (operands[1], 0)) == PLUS ! 3525: && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) ! 3526: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF ! 3527: || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) ! 3528: && ! side_effects_p (operands[0])) ! 3529: { ! 3530: rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); ! 3531: rtx other = XEXP (XEXP (operands[1], 0), 1); ! 3532: ! 3533: emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); ! 3534: DONE; ! 3535: } ! 3536: 1.1 root 3537: operands[1] = force_const_mem (SImode, operands[1]); 3538: if (! memory_address_p (SImode, XEXP (operands[1], 0)) 3539: && ! reload_in_progress) 3540: operands[1] = change_address (operands[1], SImode, 3541: XEXP (operands[1], 0)); 3542: } 3543: 3544: if (GET_CODE (operands[1]) == CONST_INT 3545: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3546: && (INTVAL (operands[1]) & 0xffff) != 0) 3547: { 3548: emit_move_insn (operands[0], 3549: gen_rtx (CONST_INT, VOIDmode, 3550: INTVAL (operands[1]) & 0xffff0000)); 3551: emit_insn (gen_iorsi3 (operands[0], operands[0], 3552: gen_rtx (CONST_INT, VOIDmode, 3553: INTVAL (operands[1]) & 0xffff))); 3554: DONE; 3555: } 3556: }") 3557: 3558: (define_insn "" 1.1.1.3 ! root 3559: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h") ! 3560: (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))] ! 3561: "gpc_reg_operand (operands[0], SImode) ! 3562: || gpc_reg_operand (operands[1], SImode)" 1.1 root 3563: "@ 1.1.1.3 ! root 3564: mr %0,%1 1.1.1.2 root 3565: {l%U1%X1|lwz%U1%X1} %0,%1 3566: {st%U0%X0|stw%U0%X0} %1,%0 1.1.1.3 ! root 3567: {lil|li} %0,%1 ! 3568: {liu|lis} %0,%u1 ! 3569: {cal|la} %0,%1(%*) 1.1 root 3570: mf%1 %0 3571: mt%0 %1 3572: mt%0 %1 3573: cror 0,0,0" 1.1.1.3 ! root 3574: [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 3575: 1.1 root 3576: ;; Split a load of a large constant into the appropriate two-insn 3577: ;; sequence. 3578: 3579: (define_split 3580: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3581: (match_operand:SI 1 "const_int_operand" ""))] 3582: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3583: && (INTVAL (operands[1]) & 0xffff) != 0" 3584: [(set (match_dup 0) 3585: (match_dup 2)) 3586: (set (match_dup 0) 3587: (ior:SI (match_dup 0) 3588: (match_dup 3)))] 3589: " 3590: { 3591: operands[2] = gen_rtx (CONST_INT, VOIDmode, 3592: INTVAL (operands[1]) & 0xffff0000); 3593: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); 3594: }") 3595: 3596: (define_insn "" 3597: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 3598: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 3599: (const_int 0))) 3600: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 3601: "" 1.1.1.3 ! root 3602: "mr. %0,%1" 1.1 root 3603: [(set_attr "type" "compare")]) 3604: 3605: (define_expand "movhi" 3606: [(set (match_operand:HI 0 "general_operand" "") 3607: (match_operand:HI 1 "any_operand" ""))] 3608: "" 3609: " 3610: { 3611: if (GET_CODE (operands[0]) != REG) 3612: operands[1] = force_reg (HImode, operands[1]); 3613: 3614: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 3615: { 3616: operands[1] = force_const_mem (HImode, operands[1]); 3617: if (! memory_address_p (HImode, XEXP (operands[1], 0)) 3618: && ! reload_in_progress) 3619: operands[1] = change_address (operands[1], HImode, 3620: XEXP (operands[1], 0)); 3621: } 3622: }") 3623: 3624: (define_insn "" 1.1.1.3 ! root 3625: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") ! 3626: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] ! 3627: "gpc_reg_operand (operands[0], HImode) ! 3628: || gpc_reg_operand (operands[1], HImode)" 1.1 root 3629: "@ 1.1.1.3 ! root 3630: mr %0,%1 1.1 root 3631: lhz%U1%X1 %0,%1 3632: sth%U0%X0 %1,%0 1.1.1.3 ! root 3633: {lil|li} %0,%w1 1.1 root 3634: mf%1 %0 3635: mt%0 %1 1.1.1.3 ! root 3636: mt%0 %1 1.1 root 3637: cror 0,0,0" 1.1.1.3 ! root 3638: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 3639: 1.1 root 3640: (define_expand "movqi" 3641: [(set (match_operand:QI 0 "general_operand" "") 3642: (match_operand:QI 1 "any_operand" ""))] 3643: "" 3644: " 3645: { 3646: if (GET_CODE (operands[0]) != REG) 3647: operands[1] = force_reg (QImode, operands[1]); 3648: 3649: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 3650: { 3651: operands[1] = force_const_mem (QImode, operands[1]); 3652: if (! memory_address_p (QImode, XEXP (operands[1], 0)) 3653: && ! reload_in_progress) 3654: operands[1] = change_address (operands[1], QImode, 3655: XEXP (operands[1], 0)); 3656: } 3657: }") 3658: 3659: (define_insn "" 1.1.1.3 ! root 3660: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") ! 3661: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] ! 3662: "gpc_reg_operand (operands[0], QImode) ! 3663: || gpc_reg_operand (operands[1], QImode)" 1.1 root 3664: "@ 1.1.1.3 ! root 3665: mr %0,%1 1.1 root 3666: lbz%U1%X1 %0,%1 3667: stb%U0%X0 %1,%0 1.1.1.3 ! root 3668: {lil|li} %0,%1 1.1 root 3669: mf%1 %0 3670: mt%0 %1 1.1.1.3 ! root 3671: mt%0 %1 1.1 root 3672: cror 0,0,0" 1.1.1.3 ! root 3673: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1 root 3674: 3675: ;; Here is how to move condition codes around. When we store CC data in 3676: ;; an integer register or memory, we store just the high-order 4 bits. 3677: ;; This lets us not shift in the most common case of CR0. 3678: (define_expand "movcc" 3679: [(set (match_operand:CC 0 "nonimmediate_operand" "") 3680: (match_operand:CC 1 "nonimmediate_operand" ""))] 3681: "" 3682: "") 3683: 3684: (define_insn "" 3685: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") 3686: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] 3687: "register_operand (operands[0], CCmode) 3688: || register_operand (operands[1], CCmode)" 3689: "@ 3690: mcrf %0,%1 3691: mtcrf 128,%1 1.1.1.2 root 3692: {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 1.1 root 3693: mfcr %0 1.1.1.2 root 3694: mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 1.1.1.3 ! root 3695: mr %0,%1 1.1.1.2 root 3696: {l%U1%X1|lwz%U1%X1} %0,%1 3697: {st%U0%U1|stw%U0%U1} %1,%0" 3698: [(set_attr "type" "*,*,*,compare,*,*,load,*") 3699: (set_attr "length" "*,*,12,*,8,*,*,*")]) 1.1 root 3700: 3701: ;; For floating-point, we normally deal with the floating-point registers. 3702: ;; The sole exception is that parameter passing can produce floating-point 3703: ;; values in fixed-point registers. Unless the value is a simple constant 3704: ;; or already in memory, we deal with this by allocating memory and copying 3705: ;; the value explicitly via that memory location. 3706: (define_expand "movsf" 3707: [(set (match_operand:SF 0 "nonimmediate_operand" "") 3708: (match_operand:SF 1 "any_operand" ""))] 3709: "" 3710: " 3711: { 3712: /* If we are called from reload, we might be getting a SUBREG of a hard 3713: reg. So expand it. */ 3714: if (GET_CODE (operands[0]) == SUBREG 3715: && GET_CODE (SUBREG_REG (operands[0])) == REG 3716: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) 3717: operands[0] = alter_subreg (operands[0]); 3718: if (GET_CODE (operands[1]) == SUBREG 3719: && GET_CODE (SUBREG_REG (operands[1])) == REG 3720: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) 3721: operands[1] = alter_subreg (operands[1]); 3722: 3723: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) 3724: { 3725: /* If this is a store to memory or another integer register do the 3726: move directly. Otherwise store to a temporary stack slot and 3727: load from there into a floating point register. */ 3728: 3729: if (GET_CODE (operands[0]) == MEM 3730: || (GET_CODE (operands[0]) == REG 3731: && (REGNO (operands[0]) < 32 3732: || (reload_in_progress 3733: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) 3734: { 3735: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), 3736: operand_subword (operands[1], 0, 0, SFmode)); 3737: DONE; 3738: } 1.1.1.3 ! root 3739: else ! 3740: { ! 3741: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); 1.1 root 3742: 1.1.1.3 ! root 3743: emit_move_insn (stack_slot, operands[1]); ! 3744: emit_move_insn (operands[0], stack_slot); ! 3745: DONE; ! 3746: } 1.1 root 3747: } 3748: 3749: if (GET_CODE (operands[0]) == MEM) 1.1.1.3 ! root 3750: { ! 3751: /* If operands[1] is a register, it may have double-precision data ! 3752: in it, so truncate it to single precision. We need not do ! 3753: this for POWERPC. */ ! 3754: if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG) ! 3755: { ! 3756: rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); ! 3757: emit_insn (gen_truncdfsf2 (newreg, ! 3758: gen_rtx (SUBREG, DFmode, operands[1], 0))); ! 3759: operands[1] = newreg; ! 3760: } ! 3761: ! 3762: operands[1] = force_reg (SFmode, operands[1]); ! 3763: } 1.1 root 3764: 3765: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) 3766: { 3767: if (GET_CODE (operands[1]) == MEM 3768: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) 3769: || GET_CODE (operands[1]) == CONST_DOUBLE 3770: #endif 1.1.1.3 ! root 3771: || (GET_CODE (operands[1]) == REG ! 3772: && (REGNO (operands[1]) < 32 ! 3773: || (reload_in_progress ! 3774: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)))) 1.1 root 3775: { 3776: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), 3777: operand_subword (operands[1], 0, 0, SFmode)); 3778: DONE; 3779: } 3780: else 1.1.1.3 ! root 3781: { ! 3782: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); ! 3783: ! 3784: emit_move_insn (stack_slot, operands[1]); ! 3785: emit_move_insn (operands[0], stack_slot); ! 3786: DONE; ! 3787: } 1.1 root 3788: } 3789: 3790: if (CONSTANT_P (operands[1])) 3791: { 3792: operands[1] = force_const_mem (SFmode, operands[1]); 3793: if (! memory_address_p (SFmode, XEXP (operands[1], 0)) 3794: && ! reload_in_progress) 3795: operands[1] = change_address (operands[1], SFmode, 3796: XEXP (operands[1], 0)); 3797: } 3798: }") 3799: 3800: (define_split 3801: [(set (match_operand:SF 0 "gpc_reg_operand" "") 3802: (match_operand:SF 1 "easy_fp_constant" ""))] 3803: "reload_completed && REGNO (operands[0]) <= 31" 3804: [(set (match_dup 2) (match_dup 3))] 3805: " 3806: { operands[2] = operand_subword (operands[0], 0, 0, SFmode); 3807: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") 3808: 3809: (define_insn "" 3810: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") 3811: (match_operand:SF 1 "input_operand" "f,m,f"))] 3812: "gpc_reg_operand (operands[0], SFmode) 3813: || gpc_reg_operand (operands[1], SFmode)" 3814: "@ 3815: fmr %0,%1 3816: lfs%U1%X1 %0,%1 1.1.1.3 ! root 3817: stfs%U0%X0 %1,%0" ! 3818: [(set_attr "type" "fp,fpload,*")]) 1.1 root 3819: 3820: (define_expand "movdf" 3821: [(set (match_operand:DF 0 "nonimmediate_operand" "") 3822: (match_operand:DF 1 "any_operand" ""))] 3823: "" 3824: " 3825: { 1.1.1.2 root 3826: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1 root 3827: { 1.1.1.2 root 3828: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 3829: operand_subword_force (operands[1], 1, DFmode)); 3830: emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), 3831: operand_subword_force (operands[1], 0, DFmode)); 1.1 root 3832: DONE; 3833: } 3834: 1.1.1.2 root 3835: if (GET_CODE (operands[0]) != REG) 3836: operands[1] = force_reg (DFmode, operands[1]); 1.1 root 3837: 1.1.1.2 root 3838: if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) 1.1 root 3839: { 3840: operands[1] = force_const_mem (DFmode, operands[1]); 3841: if (! memory_address_p (DFmode, XEXP (operands[1], 0)) 3842: && ! reload_in_progress) 3843: operands[1] = change_address (operands[1], DFmode, 3844: XEXP (operands[1], 0)); 3845: } 3846: }") 3847: 3848: (define_split 3849: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3850: (match_operand:DF 1 "easy_fp_constant" ""))] 3851: "reload_completed && REGNO (operands[0]) <= 31" 3852: [(set (match_dup 2) (match_dup 3)) 3853: (set (match_dup 4) (match_dup 5))] 3854: " 3855: { operands[2] = operand_subword (operands[0], 0, 0, DFmode); 3856: operands[3] = operand_subword (operands[1], 0, 0, DFmode); 3857: operands[4] = operand_subword (operands[0], 1, 0, DFmode); 3858: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") 1.1.1.2 root 3859: 3860: ;; Don't have reload use general registers to load a constant. First, 3861: ;; it might not work if the output operand has is the equivalent of 3862: ;; a non-offsettable memref, but also it is less efficient than loading 3863: ;; the constant into an FP register, since it will probably be used there. 3864: ;; The "??" is a kludge until we can figure out a more reasonable way 3865: ;; of handling these non-offsettable values. 3866: (define_insn "" 3867: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") 3868: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] 1.1.1.3 ! root 3869: "! TARGET_POWERPC64 && (register_operand (operands[0], DFmode) ! 3870: || register_operand (operands[1], DFmode))" 1.1.1.2 root 3871: "* 3872: { 3873: switch (which_alternative) 3874: { 3875: case 0: 3876: /* We normally copy the low-numbered register first. However, if 3877: the first register operand 0 is the same as the second register of 3878: operand 1, we must copy in the opposite order. */ 3879: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 ! root 3880: return \"mr %L0,%L1\;mr %0,%1\"; 1.1.1.2 root 3881: else 1.1.1.3 ! root 3882: return \"mr %0,%1\;mr %L0,%L1\"; 1.1.1.2 root 3883: case 1: 3884: /* If the low-address word is used in the address, we must load it 3885: last. Otherwise, load it first. Note that we cannot have 3886: auto-increment in that case since the address register is known to be 3887: dead. */ 3888: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 3889: operands [1], 0)) 3890: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 3891: else 3892: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 3893: case 2: 3894: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 3895: case 3: 3896: return \"#\"; 3897: case 4: 3898: return \"fmr %0,%1\"; 3899: case 5: 3900: return \"lfd%U1%X1 %0,%1\"; 3901: case 6: 3902: return \"stfd%U0%X0 %1,%0\"; 3903: } 3904: }" 3905: [(set_attr "type" "*,load,*,*,fp,fpload,*") 3906: (set_attr "length" "8,8,8,8,*,*,*")]) 1.1.1.3 ! root 3907: ! 3908: (define_insn "" ! 3909: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") ! 3910: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] ! 3911: "TARGET_POWERPC64 && (register_operand (operands[0], DFmode) ! 3912: || register_operand (operands[1], DFmode))" ! 3913: "@ ! 3914: mr %0,%1 ! 3915: ld%U1%X1 %0,%1 ! 3916: sd%U0%X0 %1,%0 ! 3917: # ! 3918: fmr %0,%1 ! 3919: lfd%U1%X1 %0,%1 ! 3920: stfd%U0%X0 %1,%0" ! 3921: [(set_attr "type" "*,load,*,*,fp,fpload,*")]) 1.1 root 3922: 3923: ;; Next come the multi-word integer load and store and the load and store 3924: ;; multiple insns. 3925: (define_expand "movdi" 3926: [(set (match_operand:DI 0 "general_operand" "") 3927: (match_operand:DI 1 "general_operand" ""))] 3928: "" 3929: " 3930: { 3931: if (GET_CODE (operands[1]) == CONST_DOUBLE 3932: || GET_CODE (operands[1]) == CONST_INT) 3933: { 3934: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), 3935: operand_subword (operands[1], 0, 0, DImode)); 3936: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), 3937: operand_subword (operands[1], 1, 0, DImode)); 3938: DONE; 3939: } 3940: 3941: if (GET_CODE (operands[0]) == MEM) 3942: operands[1] = force_reg (DImode, operands[1]); 1.1.1.3 ! root 3943: ! 3944: /* Stores between FPR and any non-FPR registers must go through a ! 3945: temporary stack slot. */ ! 3946: ! 3947: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG ! 3948: && ((FP_REGNO_P (REGNO (operands[0])) ! 3949: && ! FP_REGNO_P (REGNO (operands[1]))) ! 3950: || (FP_REGNO_P (REGNO (operands[1])) ! 3951: && ! FP_REGNO_P (REGNO (operands[0]))))) ! 3952: { ! 3953: rtx stack_slot = assign_stack_temp (DImode, 8, 0); ! 3954: ! 3955: emit_move_insn (stack_slot, operands[1]); ! 3956: emit_move_insn (operands[0], stack_slot); ! 3957: DONE; ! 3958: } 1.1 root 3959: }") 3960: 3961: (define_insn "" 1.1.1.3 ! root 3962: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m") ! 3963: (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))] ! 3964: "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) ! 3965: || gpc_reg_operand (operands[1], DImode))" 1.1 root 3966: "* 3967: { 3968: switch (which_alternative) 3969: { 3970: case 0: 3971: /* We normally copy the low-numbered register first. However, if 3972: the first register operand 0 is the same as the second register of 3973: operand 1, we must copy in the opposite order. */ 3974: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 ! root 3975: return \"mr %L0,%L1\;mr %0,%1\"; 1.1 root 3976: else 1.1.1.3 ! root 3977: return \"mr %0,%1\;mr %L0,%L1\"; 1.1 root 3978: case 1: 3979: /* If the low-address word is used in the address, we must load it 3980: last. Otherwise, load it first. Note that we cannot have 3981: auto-increment in that case since the address register is known to be 3982: dead. */ 3983: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 3984: operands [1], 0)) 1.1.1.2 root 3985: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 1.1 root 3986: else 1.1.1.2 root 3987: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 1.1 root 3988: case 2: 1.1.1.2 root 3989: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 1.1.1.3 ! root 3990: case 3: ! 3991: return \"fmr %0,%1\"; ! 3992: case 4: ! 3993: return \"lfd%U1%X1 %0,%1\"; ! 3994: case 5: ! 3995: return \"stfd%U0%X0 %1,%0\"; 1.1 root 3996: } 3997: }" 1.1.1.3 ! root 3998: [(set_attr "type" "*,load,*,fp,fpload,*") ! 3999: (set_attr "length" "8,8,8,*,*,*")]) ! 4000: ! 4001: (define_insn "" ! 4002: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h") ! 4003: (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))] ! 4004: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) ! 4005: || gpc_reg_operand (operands[1], DImode))" ! 4006: "@ ! 4007: mr %0,%1 ! 4008: ld%U1%X1 %0,%1 ! 4009: sd%U0%X0 %1,%0 ! 4010: li %0,%1 ! 4011: lis %0,%u1 ! 4012: {cal|la} %0,%1(%*) ! 4013: fmr %0,%1 ! 4014: lfd%U1%X1 %0,%1 ! 4015: stfd%U0%X0 %1,%0 ! 4016: mf%1 %0 ! 4017: mt%0 %1" ! 4018: [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")]) 1.1 root 4019: 4020: ;; TImode is similar, except that we usually want to compute the address into 4021: ;; a register and use lsi/stsi (the exception is during reload). MQ is also 1.1.1.2 root 4022: ;; clobbered in stsi for POWER, so we need a SCRATCH for it. 1.1 root 4023: (define_expand "movti" 4024: [(parallel [(set (match_operand:TI 0 "general_operand" "") 4025: (match_operand:TI 1 "general_operand" "")) 4026: (clobber (scratch:SI))])] 1.1.1.3 ! root 4027: "TARGET_POWER || TARGET_POWERPC64" 1.1 root 4028: " 4029: { 4030: if (GET_CODE (operands[0]) == MEM) 4031: operands[1] = force_reg (TImode, operands[1]); 4032: 4033: if (GET_CODE (operands[0]) == MEM 4034: && GET_CODE (XEXP (operands[0], 0)) != REG 4035: && ! reload_in_progress) 4036: operands[0] = change_address (operands[0], TImode, 4037: copy_addr_to_reg (XEXP (operands[0], 0))); 4038: 4039: if (GET_CODE (operands[1]) == MEM 4040: && GET_CODE (XEXP (operands[1], 0)) != REG 4041: && ! reload_in_progress) 4042: operands[1] = change_address (operands[1], TImode, 4043: copy_addr_to_reg (XEXP (operands[1], 0))); 4044: }") 4045: 4046: ;; We say that MQ is clobbered in the last alternative because the first 4047: ;; alternative would never get used otherwise since it would need a reload 4048: ;; while the 2nd alternative would not. We put memory cases first so they 4049: ;; are preferred. Otherwise, we'd try to reload the output instead of 4050: ;; giving the SCRATCH mq. 4051: (define_insn "" 1.1.1.3 ! root 4052: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 1.1 root 4053: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) 4054: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] 1.1.1.3 ! root 4055: "TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 1.1.1.2 root 4056: || gpc_reg_operand (operands[1], TImode))" 1.1 root 4057: "* 4058: { 4059: switch (which_alternative) 4060: { 4061: case 0: 1.1.1.2 root 4062: return \"{stsi|stswi} %1,%P0,16\"; 1.1 root 4063: 4064: case 1: 1.1.1.2 root 4065: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 1.1 root 4066: 4067: case 2: 4068: /* Normally copy registers with lowest numbered register copied first. 4069: But copy in the other order if the first register of the output 4070: is the second, third, or fourth register in the input. */ 4071: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 4072: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 1.1.1.3 ! root 4073: return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 1.1 root 4074: else 1.1.1.3 ! root 4075: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 1.1 root 4076: case 3: 4077: /* If the address is not used in the output, we can use lsi. Otherwise, 4078: fall through to generating four loads. */ 4079: if (! reg_overlap_mentioned_p (operands[0], operands[1])) 1.1.1.2 root 4080: return \"{lsi|lswi} %0,%P1,16\"; 1.1 root 4081: /* ... fall through ... */ 4082: case 4: 4083: /* If the address register is the same as the register for the lowest- 4084: addressed word, load it last. Similarly for the next two words. 4085: Otherwise load lowest address to highest. */ 4086: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4087: operands[1], 0)) 1.1.1.2 root 4088: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 1.1 root 4089: else if (refers_to_regno_p (REGNO (operands[0]) + 1, 4090: REGNO (operands[0]) + 2, operands[1], 0)) 1.1.1.2 root 4091: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 1.1 root 4092: else if (refers_to_regno_p (REGNO (operands[0]) + 2, 4093: REGNO (operands[0]) + 3, operands[1], 0)) 1.1.1.2 root 4094: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 1.1 root 4095: else 1.1.1.2 root 4096: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 1.1 root 4097: } 4098: }" 1.1.1.2 root 4099: [(set_attr "type" "*,load,load,*,*") 4100: (set_attr "length" "*,16,16,*,16")]) 1.1.1.3 ! root 4101: ! 4102: (define_insn "" ! 4103: [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") ! 4104: (match_operand:TI 1 "input_operand" "r,m,r"))] ! 4105: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) ! 4106: || gpc_reg_operand (operands[1], TImode))" ! 4107: "* ! 4108: { ! 4109: switch (which_alternative) ! 4110: { ! 4111: case 0: ! 4112: /* We normally copy the low-numbered register first. However, if ! 4113: the first register operand 0 is the same as the second register of ! 4114: operand 1, we must copy in the opposite order. */ ! 4115: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 4116: return \"mr %L0,%L1\;mr %0,%1\"; ! 4117: else ! 4118: return \"mr %0,%1\;mr %L0,%L1\"; ! 4119: case 1: ! 4120: /* If the low-address word is used in the address, we must load it ! 4121: last. Otherwise, load it first. Note that we cannot have ! 4122: auto-increment in that case since the address register is known to be ! 4123: dead. */ ! 4124: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 4125: operands [1], 0)) ! 4126: return \"ld %L0,%L1\;ld %0,%1\"; ! 4127: else ! 4128: return \"ld%U1 %0,%1\;ld %L0,%L1\"; ! 4129: case 2: ! 4130: return \"std%U0 %1,%0\;std %L1,%L0\"; ! 4131: } ! 4132: }" ! 4133: [(set_attr "type" "*,load,*") ! 4134: (set_attr "length" "8,8,8")]) 1.1 root 4135: 4136: (define_expand "load_multiple" 4137: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4138: (match_operand:SI 1 "" "")) 4139: (use (match_operand:SI 2 "" ""))])] 1.1.1.2 root 4140: "TARGET_POWER" 1.1 root 4141: " 4142: { 4143: int regno; 4144: int count; 4145: rtx from; 4146: int i; 4147: 4148: /* Support only loading a constant number of fixed-point registers from 4149: memory and only bother with this if more than two; the machine 4150: doesn't support more than eight. */ 4151: if (GET_CODE (operands[2]) != CONST_INT 4152: || INTVAL (operands[2]) <= 2 4153: || INTVAL (operands[2]) > 8 4154: || GET_CODE (operands[1]) != MEM 4155: || GET_CODE (operands[0]) != REG 4156: || REGNO (operands[0]) >= 32) 4157: FAIL; 4158: 4159: count = INTVAL (operands[2]); 4160: regno = REGNO (operands[0]); 4161: 4162: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); 4163: from = force_reg (SImode, XEXP (operands[1], 0)); 4164: 4165: for (i = 0; i < count; i++) 4166: XVECEXP (operands[3], 0, i) 4167: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), 4168: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); 4169: }") 4170: 4171: (define_insn "" 4172: [(match_parallel 0 "load_multiple_operation" 4173: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 4174: (match_operand:SI 2 "indirect_operand" "Q"))])] 1.1.1.2 root 4175: "TARGET_POWER" 1.1 root 4176: "* 4177: { 4178: /* We have to handle the case where the pseudo used to contain the address 4179: is assigned to one of the output registers. In that case, do the 4180: lsi, but then load the correct value. This is a bit of a mess, but is 1.1.1.2 root 4181: the best we can do. 4182: We set the length attribute to the maximum possible size (8 bytes). */ 1.1 root 4183: static char result[100]; 4184: char newload[40]; 4185: int i; 4186: 1.1.1.2 root 4187: strcpy (result, \"{lsi|lswi} %1,%P2,%N0\"); 1.1 root 4188: for (i = 0; i < XVECLEN (operands[0], 0); i++) 4189: if (refers_to_regno_p (REGNO (operands[1]) + i, 4190: REGNO (operands[1]) + i + 1, operands[2], 0)) 4191: { 1.1.1.2 root 4192: sprintf (newload, \"\;{l|lwz} %d,%d(%d)\", 1.1 root 4193: REGNO (operands[1]) + i, 4194: i * 4, REGNO (XEXP (operands[2], 0))); 4195: strcat (result, newload); 4196: } 4197: 4198: return result; 4199: }" 1.1.1.2 root 4200: [(set_attr "type" "load") 4201: (set_attr "length" "8")]) 1.1 root 4202: 1.1.1.2 root 4203: 1.1 root 4204: (define_expand "store_multiple" 4205: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4206: (match_operand:SI 1 "" "")) 4207: (clobber (scratch:SI)) 4208: (use (match_operand:SI 2 "" ""))])] 1.1.1.2 root 4209: "TARGET_POWER" 1.1 root 4210: " 4211: { 4212: int regno; 4213: int count; 4214: rtx to; 4215: int i; 4216: 4217: /* Support only storing a constant number of fixed-point registers to 4218: memory and only bother with this if more than two; the machine 4219: doesn't support more than eight. */ 4220: if (GET_CODE (operands[2]) != CONST_INT 4221: || INTVAL (operands[2]) <= 2 4222: || INTVAL (operands[2]) > 8 4223: || GET_CODE (operands[0]) != MEM 4224: || GET_CODE (operands[1]) != REG 4225: || REGNO (operands[1]) >= 32) 4226: FAIL; 4227: 4228: count = INTVAL (operands[2]); 4229: regno = REGNO (operands[1]); 4230: 4231: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); 4232: to = force_reg (SImode, XEXP (operands[0], 0)); 4233: 4234: XVECEXP (operands[3], 0, 0) 4235: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); 4236: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, 4237: gen_rtx (SCRATCH, SImode)); 4238: 4239: for (i = 1; i < count; i++) 4240: XVECEXP (operands[3], 0, i + 1) 4241: = gen_rtx (SET, VOIDmode, 4242: gen_rtx (MEM, SImode, plus_constant (to, i * 4)), 4243: gen_rtx (REG, SImode, regno + i)); 4244: }") 4245: 4246: (define_insn "" 4247: [(match_parallel 0 "store_multiple_operation" 4248: [(set (match_operand:SI 1 "indirect_operand" "=Q") 4249: (match_operand:SI 2 "gpc_reg_operand" "r")) 4250: (clobber (match_scratch:SI 3 "=q"))])] 1.1.1.2 root 4251: "TARGET_POWER" 4252: "{stsi|stswi} %2,%P1,%O0") 1.1 root 4253: 4254: ;; Define insns that do load or store with update. Some of these we can 4255: ;; get by using pre-decrement or pre-increment, but the hardware can also 4256: ;; do cases where the increment is not the size of the object. 4257: ;; 4258: ;; In all these cases, we use operands 0 and 1 for the register being 4259: ;; incremented because those are the operands that local-alloc will 4260: ;; tie and these are the pair most likely to be tieable (and the ones 4261: ;; that will benefit the most). 4262: 4263: (define_insn "" 1.1.1.3 ! root 4264: [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") ! 4265: (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") ! 4266: (match_operand:DI 2 "reg_or_short_operand" "r,I")))) ! 4267: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") ! 4268: (plus:DI (match_dup 1) (match_dup 2)))] ! 4269: "TARGET_POWERPC64" ! 4270: "@ ! 4271: ldux %3,%0,%2 ! 4272: ldu %3,%2(%0)" ! 4273: [(set_attr "type" "load")]) ! 4274: ! 4275: (define_insn "" ! 4276: [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") ! 4277: (match_operand:DI 2 "reg_or_short_operand" "r,I"))) ! 4278: (match_operand:DI 3 "gpc_reg_operand" "r,r")) ! 4279: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") ! 4280: (plus:DI (match_dup 1) (match_dup 2)))] ! 4281: "TARGET_POWERPC64" ! 4282: "@ ! 4283: stdux %3,%0,%2 ! 4284: stdu %3,%2(%0)") ! 4285: ! 4286: (define_insn "" 1.1 root 4287: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 4288: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4289: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 4290: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4291: (plus:SI (match_dup 1) (match_dup 2)))] 4292: "" 4293: "@ 1.1.1.2 root 4294: {lux|lwzux} %3,%0,%2 4295: {lu|lwzu} %3,%2(%0)" 4296: [(set_attr "type" "load")]) 1.1 root 4297: 4298: (define_insn "" 4299: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4300: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 4301: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 4302: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4303: (plus:SI (match_dup 1) (match_dup 2)))] 4304: "" 4305: "@ 1.1.1.2 root 4306: {stux|stwux} %3,%0,%2 4307: {stu|stwu} %3,%2(%0)") 1.1 root 4308: 4309: (define_insn "" 4310: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 4311: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4312: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 4313: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4314: (plus:SI (match_dup 1) (match_dup 2)))] 4315: "" 4316: "@ 4317: lhzux %3,%0,%2 4318: lhzu %3,%2(%0)" 1.1.1.2 root 4319: [(set_attr "type" "load")]) 1.1 root 4320: 4321: (define_insn "" 4322: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 4323: (zero_extend:SI 4324: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4325: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 4326: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4327: (plus:SI (match_dup 1) (match_dup 2)))] 4328: "" 4329: "@ 4330: lhzux %3,%0,%2 4331: lhzu %3,%2(%0)" 1.1.1.2 root 4332: [(set_attr "type" "load")]) 1.1 root 4333: 4334: (define_insn "" 4335: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 4336: (sign_extend:SI 4337: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4338: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 4339: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4340: (plus:SI (match_dup 1) (match_dup 2)))] 4341: "" 4342: "@ 4343: lhaux %3,%0,%2 4344: lhau %3,%2(%0)" 1.1.1.2 root 4345: [(set_attr "type" "load")]) 1.1 root 4346: 4347: (define_insn "" 4348: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4349: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 4350: (match_operand:HI 3 "gpc_reg_operand" "r,r")) 4351: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4352: (plus:SI (match_dup 1) (match_dup 2)))] 4353: "" 4354: "@ 4355: sthux %3,%0,%2 1.1.1.2 root 4356: sthu %3,%2(%0)") 1.1 root 4357: 4358: (define_insn "" 4359: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 4360: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4361: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 4362: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4363: (plus:SI (match_dup 1) (match_dup 2)))] 4364: "" 4365: "@ 4366: lbzux %3,%0,%2 4367: lbzu %3,%2(%0)" 1.1.1.2 root 4368: [(set_attr "type" "load")]) 1.1 root 4369: 4370: (define_insn "" 4371: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 4372: (zero_extend:SI 4373: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4374: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 4375: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4376: (plus:SI (match_dup 1) (match_dup 2)))] 4377: "" 4378: "@ 4379: lbzux %3,%0,%2 4380: lbzu %3,%2(%0)" 1.1.1.2 root 4381: [(set_attr "type" "load")]) 1.1 root 4382: 4383: (define_insn "" 4384: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4385: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 4386: (match_operand:QI 3 "gpc_reg_operand" "r,r")) 4387: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4388: (plus:SI (match_dup 1) (match_dup 2)))] 4389: "" 4390: "@ 4391: stbux %3,%0,%2 4392: stbu %3,%2(%0)") 4393: 4394: (define_insn "" 4395: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 1.1.1.3 ! root 4396: (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 1.1 root 4397: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 4398: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4399: (plus:SI (match_dup 1) (match_dup 2)))] 4400: "" 4401: "@ 4402: lfsux %3,%0,%2 4403: lfsu %3,%2(%0)" 1.1.1.2 root 4404: [(set_attr "type" "fpload")]) 1.1 root 4405: 4406: (define_insn "" 4407: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4408: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 4409: (match_operand:SF 3 "gpc_reg_operand" "f,f")) 4410: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4411: (plus:SI (match_dup 1) (match_dup 2)))] 4412: "" 4413: "@ 1.1.1.3 ! root 4414: stfsux %3,%0,%2 ! 4415: stfsu %3,%2(%0)") 1.1 root 4416: 4417: (define_insn "" 4418: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 4419: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4420: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 4421: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4422: (plus:SI (match_dup 1) (match_dup 2)))] 4423: "" 4424: "@ 4425: lfdux %3,%0,%2 4426: lfdu %3,%2(%0)" 1.1.1.2 root 4427: [(set_attr "type" "fpload")]) 1.1 root 4428: 4429: (define_insn "" 4430: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 4431: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 4432: (match_operand:DF 3 "gpc_reg_operand" "f,f")) 4433: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 4434: (plus:SI (match_dup 1) (match_dup 2)))] 4435: "" 4436: "@ 4437: stfdux %3,%0,%2 4438: stfdu %3,%2(%0)") 4439: 4440: ;; Next come insns related to the calling sequence. 4441: ;; 4442: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 4443: ;; We move the back-chain and decrement the stack pointer. 4444: 4445: (define_expand "allocate_stack" 4446: [(set (reg:SI 1) 4447: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] 4448: "" 4449: " 4450: { rtx chain = gen_reg_rtx (SImode); 4451: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); 4452: 4453: emit_move_insn (chain, stack_bot); 4454: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); 4455: emit_move_insn (stack_bot, chain); 4456: DONE; 4457: }") 4458: 4459: ;; These patterns say how to save and restore the stack pointer. We need not 4460: ;; save the stack pointer at function level since we are careful to 4461: ;; preserve the backchain. At block level, we have to restore the backchain 4462: ;; when we restore the stack pointer. 4463: ;; 4464: ;; For nonlocal gotos, we must save both the stack pointer and its 4465: ;; backchain and restore both. Note that in the nonlocal case, the 4466: ;; save area is a memory location. 4467: 4468: (define_expand "save_stack_function" 4469: [(use (const_int 0))] 4470: "" 4471: "") 4472: 4473: (define_expand "restore_stack_function" 4474: [(use (const_int 0))] 4475: "" 4476: "") 4477: 4478: (define_expand "restore_stack_block" 4479: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) 4480: (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) 4481: (set (mem:SI (match_dup 0)) (match_dup 2))] 4482: "" 4483: " 4484: { operands[2] = gen_reg_rtx (SImode); }") 4485: 4486: (define_expand "save_stack_nonlocal" 4487: [(match_operand:DI 0 "memory_operand" "") 4488: (match_operand:SI 1 "register_operand" "")] 4489: "" 4490: " 4491: { 4492: rtx temp = gen_reg_rtx (SImode); 4493: 4494: /* Copy the backchain to the first word, sp to the second. */ 4495: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); 4496: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); 4497: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); 4498: DONE; 4499: }") 4500: 4501: (define_expand "restore_stack_nonlocal" 4502: [(match_operand:SI 0 "register_operand" "") 4503: (match_operand:DI 1 "memory_operand" "")] 4504: "" 4505: " 4506: { 4507: rtx temp = gen_reg_rtx (SImode); 4508: 4509: /* Restore the backchain from the first word, sp from the second. */ 4510: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); 4511: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); 4512: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); 4513: DONE; 4514: }") 4515: 4516: ;; A function pointer is a pointer to a data area whose first word contains 4517: ;; the actual address of the function, whose second word contains a pointer 4518: ;; to its TOC, and whose third word contains a value to place in the static 4519: ;; chain register (r11). Note that if we load the static chain, our 4520: ;; "trampoline" need not have any executable code. 4521: ;; 4522: ;; operands[0] is an SImode pseudo in which we place the address of the 4523: ;; function. 4524: ;; operands[1] is the address of data area of the function to call 4525: 4526: (define_expand "call_via_ptr" 4527: [(set (match_operand:SI 0 "gpc_reg_operand" "") 4528: (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 4529: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 4530: (reg:SI 2)) 4531: (set (reg:SI 2) 4532: (mem:SI (plus:SI (match_dup 1) 4533: (const_int 4)))) 4534: (set (reg:SI 11) 4535: (mem:SI (plus:SI (match_dup 1) 4536: (const_int 8)))) 4537: (use (reg:SI 2)) 4538: (use (reg:SI 11))] 4539: "" 4540: "") 4541: 4542: (define_expand "call" 4543: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) 4544: (match_operand 1 "" "")) 4545: (clobber (scratch:SI))])] 4546: "" 4547: " 4548: { 4549: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 4550: abort (); 4551: 4552: operands[0] = XEXP (operands[0], 0); 4553: if (GET_CODE (operands[0]) != SYMBOL_REF) 4554: { 4555: rtx temp = gen_reg_rtx (SImode); 4556: 4557: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); 4558: operands[0] = temp; 4559: } 4560: }") 4561: 4562: (define_expand "call_value" 4563: [(parallel [(set (match_operand 0 "" "") 4564: (call (mem:SI (match_operand:SI 1 "address_operand" "")) 4565: (match_operand 2 "" ""))) 4566: (clobber (scratch:SI))])] 4567: "" 4568: " 4569: { 4570: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 4571: abort (); 4572: 4573: operands[1] = XEXP (operands[1], 0); 4574: if (GET_CODE (operands[1]) != SYMBOL_REF) 4575: { 4576: rtx temp = gen_reg_rtx (SImode); 4577: 4578: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); 4579: operands[1] = temp; 4580: } 4581: }") 4582: 1.1.1.2 root 4583: ;; Call to function in current module. No TOC pointer reload needed. 4584: 4585: (define_insn "" 4586: [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s")) 4587: (match_operand 1 "" "g")) 4588: (clobber (match_scratch:SI 2 "=l"))] 4589: "" 4590: "bl %z0") 4591: 4592: ;; Call to function which may be in another module. Restore the TOC 4593: ;; pointer (r2) after the call. 4594: 1.1 root 4595: (define_insn "" 4596: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) 4597: (match_operand 1 "" "fg,fg")) 4598: (clobber (match_scratch:SI 2 "=l,l"))] 4599: "" 4600: "@ 1.1.1.2 root 4601: {brl|blrl}\;{l|lwz} 2,20(1) 4602: bl %z0\;%." 4603: [(set_attr "length" "8")]) 4604: 4605: (define_insn "" 4606: [(set (match_operand 0 "" "=fg") 4607: (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s")) 4608: (match_operand 2 "" "g"))) 4609: (clobber (match_scratch:SI 3 "=l"))] 4610: "" 4611: "bl %z1") 1.1 root 4612: 4613: (define_insn "" 4614: [(set (match_operand 0 "" "=fg,fg") 4615: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) 4616: (match_operand 2 "" "fg,fg"))) 4617: (clobber (match_scratch:SI 3 "=l,l"))] 4618: "" 4619: "@ 1.1.1.2 root 4620: {brl|blrl}\;{l|lwz} 2,20(1) 4621: bl %z1\;%." 4622: [(set_attr "length" "8")]) 1.1 root 4623: 4624: ;; Call subroutine returning any type. 4625: 4626: (define_expand "untyped_call" 4627: [(parallel [(call (match_operand 0 "" "") 4628: (const_int 0)) 4629: (match_operand 1 "" "") 4630: (match_operand 2 "" "")])] 4631: "" 4632: " 4633: { 4634: int i; 4635: 4636: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 4637: 4638: for (i = 0; i < XVECLEN (operands[2], 0); i++) 4639: { 4640: rtx set = XVECEXP (operands[2], 0, i); 4641: emit_move_insn (SET_DEST (set), SET_SRC (set)); 4642: } 4643: 4644: /* The optimizer does not know that the call sets the function value 4645: registers we stored in the result block. We avoid problems by 4646: claiming that all hard registers are used and clobbered at this 4647: point. */ 4648: emit_insn (gen_blockage ()); 4649: 4650: DONE; 4651: }") 4652: 4653: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 4654: ;; all of memory. This blocks insns from being moved across this point. 4655: 4656: (define_insn "blockage" 4657: [(unspec_volatile [(const_int 0)] 0)] 4658: "" 4659: "") 4660: 4661: ;; Compare insns are next. Note that the RS/6000 has two types of compares, 4662: ;; signed & unsigned, and one type of branch. 4663: ;; 4664: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 4665: ;; insns, and branches. We store the operands of compares until we see 4666: ;; how it is used. 4667: (define_expand "cmpsi" 4668: [(set (cc0) 4669: (compare (match_operand:SI 0 "gpc_reg_operand" "") 4670: (match_operand:SI 1 "reg_or_short_operand" "")))] 4671: "" 4672: " 4673: { 4674: /* Take care of the possibility that operands[1] might be negative but 4675: this might be a logical operation. That insn doesn't exist. */ 4676: if (GET_CODE (operands[1]) == CONST_INT 4677: && INTVAL (operands[1]) < 0) 4678: operands[1] = force_reg (SImode, operands[1]); 4679: 4680: rs6000_compare_op0 = operands[0]; 4681: rs6000_compare_op1 = operands[1]; 4682: rs6000_compare_fp_p = 0; 4683: DONE; 4684: }") 4685: 4686: (define_expand "cmpsf" 4687: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") 4688: (match_operand:SF 1 "gpc_reg_operand" "")))] 4689: "" 4690: " 4691: { 4692: rs6000_compare_op0 = operands[0]; 4693: rs6000_compare_op1 = operands[1]; 4694: rs6000_compare_fp_p = 1; 4695: DONE; 4696: }") 4697: 4698: (define_expand "cmpdf" 4699: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") 4700: (match_operand:DF 1 "gpc_reg_operand" "")))] 4701: "" 4702: " 4703: { 4704: rs6000_compare_op0 = operands[0]; 4705: rs6000_compare_op1 = operands[1]; 4706: rs6000_compare_fp_p = 1; 4707: DONE; 4708: }") 4709: 4710: (define_expand "beq" 4711: [(set (match_dup 2) (match_dup 1)) 4712: (set (pc) 4713: (if_then_else (eq (match_dup 2) 4714: (const_int 0)) 4715: (label_ref (match_operand 0 "" "")) 4716: (pc)))] 4717: "" 4718: " 4719: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4720: operands[1] = gen_rtx (COMPARE, mode, 4721: rs6000_compare_op0, rs6000_compare_op1); 4722: operands[2] = gen_reg_rtx (mode); 4723: }") 4724: 4725: (define_expand "bne" 4726: [(set (match_dup 2) (match_dup 1)) 4727: (set (pc) 4728: (if_then_else (ne (match_dup 2) 4729: (const_int 0)) 4730: (label_ref (match_operand 0 "" "")) 4731: (pc)))] 4732: "" 4733: " 4734: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4735: operands[1] = gen_rtx (COMPARE, mode, 4736: rs6000_compare_op0, rs6000_compare_op1); 4737: operands[2] = gen_reg_rtx (mode); 4738: }") 4739: 4740: (define_expand "blt" 4741: [(set (match_dup 2) (match_dup 1)) 4742: (set (pc) 4743: (if_then_else (lt (match_dup 2) 4744: (const_int 0)) 4745: (label_ref (match_operand 0 "" "")) 4746: (pc)))] 4747: "" 4748: " 4749: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4750: operands[1] = gen_rtx (COMPARE, mode, 4751: rs6000_compare_op0, rs6000_compare_op1); 4752: operands[2] = gen_reg_rtx (mode); 4753: }") 4754: 4755: (define_expand "bgt" 4756: [(set (match_dup 2) (match_dup 1)) 4757: (set (pc) 4758: (if_then_else (gt (match_dup 2) 4759: (const_int 0)) 4760: (label_ref (match_operand 0 "" "")) 4761: (pc)))] 4762: "" 4763: " 4764: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4765: operands[1] = gen_rtx (COMPARE, mode, 4766: rs6000_compare_op0, rs6000_compare_op1); 4767: operands[2] = gen_reg_rtx (mode); 4768: }") 4769: 4770: (define_expand "ble" 4771: [(set (match_dup 2) (match_dup 1)) 4772: (set (pc) 4773: (if_then_else (le (match_dup 2) 4774: (const_int 0)) 4775: (label_ref (match_operand 0 "" "")) 4776: (pc)))] 4777: "" 4778: " 4779: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4780: operands[1] = gen_rtx (COMPARE, mode, 4781: rs6000_compare_op0, rs6000_compare_op1); 4782: operands[2] = gen_reg_rtx (mode); 4783: }") 4784: 4785: (define_expand "bge" 4786: [(set (match_dup 2) (match_dup 1)) 4787: (set (pc) 4788: (if_then_else (ge (match_dup 2) 4789: (const_int 0)) 4790: (label_ref (match_operand 0 "" "")) 4791: (pc)))] 4792: "" 4793: " 4794: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4795: operands[1] = gen_rtx (COMPARE, mode, 4796: rs6000_compare_op0, rs6000_compare_op1); 4797: operands[2] = gen_reg_rtx (mode); 4798: }") 4799: 4800: (define_expand "bgtu" 4801: [(set (match_dup 2) (match_dup 1)) 4802: (set (pc) 4803: (if_then_else (gtu (match_dup 2) 4804: (const_int 0)) 4805: (label_ref (match_operand 0 "" "")) 4806: (pc)))] 4807: "" 4808: " 4809: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4810: rs6000_compare_op0, rs6000_compare_op1); 4811: operands[2] = gen_reg_rtx (CCUNSmode); 4812: }") 4813: 4814: (define_expand "bltu" 4815: [(set (match_dup 2) (match_dup 1)) 4816: (set (pc) 4817: (if_then_else (ltu (match_dup 2) 4818: (const_int 0)) 4819: (label_ref (match_operand 0 "" "")) 4820: (pc)))] 4821: "" 4822: " 4823: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4824: rs6000_compare_op0, rs6000_compare_op1); 4825: operands[2] = gen_reg_rtx (CCUNSmode); 4826: }") 4827: 4828: (define_expand "bgeu" 4829: [(set (match_dup 2) (match_dup 1)) 4830: (set (pc) 4831: (if_then_else (geu (match_dup 2) 4832: (const_int 0)) 4833: (label_ref (match_operand 0 "" "")) 4834: (pc)))] 4835: "" 4836: " 4837: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4838: rs6000_compare_op0, rs6000_compare_op1); 4839: operands[2] = gen_reg_rtx (CCUNSmode); 4840: }") 4841: 4842: (define_expand "bleu" 4843: [(set (match_dup 2) (match_dup 1)) 4844: (set (pc) 4845: (if_then_else (leu (match_dup 2) 4846: (const_int 0)) 4847: (label_ref (match_operand 0 "" "")) 4848: (pc)))] 4849: "" 4850: " 4851: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4852: rs6000_compare_op0, rs6000_compare_op1); 4853: operands[2] = gen_reg_rtx (CCUNSmode); 4854: }") 4855: 4856: ;; For SNE, we would prefer that the xor/abs sequence be used for integers. 4857: ;; For SEQ, likewise, except that comparisons with zero should be done 4858: ;; with an scc insns. However, due to the order that combine see the 4859: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 4860: ;; the cases we don't want to handle. 4861: (define_expand "seq" 4862: [(set (match_dup 2) (match_dup 1)) 4863: (set (match_operand:SI 0 "gpc_reg_operand" "") 4864: (eq:SI (match_dup 2) (const_int 0)))] 4865: "" 4866: " 4867: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4868: operands[1] = gen_rtx (COMPARE, mode, 4869: rs6000_compare_op0, rs6000_compare_op1); 4870: operands[2] = gen_reg_rtx (mode); 4871: }") 4872: 4873: (define_expand "sne" 4874: [(set (match_dup 2) (match_dup 1)) 4875: (set (match_operand:SI 0 "gpc_reg_operand" "") 4876: (ne:SI (match_dup 2) (const_int 0)))] 4877: "" 4878: " 4879: { if (! rs6000_compare_fp_p) 4880: FAIL; 4881: 4882: operands[1] = gen_rtx (COMPARE, CCFPmode, 4883: rs6000_compare_op0, rs6000_compare_op1); 4884: operands[2] = gen_reg_rtx (CCFPmode); 4885: }") 4886: 4887: ;; A > 0 is best done using the portable sequence, so fail in that case. 4888: (define_expand "sgt" 4889: [(set (match_dup 2) (match_dup 1)) 4890: (set (match_operand:SI 0 "gpc_reg_operand" "") 4891: (gt:SI (match_dup 2) (const_int 0)))] 4892: "" 4893: " 4894: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4895: 4896: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 4897: FAIL; 4898: 4899: operands[1] = gen_rtx (COMPARE, mode, 4900: rs6000_compare_op0, rs6000_compare_op1); 4901: operands[2] = gen_reg_rtx (mode); 4902: }") 4903: 4904: ;; A < 0 is best done in the portable way for A an integer. 4905: (define_expand "slt" 4906: [(set (match_dup 2) (match_dup 1)) 4907: (set (match_operand:SI 0 "gpc_reg_operand" "") 4908: (lt:SI (match_dup 2) (const_int 0)))] 4909: "" 4910: " 4911: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4912: 4913: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 4914: FAIL; 4915: 4916: operands[1] = gen_rtx (COMPARE, mode, 4917: rs6000_compare_op0, rs6000_compare_op1); 4918: operands[2] = gen_reg_rtx (mode); 4919: }") 4920: 4921: (define_expand "sge" 4922: [(set (match_dup 2) (match_dup 1)) 4923: (set (match_operand:SI 0 "gpc_reg_operand" "") 4924: (ge:SI (match_dup 2) (const_int 0)))] 4925: "" 4926: " 4927: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4928: operands[1] = gen_rtx (COMPARE, mode, 4929: rs6000_compare_op0, rs6000_compare_op1); 4930: operands[2] = gen_reg_rtx (mode); 4931: }") 4932: 4933: ;; A <= 0 is best done the portable way for A an integer. 4934: (define_expand "sle" 4935: [(set (match_dup 2) (match_dup 1)) 4936: (set (match_operand:SI 0 "gpc_reg_operand" "") 4937: (le:SI (match_dup 2) (const_int 0)))] 4938: "" 4939: " 4940: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 4941: 4942: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 4943: FAIL; 4944: 4945: operands[1] = gen_rtx (COMPARE, mode, 4946: rs6000_compare_op0, rs6000_compare_op1); 4947: operands[2] = gen_reg_rtx (mode); 4948: }") 4949: 4950: (define_expand "sgtu" 4951: [(set (match_dup 2) (match_dup 1)) 4952: (set (match_operand:SI 0 "gpc_reg_operand" "") 4953: (gtu:SI (match_dup 2) (const_int 0)))] 4954: "" 4955: " 4956: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4957: rs6000_compare_op0, rs6000_compare_op1); 4958: operands[2] = gen_reg_rtx (CCUNSmode); 4959: }") 4960: 4961: (define_expand "sltu" 4962: [(set (match_dup 2) (match_dup 1)) 4963: (set (match_operand:SI 0 "gpc_reg_operand" "") 4964: (ltu:SI (match_dup 2) (const_int 0)))] 4965: "" 4966: " 4967: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4968: rs6000_compare_op0, rs6000_compare_op1); 4969: operands[2] = gen_reg_rtx (CCUNSmode); 4970: }") 4971: 4972: (define_expand "sgeu" 4973: [(set (match_dup 2) (match_dup 1)) 4974: (set (match_operand:SI 0 "gpc_reg_operand" "") 4975: (geu:SI (match_dup 2) (const_int 0)))] 4976: "" 4977: " 4978: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4979: rs6000_compare_op0, rs6000_compare_op1); 4980: operands[2] = gen_reg_rtx (CCUNSmode); 4981: }") 4982: 4983: (define_expand "sleu" 4984: [(set (match_dup 2) (match_dup 1)) 4985: (set (match_operand:SI 0 "gpc_reg_operand" "") 4986: (leu:SI (match_dup 2) (const_int 0)))] 4987: "" 4988: " 4989: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 4990: rs6000_compare_op0, rs6000_compare_op1); 4991: operands[2] = gen_reg_rtx (CCUNSmode); 4992: }") 4993: 4994: ;; Here are the actual compare insns. 4995: (define_insn "" 4996: [(set (match_operand:CC 0 "cc_reg_operand" "=y") 4997: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 4998: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 4999: "" 1.1.1.2 root 5000: "{cmp%I2|cmpw%I2} %0,%1,%2" 1.1 root 5001: [(set_attr "type" "compare")]) 5002: 5003: ;; If we are comparing a register for equality with a large constant, 5004: ;; we can do this with an XOR followed by a compare. But we need a scratch 5005: ;; register for the result of the XOR. 5006: 5007: (define_split 5008: [(set (match_operand:CC 0 "cc_reg_operand" "") 5009: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 5010: (match_operand:SI 2 "non_short_cint_operand" ""))) 5011: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 5012: "find_single_use (operands[0], insn, 0) 5013: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 5014: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 5015: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 5016: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 5017: " 5018: { 5019: /* Get the constant we are comparing against, C, and see what it looks like 5020: sign-extended to 16 bits. Then see what constant could be XOR'ed 5021: with C to get the sign-extended value. */ 5022: 5023: int c = INTVAL (operands[2]); 5024: int sextc = (c << 16) >> 16; 5025: int xorv = c ^ sextc; 5026: 5027: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); 5028: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); 5029: }") 5030: 5031: (define_insn "" 5032: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 5033: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 5034: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] 5035: "" 1.1.1.2 root 5036: "{cmpl%I2|cmplw%I2} %0,%1,%W2" 1.1 root 5037: [(set_attr "type" "compare")]) 5038: 5039: ;; The following two insns don't exist as single insns, but if we provide 5040: ;; them, we can swap an add and compare, which will enable us to overlap more 5041: ;; of the required delay between a compare and branch. We generate code for 5042: ;; them by splitting. 5043: 5044: (define_insn "" 5045: [(set (match_operand:CC 3 "cc_reg_operand" "=y") 5046: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 5047: (match_operand:SI 2 "short_cint_operand" "i"))) 5048: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5049: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 5050: "" 1.1.1.2 root 5051: "#" 5052: [(set_attr "length" "8")]) 1.1 root 5053: 5054: (define_insn "" 5055: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 5056: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 5057: (match_operand:SI 2 "u_short_cint_operand" "i"))) 5058: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5059: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 5060: "" 1.1.1.2 root 5061: "#" 5062: [(set_attr "length" "8")]) 1.1 root 5063: 5064: (define_split 5065: [(set (match_operand:CC 3 "cc_reg_operand" "") 5066: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 5067: (match_operand:SI 2 "short_cint_operand" ""))) 5068: (set (match_operand:SI 0 "gpc_reg_operand" "") 5069: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 5070: "" 5071: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 5072: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 5073: 5074: (define_split 5075: [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 5076: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 5077: (match_operand:SI 2 "u_short_cint_operand" ""))) 5078: (set (match_operand:SI 0 "gpc_reg_operand" "") 5079: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 5080: "" 5081: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 5082: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 5083: 5084: (define_insn "" 5085: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 5086: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 5087: (match_operand:SF 2 "gpc_reg_operand" "f")))] 5088: "" 5089: "fcmpu %0,%1,%2" 5090: [(set_attr "type" "fpcompare")]) 5091: 5092: (define_insn "" 5093: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 5094: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 5095: (match_operand:DF 2 "gpc_reg_operand" "f")))] 5096: "" 5097: "fcmpu %0,%1,%2" 5098: [(set_attr "type" "fpcompare")]) 5099: 5100: ;; Now we have the scc insns. We can do some combinations because of the 5101: ;; way the machine works. 5102: ;; 5103: ;; Note that this is probably faster if we can put an insn between the 5104: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 5105: ;; cases the insns below which don't use an intermediate CR field will 5106: ;; be used instead. 5107: (define_insn "" 5108: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5109: (match_operator:SI 1 "scc_comparison_operator" 5110: [(match_operand 2 "cc_reg_operand" "y") 5111: (const_int 0)]))] 5112: "" 1.1.1.2 root 5113: "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" 5114: [(set_attr "length" "12")]) 1.1 root 5115: 5116: (define_insn "" 5117: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5118: (compare:CC (match_operator:SI 1 "scc_comparison_operator" 5119: [(match_operand 2 "cc_reg_operand" "y") 5120: (const_int 0)]) 5121: (const_int 0))) 5122: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 5123: (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 5124: "" 1.1.1.2 root 5125: "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" 5126: [(set_attr "type" "delayed_compare") 5127: (set_attr "length" "12")]) 1.1 root 5128: 5129: (define_insn "" 5130: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5131: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 5132: [(match_operand 2 "cc_reg_operand" "y") 5133: (const_int 0)]) 5134: (match_operand:SI 3 "const_int_operand" "n")))] 5135: "" 5136: "* 5137: { 5138: int is_bit = ccr_bit (operands[1], 1); 5139: int put_bit = 31 - (INTVAL (operands[3]) & 31); 5140: int count; 5141: 5142: if (is_bit >= put_bit) 5143: count = is_bit - put_bit; 5144: else 5145: count = 32 - (put_bit - is_bit); 5146: 5147: operands[4] = gen_rtx (CONST_INT, VOIDmode, count); 5148: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); 5149: 1.1.1.2 root 5150: return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 5151: }" 5152: [(set_attr "length" "12")]) 1.1 root 5153: 5154: (define_insn "" 5155: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5156: (compare:CC 5157: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 5158: [(match_operand 2 "cc_reg_operand" "y") 5159: (const_int 0)]) 5160: (match_operand:SI 3 "const_int_operand" "n")) 5161: (const_int 0))) 5162: (set (match_operand:SI 4 "gpc_reg_operand" "=r") 5163: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 5164: (match_dup 3)))] 5165: "" 5166: "* 5167: { 5168: int is_bit = ccr_bit (operands[1], 1); 5169: int put_bit = 31 - (INTVAL (operands[3]) & 31); 5170: int count; 5171: 5172: if (is_bit >= put_bit) 5173: count = is_bit - put_bit; 5174: else 5175: count = 32 - (put_bit - is_bit); 5176: 5177: operands[5] = gen_rtx (CONST_INT, VOIDmode, count); 5178: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); 5179: 1.1.1.2 root 5180: return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 1.1 root 5181: }" 1.1.1.2 root 5182: [(set_attr "type" "delayed_compare") 5183: (set_attr "length" "12")]) 1.1 root 5184: 5185: ;; If we are comparing the result of two comparisons, this can be done 5186: ;; using creqv or crxor. 5187: 5188: (define_insn "" 5189: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 5190: (compare:CCEQ (match_operator 1 "scc_comparison_operator" 5191: [(match_operand 2 "cc_reg_operand" "y") 5192: (const_int 0)]) 5193: (match_operator 3 "scc_comparison_operator" 5194: [(match_operand 4 "cc_reg_operand" "y") 5195: (const_int 0)])))] 5196: "REGNO (operands[2]) != REGNO (operands[4])" 5197: "* 5198: { 5199: enum rtx_code code1, code2; 5200: 5201: code1 = GET_CODE (operands[1]); 5202: code2 = GET_CODE (operands[3]); 5203: 5204: if ((code1 == EQ || code1 == LT || code1 == GT 5205: || code1 == LTU || code1 == GTU 5206: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) 5207: != 5208: (code2 == EQ || code2 == LT || code2 == GT 5209: || code2 == LTU || code2 == GTU 5210: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) 5211: return \"%C1%C3crxor %E0,%j1,%j3\"; 5212: else 5213: return \"%C1%C3creqv %E0,%j1,%j3\"; 1.1.1.2 root 5214: }" 5215: [(set_attr "length" "12")]) 1.1 root 5216: 5217: ;; There is a 3 cycle delay between consecutive mfcr instructions 5218: ;; so it is useful to combine 2 scc instructions to use only one mfcr. 5219: 5220: (define_peephole 5221: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5222: (match_operator:SI 1 "scc_comparison_operator" 5223: [(match_operand 2 "cc_reg_operand" "y") 5224: (const_int 0)])) 5225: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 5226: (match_operator:SI 4 "scc_comparison_operator" 5227: [(match_operand 5 "cc_reg_operand" "y") 5228: (const_int 0)]))] 5229: "REGNO (operands[2]) != REGNO (operands[5])" 1.1.1.2 root 5230: "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 5231: [(set_attr "length" "20")]) 1.1 root 5232: 5233: ;; There are some scc insns that can be done directly, without a compare. 5234: ;; These are faster because they don't involve the communications between 5235: ;; the FXU and branch units. In fact, we will be replacing all of the 5236: ;; integer scc insns here or in the portable methods in emit_store_flag. 5237: ;; 5238: ;; Also support (neg (scc ..)) since that construct is used to replace 5239: ;; branches, (plus (scc ..) ..) since that construct is common and 5240: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 5241: ;; cases where it is no more expensive than (neg (scc ..)). 5242: 5243: ;; Have reload force a constant into a register for the simple insns that 5244: ;; otherwise won't accept constants. We do this because it is faster than 5245: ;; the cmp/mfcr sequence we would otherwise generate. 5246: 5247: (define_insn "" 5248: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 5249: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 5250: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) 5251: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 5252: "" 5253: "@ 1.1.1.2 root 5254: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 5255: {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 5256: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 5257: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 5258: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 5259: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 5260: 5261: (define_insn "" 5262: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") 5263: (compare:CC 5264: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 5265: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 5266: (const_int 0))) 5267: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 5268: (eq:SI (match_dup 1) (match_dup 2))) 5269: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 5270: "" 5271: "@ 1.1.1.2 root 5272: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 5273: {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 5274: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 5275: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 5276: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" 5277: [(set_attr "type" "compare") 5278: (set_attr "length" "12,8,12,12,12")]) 5279: 5280: ;; We have insns of the form shown by the first define_insn below. If 5281: ;; there is something inside the comparison operation, we must split it. 5282: (define_split 5283: [(set (match_operand:SI 0 "gpc_reg_operand" "") 5284: (plus:SI (match_operator 1 "comparison_operator" 5285: [(match_operand:SI 2 "" "") 5286: (match_operand:SI 3 5287: "reg_or_cint_operand" "")]) 5288: (match_operand:SI 4 "gpc_reg_operand" ""))) 5289: (clobber (match_operand:SI 5 "register_operand" ""))] 5290: "! gpc_reg_operand (operands[2], SImode)" 5291: [(set (match_dup 5) (match_dup 2)) 5292: (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 5293: (match_dup 4)))]) 1.1 root 5294: 5295: (define_insn "" 5296: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 5297: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 5298: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 5299: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) 5300: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 5301: "" 5302: "@ 1.1.1.2 root 5303: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 5304: {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 5305: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 5306: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 5307: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 5308: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 5309: 5310: (define_insn "" 5311: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") 5312: (compare:CC 5313: (plus:SI 5314: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 5315: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 5316: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 5317: (const_int 0))) 5318: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 5319: "" 5320: "@ 1.1.1.2 root 5321: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 5322: {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 5323: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 5324: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 5325: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 5326: [(set_attr "type" "compare") 5327: (set_attr "length" "12,8,12,12,12")]) 1.1 root 5328: 5329: (define_insn "" 5330: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") 5331: (compare:CC 5332: (plus:SI 5333: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 5334: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 5335: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 5336: (const_int 0))) 5337: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 5338: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5339: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 5340: "" 5341: "@ 1.1.1.2 root 5342: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 5343: {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 5344: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 5345: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 5346: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 5347: [(set_attr "type" "compare") 5348: (set_attr "length" "12,8,12,12,12")]) 1.1 root 5349: 5350: (define_insn "" 5351: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 1.1.1.3 ! root 5352: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 1.1 root 5353: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] 5354: "" 5355: "@ 1.1.1.2 root 5356: xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 5357: {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 5358: {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 5359: {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 5360: {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 5361: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 5362: 5363: ;; This is what (plus (ne X (const_int 0)) Y) looks like. 5364: (define_insn "" 5365: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5366: (plus:SI (lshiftrt:SI 5367: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 5368: (const_int 31)) 5369: (match_operand:SI 2 "gpc_reg_operand" "r"))) 5370: (clobber (match_scratch:SI 3 "=&r"))] 5371: "" 1.1.1.2 root 5372: "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 5373: [(set_attr "length" "8")]) 1.1 root 5374: 5375: (define_insn "" 5376: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5377: (compare:CC 5378: (plus:SI (lshiftrt:SI 5379: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 5380: (const_int 31)) 5381: (match_operand:SI 2 "gpc_reg_operand" "r")) 5382: (const_int 0))) 5383: (clobber (match_scratch:SI 3 "=&r"))] 5384: "" 1.1.1.2 root 5385: "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" 5386: [(set_attr "type" "compare") 5387: (set_attr "length" "8")]) 1.1 root 5388: 5389: (define_insn "" 5390: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 5391: (compare:CC 5392: (plus:SI (lshiftrt:SI 5393: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 5394: (const_int 31)) 5395: (match_operand:SI 2 "gpc_reg_operand" "r")) 5396: (const_int 0))) 5397: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5398: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 5399: (match_dup 2))) 5400: (clobber (match_scratch:SI 3 "=&r"))] 5401: "" 1.1.1.2 root 5402: "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" 5403: [(set_attr "type" "compare") 5404: (set_attr "length" "8")]) 1.1 root 5405: 5406: (define_insn "" 5407: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5408: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5409: (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 5410: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 5411: "TARGET_POWER" 1.1 root 5412: "@ 1.1.1.2 root 5413: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 5414: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 5415: [(set_attr "length" "12")]) 1.1 root 5416: 5417: (define_insn "" 5418: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") 5419: (compare:CC 5420: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5421: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 5422: (const_int 0))) 5423: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5424: (le:SI (match_dup 1) (match_dup 2))) 5425: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 5426: "TARGET_POWER" 1.1 root 5427: "@ 1.1.1.2 root 5428: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 5429: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" 1.1.1.3 ! root 5430: [(set_attr "type" "compare,delayed_compare") 1.1.1.2 root 5431: (set_attr "length" "12")]) 1.1 root 5432: 5433: (define_insn "" 5434: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5435: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5436: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 5437: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 5438: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 5439: "TARGET_POWER" 1.1 root 5440: "@ 1.1.1.2 root 5441: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 5442: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" 5443: [(set_attr "length" "12")]) 1.1 root 5444: 5445: (define_insn "" 5446: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 5447: (compare:CC 5448: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5449: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 5450: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5451: (const_int 0))) 5452: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 5453: "TARGET_POWER" 1.1 root 5454: "@ 1.1.1.2 root 5455: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 5456: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" 5457: [(set_attr "type" "compare") 5458: (set_attr "length" "12")]) 1.1 root 5459: 5460: (define_insn "" 5461: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 5462: (compare:CC 5463: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5464: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 5465: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5466: (const_int 0))) 5467: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5468: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5469: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 5470: "TARGET_POWER" 1.1 root 5471: "@ 1.1.1.2 root 5472: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 5473: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" 5474: [(set_attr "type" "compare") 5475: (set_attr "length" "12")]) 1.1 root 5476: 5477: (define_insn "" 5478: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5479: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5480: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 1.1.1.2 root 5481: "TARGET_POWER" 1.1 root 5482: "@ 1.1.1.2 root 5483: doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 5484: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 5485: [(set_attr "length" "12")]) 1.1 root 5486: 5487: (define_insn "" 5488: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5489: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5490: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 5491: "" 1.1.1.2 root 5492: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 5493: [(set_attr "length" "12")]) 1.1 root 5494: 5495: (define_insn "" 5496: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 5497: (compare:CC 5498: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5499: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5500: (const_int 0))) 5501: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5502: (leu:SI (match_dup 1) (match_dup 2)))] 5503: "" 1.1.1.2 root 5504: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 5505: [(set_attr "type" "compare") 5506: (set_attr "length" "12")]) 1.1 root 5507: 5508: (define_insn "" 5509: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5510: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5511: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5512: (match_operand:SI 3 "gpc_reg_operand" "r"))) 5513: (clobber (match_scratch:SI 4 "=&r"))] 5514: "" 1.1.1.2 root 5515: "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" 5516: [(set_attr "length" "8")]) 1.1 root 5517: 5518: (define_insn "" 5519: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5520: (compare:CC 5521: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5522: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5523: (match_operand:SI 3 "gpc_reg_operand" "r")) 5524: (const_int 0))) 5525: (clobber (match_scratch:SI 4 "=&r"))] 5526: "" 1.1.1.2 root 5527: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" 5528: [(set_attr "type" "compare") 5529: (set_attr "length" "8")]) 1.1 root 5530: 5531: (define_insn "" 5532: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 5533: (compare:CC 5534: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5535: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5536: (match_operand:SI 3 "gpc_reg_operand" "r")) 5537: (const_int 0))) 5538: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5539: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5540: (clobber (match_scratch:SI 4 "=&r"))] 5541: "" 1.1.1.2 root 5542: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" 5543: [(set_attr "type" "compare") 5544: (set_attr "length" "8")]) 1.1 root 5545: 5546: (define_insn "" 5547: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5548: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5549: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 5550: "" 1.1.1.2 root 5551: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 5552: [(set_attr "length" "12")]) 1.1 root 5553: 5554: (define_insn "" 5555: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5556: (and:SI (neg:SI 5557: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5558: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 5559: (match_operand:SI 3 "gpc_reg_operand" "r"))) 5560: (clobber (match_scratch:SI 4 "=&r"))] 5561: "" 1.1.1.2 root 5562: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 5563: [(set_attr "length" "12")]) 1.1 root 5564: 5565: (define_insn "" 5566: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5567: (compare:CC 5568: (and:SI (neg:SI 5569: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5570: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 5571: (match_operand:SI 3 "gpc_reg_operand" "r")) 5572: (const_int 0))) 5573: (clobber (match_scratch:SI 4 "=&r"))] 5574: "" 1.1.1.2 root 5575: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 5576: [(set_attr "type" "compare") 5577: (set_attr "length" "12")]) 1.1 root 5578: 5579: (define_insn "" 5580: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 5581: (compare:CC 5582: (and:SI (neg:SI 5583: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5584: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 5585: (match_operand:SI 3 "gpc_reg_operand" "r")) 5586: (const_int 0))) 5587: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5588: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 5589: (clobber (match_scratch:SI 4 "=&r"))] 5590: "" 1.1.1.2 root 5591: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 5592: [(set_attr "type" "compare") 5593: (set_attr "length" "12")]) 1.1 root 5594: 5595: (define_insn "" 5596: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5597: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5598: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 1.1.1.2 root 5599: "TARGET_POWER" 5600: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 5601: [(set_attr "length" "12")]) 1.1 root 5602: 5603: (define_insn "" 1.1.1.3 ! root 5604: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1 root 5605: (compare:CC 5606: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5607: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5608: (const_int 0))) 5609: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5610: (lt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 5611: "TARGET_POWER" 5612: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 5613: [(set_attr "type" "delayed_compare") 5614: (set_attr "length" "12")]) 1.1 root 5615: 5616: (define_insn "" 5617: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5618: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5619: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5620: (match_operand:SI 3 "gpc_reg_operand" "r"))) 5621: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5622: "TARGET_POWER" 5623: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 5624: [(set_attr "length" "12")]) 1.1 root 5625: 5626: (define_insn "" 1.1.1.3 ! root 5627: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1 root 5628: (compare:CC 5629: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5630: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5631: (match_operand:SI 3 "gpc_reg_operand" "r")) 5632: (const_int 0))) 5633: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5634: "TARGET_POWER" 5635: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 5636: [(set_attr "type" "compare") 5637: (set_attr "length" "12")]) 1.1 root 5638: 5639: (define_insn "" 1.1.1.3 ! root 5640: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 1.1 root 5641: (compare:CC 5642: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5643: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5644: (match_operand:SI 3 "gpc_reg_operand" "r")) 5645: (const_int 0))) 5646: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5647: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5648: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5649: "TARGET_POWER" 5650: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 5651: [(set_attr "type" "compare") 5652: (set_attr "length" "12")]) 1.1 root 5653: 5654: (define_insn "" 5655: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5656: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5657: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 5658: "TARGET_POWER" 5659: "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 5660: [(set_attr "length" "12")]) 1.1 root 5661: 5662: (define_insn "" 5663: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5664: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5665: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 5666: "" 5667: "@ 1.1.1.2 root 5668: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 5669: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 5670: [(set_attr "length" "12")]) 1.1 root 5671: 5672: (define_insn "" 5673: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 5674: (compare:CC 5675: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5676: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5677: (const_int 0))) 5678: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5679: (ltu:SI (match_dup 1) (match_dup 2)))] 5680: "" 5681: "@ 1.1.1.2 root 5682: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 5683: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 5684: [(set_attr "type" "compare") 5685: (set_attr "length" "12")]) 1.1 root 5686: 5687: (define_insn "" 5688: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 5689: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 5690: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) 5691: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) 5692: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] 5693: "" 5694: "@ 1.1.1.2 root 5695: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 5696: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 5697: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 5698: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 5699: [(set_attr "length" "12")]) 1.1 root 5700: 5701: (define_insn "" 1.1.1.2 root 5702: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 5703: (compare:CC 1.1.1.2 root 5704: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5705: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5706: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 5707: (const_int 0))) 1.1.1.2 root 5708: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 5709: "" 5710: "@ 1.1.1.2 root 5711: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 5712: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" 5713: [(set_attr "type" "compare") 5714: (set_attr "length" "12")]) 1.1 root 5715: 5716: (define_insn "" 1.1.1.2 root 5717: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 5718: (compare:CC 1.1.1.2 root 5719: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5720: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5721: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 5722: (const_int 0))) 1.1.1.2 root 5723: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 5724: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 5725: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 5726: "" 5727: "@ 1.1.1.2 root 5728: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 5729: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 5730: [(set_attr "type" "compare") 5731: (set_attr "length" "12")]) 1.1 root 5732: 5733: (define_insn "" 5734: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5735: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5736: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] 5737: "" 5738: "@ 1.1.1.2 root 5739: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 5740: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 5741: [(set_attr "length" "8")]) 1.1 root 5742: 5743: (define_insn "" 5744: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5745: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5746: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 5747: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 5748: "TARGET_POWER" 5749: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 5750: [(set_attr "length" "12")]) 1.1 root 5751: 5752: (define_insn "" 5753: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 5754: (compare:CC 5755: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5756: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5757: (const_int 0))) 5758: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5759: (ge:SI (match_dup 1) (match_dup 2))) 5760: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 5761: "TARGET_POWER" 5762: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" 5763: [(set_attr "type" "compare") 5764: (set_attr "length" "12")]) 1.1 root 5765: 5766: (define_insn "" 5767: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5768: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5769: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5770: (match_operand:SI 3 "gpc_reg_operand" "r"))) 5771: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5772: "TARGET_POWER" 5773: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 5774: [(set_attr "length" "12")]) 1.1 root 5775: 5776: (define_insn "" 5777: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5778: (compare:CC 5779: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5780: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5781: (match_operand:SI 3 "gpc_reg_operand" "r")) 5782: (const_int 0))) 5783: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5784: "TARGET_POWER" 5785: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 5786: [(set_attr "type" "compare") 5787: (set_attr "length" "12")]) 1.1 root 5788: 5789: (define_insn "" 5790: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 5791: (compare:CC 5792: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5793: (match_operand:SI 2 "reg_or_short_operand" "rI")) 5794: (match_operand:SI 3 "gpc_reg_operand" "r")) 5795: (const_int 0))) 5796: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5797: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5798: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 5799: "TARGET_POWER" 5800: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 5801: [(set_attr "type" "compare") 5802: (set_attr "length" "12")]) 1.1 root 5803: 5804: (define_insn "" 5805: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5806: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5807: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 5808: "TARGET_POWER" 5809: "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 5810: [(set_attr "length" "12")]) 1.1 root 5811: 5812: ;; This is (and (neg (ge X (const_int 0))) Y). 5813: (define_insn "" 5814: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5815: (and:SI (neg:SI 5816: (lshiftrt:SI 5817: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 5818: (const_int 31))) 5819: (match_operand:SI 2 "gpc_reg_operand" "r"))) 5820: (clobber (match_scratch:SI 3 "=&r"))] 5821: "" 1.1.1.2 root 5822: "{srai|srawi} %3,%1,31\;andc %0,%2,%3" 5823: [(set_attr "length" "8")]) 1.1 root 5824: 5825: (define_insn "" 5826: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 5827: (compare:CC 5828: (and:SI (neg:SI 5829: (lshiftrt:SI 5830: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 5831: (const_int 31))) 5832: (match_operand:SI 2 "gpc_reg_operand" "r")) 5833: (const_int 0))) 5834: (clobber (match_scratch:SI 3 "=&r"))] 5835: "" 1.1.1.2 root 5836: "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" 5837: [(set_attr "type" "compare") 5838: (set_attr "length" "8")]) 1.1 root 5839: 5840: (define_insn "" 5841: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 5842: (compare:CC 5843: (and:SI (neg:SI 5844: (lshiftrt:SI 5845: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 5846: (const_int 31))) 5847: (match_operand:SI 2 "gpc_reg_operand" "r")) 5848: (const_int 0))) 5849: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 5850: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) 5851: (const_int 31))) 5852: (match_dup 2))) 5853: (clobber (match_scratch:SI 3 "=&r"))] 5854: "" 1.1.1.2 root 5855: "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" 5856: [(set_attr "type" "compare") 5857: (set_attr "length" "8")]) 1.1 root 5858: 5859: (define_insn "" 5860: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5861: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5862: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 5863: "" 5864: "@ 1.1.1.2 root 5865: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 5866: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 5867: [(set_attr "length" "12")]) 1.1 root 5868: 5869: (define_insn "" 5870: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 5871: (compare:CC 5872: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5873: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5874: (const_int 0))) 5875: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5876: (geu:SI (match_dup 1) (match_dup 2)))] 5877: "" 5878: "@ 1.1.1.2 root 5879: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 5880: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 5881: [(set_attr "type" "compare") 5882: (set_attr "length" "12")]) 1.1 root 5883: 5884: (define_insn "" 5885: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5886: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5887: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5888: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 5889: (clobber (match_scratch:SI 4 "=&r,&r"))] 5890: "" 5891: "@ 1.1.1.2 root 5892: {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 5893: {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" 5894: [(set_attr "length" "8")]) 1.1 root 5895: 5896: (define_insn "" 5897: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 5898: (compare:CC 5899: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5900: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5901: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5902: (const_int 0))) 5903: (clobber (match_scratch:SI 4 "=&r,&r"))] 5904: "" 5905: "@ 1.1.1.2 root 5906: {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 5907: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 5908: [(set_attr "type" "compare") 5909: (set_attr "length" "8")]) 1.1 root 5910: 5911: (define_insn "" 5912: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 5913: (compare:CC 5914: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5915: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 5916: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5917: (const_int 0))) 5918: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5919: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 5920: (clobber (match_scratch:SI 4 "=&r,&r"))] 5921: "" 5922: "@ 1.1.1.2 root 5923: {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 5924: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 5925: [(set_attr "type" "compare") 5926: (set_attr "length" "8")]) 1.1 root 5927: 5928: (define_insn "" 5929: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5930: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5931: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] 5932: "" 5933: "@ 1.1.1.2 root 5934: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 5935: {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0" 5936: [(set_attr "length" "12")]) 1.1 root 5937: 5938: (define_insn "" 5939: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5940: (and:SI (neg:SI 5941: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5942: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 5943: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 5944: (clobber (match_scratch:SI 4 "=&r,&r"))] 5945: "" 5946: "@ 1.1.1.2 root 5947: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 5948: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 5949: [(set_attr "length" "12")]) 1.1 root 5950: 5951: (define_insn "" 5952: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 5953: (compare:CC 5954: (and:SI (neg:SI 5955: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5956: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 5957: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5958: (const_int 0))) 5959: (clobber (match_scratch:SI 4 "=&r,&r"))] 5960: "" 5961: "@ 1.1.1.2 root 5962: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 5963: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 5964: [(set_attr "type" "compare") 5965: (set_attr "length" "12")]) 1.1 root 5966: 5967: (define_insn "" 5968: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 5969: (compare:CC 5970: (and:SI (neg:SI 5971: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 5972: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 5973: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5974: (const_int 0))) 5975: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 5976: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 5977: (clobber (match_scratch:SI 4 "=&r,&r"))] 5978: "" 5979: "@ 1.1.1.2 root 5980: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 5981: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 5982: [(set_attr "type" "compare") 5983: (set_attr "length" "12")]) 1.1 root 5984: 5985: (define_insn "" 5986: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5987: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5988: (const_int 0)))] 5989: "" 1.1.1.2 root 5990: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" 5991: [(set_attr "length" "12")]) 1.1 root 5992: 5993: (define_insn "" 5994: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 5995: (compare:CC 5996: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 5997: (const_int 0)) 5998: (const_int 0))) 5999: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6000: (gt:SI (match_dup 1) (const_int 0)))] 6001: "" 1.1.1.2 root 6002: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" 6003: [(set_attr "type" "delayed_compare") 6004: (set_attr "length" "12")]) 1.1 root 6005: 6006: (define_insn "" 6007: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6008: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6009: (match_operand:SI 2 "reg_or_short_operand" "r")))] 1.1.1.2 root 6010: "TARGET_POWER" 6011: "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 6012: [(set_attr "length" "12")]) 1.1 root 6013: 6014: (define_insn "" 6015: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 6016: (compare:CC 6017: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6018: (match_operand:SI 2 "reg_or_short_operand" "r")) 6019: (const_int 0))) 6020: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6021: (gt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 6022: "TARGET_POWER" 6023: "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 6024: [(set_attr "type" "delayed_compare") 6025: (set_attr "length" "12")]) 1.1 root 6026: 6027: (define_insn "" 6028: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6029: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6030: (const_int 0)) 6031: (match_operand:SI 2 "gpc_reg_operand" "r"))) 6032: (clobber (match_scratch:SI 3 "=&r"))] 6033: "" 1.1.1.2 root 6034: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" 6035: [(set_attr "length" "12")]) 1.1 root 6036: 6037: (define_insn "" 6038: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6039: (compare:CC 6040: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6041: (const_int 0)) 6042: (match_operand:SI 2 "gpc_reg_operand" "r")) 6043: (const_int 0))) 6044: (clobber (match_scratch:SI 3 "=&r"))] 6045: "" 1.1.1.2 root 6046: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" 6047: [(set_attr "type" "compare") 6048: (set_attr "length" "12")]) 1.1 root 6049: 6050: (define_insn "" 6051: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6052: (compare:CC 6053: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6054: (const_int 0)) 6055: (match_operand:SI 2 "gpc_reg_operand" "r")) 6056: (const_int 0))) 6057: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6058: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 6059: (clobber (match_scratch:SI 3 "=&r"))] 6060: "" 1.1.1.2 root 6061: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" 6062: [(set_attr "type" "compare") 6063: (set_attr "length" "12")]) 1.1 root 6064: 6065: (define_insn "" 6066: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6067: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6068: (match_operand:SI 2 "reg_or_short_operand" "r")) 6069: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6070: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6071: "TARGET_POWER" 6072: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 6073: [(set_attr "length" "12")]) 1.1 root 6074: 6075: (define_insn "" 6076: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6077: (compare:CC 6078: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6079: (match_operand:SI 2 "reg_or_short_operand" "r")) 6080: (match_operand:SI 3 "gpc_reg_operand" "r")) 6081: (const_int 0))) 6082: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6083: "TARGET_POWER" 6084: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 6085: [(set_attr "type" "compare") 6086: (set_attr "length" "12")]) 1.1 root 6087: 6088: (define_insn "" 6089: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6090: (compare:CC 6091: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6092: (match_operand:SI 2 "reg_or_short_operand" "r")) 6093: (match_operand:SI 3 "gpc_reg_operand" "r")) 6094: (const_int 0))) 6095: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6096: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6097: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6098: "TARGET_POWER" 6099: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 6100: [(set_attr "type" "compare") 6101: (set_attr "length" "12")]) 1.1 root 6102: 6103: (define_insn "" 6104: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6105: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6106: (const_int 0))))] 6107: "" 1.1.1.2 root 6108: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" 6109: [(set_attr "length" "12")]) 1.1 root 6110: 6111: (define_insn "" 6112: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6113: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6114: (match_operand:SI 2 "reg_or_short_operand" "r"))))] 1.1.1.2 root 6115: "TARGET_POWER" 6116: "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 6117: [(set_attr "length" "12")]) 1.1 root 6118: 6119: (define_insn "" 6120: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6121: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6122: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 6123: "" 1.1.1.2 root 6124: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 6125: [(set_attr "length" "12")]) 1.1 root 6126: 6127: (define_insn "" 6128: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 6129: (compare:CC 6130: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6131: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6132: (const_int 0))) 6133: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6134: (gtu:SI (match_dup 1) (match_dup 2)))] 6135: "" 1.1.1.2 root 6136: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 6137: [(set_attr "type" "compare") 6138: (set_attr "length" "12")]) 1.1 root 6139: 6140: (define_insn "" 6141: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 6142: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 6143: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) 6144: (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) 6145: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] 6146: "" 6147: "@ 1.1.1.2 root 6148: {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 6149: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6150: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 6151: [(set_attr "length" "8,12,12")]) 1.1 root 6152: 6153: (define_insn "" 1.1.1.2 root 6154: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 6155: (compare:CC 1.1.1.2 root 6156: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6157: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 6158: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6159: (const_int 0))) 1.1.1.2 root 6160: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6161: "" 6162: "@ 1.1.1.2 root 6163: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 6164: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 6165: [(set_attr "type" "compare") 6166: (set_attr "length" "8,12")]) 1.1 root 6167: 6168: (define_insn "" 1.1.1.2 root 6169: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 6170: (compare:CC 1.1.1.2 root 6171: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6172: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 6173: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6174: (const_int 0))) 1.1.1.2 root 6175: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 6176: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 6177: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6178: "" 6179: "@ 1.1.1.2 root 6180: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 6181: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 6182: [(set_attr "type" "compare") 6183: (set_attr "length" "8,12")]) 1.1 root 6184: 6185: (define_insn "" 6186: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6187: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6188: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 6189: "" 1.1.1.2 root 6190: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 6191: [(set_attr "length" "8")]) 1.1 root 6192: 6193: ;; Define both directions of branch and return. If we need a reload 6194: ;; register, we'd rather use CR0 since it is much easier to copy a 6195: ;; register CC value to there. 6196: 6197: (define_insn "" 6198: [(set (pc) 6199: (if_then_else (match_operator 1 "branch_comparison_operator" 6200: [(match_operand 2 6201: "cc_reg_operand" "x,?y") 6202: (const_int 0)]) 6203: (label_ref (match_operand 0 "" "")) 6204: (pc)))] 6205: "" 1.1.1.2 root 6206: "* 6207: { 6208: if (get_attr_length (insn) == 8) 6209: return \"%C1bc %t1,%j1,%l0\"; 6210: else 6211: return \"%C1bc %T1,%j1,$+8\;b %l0\"; 6212: }" 6213: [(set_attr "type" "branch")]) 6214: 1.1 root 6215: (define_insn "" 6216: [(set (pc) 6217: (if_then_else (match_operator 0 "branch_comparison_operator" 6218: [(match_operand 1 6219: "cc_reg_operand" "x,?y") 6220: (const_int 0)]) 6221: (return) 6222: (pc)))] 6223: "direct_return ()" 1.1.1.2 root 6224: "{%C0bcr|%C0bclr} %t0,%j0" 6225: [(set_attr "length" "8")]) 1.1 root 6226: 6227: (define_insn "" 6228: [(set (pc) 6229: (if_then_else (match_operator 1 "branch_comparison_operator" 6230: [(match_operand 2 6231: "cc_reg_operand" "x,?y") 6232: (const_int 0)]) 6233: (pc) 6234: (label_ref (match_operand 0 "" ""))))] 6235: "" 1.1.1.2 root 6236: "* 6237: { 6238: if (get_attr_length (insn) == 8) 6239: return \"%C1bc %T1,%j1,%l0\"; 6240: else 6241: return \"%C1bc %t1,%j1,$+8\;b %l0\"; 6242: }" 6243: [(set_attr "type" "branch")]) 1.1 root 6244: 6245: (define_insn "" 6246: [(set (pc) 6247: (if_then_else (match_operator 0 "branch_comparison_operator" 6248: [(match_operand 1 6249: "cc_reg_operand" "x,?y") 6250: (const_int 0)]) 6251: (pc) 6252: (return)))] 6253: "direct_return ()" 1.1.1.2 root 6254: "{%C0bcr|%C0bclr} %T0,%j0" 6255: [(set_attr "length" "8")]) 1.1 root 6256: 6257: ;; Unconditional branch and return. 6258: 6259: (define_insn "jump" 6260: [(set (pc) 6261: (label_ref (match_operand 0 "" "")))] 6262: "" 6263: "b %l0") 6264: 6265: (define_insn "return" 6266: [(return)] 6267: "direct_return ()" 1.1.1.3 ! root 6268: "{br|blr}" ! 6269: [(set_attr "type" "jmpreg")]) 1.1 root 6270: 6271: (define_insn "indirect_jump" 6272: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] 6273: "" 6274: "@ 6275: bctr 1.1.1.3 ! root 6276: {br|blr}" ! 6277: [(set_attr "type" "jmpreg")]) 1.1 root 6278: 6279: ;; Table jump for switch statements: 6280: (define_expand "tablejump" 6281: [(set (match_dup 3) 6282: (plus:SI (match_operand:SI 0 "" "") 6283: (match_dup 2))) 6284: (parallel [(set (pc) (match_dup 3)) 6285: (use (label_ref (match_operand 1 "" "")))])] 6286: "" 6287: " 6288: { operands[0] = force_reg (SImode, operands[0]); 6289: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); 6290: operands[3] = gen_reg_rtx (SImode); 6291: }") 6292: 6293: (define_insn "" 6294: [(set (pc) 6295: (match_operand:SI 0 "register_operand" "c,l")) 6296: (use (label_ref (match_operand 1 "" "")))] 6297: "" 6298: "@ 6299: bctr 1.1.1.2 root 6300: {br|blr}") 1.1 root 6301: 6302: (define_insn "nop" 6303: [(const_int 0)] 6304: "" 1.1.1.2 root 6305: "{cror 0,0,0|nop}") 1.1 root 6306: 6307: ;; Define the subtract-one-and-jump insns, starting with the template 6308: ;; so loop.c knows what to generate. 6309: 6310: (define_expand "decrement_and_branchsi" 6311: [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c") 6312: (const_int 1)) 6313: (label_ref (match_operand 1 "" "")) 6314: (pc))) 6315: (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] 6316: "" 6317: "") 6318: 6319: ;; We need to be able to do this for any operand, including MEM, or we 6320: ;; will cause reload to blow up since we don't allow output reloads on 6321: ;; JUMP_INSNs. 6322: (define_insn "" 6323: [(set (pc) 6324: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r") 6325: (const_int 1)) 6326: (label_ref (match_operand 2 "" "")) 6327: (pc))) 6328: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") 6329: (plus:SI (match_dup 1) (const_int -1))) 6330: (clobber (match_scratch:CC 3 "=X,&x,&x")) 6331: (clobber (match_scratch:SI 4 "=X,X,r"))] 6332: "" 1.1.1.2 root 6333: "* 6334: { 6335: if (which_alternative != 0) 6336: return \"#\"; 6337: else if (get_attr_length (insn) == 8) 6338: return \"{bdn|bdnz} %l2\"; 6339: else 6340: return \"bdz $+8\;b %l2\"; 6341: }" 6342: [(set_attr "type" "branch") 6343: (set_attr "length" "*,12,16")]) 1.1 root 6344: 6345: ;; Similar, but we can use GE since we have a REG_NONNEG. 6346: (define_insn "" 6347: [(set (pc) 6348: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r") 6349: (const_int 0)) 6350: (label_ref (match_operand 2 "" "")) 6351: (pc))) 6352: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") 6353: (plus:SI (match_dup 1) (const_int -1))) 6354: (clobber (match_scratch:CC 3 "=X,&x,&X")) 6355: (clobber (match_scratch:SI 4 "=X,X,r"))] 6356: "find_reg_note (insn, REG_NONNEG, 0)" 1.1.1.2 root 6357: "* 6358: { 6359: if (which_alternative != 0) 6360: return \"#\"; 6361: else if (get_attr_length (insn) == 8) 6362: return \"{bdn|bdnz} %l2\"; 6363: else 6364: return \"bdz $+8\;b %l2\"; 6365: }" 6366: [(set_attr "type" "branch") 6367: (set_attr "length" "*,12,16")]) 1.1 root 6368: 6369: (define_insn "" 6370: [(set (pc) 6371: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r") 6372: (const_int 1)) 6373: (label_ref (match_operand 2 "" "")) 6374: (pc))) 6375: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") 6376: (plus:SI (match_dup 1) (const_int -1))) 6377: (clobber (match_scratch:CC 3 "=X,&x,&x")) 6378: (clobber (match_scratch:SI 4 "=X,X,r"))] 6379: "" 1.1.1.2 root 6380: "* 6381: { 6382: if (which_alternative != 0) 6383: return \"#\"; 6384: else if (get_attr_length (insn) == 8) 6385: return \"bdz %l2\"; 6386: else 6387: return \"{bdn|bdnz} $+8\;b %l2\"; 6388: }" 6389: [(set_attr "type" "branch") 6390: (set_attr "length" "*,12,16")]) 1.1 root 6391: 6392: (define_split 6393: [(set (pc) 6394: (if_then_else (match_operator 2 "comparison_operator" 6395: [(match_operand:SI 1 "gpc_reg_operand" "") 6396: (const_int 1)]) 6397: (match_operand 5 "" "") 6398: (match_operand 6 "" ""))) 6399: (set (match_operand:SI 0 "gpc_reg_operand" "") 6400: (plus:SI (match_dup 1) (const_int -1))) 6401: (clobber (match_scratch:CC 3 "")) 6402: (clobber (match_scratch:SI 4 ""))] 6403: "reload_completed" 6404: [(parallel [(set (match_dup 3) 6405: (compare:CC (plus:SI (match_dup 1) (const_int -1)) 6406: (const_int 0))) 6407: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) 6408: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] 6409: " 6410: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 6411: const0_rtx); }") 6412: 6413: (define_split 6414: [(set (pc) 6415: (if_then_else (match_operator 2 "comparison_operator" 6416: [(match_operand:SI 1 "gpc_reg_operand" "") 6417: (const_int 1)]) 6418: (match_operand 5 "" "") 6419: (match_operand 6 "" ""))) 6420: (set (match_operand:SI 0 "general_operand" "") 6421: (plus:SI (match_dup 1) (const_int -1))) 6422: (clobber (match_scratch:CC 3 "")) 6423: (clobber (match_scratch:SI 4 ""))] 6424: "reload_completed && ! gpc_reg_operand (operands[0], SImode)" 6425: [(parallel [(set (match_dup 3) 6426: (compare:CC (plus:SI (match_dup 1) (const_int -1)) 6427: (const_int 0))) 6428: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))]) 6429: (set (match_dup 0) (match_dup 4)) 6430: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] 6431: " 6432: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 6433: const0_rtx); }")
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