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1.1.1.3 root 1: ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 1.1.1.4 ! root 2: ;; Copyright (C) 1990, 91, 92, 93, 94, 1995 Free Software Foundation, Inc. 1.1.1.3 root 3: ;; Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 19: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 20: ;; Boston, MA 02111-1307, USA. 1.1 root 21: 22: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 23: 24: ;; Define an insn type attribute. This is used in function unit delay 25: ;; computations. 1.1.1.3 root 26: (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" 1.1 root 27: (const_string "integer")) 28: 1.1.1.2 root 29: ;; Length (in bytes). 30: (define_attr "length" "" 31: (if_then_else (eq_attr "type" "branch") 32: (if_then_else (and (ge (minus (pc) (match_dup 0)) 33: (const_int -32768)) 34: (lt (minus (pc) (match_dup 0)) 35: (const_int 32767))) 36: (const_int 8) 37: (const_int 12)) 38: (const_int 4))) 39: 40: ;; Processor type -- this attribute must exactly match the processor_type 41: ;; enumeration in rs6000.h. 42: 1.1.1.4 ! root 43: (define_attr "cpu" "rios1,rios2,ppc403,ppc601,ppc603,ppc604,ppc620" 1.1.1.2 root 44: (const (symbol_ref "rs6000_cpu_attr"))) 45: 46: ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY 47: ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) 48: 1.1.1.3 root 49: ; Load/Store Unit -- POWER/2 and pure PowerPC only 50: ; (POWER and 601 use Integer Unit) 1.1.1.2 root 51: (define_function_unit "lsu" 1 0 52: (and (eq_attr "type" "load") 53: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 54: 2 0) 55: 56: (define_function_unit "lsu" 1 0 57: (and (eq_attr "type" "fpload") 58: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 59: 2 0) 60: 61: (define_function_unit "iu" 1 0 62: (and (eq_attr "type" "load") 1.1.1.4 ! root 63: (eq_attr "cpu" "rios1,ppc403,ppc601")) 1.1.1.2 root 64: 2 0) 65: 66: (define_function_unit "iu" 1 0 67: (and (eq_attr "type" "fpload") 68: (eq_attr "cpu" "rios1,ppc601")) 69: 3 0) 70: 1.1.1.3 root 71: ; Integer Unit (RIOS1, PPC601, PPC603) 72: ; Trivial operations take one cycle which need not be listed here. 1.1.1.2 root 73: (define_function_unit "iu" 1 0 74: (and (eq_attr "type" "imul") 75: (eq_attr "cpu" "rios1")) 1.1.1.3 root 76: 3 3) 1.1.1.2 root 77: 78: (define_function_unit "iu" 1 0 79: (and (eq_attr "type" "imul") 1.1.1.4 ! root 80: (eq_attr "cpu" "ppc403")) ! 81: 4 4) ! 82: ! 83: (define_function_unit "iu" 1 0 ! 84: (and (eq_attr "type" "imul") 1.1.1.3 root 85: (eq_attr "cpu" "ppc601,ppc603")) 86: 5 5) 1.1.1.2 root 87: 88: (define_function_unit "iu" 1 0 89: (and (eq_attr "type" "idiv") 90: (eq_attr "cpu" "rios1")) 1.1.1.3 root 91: 19 19) 1.1.1.2 root 92: 93: (define_function_unit "iu" 1 0 94: (and (eq_attr "type" "idiv") 1.1.1.4 ! root 95: (eq_attr "cpu" "ppc403")) ! 96: 33 33) ! 97: ! 98: (define_function_unit "iu" 1 0 ! 99: (and (eq_attr "type" "idiv") 1.1.1.3 root 100: (eq_attr "cpu" "ppc601")) 101: 36 36) 102: 103: (define_function_unit "iu" 1 0 104: (and (eq_attr "type" "idiv") 105: (eq_attr "cpu" "ppc603")) 106: 37 36) 107: 108: ; RIOS2 has two integer units: a primary one which can perform all 109: ; operations and a secondary one which is fed in lock step with the first 110: ; and can perform "simple" integer operations. 111: (define_function_unit "iu2" 2 0 112: (and (eq_attr "type" "integer") 113: (eq_attr "cpu" "rios2")) 114: 1 0 115: [(eq_attr "type" "imul,idiv")]) 116: 117: (define_function_unit "imuldiv" 1 0 118: (and (eq_attr "type" "imul") 119: (eq_attr "cpu" "rios2")) 120: 2 2 121: [(eq_attr "type" "integer")]) 122: 123: (define_function_unit "imuldiv" 1 0 124: (and (eq_attr "type" "idiv") 125: (eq_attr "cpu" "rios2")) 126: 13 13 127: [(eq_attr "type" "integer")]) 128: 129: ; PPC604 has three integer units: one primary and two secondary. 130: (define_function_unit "iu3" 3 0 131: (and (eq_attr "type" "integer") 132: (eq_attr "cpu" "ppc604,ppc620")) 133: 1 0 134: [(eq_attr "type" "imul,idiv")]) 135: 136: (define_function_unit "imuldiv" 1 0 137: (and (eq_attr "type" "imul") 138: (eq_attr "cpu" "ppc604,ppc620")) 139: 4 2 140: [(eq_attr "type" "integer")]) 141: 142: (define_function_unit "imuldiv" 1 0 143: (and (eq_attr "type" "idiv") 144: (eq_attr "cpu" "ppc604,ppc620")) 145: 20 19 146: [(eq_attr "type" "integer")]) 1.1.1.2 root 147: 1.1.1.3 root 148: ; Branch Processing Unit 1.1.1.2 root 149: (define_function_unit "bpu" 1 0 150: (eq_attr "type" "compare") 151: 4 0) 152: 153: (define_function_unit "bpu" 1 0 154: (eq_attr "type" "delayed_compare") 155: 5 0) 156: 157: (define_function_unit "bpu" 1 0 158: (and (eq_attr "type" "fpcompare") 159: (eq_attr "cpu" "rios1,rios2")) 160: 8 0) 161: 162: (define_function_unit "bpu" 1 0 163: (and (eq_attr "type" "fpcompare") 164: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) 165: 4 0) 166: 167: (define_function_unit "bpu" 1 0 1.1.1.3 root 168: (and (eq_attr "type" "mtjmpr") 1.1.1.2 root 169: (eq_attr "cpu" "rios1,rios2")) 170: 5 0) 171: 172: (define_function_unit "bpu" 1 0 1.1.1.3 root 173: (and (eq_attr "type" "mtjmpr") 1.1.1.4 ! root 174: (eq_attr "cpu" "ppc403,ppc601,ppc603,ppc604,ppc620")) 1.1.1.2 root 175: 4 0) 176: 1.1.1.3 root 177: ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604). 1.1.1.2 root 178: (define_function_unit "fpu" 1 0 1.1.1.3 root 179: (and (eq_attr "type" "fp,dmul") 1.1.1.2 root 180: (eq_attr "cpu" "rios1")) 181: 2 0) 182: 183: (define_function_unit "fpu" 1 0 184: (and (eq_attr "type" "fp") 1.1.1.3 root 185: (eq_attr "cpu" "ppc601")) 1.1.1.2 root 186: 4 0) 187: 188: (define_function_unit "fpu" 1 0 1.1.1.3 root 189: (and (eq_attr "type" "fp") 190: (eq_attr "cpu" "ppc603,ppc604,ppc620")) 191: 3 0) 192: 193: (define_function_unit "fpu" 1 0 1.1.1.2 root 194: (and (eq_attr "type" "dmul") 1.1.1.3 root 195: (eq_attr "cpu" "ppc601")) 196: 5 5) 1.1.1.2 root 197: 198: (define_function_unit "fpu" 1 0 199: (and (eq_attr "type" "dmul") 1.1.1.3 root 200: (eq_attr "cpu" "ppc603")) 201: 4 2) 1.1.1.2 root 202: 203: (define_function_unit "fpu" 1 0 1.1.1.3 root 204: (and (eq_attr "type" "dmul") 205: (eq_attr "cpu" "ppc604,ppc620")) 206: 3 0) 207: 208: (define_function_unit "fpu" 1 0 209: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 210: (eq_attr "cpu" "rios1")) 1.1.1.3 root 211: 19 19) 1.1.1.2 root 212: 213: (define_function_unit "fpu" 1 0 214: (and (eq_attr "type" "sdiv") 1.1.1.3 root 215: (eq_attr "cpu" "ppc601")) 216: 17 17) 217: 218: (define_function_unit "fpu" 1 0 219: (and (eq_attr "type" "sdiv") 220: (eq_attr "cpu" "ppc603,ppc604,ppc620")) 221: 18 18) 1.1.1.2 root 222: 223: (define_function_unit "fpu" 1 0 224: (and (eq_attr "type" "ddiv") 1.1.1.3 root 225: (eq_attr "cpu" "ppc601,ppc604,ppc620")) 226: 31 31) 1.1.1.2 root 227: 228: (define_function_unit "fpu" 1 0 229: (and (eq_attr "type" "ddiv") 1.1.1.3 root 230: (eq_attr "cpu" "ppc603")) 231: 33 33) 1.1.1.2 root 232: 233: (define_function_unit "fpu" 1 0 234: (and (eq_attr "type" "ssqrt") 1.1.1.3 root 235: (eq_attr "cpu" "ppc620")) 236: 31 31) 1.1.1.2 root 237: 238: (define_function_unit "fpu" 1 0 239: (and (eq_attr "type" "dsqrt") 1.1.1.3 root 240: (eq_attr "cpu" "ppc620")) 241: 31 31) 1.1.1.2 root 242: 1.1.1.3 root 243: ; RIOS2 has two symmetric FPUs. 1.1.1.2 root 244: (define_function_unit "fpu2" 2 0 245: (and (eq_attr "type" "fp") 246: (eq_attr "cpu" "rios2")) 247: 2 0) 248: 249: (define_function_unit "fpu2" 2 0 250: (and (eq_attr "type" "dmul") 251: (eq_attr "cpu" "rios2")) 252: 2 0) 253: 254: (define_function_unit "fpu2" 2 0 1.1.1.3 root 255: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 256: (eq_attr "cpu" "rios2")) 1.1.1.3 root 257: 17 17) 1.1.1.2 root 258: 259: (define_function_unit "fpu2" 2 0 1.1.1.3 root 260: (and (eq_attr "type" "ssqrt,dsqrt") 1.1.1.2 root 261: (eq_attr "cpu" "rios2")) 1.1.1.3 root 262: 26 26) 1.1 root 263: 264: ;; Start with fixed-point load and store insns. Here we put only the more 265: ;; complex forms. Basic data transfer is done later. 266: 1.1.1.3 root 267: (define_expand "zero_extendqidi2" 268: [(set (match_operand:DI 0 "gpc_reg_operand" "") 269: (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] 270: "TARGET_POWERPC64" 271: "") 272: 273: (define_insn "" 274: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 275: (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 276: "TARGET_POWERPC64" 277: "@ 278: lbz%U1%X1 %0,%1 279: rldicl %0,%1,0,56" 280: [(set_attr "type" "load,*")]) 281: 282: (define_insn "" 283: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 284: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 285: (const_int 0))) 286: (clobber (match_scratch:DI 2 "=r"))] 287: "TARGET_POWERPC64" 288: "rldicl. %2,%1,0,56" 289: [(set_attr "type" "compare")]) 290: 291: (define_insn "" 292: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 293: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 294: (const_int 0))) 295: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 296: (zero_extend:DI (match_dup 1)))] 297: "TARGET_POWERPC64" 298: "rldicl. %0,%1,0,56" 299: [(set_attr "type" "compare")]) 300: 301: (define_insn "extendqidi2" 302: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 303: (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 304: "TARGET_POWERPC64" 305: "extsb %0,%1") 306: 307: (define_insn "" 308: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 309: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 310: (const_int 0))) 311: (clobber (match_scratch:DI 2 "=r"))] 312: "TARGET_POWERPC64" 313: "extsb. %2,%1" 314: [(set_attr "type" "compare")]) 315: 316: (define_insn "" 317: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 318: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 319: (const_int 0))) 320: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 321: (sign_extend:DI (match_dup 1)))] 322: "TARGET_POWERPC64" 323: "extsb. %0,%1" 324: [(set_attr "type" "compare")]) 325: 326: (define_expand "zero_extendhidi2" 327: [(set (match_operand:DI 0 "gpc_reg_operand" "") 328: (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 329: "TARGET_POWERPC64" 330: "") 331: 332: (define_insn "" 333: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 334: (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 335: "TARGET_POWERPC64" 336: "@ 337: lhz%U1%X1 %0,%1 338: rldicl %0,%1,0,48" 339: [(set_attr "type" "load,*")]) 340: 341: (define_insn "" 342: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 343: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 344: (const_int 0))) 345: (clobber (match_scratch:DI 2 "=r"))] 346: "TARGET_POWERPC64" 347: "rldicl. %2,%1,0,48" 348: [(set_attr "type" "compare")]) 349: 350: (define_insn "" 351: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 352: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 353: (const_int 0))) 354: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 355: (zero_extend:DI (match_dup 1)))] 356: "TARGET_POWERPC64" 357: "rldicl. %0,%1,0,48" 358: [(set_attr "type" "compare")]) 359: 360: (define_expand "extendhidi2" 361: [(set (match_operand:DI 0 "gpc_reg_operand" "") 362: (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 363: "TARGET_POWERPC64" 364: "") 365: 366: (define_insn "" 367: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 368: (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 369: "TARGET_POWERPC64" 370: "@ 371: lha%U1%X1 %0,%1 372: extsh %0,%1" 373: [(set_attr "type" "load,*")]) 374: 375: (define_insn "" 376: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 377: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 378: (const_int 0))) 379: (clobber (match_scratch:DI 2 "=r"))] 380: "TARGET_POWERPC64" 381: "extsh. %2,%1" 382: [(set_attr "type" "compare")]) 383: 384: (define_insn "" 385: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 386: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 387: (const_int 0))) 388: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 389: (sign_extend:DI (match_dup 1)))] 390: "TARGET_POWERPC64" 391: "extsh. %0,%1" 392: [(set_attr "type" "compare")]) 393: 394: (define_expand "zero_extendsidi2" 395: [(set (match_operand:DI 0 "gpc_reg_operand" "") 396: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 397: "TARGET_POWERPC64" 398: "") 399: 400: (define_insn "" 401: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 402: (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] 403: "TARGET_POWERPC64" 404: "@ 405: lwz%U1%X1 %0,%1 406: rldicl %0,%1,0,32" 407: [(set_attr "type" "load,*")]) 408: 409: (define_insn "" 410: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 411: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 412: (const_int 0))) 413: (clobber (match_scratch:DI 2 "=r"))] 414: "TARGET_POWERPC64" 415: "rldicl. %2,%1,0,32" 416: [(set_attr "type" "compare")]) 417: 418: (define_insn "" 419: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 420: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 421: (const_int 0))) 422: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 423: (zero_extend:DI (match_dup 1)))] 424: "TARGET_POWERPC64" 425: "rldicl. %0,%1,0,32" 426: [(set_attr "type" "compare")]) 427: 428: (define_expand "extendsidi2" 429: [(set (match_operand:DI 0 "gpc_reg_operand" "") 430: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 431: "TARGET_POWERPC64" 432: "") 433: 434: (define_insn "" 435: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1.1.1.4 ! root 436: (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] 1.1.1.3 root 437: "TARGET_POWERPC64" 438: "@ 439: lwa%U1%X1 %0,%1 440: extsw %0,%1" 441: [(set_attr "type" "load,*")]) 442: 443: (define_insn "" 444: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 445: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 446: (const_int 0))) 447: (clobber (match_scratch:DI 2 "=r"))] 448: "TARGET_POWERPC64" 449: "extsw. %2,%1" 450: [(set_attr "type" "compare")]) 451: 452: (define_insn "" 453: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 454: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 455: (const_int 0))) 456: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 457: (sign_extend:DI (match_dup 1)))] 458: "TARGET_POWERPC64" 459: "extsw. %0,%1" 460: [(set_attr "type" "compare")]) 461: 1.1 root 462: (define_expand "zero_extendqisi2" 463: [(set (match_operand:SI 0 "gpc_reg_operand" "") 464: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 465: "" 466: "") 467: 468: (define_insn "" 469: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 470: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 471: "" 472: "@ 473: lbz%U1%X1 %0,%1 1.1.1.2 root 474: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 475: [(set_attr "type" "load,*")]) 476: 477: (define_insn "" 478: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 479: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 480: (const_int 0))) 481: (clobber (match_scratch:SI 2 "=r"))] 482: "" 1.1.1.2 root 483: "{andil.|andi.} %2,%1,0xff" 1.1 root 484: [(set_attr "type" "compare")]) 485: 486: (define_insn "" 487: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 488: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 489: (const_int 0))) 490: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 491: (zero_extend:SI (match_dup 1)))] 492: "" 1.1.1.2 root 493: "{andil.|andi.} %0,%1,0xff" 1.1 root 494: [(set_attr "type" "compare")]) 495: 1.1.1.3 root 496: (define_expand "extendqisi2" 497: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 498: (use (match_operand:QI 1 "gpc_reg_operand" ""))] 499: "" 500: " 501: { 502: if (TARGET_POWERPC) 503: emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); 504: else if (TARGET_POWER) 505: emit_insn (gen_extendqisi2_power (operands[0], operands[1])); 506: else 507: emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); 508: DONE; 509: }") 510: 511: (define_insn "extendqisi2_ppc" 512: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 513: (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 514: "TARGET_POWERPC" 515: "extsb %0,%1") 516: 517: (define_insn "" 518: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 519: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 520: (const_int 0))) 521: (clobber (match_scratch:SI 2 "=r"))] 522: "TARGET_POWERPC" 523: "extsb. %2,%1" 524: [(set_attr "type" "compare")]) 525: 526: (define_insn "" 527: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 528: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 529: (const_int 0))) 530: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 531: (sign_extend:SI (match_dup 1)))] 532: "TARGET_POWERPC" 533: "extsb. %0,%1" 534: [(set_attr "type" "compare")]) 535: 536: (define_expand "extendqisi2_power" 537: [(parallel [(set (match_dup 2) 538: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 539: (const_int 24))) 540: (clobber (scratch:SI))]) 541: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 542: (ashiftrt:SI (match_dup 2) 543: (const_int 24))) 544: (clobber (scratch:SI))])] 545: "TARGET_POWER" 546: " 547: { operands[1] = gen_lowpart (SImode, operands[1]); 548: operands[2] = gen_reg_rtx (SImode); }") 549: 550: (define_expand "extendqisi2_no_power" 551: [(set (match_dup 2) 552: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 553: (const_int 24))) 554: (set (match_operand:SI 0 "gpc_reg_operand" "") 555: (ashiftrt:SI (match_dup 2) 556: (const_int 24)))] 557: "! TARGET_POWER && ! TARGET_POWERPC" 558: " 559: { operands[1] = gen_lowpart (SImode, operands[1]); 560: operands[2] = gen_reg_rtx (SImode); }") 561: 1.1 root 562: (define_expand "zero_extendqihi2" 563: [(set (match_operand:HI 0 "gpc_reg_operand" "") 564: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 565: "" 566: "") 567: 568: (define_insn "" 569: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 570: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 571: "" 572: "@ 573: lbz%U1%X1 %0,%1 1.1.1.2 root 574: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 575: [(set_attr "type" "load,*")]) 576: 1.1.1.3 root 577: (define_insn "" 578: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 579: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 580: (const_int 0))) 581: (clobber (match_scratch:HI 2 "=r"))] 582: "" 583: "{andil.|andi.} %2,%1,0xff" 584: [(set_attr "type" "compare")]) 585: 586: (define_insn "" 587: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 588: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 589: (const_int 0))) 590: (set (match_operand:HI 0 "gpc_reg_operand" "=r") 591: (zero_extend:HI (match_dup 1)))] 592: "" 593: "{andil.|andi.} %0,%1,0xff" 594: [(set_attr "type" "compare")]) 595: 596: (define_expand "extendqihi2" 597: [(use (match_operand:HI 0 "gpc_reg_operand" "")) 598: (use (match_operand:QI 1 "gpc_reg_operand" ""))] 599: "" 600: " 601: { 602: if (TARGET_POWERPC) 603: emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); 604: else if (TARGET_POWER) 605: emit_insn (gen_extendqihi2_power (operands[0], operands[1])); 606: else 607: emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); 608: DONE; 609: }") 610: 611: (define_insn "extendqihi2_ppc" 612: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 613: (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 614: "TARGET_POWERPC" 615: "extsb %0,%1") 616: 617: (define_insn "" 618: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 619: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 620: (const_int 0))) 621: (clobber (match_scratch:HI 2 "=r"))] 622: "TARGET_POWERPC" 623: "extsb. %2,%1" 624: [(set_attr "type" "compare")]) 625: 626: (define_insn "" 627: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 628: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 629: (const_int 0))) 630: (set (match_operand:HI 0 "gpc_reg_operand" "=r") 631: (sign_extend:HI (match_dup 1)))] 632: "TARGET_POWERPC" 633: "extsb. %0,%1" 634: [(set_attr "type" "compare")]) 635: 636: (define_expand "extendqihi2_power" 637: [(parallel [(set (match_dup 2) 638: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 639: (const_int 24))) 640: (clobber (scratch:SI))]) 641: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") 642: (ashiftrt:SI (match_dup 2) 643: (const_int 24))) 644: (clobber (scratch:SI))])] 645: "TARGET_POWER" 646: " 647: { operands[0] = gen_lowpart (SImode, operands[0]); 648: operands[1] = gen_lowpart (SImode, operands[1]); 649: operands[2] = gen_reg_rtx (SImode); }") 650: 651: (define_expand "extendqihi2_no_power" 652: [(set (match_dup 2) 653: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 654: (const_int 24))) 655: (set (match_operand:HI 0 "gpc_reg_operand" "") 656: (ashiftrt:SI (match_dup 2) 657: (const_int 24)))] 658: "! TARGET_POWER && ! TARGET_POWERPC" 659: " 660: { operands[0] = gen_lowpart (SImode, operands[0]); 661: operands[1] = gen_lowpart (SImode, operands[1]); 662: operands[2] = gen_reg_rtx (SImode); }") 663: 1.1 root 664: (define_expand "zero_extendhisi2" 665: [(set (match_operand:SI 0 "gpc_reg_operand" "") 666: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 667: "" 668: "") 669: 670: (define_insn "" 671: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 672: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 673: "" 674: "@ 675: lhz%U1%X1 %0,%1 1.1.1.2 root 676: {rlinm|rlwinm} %0,%1,0,0xffff" 1.1 root 677: [(set_attr "type" "load,*")]) 678: 679: (define_insn "" 680: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 681: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 682: (const_int 0))) 683: (clobber (match_scratch:SI 2 "=r"))] 684: "" 1.1.1.2 root 685: "{andil.|andi.} %2,%1,0xffff" 1.1 root 686: [(set_attr "type" "compare")]) 687: 688: (define_insn "" 689: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 690: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 691: (const_int 0))) 692: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 693: (zero_extend:SI (match_dup 1)))] 694: "" 1.1.1.2 root 695: "{andil.|andi.} %0,%1,0xffff" 1.1 root 696: [(set_attr "type" "compare")]) 697: 698: (define_expand "extendhisi2" 699: [(set (match_operand:SI 0 "gpc_reg_operand" "") 700: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 701: "" 702: "") 703: 704: (define_insn "" 705: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 706: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 707: "" 708: "@ 709: lha%U1%X1 %0,%1 1.1.1.2 root 710: {exts|extsh} %0,%1" 1.1 root 711: [(set_attr "type" "load,*")]) 712: 713: (define_insn "" 714: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 715: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 716: (const_int 0))) 717: (clobber (match_scratch:SI 2 "=r"))] 718: "" 1.1.1.2 root 719: "{exts.|extsh.} %2,%1" 1.1 root 720: [(set_attr "type" "compare")]) 721: 722: (define_insn "" 723: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 724: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 725: (const_int 0))) 726: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 727: (sign_extend:SI (match_dup 1)))] 728: "" 1.1.1.2 root 729: "{exts.|extsh.} %0,%1" 1.1 root 730: [(set_attr "type" "compare")]) 731: 732: ;; Fixed-point arithmetic insns. 1.1.1.3 root 733: 734: ;; Discourage ai/addic because of carry but provide it in an alternative 735: ;; allowing register zero as source. 1.1 root 736: (define_insn "addsi3" 1.1.1.3 root 737: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") 738: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") 739: (match_operand:SI 2 "add_operand" "r,I,I,J")))] 1.1 root 740: "" 741: "@ 1.1.1.3 root 742: {cax|add} %0,%1,%2 743: {cal %0,%2(%1)|addi %0,%1,%2} 744: {ai|addic} %0,%1,%2 1.1.1.2 root 745: {cau|addis} %0,%1,%u2") 1.1 root 746: 747: (define_insn "" 1.1.1.3 root 748: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 749: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 750: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 751: (const_int 0))) 1.1.1.3 root 752: (clobber (match_scratch:SI 3 "=r,r"))] 1.1 root 753: "" 1.1.1.3 root 754: "@ 755: {cax.|add.} %3,%1,%2 756: {ai.|addic.} %3,%1,%2" 1.1 root 757: [(set_attr "type" "compare")]) 1.1.1.4 ! root 758: 1.1 root 759: (define_insn "" 1.1.1.3 root 760: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 761: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 762: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 763: (const_int 0))) 1.1.1.3 root 764: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 765: (plus:SI (match_dup 1) (match_dup 2)))] 766: "" 1.1.1.3 root 767: "@ 768: {cax.|add.} %0,%1,%2 769: {ai.|addic.} %0,%1,%2" 1.1 root 770: [(set_attr "type" "compare")]) 1.1.1.4 ! root 771: 1.1 root 772: ;; Split an add that we can't do in one insn into two insns, each of which 773: ;; does one 16-bit part. This is used by combine. Note that the low-order 774: ;; add should be last in case the result gets used in an address. 775: 776: (define_split 777: [(set (match_operand:SI 0 "gpc_reg_operand" "") 778: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 779: (match_operand:SI 2 "non_add_cint_operand" "")))] 780: "" 781: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 782: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 783: " 784: { 785: int low = INTVAL (operands[2]) & 0xffff; 786: int high = (unsigned) INTVAL (operands[2]) >> 16; 787: 788: if (low & 0x8000) 789: high++, low |= 0xffff0000; 790: 791: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); 792: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); 793: }") 794: 1.1.1.3 root 795: (define_insn "one_cmplsi2" 1.1 root 796: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 797: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 798: "" 1.1.1.2 root 799: "nor %0,%1,%1") 800: 801: (define_insn "" 802: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 803: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 804: (const_int 0))) 805: (clobber (match_scratch:SI 2 "=r"))] 1.1 root 806: "" 1.1.1.2 root 807: "nor. %2,%1,%1" 808: [(set_attr "type" "compare")]) 809: 810: (define_insn "" 1.1.1.3 root 811: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1.1.1.2 root 812: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 813: (const_int 0))) 814: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 815: (not:SI (match_dup 1)))] 816: "" 817: "nor. %0,%2,%1" 818: [(set_attr "type" "compare")]) 819: 820: (define_insn "" 821: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 822: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 823: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1.1.1.3 root 824: "! TARGET_POWERPC" 1.1.1.2 root 825: "{sf%I1|subf%I1c} %0,%2,%1") 1.1 root 826: 827: (define_insn "" 1.1.1.3 root 828: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 829: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") 830: (match_operand:SI 2 "gpc_reg_operand" "r,r")))] 831: "TARGET_POWERPC" 832: "@ 833: subf %0,%2,%1 834: subfic %0,%2,%1") 835: 836: (define_insn "" 1.1 root 837: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 838: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 839: (match_operand:SI 2 "gpc_reg_operand" "r")) 840: (const_int 0))) 841: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 root 842: "! TARGET_POWERPC" 1.1.1.2 root 843: "{sf.|subfc.} %3,%2,%1" 1.1 root 844: [(set_attr "type" "compare")]) 845: 846: (define_insn "" 1.1.1.3 root 847: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 848: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 849: (match_operand:SI 2 "gpc_reg_operand" "r")) 850: (const_int 0))) 851: (clobber (match_scratch:SI 3 "=r"))] 852: "TARGET_POWERPC" 853: "subf. %3,%2,%1" 854: [(set_attr "type" "compare")]) 855: 856: (define_insn "" 1.1 root 857: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 858: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 859: (match_operand:SI 2 "gpc_reg_operand" "r")) 860: (const_int 0))) 861: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 862: (minus:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 863: "! TARGET_POWERPC" 1.1.1.2 root 864: "{sf.|subfc.} %0,%2,%1" 1.1 root 865: [(set_attr "type" "compare")]) 866: 1.1.1.3 root 867: (define_insn "" 868: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 869: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 870: (match_operand:SI 2 "gpc_reg_operand" "r")) 871: (const_int 0))) 872: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 873: (minus:SI (match_dup 1) (match_dup 2)))] 874: "TARGET_POWERPC" 875: "subf. %0,%2,%1" 876: [(set_attr "type" "compare")]) 877: 1.1 root 878: (define_expand "subsi3" 879: [(set (match_operand:SI 0 "gpc_reg_operand" "") 880: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") 881: (match_operand:SI 2 "reg_or_cint_operand" "")))] 882: "" 883: " 884: { 885: if (GET_CODE (operands[2]) == CONST_INT) 886: { 887: emit_insn (gen_addsi3 (operands[0], operands[1], 888: negate_rtx (SImode, operands[2]))); 889: DONE; 890: } 891: }") 892: 893: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 894: ;; instruction and some auxiliary computations. Then we just have a single 895: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 896: ;; combine. 897: 898: (define_expand "sminsi3" 899: [(set (match_dup 3) 900: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 901: (match_operand:SI 2 "reg_or_short_operand" "")) 902: (const_int 0) 903: (minus:SI (match_dup 2) (match_dup 1)))) 904: (set (match_operand:SI 0 "gpc_reg_operand" "") 905: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 906: "TARGET_POWER" 1.1 root 907: " 908: { operands[3] = gen_reg_rtx (SImode); }") 909: 910: (define_split 911: [(set (match_operand:SI 0 "gpc_reg_operand" "") 912: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 913: (match_operand:SI 2 "reg_or_short_operand" ""))) 914: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 915: "TARGET_POWER" 1.1 root 916: [(set (match_dup 3) 917: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 918: (const_int 0) 919: (minus:SI (match_dup 2) (match_dup 1)))) 920: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 921: "") 922: 923: (define_expand "smaxsi3" 924: [(set (match_dup 3) 925: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 926: (match_operand:SI 2 "reg_or_short_operand" "")) 927: (const_int 0) 928: (minus:SI (match_dup 2) (match_dup 1)))) 929: (set (match_operand:SI 0 "gpc_reg_operand" "") 930: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 931: "TARGET_POWER" 1.1 root 932: " 933: { operands[3] = gen_reg_rtx (SImode); }") 934: 935: (define_split 936: [(set (match_operand:SI 0 "gpc_reg_operand" "") 937: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 938: (match_operand:SI 2 "reg_or_short_operand" ""))) 939: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 940: "TARGET_POWER" 1.1 root 941: [(set (match_dup 3) 942: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 943: (const_int 0) 944: (minus:SI (match_dup 2) (match_dup 1)))) 945: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 946: "") 947: 948: (define_expand "uminsi3" 949: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1.1.4 ! root 950: (match_dup 5))) 1.1 root 951: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.4 ! root 952: (match_dup 5))) 1.1 root 953: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 954: (const_int 0) 955: (minus:SI (match_dup 4) (match_dup 3)))) 956: (set (match_operand:SI 0 "gpc_reg_operand" "") 957: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 958: "TARGET_POWER" 1.1 root 959: " 1.1.1.4 ! root 960: { ! 961: operands[3] = gen_reg_rtx (SImode); ! 962: operands[4] = gen_reg_rtx (SImode); ! 963: operands[5] = GEN_INT (-2147483647 - 1); ! 964: }") 1.1 root 965: 966: (define_expand "umaxsi3" 967: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1.1.4 ! root 968: (match_dup 5))) 1.1 root 969: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.4 ! root 970: (match_dup 5))) 1.1 root 971: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 972: (const_int 0) 973: (minus:SI (match_dup 4) (match_dup 3)))) 974: (set (match_operand:SI 0 "gpc_reg_operand" "") 975: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 976: "TARGET_POWER" 1.1 root 977: " 1.1.1.4 ! root 978: { ! 979: operands[3] = gen_reg_rtx (SImode); ! 980: operands[4] = gen_reg_rtx (SImode); ! 981: operands[5] = GEN_INT (-2147483647 - 1); ! 982: }") 1.1 root 983: 984: (define_insn "" 985: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 986: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 987: (match_operand:SI 2 "reg_or_short_operand" "rI")) 988: (const_int 0) 989: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 990: "TARGET_POWER" 1.1 root 991: "doz%I2 %0,%1,%2") 992: 993: (define_insn "" 994: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 995: (compare:CC 996: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 997: (match_operand:SI 2 "reg_or_short_operand" "rI")) 998: (const_int 0) 999: (minus:SI (match_dup 2) (match_dup 1))) 1000: (const_int 0))) 1001: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 1002: "TARGET_POWER" 1.1 root 1003: "doz%I2. %3,%1,%2" 1004: [(set_attr "type" "delayed_compare")]) 1005: 1006: (define_insn "" 1007: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1008: (compare:CC 1009: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 1010: (match_operand:SI 2 "reg_or_short_operand" "rI")) 1011: (const_int 0) 1012: (minus:SI (match_dup 2) (match_dup 1))) 1013: (const_int 0))) 1014: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1015: (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1016: (const_int 0) 1017: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 1018: "TARGET_POWER" 1.1 root 1019: "doz%I2. %0,%1,%2" 1020: [(set_attr "type" "delayed_compare")]) 1021: 1022: ;; We don't need abs with condition code because such comparisons should 1023: ;; never be done. 1.1.1.4 ! root 1024: (define_expand "abssi2" ! 1025: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1026: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] ! 1027: "" ! 1028: " ! 1029: { ! 1030: if (!TARGET_POWER) ! 1031: { ! 1032: emit_insn (gen_abssi2_nopower (operands[0], operands[1])); ! 1033: DONE; ! 1034: } ! 1035: }") ! 1036: ! 1037: (define_insn "abssi2_power" 1.1 root 1038: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1039: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.2 root 1040: "TARGET_POWER" 1.1 root 1041: "abs %0,%1") 1042: 1.1.1.4 ! root 1043: (define_insn "abssi2_nopower" ! 1044: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") ! 1045: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) ! 1046: (clobber (match_scratch:SI 2 "=&r,&r"))] ! 1047: "!TARGET_POWER" ! 1048: "* ! 1049: { ! 1050: return (TARGET_POWERPC) ! 1051: ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" ! 1052: : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; ! 1053: }" ! 1054: [(set_attr "length" "12")]) ! 1055: ! 1056: (define_split ! 1057: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") ! 1058: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) ! 1059: (clobber (match_scratch:SI 2 "=&r,&r"))] ! 1060: "!TARGET_POWER && reload_completed" ! 1061: [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) ! 1062: (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) ! 1063: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] ! 1064: "") ! 1065: 1.1 root 1066: (define_insn "" 1067: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1068: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1069: "TARGET_POWER" 1.1 root 1070: "nabs %0,%1") 1071: 1.1.1.4 ! root 1072: (define_insn "" ! 1073: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") ! 1074: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) ! 1075: (clobber (match_scratch:SI 2 "=&r,&r"))] ! 1076: "!TARGET_POWER" ! 1077: "* ! 1078: { ! 1079: return (TARGET_POWERPC) ! 1080: ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" ! 1081: : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; ! 1082: }" ! 1083: [(set_attr "length" "12")]) ! 1084: ! 1085: (define_split ! 1086: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") ! 1087: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) ! 1088: (clobber (match_scratch:SI 2 "=&r,&r"))] ! 1089: "!TARGET_POWER && reload_completed" ! 1090: [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) ! 1091: (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) ! 1092: (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] ! 1093: "") ! 1094: 1.1 root 1095: (define_insn "negsi2" 1096: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1097: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1098: "" 1099: "neg %0,%1") 1100: 1101: (define_insn "" 1102: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1103: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1104: (const_int 0))) 1105: (clobber (match_scratch:SI 2 "=r"))] 1106: "" 1107: "neg. %2,%1" 1108: [(set_attr "type" "compare")]) 1109: 1110: (define_insn "" 1111: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1112: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1113: (const_int 0))) 1114: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1115: (neg:SI (match_dup 1)))] 1116: "" 1117: "neg. %0,%1" 1118: [(set_attr "type" "compare")]) 1119: 1120: (define_insn "ffssi2" 1.1.1.4 ! root 1121: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") ! 1122: (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 1123: "" 1.1.1.2 root 1124: "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" 1125: [(set_attr "length" "16")]) 1126: 1127: (define_expand "mulsi3" 1128: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1129: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1130: (use (match_operand:SI 2 "reg_or_short_operand" ""))] 1131: "" 1132: " 1133: { 1134: if (TARGET_POWER) 1135: emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 1136: else 1137: emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 1138: DONE; 1139: }") 1.1 root 1140: 1.1.1.2 root 1141: (define_insn "mulsi3_mq" 1.1 root 1142: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1143: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1144: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 1145: (clobber (match_scratch:SI 3 "=q,q"))] 1.1.1.2 root 1146: "TARGET_POWER" 1.1 root 1147: "@ 1.1.1.2 root 1148: {muls|mullw} %0,%1,%2 1149: {muli|mulli} %0,%1,%2" 1150: [(set_attr "type" "imul")]) 1151: 1152: (define_insn "mulsi3_no_mq" 1153: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1154: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1155: (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 1156: "! TARGET_POWER" 1157: "@ 1.1.1.4 ! root 1158: {muls|mullw} %0,%1,%2 ! 1159: {muli|mulli} %0,%1,%2" 1.1.1.2 root 1160: [(set_attr "type" "imul")]) 1.1 root 1161: 1162: (define_insn "" 1163: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1164: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1165: (match_operand:SI 2 "gpc_reg_operand" "r")) 1166: (const_int 0))) 1167: (clobber (match_scratch:SI 3 "=r")) 1168: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1169: "TARGET_POWER" 1170: "{muls.|mullw.} %3,%1,%2" 1171: [(set_attr "type" "delayed_compare")]) 1172: 1173: (define_insn "" 1174: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1175: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1176: (match_operand:SI 2 "gpc_reg_operand" "r")) 1177: (const_int 0))) 1178: (clobber (match_scratch:SI 3 "=r"))] 1179: "! TARGET_POWER" 1.1.1.4 ! root 1180: "{muls.|mullw.} %3,%1,%2" 1.1 root 1181: [(set_attr "type" "delayed_compare")]) 1182: 1183: (define_insn "" 1184: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1185: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1186: (match_operand:SI 2 "gpc_reg_operand" "r")) 1187: (const_int 0))) 1188: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1189: (mult:SI (match_dup 1) (match_dup 2))) 1190: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1191: "TARGET_POWER" 1192: "{muls.|mullw.} %0,%1,%2" 1193: [(set_attr "type" "delayed_compare")]) 1194: 1195: (define_insn "" 1196: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1197: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1198: (match_operand:SI 2 "gpc_reg_operand" "r")) 1199: (const_int 0))) 1200: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1201: (mult:SI (match_dup 1) (match_dup 2)))] 1202: "! TARGET_POWER" 1.1.1.4 ! root 1203: "{muls.|mullw.} %0,%1,%2" 1.1 root 1204: [(set_attr "type" "delayed_compare")]) 1205: 1206: ;; Operand 1 is divided by operand 2; quotient goes to operand 1207: ;; 0 and remainder to operand 3. 1208: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 1209: 1.1.1.3 root 1210: (define_expand "divmodsi4" 1211: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1212: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1213: (match_operand:SI 2 "gpc_reg_operand" ""))) 1214: (set (match_operand:SI 3 "gpc_reg_operand" "") 1215: (mod:SI (match_dup 1) (match_dup 2)))])] 1216: "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" 1217: " 1218: { 1219: if (! TARGET_POWER && ! TARGET_POWERPC) 1220: { 1221: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1222: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1223: emit_insn (gen_divss_call ()); 1224: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1225: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); 1226: DONE; 1227: } 1228: }") 1229: 1230: (define_insn "" 1.1 root 1231: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1232: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1233: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1234: (set (match_operand:SI 3 "gpc_reg_operand" "=q") 1235: (mod:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 1236: "TARGET_POWER" 1237: "divs %0,%1,%2" 1238: [(set_attr "type" "idiv")]) 1239: 1240: (define_insn "" 1241: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1242: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1243: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1244: "TARGET_POWERPC" 1.1.1.3 root 1245: "divw %0,%1,%2" 1.1.1.2 root 1246: [(set_attr "type" "idiv")]) 1247: 1.1.1.3 root 1248: (define_expand "udivsi3" 1249: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1250: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1251: (match_operand:SI 2 "gpc_reg_operand" "")))] 1252: "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" 1253: " 1254: { 1255: if (! TARGET_POWER && ! TARGET_POWERPC) 1256: { 1257: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1258: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1259: emit_insn (gen_quous_call ()); 1260: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1261: DONE; 1262: } 1263: }") 1264: 1265: (define_insn "" 1.1.1.2 root 1266: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1267: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1268: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1269: "TARGET_POWERPC" 1.1.1.3 root 1270: "divwu %0,%1,%2" 1.1.1.2 root 1271: [(set_attr "type" "idiv")]) 1.1 root 1272: 1273: ;; For powers of two we can do srai/aze for divide and then adjust for 1.1.1.2 root 1274: ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 1.1.1.3 root 1275: ;; used; for PowerPC, force operands into register and do a normal divide; 1276: ;; for AIX common-mode, use quoss call on register operands. 1.1 root 1277: (define_expand "divsi3" 1278: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1279: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1280: (match_operand:SI 2 "reg_or_cint_operand" "")))] 1281: "" 1282: " 1283: { 1.1.1.2 root 1284: if (GET_CODE (operands[2]) == CONST_INT 1285: && exact_log2 (INTVAL (operands[2])) >= 0) 1286: ; 1.1.1.3 root 1287: else if (TARGET_POWER && ! TARGET_POWERPC) 1.1 root 1288: FAIL; 1.1.1.2 root 1289: else 1290: operands[2] = force_reg (SImode, operands[2]); 1.1.1.3 root 1291: 1292: if (! TARGET_POWER && ! TARGET_POWERPC) 1293: { 1294: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1295: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1296: emit_insn (gen_quoss_call ()); 1297: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1298: DONE; 1299: } 1.1 root 1300: }") 1301: 1302: (define_expand "modsi3" 1.1.1.2 root 1303: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1304: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1305: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 1.1 root 1306: "" 1307: " 1308: { 1309: int i = exact_log2 (INTVAL (operands[2])); 1.1.1.2 root 1310: rtx temp1; 1311: rtx temp2; 1.1 root 1312: 1313: if (GET_CODE (operands[2]) != CONST_INT || i < 0) 1314: FAIL; 1315: 1.1.1.2 root 1316: temp1 = gen_reg_rtx (SImode); 1317: temp2 = gen_reg_rtx (SImode); 1318: 1319: emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); 1320: emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); 1321: emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); 1322: DONE; 1.1 root 1323: }") 1324: 1325: (define_insn "" 1326: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1327: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1328: (match_operand:SI 2 "const_int_operand" "N")))] 1329: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1330: "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" 1331: [(set_attr "length" "8")]) 1.1 root 1332: 1333: (define_insn "" 1334: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1335: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1336: (match_operand:SI 2 "const_int_operand" "N")) 1337: (const_int 0))) 1.1 root 1338: (clobber (match_scratch:SI 3 "=r"))] 1339: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1340: "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" 1341: [(set_attr "type" "compare") 1342: (set_attr "length" "8")]) 1.1 root 1343: 1344: (define_insn "" 1345: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1346: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1347: (match_operand:SI 2 "const_int_operand" "N")) 1348: (const_int 0))) 1.1 root 1349: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1350: (div:SI (match_dup 1) (match_dup 2)))] 1351: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1352: "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" 1353: [(set_attr "type" "compare") 1354: (set_attr "length" "8")]) 1.1 root 1355: 1356: (define_insn "" 1357: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1358: (udiv:SI 1.1.1.3 root 1359: (plus:DI (ashift:DI 1.1 root 1360: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1361: (const_int 32)) 1362: (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 1363: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1364: (set (match_operand:SI 2 "register_operand" "=*q") 1365: (umod:SI 1.1.1.3 root 1366: (plus:DI (ashift:DI 1.1 root 1367: (zero_extend:DI (match_dup 1)) (const_int 32)) 1368: (zero_extend:DI (match_dup 4))) 1369: (match_dup 3)))] 1.1.1.2 root 1370: "TARGET_POWER" 1371: "div %0,%1,%3" 1372: [(set_attr "type" "idiv")]) 1.1 root 1373: 1374: ;; To do unsigned divide we handle the cases of the divisor looking like a 1375: ;; negative number. If it is a constant that is less than 2**31, we don't 1376: ;; have to worry about the branches. So make a few subroutines here. 1377: ;; 1378: ;; First comes the normal case. 1379: (define_expand "udivmodsi4_normal" 1380: [(set (match_dup 4) (const_int 0)) 1381: (parallel [(set (match_operand:SI 0 "" "") 1.1.1.3 root 1382: (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1383: (const_int 32)) 1384: (zero_extend:DI (match_operand:SI 1 "" ""))) 1385: (match_operand:SI 2 "" ""))) 1386: (set (match_operand:SI 3 "" "") 1.1.1.3 root 1387: (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1388: (const_int 32)) 1389: (zero_extend:DI (match_dup 1))) 1390: (match_dup 2)))])] 1.1.1.2 root 1391: "TARGET_POWER" 1.1 root 1392: " 1393: { operands[4] = gen_reg_rtx (SImode); }") 1394: 1395: ;; This handles the branches. 1396: (define_expand "udivmodsi4_tests" 1397: [(set (match_operand:SI 0 "" "") (const_int 0)) 1398: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 1399: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 1400: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 1401: (label_ref (match_operand:SI 4 "" "")) (pc))) 1402: (set (match_dup 0) (const_int 1)) 1403: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 1404: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 1405: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 1406: (label_ref (match_dup 4)) (pc)))] 1.1.1.2 root 1407: "TARGET_POWER" 1.1 root 1408: " 1409: { operands[5] = gen_reg_rtx (CCUNSmode); 1410: operands[6] = gen_reg_rtx (CCmode); 1411: }") 1412: 1413: (define_expand "udivmodsi4" 1414: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1415: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1416: (match_operand:SI 2 "reg_or_cint_operand" ""))) 1417: (set (match_operand:SI 3 "gpc_reg_operand" "") 1418: (umod:SI (match_dup 1) (match_dup 2)))])] 1.1.1.3 root 1419: "" 1.1 root 1420: " 1421: { 1422: rtx label = 0; 1423: 1.1.1.3 root 1424: if (! TARGET_POWER) 1425: if (! TARGET_POWERPC) 1426: { 1427: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1428: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1429: emit_insn (gen_divus_call ()); 1430: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1431: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); 1432: DONE; 1433: } 1434: else 1435: FAIL; 1436: 1.1 root 1437: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 1438: { 1439: operands[2] = force_reg (SImode, operands[2]); 1440: label = gen_label_rtx (); 1441: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 1442: operands[3], label)); 1443: } 1444: else 1445: operands[2] = force_reg (SImode, operands[2]); 1446: 1447: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 1448: operands[3])); 1449: if (label) 1450: emit_label (label); 1451: 1452: DONE; 1453: }") 1.1.1.3 root 1454: 1455: ;; AIX architecture-independent common-mode multiply (DImode), 1456: ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and 1.1.1.4 ! root 1457: ;; R4; results in R3 and sometimes R4; link register always clobbered by bla 1.1.1.3 root 1458: ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but 1459: ;; assumed unused if generating common-mode, so ignore. 1460: (define_insn "mulh_call" 1461: [(set (reg:SI 3) 1462: (truncate:SI 1463: (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) 1464: (sign_extend:DI (reg:SI 4))) 1465: (const_int 32)))) 1466: (clobber (match_scratch:SI 0 "=l"))] 1467: "! TARGET_POWER && ! TARGET_POWERPC" 1468: "bla __mulh") 1469: 1470: (define_insn "mull_call" 1471: [(set (reg:DI 3) 1472: (mult:DI (sign_extend:DI (reg:SI 3)) 1473: (sign_extend:DI (reg:SI 4)))) 1474: (clobber (match_scratch:SI 0 "=l")) 1475: (clobber (reg:SI 0))] 1476: "! TARGET_POWER && ! TARGET_POWERPC" 1477: "bla __mull") 1478: 1479: (define_insn "divss_call" 1480: [(set (reg:SI 3) 1481: (div:SI (reg:SI 3) (reg:SI 4))) 1482: (set (reg:SI 4) 1483: (mod:SI (reg:SI 3) (reg:SI 4))) 1484: (clobber (match_scratch:SI 0 "=l")) 1485: (clobber (reg:SI 0))] 1486: "! TARGET_POWER && ! TARGET_POWERPC" 1487: "bla __divss") 1488: 1489: (define_insn "divus_call" 1490: [(set (reg:SI 3) 1491: (udiv:SI (reg:SI 3) (reg:SI 4))) 1492: (set (reg:SI 4) 1493: (umod:SI (reg:SI 3) (reg:SI 4))) 1494: (clobber (match_scratch:SI 0 "=l")) 1495: (clobber (reg:SI 0))] 1496: "! TARGET_POWER && ! TARGET_POWERPC" 1497: "bla __divus") 1498: 1499: (define_insn "quoss_call" 1500: [(set (reg:SI 3) 1501: (div:SI (reg:SI 3) (reg:SI 4))) 1502: (clobber (match_scratch:SI 0 "=l"))] 1503: "! TARGET_POWER && ! TARGET_POWERPC" 1504: "bla __quoss") 1505: 1506: (define_insn "quous_call" 1507: [(set (reg:SI 3) 1508: (udiv:SI (reg:SI 3) (reg:SI 4))) 1509: (clobber (match_scratch:SI 0 "=l")) 1510: (clobber (reg:SI 0))] 1511: "! TARGET_POWER && ! TARGET_POWERPC" 1512: "bla __quous") 1513: 1.1 root 1514: (define_insn "andsi3" 1515: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1516: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1517: (match_operand:SI 2 "and_operand" "?r,L,K,J"))) 1518: (clobber (match_scratch:CC 3 "=X,X,x,x"))] 1519: "" 1520: "@ 1521: and %0,%1,%2 1.1.1.2 root 1522: {rlinm|rlwinm} %0,%1,0,%m2,%M2 1523: {andil.|andi.} %0,%1,%b2 1524: {andiu.|andis.} %0,%1,%u2") 1.1 root 1525: 1526: (define_insn "" 1527: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") 1528: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1529: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1530: (const_int 0))) 1531: (clobber (match_scratch:SI 3 "=r,r,r,r"))] 1532: "" 1533: "@ 1534: and. %3,%1,%2 1.1.1.2 root 1535: {andil.|andi.} %3,%1,%b2 1536: {andiu.|andis.} %3,%1,%u2 1537: {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" 1.1 root 1538: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1539: 1540: (define_insn "" 1541: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") 1542: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1543: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1544: (const_int 0))) 1545: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1546: (and:SI (match_dup 1) (match_dup 2)))] 1547: "" 1548: "@ 1549: and. %0,%1,%2 1.1.1.2 root 1550: {andil.|andi.} %0,%1,%b2 1551: {andiu.|andis.} %0,%1,%u2 1552: {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" 1553: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1.1 root 1554: 1555: ;; Take a AND with a constant that cannot be done in a single insn and try to 1556: ;; split it into two insns. This does not verify that the insns are valid 1557: ;; since this need not be done as combine will do it. 1558: 1559: (define_split 1560: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1561: (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1562: (match_operand:SI 2 "non_and_cint_operand" "")))] 1563: "" 1564: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) 1565: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] 1566: " 1567: { 1568: int maskval = INTVAL (operands[2]); 1569: int i, transitions, last_bit_value; 1570: int orig = maskval, first_c = maskval, second_c; 1571: 1572: /* We know that MASKVAL must have more than 2 bit-transitions. Start at 1573: the low-order bit and count for the third transition. When we get there, 1574: make a first mask that has everything to the left of that position 1575: a one. Then make the second mask to turn off whatever else is needed. */ 1576: 1577: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) 1578: { 1579: if (((maskval >>= 1) & 1) != last_bit_value) 1580: last_bit_value ^= 1, transitions++; 1581: 1582: if (transitions > 2) 1583: { 1584: first_c |= (~0) << i; 1585: break; 1586: } 1587: } 1588: 1589: second_c = orig | ~ first_c; 1590: 1591: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); 1592: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); 1593: }") 1594: 1595: (define_insn "iorsi3" 1596: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1597: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1598: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1599: "" 1600: "@ 1601: or %0,%1,%2 1.1.1.2 root 1602: {oril|ori} %0,%1,%b2 1603: {oriu|oris} %0,%1,%u2") 1.1 root 1604: 1605: (define_insn "" 1606: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1607: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1608: (match_operand:SI 2 "gpc_reg_operand" "r")) 1609: (const_int 0))) 1610: (clobber (match_scratch:SI 3 "=r"))] 1611: "" 1612: "or. %3,%1,%2" 1613: [(set_attr "type" "compare")]) 1614: 1615: (define_insn "" 1616: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1617: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1618: (match_operand:SI 2 "gpc_reg_operand" "r")) 1619: (const_int 0))) 1620: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1621: (ior:SI (match_dup 1) (match_dup 2)))] 1622: "" 1623: "or. %0,%1,%2" 1624: [(set_attr "type" "compare")]) 1625: 1626: ;; Split an IOR that we can't do in one insn into two insns, each of which 1627: ;; does one 16-bit part. This is used by combine. 1628: 1629: (define_split 1630: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1631: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 1632: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1633: "" 1634: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) 1635: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] 1636: " 1637: { 1638: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1639: INTVAL (operands[2]) & 0xffff0000); 1640: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1641: }") 1642: 1643: (define_insn "xorsi3" 1644: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1645: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1646: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1647: "" 1648: "@ 1649: xor %0,%1,%2 1.1.1.2 root 1650: {xoril|xori} %0,%1,%b2 1651: {xoriu|xoris} %0,%1,%u2") 1.1 root 1652: 1653: (define_insn "" 1654: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1655: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1656: (match_operand:SI 2 "gpc_reg_operand" "r")) 1657: (const_int 0))) 1658: (clobber (match_scratch:SI 3 "=r"))] 1659: "" 1660: "xor. %3,%1,%2" 1661: [(set_attr "type" "compare")]) 1662: 1663: (define_insn "" 1664: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1665: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1666: (match_operand:SI 2 "gpc_reg_operand" "r")) 1667: (const_int 0))) 1668: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1669: (xor:SI (match_dup 1) (match_dup 2)))] 1670: "" 1671: "xor. %0,%1,%2" 1672: [(set_attr "type" "compare")]) 1673: 1674: ;; Split an XOR that we can't do in one insn into two insns, each of which 1675: ;; does one 16-bit part. This is used by combine. 1676: 1677: (define_split 1678: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1679: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1680: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1681: "" 1682: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) 1683: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] 1684: " 1685: { 1686: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1687: INTVAL (operands[2]) & 0xffff0000); 1688: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1689: }") 1690: 1691: (define_insn "" 1692: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1693: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1694: (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1695: "" 1696: "eqv %0,%1,%2") 1697: 1698: (define_insn "" 1699: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1700: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1701: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1702: (const_int 0))) 1703: (clobber (match_scratch:SI 3 "=r"))] 1704: "" 1705: "eqv. %3,%1,%2" 1706: [(set_attr "type" "compare")]) 1707: 1708: (define_insn "" 1709: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1710: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1711: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1712: (const_int 0))) 1713: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1714: (not:SI (xor:SI (match_dup 1) (match_dup 2))))] 1715: "" 1716: "eqv. %0,%1,%2" 1717: [(set_attr "type" "compare")]) 1718: 1719: (define_insn "" 1720: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1721: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1722: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1723: "" 1724: "andc %0,%2,%1") 1725: 1726: (define_insn "" 1727: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1728: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1729: (match_operand:SI 2 "gpc_reg_operand" "r")) 1730: (const_int 0))) 1731: (clobber (match_scratch:SI 3 "=r"))] 1732: "" 1733: "andc. %3,%2,%1" 1734: [(set_attr "type" "compare")]) 1735: 1736: (define_insn "" 1737: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1738: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1739: (match_operand:SI 2 "gpc_reg_operand" "r")) 1740: (const_int 0))) 1741: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1742: (and:SI (not:SI (match_dup 1)) (match_dup 2)))] 1743: "" 1744: "andc. %0,%2,%1" 1745: [(set_attr "type" "compare")]) 1746: 1747: (define_insn "" 1748: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1749: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1750: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1751: "" 1752: "orc %0,%2,%1") 1753: 1754: (define_insn "" 1755: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1756: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1757: (match_operand:SI 2 "gpc_reg_operand" "r")) 1758: (const_int 0))) 1759: (clobber (match_scratch:SI 3 "=r"))] 1760: "" 1761: "orc. %3,%2,%1" 1762: [(set_attr "type" "compare")]) 1763: 1764: (define_insn "" 1765: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1766: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1767: (match_operand:SI 2 "gpc_reg_operand" "r")) 1768: (const_int 0))) 1769: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1770: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] 1771: "" 1772: "orc. %0,%2,%1" 1773: [(set_attr "type" "compare")]) 1774: 1775: (define_insn "" 1776: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 1777: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1778: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1779: "" 1780: "nand %0,%1,%2") 1781: 1782: (define_insn "" 1783: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1784: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1785: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1786: (const_int 0))) 1787: (clobber (match_scratch:SI 3 "=r"))] 1788: "" 1789: "nand. %3,%1,%2" 1790: [(set_attr "type" "compare")]) 1791: 1792: (define_insn "" 1793: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1794: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1795: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1796: (const_int 0))) 1797: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1798: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1799: "" 1800: "nand. %0,%1,%2" 1801: [(set_attr "type" "compare")]) 1802: 1803: (define_insn "" 1804: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 1805: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1806: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1807: "" 1808: "nor %0,%1,%2") 1809: 1810: (define_insn "" 1811: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1812: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1813: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1814: (const_int 0))) 1815: (clobber (match_scratch:SI 3 "=r"))] 1816: "" 1817: "nor. %3,%1,%2" 1818: [(set_attr "type" "compare")]) 1819: 1820: (define_insn "" 1821: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1822: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1823: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1824: (const_int 0))) 1825: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1826: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1827: "" 1828: "nor. %0,%1,%2" 1829: [(set_attr "type" "compare")]) 1830: 1831: ;; maskir insn. We need four forms because things might be in arbitrary 1832: ;; orders. Don't define forms that only set CR fields because these 1833: ;; would modify an input register. 1834: 1835: (define_insn "" 1836: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1837: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1838: (match_operand:SI 1 "gpc_reg_operand" "0")) 1839: (and:SI (match_dup 2) 1840: (match_operand:SI 3 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1841: "TARGET_POWER" 1.1 root 1842: "maskir %0,%3,%2") 1843: 1844: (define_insn "" 1.1.1.4 ! root 1845: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1846: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1847: (match_operand:SI 1 "gpc_reg_operand" "0")) 1848: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1849: (match_dup 2))))] 1.1.1.2 root 1850: "TARGET_POWER" 1.1 root 1851: "maskir %0,%3,%2") 1852: 1853: (define_insn "" 1854: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1855: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1856: (match_operand:SI 3 "gpc_reg_operand" "r")) 1857: (and:SI (not:SI (match_dup 2)) 1858: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1859: "TARGET_POWER" 1.1 root 1860: "maskir %0,%3,%2") 1861: 1862: (define_insn "" 1863: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1864: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1865: (match_operand:SI 2 "gpc_reg_operand" "r")) 1866: (and:SI (not:SI (match_dup 2)) 1867: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1868: "TARGET_POWER" 1.1 root 1869: "maskir %0,%3,%2") 1870: 1871: (define_insn "" 1872: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1873: (compare:CC 1874: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1875: (match_operand:SI 1 "gpc_reg_operand" "0")) 1876: (and:SI (match_dup 2) 1877: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1878: (const_int 0))) 1879: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1880: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1881: (and:SI (match_dup 2) (match_dup 3))))] 1.1.1.2 root 1882: "TARGET_POWER" 1.1 root 1883: "maskir. %0,%3,%2" 1884: [(set_attr "type" "compare")]) 1885: 1886: (define_insn "" 1887: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1888: (compare:CC 1889: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1890: (match_operand:SI 1 "gpc_reg_operand" "0")) 1891: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1892: (match_dup 2))) 1893: (const_int 0))) 1.1.1.4 ! root 1894: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1895: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1896: (and:SI (match_dup 3) (match_dup 2))))] 1.1.1.2 root 1897: "TARGET_POWER" 1.1 root 1898: "maskir. %0,%3,%2" 1899: [(set_attr "type" "compare")]) 1900: 1901: (define_insn "" 1902: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1903: (compare:CC 1904: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1905: (match_operand:SI 3 "gpc_reg_operand" "r")) 1906: (and:SI (not:SI (match_dup 2)) 1907: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1908: (const_int 0))) 1909: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1910: (ior:SI (and:SI (match_dup 2) (match_dup 3)) 1911: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1912: "TARGET_POWER" 1.1 root 1913: "maskir. %0,%3,%2" 1914: [(set_attr "type" "compare")]) 1915: 1916: (define_insn "" 1917: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1918: (compare:CC 1919: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1920: (match_operand:SI 2 "gpc_reg_operand" "r")) 1921: (and:SI (not:SI (match_dup 2)) 1922: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1923: (const_int 0))) 1924: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1925: (ior:SI (and:SI (match_dup 3) (match_dup 2)) 1926: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1927: "TARGET_POWER" 1.1 root 1928: "maskir. %0,%3,%2" 1929: [(set_attr "type" "compare")]) 1930: 1931: ;; Rotate and shift insns, in all their variants. These support shifts, 1932: ;; field inserts and extracts, and various combinations thereof. 1.1.1.4 ! root 1933: (define_expand "insv" ! 1934: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1935: (match_operand:SI 1 "const_int_operand" "i") ! 1936: (match_operand:SI 2 "const_int_operand" "i")) ! 1937: (match_operand:SI 3 "gpc_reg_operand" "r"))] ! 1938: "" ! 1939: " ! 1940: { ! 1941: /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since ! 1942: the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the ! 1943: compiler if the address of the structure is taken later. */ ! 1944: if (GET_CODE (operands[0]) == SUBREG ! 1945: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) ! 1946: FAIL; ! 1947: }") ! 1948: ! 1949: (define_insn "" 1.1 root 1950: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1951: (match_operand:SI 1 "const_int_operand" "i") 1952: (match_operand:SI 2 "const_int_operand" "i")) 1953: (match_operand:SI 3 "gpc_reg_operand" "r"))] 1954: "" 1955: "* 1956: { 1957: int start = INTVAL (operands[2]) & 31; 1958: int size = INTVAL (operands[1]) & 31; 1959: 1960: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); 1961: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 1.1.1.2 root 1962: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 1.1 root 1963: }") 1964: 1.1.1.4 ! root 1965: (define_insn "" ! 1966: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1967: (match_operand:SI 1 "const_int_operand" "i") ! 1968: (match_operand:SI 2 "const_int_operand" "i")) ! 1969: (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1970: (match_operand:SI 4 "const_int_operand" "i")))] ! 1971: "" ! 1972: "* ! 1973: { ! 1974: int shift = INTVAL (operands[4]) & 31; ! 1975: int start = INTVAL (operands[2]) & 31; ! 1976: int size = INTVAL (operands[1]) & 31; ! 1977: ! 1978: operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31); ! 1979: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); ! 1980: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; ! 1981: }") ! 1982: ! 1983: (define_insn "" ! 1984: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1985: (match_operand:SI 1 "const_int_operand" "i") ! 1986: (match_operand:SI 2 "const_int_operand" "i")) ! 1987: (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1988: (match_operand:SI 4 "const_int_operand" "i")))] ! 1989: "" ! 1990: "* ! 1991: { ! 1992: int shift = INTVAL (operands[4]) & 31; ! 1993: int start = INTVAL (operands[2]) & 31; ! 1994: int size = INTVAL (operands[1]) & 31; ! 1995: ! 1996: operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31); ! 1997: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); ! 1998: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; ! 1999: }") ! 2000: ! 2001: (define_insn "" ! 2002: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 2003: (match_operand:SI 1 "const_int_operand" "i") ! 2004: (match_operand:SI 2 "const_int_operand" "i")) ! 2005: (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 2006: (match_operand:SI 4 "const_int_operand" "i")))] ! 2007: "" ! 2008: "* ! 2009: { ! 2010: int shift = INTVAL (operands[4]) & 31; ! 2011: int start = INTVAL (operands[2]) & 31; ! 2012: int size = INTVAL (operands[1]) & 31; ! 2013: ! 2014: operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31); ! 2015: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); ! 2016: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; ! 2017: }") ! 2018: ! 2019: (define_insn "" ! 2020: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 2021: (match_operand:SI 1 "const_int_operand" "i") ! 2022: (match_operand:SI 2 "const_int_operand" "i")) ! 2023: (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 2024: (match_operand:SI 4 "const_int_operand" "i") ! 2025: (match_operand:SI 5 "const_int_operand" "i")))] ! 2026: "INTVAL (operands[4]) >= INTVAL (operands[1])" ! 2027: "* ! 2028: { ! 2029: int extract_start = INTVAL (operands[5]) & 31; ! 2030: int extract_size = INTVAL (operands[4]) & 31; ! 2031: int insert_start = INTVAL (operands[2]) & 31; ! 2032: int insert_size = INTVAL (operands[1]) & 31; ! 2033: ! 2034: /* Align extract field with insert field */ ! 2035: operands[5] = gen_rtx (CONST_INT, VOIDmode, ! 2036: (extract_start + extract_size - insert_start - insert_size) & 31); ! 2037: operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1); ! 2038: return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\"; ! 2039: }") ! 2040: ! 2041: (define_expand "extzv" ! 2042: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 2043: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 2044: (match_operand:SI 2 "const_int_operand" "i") ! 2045: (match_operand:SI 3 "const_int_operand" "i")))] ! 2046: "" ! 2047: " ! 2048: { ! 2049: /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since ! 2050: the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the ! 2051: compiler if the address of the structure is taken later. */ ! 2052: if (GET_CODE (operands[0]) == SUBREG ! 2053: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) ! 2054: FAIL; ! 2055: }") ! 2056: ! 2057: (define_insn "" 1.1 root 2058: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2059: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2060: (match_operand:SI 2 "const_int_operand" "i") 2061: (match_operand:SI 3 "const_int_operand" "i")))] 2062: "" 2063: "* 2064: { 2065: int start = INTVAL (operands[3]) & 31; 2066: int size = INTVAL (operands[2]) & 31; 2067: 2068: if (start + size >= 32) 2069: operands[3] = const0_rtx; 2070: else 2071: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2072: return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 1.1 root 2073: }") 2074: 2075: (define_insn "" 2076: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2077: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2078: (match_operand:SI 2 "const_int_operand" "i") 2079: (match_operand:SI 3 "const_int_operand" "i")) 2080: (const_int 0))) 2081: (clobber (match_scratch:SI 4 "=r"))] 2082: "" 2083: "* 2084: { 2085: int start = INTVAL (operands[3]) & 31; 2086: int size = INTVAL (operands[2]) & 31; 2087: 2088: /* If the bitfield being tested fits in the upper or lower half of a 2089: word, it is possible to use andiu. or andil. to test it. This is 2090: useful because the condition register set-use delay is smaller for 2091: andi[ul]. than for rlinm. This doesn't work when the starting bit 2092: position is 0 because the LT and GT bits may be set wrong. */ 2093: 2094: if ((start > 0 && start + size <= 16) || start >= 16) 2095: { 2096: operands[3] = gen_rtx (CONST_INT, VOIDmode, 2097: ((1 << (16 - (start & 15))) 2098: - (1 << (16 - (start & 15) - size)))); 2099: if (start < 16) 1.1.1.2 root 2100: return \"{andiu.|andis.} %4,%1,%3\"; 1.1 root 2101: else 1.1.1.2 root 2102: return \"{andil.|andi.} %4,%1,%3\"; 1.1 root 2103: } 1.1.1.4 ! root 2104: 1.1 root 2105: if (start + size >= 32) 2106: operands[3] = const0_rtx; 2107: else 2108: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2109: return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 1.1 root 2110: }" 2111: [(set_attr "type" "compare")]) 2112: 2113: (define_insn "" 2114: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2115: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2116: (match_operand:SI 2 "const_int_operand" "i") 2117: (match_operand:SI 3 "const_int_operand" "i")) 2118: (const_int 0))) 2119: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2120: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 2121: "" 2122: "* 2123: { 2124: int start = INTVAL (operands[3]) & 31; 2125: int size = INTVAL (operands[2]) & 31; 2126: 2127: if (start >= 16 && start + size == 32) 2128: { 2129: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); 1.1.1.2 root 2130: return \"{andil.|andi.} %0,%1,%3\"; 1.1 root 2131: } 1.1.1.4 ! root 2132: 1.1 root 2133: if (start + size >= 32) 2134: operands[3] = const0_rtx; 2135: else 2136: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2137: return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 1.1 root 2138: }" 2139: [(set_attr "type" "delayed_compare")]) 2140: 2141: (define_insn "rotlsi3" 2142: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2143: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2144: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2145: "" 1.1.1.2 root 2146: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 1.1 root 2147: 2148: (define_insn "" 2149: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2150: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2151: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2152: (const_int 0))) 2153: (clobber (match_scratch:SI 3 "=r"))] 2154: "" 1.1.1.2 root 2155: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" 1.1 root 2156: [(set_attr "type" "delayed_compare")]) 2157: 2158: (define_insn "" 2159: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2160: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2161: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2162: (const_int 0))) 2163: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2164: (rotate:SI (match_dup 1) (match_dup 2)))] 2165: "" 1.1.1.2 root 2166: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" 1.1 root 2167: [(set_attr "type" "delayed_compare")]) 2168: 2169: (define_insn "" 2170: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2171: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2172: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2173: (match_operand:SI 3 "mask_operand" "L")))] 2174: "" 1.1.1.2 root 2175: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 1.1 root 2176: 2177: (define_insn "" 2178: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2179: (compare:CC (and:SI 2180: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2181: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2182: (match_operand:SI 3 "mask_operand" "L")) 2183: (const_int 0))) 2184: (clobber (match_scratch:SI 4 "=r"))] 2185: "" 1.1.1.2 root 2186: "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" 1.1 root 2187: [(set_attr "type" "delayed_compare")]) 2188: 2189: (define_insn "" 2190: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2191: (compare:CC (and:SI 2192: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2193: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2194: (match_operand:SI 3 "mask_operand" "L")) 2195: (const_int 0))) 2196: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2197: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2198: "" 1.1.1.2 root 2199: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" 1.1 root 2200: [(set_attr "type" "delayed_compare")]) 2201: 2202: (define_insn "" 2203: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2204: (zero_extend:SI 2205: (subreg:QI 2206: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2207: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2208: "" 1.1.1.2 root 2209: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 1.1 root 2210: 2211: (define_insn "" 2212: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2213: (compare:CC (zero_extend:SI 2214: (subreg:QI 2215: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2216: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2217: (const_int 0))) 2218: (clobber (match_scratch:SI 3 "=r"))] 2219: "" 1.1.1.2 root 2220: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" 1.1 root 2221: [(set_attr "type" "delayed_compare")]) 2222: 2223: (define_insn "" 2224: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2225: (compare:CC (zero_extend:SI 2226: (subreg:QI 2227: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2228: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2229: (const_int 0))) 2230: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2231: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2232: "" 1.1.1.2 root 2233: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" 1.1 root 2234: [(set_attr "type" "delayed_compare")]) 2235: 2236: (define_insn "" 2237: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2238: (zero_extend:SI 2239: (subreg:HI 2240: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2241: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2242: "" 1.1.1.2 root 2243: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 1.1 root 2244: 2245: (define_insn "" 2246: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2247: (compare:CC (zero_extend:SI 2248: (subreg:HI 2249: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2250: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2251: (const_int 0))) 2252: (clobber (match_scratch:SI 3 "=r"))] 2253: "" 1.1.1.2 root 2254: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" 1.1 root 2255: [(set_attr "type" "delayed_compare")]) 2256: 2257: (define_insn "" 2258: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2259: (compare:CC (zero_extend:SI 2260: (subreg:HI 2261: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2262: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2263: (const_int 0))) 2264: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2265: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2266: "" 1.1.1.2 root 2267: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" 1.1 root 2268: [(set_attr "type" "delayed_compare")]) 2269: 2270: ;; Note that we use "sle." instead of "sl." so that we can set 2271: ;; SHIFT_COUNT_TRUNCATED. 2272: 1.1.1.2 root 2273: (define_expand "ashlsi3" 2274: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2275: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2276: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2277: "" 2278: " 2279: { 2280: if (TARGET_POWER) 2281: emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 2282: else 2283: emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 2284: DONE; 2285: }") 2286: 2287: (define_insn "ashlsi3_power" 1.1 root 2288: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2289: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2290: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2291: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2292: "TARGET_POWER" 1.1 root 2293: "@ 2294: sle %0,%1,%2 1.1.1.2 root 2295: {sli|slwi} %0,%1,%h2" 2296: [(set_attr "length" "8")]) 2297: 2298: (define_insn "ashlsi3_no_power" 2299: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2300: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2301: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2302: "! TARGET_POWER" 1.1.1.4 ! root 2303: "{sl|slw}%I2 %0,%1,%h2" 1.1.1.2 root 2304: [(set_attr "length" "8")]) 1.1 root 2305: 2306: (define_insn "" 2307: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2308: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2309: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2310: (const_int 0))) 2311: (clobber (match_scratch:SI 3 "=r,r")) 2312: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2313: "TARGET_POWER" 1.1 root 2314: "@ 2315: sle. %3,%1,%2 1.1.1.2 root 2316: {sli.|slwi.} %3,%1,%h2" 2317: [(set_attr "type" "delayed_compare")]) 2318: 2319: (define_insn "" 2320: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2321: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2322: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2323: (const_int 0))) 2324: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 root 2325: "! TARGET_POWER" 1.1.1.4 ! root 2326: "{sl|slw}%I2. %3,%1,%h2" 1.1 root 2327: [(set_attr "type" "delayed_compare")]) 2328: 2329: (define_insn "" 2330: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2331: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2332: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2333: (const_int 0))) 2334: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2335: (ashift:SI (match_dup 1) (match_dup 2))) 2336: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2337: "TARGET_POWER" 1.1 root 2338: "@ 2339: sle. %0,%1,%2 1.1.1.2 root 2340: {sli.|slwi.} %0,%1,%h2" 2341: [(set_attr "type" "delayed_compare")]) 2342: 2343: (define_insn "" 2344: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2345: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2346: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2347: (const_int 0))) 2348: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2349: (ashift:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 2350: "! TARGET_POWER" 1.1.1.4 ! root 2351: "{sl|slw}%I2. %0,%1,%h2" 1.1 root 2352: [(set_attr "type" "delayed_compare")]) 2353: 2354: (define_insn "" 2355: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2356: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2357: (match_operand:SI 2 "const_int_operand" "i")) 2358: (match_operand:SI 3 "mask_operand" "L")))] 2359: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 ! root 2360: "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") 1.1 root 2361: 2362: (define_insn "" 2363: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2364: (compare:CC 2365: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2366: (match_operand:SI 2 "const_int_operand" "i")) 2367: (match_operand:SI 3 "mask_operand" "L")) 2368: (const_int 0))) 2369: (clobber (match_scratch:SI 4 "=r"))] 2370: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 ! root 2371: "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" 1.1 root 2372: [(set_attr "type" "delayed_compare")]) 2373: 2374: (define_insn "" 2375: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2376: (compare:CC 2377: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2378: (match_operand:SI 2 "const_int_operand" "i")) 2379: (match_operand:SI 3 "mask_operand" "L")) 2380: (const_int 0))) 2381: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2382: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2383: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 ! root 2384: "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" 1.1 root 2385: [(set_attr "type" "delayed_compare")]) 2386: 1.1.1.2 root 2387: ;; The AIX assembler mis-handles "sri x,x,0", so write that case as 1.1 root 2388: ;; "sli x,x,0". 1.1.1.2 root 2389: (define_expand "lshrsi3" 2390: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2391: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2392: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2393: "" 2394: " 2395: { 2396: if (TARGET_POWER) 2397: emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 2398: else 2399: emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 2400: DONE; 2401: }") 2402: 2403: (define_insn "lshrsi3_power" 1.1 root 2404: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2405: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2406: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2407: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2408: "TARGET_POWER" 1.1 root 2409: "@ 2410: sre %0,%1,%2 1.1.1.2 root 2411: {s%A2i|s%A2wi} %0,%1,%h2") 2412: 2413: (define_insn "lshrsi3_no_power" 2414: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2415: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2416: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2417: "! TARGET_POWER" 1.1.1.4 ! root 2418: "{sr|srw}%I2 %0,%1,%h2") 1.1 root 2419: 2420: (define_insn "" 2421: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2422: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2423: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2424: (const_int 0))) 2425: (clobber (match_scratch:SI 3 "=r,r")) 2426: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2427: "TARGET_POWER" 1.1 root 2428: "@ 2429: sre. %3,%1,%2 1.1.1.2 root 2430: {s%A2i.|s%A2wi.} %3,%1,%h2" 2431: [(set_attr "type" "delayed_compare")]) 2432: 2433: (define_insn "" 2434: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2435: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2436: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2437: (const_int 0))) 2438: (clobber (match_scratch:SI 3 "=r"))] 2439: "! TARGET_POWER" 1.1.1.4 ! root 2440: "{sr|srw}%I2. %3,%1,%h2" 1.1 root 2441: [(set_attr "type" "delayed_compare")]) 2442: 2443: (define_insn "" 2444: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2445: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2446: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2447: (const_int 0))) 2448: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2449: (lshiftrt:SI (match_dup 1) (match_dup 2))) 2450: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2451: "TARGET_POWER" 1.1 root 2452: "@ 2453: sre. %0,%1,%2 1.1.1.2 root 2454: {s%A2i.|s%A2wi.} %0,%1,%h2" 2455: [(set_attr "type" "delayed_compare")]) 2456: 2457: (define_insn "" 2458: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2459: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2460: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2461: (const_int 0))) 2462: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2463: (lshiftrt:SI (match_dup 1) (match_dup 2)))] 2464: "! TARGET_POWER" 1.1.1.4 ! root 2465: "{sr|srw}%I2. %0,%1,%h2" 1.1 root 2466: [(set_attr "type" "delayed_compare")]) 2467: 2468: (define_insn "" 2469: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2470: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2471: (match_operand:SI 2 "const_int_operand" "i")) 2472: (match_operand:SI 3 "mask_operand" "L")))] 2473: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2474: "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 1.1 root 2475: 2476: (define_insn "" 2477: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2478: (compare:CC 2479: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2480: (match_operand:SI 2 "const_int_operand" "i")) 2481: (match_operand:SI 3 "mask_operand" "L")) 2482: (const_int 0))) 2483: (clobber (match_scratch:SI 4 "=r"))] 2484: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2485: "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" 1.1 root 2486: [(set_attr "type" "delayed_compare")]) 2487: 2488: (define_insn "" 2489: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2490: (compare:CC 2491: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2492: (match_operand:SI 2 "const_int_operand" "i")) 2493: (match_operand:SI 3 "mask_operand" "L")) 2494: (const_int 0))) 2495: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2496: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2497: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2498: "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" 1.1 root 2499: [(set_attr "type" "delayed_compare")]) 2500: 2501: (define_insn "" 2502: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2503: (zero_extend:SI 2504: (subreg:QI 2505: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2506: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2507: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2508: "{rlinm|rlwinm} %0,%1,%s2,0xff") 1.1 root 2509: 2510: (define_insn "" 2511: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2512: (compare:CC 2513: (zero_extend:SI 2514: (subreg:QI 2515: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2516: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2517: (const_int 0))) 2518: (clobber (match_scratch:SI 3 "=r"))] 2519: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2520: "{rlinm.|rlwinm.} %3,%1,%s2,0xff" 1.1 root 2521: [(set_attr "type" "delayed_compare")]) 2522: 2523: (define_insn "" 2524: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2525: (compare:CC 2526: (zero_extend:SI 2527: (subreg:QI 2528: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2529: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2530: (const_int 0))) 2531: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2532: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2533: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2534: "{rlinm.|rlwinm.} %0,%1,%s2,0xff" 1.1 root 2535: [(set_attr "type" "delayed_compare")]) 2536: 2537: (define_insn "" 2538: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2539: (zero_extend:SI 2540: (subreg:HI 2541: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2542: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2543: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2544: "{rlinm|rlwinm} %0,%1,%s2,0xffff") 1.1 root 2545: 2546: (define_insn "" 2547: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2548: (compare:CC 2549: (zero_extend:SI 2550: (subreg:HI 2551: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2552: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2553: (const_int 0))) 2554: (clobber (match_scratch:SI 3 "=r"))] 2555: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2556: "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" 1.1 root 2557: [(set_attr "type" "delayed_compare")]) 2558: 2559: (define_insn "" 2560: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2561: (compare:CC 2562: (zero_extend:SI 2563: (subreg:HI 2564: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2565: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2566: (const_int 0))) 2567: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2568: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2569: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2570: "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" 1.1 root 2571: [(set_attr "type" "delayed_compare")]) 2572: 2573: (define_insn "" 2574: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2575: (const_int 1) 2576: (match_operand:SI 1 "gpc_reg_operand" "r")) 2577: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2578: (const_int 31)))] 1.1.1.2 root 2579: "TARGET_POWER" 1.1 root 2580: "rrib %0,%1,%2") 2581: 2582: (define_insn "" 2583: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2584: (const_int 1) 2585: (match_operand:SI 1 "gpc_reg_operand" "r")) 2586: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2587: (const_int 31)))] 1.1.1.2 root 2588: "TARGET_POWER" 1.1 root 2589: "rrib %0,%1,%2") 2590: 2591: (define_insn "" 2592: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2593: (const_int 1) 2594: (match_operand:SI 1 "gpc_reg_operand" "r")) 2595: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2596: (const_int 1) 2597: (const_int 0)))] 1.1.1.2 root 2598: "TARGET_POWER" 1.1 root 2599: "rrib %0,%1,%2") 2600: 1.1.1.2 root 2601: (define_expand "ashrsi3" 2602: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2603: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 2604: (match_operand:SI 2 "reg_or_cint_operand" "")))] 2605: "" 2606: " 2607: { 2608: if (TARGET_POWER) 2609: emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 2610: else 2611: emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 2612: DONE; 2613: }") 2614: 2615: (define_insn "ashrsi3_power" 1.1 root 2616: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2617: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2618: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2619: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2620: "TARGET_POWER" 1.1 root 2621: "@ 2622: srea %0,%1,%2 1.1.1.2 root 2623: {srai|srawi} %0,%1,%h2") 2624: 2625: (define_insn "ashrsi3_no_power" 2626: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2627: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2628: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2629: "! TARGET_POWER" 1.1.1.4 ! root 2630: "{sra|sraw}%I2 %0,%1,%h2") 1.1 root 2631: 2632: (define_insn "" 2633: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2634: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2635: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2636: (const_int 0))) 2637: (clobber (match_scratch:SI 3 "=r,r")) 2638: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2639: "TARGET_POWER" 1.1 root 2640: "@ 2641: srea. %3,%1,%2 1.1.1.2 root 2642: {srai.|srawi.} %3,%1,%h2" 2643: [(set_attr "type" "delayed_compare")]) 2644: 2645: (define_insn "" 2646: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2647: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2648: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2649: (const_int 0))) 2650: (clobber (match_scratch:SI 3 "=r"))] 2651: "! TARGET_POWER" 1.1.1.4 ! root 2652: "{sra|sraw}%I2. %3,%1,%h2" 1.1 root 2653: [(set_attr "type" "delayed_compare")]) 2654: 2655: (define_insn "" 2656: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2657: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2658: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2659: (const_int 0))) 2660: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2661: (ashiftrt:SI (match_dup 1) (match_dup 2))) 2662: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2663: "TARGET_POWER" 1.1 root 2664: "@ 2665: srea. %0,%1,%2 1.1.1.2 root 2666: {srai.|srawi.} %0,%1,%h2" 2667: [(set_attr "type" "delayed_compare")]) 2668: 2669: (define_insn "" 2670: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2671: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2672: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2673: (const_int 0))) 2674: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2675: (ashiftrt:SI (match_dup 1) (match_dup 2)))] 2676: "! TARGET_POWER" 1.1.1.4 ! root 2677: "{sra|sraw}%I2. %0,%1,%h2" 1.1 root 2678: [(set_attr "type" "delayed_compare")]) 2679: 2680: ;; Floating-point insns, excluding normal data motion. 2681: ;; 1.1.1.2 root 2682: ;; PowerPC has a full set of single-precision floating point instructions. 2683: ;; 2684: ;; For the POWER architecture, we pretend that we have both SFmode and 2685: ;; DFmode insns, while, in fact, all fp insns are actually done in double. 2686: ;; The only conversions we will do will be when storing to memory. In that 2687: ;; case, we will use the "frsp" instruction before storing. 1.1 root 2688: ;; 2689: ;; Note that when we store into a single-precision memory location, we need to 2690: ;; use the frsp insn first. If the register being stored isn't dead, we 2691: ;; need a scratch register for the frsp. But this is difficult when the store 2692: ;; is done by reload. It is not incorrect to do the frsp on the register in 2693: ;; this case, we just lose precision that we would have otherwise gotten but 2694: ;; is not guaranteed. Perhaps this should be tightened up at some point. 2695: 2696: (define_insn "extendsfdf2" 2697: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2698: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2699: "TARGET_HARD_FLOAT" 1.1 root 2700: "* 2701: { 2702: if (REGNO (operands[0]) == REGNO (operands[1])) 2703: return \"\"; 2704: else 2705: return \"fmr %0,%1\"; 2706: }" 2707: [(set_attr "type" "fp")]) 2708: 2709: (define_insn "truncdfsf2" 2710: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2711: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2712: "TARGET_HARD_FLOAT" ! 2713: "frsp %0,%1" ! 2714: [(set_attr "type" "fp")]) ! 2715: ! 2716: (define_insn "aux_truncdfsf2" ! 2717: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2718: (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] ! 2719: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2720: "frsp %0,%1" 1.1 root 2721: [(set_attr "type" "fp")]) 2722: 2723: (define_insn "negsf2" 2724: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2725: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2726: "TARGET_HARD_FLOAT" 1.1 root 2727: "fneg %0,%1" 2728: [(set_attr "type" "fp")]) 2729: 2730: (define_insn "abssf2" 2731: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2732: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2733: "TARGET_HARD_FLOAT" 1.1 root 2734: "fabs %0,%1" 2735: [(set_attr "type" "fp")]) 2736: 2737: (define_insn "" 2738: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2739: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 2740: "TARGET_HARD_FLOAT" 1.1 root 2741: "fnabs %0,%1" 2742: [(set_attr "type" "fp")]) 2743: 1.1.1.2 root 2744: (define_expand "addsf3" 2745: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2746: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2747: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 ! root 2748: "TARGET_HARD_FLOAT" 1.1.1.2 root 2749: "") 2750: 2751: (define_insn "" 2752: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2753: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2754: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2755: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2756: "fadds %0,%1,%2" 2757: [(set_attr "type" "fp")]) 2758: 2759: (define_insn "" 1.1 root 2760: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2761: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2762: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2763: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2764: "{fa|fadd} %0,%1,%2" 2765: [(set_attr "type" "fp")]) 2766: 2767: (define_expand "subsf3" 2768: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2769: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2770: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 ! root 2771: "TARGET_HARD_FLOAT" 1.1.1.2 root 2772: "") 2773: 2774: (define_insn "" 2775: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2776: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2777: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2778: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2779: "fsubs %0,%1,%2" 1.1 root 2780: [(set_attr "type" "fp")]) 2781: 1.1.1.2 root 2782: (define_insn "" 1.1 root 2783: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2784: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2785: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2786: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2787: "{fs|fsub} %0,%1,%2" 2788: [(set_attr "type" "fp")]) 2789: 2790: (define_expand "mulsf3" 2791: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2792: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 2793: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 ! root 2794: "TARGET_HARD_FLOAT" 1.1.1.2 root 2795: "") 2796: 2797: (define_insn "" 2798: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2799: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2800: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2801: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2802: "fmuls %0,%1,%2" 1.1 root 2803: [(set_attr "type" "fp")]) 2804: 1.1.1.2 root 2805: (define_insn "" 1.1 root 2806: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2807: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2808: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2809: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2810: "{fm|fmul} %0,%1,%2" 1.1 root 2811: [(set_attr "type" "fp")]) 2812: 1.1.1.2 root 2813: (define_expand "divsf3" 2814: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2815: (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 2816: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 ! root 2817: "TARGET_HARD_FLOAT" 1.1.1.2 root 2818: "") 2819: 2820: (define_insn "" 1.1 root 2821: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2822: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2823: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2824: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2825: "fdivs %0,%1,%2" 2826: [(set_attr "type" "sdiv")]) 2827: 2828: (define_insn "" 2829: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2830: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2831: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2832: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2833: "{fd|fdiv} %0,%1,%2" 2834: [(set_attr "type" "sdiv")]) 2835: 2836: (define_insn "" 2837: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2838: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2839: (match_operand:SF 2 "gpc_reg_operand" "f")) 2840: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2841: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2842: "fmadds %0,%1,%2,%3" 1.1 root 2843: [(set_attr "type" "fp")]) 2844: 2845: (define_insn "" 2846: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2847: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2848: (match_operand:SF 2 "gpc_reg_operand" "f")) 2849: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2850: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2851: "{fma|fmadd} %0,%1,%2,%3" 1.1 root 2852: [(set_attr "type" "fp")]) 2853: 2854: (define_insn "" 2855: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2856: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2857: (match_operand:SF 2 "gpc_reg_operand" "f")) 2858: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2859: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2860: "fmsubs %0,%1,%2,%3" 2861: [(set_attr "type" "fp")]) 2862: 2863: (define_insn "" 2864: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2865: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2866: (match_operand:SF 2 "gpc_reg_operand" "f")) 2867: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2868: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2869: "{fms|fmsub} %0,%1,%2,%3" 1.1 root 2870: [(set_attr "type" "fp")]) 2871: 2872: (define_insn "" 2873: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2874: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2875: (match_operand:SF 2 "gpc_reg_operand" "f")) 2876: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 2877: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2878: "fnmadds %0,%1,%2,%3" 2879: [(set_attr "type" "fp")]) 2880: 2881: (define_insn "" 2882: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2883: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2884: (match_operand:SF 2 "gpc_reg_operand" "f")) 2885: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 2886: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2887: "{fnma|fnmadd} %0,%1,%2,%3" 1.1 root 2888: [(set_attr "type" "fp")]) 2889: 2890: (define_insn "" 2891: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2892: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2893: (match_operand:SF 2 "gpc_reg_operand" "f")) 2894: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 2895: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2896: "fnmsubs %0,%1,%2,%3" 2897: [(set_attr "type" "fp")]) 2898: 2899: (define_insn "" 2900: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2901: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2902: (match_operand:SF 2 "gpc_reg_operand" "f")) 2903: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 2904: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2905: "{fnms|fnmsub} %0,%1,%2,%3" 1.1 root 2906: [(set_attr "type" "fp")]) 2907: 1.1.1.2 root 2908: (define_expand "sqrtsf2" 2909: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2910: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.4 ! root 2911: "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 1.1.1.2 root 2912: "") 2913: 2914: (define_insn "" 2915: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2916: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2917: "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" 1.1.1.2 root 2918: "fsqrts %0,%1" 2919: [(set_attr "type" "ssqrt")]) 2920: 2921: (define_insn "" 2922: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2923: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 2924: "TARGET_POWER2 && TARGET_HARD_FLOAT" 1.1.1.2 root 2925: "fsqrt %0,%1" 2926: [(set_attr "type" "dsqrt")]) 2927: 1.1.1.4 ! root 2928: ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ! 2929: ;; fsel instruction and some auxiliary computations. Then we just have a ! 2930: ;; single DEFINE_INSN for fsel and the define_splits to make them if made by 1.1.1.3 root 2931: ;; combine. 2932: (define_expand "maxsf3" 2933: [(set (match_dup 3) 2934: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2935: (match_operand:SF 2 "gpc_reg_operand" ""))) 2936: (set (match_operand:SF 0 "gpc_reg_operand" "") 2937: (if_then_else:SF (ge (match_dup 3) 2938: (const_int 0)) 2939: (match_dup 1) 2940: (match_dup 2)))] 1.1.1.4 ! root 2941: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2942: " 2943: { operands[3] = gen_reg_rtx (SFmode); }") 2944: 2945: (define_split 2946: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2947: (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") 2948: (match_operand:SF 2 "gpc_reg_operand" ""))) 2949: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] 1.1.1.4 ! root 2950: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2951: [(set (match_dup 3) 2952: (minus:SF (match_dup 1) (match_dup 2))) 1.1.1.4 ! root 2953: (set (match_dup 0) 1.1.1.3 root 2954: (if_then_else:SF (ge (match_dup 3) 2955: (const_int 0)) 2956: (match_dup 1) 2957: (match_dup 2)))] 2958: "") 2959: 2960: (define_expand "minsf3" 2961: [(set (match_dup 3) 2962: (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") 2963: (match_operand:SF 1 "gpc_reg_operand" ""))) 2964: (set (match_operand:SF 0 "gpc_reg_operand" "") 2965: (if_then_else:SF (ge (match_dup 3) 2966: (const_int 0)) 2967: (match_dup 1) 2968: (match_dup 2)))] 1.1.1.4 ! root 2969: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2970: " 2971: { operands[3] = gen_reg_rtx (SFmode); }") 2972: 2973: (define_split 2974: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2975: (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") 2976: (match_operand:SF 2 "gpc_reg_operand" ""))) 2977: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] 1.1.1.4 ! root 2978: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2979: [(set (match_dup 3) 2980: (minus:SF (match_dup 2) (match_dup 1))) 1.1.1.4 ! root 2981: (set (match_dup 0) 1.1.1.3 root 2982: (if_then_else:SF (ge (match_dup 3) 2983: (const_int 0)) 2984: (match_dup 1) 2985: (match_dup 2)))] 2986: "") 2987: 1.1.1.4 ! root 2988: (define_expand "movsfcc" ! 2989: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2990: (if_then_else:SF (match_operand 1 "comparison_operator" "") ! 2991: (match_operand:SF 2 "gpc_reg_operand" "f") ! 2992: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2993: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" ! 2994: " ! 2995: { ! 2996: rtx temp, op0, op1; ! 2997: enum rtx_code code = GET_CODE (operands[1]); ! 2998: if (! rs6000_compare_fp_p) ! 2999: FAIL; ! 3000: switch (code) ! 3001: { ! 3002: case GE: case EQ: case NE: ! 3003: op0 = rs6000_compare_op0; ! 3004: op1 = rs6000_compare_op1; ! 3005: break; ! 3006: case GT: ! 3007: op0 = rs6000_compare_op1; ! 3008: op1 = rs6000_compare_op0; ! 3009: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; ! 3010: break; ! 3011: case LE: ! 3012: op0 = rs6000_compare_op1; ! 3013: op1 = rs6000_compare_op0; ! 3014: break; ! 3015: case LT: ! 3016: op0 = rs6000_compare_op0; ! 3017: op1 = rs6000_compare_op1; ! 3018: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; ! 3019: break; ! 3020: default: ! 3021: FAIL; ! 3022: } ! 3023: if (GET_MODE (rs6000_compare_op0) == DFmode) ! 3024: { ! 3025: temp = gen_reg_rtx (DFmode); ! 3026: emit_insn (gen_subdf3 (temp, op0, op1)); ! 3027: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); ! 3028: if (code == EQ) ! 3029: { ! 3030: emit_insn (gen_negdf2 (temp, temp)); ! 3031: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); ! 3032: } ! 3033: if (code == NE) ! 3034: { ! 3035: emit_insn (gen_negdf2 (temp, temp)); ! 3036: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); ! 3037: } ! 3038: } ! 3039: else ! 3040: { ! 3041: temp = gen_reg_rtx (SFmode); ! 3042: emit_insn (gen_subsf3 (temp, op0, op1)); ! 3043: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); ! 3044: if (code == EQ) ! 3045: { ! 3046: emit_insn (gen_negsf2 (temp, temp)); ! 3047: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); ! 3048: } ! 3049: if (code == NE) ! 3050: { ! 3051: emit_insn (gen_negsf2 (temp, temp)); ! 3052: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); ! 3053: } ! 3054: } ! 3055: DONE; ! 3056: }") ! 3057: ! 3058: (define_insn "fselsfsf4" 1.1.1.3 root 3059: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 3060: (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 3061: (const_int 0)) 3062: (match_operand:SF 2 "gpc_reg_operand" "f") 3063: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3064: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" ! 3065: "fsel %0,%1,%2,%3" ! 3066: [(set_attr "type" "fp")]) ! 3067: ! 3068: (define_insn "fseldfsf4" ! 3069: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 3070: (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") ! 3071: (const_int 0)) ! 3072: (match_operand:SF 2 "gpc_reg_operand" "f") ! 3073: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 3074: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3075: "fsel %0,%1,%2,%3" 3076: [(set_attr "type" "fp")]) 3077: 1.1 root 3078: (define_insn "negdf2" 3079: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3080: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3081: "TARGET_HARD_FLOAT" 1.1 root 3082: "fneg %0,%1" 3083: [(set_attr "type" "fp")]) 3084: 3085: (define_insn "absdf2" 3086: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3087: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3088: "TARGET_HARD_FLOAT" 1.1 root 3089: "fabs %0,%1" 3090: [(set_attr "type" "fp")]) 3091: 3092: (define_insn "" 3093: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3094: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 3095: "TARGET_HARD_FLOAT" 1.1 root 3096: "fnabs %0,%1" 3097: [(set_attr "type" "fp")]) 3098: 3099: (define_insn "adddf3" 3100: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3101: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3102: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3103: "TARGET_HARD_FLOAT" 1.1.1.2 root 3104: "{fa|fadd} %0,%1,%2" 1.1 root 3105: [(set_attr "type" "fp")]) 3106: 3107: (define_insn "subdf3" 3108: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3109: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 3110: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3111: "TARGET_HARD_FLOAT" 1.1.1.2 root 3112: "{fs|fsub} %0,%1,%2" 1.1 root 3113: [(set_attr "type" "fp")]) 3114: 3115: (define_insn "muldf3" 3116: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3117: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3118: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3119: "TARGET_HARD_FLOAT" 1.1.1.2 root 3120: "{fm|fmul} %0,%1,%2" 3121: [(set_attr "type" "dmul")]) 1.1 root 3122: 3123: (define_insn "divdf3" 3124: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3125: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 3126: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3127: "TARGET_HARD_FLOAT" 1.1.1.2 root 3128: "{fd|fdiv} %0,%1,%2" 3129: [(set_attr "type" "ddiv")]) 1.1 root 3130: 3131: (define_insn "" 3132: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3133: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3134: (match_operand:DF 2 "gpc_reg_operand" "f")) 3135: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3136: "TARGET_HARD_FLOAT" 1.1.1.2 root 3137: "{fma|fmadd} %0,%1,%2,%3" 3138: [(set_attr "type" "dmul")]) 1.1 root 3139: 3140: (define_insn "" 3141: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3142: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3143: (match_operand:DF 2 "gpc_reg_operand" "f")) 3144: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3145: "TARGET_HARD_FLOAT" 1.1.1.2 root 3146: "{fms|fmsub} %0,%1,%2,%3" 3147: [(set_attr "type" "dmul")]) 1.1 root 3148: 3149: (define_insn "" 3150: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3151: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3152: (match_operand:DF 2 "gpc_reg_operand" "f")) 3153: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 3154: "TARGET_HARD_FLOAT" 1.1.1.2 root 3155: "{fnma|fnmadd} %0,%1,%2,%3" 3156: [(set_attr "type" "dmul")]) 1.1 root 3157: 3158: (define_insn "" 3159: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3160: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3161: (match_operand:DF 2 "gpc_reg_operand" "f")) 3162: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 3163: "TARGET_HARD_FLOAT" 1.1.1.2 root 3164: "{fnms|fnmsub} %0,%1,%2,%3" 3165: [(set_attr "type" "dmul")]) 3166: 3167: (define_insn "sqrtdf2" 3168: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3169: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3170: "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 1.1.1.2 root 3171: "fsqrt %0,%1" 3172: [(set_attr "type" "dsqrt")]) 1.1.1.3 root 3173: 1.1.1.4 ! root 3174: ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ! 3175: ;; fsel instruction and some auxiliary computations. Then we just have a ! 3176: ;; single DEFINE_INSN for fsel and the define_splits to make them if made by 1.1.1.3 root 3177: ;; combine. 3178: 3179: (define_expand "maxdf3" 3180: [(set (match_dup 3) 3181: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") 3182: (match_operand:DF 2 "gpc_reg_operand" ""))) 3183: (set (match_operand:DF 0 "gpc_reg_operand" "") 3184: (if_then_else:DF (ge (match_dup 3) 3185: (const_int 0)) 3186: (match_dup 1) 3187: (match_dup 2)))] 1.1.1.4 ! root 3188: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3189: " 3190: { operands[3] = gen_reg_rtx (DFmode); }") 3191: 3192: (define_split 3193: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3194: (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") 3195: (match_operand:DF 2 "gpc_reg_operand" ""))) 3196: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] 1.1.1.4 ! root 3197: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3198: [(set (match_dup 3) 3199: (minus:DF (match_dup 1) (match_dup 2))) 1.1.1.4 ! root 3200: (set (match_dup 0) 1.1.1.3 root 3201: (if_then_else:DF (ge (match_dup 3) 3202: (const_int 0)) 3203: (match_dup 1) 3204: (match_dup 2)))] 3205: "") 3206: 3207: (define_expand "mindf3" 3208: [(set (match_dup 3) 3209: (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") 3210: (match_operand:DF 1 "gpc_reg_operand" ""))) 3211: (set (match_operand:DF 0 "gpc_reg_operand" "") 3212: (if_then_else:DF (ge (match_dup 3) 3213: (const_int 0)) 3214: (match_dup 1) 3215: (match_dup 2)))] 1.1.1.4 ! root 3216: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3217: " 3218: { operands[3] = gen_reg_rtx (DFmode); }") 3219: 3220: (define_split 3221: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3222: (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") 3223: (match_operand:DF 2 "gpc_reg_operand" ""))) 3224: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] 1.1.1.4 ! root 3225: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3226: [(set (match_dup 3) 3227: (minus:DF (match_dup 2) (match_dup 1))) 1.1.1.4 ! root 3228: (set (match_dup 0) 1.1.1.3 root 3229: (if_then_else:DF (ge (match_dup 3) 3230: (const_int 0)) 3231: (match_dup 1) 3232: (match_dup 2)))] 3233: "") 3234: 1.1.1.4 ! root 3235: (define_expand "movdfcc" ! 3236: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 3237: (if_then_else:DF (match_operand 1 "comparison_operator" "") ! 3238: (match_operand:DF 2 "gpc_reg_operand" "f") ! 3239: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 3240: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" ! 3241: " ! 3242: { ! 3243: rtx temp, op0, op1; ! 3244: enum rtx_code code = GET_CODE (operands[1]); ! 3245: if (! rs6000_compare_fp_p) ! 3246: FAIL; ! 3247: switch (code) ! 3248: { ! 3249: case GE: case EQ: case NE: ! 3250: op0 = rs6000_compare_op0; ! 3251: op1 = rs6000_compare_op1; ! 3252: break; ! 3253: case GT: ! 3254: op0 = rs6000_compare_op1; ! 3255: op1 = rs6000_compare_op0; ! 3256: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; ! 3257: break; ! 3258: case LE: ! 3259: op0 = rs6000_compare_op1; ! 3260: op1 = rs6000_compare_op0; ! 3261: break; ! 3262: case LT: ! 3263: op0 = rs6000_compare_op0; ! 3264: op1 = rs6000_compare_op1; ! 3265: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; ! 3266: break; ! 3267: default: ! 3268: FAIL; ! 3269: } ! 3270: if (GET_MODE (rs6000_compare_op0) == DFmode) ! 3271: { ! 3272: temp = gen_reg_rtx (DFmode); ! 3273: emit_insn (gen_subdf3 (temp, op0, op1)); ! 3274: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); ! 3275: if (code == EQ) ! 3276: { ! 3277: emit_insn (gen_negdf2 (temp, temp)); ! 3278: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); ! 3279: } ! 3280: if (code == NE) ! 3281: { ! 3282: emit_insn (gen_negdf2 (temp, temp)); ! 3283: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); ! 3284: } ! 3285: } ! 3286: else ! 3287: { ! 3288: temp = gen_reg_rtx (SFmode); ! 3289: emit_insn (gen_subsf3 (temp, op0, op1)); ! 3290: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); ! 3291: if (code == EQ) ! 3292: { ! 3293: emit_insn (gen_negsf2 (temp, temp)); ! 3294: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); ! 3295: } ! 3296: if (code == NE) ! 3297: { ! 3298: emit_insn (gen_negsf2 (temp, temp)); ! 3299: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); ! 3300: } ! 3301: } ! 3302: DONE; ! 3303: }") ! 3304: ! 3305: (define_insn "fseldfdf4" 1.1.1.3 root 3306: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3307: (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 3308: (const_int 0)) 3309: (match_operand:DF 2 "gpc_reg_operand" "f") 3310: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3311: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" ! 3312: "fsel %0,%1,%2,%3" ! 3313: [(set_attr "type" "fp")]) ! 3314: ! 3315: (define_insn "fselsfdf4" ! 3316: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 3317: (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") ! 3318: (const_int 0)) ! 3319: (match_operand:DF 2 "gpc_reg_operand" "f") ! 3320: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.3 root 3321: "TARGET_PPC_GFXOPT" 3322: "fsel %0,%1,%2,%3" 3323: [(set_attr "type" "fp")]) 1.1 root 3324: 3325: ;; Conversions to and from floating-point. 3326: (define_expand "floatsidf2" 1.1.1.4 ! root 3327: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 3328: (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))] ! 3329: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3330: " 3331: { 1.1.1.4 ! root 3332: if (operands[0]) ! 3333: { /* prevent unused warning messages */ ! 3334: rtx high = force_reg (SImode, GEN_INT (0x43300000)); ! 3335: rtx low = gen_reg_rtx (SImode); ! 3336: rtx df = gen_reg_rtx (DFmode); ! 3337: rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); ! 3338: ! 3339: emit_insn (gen_xorsi3 (low, operands[1], GEN_INT (0x80000000))); ! 3340: emit_insn (gen_move_to_float (df, low, high)); ! 3341: emit_insn (gen_subdf3 (operands[0], df, adjust)); ! 3342: DONE; ! 3343: } 1.1 root 3344: }") 3345: 3346: (define_expand "floatunssidf2" 1.1.1.4 ! root 3347: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 3348: (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))] ! 3349: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3350: " 3351: { 1.1.1.4 ! root 3352: if (operands[0]) ! 3353: { /* prevent unused warning messages */ ! 3354: rtx high = force_reg (SImode, GEN_INT (0x43300000)); ! 3355: rtx df = gen_reg_rtx (DFmode); ! 3356: rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); 1.1 root 3357: 1.1.1.4 ! root 3358: emit_insn (gen_move_to_float (df, operands[1], high)); ! 3359: emit_insn (gen_subdf3 (operands[0], df, adjust)); ! 3360: DONE; ! 3361: } 1.1 root 3362: }") 3363: 1.1.1.4 ! root 3364: (define_expand "move_to_float" ! 3365: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 3366: (unspec [(match_operand:SI 1 "gpc_reg_operand" "") ! 3367: (match_operand:SI 2 "gpc_reg_operand" "") ! 3368: (match_dup 3)] 2))] ! 3369: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3370: " 1.1.1.4 ! root 3371: { ! 3372: operands[3] = XEXP (rs6000_stack_temp (DFmode, 8, 1), 0); 1.1 root 3373: }") 3374: 3375: (define_split 1.1.1.4 ! root 3376: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 3377: (unspec [(match_operand:SI 1 "gpc_reg_operand" "") ! 3378: (match_operand:SI 2 "gpc_reg_operand" "") ! 3379: (match_operand:SI 3 "offsettable_addr_operand" "")] 2))] ! 3380: "reload_completed" ! 3381: [(set (match_dup 4) (match_dup 1)) ! 3382: (set (match_dup 5) (match_dup 2)) ! 3383: (set (match_dup 0) (mem:DF (match_dup 3)))] ! 3384: " ! 3385: { ! 3386: rtx word1 = gen_rtx (MEM, SImode, operands[3]); ! 3387: rtx word2 = gen_rtx (MEM, SImode, plus_constant (operands[3], 4)); ! 3388: ! 3389: MEM_IN_STRUCT_P (word1) = 1; ! 3390: MEM_IN_STRUCT_P (word2) = 1; 1.1 root 3391: 1.1.1.4 ! root 3392: if (WORDS_BIG_ENDIAN) 1.1 root 3393: { 1.1.1.4 ! root 3394: operands[4] = word2; ! 3395: operands[5] = word1; 1.1 root 3396: } 1.1.1.4 ! root 3397: else 1.1 root 3398: { 1.1.1.4 ! root 3399: operands[4] = word1; ! 3400: operands[5] = word2; 1.1 root 3401: } 3402: }") 3403: 3404: (define_insn "" 1.1.1.4 ! root 3405: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 3406: (unspec [(match_operand:SI 1 "gpc_reg_operand" "r") ! 3407: (match_operand:SI 2 "gpc_reg_operand" "r") ! 3408: (match_operand:SI 3 "offsettable_addr_operand" "p")] 2))] ! 3409: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.2 root 3410: "#" 1.1.1.4 ! root 3411: [(set_attr "length" "12")]) 1.1 root 3412: 3413: (define_expand "fix_truncdfsi2" 3414: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3415: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 ! root 3416: "TARGET_HARD_FLOAT" 1.1 root 3417: " 3418: { 1.1.1.3 root 3419: if (TARGET_POWER2 || TARGET_POWERPC) 3420: { 1.1.1.4 ! root 3421: int endian = (WORDS_BIG_ENDIAN == 0); ! 3422: rtx stack_slot = rs6000_stack_temp (DImode, 8, 1); ! 3423: rtx temp = gen_reg_rtx (DImode); 1.1.1.3 root 3424: 3425: emit_insn (gen_fpcvtsi (temp, operands[1])); 3426: emit_move_insn (stack_slot, temp); 3427: emit_move_insn (operands[0], 1.1.1.4 ! root 3428: operand_subword (stack_slot, 1 - endian, 0, DImode)); 1.1.1.3 root 3429: DONE; 3430: } 3431: else 3432: { 3433: emit_insn (gen_trunc_call (operands[0], operands[1], 3434: gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC))); 3435: DONE; 3436: } 1.1 root 3437: }") 3438: 1.1.1.3 root 3439: (define_insn "fpcvtsi" 3440: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 3441: (sign_extend:DI 3442: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 ! root 3443: "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 1.1.1.3 root 3444: "{fcirz|fctiwz} %0,%1" 3445: [(set_attr "type" "fp")]) 3446: 1.1 root 3447: (define_expand "fixuns_truncdfsi2" 3448: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3449: (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 ! root 3450: "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1 root 3451: " 3452: { 3453: emit_insn (gen_trunc_call (operands[0], operands[1], 1.1.1.3 root 3454: gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC))); 1.1 root 3455: DONE; 3456: }") 3457: 3458: (define_expand "trunc_call" 3459: [(parallel [(set (match_operand:SI 0 "" "") 3460: (fix:SI (match_operand:DF 1 "" ""))) 3461: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 ! root 3462: "TARGET_HARD_FLOAT" 1.1 root 3463: " 3464: { 3465: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); 3466: rtx first = XVECEXP (insns, 0, 0); 3467: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); 3468: 3469: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, 3470: REG_NOTES (first)); 3471: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); 3472: 3473: emit_insn (insns); 3474: DONE; 3475: }") 3476: 3477: (define_expand "trunc_call_rtl" 3478: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) 3479: (use (reg:DF 33)) 3480: (parallel [(set (reg:SI 3) 3481: (call (mem:SI (match_operand 2 "" "")) (const_int 0))) 1.1.1.4 ! root 3482: (use (const_int 0)) 1.1 root 3483: (clobber (scratch:SI))]) 3484: (set (match_operand:SI 0 "gpc_reg_operand" "") 3485: (reg:SI 3))] 1.1.1.4 ! root 3486: "TARGET_HARD_FLOAT" 1.1 root 3487: " 1.1.1.4 ! root 3488: { 1.1 root 3489: rs6000_trunc_used = 1; 3490: }") 1.1.1.3 root 3491: 3492: (define_insn "floatdidf2" 3493: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3494: (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3495: "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.3 root 3496: "fcfid %0,%1" 3497: [(set_attr "type" "fp")]) 3498: 3499: (define_insn "fix_truncdfdi2" 3500: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 3501: (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 3502: "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.3 root 3503: "fctidz %0,%1" 3504: [(set_attr "type" "fp")]) 1.1 root 3505: 3506: ;; Define the DImode operations that can be done in a small number 1.1.1.4 ! root 3507: ;; of instructions. The & constraints are to prevent the register ! 3508: ;; allocator from allocating registers that overlap with the inputs ! 3509: ;; (for example, having an input in 7,8 and an output in 6,7). We ! 3510: ;; also allow for the the output being the same as one of the inputs. ! 3511: 1.1.1.2 root 3512: (define_expand "adddi3" 3513: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3514: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 3515: (match_operand:DI 2 "reg_or_short_operand" "")))] 3516: "" 3517: " 3518: { 1.1.1.3 root 3519: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3520: && short_cint_operand (operands[2], DImode)) 3521: FAIL; 3522: }") 3523: 3524: (define_insn "" 1.1.1.4 ! root 3525: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") ! 3526: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") ! 3527: (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 1.1.1.3 root 3528: "TARGET_POWER && ! TARGET_POWERPC64" 1.1 root 3529: "@ 1.1.1.2 root 3530: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 1.1.1.4 ! root 3531: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1 ! 3532: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 1.1.1.2 root 3533: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" 3534: [(set_attr "length" "8")]) 1.1 root 3535: 1.1.1.2 root 3536: (define_insn "" 1.1.1.4 ! root 3537: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") ! 3538: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,0") ! 3539: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 1.1.1.3 root 3540: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.4 ! root 3541: "* ! 3542: { ! 3543: return (WORDS_BIG_ENDIAN) ! 3544: ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" ! 3545: : \"addc %0,%1,%2\;adde %L0,%L1,%L2\"; ! 3546: }" 1.1.1.2 root 3547: [(set_attr "length" "8")]) 3548: 3549: (define_expand "subdi3" 1.1.1.4 ! root 3550: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 3551: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") ! 3552: (match_operand:DI 2 "gpc_reg_operand" "")))] 1.1 root 3553: "" 1.1.1.2 root 3554: " 3555: { 1.1.1.3 root 3556: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3557: && short_cint_operand (operands[1], DImode)) 3558: FAIL; 3559: }") 3560: 3561: (define_insn "" 1.1.1.4 ! root 3562: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") ! 3563: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") ! 3564: (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 1.1.1.3 root 3565: "TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.2 root 3566: "@ 3567: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 1.1.1.4 ! root 3568: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2 ! 3569: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 ! 3570: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 1.1.1.2 root 3571: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" 3572: [(set_attr "length" "8")]) 3573: 3574: (define_insn "" 1.1.1.4 ! root 3575: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r") ! 3576: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,0,r") ! 3577: (match_operand:DI 2 "gpc_reg_operand" "r,r,0")))] 1.1.1.3 root 3578: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.4 ! root 3579: "* ! 3580: { ! 3581: return (WORDS_BIG_ENDIAN) ! 3582: ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" ! 3583: : \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"; ! 3584: }" 1.1.1.2 root 3585: [(set_attr "length" "8")]) 3586: 3587: (define_expand "negdi2" 3588: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3589: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 3590: "" 3591: "") 1.1 root 3592: 1.1.1.2 root 3593: (define_insn "" 1.1.1.4 ! root 3594: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") ! 3595: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 1.1.1.3 root 3596: "! TARGET_POWERPC64" 1.1.1.4 ! root 3597: "* ! 3598: { ! 3599: return (WORDS_BIG_ENDIAN) ! 3600: ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" ! 3601: : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; ! 3602: }" 1.1.1.2 root 3603: [(set_attr "length" "8")]) 1.1 root 3604: 1.1.1.3 root 3605: (define_expand "mulsidi3" 3606: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3607: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 3608: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 3609: "" 3610: " 3611: { 3612: if (! TARGET_POWER && ! TARGET_POWERPC) 3613: { 1.1.1.4 ! root 3614: int endian = (WORDS_BIG_ENDIAN == 0); 1.1.1.3 root 3615: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 3616: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 3617: emit_insn (gen_mull_call ()); 1.1.1.4 ! root 3618: emit_move_insn (operand_subword (operands[0], endian, 0, DImode), 1.1.1.3 root 3619: gen_rtx (REG, SImode, 3)); 1.1.1.4 ! root 3620: emit_move_insn (operand_subword (operands[0], 1 - endian, 0, DImode), 1.1.1.3 root 3621: gen_rtx (REG, SImode, 4)); 3622: DONE; 3623: } 3624: else if (TARGET_POWER) 3625: { 3626: emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); 3627: DONE; 3628: } 3629: }") 3630: 3631: (define_insn "mulsidi3_mq" 1.1 root 3632: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 3633: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 3634: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 3635: (clobber (match_scratch:SI 3 "=q"))] 1.1.1.2 root 3636: "TARGET_POWER" 3637: "mul %0,%1,%2\;mfmq %L0" 1.1.1.3 root 3638: [(set_attr "type" "imul") 3639: (set_attr "length" "8")]) 3640: 3641: (define_insn "" 3642: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 3643: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 3644: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 3645: "TARGET_POWERPC && ! TARGET_POWERPC64" 1.1.1.4 ! root 3646: "* ! 3647: { ! 3648: return (WORDS_BIG_ENDIAN) ! 3649: ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" ! 3650: : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; ! 3651: }" 1.1.1.3 root 3652: [(set_attr "type" "imul") 3653: (set_attr "length" "8")]) 3654: 3655: (define_expand "smulsi3_highpart" 3656: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3657: (truncate:SI 3658: (lshiftrt:DI (mult:DI (sign_extend:DI 3659: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3660: (sign_extend:DI 3661: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3662: (const_int 32))))] 3663: "" 3664: " 3665: { 3666: if (! TARGET_POWER && ! TARGET_POWERPC) 3667: { 3668: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 3669: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 3670: emit_insn (gen_mulh_call ()); 3671: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 3672: DONE; 3673: } 3674: else if (TARGET_POWER) 3675: { 3676: emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); 3677: DONE; 3678: } 3679: }") 3680: 3681: (define_insn "smulsi3_highpart_mq" 3682: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3683: (truncate:SI 3684: (lshiftrt:DI (mult:DI (sign_extend:DI 3685: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3686: (sign_extend:DI 3687: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3688: (const_int 32)))) 3689: (clobber (match_scratch:SI 3 "=q"))] 3690: "TARGET_POWER" 3691: "mul %0,%1,%2" 3692: [(set_attr "type" "imul")]) 3693: 3694: (define_insn "" 3695: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3696: (truncate:SI 3697: (lshiftrt:DI (mult:DI (sign_extend:DI 3698: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3699: (sign_extend:DI 3700: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3701: (const_int 32))))] 3702: "TARGET_POWERPC" 3703: "mulhw %0,%1,%2" 3704: [(set_attr "type" "imul")]) 3705: 3706: (define_insn "umulsi3_highpart" 3707: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3708: (truncate:SI 3709: (lshiftrt:DI (mult:DI (zero_extend:DI 3710: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3711: (zero_extend:DI 3712: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3713: (const_int 32))))] 3714: "TARGET_POWERPC" 3715: "mulhwu %0,%1,%2" 3716: [(set_attr "type" "imul")]) 1.1 root 3717: 3718: ;; If operands 0 and 2 are in the same register, we have a problem. But 3719: ;; operands 0 and 1 (the usual case) can be in the same register. That's 3720: ;; why we have the strange constraints below. 3721: (define_insn "ashldi3" 3722: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 3723: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3724: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3725: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3726: "TARGET_POWER" 1.1 root 3727: "@ 1.1.1.2 root 3728: {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 1.1 root 3729: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 3730: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 1.1.1.2 root 3731: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 3732: [(set_attr "length" "8")]) 1.1 root 3733: 3734: (define_insn "lshrdi3" 3735: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") 3736: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3737: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3738: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3739: "TARGET_POWER" 1.1 root 3740: "@ 1.1.1.2 root 3741: {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2 1.1 root 3742: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 3743: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 1.1.1.2 root 3744: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 3745: [(set_attr "length" "8")]) 1.1 root 3746: 3747: ;; Shift by a variable amount is too complex to be worth open-coding. We 3748: ;; just handle shifts by constants. 3749: 3750: (define_expand "ashrdi3" 1.1.1.3 root 3751: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") 1.1 root 3752: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 3753: (match_operand:SI 2 "general_operand" ""))) 3754: (clobber (match_scratch:SI 3 ""))])] 1.1.1.2 root 3755: "TARGET_POWER" 1.1 root 3756: " 3757: { if (GET_CODE (operands[2]) != CONST_INT) 3758: FAIL; 3759: }") 3760: 3761: (define_insn "" 3762: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3763: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 3764: (match_operand:SI 2 "const_int_operand" "M,i"))) 3765: (clobber (match_scratch:SI 3 "=X,q"))] 1.1.1.2 root 3766: "TARGET_POWER" 1.1 root 3767: "@ 1.1.1.2 root 3768: {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 3769: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 3770: [(set_attr "length" "8")]) 1.1 root 3771: 1.1.1.3 root 3772: ;; PowerPC64 DImode operations. 3773: 3774: (define_insn "ffsdi2" 1.1.1.4 ! root 3775: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") ! 3776: (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 1.1.1.3 root 3777: "TARGET_POWERPC64" 3778: "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" 3779: [(set_attr "length" "16")]) 3780: 3781: (define_insn "muldi3" 3782: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3783: (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 3784: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3785: "TARGET_POWERPC64" 3786: "mulld %0,%1,%2" 3787: [(set_attr "type" "imul")]) 3788: 3789: (define_insn "smuldi3_highpart" 3790: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3791: (truncate:DI 3792: (lshiftrt:TI (mult:TI (sign_extend:TI 3793: (match_operand:DI 1 "gpc_reg_operand" "%r")) 3794: (sign_extend:TI 3795: (match_operand:DI 2 "gpc_reg_operand" "r"))) 3796: (const_int 64))))] 3797: "TARGET_POWERPC64" 3798: "mulhd %0,%1,%2" 3799: [(set_attr "type" "imul")]) 3800: 3801: (define_insn "umuldi3_highpart" 3802: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3803: (truncate:DI 3804: (lshiftrt:TI (mult:TI (zero_extend:TI 3805: (match_operand:DI 1 "gpc_reg_operand" "%r")) 3806: (zero_extend:TI 3807: (match_operand:DI 2 "gpc_reg_operand" "r"))) 3808: (const_int 64))))] 3809: "TARGET_POWERPC64" 3810: "mulhdu %0,%1,%2" 3811: [(set_attr "type" "imul")]) 3812: 3813: (define_insn "divdi3" 3814: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3815: (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3816: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3817: "TARGET_POWERPC64" 3818: "divd %0,%1,%2" 3819: [(set_attr "type" "idiv")]) 3820: 3821: (define_insn "udivdi3" 3822: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3823: (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3824: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3825: "TARGET_POWERPC64" 3826: "divdu %0,%1,%2" 3827: [(set_attr "type" "idiv")]) 3828: 3829: (define_insn "rotldi3" 3830: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3831: (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3832: (match_operand:DI 2 "reg_or_cint_operand" "ri")))] 3833: "TARGET_POWERPC64" 3834: "rld%I2cl %0,%1,%h2,0") 3835: 3836: (define_insn "" 3837: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 3838: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3839: (match_operand:DI 2 "reg_or_cint_operand" "ri")) 3840: (const_int 0))) 3841: (clobber (match_scratch:DI 3 "=r"))] 3842: "TARGET_POWERPC64" 3843: "rld%I2cl. %3,%1,%h2,0" 3844: [(set_attr "type" "delayed_compare")]) 3845: 3846: (define_insn "" 3847: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 3848: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3849: (match_operand:DI 2 "reg_or_cint_operand" "ri")) 3850: (const_int 0))) 3851: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3852: (rotate:DI (match_dup 1) (match_dup 2)))] 3853: "TARGET_POWERPC64" 3854: "rld%I2cl. %0,%1,%h2,0" 3855: [(set_attr "type" "delayed_compare")]) 3856: 1.1 root 3857: ;; Now define ways of moving data around. 1.1.1.4 ! root 3858: ! 3859: ;; Elf specific ways of loading addresses for non-PIC code. ! 3860: ;; The output of this could be r0, but we limit it to base ! 3861: ;; registers, since almost all uses of this will need it ! 3862: ;; in a base register shortly. ! 3863: (define_insn "elf_high" ! 3864: [(set (match_operand:SI 0 "register_operand" "=b") ! 3865: (high:SI (match_operand 1 "" "")))] ! 3866: "TARGET_ELF && !TARGET_64BIT" ! 3867: "{cau|addis} %0,0,%1@ha") ! 3868: ! 3869: (define_insn "elf_low" ! 3870: [(set (match_operand:SI 0 "register_operand" "=r") ! 3871: (lo_sum:SI (match_operand:SI 1 "register_operand" "b") ! 3872: (match_operand 2 "" "")))] ! 3873: "TARGET_ELF && !TARGET_64BIT" ! 3874: "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}") ! 3875: 1.1 root 3876: ;; For SI, we special-case integers that can't be loaded in one insn. We 3877: ;; do the load 16-bits at a time. We could do this by loading from memory, 3878: ;; and this is even supposed to be faster, but it is simpler not to get 3879: ;; integers in the TOC. 3880: (define_expand "movsi" 3881: [(set (match_operand:SI 0 "general_operand" "") 3882: (match_operand:SI 1 "any_operand" ""))] 3883: "" 3884: " 3885: { 3886: if (GET_CODE (operands[0]) != REG) 3887: operands[1] = force_reg (SImode, operands[1]); 3888: 1.1.1.4 ! root 3889: /* Convert a move of a CONST_DOUBLE into a CONST_INT */ ! 3890: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 3891: operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); ! 3892: ! 3893: if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT ! 3894: && CONSTANT_P (operands[1]) ! 3895: && GET_CODE (operands[1]) != HIGH ! 3896: && GET_CODE (operands[1]) != CONST_INT) ! 3897: { ! 3898: rtx target = (reload_completed || reload_in_progress) ! 3899: ? operands[0] : gen_reg_rtx (SImode); ! 3900: ! 3901: emit_insn (gen_elf_high (target, operands[1])); ! 3902: emit_insn (gen_elf_low (operands[0], target, operands[1])); ! 3903: DONE; ! 3904: } ! 3905: ! 3906: if (CONSTANT_P (operands[1]) ! 3907: && GET_CODE (operands[1]) != CONST_INT ! 3908: && GET_CODE (operands[1]) != HIGH 1.1.1.2 root 3909: && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) 1.1 root 3910: { 1.1.1.3 root 3911: /* If we are to limit the number of things we put in the TOC and 3912: this is a symbol plus a constant we can add in one insn, 1.1.1.4 ! root 3913: just put the symbol in the TOC and add the constant. Don't do 1.1.1.3 root 3914: this if reload is in progress. */ 3915: if (GET_CODE (operands[1]) == CONST 3916: && TARGET_NO_SUM_IN_TOC && ! reload_in_progress 3917: && GET_CODE (XEXP (operands[1], 0)) == PLUS 3918: && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) 3919: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF 3920: || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) 3921: && ! side_effects_p (operands[0])) 3922: { 3923: rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); 3924: rtx other = XEXP (XEXP (operands[1], 0), 1); 3925: 3926: emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); 3927: DONE; 3928: } 3929: 1.1 root 3930: operands[1] = force_const_mem (SImode, operands[1]); 3931: if (! memory_address_p (SImode, XEXP (operands[1], 0)) 3932: && ! reload_in_progress) 3933: operands[1] = change_address (operands[1], SImode, 3934: XEXP (operands[1], 0)); 3935: } 3936: 3937: if (GET_CODE (operands[1]) == CONST_INT 3938: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3939: && (INTVAL (operands[1]) & 0xffff) != 0) 3940: { 3941: emit_move_insn (operands[0], 3942: gen_rtx (CONST_INT, VOIDmode, 3943: INTVAL (operands[1]) & 0xffff0000)); 3944: emit_insn (gen_iorsi3 (operands[0], operands[0], 3945: gen_rtx (CONST_INT, VOIDmode, 3946: INTVAL (operands[1]) & 0xffff))); 3947: DONE; 3948: } 3949: }") 3950: 3951: (define_insn "" 1.1.1.3 root 3952: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h") 3953: (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))] 3954: "gpc_reg_operand (operands[0], SImode) 3955: || gpc_reg_operand (operands[1], SImode)" 1.1 root 3956: "@ 1.1.1.3 root 3957: mr %0,%1 1.1.1.2 root 3958: {l%U1%X1|lwz%U1%X1} %0,%1 3959: {st%U0%X0|stw%U0%X0} %1,%0 1.1.1.3 root 3960: {lil|li} %0,%1 3961: {liu|lis} %0,%u1 3962: {cal|la} %0,%1(%*) 1.1 root 3963: mf%1 %0 3964: mt%0 %1 3965: mt%0 %1 3966: cror 0,0,0" 1.1.1.3 root 3967: [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 3968: 1.1 root 3969: ;; Split a load of a large constant into the appropriate two-insn 3970: ;; sequence. 3971: 3972: (define_split 3973: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3974: (match_operand:SI 1 "const_int_operand" ""))] 3975: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3976: && (INTVAL (operands[1]) & 0xffff) != 0" 3977: [(set (match_dup 0) 3978: (match_dup 2)) 3979: (set (match_dup 0) 3980: (ior:SI (match_dup 0) 3981: (match_dup 3)))] 3982: " 3983: { 3984: operands[2] = gen_rtx (CONST_INT, VOIDmode, 3985: INTVAL (operands[1]) & 0xffff0000); 3986: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); 3987: }") 3988: 3989: (define_insn "" 3990: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 3991: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 3992: (const_int 0))) 3993: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 3994: "" 1.1.1.3 root 3995: "mr. %0,%1" 1.1 root 3996: [(set_attr "type" "compare")]) 3997: 3998: (define_expand "movhi" 3999: [(set (match_operand:HI 0 "general_operand" "") 4000: (match_operand:HI 1 "any_operand" ""))] 4001: "" 4002: " 4003: { 4004: if (GET_CODE (operands[0]) != REG) 4005: operands[1] = force_reg (HImode, operands[1]); 4006: 4007: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 4008: { 4009: operands[1] = force_const_mem (HImode, operands[1]); 4010: if (! memory_address_p (HImode, XEXP (operands[1], 0)) 4011: && ! reload_in_progress) 4012: operands[1] = change_address (operands[1], HImode, 4013: XEXP (operands[1], 0)); 4014: } 4015: }") 4016: 4017: (define_insn "" 1.1.1.3 root 4018: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 4019: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 4020: "gpc_reg_operand (operands[0], HImode) 4021: || gpc_reg_operand (operands[1], HImode)" 1.1 root 4022: "@ 1.1.1.3 root 4023: mr %0,%1 1.1 root 4024: lhz%U1%X1 %0,%1 4025: sth%U0%X0 %1,%0 1.1.1.3 root 4026: {lil|li} %0,%w1 1.1 root 4027: mf%1 %0 4028: mt%0 %1 1.1.1.3 root 4029: mt%0 %1 1.1 root 4030: cror 0,0,0" 1.1.1.3 root 4031: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 4032: 1.1 root 4033: (define_expand "movqi" 4034: [(set (match_operand:QI 0 "general_operand" "") 4035: (match_operand:QI 1 "any_operand" ""))] 4036: "" 4037: " 4038: { 4039: if (GET_CODE (operands[0]) != REG) 4040: operands[1] = force_reg (QImode, operands[1]); 4041: 4042: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 4043: { 4044: operands[1] = force_const_mem (QImode, operands[1]); 4045: if (! memory_address_p (QImode, XEXP (operands[1], 0)) 4046: && ! reload_in_progress) 4047: operands[1] = change_address (operands[1], QImode, 4048: XEXP (operands[1], 0)); 4049: } 4050: }") 4051: 4052: (define_insn "" 1.1.1.3 root 4053: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 4054: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 4055: "gpc_reg_operand (operands[0], QImode) 4056: || gpc_reg_operand (operands[1], QImode)" 1.1 root 4057: "@ 1.1.1.3 root 4058: mr %0,%1 1.1 root 4059: lbz%U1%X1 %0,%1 4060: stb%U0%X0 %1,%0 1.1.1.3 root 4061: {lil|li} %0,%1 1.1 root 4062: mf%1 %0 4063: mt%0 %1 1.1.1.3 root 4064: mt%0 %1 1.1 root 4065: cror 0,0,0" 1.1.1.3 root 4066: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1 root 4067: 4068: ;; Here is how to move condition codes around. When we store CC data in 4069: ;; an integer register or memory, we store just the high-order 4 bits. 4070: ;; This lets us not shift in the most common case of CR0. 4071: (define_expand "movcc" 4072: [(set (match_operand:CC 0 "nonimmediate_operand" "") 4073: (match_operand:CC 1 "nonimmediate_operand" ""))] 4074: "" 4075: "") 4076: 4077: (define_insn "" 4078: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") 4079: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] 4080: "register_operand (operands[0], CCmode) 4081: || register_operand (operands[1], CCmode)" 4082: "@ 4083: mcrf %0,%1 4084: mtcrf 128,%1 1.1.1.2 root 4085: {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 1.1 root 4086: mfcr %0 1.1.1.2 root 4087: mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 1.1.1.3 root 4088: mr %0,%1 1.1.1.2 root 4089: {l%U1%X1|lwz%U1%X1} %0,%1 4090: {st%U0%U1|stw%U0%U1} %1,%0" 4091: [(set_attr "type" "*,*,*,compare,*,*,load,*") 4092: (set_attr "length" "*,*,12,*,8,*,*,*")]) 1.1 root 4093: 1.1.1.4 ! root 4094: ;; For floating-point, we normally deal with the floating-point registers ! 4095: ;; unless -msoft-float is used. The sole exception is that parameter passing ! 4096: ;; can produce floating-point values in fixed-point registers. Unless the ! 4097: ;; value is a simple constant or already in memory, we deal with this by ! 4098: ;; allocating memory and copying the value explicitly via that memory location. 1.1 root 4099: (define_expand "movsf" 4100: [(set (match_operand:SF 0 "nonimmediate_operand" "") 4101: (match_operand:SF 1 "any_operand" ""))] 4102: "" 4103: " 4104: { 4105: /* If we are called from reload, we might be getting a SUBREG of a hard 4106: reg. So expand it. */ 4107: if (GET_CODE (operands[0]) == SUBREG 4108: && GET_CODE (SUBREG_REG (operands[0])) == REG 4109: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) 4110: operands[0] = alter_subreg (operands[0]); 4111: if (GET_CODE (operands[1]) == SUBREG 4112: && GET_CODE (SUBREG_REG (operands[1])) == REG 4113: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) 4114: operands[1] = alter_subreg (operands[1]); 4115: 1.1.1.4 ! root 4116: if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM) ! 4117: operands[1] = force_reg (SFmode, operands[1]); ! 4118: ! 4119: else if (TARGET_HARD_FLOAT) 1.1 root 4120: { 1.1.1.4 ! root 4121: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) 1.1 root 4122: { 1.1.1.4 ! root 4123: /* If this is a store to memory or another integer register do the ! 4124: move directly. Otherwise store to a temporary stack slot and ! 4125: load from there into a floating point register. */ ! 4126: ! 4127: if (GET_CODE (operands[0]) == MEM ! 4128: || (GET_CODE (operands[0]) == REG ! 4129: && (REGNO (operands[0]) < 32 ! 4130: || (reload_in_progress ! 4131: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) ! 4132: { ! 4133: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 4134: operand_subword (operands[1], 0, 0, SFmode)); ! 4135: DONE; ! 4136: } ! 4137: else ! 4138: { ! 4139: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); ! 4140: ! 4141: emit_move_insn (stack_slot, operands[1]); ! 4142: emit_move_insn (operands[0], stack_slot); ! 4143: DONE; ! 4144: } 1.1 root 4145: } 1.1.1.4 ! root 4146: ! 4147: if (GET_CODE (operands[0]) == MEM) 1.1.1.3 root 4148: { 1.1.1.4 ! root 4149: /* If operands[1] is a register, it may have double-precision data ! 4150: in it, so truncate it to single precision. We need not do ! 4151: this for POWERPC. */ ! 4152: if (! TARGET_POWERPC && TARGET_HARD_FLOAT ! 4153: && GET_CODE (operands[1]) == REG) ! 4154: { ! 4155: rtx newreg ! 4156: = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); ! 4157: emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); ! 4158: operands[1] = newreg; ! 4159: } 1.1 root 4160: 1.1.1.4 ! root 4161: operands[1] = force_reg (SFmode, operands[1]); 1.1.1.3 root 4162: } 1.1 root 4163: 1.1.1.4 ! root 4164: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) 1.1.1.3 root 4165: { 1.1.1.4 ! root 4166: if (GET_CODE (operands[1]) == MEM 1.1 root 4167: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) 1.1.1.4 ! root 4168: || GET_CODE (operands[1]) == CONST_DOUBLE 1.1 root 4169: #endif 1.1.1.4 ! root 4170: || (GET_CODE (operands[1]) == REG ! 4171: && (REGNO (operands[1]) < 32 ! 4172: || (reload_in_progress ! 4173: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)))) ! 4174: { ! 4175: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 4176: operand_subword (operands[1], 0, 0, SFmode)); ! 4177: DONE; ! 4178: } ! 4179: else ! 4180: { ! 4181: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); ! 4182: ! 4183: emit_move_insn (stack_slot, operands[1]); ! 4184: emit_move_insn (operands[0], stack_slot); ! 4185: DONE; ! 4186: } 1.1.1.3 root 4187: } 1.1 root 4188: } 4189: 4190: if (CONSTANT_P (operands[1])) 4191: { 4192: operands[1] = force_const_mem (SFmode, operands[1]); 4193: if (! memory_address_p (SFmode, XEXP (operands[1], 0)) 4194: && ! reload_in_progress) 4195: operands[1] = change_address (operands[1], SFmode, 4196: XEXP (operands[1], 0)); 4197: } 4198: }") 4199: 4200: (define_split 4201: [(set (match_operand:SF 0 "gpc_reg_operand" "") 4202: (match_operand:SF 1 "easy_fp_constant" ""))] 4203: "reload_completed && REGNO (operands[0]) <= 31" 4204: [(set (match_dup 2) (match_dup 3))] 4205: " 4206: { operands[2] = operand_subword (operands[0], 0, 0, SFmode); 4207: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") 1.1.1.4 ! root 4208: 1.1 root 4209: (define_insn "" 4210: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") 4211: (match_operand:SF 1 "input_operand" "f,m,f"))] 1.1.1.4 ! root 4212: "(gpc_reg_operand (operands[0], SFmode) ! 4213: || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" 1.1 root 4214: "@ 4215: fmr %0,%1 4216: lfs%U1%X1 %0,%1 1.1.1.3 root 4217: stfs%U0%X0 %1,%0" 4218: [(set_attr "type" "fp,fpload,*")]) 1.1.1.4 ! root 4219: ! 4220: (define_insn "" ! 4221: [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r") ! 4222: (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))] ! 4223: "(gpc_reg_operand (operands[0], SFmode) ! 4224: || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" ! 4225: "@ ! 4226: mr %0,%1 ! 4227: {l%U1%X1|lwz%U1%X1} %0,%1 ! 4228: {st%U0%X0|stw%U0%X0} %1,%0 ! 4229: {lil|li} %0,%1 ! 4230: {liu|lis} %0,%u1 ! 4231: {cal|la} %0,%1(%*)" ! 4232: [(set_attr "type" "*,load,*,*,*,*")]) ! 4233: 1.1 root 4234: 4235: (define_expand "movdf" 4236: [(set (match_operand:DF 0 "nonimmediate_operand" "") 4237: (match_operand:DF 1 "any_operand" ""))] 4238: "" 4239: " 4240: { 1.1.1.2 root 4241: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1 root 4242: { 1.1.1.2 root 4243: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 4244: operand_subword_force (operands[1], 1, DFmode)); 4245: emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), 4246: operand_subword_force (operands[1], 0, DFmode)); 1.1 root 4247: DONE; 4248: } 4249: 1.1.1.2 root 4250: if (GET_CODE (operands[0]) != REG) 4251: operands[1] = force_reg (DFmode, operands[1]); 1.1 root 4252: 1.1.1.2 root 4253: if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) 1.1 root 4254: { 4255: operands[1] = force_const_mem (DFmode, operands[1]); 4256: if (! memory_address_p (DFmode, XEXP (operands[1], 0)) 4257: && ! reload_in_progress) 4258: operands[1] = change_address (operands[1], DFmode, 4259: XEXP (operands[1], 0)); 4260: } 4261: }") 4262: 4263: (define_split 4264: [(set (match_operand:DF 0 "gpc_reg_operand" "") 4265: (match_operand:DF 1 "easy_fp_constant" ""))] 4266: "reload_completed && REGNO (operands[0]) <= 31" 4267: [(set (match_dup 2) (match_dup 3)) 4268: (set (match_dup 4) (match_dup 5))] 4269: " 4270: { operands[2] = operand_subword (operands[0], 0, 0, DFmode); 4271: operands[3] = operand_subword (operands[1], 0, 0, DFmode); 4272: operands[4] = operand_subword (operands[0], 1, 0, DFmode); 4273: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") 1.1.1.2 root 4274: 4275: ;; Don't have reload use general registers to load a constant. First, 4276: ;; it might not work if the output operand has is the equivalent of 4277: ;; a non-offsettable memref, but also it is less efficient than loading 4278: ;; the constant into an FP register, since it will probably be used there. 4279: ;; The "??" is a kludge until we can figure out a more reasonable way 4280: ;; of handling these non-offsettable values. 4281: (define_insn "" 4282: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") 4283: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] 1.1.1.4 ! root 4284: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT ! 4285: && (register_operand (operands[0], DFmode) ! 4286: || register_operand (operands[1], DFmode))" 1.1.1.2 root 4287: "* 4288: { 4289: switch (which_alternative) 4290: { 4291: case 0: 4292: /* We normally copy the low-numbered register first. However, if 4293: the first register operand 0 is the same as the second register of 4294: operand 1, we must copy in the opposite order. */ 4295: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 root 4296: return \"mr %L0,%L1\;mr %0,%1\"; 1.1.1.2 root 4297: else 1.1.1.3 root 4298: return \"mr %0,%1\;mr %L0,%L1\"; 1.1.1.2 root 4299: case 1: 4300: /* If the low-address word is used in the address, we must load it 4301: last. Otherwise, load it first. Note that we cannot have 4302: auto-increment in that case since the address register is known to be 4303: dead. */ 4304: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4305: operands [1], 0)) 4306: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 4307: else 4308: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 4309: case 2: 4310: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 4311: case 3: 4312: return \"#\"; 4313: case 4: 4314: return \"fmr %0,%1\"; 4315: case 5: 4316: return \"lfd%U1%X1 %0,%1\"; 4317: case 6: 4318: return \"stfd%U0%X0 %1,%0\"; 4319: } 4320: }" 4321: [(set_attr "type" "*,load,*,*,fp,fpload,*") 4322: (set_attr "length" "8,8,8,8,*,*,*")]) 1.1.1.3 root 4323: 4324: (define_insn "" 1.1.1.4 ! root 4325: [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r") ! 4326: (match_operand:DF 1 "input_operand" "r,o,r,G"))] ! 4327: "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT ! 4328: && (register_operand (operands[0], DFmode) ! 4329: || register_operand (operands[1], DFmode))" ! 4330: "* ! 4331: { ! 4332: switch (which_alternative) ! 4333: { ! 4334: case 0: ! 4335: /* We normally copy the low-numbered register first. However, if ! 4336: the first register operand 0 is the same as the second register of ! 4337: operand 1, we must copy in the opposite order. */ ! 4338: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 4339: return \"mr %L0,%L1\;mr %0,%1\"; ! 4340: else ! 4341: return \"mr %0,%1\;mr %L0,%L1\"; ! 4342: case 1: ! 4343: /* If the low-address word is used in the address, we must load it ! 4344: last. Otherwise, load it first. Note that we cannot have ! 4345: auto-increment in that case since the address register is known to be ! 4346: dead. */ ! 4347: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 4348: operands [1], 0)) ! 4349: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; ! 4350: else ! 4351: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; ! 4352: case 2: ! 4353: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; ! 4354: case 3: ! 4355: return \"#\"; ! 4356: } ! 4357: }" ! 4358: [(set_attr "type" "*,load,*,*") ! 4359: (set_attr "length" "8,8,8,8")]) ! 4360: ! 4361: (define_insn "" 1.1.1.3 root 4362: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") 4363: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] 1.1.1.4 ! root 4364: "TARGET_POWERPC64 && TARGET_HARD_FLOAT ! 4365: && (register_operand (operands[0], DFmode) ! 4366: || register_operand (operands[1], DFmode))" 1.1.1.3 root 4367: "@ 4368: mr %0,%1 4369: ld%U1%X1 %0,%1 4370: sd%U0%X0 %1,%0 4371: # 4372: fmr %0,%1 4373: lfd%U1%X1 %0,%1 4374: stfd%U0%X0 %1,%0" 4375: [(set_attr "type" "*,load,*,*,fp,fpload,*")]) 1.1.1.4 ! root 4376: ! 4377: (define_insn "" ! 4378: [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r") ! 4379: (match_operand:DF 1 "input_operand" "r,o,r,G"))] ! 4380: "TARGET_POWERPC64 && TARGET_SOFT_FLOAT ! 4381: && (register_operand (operands[0], DFmode) ! 4382: || register_operand (operands[1], DFmode))" ! 4383: "@ ! 4384: mr %0,%1 ! 4385: ld%U1%X1 %0,%1 ! 4386: sd%U0%X0 %1,%0 ! 4387: #" ! 4388: [(set_attr "type" "*,load,*,*")]) 1.1 root 4389: 4390: ;; Next come the multi-word integer load and store and the load and store 4391: ;; multiple insns. 4392: (define_expand "movdi" 4393: [(set (match_operand:DI 0 "general_operand" "") 4394: (match_operand:DI 1 "general_operand" ""))] 4395: "" 4396: " 4397: { 1.1.1.4 ! root 4398: if (GET_CODE (operands[0]) == MEM) ! 4399: operands[1] = force_reg (DImode, operands[1]); ! 4400: 1.1 root 4401: if (GET_CODE (operands[1]) == CONST_DOUBLE 4402: || GET_CODE (operands[1]) == CONST_INT) 4403: { 1.1.1.4 ! root 4404: HOST_WIDE_INT low; ! 4405: HOST_WIDE_INT high; ! 4406: ! 4407: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 4408: { ! 4409: low = CONST_DOUBLE_LOW (operands[1]); ! 4410: high = CONST_DOUBLE_HIGH (operands[1]); ! 4411: } ! 4412: else ! 4413: { ! 4414: low = INTVAL (operands[1]); ! 4415: high = (low < 0) ? ~0 : 0; ! 4416: } ! 4417: ! 4418: emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN), ! 4419: GEN_INT (low)); ! 4420: ! 4421: emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], !WORDS_BIG_ENDIAN), ! 4422: GEN_INT (high)); 1.1 root 4423: DONE; 4424: } 4425: 1.1.1.3 root 4426: /* Stores between FPR and any non-FPR registers must go through a 4427: temporary stack slot. */ 4428: 4429: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG 4430: && ((FP_REGNO_P (REGNO (operands[0])) 4431: && ! FP_REGNO_P (REGNO (operands[1]))) 4432: || (FP_REGNO_P (REGNO (operands[1])) 4433: && ! FP_REGNO_P (REGNO (operands[0]))))) 4434: { 4435: rtx stack_slot = assign_stack_temp (DImode, 8, 0); 4436: 4437: emit_move_insn (stack_slot, operands[1]); 4438: emit_move_insn (operands[0], stack_slot); 4439: DONE; 4440: } 1.1 root 4441: }") 4442: 4443: (define_insn "" 1.1.1.3 root 4444: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m") 4445: (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))] 4446: "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) 4447: || gpc_reg_operand (operands[1], DImode))" 1.1 root 4448: "* 4449: { 4450: switch (which_alternative) 4451: { 4452: case 0: 4453: /* We normally copy the low-numbered register first. However, if 4454: the first register operand 0 is the same as the second register of 4455: operand 1, we must copy in the opposite order. */ 4456: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 root 4457: return \"mr %L0,%L1\;mr %0,%1\"; 1.1 root 4458: else 1.1.1.3 root 4459: return \"mr %0,%1\;mr %L0,%L1\"; 1.1 root 4460: case 1: 4461: /* If the low-address word is used in the address, we must load it 4462: last. Otherwise, load it first. Note that we cannot have 4463: auto-increment in that case since the address register is known to be 4464: dead. */ 4465: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4466: operands [1], 0)) 1.1.1.2 root 4467: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 1.1 root 4468: else 1.1.1.2 root 4469: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 1.1 root 4470: case 2: 1.1.1.2 root 4471: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 1.1.1.3 root 4472: case 3: 4473: return \"fmr %0,%1\"; 4474: case 4: 4475: return \"lfd%U1%X1 %0,%1\"; 4476: case 5: 4477: return \"stfd%U0%X0 %1,%0\"; 1.1 root 4478: } 4479: }" 1.1.1.3 root 4480: [(set_attr "type" "*,load,*,fp,fpload,*") 4481: (set_attr "length" "8,8,8,*,*,*")]) 4482: 4483: (define_insn "" 4484: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h") 4485: (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))] 4486: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) 4487: || gpc_reg_operand (operands[1], DImode))" 4488: "@ 4489: mr %0,%1 4490: ld%U1%X1 %0,%1 4491: sd%U0%X0 %1,%0 4492: li %0,%1 4493: lis %0,%u1 4494: {cal|la} %0,%1(%*) 4495: fmr %0,%1 4496: lfd%U1%X1 %0,%1 4497: stfd%U0%X0 %1,%0 4498: mf%1 %0 4499: mt%0 %1" 4500: [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")]) 1.1 root 4501: 4502: ;; TImode is similar, except that we usually want to compute the address into 4503: ;; a register and use lsi/stsi (the exception is during reload). MQ is also 1.1.1.2 root 4504: ;; clobbered in stsi for POWER, so we need a SCRATCH for it. 1.1 root 4505: (define_expand "movti" 4506: [(parallel [(set (match_operand:TI 0 "general_operand" "") 4507: (match_operand:TI 1 "general_operand" "")) 4508: (clobber (scratch:SI))])] 1.1.1.4 ! root 4509: "TARGET_STRING || TARGET_POWERPC64" 1.1 root 4510: " 4511: { 4512: if (GET_CODE (operands[0]) == MEM) 4513: operands[1] = force_reg (TImode, operands[1]); 4514: 4515: if (GET_CODE (operands[0]) == MEM 4516: && GET_CODE (XEXP (operands[0], 0)) != REG 4517: && ! reload_in_progress) 4518: operands[0] = change_address (operands[0], TImode, 4519: copy_addr_to_reg (XEXP (operands[0], 0))); 4520: 4521: if (GET_CODE (operands[1]) == MEM 4522: && GET_CODE (XEXP (operands[1], 0)) != REG 4523: && ! reload_in_progress) 4524: operands[1] = change_address (operands[1], TImode, 4525: copy_addr_to_reg (XEXP (operands[1], 0))); 4526: }") 4527: 4528: ;; We say that MQ is clobbered in the last alternative because the first 4529: ;; alternative would never get used otherwise since it would need a reload 4530: ;; while the 2nd alternative would not. We put memory cases first so they 4531: ;; are preferred. Otherwise, we'd try to reload the output instead of 4532: ;; giving the SCRATCH mq. 4533: (define_insn "" 1.1.1.3 root 4534: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 1.1 root 4535: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) 4536: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] 1.1.1.4 ! root 4537: "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 ! 4538: && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 1.1 root 4539: "* 4540: { 4541: switch (which_alternative) 4542: { 1.1.1.4 ! root 4543: default: ! 4544: abort (); ! 4545: 1.1 root 4546: case 0: 1.1.1.2 root 4547: return \"{stsi|stswi} %1,%P0,16\"; 1.1 root 4548: 4549: case 1: 1.1.1.2 root 4550: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 1.1 root 4551: 4552: case 2: 4553: /* Normally copy registers with lowest numbered register copied first. 4554: But copy in the other order if the first register of the output 4555: is the second, third, or fourth register in the input. */ 4556: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 4557: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 1.1.1.3 root 4558: return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 1.1 root 4559: else 1.1.1.3 root 4560: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 1.1 root 4561: case 3: 4562: /* If the address is not used in the output, we can use lsi. Otherwise, 4563: fall through to generating four loads. */ 4564: if (! reg_overlap_mentioned_p (operands[0], operands[1])) 1.1.1.2 root 4565: return \"{lsi|lswi} %0,%P1,16\"; 1.1 root 4566: /* ... fall through ... */ 4567: case 4: 4568: /* If the address register is the same as the register for the lowest- 4569: addressed word, load it last. Similarly for the next two words. 4570: Otherwise load lowest address to highest. */ 4571: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4572: operands[1], 0)) 1.1.1.2 root 4573: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 1.1 root 4574: else if (refers_to_regno_p (REGNO (operands[0]) + 1, 4575: REGNO (operands[0]) + 2, operands[1], 0)) 1.1.1.2 root 4576: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 1.1 root 4577: else if (refers_to_regno_p (REGNO (operands[0]) + 2, 4578: REGNO (operands[0]) + 3, operands[1], 0)) 1.1.1.2 root 4579: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 1.1 root 4580: else 1.1.1.2 root 4581: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 1.1 root 4582: } 4583: }" 1.1.1.2 root 4584: [(set_attr "type" "*,load,load,*,*") 4585: (set_attr "length" "*,16,16,*,16")]) 1.1.1.3 root 4586: 4587: (define_insn "" 1.1.1.4 ! root 4588: [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") ! 4589: (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) ! 4590: (clobber (match_scratch:SI 2 "=X,X,X"))] ! 4591: "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64 ! 4592: && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" ! 4593: "* ! 4594: { ! 4595: switch (which_alternative) ! 4596: { ! 4597: default: ! 4598: abort (); ! 4599: ! 4600: case 0: ! 4601: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; ! 4602: ! 4603: case 1: ! 4604: /* Normally copy registers with lowest numbered register copied first. ! 4605: But copy in the other order if the first register of the output ! 4606: is the second, third, or fourth register in the input. */ ! 4607: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 ! 4608: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) ! 4609: return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; ! 4610: else ! 4611: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; ! 4612: case 2: ! 4613: /* If the address register is the same as the register for the lowest- ! 4614: addressed word, load it last. Similarly for the next two words. ! 4615: Otherwise load lowest address to highest. */ ! 4616: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 4617: operands[1], 0)) ! 4618: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; ! 4619: else if (refers_to_regno_p (REGNO (operands[0]) + 1, ! 4620: REGNO (operands[0]) + 2, operands[1], 0)) ! 4621: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; ! 4622: else if (refers_to_regno_p (REGNO (operands[0]) + 2, ! 4623: REGNO (operands[0]) + 3, operands[1], 0)) ! 4624: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; ! 4625: else ! 4626: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; ! 4627: } ! 4628: }" ! 4629: [(set_attr "type" "load,*,*") ! 4630: (set_attr "length" "16,16,16")]) ! 4631: ! 4632: (define_insn "" 1.1.1.3 root 4633: [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") 4634: (match_operand:TI 1 "input_operand" "r,m,r"))] 4635: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 4636: || gpc_reg_operand (operands[1], TImode))" 4637: "* 4638: { 4639: switch (which_alternative) 4640: { 4641: case 0: 4642: /* We normally copy the low-numbered register first. However, if 4643: the first register operand 0 is the same as the second register of 4644: operand 1, we must copy in the opposite order. */ 4645: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 4646: return \"mr %L0,%L1\;mr %0,%1\"; 4647: else 4648: return \"mr %0,%1\;mr %L0,%L1\"; 4649: case 1: 4650: /* If the low-address word is used in the address, we must load it 4651: last. Otherwise, load it first. Note that we cannot have 4652: auto-increment in that case since the address register is known to be 4653: dead. */ 4654: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4655: operands [1], 0)) 4656: return \"ld %L0,%L1\;ld %0,%1\"; 4657: else 4658: return \"ld%U1 %0,%1\;ld %L0,%L1\"; 4659: case 2: 4660: return \"std%U0 %1,%0\;std %L1,%L0\"; 4661: } 4662: }" 4663: [(set_attr "type" "*,load,*") 4664: (set_attr "length" "8,8,8")]) 1.1 root 4665: 4666: (define_expand "load_multiple" 4667: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4668: (match_operand:SI 1 "" "")) 4669: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 ! root 4670: "TARGET_STRING" 1.1 root 4671: " 4672: { 4673: int regno; 4674: int count; 4675: rtx from; 4676: int i; 4677: 4678: /* Support only loading a constant number of fixed-point registers from 4679: memory and only bother with this if more than two; the machine 4680: doesn't support more than eight. */ 4681: if (GET_CODE (operands[2]) != CONST_INT 4682: || INTVAL (operands[2]) <= 2 4683: || INTVAL (operands[2]) > 8 4684: || GET_CODE (operands[1]) != MEM 4685: || GET_CODE (operands[0]) != REG 4686: || REGNO (operands[0]) >= 32) 4687: FAIL; 4688: 4689: count = INTVAL (operands[2]); 4690: regno = REGNO (operands[0]); 4691: 4692: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); 4693: from = force_reg (SImode, XEXP (operands[1], 0)); 4694: 4695: for (i = 0; i < count; i++) 4696: XVECEXP (operands[3], 0, i) 4697: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), 4698: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); 4699: }") 4700: 4701: (define_insn "" 4702: [(match_parallel 0 "load_multiple_operation" 4703: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 1.1.1.4 ! root 4704: (mem:SI (match_operand:SI 2 "register_operand" "b")))])] ! 4705: "TARGET_STRING" 1.1 root 4706: "* 4707: { 4708: /* We have to handle the case where the pseudo used to contain the address 1.1.1.4 ! root 4709: is assigned to one of the output registers. */ ! 4710: int i, j; ! 4711: int words = XVECLEN (operands[0], 0); ! 4712: rtx xop[10]; 1.1 root 4713: 1.1.1.4 ! root 4714: if (XVECLEN (operands[0], 0) == 1) ! 4715: return \"{l|lwz} %1,0(%2)\"; ! 4716: ! 4717: for (i = 0; i < words; i++) 1.1 root 4718: if (refers_to_regno_p (REGNO (operands[1]) + i, 4719: REGNO (operands[1]) + i + 1, operands[2], 0)) 4720: { 1.1.1.4 ! root 4721: if (i == words-1) ! 4722: { ! 4723: xop[0] = operands[1]; ! 4724: xop[1] = operands[2]; ! 4725: xop[2] = GEN_INT (4 * (words-1)); ! 4726: output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); ! 4727: return \"\"; ! 4728: } ! 4729: else if (i == 0) ! 4730: { ! 4731: xop[0] = operands[1]; ! 4732: xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 4733: xop[2] = GEN_INT (4 * (words-1)); ! 4734: output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); ! 4735: return \"\"; ! 4736: } ! 4737: else ! 4738: { ! 4739: for (j = 0; j < words; j++) ! 4740: if (j != i) ! 4741: { ! 4742: xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j); ! 4743: xop[1] = operands[2]; ! 4744: xop[2] = GEN_INT (j * 4); ! 4745: output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); ! 4746: } ! 4747: xop[0] = operands[2]; ! 4748: xop[1] = GEN_INT (i * 4); ! 4749: output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); ! 4750: return \"\"; ! 4751: } 1.1 root 4752: } 4753: 1.1.1.4 ! root 4754: return \"{lsi|lswi} %1,%2,%N0\"; 1.1 root 4755: }" 1.1.1.2 root 4756: [(set_attr "type" "load") 1.1.1.4 ! root 4757: (set_attr "length" "32")]) 1.1 root 4758: 1.1.1.2 root 4759: 1.1 root 4760: (define_expand "store_multiple" 4761: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4762: (match_operand:SI 1 "" "")) 4763: (clobber (scratch:SI)) 4764: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 ! root 4765: "TARGET_STRING" 1.1 root 4766: " 4767: { 4768: int regno; 4769: int count; 4770: rtx to; 4771: int i; 4772: 4773: /* Support only storing a constant number of fixed-point registers to 4774: memory and only bother with this if more than two; the machine 4775: doesn't support more than eight. */ 4776: if (GET_CODE (operands[2]) != CONST_INT 4777: || INTVAL (operands[2]) <= 2 4778: || INTVAL (operands[2]) > 8 4779: || GET_CODE (operands[0]) != MEM 4780: || GET_CODE (operands[1]) != REG 4781: || REGNO (operands[1]) >= 32) 4782: FAIL; 4783: 4784: count = INTVAL (operands[2]); 4785: regno = REGNO (operands[1]); 4786: 4787: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); 4788: to = force_reg (SImode, XEXP (operands[0], 0)); 4789: 4790: XVECEXP (operands[3], 0, 0) 4791: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); 4792: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, 4793: gen_rtx (SCRATCH, SImode)); 4794: 4795: for (i = 1; i < count; i++) 4796: XVECEXP (operands[3], 0, i + 1) 4797: = gen_rtx (SET, VOIDmode, 4798: gen_rtx (MEM, SImode, plus_constant (to, i * 4)), 4799: gen_rtx (REG, SImode, regno + i)); 4800: }") 4801: 4802: (define_insn "" 4803: [(match_parallel 0 "store_multiple_operation" 4804: [(set (match_operand:SI 1 "indirect_operand" "=Q") 4805: (match_operand:SI 2 "gpc_reg_operand" "r")) 4806: (clobber (match_scratch:SI 3 "=q"))])] 1.1.1.4 ! root 4807: "TARGET_STRING && TARGET_POWER" 1.1.1.2 root 4808: "{stsi|stswi} %2,%P1,%O0") 1.1.1.4 ! root 4809: ! 4810: (define_insn "" ! 4811: [(match_parallel 0 "store_multiple_operation" ! 4812: [(set (mem:SI (match_operand:SI 1 "register_operand" "b")) ! 4813: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4814: (clobber (match_scratch:SI 3 "X"))])] ! 4815: "TARGET_STRING && !TARGET_POWER" ! 4816: "{stsi|stswi} %2,%1,%O0") ! 4817: 1.1 root 4818: 1.1.1.4 ! root 4819: ;; String/block move insn. ! 4820: ;; Argument 0 is the destination ! 4821: ;; Argument 1 is the source ! 4822: ;; Argument 2 is the length ! 4823: ;; Argument 3 is the alignment ! 4824: ! 4825: (define_expand "movstrsi" ! 4826: [(parallel [(set (match_operand:BLK 0 "memory_operand" "") ! 4827: (match_operand:BLK 1 "memory_operand" "")) ! 4828: (use (match_operand:SI 2 "general_operand" "")) ! 4829: (use (match_operand:SI 3 "immediate_operand" ""))])] ! 4830: "" ! 4831: " ! 4832: { ! 4833: if (expand_block_move (operands)) ! 4834: DONE; ! 4835: else ! 4836: FAIL; ! 4837: }") ! 4838: ! 4839: ;; Move up to 32 bytes at a time. The fixed registers are needed because the ! 4840: ;; register allocator doesn't have a clue about allocating 8 word registers ! 4841: (define_expand "movstrsi_8reg" ! 4842: [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) ! 4843: (mem:BLK (match_operand:SI 1 "register_operand" ""))) ! 4844: (use (match_operand:SI 2 "immediate_operand" "")) ! 4845: (use (match_operand:SI 3 "immediate_operand" "")) ! 4846: (clobber (reg:SI 5)) ! 4847: (clobber (reg:SI 6)) ! 4848: (clobber (reg:SI 7)) ! 4849: (clobber (reg:SI 8)) ! 4850: (clobber (reg:SI 9)) ! 4851: (clobber (reg:SI 10)) ! 4852: (clobber (reg:SI 11)) ! 4853: (clobber (reg:SI 12)) ! 4854: (clobber (match_scratch:SI 4 ""))])] ! 4855: "TARGET_STRING" ! 4856: "") ! 4857: ! 4858: (define_insn "" ! 4859: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4860: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4861: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4862: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4863: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4864: (clobber (reg:SI 6)) ! 4865: (clobber (reg:SI 7)) ! 4866: (clobber (reg:SI 8)) ! 4867: (clobber (reg:SI 9)) ! 4868: (clobber (reg:SI 10)) ! 4869: (clobber (reg:SI 11)) ! 4870: (clobber (reg:SI 12)) ! 4871: (clobber (match_scratch:SI 5 "=q"))] ! 4872: "TARGET_STRING && TARGET_POWER ! 4873: && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) ! 4874: && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) ! 4875: && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) ! 4876: && REGNO (operands[4]) == 5" ! 4877: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 4878: [(set_attr "length" "8")]) ! 4879: ! 4880: (define_insn "" ! 4881: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4882: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4883: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4884: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4885: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4886: (clobber (reg:SI 6)) ! 4887: (clobber (reg:SI 7)) ! 4888: (clobber (reg:SI 8)) ! 4889: (clobber (reg:SI 9)) ! 4890: (clobber (reg:SI 10)) ! 4891: (clobber (reg:SI 11)) ! 4892: (clobber (reg:SI 12)) ! 4893: (clobber (match_scratch:SI 5 "X"))] ! 4894: "TARGET_STRING && !TARGET_POWER ! 4895: && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) ! 4896: && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) ! 4897: && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) ! 4898: && REGNO (operands[4]) == 5" ! 4899: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 4900: [(set_attr "length" "8")]) ! 4901: ! 4902: ;; Move up to 24 bytes at a time. The fixed registers are needed because the ! 4903: ;; register allocator doesn't have a clue about allocating 6 word registers ! 4904: (define_expand "movstrsi_6reg" ! 4905: [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) ! 4906: (mem:BLK (match_operand:SI 1 "register_operand" ""))) ! 4907: (use (match_operand:SI 2 "immediate_operand" "")) ! 4908: (use (match_operand:SI 3 "immediate_operand" "")) ! 4909: (clobber (reg:SI 7)) ! 4910: (clobber (reg:SI 8)) ! 4911: (clobber (reg:SI 9)) ! 4912: (clobber (reg:SI 10)) ! 4913: (clobber (reg:SI 11)) ! 4914: (clobber (reg:SI 12)) ! 4915: (clobber (match_scratch:SI 4 ""))])] ! 4916: "TARGET_STRING" ! 4917: "") ! 4918: ! 4919: (define_insn "" ! 4920: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4921: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4922: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4923: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4924: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4925: (clobber (reg:SI 8)) ! 4926: (clobber (reg:SI 9)) ! 4927: (clobber (reg:SI 10)) ! 4928: (clobber (reg:SI 11)) ! 4929: (clobber (reg:SI 12)) ! 4930: (clobber (match_scratch:SI 5 "=q"))] ! 4931: "TARGET_STRING && TARGET_POWER ! 4932: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 ! 4933: && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) ! 4934: && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) ! 4935: && REGNO (operands[4]) == 7" ! 4936: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 4937: [(set_attr "length" "8")]) ! 4938: ! 4939: (define_insn "" ! 4940: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4941: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4942: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4943: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4944: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4945: (clobber (reg:SI 8)) ! 4946: (clobber (reg:SI 9)) ! 4947: (clobber (reg:SI 10)) ! 4948: (clobber (reg:SI 11)) ! 4949: (clobber (reg:SI 12)) ! 4950: (clobber (match_scratch:SI 5 "X"))] ! 4951: "TARGET_STRING && !TARGET_POWER ! 4952: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 ! 4953: && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) ! 4954: && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) ! 4955: && REGNO (operands[4]) == 7" ! 4956: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 4957: [(set_attr "length" "8")]) ! 4958: ! 4959: ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems ! 4960: ;; with TImode ! 4961: (define_expand "movstrsi_4reg" ! 4962: [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) ! 4963: (mem:BLK (match_operand:SI 1 "register_operand" ""))) ! 4964: (use (match_operand:SI 2 "immediate_operand" "")) ! 4965: (use (match_operand:SI 3 "immediate_operand" "")) ! 4966: (clobber (reg:SI 9)) ! 4967: (clobber (reg:SI 10)) ! 4968: (clobber (reg:SI 11)) ! 4969: (clobber (reg:SI 12)) ! 4970: (clobber (match_scratch:SI 4 ""))])] ! 4971: "TARGET_STRING" ! 4972: "") ! 4973: ! 4974: (define_insn "" ! 4975: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4976: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4977: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4978: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4979: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4980: (clobber (reg:SI 10)) ! 4981: (clobber (reg:SI 11)) ! 4982: (clobber (reg:SI 12)) ! 4983: (clobber (match_scratch:SI 5 "=q"))] ! 4984: "TARGET_STRING && TARGET_POWER ! 4985: && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 ! 4986: && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) ! 4987: && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) ! 4988: && REGNO (operands[4]) == 9" ! 4989: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 4990: [(set_attr "length" "8")]) ! 4991: ! 4992: (define_insn "" ! 4993: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 4994: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 4995: (use (match_operand:SI 2 "immediate_operand" "i")) ! 4996: (use (match_operand:SI 3 "immediate_operand" "i")) ! 4997: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 4998: (clobber (reg:SI 10)) ! 4999: (clobber (reg:SI 11)) ! 5000: (clobber (reg:SI 12)) ! 5001: (clobber (match_scratch:SI 5 "X"))] ! 5002: "TARGET_STRING && !TARGET_POWER ! 5003: && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 ! 5004: && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) ! 5005: && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) ! 5006: && REGNO (operands[4]) == 9" ! 5007: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 5008: [(set_attr "length" "8")]) ! 5009: ! 5010: ;; Move up to 8 bytes at a time. ! 5011: (define_expand "movstrsi_2reg" ! 5012: [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) ! 5013: (mem:BLK (match_operand:SI 1 "register_operand" ""))) ! 5014: (use (match_operand:SI 2 "immediate_operand" "")) ! 5015: (use (match_operand:SI 3 "immediate_operand" "")) ! 5016: (clobber (match_scratch:DI 4 "")) ! 5017: (clobber (match_scratch:SI 5 ""))])] ! 5018: "TARGET_STRING && !TARGET_64BIT" ! 5019: "") ! 5020: ! 5021: (define_insn "" ! 5022: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 5023: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 5024: (use (match_operand:SI 2 "immediate_operand" "i")) ! 5025: (use (match_operand:SI 3 "immediate_operand" "i")) ! 5026: (clobber (match_scratch:DI 4 "=&r")) ! 5027: (clobber (match_scratch:SI 5 "=q"))] ! 5028: "TARGET_STRING && TARGET_POWER && !TARGET_64BIT ! 5029: && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" ! 5030: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 5031: [(set_attr "length" "8")]) ! 5032: ! 5033: (define_insn "" ! 5034: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 5035: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 5036: (use (match_operand:SI 2 "immediate_operand" "i")) ! 5037: (use (match_operand:SI 3 "immediate_operand" "i")) ! 5038: (clobber (match_scratch:DI 4 "=&r")) ! 5039: (clobber (match_scratch:SI 5 "X"))] ! 5040: "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT ! 5041: && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" ! 5042: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 5043: [(set_attr "length" "8")]) ! 5044: ! 5045: ;; Move up to 4 bytes at a time. ! 5046: (define_expand "movstrsi_1reg" ! 5047: [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) ! 5048: (mem:BLK (match_operand:SI 1 "register_operand" ""))) ! 5049: (use (match_operand:SI 2 "immediate_operand" "")) ! 5050: (use (match_operand:SI 3 "immediate_operand" "")) ! 5051: (clobber (match_scratch:SI 4 "")) ! 5052: (clobber (match_scratch:SI 5 ""))])] ! 5053: "TARGET_STRING" ! 5054: "") ! 5055: ! 5056: (define_insn "" ! 5057: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 5058: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 5059: (use (match_operand:SI 2 "immediate_operand" "i")) ! 5060: (use (match_operand:SI 3 "immediate_operand" "i")) ! 5061: (clobber (match_scratch:SI 4 "=&r")) ! 5062: (clobber (match_scratch:SI 5 "=q"))] ! 5063: "TARGET_STRING && TARGET_POWER ! 5064: && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" ! 5065: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 5066: [(set_attr "length" "8")]) ! 5067: ! 5068: (define_insn "" ! 5069: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) ! 5070: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) ! 5071: (use (match_operand:SI 2 "immediate_operand" "i")) ! 5072: (use (match_operand:SI 3 "immediate_operand" "i")) ! 5073: (clobber (match_scratch:SI 4 "=&r")) ! 5074: (clobber (match_scratch:SI 5 "X"))] ! 5075: "TARGET_STRING && !TARGET_POWER ! 5076: && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" ! 5077: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" ! 5078: [(set_attr "length" "8")]) ! 5079: ! 5080: ! 5081: ;; Define insns that do load or store with update. Some of these we can 1.1 root 5082: ;; get by using pre-decrement or pre-increment, but the hardware can also 5083: ;; do cases where the increment is not the size of the object. 5084: ;; 5085: ;; In all these cases, we use operands 0 and 1 for the register being 5086: ;; incremented because those are the operands that local-alloc will 5087: ;; tie and these are the pair most likely to be tieable (and the ones 5088: ;; that will benefit the most). 5089: 5090: (define_insn "" 1.1.1.3 root 5091: [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 5092: (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 5093: (match_operand:DI 2 "reg_or_short_operand" "r,I")))) 5094: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 5095: (plus:DI (match_dup 1) (match_dup 2)))] 5096: "TARGET_POWERPC64" 5097: "@ 5098: ldux %3,%0,%2 5099: ldu %3,%2(%0)" 5100: [(set_attr "type" "load")]) 5101: 5102: (define_insn "" 1.1.1.4 ! root 5103: [(set (match_operand:DI 3 "gpc_reg_operand" "=r") ! 5104: (sign_extend:DI ! 5105: (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") ! 5106: (match_operand:DI 2 "gpc_reg_operand" "r"))))) ! 5107: (set (match_operand:DI 0 "gpc_reg_operand" "=b") ! 5108: (plus:DI (match_dup 1) (match_dup 2)))] ! 5109: "TARGET_POWERPC64" ! 5110: "lwaux %3,%0,%2" ! 5111: [(set_attr "type" "load")]) ! 5112: ! 5113: (define_insn "movdi_update" 1.1.1.3 root 5114: [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 5115: (match_operand:DI 2 "reg_or_short_operand" "r,I"))) 5116: (match_operand:DI 3 "gpc_reg_operand" "r,r")) 5117: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 5118: (plus:DI (match_dup 1) (match_dup 2)))] 5119: "TARGET_POWERPC64" 5120: "@ 5121: stdux %3,%0,%2 5122: stdu %3,%2(%0)") 5123: 5124: (define_insn "" 1.1 root 5125: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5126: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5127: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5128: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5129: (plus:SI (match_dup 1) (match_dup 2)))] 5130: "" 5131: "@ 1.1.1.2 root 5132: {lux|lwzux} %3,%0,%2 5133: {lu|lwzu} %3,%2(%0)" 5134: [(set_attr "type" "load")]) 1.1 root 5135: 1.1.1.4 ! root 5136: (define_insn "movsi_update" 1.1 root 5137: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5138: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5139: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5140: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5141: (plus:SI (match_dup 1) (match_dup 2)))] 5142: "" 5143: "@ 1.1.1.2 root 5144: {stux|stwux} %3,%0,%2 5145: {stu|stwu} %3,%2(%0)") 1.1 root 5146: 5147: (define_insn "" 5148: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 5149: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5150: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5151: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5152: (plus:SI (match_dup 1) (match_dup 2)))] 5153: "" 5154: "@ 5155: lhzux %3,%0,%2 5156: lhzu %3,%2(%0)" 1.1.1.2 root 5157: [(set_attr "type" "load")]) 1.1 root 5158: 5159: (define_insn "" 5160: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5161: (zero_extend:SI 5162: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5163: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5164: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5165: (plus:SI (match_dup 1) (match_dup 2)))] 5166: "" 5167: "@ 5168: lhzux %3,%0,%2 5169: lhzu %3,%2(%0)" 1.1.1.2 root 5170: [(set_attr "type" "load")]) 1.1 root 5171: 5172: (define_insn "" 5173: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5174: (sign_extend:SI 5175: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5176: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5177: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5178: (plus:SI (match_dup 1) (match_dup 2)))] 5179: "" 5180: "@ 5181: lhaux %3,%0,%2 5182: lhau %3,%2(%0)" 1.1.1.2 root 5183: [(set_attr "type" "load")]) 1.1 root 5184: 5185: (define_insn "" 5186: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5187: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5188: (match_operand:HI 3 "gpc_reg_operand" "r,r")) 5189: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5190: (plus:SI (match_dup 1) (match_dup 2)))] 5191: "" 5192: "@ 5193: sthux %3,%0,%2 1.1.1.2 root 5194: sthu %3,%2(%0)") 1.1 root 5195: 5196: (define_insn "" 5197: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 5198: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5199: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5200: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5201: (plus:SI (match_dup 1) (match_dup 2)))] 5202: "" 5203: "@ 5204: lbzux %3,%0,%2 5205: lbzu %3,%2(%0)" 1.1.1.2 root 5206: [(set_attr "type" "load")]) 1.1 root 5207: 5208: (define_insn "" 5209: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5210: (zero_extend:SI 5211: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5212: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5213: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5214: (plus:SI (match_dup 1) (match_dup 2)))] 5215: "" 5216: "@ 5217: lbzux %3,%0,%2 5218: lbzu %3,%2(%0)" 1.1.1.2 root 5219: [(set_attr "type" "load")]) 1.1 root 5220: 5221: (define_insn "" 5222: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5223: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5224: (match_operand:QI 3 "gpc_reg_operand" "r,r")) 5225: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5226: (plus:SI (match_dup 1) (match_dup 2)))] 5227: "" 5228: "@ 5229: stbux %3,%0,%2 5230: stbu %3,%2(%0)") 5231: 5232: (define_insn "" 5233: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 1.1.1.3 root 5234: (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 1.1 root 5235: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5236: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5237: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 ! root 5238: "TARGET_HARD_FLOAT" 1.1 root 5239: "@ 5240: lfsux %3,%0,%2 5241: lfsu %3,%2(%0)" 1.1.1.2 root 5242: [(set_attr "type" "fpload")]) 1.1 root 5243: 5244: (define_insn "" 5245: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5246: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5247: (match_operand:SF 3 "gpc_reg_operand" "f,f")) 5248: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5249: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 ! root 5250: "TARGET_HARD_FLOAT" 1.1 root 5251: "@ 1.1.1.3 root 5252: stfsux %3,%0,%2 5253: stfsu %3,%2(%0)") 1.1 root 5254: 5255: (define_insn "" 5256: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 5257: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5258: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5259: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5260: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 ! root 5261: "TARGET_HARD_FLOAT" 1.1 root 5262: "@ 5263: lfdux %3,%0,%2 5264: lfdu %3,%2(%0)" 1.1.1.2 root 5265: [(set_attr "type" "fpload")]) 1.1 root 5266: 5267: (define_insn "" 5268: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5269: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5270: (match_operand:DF 3 "gpc_reg_operand" "f,f")) 5271: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5272: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 ! root 5273: "TARGET_HARD_FLOAT" 1.1 root 5274: "@ 5275: stfdux %3,%0,%2 5276: stfdu %3,%2(%0)") 1.1.1.4 ! root 5277: ! 5278: ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. ! 5279: ! 5280: (define_peephole ! 5281: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 5282: (match_operand:DF 1 "memory_operand" "")) ! 5283: (set (match_operand:DF 2 "gpc_reg_operand" "=f") ! 5284: (match_operand:DF 3 "memory_operand" ""))] ! 5285: "TARGET_POWER2 ! 5286: && TARGET_HARD_FLOAT ! 5287: && registers_ok_for_quad_peep (operands[0], operands[2]) ! 5288: && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) ! 5289: && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" ! 5290: "lfq%U1%X1 %0,%1") ! 5291: ! 5292: (define_peephole ! 5293: [(set (match_operand:DF 0 "memory_operand" "") ! 5294: (match_operand:DF 1 "gpc_reg_operand" "f")) ! 5295: (set (match_operand:DF 2 "memory_operand" "") ! 5296: (match_operand:DF 3 "gpc_reg_operand" "f"))] ! 5297: "TARGET_POWER2 ! 5298: && TARGET_HARD_FLOAT ! 5299: && registers_ok_for_quad_peep (operands[1], operands[3]) ! 5300: && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) ! 5301: && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" ! 5302: "stfq%U0%X0 %1,%0") 1.1 root 5303: 5304: ;; Next come insns related to the calling sequence. 5305: ;; 5306: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 1.1.1.4 ! root 5307: ;; We move the back-chain and decrement the stack pointer. 1.1 root 5308: 5309: (define_expand "allocate_stack" 5310: [(set (reg:SI 1) 5311: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] 5312: "" 5313: " 1.1.1.4 ! root 5314: { rtx chain = gen_reg_rtx (Pmode); 1.1 root 5315: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); 1.1.1.4 ! root 5316: rtx neg_op0; 1.1 root 5317: 5318: emit_move_insn (chain, stack_bot); 1.1.1.4 ! root 5319: ! 5320: if (GET_CODE (operands[0]) != CONST_INT ! 5321: || INTVAL (operands[0]) < -32767 ! 5322: || INTVAL (operands[0]) > 32768) ! 5323: { ! 5324: neg_op0 = gen_reg_rtx (Pmode); ! 5325: if (TARGET_POWERPC64) ! 5326: emit_insn (gen_negdi2 (neg_op0, operands[0])); ! 5327: else ! 5328: emit_insn (gen_negsi2 (neg_op0, operands[0])); ! 5329: } ! 5330: else ! 5331: neg_op0 = GEN_INT (- INTVAL (operands[0])); ! 5332: ! 5333: if (TARGET_POWERPC64) ! 5334: emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); ! 5335: else ! 5336: emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); ! 5337: 1.1 root 5338: DONE; 5339: }") 5340: 5341: ;; These patterns say how to save and restore the stack pointer. We need not 5342: ;; save the stack pointer at function level since we are careful to 5343: ;; preserve the backchain. At block level, we have to restore the backchain 5344: ;; when we restore the stack pointer. 5345: ;; 5346: ;; For nonlocal gotos, we must save both the stack pointer and its 5347: ;; backchain and restore both. Note that in the nonlocal case, the 5348: ;; save area is a memory location. 5349: 5350: (define_expand "save_stack_function" 5351: [(use (const_int 0))] 5352: "" 5353: "") 5354: 5355: (define_expand "restore_stack_function" 5356: [(use (const_int 0))] 5357: "" 5358: "") 5359: 5360: (define_expand "restore_stack_block" 5361: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) 5362: (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) 5363: (set (mem:SI (match_dup 0)) (match_dup 2))] 5364: "" 5365: " 5366: { operands[2] = gen_reg_rtx (SImode); }") 5367: 5368: (define_expand "save_stack_nonlocal" 5369: [(match_operand:DI 0 "memory_operand" "") 5370: (match_operand:SI 1 "register_operand" "")] 5371: "" 5372: " 5373: { 5374: rtx temp = gen_reg_rtx (SImode); 5375: 5376: /* Copy the backchain to the first word, sp to the second. */ 5377: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); 5378: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); 5379: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); 5380: DONE; 5381: }") 1.1.1.4 ! root 5382: 1.1 root 5383: (define_expand "restore_stack_nonlocal" 5384: [(match_operand:SI 0 "register_operand" "") 5385: (match_operand:DI 1 "memory_operand" "")] 5386: "" 5387: " 5388: { 5389: rtx temp = gen_reg_rtx (SImode); 5390: 5391: /* Restore the backchain from the first word, sp from the second. */ 5392: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); 5393: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); 5394: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); 5395: DONE; 5396: }") 5397: 5398: ;; A function pointer is a pointer to a data area whose first word contains 5399: ;; the actual address of the function, whose second word contains a pointer 5400: ;; to its TOC, and whose third word contains a value to place in the static 1.1.1.4 ! root 5401: ;; chain register (r11). Note that if we load the static chain, our 1.1 root 5402: ;; "trampoline" need not have any executable code. 5403: ;; 5404: ;; operands[0] is an SImode pseudo in which we place the address of the 5405: ;; function. 5406: ;; operands[1] is the address of data area of the function to call 5407: 5408: (define_expand "call_via_ptr" 5409: [(set (match_operand:SI 0 "gpc_reg_operand" "") 5410: (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 5411: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 5412: (reg:SI 2)) 5413: (set (reg:SI 2) 5414: (mem:SI (plus:SI (match_dup 1) 5415: (const_int 4)))) 5416: (set (reg:SI 11) 5417: (mem:SI (plus:SI (match_dup 1) 5418: (const_int 8)))) 5419: (use (reg:SI 2)) 5420: (use (reg:SI 11))] 5421: "" 5422: "") 5423: 5424: (define_expand "call" 5425: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) 5426: (match_operand 1 "" "")) 1.1.1.4 ! root 5427: (use (match_operand 2 "" "")) 1.1 root 5428: (clobber (scratch:SI))])] 5429: "" 5430: " 5431: { 5432: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 5433: abort (); 5434: 5435: operands[0] = XEXP (operands[0], 0); 5436: if (GET_CODE (operands[0]) != SYMBOL_REF) 5437: { 1.1.1.4 ! root 5438: #ifndef USING_SVR4_H ! 5439: /* AIX function pointers are really pointers to a three word area */ 1.1 root 5440: rtx temp = gen_reg_rtx (SImode); 5441: 5442: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); 5443: operands[0] = temp; 1.1.1.4 ! root 5444: #endif /* !USING_SVR4_H */ 1.1 root 5445: } 5446: }") 5447: 5448: (define_expand "call_value" 5449: [(parallel [(set (match_operand 0 "" "") 5450: (call (mem:SI (match_operand:SI 1 "address_operand" "")) 5451: (match_operand 2 "" ""))) 1.1.1.4 ! root 5452: (use (match_operand 3 "" "")) 1.1 root 5453: (clobber (scratch:SI))])] 5454: "" 5455: " 5456: { 5457: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 5458: abort (); 5459: 5460: operands[1] = XEXP (operands[1], 0); 5461: if (GET_CODE (operands[1]) != SYMBOL_REF) 5462: { 1.1.1.4 ! root 5463: #ifndef USING_SVR4_H ! 5464: /* AIX function pointers are really pointers to a three word area */ 1.1 root 5465: rtx temp = gen_reg_rtx (SImode); 5466: 5467: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); 5468: operands[1] = temp; 1.1.1.4 ! root 5469: #endif /* !USING_SVR4_H */ 1.1 root 5470: } 5471: }") 5472: 1.1.1.2 root 5473: ;; Call to function in current module. No TOC pointer reload needed. 1.1.1.4 ! root 5474: ;; Operand2 is non-zero if we are using the V.4 calling sequence and ! 5475: ;; either the function was not prototyped, or it was prototyped as a ! 5476: ;; variable argument function. It is > 0 if FP registers were passed ! 5477: ;; and < 0 if they were not. 1.1.1.2 root 5478: 5479: (define_insn "" 1.1.1.4 ! root 5480: [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) ! 5481: (match_operand 1 "" "g,g")) ! 5482: (use (match_operand:SI 2 "immediate_operand" "O,n")) ! 5483: (clobber (match_scratch:SI 3 "=l,l"))] 1.1.1.2 root 5484: "" 1.1.1.4 ! root 5485: "* ! 5486: { ! 5487: if (INTVAL (operands[2]) > 0) ! 5488: return \"creqv 6,6,6\;bl %z0\"; ! 5489: ! 5490: else if (INTVAL (operands[2]) < 0) ! 5491: return \"crxor 6,6,6\;bl %z0\"; ! 5492: ! 5493: return \"bl %z0\"; ! 5494: }" ! 5495: [(set_attr "length" "4,8")]) 1.1.1.2 root 5496: 5497: ;; Call to function which may be in another module. Restore the TOC 1.1.1.4 ! root 5498: ;; pointer (r2) after the call unless this is System V. ! 5499: ;; Operand2 is non-zero if we are using the V.4 calling sequence and ! 5500: ;; either the function was not prototyped, or it was prototyped as a ! 5501: ;; variable argument function. It is > 0 if FP registers were passed ! 5502: ;; and < 0 if they were not. 1.1.1.2 root 5503: 1.1 root 5504: (define_insn "" 1.1.1.4 ! root 5505: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s,l,s")) ! 5506: (match_operand 1 "" "fg,fg,fg,fg")) ! 5507: (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) ! 5508: (clobber (match_scratch:SI 3 "=l,l,l,l"))] 1.1 root 5509: "" 1.1.1.4 ! root 5510: "* ! 5511: { ! 5512: if (INTVAL (operands[2]) > 0) ! 5513: output_asm_insn (\"creqv 6,6,6\", operands); ! 5514: ! 5515: else if (INTVAL (operands[2]) < 0) ! 5516: output_asm_insn (\"crxor 6,6,6\", operands); ! 5517: ! 5518: #ifndef USING_SVR4_H ! 5519: if (GET_CODE (operands[0]) == REG) ! 5520: return \"{brl|blrl}\;{l|lwz} 2,20(1)\"; ! 5521: ! 5522: return \"bl %z0\;%.\"; ! 5523: ! 5524: #else ! 5525: if (GET_CODE (operands[0]) == REG) ! 5526: return \"{brl|blrl}\"; ! 5527: ! 5528: return \"bl %z0\"; ! 5529: #endif ! 5530: }" ! 5531: [(set_attr "length" "8,8,12,12")]) 1.1.1.2 root 5532: 5533: (define_insn "" 1.1.1.4 ! root 5534: [(set (match_operand 0 "" "=fg,fg") ! 5535: (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) ! 5536: (match_operand 2 "" "g,g"))) ! 5537: (use (match_operand:SI 3 "immediate_operand" "O,n")) ! 5538: (clobber (match_scratch:SI 4 "=l,l"))] 1.1.1.2 root 5539: "" 1.1.1.4 ! root 5540: "* ! 5541: { ! 5542: if (INTVAL (operands[3]) > 0) ! 5543: return \"creqv 6,6,6\;bl %z1\"; ! 5544: ! 5545: else if (INTVAL (operands[3]) < 0) ! 5546: return \"crxor 6,6,6\;bl %z1\"; ! 5547: ! 5548: return \"bl %z1\"; ! 5549: }" ! 5550: [(set_attr "length" "4,8")]) 1.1 root 5551: 5552: (define_insn "" 1.1.1.4 ! root 5553: [(set (match_operand 0 "" "=fg,fg,fg,fg") ! 5554: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s,l,s")) ! 5555: (match_operand 2 "" "fg,fg,fg,fg"))) ! 5556: (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) ! 5557: (clobber (match_scratch:SI 4 "=l,l,l,l"))] 1.1 root 5558: "" 1.1.1.4 ! root 5559: "* ! 5560: { ! 5561: if (INTVAL (operands[3]) > 0) ! 5562: output_asm_insn (\"creqv 6,6,6\", operands); ! 5563: ! 5564: else if (INTVAL (operands[3]) < 0) ! 5565: output_asm_insn (\"crxor 6,6,6\", operands); ! 5566: ! 5567: #ifndef USING_SVR4_H ! 5568: if (GET_CODE (operands[1]) == REG) ! 5569: return \"{brl|blrl}\;{l|lwz} 2,20(1)\"; ! 5570: ! 5571: return \"bl %z1\;%.\"; ! 5572: ! 5573: #else ! 5574: if (GET_CODE (operands[1]) == REG) ! 5575: return \"{brl|blrl}\"; ! 5576: ! 5577: return \"bl %z1\"; ! 5578: #endif ! 5579: }" ! 5580: [(set_attr "length" "8,8,12,12")]) 1.1 root 5581: 5582: ;; Call subroutine returning any type. 5583: 5584: (define_expand "untyped_call" 5585: [(parallel [(call (match_operand 0 "" "") 5586: (const_int 0)) 5587: (match_operand 1 "" "") 5588: (match_operand 2 "" "")])] 5589: "" 5590: " 5591: { 5592: int i; 5593: 1.1.1.4 ! root 5594: emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); 1.1 root 5595: 5596: for (i = 0; i < XVECLEN (operands[2], 0); i++) 5597: { 5598: rtx set = XVECEXP (operands[2], 0, i); 5599: emit_move_insn (SET_DEST (set), SET_SRC (set)); 5600: } 5601: 5602: /* The optimizer does not know that the call sets the function value 5603: registers we stored in the result block. We avoid problems by 5604: claiming that all hard registers are used and clobbered at this 5605: point. */ 5606: emit_insn (gen_blockage ()); 5607: 5608: DONE; 5609: }") 5610: 5611: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 5612: ;; all of memory. This blocks insns from being moved across this point. 5613: 5614: (define_insn "blockage" 5615: [(unspec_volatile [(const_int 0)] 0)] 5616: "" 5617: "") 1.1.1.4 ! root 5618: ! 5619: ;; Synchronize instruction/data caches for V.4 trampolines ! 5620: (define_insn "sync_isync" ! 5621: [(unspec [(match_operand 0 "memory_operand" "=m")] 1)] ! 5622: "" ! 5623: "{dcs|sync}\;{ics|isync}" ! 5624: [(set_attr "length" "8")]) ! 5625: 1.1 root 5626: 5627: ;; Compare insns are next. Note that the RS/6000 has two types of compares, 1.1.1.4 ! root 5628: ;; signed & unsigned, and one type of branch. 1.1 root 5629: ;; 5630: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 5631: ;; insns, and branches. We store the operands of compares until we see 5632: ;; how it is used. 5633: (define_expand "cmpsi" 5634: [(set (cc0) 5635: (compare (match_operand:SI 0 "gpc_reg_operand" "") 5636: (match_operand:SI 1 "reg_or_short_operand" "")))] 5637: "" 5638: " 5639: { 5640: /* Take care of the possibility that operands[1] might be negative but 5641: this might be a logical operation. That insn doesn't exist. */ 5642: if (GET_CODE (operands[1]) == CONST_INT 5643: && INTVAL (operands[1]) < 0) 5644: operands[1] = force_reg (SImode, operands[1]); 5645: 5646: rs6000_compare_op0 = operands[0]; 5647: rs6000_compare_op1 = operands[1]; 5648: rs6000_compare_fp_p = 0; 5649: DONE; 5650: }") 5651: 5652: (define_expand "cmpsf" 5653: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") 5654: (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.4 ! root 5655: "TARGET_HARD_FLOAT" 1.1 root 5656: " 5657: { 5658: rs6000_compare_op0 = operands[0]; 5659: rs6000_compare_op1 = operands[1]; 5660: rs6000_compare_fp_p = 1; 5661: DONE; 5662: }") 5663: 5664: (define_expand "cmpdf" 5665: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") 5666: (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 ! root 5667: "TARGET_HARD_FLOAT" 1.1 root 5668: " 5669: { 5670: rs6000_compare_op0 = operands[0]; 5671: rs6000_compare_op1 = operands[1]; 5672: rs6000_compare_fp_p = 1; 5673: DONE; 5674: }") 5675: 5676: (define_expand "beq" 5677: [(set (match_dup 2) (match_dup 1)) 5678: (set (pc) 5679: (if_then_else (eq (match_dup 2) 5680: (const_int 0)) 5681: (label_ref (match_operand 0 "" "")) 5682: (pc)))] 5683: "" 5684: " 5685: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5686: operands[1] = gen_rtx (COMPARE, mode, 5687: rs6000_compare_op0, rs6000_compare_op1); 5688: operands[2] = gen_reg_rtx (mode); 5689: }") 5690: 5691: (define_expand "bne" 5692: [(set (match_dup 2) (match_dup 1)) 5693: (set (pc) 5694: (if_then_else (ne (match_dup 2) 5695: (const_int 0)) 5696: (label_ref (match_operand 0 "" "")) 5697: (pc)))] 5698: "" 5699: " 5700: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5701: operands[1] = gen_rtx (COMPARE, mode, 5702: rs6000_compare_op0, rs6000_compare_op1); 5703: operands[2] = gen_reg_rtx (mode); 5704: }") 5705: 5706: (define_expand "blt" 5707: [(set (match_dup 2) (match_dup 1)) 5708: (set (pc) 5709: (if_then_else (lt (match_dup 2) 5710: (const_int 0)) 5711: (label_ref (match_operand 0 "" "")) 5712: (pc)))] 5713: "" 5714: " 5715: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5716: operands[1] = gen_rtx (COMPARE, mode, 5717: rs6000_compare_op0, rs6000_compare_op1); 5718: operands[2] = gen_reg_rtx (mode); 5719: }") 5720: 5721: (define_expand "bgt" 5722: [(set (match_dup 2) (match_dup 1)) 5723: (set (pc) 5724: (if_then_else (gt (match_dup 2) 5725: (const_int 0)) 5726: (label_ref (match_operand 0 "" "")) 5727: (pc)))] 5728: "" 5729: " 5730: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5731: operands[1] = gen_rtx (COMPARE, mode, 5732: rs6000_compare_op0, rs6000_compare_op1); 5733: operands[2] = gen_reg_rtx (mode); 5734: }") 5735: 5736: (define_expand "ble" 5737: [(set (match_dup 2) (match_dup 1)) 5738: (set (pc) 5739: (if_then_else (le (match_dup 2) 5740: (const_int 0)) 5741: (label_ref (match_operand 0 "" "")) 5742: (pc)))] 5743: "" 5744: " 5745: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5746: operands[1] = gen_rtx (COMPARE, mode, 5747: rs6000_compare_op0, rs6000_compare_op1); 5748: operands[2] = gen_reg_rtx (mode); 5749: }") 5750: 5751: (define_expand "bge" 5752: [(set (match_dup 2) (match_dup 1)) 5753: (set (pc) 5754: (if_then_else (ge (match_dup 2) 5755: (const_int 0)) 5756: (label_ref (match_operand 0 "" "")) 5757: (pc)))] 5758: "" 5759: " 5760: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5761: operands[1] = gen_rtx (COMPARE, mode, 5762: rs6000_compare_op0, rs6000_compare_op1); 5763: operands[2] = gen_reg_rtx (mode); 5764: }") 5765: 5766: (define_expand "bgtu" 5767: [(set (match_dup 2) (match_dup 1)) 5768: (set (pc) 5769: (if_then_else (gtu (match_dup 2) 5770: (const_int 0)) 5771: (label_ref (match_operand 0 "" "")) 5772: (pc)))] 5773: "" 5774: " 5775: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5776: rs6000_compare_op0, rs6000_compare_op1); 5777: operands[2] = gen_reg_rtx (CCUNSmode); 5778: }") 5779: 5780: (define_expand "bltu" 5781: [(set (match_dup 2) (match_dup 1)) 5782: (set (pc) 5783: (if_then_else (ltu (match_dup 2) 5784: (const_int 0)) 5785: (label_ref (match_operand 0 "" "")) 5786: (pc)))] 5787: "" 5788: " 5789: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5790: rs6000_compare_op0, rs6000_compare_op1); 5791: operands[2] = gen_reg_rtx (CCUNSmode); 5792: }") 5793: 5794: (define_expand "bgeu" 5795: [(set (match_dup 2) (match_dup 1)) 5796: (set (pc) 5797: (if_then_else (geu (match_dup 2) 5798: (const_int 0)) 5799: (label_ref (match_operand 0 "" "")) 5800: (pc)))] 5801: "" 5802: " 5803: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5804: rs6000_compare_op0, rs6000_compare_op1); 5805: operands[2] = gen_reg_rtx (CCUNSmode); 5806: }") 5807: 5808: (define_expand "bleu" 5809: [(set (match_dup 2) (match_dup 1)) 5810: (set (pc) 5811: (if_then_else (leu (match_dup 2) 5812: (const_int 0)) 5813: (label_ref (match_operand 0 "" "")) 5814: (pc)))] 5815: "" 5816: " 5817: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5818: rs6000_compare_op0, rs6000_compare_op1); 5819: operands[2] = gen_reg_rtx (CCUNSmode); 5820: }") 5821: 5822: ;; For SNE, we would prefer that the xor/abs sequence be used for integers. 5823: ;; For SEQ, likewise, except that comparisons with zero should be done 5824: ;; with an scc insns. However, due to the order that combine see the 5825: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 5826: ;; the cases we don't want to handle. 5827: (define_expand "seq" 5828: [(set (match_dup 2) (match_dup 1)) 5829: (set (match_operand:SI 0 "gpc_reg_operand" "") 5830: (eq:SI (match_dup 2) (const_int 0)))] 5831: "" 5832: " 5833: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5834: operands[1] = gen_rtx (COMPARE, mode, 5835: rs6000_compare_op0, rs6000_compare_op1); 5836: operands[2] = gen_reg_rtx (mode); 5837: }") 5838: 5839: (define_expand "sne" 5840: [(set (match_dup 2) (match_dup 1)) 5841: (set (match_operand:SI 0 "gpc_reg_operand" "") 5842: (ne:SI (match_dup 2) (const_int 0)))] 5843: "" 5844: " 5845: { if (! rs6000_compare_fp_p) 5846: FAIL; 5847: 5848: operands[1] = gen_rtx (COMPARE, CCFPmode, 5849: rs6000_compare_op0, rs6000_compare_op1); 5850: operands[2] = gen_reg_rtx (CCFPmode); 5851: }") 5852: 5853: ;; A > 0 is best done using the portable sequence, so fail in that case. 5854: (define_expand "sgt" 5855: [(set (match_dup 2) (match_dup 1)) 5856: (set (match_operand:SI 0 "gpc_reg_operand" "") 5857: (gt:SI (match_dup 2) (const_int 0)))] 5858: "" 5859: " 5860: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5861: 5862: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5863: FAIL; 5864: 5865: operands[1] = gen_rtx (COMPARE, mode, 5866: rs6000_compare_op0, rs6000_compare_op1); 5867: operands[2] = gen_reg_rtx (mode); 5868: }") 5869: 5870: ;; A < 0 is best done in the portable way for A an integer. 5871: (define_expand "slt" 5872: [(set (match_dup 2) (match_dup 1)) 5873: (set (match_operand:SI 0 "gpc_reg_operand" "") 5874: (lt:SI (match_dup 2) (const_int 0)))] 5875: "" 5876: " 5877: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5878: 5879: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5880: FAIL; 5881: 5882: operands[1] = gen_rtx (COMPARE, mode, 5883: rs6000_compare_op0, rs6000_compare_op1); 5884: operands[2] = gen_reg_rtx (mode); 5885: }") 5886: 5887: (define_expand "sge" 5888: [(set (match_dup 2) (match_dup 1)) 5889: (set (match_operand:SI 0 "gpc_reg_operand" "") 5890: (ge:SI (match_dup 2) (const_int 0)))] 5891: "" 5892: " 5893: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5894: operands[1] = gen_rtx (COMPARE, mode, 5895: rs6000_compare_op0, rs6000_compare_op1); 5896: operands[2] = gen_reg_rtx (mode); 5897: }") 5898: 5899: ;; A <= 0 is best done the portable way for A an integer. 5900: (define_expand "sle" 5901: [(set (match_dup 2) (match_dup 1)) 5902: (set (match_operand:SI 0 "gpc_reg_operand" "") 5903: (le:SI (match_dup 2) (const_int 0)))] 5904: "" 5905: " 5906: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5907: 5908: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5909: FAIL; 5910: 5911: operands[1] = gen_rtx (COMPARE, mode, 5912: rs6000_compare_op0, rs6000_compare_op1); 5913: operands[2] = gen_reg_rtx (mode); 5914: }") 5915: 5916: (define_expand "sgtu" 5917: [(set (match_dup 2) (match_dup 1)) 5918: (set (match_operand:SI 0 "gpc_reg_operand" "") 5919: (gtu:SI (match_dup 2) (const_int 0)))] 5920: "" 5921: " 5922: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5923: rs6000_compare_op0, rs6000_compare_op1); 5924: operands[2] = gen_reg_rtx (CCUNSmode); 5925: }") 5926: 5927: (define_expand "sltu" 5928: [(set (match_dup 2) (match_dup 1)) 5929: (set (match_operand:SI 0 "gpc_reg_operand" "") 5930: (ltu:SI (match_dup 2) (const_int 0)))] 5931: "" 5932: " 5933: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5934: rs6000_compare_op0, rs6000_compare_op1); 5935: operands[2] = gen_reg_rtx (CCUNSmode); 5936: }") 5937: 5938: (define_expand "sgeu" 5939: [(set (match_dup 2) (match_dup 1)) 5940: (set (match_operand:SI 0 "gpc_reg_operand" "") 5941: (geu:SI (match_dup 2) (const_int 0)))] 5942: "" 5943: " 5944: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5945: rs6000_compare_op0, rs6000_compare_op1); 5946: operands[2] = gen_reg_rtx (CCUNSmode); 5947: }") 5948: 5949: (define_expand "sleu" 5950: [(set (match_dup 2) (match_dup 1)) 5951: (set (match_operand:SI 0 "gpc_reg_operand" "") 5952: (leu:SI (match_dup 2) (const_int 0)))] 5953: "" 5954: " 5955: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5956: rs6000_compare_op0, rs6000_compare_op1); 5957: operands[2] = gen_reg_rtx (CCUNSmode); 5958: }") 5959: 5960: ;; Here are the actual compare insns. 5961: (define_insn "" 5962: [(set (match_operand:CC 0 "cc_reg_operand" "=y") 5963: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 5964: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 5965: "" 1.1.1.2 root 5966: "{cmp%I2|cmpw%I2} %0,%1,%2" 1.1 root 5967: [(set_attr "type" "compare")]) 5968: 5969: ;; If we are comparing a register for equality with a large constant, 5970: ;; we can do this with an XOR followed by a compare. But we need a scratch 5971: ;; register for the result of the XOR. 5972: 5973: (define_split 5974: [(set (match_operand:CC 0 "cc_reg_operand" "") 5975: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 5976: (match_operand:SI 2 "non_short_cint_operand" ""))) 5977: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 5978: "find_single_use (operands[0], insn, 0) 5979: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 5980: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 5981: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 5982: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 5983: " 5984: { 5985: /* Get the constant we are comparing against, C, and see what it looks like 5986: sign-extended to 16 bits. Then see what constant could be XOR'ed 5987: with C to get the sign-extended value. */ 5988: 5989: int c = INTVAL (operands[2]); 5990: int sextc = (c << 16) >> 16; 5991: int xorv = c ^ sextc; 5992: 5993: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); 5994: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); 5995: }") 5996: 5997: (define_insn "" 5998: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 5999: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 6000: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] 6001: "" 1.1.1.2 root 6002: "{cmpl%I2|cmplw%I2} %0,%1,%W2" 1.1 root 6003: [(set_attr "type" "compare")]) 6004: 6005: ;; The following two insns don't exist as single insns, but if we provide 6006: ;; them, we can swap an add and compare, which will enable us to overlap more 6007: ;; of the required delay between a compare and branch. We generate code for 6008: ;; them by splitting. 6009: 6010: (define_insn "" 6011: [(set (match_operand:CC 3 "cc_reg_operand" "=y") 6012: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 6013: (match_operand:SI 2 "short_cint_operand" "i"))) 6014: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6015: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 6016: "" 1.1.1.2 root 6017: "#" 6018: [(set_attr "length" "8")]) 1.1.1.4 ! root 6019: 1.1 root 6020: (define_insn "" 6021: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 6022: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 6023: (match_operand:SI 2 "u_short_cint_operand" "i"))) 6024: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6025: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 6026: "" 1.1.1.2 root 6027: "#" 6028: [(set_attr "length" "8")]) 1.1.1.4 ! root 6029: 1.1 root 6030: (define_split 6031: [(set (match_operand:CC 3 "cc_reg_operand" "") 6032: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 6033: (match_operand:SI 2 "short_cint_operand" ""))) 6034: (set (match_operand:SI 0 "gpc_reg_operand" "") 6035: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 6036: "" 6037: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 6038: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 6039: 6040: (define_split 6041: [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 6042: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 6043: (match_operand:SI 2 "u_short_cint_operand" ""))) 6044: (set (match_operand:SI 0 "gpc_reg_operand" "") 6045: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 6046: "" 6047: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 6048: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 6049: 6050: (define_insn "" 6051: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 6052: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 6053: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 6054: "TARGET_HARD_FLOAT" 1.1 root 6055: "fcmpu %0,%1,%2" 6056: [(set_attr "type" "fpcompare")]) 6057: 6058: (define_insn "" 6059: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 6060: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 6061: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 ! root 6062: "TARGET_HARD_FLOAT" 1.1 root 6063: "fcmpu %0,%1,%2" 6064: [(set_attr "type" "fpcompare")]) 6065: 6066: ;; Now we have the scc insns. We can do some combinations because of the 6067: ;; way the machine works. 6068: ;; 6069: ;; Note that this is probably faster if we can put an insn between the 6070: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 6071: ;; cases the insns below which don't use an intermediate CR field will 6072: ;; be used instead. 6073: (define_insn "" 6074: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6075: (match_operator:SI 1 "scc_comparison_operator" 6076: [(match_operand 2 "cc_reg_operand" "y") 6077: (const_int 0)]))] 6078: "" 1.1.1.2 root 6079: "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" 6080: [(set_attr "length" "12")]) 1.1 root 6081: 6082: (define_insn "" 6083: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6084: (compare:CC (match_operator:SI 1 "scc_comparison_operator" 6085: [(match_operand 2 "cc_reg_operand" "y") 6086: (const_int 0)]) 6087: (const_int 0))) 6088: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 6089: (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 6090: "" 1.1.1.2 root 6091: "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" 6092: [(set_attr "type" "delayed_compare") 6093: (set_attr "length" "12")]) 1.1 root 6094: 6095: (define_insn "" 6096: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6097: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 6098: [(match_operand 2 "cc_reg_operand" "y") 6099: (const_int 0)]) 6100: (match_operand:SI 3 "const_int_operand" "n")))] 6101: "" 6102: "* 6103: { 6104: int is_bit = ccr_bit (operands[1], 1); 6105: int put_bit = 31 - (INTVAL (operands[3]) & 31); 6106: int count; 6107: 6108: if (is_bit >= put_bit) 6109: count = is_bit - put_bit; 6110: else 6111: count = 32 - (put_bit - is_bit); 6112: 6113: operands[4] = gen_rtx (CONST_INT, VOIDmode, count); 6114: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); 6115: 1.1.1.2 root 6116: return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 6117: }" 6118: [(set_attr "length" "12")]) 1.1 root 6119: 6120: (define_insn "" 6121: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6122: (compare:CC 6123: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 6124: [(match_operand 2 "cc_reg_operand" "y") 6125: (const_int 0)]) 6126: (match_operand:SI 3 "const_int_operand" "n")) 6127: (const_int 0))) 6128: (set (match_operand:SI 4 "gpc_reg_operand" "=r") 6129: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 6130: (match_dup 3)))] 6131: "" 6132: "* 6133: { 6134: int is_bit = ccr_bit (operands[1], 1); 6135: int put_bit = 31 - (INTVAL (operands[3]) & 31); 6136: int count; 6137: 6138: if (is_bit >= put_bit) 6139: count = is_bit - put_bit; 6140: else 6141: count = 32 - (put_bit - is_bit); 6142: 6143: operands[5] = gen_rtx (CONST_INT, VOIDmode, count); 6144: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); 6145: 1.1.1.2 root 6146: return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 1.1 root 6147: }" 1.1.1.2 root 6148: [(set_attr "type" "delayed_compare") 6149: (set_attr "length" "12")]) 1.1 root 6150: 6151: ;; If we are comparing the result of two comparisons, this can be done 6152: ;; using creqv or crxor. 6153: 6154: (define_insn "" 6155: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 6156: (compare:CCEQ (match_operator 1 "scc_comparison_operator" 6157: [(match_operand 2 "cc_reg_operand" "y") 6158: (const_int 0)]) 6159: (match_operator 3 "scc_comparison_operator" 6160: [(match_operand 4 "cc_reg_operand" "y") 6161: (const_int 0)])))] 6162: "REGNO (operands[2]) != REGNO (operands[4])" 6163: "* 6164: { 6165: enum rtx_code code1, code2; 6166: 6167: code1 = GET_CODE (operands[1]); 6168: code2 = GET_CODE (operands[3]); 6169: 6170: if ((code1 == EQ || code1 == LT || code1 == GT 6171: || code1 == LTU || code1 == GTU 6172: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) 6173: != 6174: (code2 == EQ || code2 == LT || code2 == GT 6175: || code2 == LTU || code2 == GTU 6176: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) 6177: return \"%C1%C3crxor %E0,%j1,%j3\"; 6178: else 6179: return \"%C1%C3creqv %E0,%j1,%j3\"; 1.1.1.2 root 6180: }" 6181: [(set_attr "length" "12")]) 1.1 root 6182: 6183: ;; There is a 3 cycle delay between consecutive mfcr instructions 6184: ;; so it is useful to combine 2 scc instructions to use only one mfcr. 6185: 6186: (define_peephole 6187: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6188: (match_operator:SI 1 "scc_comparison_operator" 6189: [(match_operand 2 "cc_reg_operand" "y") 6190: (const_int 0)])) 6191: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 6192: (match_operator:SI 4 "scc_comparison_operator" 6193: [(match_operand 5 "cc_reg_operand" "y") 6194: (const_int 0)]))] 6195: "REGNO (operands[2]) != REGNO (operands[5])" 1.1.1.2 root 6196: "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 6197: [(set_attr "length" "20")]) 1.1 root 6198: 6199: ;; There are some scc insns that can be done directly, without a compare. 6200: ;; These are faster because they don't involve the communications between 6201: ;; the FXU and branch units. In fact, we will be replacing all of the 6202: ;; integer scc insns here or in the portable methods in emit_store_flag. 6203: ;; 6204: ;; Also support (neg (scc ..)) since that construct is used to replace 6205: ;; branches, (plus (scc ..) ..) since that construct is common and 6206: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 6207: ;; cases where it is no more expensive than (neg (scc ..)). 6208: 6209: ;; Have reload force a constant into a register for the simple insns that 6210: ;; otherwise won't accept constants. We do this because it is faster than 6211: ;; the cmp/mfcr sequence we would otherwise generate. 6212: 6213: (define_insn "" 6214: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6215: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6216: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) 6217: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 6218: "" 6219: "@ 1.1.1.2 root 6220: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6221: {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 6222: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6223: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6224: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 6225: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6226: 6227: (define_insn "" 6228: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 ! root 6229: (compare:CC 1.1 root 6230: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6231: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6232: (const_int 0))) 6233: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6234: (eq:SI (match_dup 1) (match_dup 2))) 6235: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 6236: "" 6237: "@ 1.1.1.2 root 6238: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6239: {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 6240: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6241: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6242: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" 6243: [(set_attr "type" "compare") 6244: (set_attr "length" "12,8,12,12,12")]) 6245: 6246: ;; We have insns of the form shown by the first define_insn below. If 6247: ;; there is something inside the comparison operation, we must split it. 6248: (define_split 6249: [(set (match_operand:SI 0 "gpc_reg_operand" "") 6250: (plus:SI (match_operator 1 "comparison_operator" 6251: [(match_operand:SI 2 "" "") 6252: (match_operand:SI 3 6253: "reg_or_cint_operand" "")]) 6254: (match_operand:SI 4 "gpc_reg_operand" ""))) 6255: (clobber (match_operand:SI 5 "register_operand" ""))] 6256: "! gpc_reg_operand (operands[2], SImode)" 6257: [(set (match_dup 5) (match_dup 2)) 6258: (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 6259: (match_dup 4)))]) 1.1 root 6260: 6261: (define_insn "" 6262: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6263: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6264: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6265: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) 6266: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6267: "" 6268: "@ 1.1.1.2 root 6269: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6270: {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 6271: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6272: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6273: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 6274: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6275: 6276: (define_insn "" 6277: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 ! root 6278: (compare:CC 1.1 root 6279: (plus:SI 6280: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6281: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6282: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 6283: (const_int 0))) 6284: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6285: "" 6286: "@ 1.1.1.2 root 6287: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6288: {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 6289: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6290: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6291: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 6292: [(set_attr "type" "compare") 6293: (set_attr "length" "12,8,12,12,12")]) 1.1 root 6294: 6295: (define_insn "" 6296: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 ! root 6297: (compare:CC 1.1 root 6298: (plus:SI 6299: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6300: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6301: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 6302: (const_int 0))) 6303: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6304: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6305: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6306: "" 6307: "@ 1.1.1.2 root 6308: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6309: {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 6310: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6311: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6312: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 6313: [(set_attr "type" "compare") 6314: (set_attr "length" "12,8,12,12,12")]) 1.1 root 6315: 6316: (define_insn "" 6317: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 1.1.1.3 root 6318: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 1.1 root 6319: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] 6320: "" 6321: "@ 1.1.1.2 root 6322: xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6323: {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 6324: {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6325: {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6326: {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 6327: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6328: 1.1.1.4 ! root 6329: ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, ! 6330: ;; since it nabs/sr is just as fast. ! 6331: (define_insn "" ! 6332: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 6333: (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 6334: (const_int 31))) ! 6335: (clobber (match_scratch:SI 2 "=&r"))] ! 6336: "!TARGET_POWER" ! 6337: "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" ! 6338: [(set_attr "length" "8")]) ! 6339: 1.1 root 6340: ;; This is what (plus (ne X (const_int 0)) Y) looks like. 6341: (define_insn "" 6342: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6343: (plus:SI (lshiftrt:SI 6344: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6345: (const_int 31)) 6346: (match_operand:SI 2 "gpc_reg_operand" "r"))) 6347: (clobber (match_scratch:SI 3 "=&r"))] 6348: "" 1.1.1.2 root 6349: "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 6350: [(set_attr "length" "8")]) 1.1 root 6351: 6352: (define_insn "" 6353: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6354: (compare:CC 6355: (plus:SI (lshiftrt:SI 6356: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6357: (const_int 31)) 6358: (match_operand:SI 2 "gpc_reg_operand" "r")) 6359: (const_int 0))) 6360: (clobber (match_scratch:SI 3 "=&r"))] 6361: "" 1.1.1.2 root 6362: "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" 6363: [(set_attr "type" "compare") 6364: (set_attr "length" "8")]) 1.1 root 6365: 6366: (define_insn "" 6367: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6368: (compare:CC 6369: (plus:SI (lshiftrt:SI 6370: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6371: (const_int 31)) 6372: (match_operand:SI 2 "gpc_reg_operand" "r")) 6373: (const_int 0))) 6374: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6375: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 6376: (match_dup 2))) 6377: (clobber (match_scratch:SI 3 "=&r"))] 6378: "" 1.1.1.2 root 6379: "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" 6380: [(set_attr "type" "compare") 6381: (set_attr "length" "8")]) 1.1 root 6382: 6383: (define_insn "" 6384: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6385: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6386: (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 6387: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 6388: "TARGET_POWER" 1.1 root 6389: "@ 1.1.1.2 root 6390: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 6391: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 6392: [(set_attr "length" "12")]) 1.1 root 6393: 6394: (define_insn "" 6395: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") 6396: (compare:CC 6397: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6398: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6399: (const_int 0))) 6400: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6401: (le:SI (match_dup 1) (match_dup 2))) 6402: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 6403: "TARGET_POWER" 1.1 root 6404: "@ 1.1.1.2 root 6405: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 6406: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" 1.1.1.3 root 6407: [(set_attr "type" "compare,delayed_compare") 1.1.1.2 root 6408: (set_attr "length" "12")]) 1.1 root 6409: 6410: (define_insn "" 6411: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6412: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6413: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6414: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6415: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6416: "TARGET_POWER" 1.1 root 6417: "@ 1.1.1.2 root 6418: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6419: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" 6420: [(set_attr "length" "12")]) 1.1 root 6421: 6422: (define_insn "" 6423: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6424: (compare:CC 6425: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6426: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6427: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6428: (const_int 0))) 6429: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6430: "TARGET_POWER" 1.1 root 6431: "@ 1.1.1.2 root 6432: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6433: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" 6434: [(set_attr "type" "compare") 6435: (set_attr "length" "12")]) 1.1 root 6436: 6437: (define_insn "" 6438: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6439: (compare:CC 6440: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6441: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6442: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6443: (const_int 0))) 6444: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6445: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6446: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6447: "TARGET_POWER" 1.1 root 6448: "@ 1.1.1.2 root 6449: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6450: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" 6451: [(set_attr "type" "compare") 6452: (set_attr "length" "12")]) 1.1 root 6453: 6454: (define_insn "" 6455: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6456: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6457: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 1.1.1.2 root 6458: "TARGET_POWER" 1.1 root 6459: "@ 1.1.1.2 root 6460: doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6461: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 6462: [(set_attr "length" "12")]) 1.1 root 6463: 6464: (define_insn "" 6465: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6466: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6467: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 6468: "" 1.1.1.2 root 6469: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 6470: [(set_attr "length" "12")]) 1.1 root 6471: 6472: (define_insn "" 6473: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 6474: (compare:CC 6475: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6476: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6477: (const_int 0))) 6478: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6479: (leu:SI (match_dup 1) (match_dup 2)))] 6480: "" 1.1.1.2 root 6481: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 6482: [(set_attr "type" "compare") 6483: (set_attr "length" "12")]) 1.1 root 6484: 6485: (define_insn "" 6486: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6487: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6488: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6489: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6490: (clobber (match_scratch:SI 4 "=&r"))] 6491: "" 1.1.1.2 root 6492: "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" 6493: [(set_attr "length" "8")]) 1.1 root 6494: 6495: (define_insn "" 6496: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6497: (compare:CC 6498: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6499: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6500: (match_operand:SI 3 "gpc_reg_operand" "r")) 6501: (const_int 0))) 6502: (clobber (match_scratch:SI 4 "=&r"))] 6503: "" 1.1.1.2 root 6504: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" 6505: [(set_attr "type" "compare") 6506: (set_attr "length" "8")]) 1.1 root 6507: 6508: (define_insn "" 6509: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6510: (compare:CC 6511: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6512: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6513: (match_operand:SI 3 "gpc_reg_operand" "r")) 6514: (const_int 0))) 6515: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6516: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6517: (clobber (match_scratch:SI 4 "=&r"))] 6518: "" 1.1.1.2 root 6519: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" 6520: [(set_attr "type" "compare") 6521: (set_attr "length" "8")]) 1.1 root 6522: 6523: (define_insn "" 6524: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6525: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6526: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 6527: "" 1.1.1.2 root 6528: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 6529: [(set_attr "length" "12")]) 1.1 root 6530: 6531: (define_insn "" 6532: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6533: (and:SI (neg:SI 6534: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6535: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6536: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6537: (clobber (match_scratch:SI 4 "=&r"))] 6538: "" 1.1.1.2 root 6539: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 6540: [(set_attr "length" "12")]) 1.1 root 6541: 6542: (define_insn "" 6543: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6544: (compare:CC 6545: (and:SI (neg:SI 6546: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6547: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6548: (match_operand:SI 3 "gpc_reg_operand" "r")) 6549: (const_int 0))) 6550: (clobber (match_scratch:SI 4 "=&r"))] 6551: "" 1.1.1.2 root 6552: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 6553: [(set_attr "type" "compare") 6554: (set_attr "length" "12")]) 1.1 root 6555: 6556: (define_insn "" 6557: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6558: (compare:CC 6559: (and:SI (neg:SI 6560: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6561: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6562: (match_operand:SI 3 "gpc_reg_operand" "r")) 6563: (const_int 0))) 6564: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6565: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 6566: (clobber (match_scratch:SI 4 "=&r"))] 6567: "" 1.1.1.2 root 6568: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 6569: [(set_attr "type" "compare") 6570: (set_attr "length" "12")]) 1.1 root 6571: 6572: (define_insn "" 6573: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6574: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6575: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 1.1.1.2 root 6576: "TARGET_POWER" 6577: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 6578: [(set_attr "length" "12")]) 1.1 root 6579: 6580: (define_insn "" 1.1.1.3 root 6581: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1 root 6582: (compare:CC 6583: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6584: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6585: (const_int 0))) 6586: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6587: (lt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 6588: "TARGET_POWER" 6589: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 6590: [(set_attr "type" "delayed_compare") 6591: (set_attr "length" "12")]) 1.1 root 6592: 6593: (define_insn "" 6594: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6595: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6596: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6597: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6598: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6599: "TARGET_POWER" 6600: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 6601: [(set_attr "length" "12")]) 1.1 root 6602: 6603: (define_insn "" 1.1.1.3 root 6604: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1 root 6605: (compare:CC 6606: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6607: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6608: (match_operand:SI 3 "gpc_reg_operand" "r")) 6609: (const_int 0))) 6610: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6611: "TARGET_POWER" 6612: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 6613: [(set_attr "type" "compare") 6614: (set_attr "length" "12")]) 1.1 root 6615: 6616: (define_insn "" 1.1.1.3 root 6617: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 1.1 root 6618: (compare:CC 6619: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6620: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6621: (match_operand:SI 3 "gpc_reg_operand" "r")) 6622: (const_int 0))) 6623: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6624: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6625: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6626: "TARGET_POWER" 6627: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 6628: [(set_attr "type" "compare") 6629: (set_attr "length" "12")]) 1.1 root 6630: 6631: (define_insn "" 6632: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6633: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6634: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 6635: "TARGET_POWER" 6636: "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 6637: [(set_attr "length" "12")]) 1.1 root 6638: 6639: (define_insn "" 6640: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6641: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6642: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 6643: "" 6644: "@ 1.1.1.2 root 6645: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 6646: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 6647: [(set_attr "length" "12")]) 1.1 root 6648: 6649: (define_insn "" 6650: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 6651: (compare:CC 6652: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6653: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6654: (const_int 0))) 6655: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6656: (ltu:SI (match_dup 1) (match_dup 2)))] 6657: "" 6658: "@ 1.1.1.2 root 6659: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 6660: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 6661: [(set_attr "type" "compare") 6662: (set_attr "length" "12")]) 1.1 root 6663: 6664: (define_insn "" 6665: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 6666: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 6667: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) 6668: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) 6669: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] 6670: "" 6671: "@ 1.1.1.2 root 6672: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6673: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6674: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6675: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 6676: [(set_attr "length" "12")]) 1.1 root 6677: 6678: (define_insn "" 1.1.1.2 root 6679: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 6680: (compare:CC 1.1.1.2 root 6681: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6682: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6683: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6684: (const_int 0))) 1.1.1.2 root 6685: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6686: "" 6687: "@ 1.1.1.2 root 6688: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 6689: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" 6690: [(set_attr "type" "compare") 6691: (set_attr "length" "12")]) 1.1 root 6692: 6693: (define_insn "" 1.1.1.2 root 6694: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 6695: (compare:CC 1.1.1.2 root 6696: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6697: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6698: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6699: (const_int 0))) 1.1.1.2 root 6700: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 6701: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 6702: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6703: "" 6704: "@ 1.1.1.2 root 6705: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 6706: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 6707: [(set_attr "type" "compare") 6708: (set_attr "length" "12")]) 1.1 root 6709: 6710: (define_insn "" 6711: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6712: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6713: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] 6714: "" 6715: "@ 1.1.1.2 root 6716: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 6717: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 6718: [(set_attr "length" "8")]) 1.1 root 6719: 6720: (define_insn "" 6721: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6722: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6723: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6724: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 6725: "TARGET_POWER" 6726: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 6727: [(set_attr "length" "12")]) 1.1 root 6728: 6729: (define_insn "" 6730: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6731: (compare:CC 6732: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6733: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6734: (const_int 0))) 6735: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6736: (ge:SI (match_dup 1) (match_dup 2))) 6737: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 6738: "TARGET_POWER" 6739: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" 6740: [(set_attr "type" "compare") 6741: (set_attr "length" "12")]) 1.1 root 6742: 6743: (define_insn "" 6744: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6745: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6746: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6747: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6748: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6749: "TARGET_POWER" 6750: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 6751: [(set_attr "length" "12")]) 1.1 root 6752: 6753: (define_insn "" 6754: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6755: (compare:CC 6756: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6757: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6758: (match_operand:SI 3 "gpc_reg_operand" "r")) 6759: (const_int 0))) 6760: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6761: "TARGET_POWER" 6762: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 6763: [(set_attr "type" "compare") 6764: (set_attr "length" "12")]) 1.1 root 6765: 6766: (define_insn "" 6767: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6768: (compare:CC 6769: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6770: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6771: (match_operand:SI 3 "gpc_reg_operand" "r")) 6772: (const_int 0))) 6773: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6774: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6775: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6776: "TARGET_POWER" 6777: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 6778: [(set_attr "type" "compare") 6779: (set_attr "length" "12")]) 1.1 root 6780: 6781: (define_insn "" 6782: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6783: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6784: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 6785: "TARGET_POWER" 6786: "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 6787: [(set_attr "length" "12")]) 1.1 root 6788: 6789: ;; This is (and (neg (ge X (const_int 0))) Y). 6790: (define_insn "" 6791: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6792: (and:SI (neg:SI 6793: (lshiftrt:SI 6794: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6795: (const_int 31))) 6796: (match_operand:SI 2 "gpc_reg_operand" "r"))) 6797: (clobber (match_scratch:SI 3 "=&r"))] 6798: "" 1.1.1.2 root 6799: "{srai|srawi} %3,%1,31\;andc %0,%2,%3" 6800: [(set_attr "length" "8")]) 1.1 root 6801: 6802: (define_insn "" 6803: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6804: (compare:CC 6805: (and:SI (neg:SI 6806: (lshiftrt:SI 6807: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6808: (const_int 31))) 6809: (match_operand:SI 2 "gpc_reg_operand" "r")) 6810: (const_int 0))) 6811: (clobber (match_scratch:SI 3 "=&r"))] 6812: "" 1.1.1.2 root 6813: "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" 6814: [(set_attr "type" "compare") 6815: (set_attr "length" "8")]) 1.1 root 6816: 6817: (define_insn "" 6818: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6819: (compare:CC 6820: (and:SI (neg:SI 6821: (lshiftrt:SI 6822: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6823: (const_int 31))) 6824: (match_operand:SI 2 "gpc_reg_operand" "r")) 6825: (const_int 0))) 6826: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6827: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) 6828: (const_int 31))) 6829: (match_dup 2))) 6830: (clobber (match_scratch:SI 3 "=&r"))] 6831: "" 1.1.1.2 root 6832: "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" 6833: [(set_attr "type" "compare") 6834: (set_attr "length" "8")]) 1.1 root 6835: 6836: (define_insn "" 6837: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6838: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6839: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 6840: "" 6841: "@ 1.1.1.2 root 6842: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 6843: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 6844: [(set_attr "length" "12")]) 1.1 root 6845: 6846: (define_insn "" 6847: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 6848: (compare:CC 6849: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6850: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6851: (const_int 0))) 6852: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6853: (geu:SI (match_dup 1) (match_dup 2)))] 6854: "" 6855: "@ 1.1.1.2 root 6856: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 6857: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 6858: [(set_attr "type" "compare") 6859: (set_attr "length" "12")]) 1.1 root 6860: 6861: (define_insn "" 6862: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6863: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6864: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6865: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6866: (clobber (match_scratch:SI 4 "=&r,&r"))] 6867: "" 6868: "@ 1.1.1.2 root 6869: {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 6870: {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" 6871: [(set_attr "length" "8")]) 1.1 root 6872: 6873: (define_insn "" 6874: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6875: (compare:CC 6876: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6877: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6878: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6879: (const_int 0))) 6880: (clobber (match_scratch:SI 4 "=&r,&r"))] 6881: "" 6882: "@ 1.1.1.2 root 6883: {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 6884: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 6885: [(set_attr "type" "compare") 6886: (set_attr "length" "8")]) 1.1 root 6887: 6888: (define_insn "" 6889: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6890: (compare:CC 6891: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6892: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6893: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6894: (const_int 0))) 6895: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6896: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6897: (clobber (match_scratch:SI 4 "=&r,&r"))] 6898: "" 6899: "@ 1.1.1.2 root 6900: {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 6901: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 6902: [(set_attr "type" "compare") 6903: (set_attr "length" "8")]) 1.1 root 6904: 6905: (define_insn "" 6906: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6907: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6908: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] 6909: "" 6910: "@ 1.1.1.2 root 6911: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 6912: {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0" 6913: [(set_attr "length" "12")]) 1.1 root 6914: 6915: (define_insn "" 6916: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6917: (and:SI (neg:SI 6918: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6919: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6920: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6921: (clobber (match_scratch:SI 4 "=&r,&r"))] 6922: "" 6923: "@ 1.1.1.2 root 6924: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 6925: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 6926: [(set_attr "length" "12")]) 1.1 root 6927: 6928: (define_insn "" 6929: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6930: (compare:CC 6931: (and:SI (neg:SI 6932: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6933: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6934: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6935: (const_int 0))) 6936: (clobber (match_scratch:SI 4 "=&r,&r"))] 6937: "" 6938: "@ 1.1.1.2 root 6939: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 6940: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 6941: [(set_attr "type" "compare") 6942: (set_attr "length" "12")]) 1.1 root 6943: 6944: (define_insn "" 6945: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6946: (compare:CC 6947: (and:SI (neg:SI 6948: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6949: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6950: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6951: (const_int 0))) 6952: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6953: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 6954: (clobber (match_scratch:SI 4 "=&r,&r"))] 6955: "" 6956: "@ 1.1.1.2 root 6957: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 6958: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 6959: [(set_attr "type" "compare") 6960: (set_attr "length" "12")]) 1.1 root 6961: 6962: (define_insn "" 6963: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6964: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6965: (const_int 0)))] 6966: "" 1.1.1.2 root 6967: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" 6968: [(set_attr "length" "12")]) 1.1 root 6969: 6970: (define_insn "" 6971: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 6972: (compare:CC 6973: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6974: (const_int 0)) 6975: (const_int 0))) 6976: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6977: (gt:SI (match_dup 1) (const_int 0)))] 6978: "" 1.1.1.2 root 6979: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" 6980: [(set_attr "type" "delayed_compare") 6981: (set_attr "length" "12")]) 1.1 root 6982: 6983: (define_insn "" 6984: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6985: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6986: (match_operand:SI 2 "reg_or_short_operand" "r")))] 1.1.1.2 root 6987: "TARGET_POWER" 6988: "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 6989: [(set_attr "length" "12")]) 1.1 root 6990: 6991: (define_insn "" 6992: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 6993: (compare:CC 6994: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6995: (match_operand:SI 2 "reg_or_short_operand" "r")) 6996: (const_int 0))) 6997: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6998: (gt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 6999: "TARGET_POWER" 7000: "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 7001: [(set_attr "type" "delayed_compare") 7002: (set_attr "length" "12")]) 1.1 root 7003: 7004: (define_insn "" 7005: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7006: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7007: (const_int 0)) 7008: (match_operand:SI 2 "gpc_reg_operand" "r"))) 7009: (clobber (match_scratch:SI 3 "=&r"))] 7010: "" 1.1.1.2 root 7011: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" 7012: [(set_attr "length" "12")]) 1.1 root 7013: 7014: (define_insn "" 7015: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 7016: (compare:CC 7017: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7018: (const_int 0)) 7019: (match_operand:SI 2 "gpc_reg_operand" "r")) 7020: (const_int 0))) 7021: (clobber (match_scratch:SI 3 "=&r"))] 7022: "" 1.1.1.2 root 7023: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" 7024: [(set_attr "type" "compare") 7025: (set_attr "length" "12")]) 1.1 root 7026: 7027: (define_insn "" 7028: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 7029: (compare:CC 7030: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7031: (const_int 0)) 7032: (match_operand:SI 2 "gpc_reg_operand" "r")) 7033: (const_int 0))) 7034: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7035: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 7036: (clobber (match_scratch:SI 3 "=&r"))] 7037: "" 1.1.1.2 root 7038: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" 7039: [(set_attr "type" "compare") 7040: (set_attr "length" "12")]) 1.1 root 7041: 7042: (define_insn "" 7043: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7044: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7045: (match_operand:SI 2 "reg_or_short_operand" "r")) 7046: (match_operand:SI 3 "gpc_reg_operand" "r"))) 7047: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7048: "TARGET_POWER" 7049: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 7050: [(set_attr "length" "12")]) 1.1 root 7051: 7052: (define_insn "" 7053: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 7054: (compare:CC 7055: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7056: (match_operand:SI 2 "reg_or_short_operand" "r")) 7057: (match_operand:SI 3 "gpc_reg_operand" "r")) 7058: (const_int 0))) 7059: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7060: "TARGET_POWER" 7061: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 7062: [(set_attr "type" "compare") 7063: (set_attr "length" "12")]) 1.1 root 7064: 7065: (define_insn "" 7066: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 7067: (compare:CC 7068: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7069: (match_operand:SI 2 "reg_or_short_operand" "r")) 7070: (match_operand:SI 3 "gpc_reg_operand" "r")) 7071: (const_int 0))) 7072: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7073: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 7074: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7075: "TARGET_POWER" 7076: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 7077: [(set_attr "type" "compare") 7078: (set_attr "length" "12")]) 1.1 root 7079: 7080: (define_insn "" 7081: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7082: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7083: (const_int 0))))] 7084: "" 1.1.1.2 root 7085: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" 7086: [(set_attr "length" "12")]) 1.1 root 7087: 7088: (define_insn "" 7089: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7090: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7091: (match_operand:SI 2 "reg_or_short_operand" "r"))))] 1.1.1.2 root 7092: "TARGET_POWER" 7093: "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 7094: [(set_attr "length" "12")]) 1.1 root 7095: 7096: (define_insn "" 7097: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7098: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7099: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 7100: "" 1.1.1.2 root 7101: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 7102: [(set_attr "length" "12")]) 1.1 root 7103: 7104: (define_insn "" 7105: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 7106: (compare:CC 7107: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7108: (match_operand:SI 2 "reg_or_short_operand" "rI")) 7109: (const_int 0))) 7110: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7111: (gtu:SI (match_dup 1) (match_dup 2)))] 7112: "" 1.1.1.2 root 7113: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 7114: [(set_attr "type" "compare") 7115: (set_attr "length" "12")]) 1.1 root 7116: 7117: (define_insn "" 7118: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 7119: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 7120: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) 7121: (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) 7122: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] 7123: "" 7124: "@ 1.1.1.2 root 7125: {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 7126: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 7127: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 7128: [(set_attr "length" "8,12,12")]) 1.1 root 7129: 7130: (define_insn "" 1.1.1.2 root 7131: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 7132: (compare:CC 1.1.1.2 root 7133: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 7134: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 7135: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 7136: (const_int 0))) 1.1.1.2 root 7137: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 7138: "" 7139: "@ 1.1.1.2 root 7140: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 7141: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 7142: [(set_attr "type" "compare") 7143: (set_attr "length" "8,12")]) 1.1 root 7144: 7145: (define_insn "" 1.1.1.2 root 7146: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 7147: (compare:CC 1.1.1.2 root 7148: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 7149: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 7150: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 7151: (const_int 0))) 1.1.1.2 root 7152: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 7153: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 7154: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 7155: "" 7156: "@ 1.1.1.2 root 7157: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 7158: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 7159: [(set_attr "type" "compare") 7160: (set_attr "length" "8,12")]) 1.1 root 7161: 7162: (define_insn "" 7163: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7164: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7165: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 7166: "" 1.1.1.2 root 7167: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 7168: [(set_attr "length" "8")]) 1.1 root 7169: 7170: ;; Define both directions of branch and return. If we need a reload 7171: ;; register, we'd rather use CR0 since it is much easier to copy a 7172: ;; register CC value to there. 7173: 7174: (define_insn "" 7175: [(set (pc) 7176: (if_then_else (match_operator 1 "branch_comparison_operator" 7177: [(match_operand 2 7178: "cc_reg_operand" "x,?y") 7179: (const_int 0)]) 7180: (label_ref (match_operand 0 "" "")) 7181: (pc)))] 7182: "" 1.1.1.2 root 7183: "* 7184: { 7185: if (get_attr_length (insn) == 8) 7186: return \"%C1bc %t1,%j1,%l0\"; 7187: else 7188: return \"%C1bc %T1,%j1,$+8\;b %l0\"; 7189: }" 7190: [(set_attr "type" "branch")]) 7191: 1.1 root 7192: (define_insn "" 7193: [(set (pc) 7194: (if_then_else (match_operator 0 "branch_comparison_operator" 7195: [(match_operand 1 7196: "cc_reg_operand" "x,?y") 7197: (const_int 0)]) 7198: (return) 7199: (pc)))] 7200: "direct_return ()" 1.1.1.2 root 7201: "{%C0bcr|%C0bclr} %t0,%j0" 7202: [(set_attr "length" "8")]) 1.1 root 7203: 7204: (define_insn "" 7205: [(set (pc) 7206: (if_then_else (match_operator 1 "branch_comparison_operator" 7207: [(match_operand 2 7208: "cc_reg_operand" "x,?y") 7209: (const_int 0)]) 7210: (pc) 7211: (label_ref (match_operand 0 "" ""))))] 7212: "" 1.1.1.2 root 7213: "* 7214: { 7215: if (get_attr_length (insn) == 8) 7216: return \"%C1bc %T1,%j1,%l0\"; 7217: else 7218: return \"%C1bc %t1,%j1,$+8\;b %l0\"; 7219: }" 7220: [(set_attr "type" "branch")]) 1.1 root 7221: 7222: (define_insn "" 7223: [(set (pc) 7224: (if_then_else (match_operator 0 "branch_comparison_operator" 7225: [(match_operand 1 7226: "cc_reg_operand" "x,?y") 7227: (const_int 0)]) 7228: (pc) 7229: (return)))] 7230: "direct_return ()" 1.1.1.2 root 7231: "{%C0bcr|%C0bclr} %T0,%j0" 7232: [(set_attr "length" "8")]) 1.1 root 7233: 7234: ;; Unconditional branch and return. 7235: 7236: (define_insn "jump" 7237: [(set (pc) 7238: (label_ref (match_operand 0 "" "")))] 7239: "" 7240: "b %l0") 7241: 7242: (define_insn "return" 7243: [(return)] 7244: "direct_return ()" 1.1.1.3 root 7245: "{br|blr}" 7246: [(set_attr "type" "jmpreg")]) 1.1 root 7247: 7248: (define_insn "indirect_jump" 7249: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] 7250: "" 7251: "@ 7252: bctr 1.1.1.3 root 7253: {br|blr}" 7254: [(set_attr "type" "jmpreg")]) 1.1 root 7255: 7256: ;; Table jump for switch statements: 7257: (define_expand "tablejump" 7258: [(set (match_dup 3) 7259: (plus:SI (match_operand:SI 0 "" "") 7260: (match_dup 2))) 7261: (parallel [(set (pc) (match_dup 3)) 7262: (use (label_ref (match_operand 1 "" "")))])] 7263: "" 7264: " 7265: { operands[0] = force_reg (SImode, operands[0]); 7266: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); 7267: operands[3] = gen_reg_rtx (SImode); 7268: }") 7269: 7270: (define_insn "" 7271: [(set (pc) 7272: (match_operand:SI 0 "register_operand" "c,l")) 7273: (use (label_ref (match_operand 1 "" "")))] 7274: "" 7275: "@ 7276: bctr 1.1.1.4 ! root 7277: {br|blr}" ! 7278: [(set_attr "type" "jmpreg")]) 1.1 root 7279: 7280: (define_insn "nop" 7281: [(const_int 0)] 7282: "" 1.1.1.2 root 7283: "{cror 0,0,0|nop}") 1.1 root 7284: 1.1.1.4 ! root 7285: ;; Define the subtract-one-and-jump insns, starting with the template 1.1 root 7286: ;; so loop.c knows what to generate. 7287: 7288: (define_expand "decrement_and_branchsi" 1.1.1.4 ! root 7289: [(parallel [(set (match_operand:SI 0 "register_operand" "") ! 7290: (plus:SI (match_dup 0) ! 7291: (const_int -1))) ! 7292: (set (pc) (if_then_else (ne (match_dup 0) 1.1 root 7293: (const_int 1)) 7294: (label_ref (match_operand 1 "" "")) 7295: (pc))) 1.1.1.4 ! root 7296: (clobber (match_scratch:CC 2 "")) ! 7297: (clobber (match_scratch:SI 3 ""))])] 1.1 root 7298: "" 7299: "") 7300: 7301: ;; We need to be able to do this for any operand, including MEM, or we 7302: ;; will cause reload to blow up since we don't allow output reloads on 1.1.1.4 ! root 7303: ;; JUMP_INSNs. ! 7304: ;; In order that the length attribute is calculated correctly, the ! 7305: ;; label MUST be operand 0. ! 7306: 1.1 root 7307: (define_insn "" 7308: [(set (pc) 1.1.1.4 ! root 7309: (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7310: (const_int 1)) 1.1.1.4 ! root 7311: (label_ref (match_operand 0 "" "")) 1.1 root 7312: (pc))) 1.1.1.4 ! root 7313: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7314: (plus:SI (match_dup 1) ! 7315: (const_int -1))) 1.1 root 7316: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7317: (clobber (match_scratch:SI 4 "=X,X,r"))] 7318: "" 1.1.1.2 root 7319: "* 7320: { 7321: if (which_alternative != 0) 7322: return \"#\"; 7323: else if (get_attr_length (insn) == 8) 1.1.1.4 ! root 7324: return \"{bdn|bdnz} %l0\"; 1.1.1.2 root 7325: else 1.1.1.4 ! root 7326: return \"bdz $+8\;b %l0\"; 1.1.1.2 root 7327: }" 7328: [(set_attr "type" "branch") 7329: (set_attr "length" "*,12,16")]) 1.1.1.4 ! root 7330: ! 7331: (define_insn "" ! 7332: [(set (pc) ! 7333: (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") ! 7334: (const_int 1)) ! 7335: (pc) ! 7336: (label_ref (match_operand 0 "" "")))) ! 7337: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7338: (plus:SI (match_dup 1) ! 7339: (const_int -1))) ! 7340: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 7341: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 7342: "" ! 7343: "* ! 7344: { ! 7345: if (which_alternative != 0) ! 7346: return \"#\"; ! 7347: else if (get_attr_length (insn) == 8) ! 7348: return \"bdz %l0\"; ! 7349: else ! 7350: return \"{bdn|bdnz} $+8\;b %l0\"; ! 7351: }" ! 7352: [(set_attr "type" "branch") ! 7353: (set_attr "length" "*,12,16")]) ! 7354: 1.1 root 7355: ;; Similar, but we can use GE since we have a REG_NONNEG. 7356: (define_insn "" 7357: [(set (pc) 1.1.1.4 ! root 7358: (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7359: (const_int 0)) 1.1.1.4 ! root 7360: (label_ref (match_operand 0 "" "")) 1.1 root 7361: (pc))) 1.1.1.4 ! root 7362: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7363: (plus:SI (match_dup 1) ! 7364: (const_int -1))) ! 7365: (clobber (match_scratch:CC 3 "=X,&x,&X")) ! 7366: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 7367: "find_reg_note (insn, REG_NONNEG, 0)" ! 7368: "* ! 7369: { ! 7370: if (which_alternative != 0) ! 7371: return \"#\"; ! 7372: else if (get_attr_length (insn) == 8) ! 7373: return \"{bdn|bdnz} %l0\"; ! 7374: else ! 7375: return \"bdz $+8\;b %l0\"; ! 7376: }" ! 7377: [(set_attr "type" "branch") ! 7378: (set_attr "length" "*,12,16")]) ! 7379: ! 7380: (define_insn "" ! 7381: [(set (pc) ! 7382: (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") ! 7383: (const_int 0)) ! 7384: (pc) ! 7385: (label_ref (match_operand 0 "" "")))) ! 7386: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7387: (plus:SI (match_dup 1) ! 7388: (const_int -1))) 1.1 root 7389: (clobber (match_scratch:CC 3 "=X,&x,&X")) 7390: (clobber (match_scratch:SI 4 "=X,X,r"))] 7391: "find_reg_note (insn, REG_NONNEG, 0)" 1.1.1.2 root 7392: "* 7393: { 7394: if (which_alternative != 0) 7395: return \"#\"; 7396: else if (get_attr_length (insn) == 8) 1.1.1.4 ! root 7397: return \"bdz %l0\"; 1.1.1.2 root 7398: else 1.1.1.4 ! root 7399: return \"{bdn|bdnz} $+8\;b %l0\"; 1.1.1.2 root 7400: }" 7401: [(set_attr "type" "branch") 7402: (set_attr "length" "*,12,16")]) 1.1.1.4 ! root 7403: 1.1 root 7404: (define_insn "" 7405: [(set (pc) 1.1.1.4 ! root 7406: (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7407: (const_int 1)) 1.1.1.4 ! root 7408: (label_ref (match_operand 0 "" "")) 1.1 root 7409: (pc))) 1.1.1.4 ! root 7410: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7411: (plus:SI (match_dup 1) ! 7412: (const_int -1))) ! 7413: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 7414: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 7415: "" ! 7416: "* ! 7417: { ! 7418: if (which_alternative != 0) ! 7419: return \"#\"; ! 7420: else if (get_attr_length (insn) == 8) ! 7421: return \"bdz %l0\"; ! 7422: else ! 7423: return \"{bdn|bdnz} $+8\;b %l0\"; ! 7424: }" ! 7425: [(set_attr "type" "branch") ! 7426: (set_attr "length" "*,12,16")]) ! 7427: ! 7428: (define_insn "" ! 7429: [(set (pc) ! 7430: (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") ! 7431: (const_int 1)) ! 7432: (pc) ! 7433: (label_ref (match_operand 0 "" "")))) ! 7434: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") ! 7435: (plus:SI (match_dup 1) ! 7436: (const_int -1))) 1.1 root 7437: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7438: (clobber (match_scratch:SI 4 "=X,X,r"))] 7439: "" 1.1.1.2 root 7440: "* 7441: { 7442: if (which_alternative != 0) 7443: return \"#\"; 7444: else if (get_attr_length (insn) == 8) 1.1.1.4 ! root 7445: return \"{bdn|bdnz} %l0\"; 1.1.1.2 root 7446: else 1.1.1.4 ! root 7447: return \"bdz $+8\;b %l0\"; 1.1.1.2 root 7448: }" 7449: [(set_attr "type" "branch") 7450: (set_attr "length" "*,12,16")]) 1.1 root 7451: 7452: (define_split 7453: [(set (pc) 7454: (if_then_else (match_operator 2 "comparison_operator" 7455: [(match_operand:SI 1 "gpc_reg_operand" "") 7456: (const_int 1)]) 7457: (match_operand 5 "" "") 7458: (match_operand 6 "" ""))) 7459: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1.1.4 ! root 7460: (plus:SI (match_dup 1) ! 7461: (const_int -1))) 1.1 root 7462: (clobber (match_scratch:CC 3 "")) 7463: (clobber (match_scratch:SI 4 ""))] 7464: "reload_completed" 7465: [(parallel [(set (match_dup 3) 1.1.1.4 ! root 7466: (compare:CC (plus:SI (match_dup 1) ! 7467: (const_int -1)) 1.1 root 7468: (const_int 0))) 1.1.1.4 ! root 7469: (set (match_dup 0) ! 7470: (plus:SI (match_dup 1) ! 7471: (const_int -1)))]) ! 7472: (set (pc) (if_then_else (match_dup 7) ! 7473: (match_dup 5) ! 7474: (match_dup 6)))] 1.1 root 7475: " 7476: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 7477: const0_rtx); }") 7478: 7479: (define_split 7480: [(set (pc) 7481: (if_then_else (match_operator 2 "comparison_operator" 7482: [(match_operand:SI 1 "gpc_reg_operand" "") 7483: (const_int 1)]) 7484: (match_operand 5 "" "") 7485: (match_operand 6 "" ""))) 7486: (set (match_operand:SI 0 "general_operand" "") 7487: (plus:SI (match_dup 1) (const_int -1))) 7488: (clobber (match_scratch:CC 3 "")) 7489: (clobber (match_scratch:SI 4 ""))] 7490: "reload_completed && ! gpc_reg_operand (operands[0], SImode)" 7491: [(parallel [(set (match_dup 3) 1.1.1.4 ! root 7492: (compare:CC (plus:SI (match_dup 1) ! 7493: (const_int -1)) 1.1 root 7494: (const_int 0))) 1.1.1.4 ! root 7495: (set (match_dup 4) ! 7496: (plus:SI (match_dup 1) ! 7497: (const_int -1)))]) ! 7498: (set (match_dup 0) ! 7499: (match_dup 4)) ! 7500: (set (pc) (if_then_else (match_dup 7) ! 7501: (match_dup 5) ! 7502: (match_dup 6)))] 1.1 root 7503: " 7504: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 7505: const0_rtx); }")
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