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1.1.1.3 root 1: ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 1.1.1.4 root 2: ;; Copyright (C) 1990, 91, 92, 93, 94, 1995 Free Software Foundation, Inc. 1.1.1.3 root 3: ;; Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 root 19: ;; the Free Software Foundation, 59 Temple Place - Suite 330, 20: ;; Boston, MA 02111-1307, USA. 1.1 root 21: 22: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 23: 24: ;; Define an insn type attribute. This is used in function unit delay 25: ;; computations. 1.1.1.3 root 26: (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" 1.1 root 27: (const_string "integer")) 28: 1.1.1.2 root 29: ;; Length (in bytes). 30: (define_attr "length" "" 31: (if_then_else (eq_attr "type" "branch") 32: (if_then_else (and (ge (minus (pc) (match_dup 0)) 33: (const_int -32768)) 34: (lt (minus (pc) (match_dup 0)) 35: (const_int 32767))) 36: (const_int 8) 37: (const_int 12)) 38: (const_int 4))) 39: 40: ;; Processor type -- this attribute must exactly match the processor_type 41: ;; enumeration in rs6000.h. 42: 1.1.1.4 root 43: (define_attr "cpu" "rios1,rios2,ppc403,ppc601,ppc603,ppc604,ppc620" 1.1.1.2 root 44: (const (symbol_ref "rs6000_cpu_attr"))) 45: 46: ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY 47: ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) 48: 1.1.1.3 root 49: ; Load/Store Unit -- POWER/2 and pure PowerPC only 50: ; (POWER and 601 use Integer Unit) 1.1.1.2 root 51: (define_function_unit "lsu" 1 0 52: (and (eq_attr "type" "load") 53: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 54: 2 0) 55: 56: (define_function_unit "lsu" 1 0 57: (and (eq_attr "type" "fpload") 58: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) 59: 2 0) 60: 61: (define_function_unit "iu" 1 0 62: (and (eq_attr "type" "load") 1.1.1.4 root 63: (eq_attr "cpu" "rios1,ppc403,ppc601")) 1.1.1.2 root 64: 2 0) 65: 66: (define_function_unit "iu" 1 0 67: (and (eq_attr "type" "fpload") 68: (eq_attr "cpu" "rios1,ppc601")) 69: 3 0) 70: 1.1.1.3 root 71: ; Integer Unit (RIOS1, PPC601, PPC603) 72: ; Trivial operations take one cycle which need not be listed here. 1.1.1.2 root 73: (define_function_unit "iu" 1 0 74: (and (eq_attr "type" "imul") 75: (eq_attr "cpu" "rios1")) 1.1.1.3 root 76: 3 3) 1.1.1.2 root 77: 78: (define_function_unit "iu" 1 0 79: (and (eq_attr "type" "imul") 1.1.1.4 root 80: (eq_attr "cpu" "ppc403")) 81: 4 4) 82: 83: (define_function_unit "iu" 1 0 84: (and (eq_attr "type" "imul") 1.1.1.3 root 85: (eq_attr "cpu" "ppc601,ppc603")) 86: 5 5) 1.1.1.2 root 87: 88: (define_function_unit "iu" 1 0 89: (and (eq_attr "type" "idiv") 90: (eq_attr "cpu" "rios1")) 1.1.1.3 root 91: 19 19) 1.1.1.2 root 92: 93: (define_function_unit "iu" 1 0 94: (and (eq_attr "type" "idiv") 1.1.1.4 root 95: (eq_attr "cpu" "ppc403")) 96: 33 33) 97: 98: (define_function_unit "iu" 1 0 99: (and (eq_attr "type" "idiv") 1.1.1.3 root 100: (eq_attr "cpu" "ppc601")) 101: 36 36) 102: 103: (define_function_unit "iu" 1 0 104: (and (eq_attr "type" "idiv") 105: (eq_attr "cpu" "ppc603")) 106: 37 36) 107: 108: ; RIOS2 has two integer units: a primary one which can perform all 109: ; operations and a secondary one which is fed in lock step with the first 110: ; and can perform "simple" integer operations. 111: (define_function_unit "iu2" 2 0 112: (and (eq_attr "type" "integer") 113: (eq_attr "cpu" "rios2")) 114: 1 0 115: [(eq_attr "type" "imul,idiv")]) 116: 117: (define_function_unit "imuldiv" 1 0 118: (and (eq_attr "type" "imul") 119: (eq_attr "cpu" "rios2")) 120: 2 2 121: [(eq_attr "type" "integer")]) 122: 123: (define_function_unit "imuldiv" 1 0 124: (and (eq_attr "type" "idiv") 125: (eq_attr "cpu" "rios2")) 126: 13 13 127: [(eq_attr "type" "integer")]) 128: 129: ; PPC604 has three integer units: one primary and two secondary. 130: (define_function_unit "iu3" 3 0 131: (and (eq_attr "type" "integer") 132: (eq_attr "cpu" "ppc604,ppc620")) 133: 1 0 134: [(eq_attr "type" "imul,idiv")]) 135: 136: (define_function_unit "imuldiv" 1 0 137: (and (eq_attr "type" "imul") 138: (eq_attr "cpu" "ppc604,ppc620")) 139: 4 2 140: [(eq_attr "type" "integer")]) 141: 142: (define_function_unit "imuldiv" 1 0 143: (and (eq_attr "type" "idiv") 144: (eq_attr "cpu" "ppc604,ppc620")) 145: 20 19 146: [(eq_attr "type" "integer")]) 1.1.1.2 root 147: 1.1.1.3 root 148: ; Branch Processing Unit 1.1.1.2 root 149: (define_function_unit "bpu" 1 0 150: (eq_attr "type" "compare") 151: 4 0) 152: 153: (define_function_unit "bpu" 1 0 154: (eq_attr "type" "delayed_compare") 155: 5 0) 156: 157: (define_function_unit "bpu" 1 0 158: (and (eq_attr "type" "fpcompare") 159: (eq_attr "cpu" "rios1,rios2")) 160: 8 0) 161: 162: (define_function_unit "bpu" 1 0 163: (and (eq_attr "type" "fpcompare") 164: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) 165: 4 0) 166: 167: (define_function_unit "bpu" 1 0 1.1.1.3 root 168: (and (eq_attr "type" "mtjmpr") 1.1.1.2 root 169: (eq_attr "cpu" "rios1,rios2")) 170: 5 0) 171: 172: (define_function_unit "bpu" 1 0 1.1.1.3 root 173: (and (eq_attr "type" "mtjmpr") 1.1.1.4 root 174: (eq_attr "cpu" "ppc403,ppc601,ppc603,ppc604,ppc620")) 1.1.1.2 root 175: 4 0) 176: 1.1.1.3 root 177: ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604). 1.1.1.2 root 178: (define_function_unit "fpu" 1 0 1.1.1.3 root 179: (and (eq_attr "type" "fp,dmul") 1.1.1.2 root 180: (eq_attr "cpu" "rios1")) 181: 2 0) 182: 183: (define_function_unit "fpu" 1 0 184: (and (eq_attr "type" "fp") 1.1.1.3 root 185: (eq_attr "cpu" "ppc601")) 1.1.1.2 root 186: 4 0) 187: 188: (define_function_unit "fpu" 1 0 1.1.1.3 root 189: (and (eq_attr "type" "fp") 190: (eq_attr "cpu" "ppc603,ppc604,ppc620")) 191: 3 0) 192: 193: (define_function_unit "fpu" 1 0 1.1.1.2 root 194: (and (eq_attr "type" "dmul") 1.1.1.3 root 195: (eq_attr "cpu" "ppc601")) 196: 5 5) 1.1.1.2 root 197: 198: (define_function_unit "fpu" 1 0 199: (and (eq_attr "type" "dmul") 1.1.1.3 root 200: (eq_attr "cpu" "ppc603")) 201: 4 2) 1.1.1.2 root 202: 203: (define_function_unit "fpu" 1 0 1.1.1.3 root 204: (and (eq_attr "type" "dmul") 205: (eq_attr "cpu" "ppc604,ppc620")) 206: 3 0) 207: 208: (define_function_unit "fpu" 1 0 209: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 210: (eq_attr "cpu" "rios1")) 1.1.1.3 root 211: 19 19) 1.1.1.2 root 212: 213: (define_function_unit "fpu" 1 0 214: (and (eq_attr "type" "sdiv") 1.1.1.3 root 215: (eq_attr "cpu" "ppc601")) 216: 17 17) 217: 218: (define_function_unit "fpu" 1 0 219: (and (eq_attr "type" "sdiv") 220: (eq_attr "cpu" "ppc603,ppc604,ppc620")) 221: 18 18) 1.1.1.2 root 222: 223: (define_function_unit "fpu" 1 0 224: (and (eq_attr "type" "ddiv") 1.1.1.3 root 225: (eq_attr "cpu" "ppc601,ppc604,ppc620")) 226: 31 31) 1.1.1.2 root 227: 228: (define_function_unit "fpu" 1 0 229: (and (eq_attr "type" "ddiv") 1.1.1.3 root 230: (eq_attr "cpu" "ppc603")) 231: 33 33) 1.1.1.2 root 232: 233: (define_function_unit "fpu" 1 0 234: (and (eq_attr "type" "ssqrt") 1.1.1.3 root 235: (eq_attr "cpu" "ppc620")) 236: 31 31) 1.1.1.2 root 237: 238: (define_function_unit "fpu" 1 0 239: (and (eq_attr "type" "dsqrt") 1.1.1.3 root 240: (eq_attr "cpu" "ppc620")) 241: 31 31) 1.1.1.2 root 242: 1.1.1.3 root 243: ; RIOS2 has two symmetric FPUs. 1.1.1.2 root 244: (define_function_unit "fpu2" 2 0 245: (and (eq_attr "type" "fp") 246: (eq_attr "cpu" "rios2")) 247: 2 0) 248: 249: (define_function_unit "fpu2" 2 0 250: (and (eq_attr "type" "dmul") 251: (eq_attr "cpu" "rios2")) 252: 2 0) 253: 254: (define_function_unit "fpu2" 2 0 1.1.1.3 root 255: (and (eq_attr "type" "sdiv,ddiv") 1.1.1.2 root 256: (eq_attr "cpu" "rios2")) 1.1.1.3 root 257: 17 17) 1.1.1.2 root 258: 259: (define_function_unit "fpu2" 2 0 1.1.1.3 root 260: (and (eq_attr "type" "ssqrt,dsqrt") 1.1.1.2 root 261: (eq_attr "cpu" "rios2")) 1.1.1.3 root 262: 26 26) 1.1 root 263: 264: ;; Start with fixed-point load and store insns. Here we put only the more 265: ;; complex forms. Basic data transfer is done later. 266: 1.1.1.3 root 267: (define_expand "zero_extendqidi2" 268: [(set (match_operand:DI 0 "gpc_reg_operand" "") 269: (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] 270: "TARGET_POWERPC64" 271: "") 272: 273: (define_insn "" 274: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 275: (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 276: "TARGET_POWERPC64" 277: "@ 278: lbz%U1%X1 %0,%1 279: rldicl %0,%1,0,56" 280: [(set_attr "type" "load,*")]) 281: 282: (define_insn "" 283: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 284: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 285: (const_int 0))) 286: (clobber (match_scratch:DI 2 "=r"))] 287: "TARGET_POWERPC64" 288: "rldicl. %2,%1,0,56" 289: [(set_attr "type" "compare")]) 290: 291: (define_insn "" 292: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 293: (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 294: (const_int 0))) 295: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 296: (zero_extend:DI (match_dup 1)))] 297: "TARGET_POWERPC64" 298: "rldicl. %0,%1,0,56" 299: [(set_attr "type" "compare")]) 300: 301: (define_insn "extendqidi2" 302: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 303: (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 304: "TARGET_POWERPC64" 305: "extsb %0,%1") 306: 307: (define_insn "" 308: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 309: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 310: (const_int 0))) 311: (clobber (match_scratch:DI 2 "=r"))] 312: "TARGET_POWERPC64" 313: "extsb. %2,%1" 314: [(set_attr "type" "compare")]) 315: 316: (define_insn "" 317: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 318: (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) 319: (const_int 0))) 320: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 321: (sign_extend:DI (match_dup 1)))] 322: "TARGET_POWERPC64" 323: "extsb. %0,%1" 324: [(set_attr "type" "compare")]) 325: 326: (define_expand "zero_extendhidi2" 327: [(set (match_operand:DI 0 "gpc_reg_operand" "") 328: (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 329: "TARGET_POWERPC64" 330: "") 331: 332: (define_insn "" 333: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 334: (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 335: "TARGET_POWERPC64" 336: "@ 337: lhz%U1%X1 %0,%1 338: rldicl %0,%1,0,48" 339: [(set_attr "type" "load,*")]) 340: 341: (define_insn "" 342: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 343: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 344: (const_int 0))) 345: (clobber (match_scratch:DI 2 "=r"))] 346: "TARGET_POWERPC64" 347: "rldicl. %2,%1,0,48" 348: [(set_attr "type" "compare")]) 349: 350: (define_insn "" 351: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 352: (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 353: (const_int 0))) 354: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 355: (zero_extend:DI (match_dup 1)))] 356: "TARGET_POWERPC64" 357: "rldicl. %0,%1,0,48" 358: [(set_attr "type" "compare")]) 359: 360: (define_expand "extendhidi2" 361: [(set (match_operand:DI 0 "gpc_reg_operand" "") 362: (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 363: "TARGET_POWERPC64" 364: "") 365: 366: (define_insn "" 367: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 368: (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 369: "TARGET_POWERPC64" 370: "@ 371: lha%U1%X1 %0,%1 372: extsh %0,%1" 373: [(set_attr "type" "load,*")]) 374: 375: (define_insn "" 376: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 377: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 378: (const_int 0))) 379: (clobber (match_scratch:DI 2 "=r"))] 380: "TARGET_POWERPC64" 381: "extsh. %2,%1" 382: [(set_attr "type" "compare")]) 383: 384: (define_insn "" 385: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 386: (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) 387: (const_int 0))) 388: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 389: (sign_extend:DI (match_dup 1)))] 390: "TARGET_POWERPC64" 391: "extsh. %0,%1" 392: [(set_attr "type" "compare")]) 393: 394: (define_expand "zero_extendsidi2" 395: [(set (match_operand:DI 0 "gpc_reg_operand" "") 396: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 397: "TARGET_POWERPC64" 398: "") 399: 400: (define_insn "" 401: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 402: (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] 403: "TARGET_POWERPC64" 404: "@ 405: lwz%U1%X1 %0,%1 406: rldicl %0,%1,0,32" 407: [(set_attr "type" "load,*")]) 408: 409: (define_insn "" 410: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 411: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 412: (const_int 0))) 413: (clobber (match_scratch:DI 2 "=r"))] 414: "TARGET_POWERPC64" 415: "rldicl. %2,%1,0,32" 416: [(set_attr "type" "compare")]) 417: 418: (define_insn "" 419: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 420: (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 421: (const_int 0))) 422: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 423: (zero_extend:DI (match_dup 1)))] 424: "TARGET_POWERPC64" 425: "rldicl. %0,%1,0,32" 426: [(set_attr "type" "compare")]) 427: 428: (define_expand "extendsidi2" 429: [(set (match_operand:DI 0 "gpc_reg_operand" "") 430: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 431: "TARGET_POWERPC64" 432: "") 433: 434: (define_insn "" 435: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1.1.1.4 root 436: (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] 1.1.1.3 root 437: "TARGET_POWERPC64" 438: "@ 439: lwa%U1%X1 %0,%1 440: extsw %0,%1" 441: [(set_attr "type" "load,*")]) 442: 443: (define_insn "" 444: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 445: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 446: (const_int 0))) 447: (clobber (match_scratch:DI 2 "=r"))] 448: "TARGET_POWERPC64" 449: "extsw. %2,%1" 450: [(set_attr "type" "compare")]) 451: 452: (define_insn "" 453: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 454: (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 455: (const_int 0))) 456: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 457: (sign_extend:DI (match_dup 1)))] 458: "TARGET_POWERPC64" 459: "extsw. %0,%1" 460: [(set_attr "type" "compare")]) 461: 1.1 root 462: (define_expand "zero_extendqisi2" 463: [(set (match_operand:SI 0 "gpc_reg_operand" "") 464: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 465: "" 466: "") 467: 468: (define_insn "" 469: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 470: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 471: "" 472: "@ 473: lbz%U1%X1 %0,%1 1.1.1.2 root 474: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 475: [(set_attr "type" "load,*")]) 476: 477: (define_insn "" 478: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 479: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 480: (const_int 0))) 481: (clobber (match_scratch:SI 2 "=r"))] 482: "" 1.1.1.2 root 483: "{andil.|andi.} %2,%1,0xff" 1.1 root 484: [(set_attr "type" "compare")]) 485: 486: (define_insn "" 487: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 488: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 489: (const_int 0))) 490: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 491: (zero_extend:SI (match_dup 1)))] 492: "" 1.1.1.2 root 493: "{andil.|andi.} %0,%1,0xff" 1.1 root 494: [(set_attr "type" "compare")]) 495: 1.1.1.3 root 496: (define_expand "extendqisi2" 497: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 498: (use (match_operand:QI 1 "gpc_reg_operand" ""))] 499: "" 500: " 501: { 502: if (TARGET_POWERPC) 503: emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); 504: else if (TARGET_POWER) 505: emit_insn (gen_extendqisi2_power (operands[0], operands[1])); 506: else 507: emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); 508: DONE; 509: }") 510: 511: (define_insn "extendqisi2_ppc" 512: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 513: (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 514: "TARGET_POWERPC" 515: "extsb %0,%1") 516: 517: (define_insn "" 518: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 519: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 520: (const_int 0))) 521: (clobber (match_scratch:SI 2 "=r"))] 522: "TARGET_POWERPC" 523: "extsb. %2,%1" 524: [(set_attr "type" "compare")]) 525: 526: (define_insn "" 527: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 528: (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) 529: (const_int 0))) 530: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 531: (sign_extend:SI (match_dup 1)))] 532: "TARGET_POWERPC" 533: "extsb. %0,%1" 534: [(set_attr "type" "compare")]) 535: 536: (define_expand "extendqisi2_power" 537: [(parallel [(set (match_dup 2) 538: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 539: (const_int 24))) 540: (clobber (scratch:SI))]) 541: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 542: (ashiftrt:SI (match_dup 2) 543: (const_int 24))) 544: (clobber (scratch:SI))])] 545: "TARGET_POWER" 546: " 547: { operands[1] = gen_lowpart (SImode, operands[1]); 548: operands[2] = gen_reg_rtx (SImode); }") 549: 550: (define_expand "extendqisi2_no_power" 551: [(set (match_dup 2) 552: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 553: (const_int 24))) 554: (set (match_operand:SI 0 "gpc_reg_operand" "") 555: (ashiftrt:SI (match_dup 2) 556: (const_int 24)))] 557: "! TARGET_POWER && ! TARGET_POWERPC" 558: " 559: { operands[1] = gen_lowpart (SImode, operands[1]); 560: operands[2] = gen_reg_rtx (SImode); }") 561: 1.1 root 562: (define_expand "zero_extendqihi2" 563: [(set (match_operand:HI 0 "gpc_reg_operand" "") 564: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 565: "" 566: "") 567: 568: (define_insn "" 569: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 570: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 571: "" 572: "@ 573: lbz%U1%X1 %0,%1 1.1.1.2 root 574: {rlinm|rlwinm} %0,%1,0,0xff" 1.1 root 575: [(set_attr "type" "load,*")]) 576: 1.1.1.3 root 577: (define_insn "" 578: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 579: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 580: (const_int 0))) 581: (clobber (match_scratch:HI 2 "=r"))] 582: "" 583: "{andil.|andi.} %2,%1,0xff" 584: [(set_attr "type" "compare")]) 585: 586: (define_insn "" 587: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 588: (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 589: (const_int 0))) 590: (set (match_operand:HI 0 "gpc_reg_operand" "=r") 591: (zero_extend:HI (match_dup 1)))] 592: "" 593: "{andil.|andi.} %0,%1,0xff" 594: [(set_attr "type" "compare")]) 595: 596: (define_expand "extendqihi2" 597: [(use (match_operand:HI 0 "gpc_reg_operand" "")) 598: (use (match_operand:QI 1 "gpc_reg_operand" ""))] 599: "" 600: " 601: { 602: if (TARGET_POWERPC) 603: emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); 604: else if (TARGET_POWER) 605: emit_insn (gen_extendqihi2_power (operands[0], operands[1])); 606: else 607: emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); 608: DONE; 609: }") 610: 611: (define_insn "extendqihi2_ppc" 612: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 613: (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 614: "TARGET_POWERPC" 615: "extsb %0,%1") 616: 617: (define_insn "" 618: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 619: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 620: (const_int 0))) 621: (clobber (match_scratch:HI 2 "=r"))] 622: "TARGET_POWERPC" 623: "extsb. %2,%1" 624: [(set_attr "type" "compare")]) 625: 626: (define_insn "" 627: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 628: (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) 629: (const_int 0))) 630: (set (match_operand:HI 0 "gpc_reg_operand" "=r") 631: (sign_extend:HI (match_dup 1)))] 632: "TARGET_POWERPC" 633: "extsb. %0,%1" 634: [(set_attr "type" "compare")]) 635: 636: (define_expand "extendqihi2_power" 637: [(parallel [(set (match_dup 2) 638: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 639: (const_int 24))) 640: (clobber (scratch:SI))]) 641: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") 642: (ashiftrt:SI (match_dup 2) 643: (const_int 24))) 644: (clobber (scratch:SI))])] 645: "TARGET_POWER" 646: " 647: { operands[0] = gen_lowpart (SImode, operands[0]); 648: operands[1] = gen_lowpart (SImode, operands[1]); 649: operands[2] = gen_reg_rtx (SImode); }") 650: 651: (define_expand "extendqihi2_no_power" 652: [(set (match_dup 2) 653: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 654: (const_int 24))) 655: (set (match_operand:HI 0 "gpc_reg_operand" "") 656: (ashiftrt:SI (match_dup 2) 657: (const_int 24)))] 658: "! TARGET_POWER && ! TARGET_POWERPC" 659: " 660: { operands[0] = gen_lowpart (SImode, operands[0]); 661: operands[1] = gen_lowpart (SImode, operands[1]); 662: operands[2] = gen_reg_rtx (SImode); }") 663: 1.1 root 664: (define_expand "zero_extendhisi2" 665: [(set (match_operand:SI 0 "gpc_reg_operand" "") 666: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 667: "" 668: "") 669: 670: (define_insn "" 671: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 672: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 673: "" 674: "@ 675: lhz%U1%X1 %0,%1 1.1.1.2 root 676: {rlinm|rlwinm} %0,%1,0,0xffff" 1.1 root 677: [(set_attr "type" "load,*")]) 678: 679: (define_insn "" 680: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 681: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 682: (const_int 0))) 683: (clobber (match_scratch:SI 2 "=r"))] 684: "" 1.1.1.2 root 685: "{andil.|andi.} %2,%1,0xffff" 1.1 root 686: [(set_attr "type" "compare")]) 687: 688: (define_insn "" 689: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 690: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 691: (const_int 0))) 692: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 693: (zero_extend:SI (match_dup 1)))] 694: "" 1.1.1.2 root 695: "{andil.|andi.} %0,%1,0xffff" 1.1 root 696: [(set_attr "type" "compare")]) 697: 698: (define_expand "extendhisi2" 699: [(set (match_operand:SI 0 "gpc_reg_operand" "") 700: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 701: "" 702: "") 703: 704: (define_insn "" 705: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 706: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 707: "" 708: "@ 709: lha%U1%X1 %0,%1 1.1.1.2 root 710: {exts|extsh} %0,%1" 1.1 root 711: [(set_attr "type" "load,*")]) 712: 713: (define_insn "" 714: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 715: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 716: (const_int 0))) 717: (clobber (match_scratch:SI 2 "=r"))] 718: "" 1.1.1.2 root 719: "{exts.|extsh.} %2,%1" 1.1 root 720: [(set_attr "type" "compare")]) 721: 722: (define_insn "" 723: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 724: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) 725: (const_int 0))) 726: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 727: (sign_extend:SI (match_dup 1)))] 728: "" 1.1.1.2 root 729: "{exts.|extsh.} %0,%1" 1.1 root 730: [(set_attr "type" "compare")]) 731: 732: ;; Fixed-point arithmetic insns. 1.1.1.3 root 733: 734: ;; Discourage ai/addic because of carry but provide it in an alternative 735: ;; allowing register zero as source. 1.1 root 736: (define_insn "addsi3" 1.1.1.3 root 737: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") 738: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") 739: (match_operand:SI 2 "add_operand" "r,I,I,J")))] 1.1 root 740: "" 741: "@ 1.1.1.3 root 742: {cax|add} %0,%1,%2 743: {cal %0,%2(%1)|addi %0,%1,%2} 744: {ai|addic} %0,%1,%2 1.1.1.2 root 745: {cau|addis} %0,%1,%u2") 1.1 root 746: 747: (define_insn "" 1.1.1.3 root 748: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 749: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 750: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 751: (const_int 0))) 1.1.1.3 root 752: (clobber (match_scratch:SI 3 "=r,r"))] 1.1 root 753: "" 1.1.1.3 root 754: "@ 755: {cax.|add.} %3,%1,%2 756: {ai.|addic.} %3,%1,%2" 1.1 root 757: [(set_attr "type" "compare")]) 1.1.1.4 root 758: 1.1 root 759: (define_insn "" 1.1.1.3 root 760: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 761: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 762: (match_operand:SI 2 "reg_or_short_operand" "r,I")) 1.1 root 763: (const_int 0))) 1.1.1.3 root 764: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 765: (plus:SI (match_dup 1) (match_dup 2)))] 766: "" 1.1.1.3 root 767: "@ 768: {cax.|add.} %0,%1,%2 769: {ai.|addic.} %0,%1,%2" 1.1 root 770: [(set_attr "type" "compare")]) 1.1.1.4 root 771: 1.1 root 772: ;; Split an add that we can't do in one insn into two insns, each of which 773: ;; does one 16-bit part. This is used by combine. Note that the low-order 774: ;; add should be last in case the result gets used in an address. 775: 776: (define_split 777: [(set (match_operand:SI 0 "gpc_reg_operand" "") 778: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 779: (match_operand:SI 2 "non_add_cint_operand" "")))] 780: "" 781: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 782: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 783: " 784: { 785: int low = INTVAL (operands[2]) & 0xffff; 786: int high = (unsigned) INTVAL (operands[2]) >> 16; 787: 788: if (low & 0x8000) 789: high++, low |= 0xffff0000; 790: 791: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); 792: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); 793: }") 794: 1.1.1.3 root 795: (define_insn "one_cmplsi2" 1.1 root 796: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 797: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 798: "" 1.1.1.2 root 799: "nor %0,%1,%1") 800: 801: (define_insn "" 802: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 803: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 804: (const_int 0))) 805: (clobber (match_scratch:SI 2 "=r"))] 1.1 root 806: "" 1.1.1.2 root 807: "nor. %2,%1,%1" 808: [(set_attr "type" "compare")]) 809: 810: (define_insn "" 1.1.1.3 root 811: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1.1.1.2 root 812: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 813: (const_int 0))) 814: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 815: (not:SI (match_dup 1)))] 816: "" 1.1.1.5 ! root 817: "nor. %0,%1,%1" 1.1.1.2 root 818: [(set_attr "type" "compare")]) 819: 820: (define_insn "" 821: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 822: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 823: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1.1.1.3 root 824: "! TARGET_POWERPC" 1.1.1.2 root 825: "{sf%I1|subf%I1c} %0,%2,%1") 1.1 root 826: 827: (define_insn "" 1.1.1.3 root 828: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 829: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") 830: (match_operand:SI 2 "gpc_reg_operand" "r,r")))] 831: "TARGET_POWERPC" 832: "@ 833: subf %0,%2,%1 834: subfic %0,%2,%1") 835: 836: (define_insn "" 1.1 root 837: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 838: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 839: (match_operand:SI 2 "gpc_reg_operand" "r")) 840: (const_int 0))) 841: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 root 842: "! TARGET_POWERPC" 1.1.1.2 root 843: "{sf.|subfc.} %3,%2,%1" 1.1 root 844: [(set_attr "type" "compare")]) 845: 846: (define_insn "" 1.1.1.3 root 847: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 848: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 849: (match_operand:SI 2 "gpc_reg_operand" "r")) 850: (const_int 0))) 851: (clobber (match_scratch:SI 3 "=r"))] 852: "TARGET_POWERPC" 853: "subf. %3,%2,%1" 854: [(set_attr "type" "compare")]) 855: 856: (define_insn "" 1.1 root 857: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 858: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 859: (match_operand:SI 2 "gpc_reg_operand" "r")) 860: (const_int 0))) 861: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 862: (minus:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 863: "! TARGET_POWERPC" 1.1.1.2 root 864: "{sf.|subfc.} %0,%2,%1" 1.1 root 865: [(set_attr "type" "compare")]) 866: 1.1.1.3 root 867: (define_insn "" 868: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 869: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 870: (match_operand:SI 2 "gpc_reg_operand" "r")) 871: (const_int 0))) 872: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 873: (minus:SI (match_dup 1) (match_dup 2)))] 874: "TARGET_POWERPC" 875: "subf. %0,%2,%1" 876: [(set_attr "type" "compare")]) 877: 1.1 root 878: (define_expand "subsi3" 879: [(set (match_operand:SI 0 "gpc_reg_operand" "") 880: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") 881: (match_operand:SI 2 "reg_or_cint_operand" "")))] 882: "" 883: " 884: { 885: if (GET_CODE (operands[2]) == CONST_INT) 886: { 887: emit_insn (gen_addsi3 (operands[0], operands[1], 888: negate_rtx (SImode, operands[2]))); 889: DONE; 890: } 891: }") 892: 893: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 894: ;; instruction and some auxiliary computations. Then we just have a single 895: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 896: ;; combine. 897: 898: (define_expand "sminsi3" 899: [(set (match_dup 3) 900: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 901: (match_operand:SI 2 "reg_or_short_operand" "")) 902: (const_int 0) 903: (minus:SI (match_dup 2) (match_dup 1)))) 904: (set (match_operand:SI 0 "gpc_reg_operand" "") 905: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 906: "TARGET_POWER" 1.1 root 907: " 908: { operands[3] = gen_reg_rtx (SImode); }") 909: 910: (define_split 911: [(set (match_operand:SI 0 "gpc_reg_operand" "") 912: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 913: (match_operand:SI 2 "reg_or_short_operand" ""))) 914: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 915: "TARGET_POWER" 1.1 root 916: [(set (match_dup 3) 917: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 918: (const_int 0) 919: (minus:SI (match_dup 2) (match_dup 1)))) 920: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 921: "") 922: 923: (define_expand "smaxsi3" 924: [(set (match_dup 3) 925: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 926: (match_operand:SI 2 "reg_or_short_operand" "")) 927: (const_int 0) 928: (minus:SI (match_dup 2) (match_dup 1)))) 929: (set (match_operand:SI 0 "gpc_reg_operand" "") 930: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 931: "TARGET_POWER" 1.1 root 932: " 933: { operands[3] = gen_reg_rtx (SImode); }") 934: 935: (define_split 936: [(set (match_operand:SI 0 "gpc_reg_operand" "") 937: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 938: (match_operand:SI 2 "reg_or_short_operand" ""))) 939: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1.1.1.2 root 940: "TARGET_POWER" 1.1 root 941: [(set (match_dup 3) 942: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 943: (const_int 0) 944: (minus:SI (match_dup 2) (match_dup 1)))) 945: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 946: "") 947: 948: (define_expand "uminsi3" 949: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1.1.4 root 950: (match_dup 5))) 1.1 root 951: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.4 root 952: (match_dup 5))) 1.1 root 953: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 954: (const_int 0) 955: (minus:SI (match_dup 4) (match_dup 3)))) 956: (set (match_operand:SI 0 "gpc_reg_operand" "") 957: (minus:SI (match_dup 2) (match_dup 3)))] 1.1.1.2 root 958: "TARGET_POWER" 1.1 root 959: " 1.1.1.4 root 960: { 961: operands[3] = gen_reg_rtx (SImode); 962: operands[4] = gen_reg_rtx (SImode); 963: operands[5] = GEN_INT (-2147483647 - 1); 964: }") 1.1 root 965: 966: (define_expand "umaxsi3" 967: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1.1.4 root 968: (match_dup 5))) 1.1 root 969: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.4 root 970: (match_dup 5))) 1.1 root 971: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 972: (const_int 0) 973: (minus:SI (match_dup 4) (match_dup 3)))) 974: (set (match_operand:SI 0 "gpc_reg_operand" "") 975: (plus:SI (match_dup 3) (match_dup 1)))] 1.1.1.2 root 976: "TARGET_POWER" 1.1 root 977: " 1.1.1.4 root 978: { 979: operands[3] = gen_reg_rtx (SImode); 980: operands[4] = gen_reg_rtx (SImode); 981: operands[5] = GEN_INT (-2147483647 - 1); 982: }") 1.1 root 983: 984: (define_insn "" 985: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 986: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 987: (match_operand:SI 2 "reg_or_short_operand" "rI")) 988: (const_int 0) 989: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 990: "TARGET_POWER" 1.1 root 991: "doz%I2 %0,%1,%2") 992: 993: (define_insn "" 994: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 995: (compare:CC 996: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 997: (match_operand:SI 2 "reg_or_short_operand" "rI")) 998: (const_int 0) 999: (minus:SI (match_dup 2) (match_dup 1))) 1000: (const_int 0))) 1001: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 1002: "TARGET_POWER" 1.1 root 1003: "doz%I2. %3,%1,%2" 1004: [(set_attr "type" "delayed_compare")]) 1005: 1006: (define_insn "" 1007: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1008: (compare:CC 1009: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 1010: (match_operand:SI 2 "reg_or_short_operand" "rI")) 1011: (const_int 0) 1012: (minus:SI (match_dup 2) (match_dup 1))) 1013: (const_int 0))) 1014: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1015: (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1016: (const_int 0) 1017: (minus:SI (match_dup 2) (match_dup 1))))] 1.1.1.2 root 1018: "TARGET_POWER" 1.1 root 1019: "doz%I2. %0,%1,%2" 1020: [(set_attr "type" "delayed_compare")]) 1021: 1022: ;; We don't need abs with condition code because such comparisons should 1023: ;; never be done. 1.1.1.4 root 1024: (define_expand "abssi2" 1025: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1026: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 1027: "" 1028: " 1029: { 1030: if (!TARGET_POWER) 1031: { 1032: emit_insn (gen_abssi2_nopower (operands[0], operands[1])); 1033: DONE; 1034: } 1035: }") 1036: 1037: (define_insn "abssi2_power" 1.1 root 1038: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1039: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.2 root 1040: "TARGET_POWER" 1.1 root 1041: "abs %0,%1") 1042: 1.1.1.4 root 1043: (define_insn "abssi2_nopower" 1044: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1045: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 1046: (clobber (match_scratch:SI 2 "=&r,&r"))] 1047: "!TARGET_POWER" 1048: "* 1049: { 1050: return (TARGET_POWERPC) 1051: ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" 1052: : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; 1053: }" 1054: [(set_attr "length" "12")]) 1055: 1056: (define_split 1057: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1058: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 1059: (clobber (match_scratch:SI 2 "=&r,&r"))] 1060: "!TARGET_POWER && reload_completed" 1061: [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 1062: (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 1063: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] 1064: "") 1065: 1.1 root 1066: (define_insn "" 1067: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1068: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1069: "TARGET_POWER" 1.1 root 1070: "nabs %0,%1") 1071: 1.1.1.4 root 1072: (define_insn "" 1073: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1074: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) 1075: (clobber (match_scratch:SI 2 "=&r,&r"))] 1076: "!TARGET_POWER" 1077: "* 1078: { 1079: return (TARGET_POWERPC) 1080: ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" 1081: : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; 1082: }" 1083: [(set_attr "length" "12")]) 1084: 1085: (define_split 1086: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1087: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) 1088: (clobber (match_scratch:SI 2 "=&r,&r"))] 1089: "!TARGET_POWER && reload_completed" 1090: [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 1091: (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 1092: (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] 1093: "") 1094: 1.1 root 1095: (define_insn "negsi2" 1096: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1097: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1098: "" 1099: "neg %0,%1") 1100: 1101: (define_insn "" 1102: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1103: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1104: (const_int 0))) 1105: (clobber (match_scratch:SI 2 "=r"))] 1106: "" 1107: "neg. %2,%1" 1108: [(set_attr "type" "compare")]) 1109: 1110: (define_insn "" 1111: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 1112: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1113: (const_int 0))) 1114: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1115: (neg:SI (match_dup 1)))] 1116: "" 1117: "neg. %0,%1" 1118: [(set_attr "type" "compare")]) 1119: 1120: (define_insn "ffssi2" 1.1.1.4 root 1121: [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 1122: (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 1123: "" 1.1.1.2 root 1124: "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" 1125: [(set_attr "length" "16")]) 1126: 1127: (define_expand "mulsi3" 1128: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1129: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1130: (use (match_operand:SI 2 "reg_or_short_operand" ""))] 1131: "" 1132: " 1133: { 1134: if (TARGET_POWER) 1135: emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 1136: else 1137: emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 1138: DONE; 1139: }") 1.1 root 1140: 1.1.1.2 root 1141: (define_insn "mulsi3_mq" 1.1 root 1142: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1143: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1144: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 1145: (clobber (match_scratch:SI 3 "=q,q"))] 1.1.1.2 root 1146: "TARGET_POWER" 1.1 root 1147: "@ 1.1.1.2 root 1148: {muls|mullw} %0,%1,%2 1149: {muli|mulli} %0,%1,%2" 1150: [(set_attr "type" "imul")]) 1151: 1152: (define_insn "mulsi3_no_mq" 1153: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1154: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1155: (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 1156: "! TARGET_POWER" 1157: "@ 1.1.1.4 root 1158: {muls|mullw} %0,%1,%2 1159: {muli|mulli} %0,%1,%2" 1.1.1.2 root 1160: [(set_attr "type" "imul")]) 1.1 root 1161: 1162: (define_insn "" 1163: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1164: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1165: (match_operand:SI 2 "gpc_reg_operand" "r")) 1166: (const_int 0))) 1167: (clobber (match_scratch:SI 3 "=r")) 1168: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1169: "TARGET_POWER" 1170: "{muls.|mullw.} %3,%1,%2" 1171: [(set_attr "type" "delayed_compare")]) 1172: 1173: (define_insn "" 1174: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1175: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1176: (match_operand:SI 2 "gpc_reg_operand" "r")) 1177: (const_int 0))) 1178: (clobber (match_scratch:SI 3 "=r"))] 1179: "! TARGET_POWER" 1.1.1.4 root 1180: "{muls.|mullw.} %3,%1,%2" 1.1 root 1181: [(set_attr "type" "delayed_compare")]) 1182: 1183: (define_insn "" 1184: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1185: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1186: (match_operand:SI 2 "gpc_reg_operand" "r")) 1187: (const_int 0))) 1188: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1189: (mult:SI (match_dup 1) (match_dup 2))) 1190: (clobber (match_scratch:SI 4 "=q"))] 1.1.1.2 root 1191: "TARGET_POWER" 1192: "{muls.|mullw.} %0,%1,%2" 1193: [(set_attr "type" "delayed_compare")]) 1194: 1195: (define_insn "" 1196: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1197: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.2 root 1198: (match_operand:SI 2 "gpc_reg_operand" "r")) 1199: (const_int 0))) 1200: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1201: (mult:SI (match_dup 1) (match_dup 2)))] 1202: "! TARGET_POWER" 1.1.1.4 root 1203: "{muls.|mullw.} %0,%1,%2" 1.1 root 1204: [(set_attr "type" "delayed_compare")]) 1205: 1206: ;; Operand 1 is divided by operand 2; quotient goes to operand 1207: ;; 0 and remainder to operand 3. 1208: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 1209: 1.1.1.3 root 1210: (define_expand "divmodsi4" 1211: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1212: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1213: (match_operand:SI 2 "gpc_reg_operand" ""))) 1214: (set (match_operand:SI 3 "gpc_reg_operand" "") 1215: (mod:SI (match_dup 1) (match_dup 2)))])] 1216: "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" 1217: " 1218: { 1219: if (! TARGET_POWER && ! TARGET_POWERPC) 1220: { 1221: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1222: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1223: emit_insn (gen_divss_call ()); 1224: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1225: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); 1226: DONE; 1227: } 1228: }") 1229: 1230: (define_insn "" 1.1 root 1231: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1232: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1233: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1234: (set (match_operand:SI 3 "gpc_reg_operand" "=q") 1235: (mod:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 1236: "TARGET_POWER" 1237: "divs %0,%1,%2" 1238: [(set_attr "type" "idiv")]) 1239: 1240: (define_insn "" 1241: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1242: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1243: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1244: "TARGET_POWERPC" 1.1.1.3 root 1245: "divw %0,%1,%2" 1.1.1.2 root 1246: [(set_attr "type" "idiv")]) 1247: 1.1.1.3 root 1248: (define_expand "udivsi3" 1249: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1250: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1251: (match_operand:SI 2 "gpc_reg_operand" "")))] 1252: "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" 1253: " 1254: { 1255: if (! TARGET_POWER && ! TARGET_POWERPC) 1256: { 1257: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1258: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1259: emit_insn (gen_quous_call ()); 1260: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1261: DONE; 1262: } 1263: }") 1264: 1265: (define_insn "" 1.1.1.2 root 1266: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1267: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1268: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1269: "TARGET_POWERPC" 1.1.1.3 root 1270: "divwu %0,%1,%2" 1.1.1.2 root 1271: [(set_attr "type" "idiv")]) 1.1 root 1272: 1273: ;; For powers of two we can do srai/aze for divide and then adjust for 1.1.1.2 root 1274: ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 1.1.1.3 root 1275: ;; used; for PowerPC, force operands into register and do a normal divide; 1276: ;; for AIX common-mode, use quoss call on register operands. 1.1 root 1277: (define_expand "divsi3" 1278: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1279: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1280: (match_operand:SI 2 "reg_or_cint_operand" "")))] 1281: "" 1282: " 1283: { 1.1.1.2 root 1284: if (GET_CODE (operands[2]) == CONST_INT 1285: && exact_log2 (INTVAL (operands[2])) >= 0) 1286: ; 1.1.1.3 root 1287: else if (TARGET_POWER && ! TARGET_POWERPC) 1.1 root 1288: FAIL; 1.1.1.2 root 1289: else 1290: operands[2] = force_reg (SImode, operands[2]); 1.1.1.3 root 1291: 1292: if (! TARGET_POWER && ! TARGET_POWERPC) 1293: { 1294: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1295: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1296: emit_insn (gen_quoss_call ()); 1297: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1298: DONE; 1299: } 1.1 root 1300: }") 1301: 1302: (define_expand "modsi3" 1.1.1.2 root 1303: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1304: (use (match_operand:SI 1 "gpc_reg_operand" "")) 1305: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 1.1 root 1306: "" 1307: " 1308: { 1309: int i = exact_log2 (INTVAL (operands[2])); 1.1.1.2 root 1310: rtx temp1; 1311: rtx temp2; 1.1 root 1312: 1313: if (GET_CODE (operands[2]) != CONST_INT || i < 0) 1314: FAIL; 1315: 1.1.1.2 root 1316: temp1 = gen_reg_rtx (SImode); 1317: temp2 = gen_reg_rtx (SImode); 1318: 1319: emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); 1320: emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); 1321: emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); 1322: DONE; 1.1 root 1323: }") 1324: 1325: (define_insn "" 1326: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1327: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1328: (match_operand:SI 2 "const_int_operand" "N")))] 1329: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1330: "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" 1331: [(set_attr "length" "8")]) 1.1 root 1332: 1333: (define_insn "" 1334: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1335: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1336: (match_operand:SI 2 "const_int_operand" "N")) 1337: (const_int 0))) 1.1 root 1338: (clobber (match_scratch:SI 3 "=r"))] 1339: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1340: "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" 1341: [(set_attr "type" "compare") 1342: (set_attr "length" "8")]) 1.1 root 1343: 1344: (define_insn "" 1345: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1346: (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1347: (match_operand:SI 2 "const_int_operand" "N")) 1348: (const_int 0))) 1.1 root 1349: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1350: (div:SI (match_dup 1) (match_dup 2)))] 1351: "exact_log2 (INTVAL (operands[2])) >= 0" 1.1.1.2 root 1352: "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" 1353: [(set_attr "type" "compare") 1354: (set_attr "length" "8")]) 1.1 root 1355: 1356: (define_insn "" 1357: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1358: (udiv:SI 1.1.1.3 root 1359: (plus:DI (ashift:DI 1.1 root 1360: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1361: (const_int 32)) 1362: (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 1363: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1364: (set (match_operand:SI 2 "register_operand" "=*q") 1365: (umod:SI 1.1.1.3 root 1366: (plus:DI (ashift:DI 1.1 root 1367: (zero_extend:DI (match_dup 1)) (const_int 32)) 1368: (zero_extend:DI (match_dup 4))) 1369: (match_dup 3)))] 1.1.1.2 root 1370: "TARGET_POWER" 1371: "div %0,%1,%3" 1372: [(set_attr "type" "idiv")]) 1.1 root 1373: 1374: ;; To do unsigned divide we handle the cases of the divisor looking like a 1375: ;; negative number. If it is a constant that is less than 2**31, we don't 1376: ;; have to worry about the branches. So make a few subroutines here. 1377: ;; 1378: ;; First comes the normal case. 1379: (define_expand "udivmodsi4_normal" 1380: [(set (match_dup 4) (const_int 0)) 1381: (parallel [(set (match_operand:SI 0 "" "") 1.1.1.3 root 1382: (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1383: (const_int 32)) 1384: (zero_extend:DI (match_operand:SI 1 "" ""))) 1385: (match_operand:SI 2 "" ""))) 1386: (set (match_operand:SI 3 "" "") 1.1.1.3 root 1387: (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 1.1 root 1388: (const_int 32)) 1389: (zero_extend:DI (match_dup 1))) 1390: (match_dup 2)))])] 1.1.1.2 root 1391: "TARGET_POWER" 1.1 root 1392: " 1393: { operands[4] = gen_reg_rtx (SImode); }") 1394: 1395: ;; This handles the branches. 1396: (define_expand "udivmodsi4_tests" 1397: [(set (match_operand:SI 0 "" "") (const_int 0)) 1398: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 1399: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 1400: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 1401: (label_ref (match_operand:SI 4 "" "")) (pc))) 1402: (set (match_dup 0) (const_int 1)) 1403: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 1404: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 1405: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 1406: (label_ref (match_dup 4)) (pc)))] 1.1.1.2 root 1407: "TARGET_POWER" 1.1 root 1408: " 1409: { operands[5] = gen_reg_rtx (CCUNSmode); 1410: operands[6] = gen_reg_rtx (CCmode); 1411: }") 1412: 1413: (define_expand "udivmodsi4" 1414: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1415: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1416: (match_operand:SI 2 "reg_or_cint_operand" ""))) 1417: (set (match_operand:SI 3 "gpc_reg_operand" "") 1418: (umod:SI (match_dup 1) (match_dup 2)))])] 1.1.1.3 root 1419: "" 1.1 root 1420: " 1421: { 1422: rtx label = 0; 1423: 1.1.1.3 root 1424: if (! TARGET_POWER) 1425: if (! TARGET_POWERPC) 1426: { 1427: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 1428: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 1429: emit_insn (gen_divus_call ()); 1430: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 1431: emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); 1432: DONE; 1433: } 1434: else 1435: FAIL; 1436: 1.1 root 1437: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 1438: { 1439: operands[2] = force_reg (SImode, operands[2]); 1440: label = gen_label_rtx (); 1441: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 1442: operands[3], label)); 1443: } 1444: else 1445: operands[2] = force_reg (SImode, operands[2]); 1446: 1447: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 1448: operands[3])); 1449: if (label) 1450: emit_label (label); 1451: 1452: DONE; 1453: }") 1.1.1.3 root 1454: 1455: ;; AIX architecture-independent common-mode multiply (DImode), 1456: ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and 1.1.1.4 root 1457: ;; R4; results in R3 and sometimes R4; link register always clobbered by bla 1.1.1.3 root 1458: ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but 1459: ;; assumed unused if generating common-mode, so ignore. 1460: (define_insn "mulh_call" 1461: [(set (reg:SI 3) 1462: (truncate:SI 1463: (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) 1464: (sign_extend:DI (reg:SI 4))) 1465: (const_int 32)))) 1466: (clobber (match_scratch:SI 0 "=l"))] 1467: "! TARGET_POWER && ! TARGET_POWERPC" 1468: "bla __mulh") 1469: 1470: (define_insn "mull_call" 1471: [(set (reg:DI 3) 1472: (mult:DI (sign_extend:DI (reg:SI 3)) 1473: (sign_extend:DI (reg:SI 4)))) 1474: (clobber (match_scratch:SI 0 "=l")) 1475: (clobber (reg:SI 0))] 1476: "! TARGET_POWER && ! TARGET_POWERPC" 1477: "bla __mull") 1478: 1479: (define_insn "divss_call" 1480: [(set (reg:SI 3) 1481: (div:SI (reg:SI 3) (reg:SI 4))) 1482: (set (reg:SI 4) 1483: (mod:SI (reg:SI 3) (reg:SI 4))) 1484: (clobber (match_scratch:SI 0 "=l")) 1485: (clobber (reg:SI 0))] 1486: "! TARGET_POWER && ! TARGET_POWERPC" 1487: "bla __divss") 1488: 1489: (define_insn "divus_call" 1490: [(set (reg:SI 3) 1491: (udiv:SI (reg:SI 3) (reg:SI 4))) 1492: (set (reg:SI 4) 1493: (umod:SI (reg:SI 3) (reg:SI 4))) 1494: (clobber (match_scratch:SI 0 "=l")) 1.1.1.5 ! root 1495: (clobber (reg:SI 0)) ! 1496: (clobber (match_scratch:CC 1 "=x")) ! 1497: (clobber (reg:CC 69))] 1.1.1.3 root 1498: "! TARGET_POWER && ! TARGET_POWERPC" 1499: "bla __divus") 1500: 1501: (define_insn "quoss_call" 1502: [(set (reg:SI 3) 1503: (div:SI (reg:SI 3) (reg:SI 4))) 1504: (clobber (match_scratch:SI 0 "=l"))] 1505: "! TARGET_POWER && ! TARGET_POWERPC" 1506: "bla __quoss") 1507: 1508: (define_insn "quous_call" 1509: [(set (reg:SI 3) 1510: (udiv:SI (reg:SI 3) (reg:SI 4))) 1511: (clobber (match_scratch:SI 0 "=l")) 1.1.1.5 ! root 1512: (clobber (reg:SI 0)) ! 1513: (clobber (match_scratch:CC 1 "=x")) ! 1514: (clobber (reg:CC 69))] 1.1.1.3 root 1515: "! TARGET_POWER && ! TARGET_POWERPC" 1516: "bla __quous") 1517: 1.1 root 1518: (define_insn "andsi3" 1519: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1520: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1521: (match_operand:SI 2 "and_operand" "?r,L,K,J"))) 1522: (clobber (match_scratch:CC 3 "=X,X,x,x"))] 1523: "" 1524: "@ 1525: and %0,%1,%2 1.1.1.2 root 1526: {rlinm|rlwinm} %0,%1,0,%m2,%M2 1527: {andil.|andi.} %0,%1,%b2 1528: {andiu.|andis.} %0,%1,%u2") 1.1 root 1529: 1530: (define_insn "" 1531: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") 1532: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1533: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1534: (const_int 0))) 1535: (clobber (match_scratch:SI 3 "=r,r,r,r"))] 1536: "" 1537: "@ 1538: and. %3,%1,%2 1.1.1.2 root 1539: {andil.|andi.} %3,%1,%b2 1540: {andiu.|andis.} %3,%1,%u2 1541: {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" 1.1 root 1542: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1543: 1544: (define_insn "" 1545: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") 1546: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1547: (match_operand:SI 2 "and_operand" "r,K,J,L")) 1548: (const_int 0))) 1549: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1550: (and:SI (match_dup 1) (match_dup 2)))] 1551: "" 1552: "@ 1553: and. %0,%1,%2 1.1.1.2 root 1554: {andil.|andi.} %0,%1,%b2 1555: {andiu.|andis.} %0,%1,%u2 1556: {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" 1557: [(set_attr "type" "compare,compare,compare,delayed_compare")]) 1.1 root 1558: 1559: ;; Take a AND with a constant that cannot be done in a single insn and try to 1560: ;; split it into two insns. This does not verify that the insns are valid 1561: ;; since this need not be done as combine will do it. 1562: 1563: (define_split 1564: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1565: (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1566: (match_operand:SI 2 "non_and_cint_operand" "")))] 1567: "" 1568: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) 1569: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] 1570: " 1571: { 1572: int maskval = INTVAL (operands[2]); 1573: int i, transitions, last_bit_value; 1574: int orig = maskval, first_c = maskval, second_c; 1575: 1576: /* We know that MASKVAL must have more than 2 bit-transitions. Start at 1577: the low-order bit and count for the third transition. When we get there, 1578: make a first mask that has everything to the left of that position 1579: a one. Then make the second mask to turn off whatever else is needed. */ 1580: 1581: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) 1582: { 1583: if (((maskval >>= 1) & 1) != last_bit_value) 1584: last_bit_value ^= 1, transitions++; 1585: 1586: if (transitions > 2) 1587: { 1588: first_c |= (~0) << i; 1589: break; 1590: } 1591: } 1592: 1593: second_c = orig | ~ first_c; 1594: 1595: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); 1596: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); 1597: }") 1598: 1599: (define_insn "iorsi3" 1600: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1601: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1602: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1603: "" 1604: "@ 1605: or %0,%1,%2 1.1.1.2 root 1606: {oril|ori} %0,%1,%b2 1607: {oriu|oris} %0,%1,%u2") 1.1 root 1608: 1609: (define_insn "" 1610: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1611: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1612: (match_operand:SI 2 "gpc_reg_operand" "r")) 1613: (const_int 0))) 1614: (clobber (match_scratch:SI 3 "=r"))] 1615: "" 1616: "or. %3,%1,%2" 1617: [(set_attr "type" "compare")]) 1618: 1619: (define_insn "" 1620: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1621: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1622: (match_operand:SI 2 "gpc_reg_operand" "r")) 1623: (const_int 0))) 1624: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1625: (ior:SI (match_dup 1) (match_dup 2)))] 1626: "" 1627: "or. %0,%1,%2" 1628: [(set_attr "type" "compare")]) 1629: 1630: ;; Split an IOR that we can't do in one insn into two insns, each of which 1631: ;; does one 16-bit part. This is used by combine. 1632: 1633: (define_split 1634: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1635: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 1636: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1637: "" 1638: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) 1639: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] 1640: " 1641: { 1642: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1643: INTVAL (operands[2]) & 0xffff0000); 1644: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1645: }") 1646: 1647: (define_insn "xorsi3" 1648: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 1649: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 1650: (match_operand:SI 2 "logical_operand" "r,K,J")))] 1651: "" 1652: "@ 1653: xor %0,%1,%2 1.1.1.2 root 1654: {xoril|xori} %0,%1,%b2 1655: {xoriu|xoris} %0,%1,%u2") 1.1 root 1656: 1657: (define_insn "" 1658: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1659: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1660: (match_operand:SI 2 "gpc_reg_operand" "r")) 1661: (const_int 0))) 1662: (clobber (match_scratch:SI 3 "=r"))] 1663: "" 1664: "xor. %3,%1,%2" 1665: [(set_attr "type" "compare")]) 1666: 1667: (define_insn "" 1668: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1669: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1670: (match_operand:SI 2 "gpc_reg_operand" "r")) 1671: (const_int 0))) 1672: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1673: (xor:SI (match_dup 1) (match_dup 2)))] 1674: "" 1675: "xor. %0,%1,%2" 1676: [(set_attr "type" "compare")]) 1677: 1678: ;; Split an XOR that we can't do in one insn into two insns, each of which 1679: ;; does one 16-bit part. This is used by combine. 1680: 1681: (define_split 1682: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1683: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1684: (match_operand:SI 2 "non_logical_cint_operand" "")))] 1685: "" 1686: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) 1687: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] 1688: " 1689: { 1690: operands[3] = gen_rtx (CONST_INT, VOIDmode, 1691: INTVAL (operands[2]) & 0xffff0000); 1692: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); 1693: }") 1694: 1695: (define_insn "" 1696: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1697: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1698: (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1699: "" 1700: "eqv %0,%1,%2") 1701: 1702: (define_insn "" 1703: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1704: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1705: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1706: (const_int 0))) 1707: (clobber (match_scratch:SI 3 "=r"))] 1708: "" 1709: "eqv. %3,%1,%2" 1710: [(set_attr "type" "compare")]) 1711: 1712: (define_insn "" 1713: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1714: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1715: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1716: (const_int 0))) 1717: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1718: (not:SI (xor:SI (match_dup 1) (match_dup 2))))] 1719: "" 1720: "eqv. %0,%1,%2" 1721: [(set_attr "type" "compare")]) 1722: 1723: (define_insn "" 1724: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1725: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1726: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1727: "" 1728: "andc %0,%2,%1") 1729: 1730: (define_insn "" 1731: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1732: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1733: (match_operand:SI 2 "gpc_reg_operand" "r")) 1734: (const_int 0))) 1735: (clobber (match_scratch:SI 3 "=r"))] 1736: "" 1737: "andc. %3,%2,%1" 1738: [(set_attr "type" "compare")]) 1739: 1740: (define_insn "" 1741: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1742: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1743: (match_operand:SI 2 "gpc_reg_operand" "r")) 1744: (const_int 0))) 1745: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1746: (and:SI (not:SI (match_dup 1)) (match_dup 2)))] 1747: "" 1748: "andc. %0,%2,%1" 1749: [(set_attr "type" "compare")]) 1750: 1751: (define_insn "" 1752: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1753: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1754: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1755: "" 1756: "orc %0,%2,%1") 1757: 1758: (define_insn "" 1759: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1760: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1761: (match_operand:SI 2 "gpc_reg_operand" "r")) 1762: (const_int 0))) 1763: (clobber (match_scratch:SI 3 "=r"))] 1764: "" 1765: "orc. %3,%2,%1" 1766: [(set_attr "type" "compare")]) 1767: 1768: (define_insn "" 1769: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1770: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1771: (match_operand:SI 2 "gpc_reg_operand" "r")) 1772: (const_int 0))) 1773: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1774: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] 1775: "" 1776: "orc. %0,%2,%1" 1777: [(set_attr "type" "compare")]) 1778: 1779: (define_insn "" 1780: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 1781: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1782: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1783: "" 1784: "nand %0,%1,%2") 1785: 1786: (define_insn "" 1787: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1788: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1789: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1790: (const_int 0))) 1791: (clobber (match_scratch:SI 3 "=r"))] 1792: "" 1793: "nand. %3,%1,%2" 1794: [(set_attr "type" "compare")]) 1795: 1796: (define_insn "" 1797: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1798: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1799: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1800: (const_int 0))) 1801: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1802: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1803: "" 1804: "nand. %0,%1,%2" 1805: [(set_attr "type" "compare")]) 1806: 1807: (define_insn "" 1808: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 1809: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1810: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1811: "" 1812: "nor %0,%1,%2") 1813: 1814: (define_insn "" 1815: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1.1.3 root 1816: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1817: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1818: (const_int 0))) 1819: (clobber (match_scratch:SI 3 "=r"))] 1820: "" 1821: "nor. %3,%1,%2" 1822: [(set_attr "type" "compare")]) 1823: 1824: (define_insn "" 1825: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1.1.3 root 1826: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1827: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) 1828: (const_int 0))) 1829: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1830: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] 1831: "" 1832: "nor. %0,%1,%2" 1833: [(set_attr "type" "compare")]) 1834: 1835: ;; maskir insn. We need four forms because things might be in arbitrary 1836: ;; orders. Don't define forms that only set CR fields because these 1837: ;; would modify an input register. 1838: 1839: (define_insn "" 1840: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1841: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1842: (match_operand:SI 1 "gpc_reg_operand" "0")) 1843: (and:SI (match_dup 2) 1844: (match_operand:SI 3 "gpc_reg_operand" "r"))))] 1.1.1.2 root 1845: "TARGET_POWER" 1.1 root 1846: "maskir %0,%3,%2") 1847: 1848: (define_insn "" 1.1.1.4 root 1849: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1850: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1851: (match_operand:SI 1 "gpc_reg_operand" "0")) 1852: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1853: (match_dup 2))))] 1.1.1.2 root 1854: "TARGET_POWER" 1.1 root 1855: "maskir %0,%3,%2") 1856: 1857: (define_insn "" 1858: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1859: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1860: (match_operand:SI 3 "gpc_reg_operand" "r")) 1861: (and:SI (not:SI (match_dup 2)) 1862: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1863: "TARGET_POWER" 1.1 root 1864: "maskir %0,%3,%2") 1865: 1866: (define_insn "" 1867: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1868: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1869: (match_operand:SI 2 "gpc_reg_operand" "r")) 1870: (and:SI (not:SI (match_dup 2)) 1871: (match_operand:SI 1 "gpc_reg_operand" "0"))))] 1.1.1.2 root 1872: "TARGET_POWER" 1.1 root 1873: "maskir %0,%3,%2") 1874: 1875: (define_insn "" 1876: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1877: (compare:CC 1878: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1879: (match_operand:SI 1 "gpc_reg_operand" "0")) 1880: (and:SI (match_dup 2) 1881: (match_operand:SI 3 "gpc_reg_operand" "r"))) 1882: (const_int 0))) 1883: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1884: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1885: (and:SI (match_dup 2) (match_dup 3))))] 1.1.1.2 root 1886: "TARGET_POWER" 1.1 root 1887: "maskir. %0,%3,%2" 1888: [(set_attr "type" "compare")]) 1889: 1890: (define_insn "" 1891: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1892: (compare:CC 1893: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 1894: (match_operand:SI 1 "gpc_reg_operand" "0")) 1895: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1896: (match_dup 2))) 1897: (const_int 0))) 1.1.1.4 root 1898: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1899: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 1900: (and:SI (match_dup 3) (match_dup 2))))] 1.1.1.2 root 1901: "TARGET_POWER" 1.1 root 1902: "maskir. %0,%3,%2" 1903: [(set_attr "type" "compare")]) 1904: 1905: (define_insn "" 1906: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1907: (compare:CC 1908: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1909: (match_operand:SI 3 "gpc_reg_operand" "r")) 1910: (and:SI (not:SI (match_dup 2)) 1911: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1912: (const_int 0))) 1913: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1914: (ior:SI (and:SI (match_dup 2) (match_dup 3)) 1915: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1916: "TARGET_POWER" 1.1 root 1917: "maskir. %0,%3,%2" 1918: [(set_attr "type" "compare")]) 1919: 1920: (define_insn "" 1921: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 1922: (compare:CC 1923: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1924: (match_operand:SI 2 "gpc_reg_operand" "r")) 1925: (and:SI (not:SI (match_dup 2)) 1926: (match_operand:SI 1 "gpc_reg_operand" "0"))) 1927: (const_int 0))) 1928: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1929: (ior:SI (and:SI (match_dup 3) (match_dup 2)) 1930: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 1.1.1.2 root 1931: "TARGET_POWER" 1.1 root 1932: "maskir. %0,%3,%2" 1933: [(set_attr "type" "compare")]) 1934: 1935: ;; Rotate and shift insns, in all their variants. These support shifts, 1936: ;; field inserts and extracts, and various combinations thereof. 1.1.1.4 root 1937: (define_expand "insv" 1938: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1939: (match_operand:SI 1 "const_int_operand" "i") 1940: (match_operand:SI 2 "const_int_operand" "i")) 1941: (match_operand:SI 3 "gpc_reg_operand" "r"))] 1942: "" 1943: " 1944: { 1945: /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 1946: the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 1947: compiler if the address of the structure is taken later. */ 1948: if (GET_CODE (operands[0]) == SUBREG 1949: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 1950: FAIL; 1951: }") 1952: 1953: (define_insn "" 1.1 root 1954: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1955: (match_operand:SI 1 "const_int_operand" "i") 1956: (match_operand:SI 2 "const_int_operand" "i")) 1957: (match_operand:SI 3 "gpc_reg_operand" "r"))] 1958: "" 1959: "* 1960: { 1961: int start = INTVAL (operands[2]) & 31; 1962: int size = INTVAL (operands[1]) & 31; 1963: 1964: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); 1965: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 1.1.1.2 root 1966: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 1.1 root 1967: }") 1968: 1.1.1.4 root 1969: (define_insn "" 1970: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1971: (match_operand:SI 1 "const_int_operand" "i") 1972: (match_operand:SI 2 "const_int_operand" "i")) 1973: (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1974: (match_operand:SI 4 "const_int_operand" "i")))] 1975: "" 1976: "* 1977: { 1978: int shift = INTVAL (operands[4]) & 31; 1979: int start = INTVAL (operands[2]) & 31; 1980: int size = INTVAL (operands[1]) & 31; 1981: 1982: operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31); 1983: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 1984: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 1985: }") 1986: 1987: (define_insn "" 1988: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1989: (match_operand:SI 1 "const_int_operand" "i") 1990: (match_operand:SI 2 "const_int_operand" "i")) 1991: (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 1992: (match_operand:SI 4 "const_int_operand" "i")))] 1993: "" 1994: "* 1995: { 1996: int shift = INTVAL (operands[4]) & 31; 1997: int start = INTVAL (operands[2]) & 31; 1998: int size = INTVAL (operands[1]) & 31; 1999: 2000: operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31); 2001: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 2002: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 2003: }") 2004: 2005: (define_insn "" 2006: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2007: (match_operand:SI 1 "const_int_operand" "i") 2008: (match_operand:SI 2 "const_int_operand" "i")) 2009: (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2010: (match_operand:SI 4 "const_int_operand" "i")))] 2011: "" 2012: "* 2013: { 2014: int shift = INTVAL (operands[4]) & 31; 2015: int start = INTVAL (operands[2]) & 31; 2016: int size = INTVAL (operands[1]) & 31; 2017: 2018: operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31); 2019: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); 2020: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; 2021: }") 2022: 2023: (define_insn "" 2024: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2025: (match_operand:SI 1 "const_int_operand" "i") 2026: (match_operand:SI 2 "const_int_operand" "i")) 2027: (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2028: (match_operand:SI 4 "const_int_operand" "i") 2029: (match_operand:SI 5 "const_int_operand" "i")))] 2030: "INTVAL (operands[4]) >= INTVAL (operands[1])" 2031: "* 2032: { 2033: int extract_start = INTVAL (operands[5]) & 31; 2034: int extract_size = INTVAL (operands[4]) & 31; 2035: int insert_start = INTVAL (operands[2]) & 31; 2036: int insert_size = INTVAL (operands[1]) & 31; 2037: 2038: /* Align extract field with insert field */ 2039: operands[5] = gen_rtx (CONST_INT, VOIDmode, 2040: (extract_start + extract_size - insert_start - insert_size) & 31); 2041: operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1); 2042: return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\"; 2043: }") 2044: 2045: (define_expand "extzv" 2046: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2047: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2048: (match_operand:SI 2 "const_int_operand" "i") 2049: (match_operand:SI 3 "const_int_operand" "i")))] 2050: "" 2051: " 2052: { 2053: /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 2054: the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 2055: compiler if the address of the structure is taken later. */ 2056: if (GET_CODE (operands[0]) == SUBREG 2057: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 2058: FAIL; 2059: }") 2060: 2061: (define_insn "" 1.1 root 2062: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2063: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2064: (match_operand:SI 2 "const_int_operand" "i") 2065: (match_operand:SI 3 "const_int_operand" "i")))] 2066: "" 2067: "* 2068: { 2069: int start = INTVAL (operands[3]) & 31; 2070: int size = INTVAL (operands[2]) & 31; 2071: 2072: if (start + size >= 32) 2073: operands[3] = const0_rtx; 2074: else 2075: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2076: return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 1.1 root 2077: }") 2078: 2079: (define_insn "" 2080: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2081: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2082: (match_operand:SI 2 "const_int_operand" "i") 2083: (match_operand:SI 3 "const_int_operand" "i")) 2084: (const_int 0))) 2085: (clobber (match_scratch:SI 4 "=r"))] 2086: "" 2087: "* 2088: { 2089: int start = INTVAL (operands[3]) & 31; 2090: int size = INTVAL (operands[2]) & 31; 2091: 2092: /* If the bitfield being tested fits in the upper or lower half of a 2093: word, it is possible to use andiu. or andil. to test it. This is 2094: useful because the condition register set-use delay is smaller for 2095: andi[ul]. than for rlinm. This doesn't work when the starting bit 2096: position is 0 because the LT and GT bits may be set wrong. */ 2097: 2098: if ((start > 0 && start + size <= 16) || start >= 16) 2099: { 2100: operands[3] = gen_rtx (CONST_INT, VOIDmode, 2101: ((1 << (16 - (start & 15))) 2102: - (1 << (16 - (start & 15) - size)))); 2103: if (start < 16) 1.1.1.2 root 2104: return \"{andiu.|andis.} %4,%1,%3\"; 1.1 root 2105: else 1.1.1.2 root 2106: return \"{andil.|andi.} %4,%1,%3\"; 1.1 root 2107: } 1.1.1.4 root 2108: 1.1 root 2109: if (start + size >= 32) 2110: operands[3] = const0_rtx; 2111: else 2112: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2113: return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 1.1 root 2114: }" 2115: [(set_attr "type" "compare")]) 2116: 2117: (define_insn "" 2118: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2119: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2120: (match_operand:SI 2 "const_int_operand" "i") 2121: (match_operand:SI 3 "const_int_operand" "i")) 2122: (const_int 0))) 2123: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2124: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 2125: "" 2126: "* 2127: { 2128: int start = INTVAL (operands[3]) & 31; 2129: int size = INTVAL (operands[2]) & 31; 2130: 2131: if (start >= 16 && start + size == 32) 2132: { 2133: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); 1.1.1.2 root 2134: return \"{andil.|andi.} %0,%1,%3\"; 1.1 root 2135: } 1.1.1.4 root 2136: 1.1 root 2137: if (start + size >= 32) 2138: operands[3] = const0_rtx; 2139: else 2140: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); 1.1.1.2 root 2141: return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 1.1 root 2142: }" 2143: [(set_attr "type" "delayed_compare")]) 2144: 2145: (define_insn "rotlsi3" 2146: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2147: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2148: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2149: "" 1.1.1.2 root 2150: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 1.1 root 2151: 2152: (define_insn "" 2153: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2154: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2155: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2156: (const_int 0))) 2157: (clobber (match_scratch:SI 3 "=r"))] 2158: "" 1.1.1.2 root 2159: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" 1.1 root 2160: [(set_attr "type" "delayed_compare")]) 2161: 2162: (define_insn "" 2163: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2164: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2165: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2166: (const_int 0))) 2167: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2168: (rotate:SI (match_dup 1) (match_dup 2)))] 2169: "" 1.1.1.2 root 2170: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" 1.1 root 2171: [(set_attr "type" "delayed_compare")]) 2172: 2173: (define_insn "" 2174: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2175: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2176: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2177: (match_operand:SI 3 "mask_operand" "L")))] 2178: "" 1.1.1.2 root 2179: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 1.1 root 2180: 2181: (define_insn "" 2182: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2183: (compare:CC (and:SI 2184: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2185: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2186: (match_operand:SI 3 "mask_operand" "L")) 2187: (const_int 0))) 2188: (clobber (match_scratch:SI 4 "=r"))] 2189: "" 1.1.1.2 root 2190: "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" 1.1 root 2191: [(set_attr "type" "delayed_compare")]) 2192: 2193: (define_insn "" 2194: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2195: (compare:CC (and:SI 2196: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2197: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2198: (match_operand:SI 3 "mask_operand" "L")) 2199: (const_int 0))) 2200: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2201: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2202: "" 1.1.1.2 root 2203: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" 1.1 root 2204: [(set_attr "type" "delayed_compare")]) 2205: 2206: (define_insn "" 2207: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2208: (zero_extend:SI 2209: (subreg:QI 2210: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2211: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2212: "" 1.1.1.2 root 2213: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 1.1 root 2214: 2215: (define_insn "" 2216: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2217: (compare:CC (zero_extend:SI 2218: (subreg:QI 2219: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2220: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2221: (const_int 0))) 2222: (clobber (match_scratch:SI 3 "=r"))] 2223: "" 1.1.1.2 root 2224: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" 1.1 root 2225: [(set_attr "type" "delayed_compare")]) 2226: 2227: (define_insn "" 2228: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2229: (compare:CC (zero_extend:SI 2230: (subreg:QI 2231: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2232: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2233: (const_int 0))) 2234: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2235: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2236: "" 1.1.1.2 root 2237: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" 1.1 root 2238: [(set_attr "type" "delayed_compare")]) 2239: 2240: (define_insn "" 2241: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2242: (zero_extend:SI 2243: (subreg:HI 2244: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2245: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 2246: "" 1.1.1.2 root 2247: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 1.1 root 2248: 2249: (define_insn "" 2250: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2251: (compare:CC (zero_extend:SI 2252: (subreg:HI 2253: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2254: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2255: (const_int 0))) 2256: (clobber (match_scratch:SI 3 "=r"))] 2257: "" 1.1.1.2 root 2258: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" 1.1 root 2259: [(set_attr "type" "delayed_compare")]) 2260: 2261: (define_insn "" 2262: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2263: (compare:CC (zero_extend:SI 2264: (subreg:HI 2265: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2266: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) 2267: (const_int 0))) 2268: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2269: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 2270: "" 1.1.1.2 root 2271: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" 1.1 root 2272: [(set_attr "type" "delayed_compare")]) 2273: 2274: ;; Note that we use "sle." instead of "sl." so that we can set 2275: ;; SHIFT_COUNT_TRUNCATED. 2276: 1.1.1.2 root 2277: (define_expand "ashlsi3" 2278: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2279: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2280: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2281: "" 2282: " 2283: { 2284: if (TARGET_POWER) 2285: emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 2286: else 2287: emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 2288: DONE; 2289: }") 2290: 2291: (define_insn "ashlsi3_power" 1.1 root 2292: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2293: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2294: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2295: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2296: "TARGET_POWER" 1.1 root 2297: "@ 2298: sle %0,%1,%2 1.1.1.2 root 2299: {sli|slwi} %0,%1,%h2" 2300: [(set_attr "length" "8")]) 2301: 2302: (define_insn "ashlsi3_no_power" 2303: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2304: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2305: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2306: "! TARGET_POWER" 1.1.1.4 root 2307: "{sl|slw}%I2 %0,%1,%h2" 1.1.1.2 root 2308: [(set_attr "length" "8")]) 1.1 root 2309: 2310: (define_insn "" 2311: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2312: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2313: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2314: (const_int 0))) 2315: (clobber (match_scratch:SI 3 "=r,r")) 2316: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2317: "TARGET_POWER" 1.1 root 2318: "@ 2319: sle. %3,%1,%2 1.1.1.2 root 2320: {sli.|slwi.} %3,%1,%h2" 2321: [(set_attr "type" "delayed_compare")]) 2322: 2323: (define_insn "" 2324: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2325: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2326: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2327: (const_int 0))) 2328: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.3 root 2329: "! TARGET_POWER" 1.1.1.4 root 2330: "{sl|slw}%I2. %3,%1,%h2" 1.1 root 2331: [(set_attr "type" "delayed_compare")]) 2332: 2333: (define_insn "" 2334: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2335: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2336: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2337: (const_int 0))) 2338: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2339: (ashift:SI (match_dup 1) (match_dup 2))) 2340: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2341: "TARGET_POWER" 1.1 root 2342: "@ 2343: sle. %0,%1,%2 1.1.1.2 root 2344: {sli.|slwi.} %0,%1,%h2" 2345: [(set_attr "type" "delayed_compare")]) 2346: 2347: (define_insn "" 2348: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2349: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2350: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2351: (const_int 0))) 2352: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2353: (ashift:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 2354: "! TARGET_POWER" 1.1.1.4 root 2355: "{sl|slw}%I2. %0,%1,%h2" 1.1 root 2356: [(set_attr "type" "delayed_compare")]) 2357: 2358: (define_insn "" 2359: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2360: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2361: (match_operand:SI 2 "const_int_operand" "i")) 2362: (match_operand:SI 3 "mask_operand" "L")))] 2363: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 root 2364: "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") 1.1 root 2365: 2366: (define_insn "" 2367: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2368: (compare:CC 2369: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2370: (match_operand:SI 2 "const_int_operand" "i")) 2371: (match_operand:SI 3 "mask_operand" "L")) 2372: (const_int 0))) 2373: (clobber (match_scratch:SI 4 "=r"))] 2374: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 root 2375: "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" 1.1 root 2376: [(set_attr "type" "delayed_compare")]) 2377: 2378: (define_insn "" 2379: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2380: (compare:CC 2381: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2382: (match_operand:SI 2 "const_int_operand" "i")) 2383: (match_operand:SI 3 "mask_operand" "L")) 2384: (const_int 0))) 2385: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2386: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2387: "includes_lshift_p (operands[2], operands[3])" 1.1.1.4 root 2388: "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" 1.1 root 2389: [(set_attr "type" "delayed_compare")]) 2390: 1.1.1.2 root 2391: ;; The AIX assembler mis-handles "sri x,x,0", so write that case as 1.1 root 2392: ;; "sli x,x,0". 1.1.1.2 root 2393: (define_expand "lshrsi3" 2394: [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2395: (use (match_operand:SI 1 "gpc_reg_operand" "")) 2396: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2397: "" 2398: " 2399: { 2400: if (TARGET_POWER) 2401: emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 2402: else 2403: emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 2404: DONE; 2405: }") 2406: 2407: (define_insn "lshrsi3_power" 1.1 root 2408: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2409: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2410: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2411: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2412: "TARGET_POWER" 1.1 root 2413: "@ 2414: sre %0,%1,%2 1.1.1.2 root 2415: {s%A2i|s%A2wi} %0,%1,%h2") 2416: 2417: (define_insn "lshrsi3_no_power" 2418: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2419: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2420: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2421: "! TARGET_POWER" 1.1.1.4 root 2422: "{sr|srw}%I2 %0,%1,%h2") 1.1 root 2423: 2424: (define_insn "" 2425: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2426: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2427: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2428: (const_int 0))) 2429: (clobber (match_scratch:SI 3 "=r,r")) 2430: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2431: "TARGET_POWER" 1.1 root 2432: "@ 2433: sre. %3,%1,%2 1.1.1.2 root 2434: {s%A2i.|s%A2wi.} %3,%1,%h2" 2435: [(set_attr "type" "delayed_compare")]) 2436: 2437: (define_insn "" 2438: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2439: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2440: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2441: (const_int 0))) 2442: (clobber (match_scratch:SI 3 "=r"))] 2443: "! TARGET_POWER" 1.1.1.4 root 2444: "{sr|srw}%I2. %3,%1,%h2" 1.1 root 2445: [(set_attr "type" "delayed_compare")]) 2446: 2447: (define_insn "" 2448: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2449: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2450: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2451: (const_int 0))) 2452: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2453: (lshiftrt:SI (match_dup 1) (match_dup 2))) 2454: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2455: "TARGET_POWER" 1.1 root 2456: "@ 2457: sre. %0,%1,%2 1.1.1.2 root 2458: {s%A2i.|s%A2wi.} %0,%1,%h2" 2459: [(set_attr "type" "delayed_compare")]) 2460: 2461: (define_insn "" 2462: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2463: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2464: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2465: (const_int 0))) 2466: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2467: (lshiftrt:SI (match_dup 1) (match_dup 2)))] 2468: "! TARGET_POWER" 1.1.1.4 root 2469: "{sr|srw}%I2. %0,%1,%h2" 1.1 root 2470: [(set_attr "type" "delayed_compare")]) 2471: 2472: (define_insn "" 2473: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2474: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2475: (match_operand:SI 2 "const_int_operand" "i")) 2476: (match_operand:SI 3 "mask_operand" "L")))] 2477: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2478: "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 1.1 root 2479: 2480: (define_insn "" 2481: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2482: (compare:CC 2483: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2484: (match_operand:SI 2 "const_int_operand" "i")) 2485: (match_operand:SI 3 "mask_operand" "L")) 2486: (const_int 0))) 2487: (clobber (match_scratch:SI 4 "=r"))] 2488: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2489: "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" 1.1 root 2490: [(set_attr "type" "delayed_compare")]) 2491: 2492: (define_insn "" 2493: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 2494: (compare:CC 2495: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2496: (match_operand:SI 2 "const_int_operand" "i")) 2497: (match_operand:SI 3 "mask_operand" "L")) 2498: (const_int 0))) 2499: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2500: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 2501: "includes_rshift_p (operands[2], operands[3])" 1.1.1.2 root 2502: "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" 1.1 root 2503: [(set_attr "type" "delayed_compare")]) 2504: 2505: (define_insn "" 2506: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2507: (zero_extend:SI 2508: (subreg:QI 2509: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2510: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2511: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2512: "{rlinm|rlwinm} %0,%1,%s2,0xff") 1.1 root 2513: 2514: (define_insn "" 2515: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2516: (compare:CC 2517: (zero_extend:SI 2518: (subreg:QI 2519: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2520: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2521: (const_int 0))) 2522: (clobber (match_scratch:SI 3 "=r"))] 2523: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2524: "{rlinm.|rlwinm.} %3,%1,%s2,0xff" 1.1 root 2525: [(set_attr "type" "delayed_compare")]) 2526: 2527: (define_insn "" 2528: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2529: (compare:CC 2530: (zero_extend:SI 2531: (subreg:QI 2532: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2533: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2534: (const_int 0))) 2535: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2536: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2537: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" 1.1.1.2 root 2538: "{rlinm.|rlwinm.} %0,%1,%s2,0xff" 1.1 root 2539: [(set_attr "type" "delayed_compare")]) 2540: 2541: (define_insn "" 2542: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2543: (zero_extend:SI 2544: (subreg:HI 2545: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2546: (match_operand:SI 2 "const_int_operand" "i")) 0)))] 2547: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2548: "{rlinm|rlwinm} %0,%1,%s2,0xffff") 1.1 root 2549: 2550: (define_insn "" 2551: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2552: (compare:CC 2553: (zero_extend:SI 2554: (subreg:HI 2555: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2556: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2557: (const_int 0))) 2558: (clobber (match_scratch:SI 3 "=r"))] 2559: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2560: "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" 1.1 root 2561: [(set_attr "type" "delayed_compare")]) 2562: 2563: (define_insn "" 2564: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2565: (compare:CC 2566: (zero_extend:SI 2567: (subreg:HI 2568: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2569: (match_operand:SI 2 "const_int_operand" "i")) 0)) 2570: (const_int 0))) 2571: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2572: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 2573: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" 1.1.1.2 root 2574: "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" 1.1 root 2575: [(set_attr "type" "delayed_compare")]) 2576: 2577: (define_insn "" 2578: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2579: (const_int 1) 2580: (match_operand:SI 1 "gpc_reg_operand" "r")) 2581: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2582: (const_int 31)))] 1.1.1.2 root 2583: "TARGET_POWER" 1.1 root 2584: "rrib %0,%1,%2") 2585: 2586: (define_insn "" 2587: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2588: (const_int 1) 2589: (match_operand:SI 1 "gpc_reg_operand" "r")) 2590: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2591: (const_int 31)))] 1.1.1.2 root 2592: "TARGET_POWER" 1.1 root 2593: "rrib %0,%1,%2") 2594: 2595: (define_insn "" 2596: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2597: (const_int 1) 2598: (match_operand:SI 1 "gpc_reg_operand" "r")) 2599: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2600: (const_int 1) 2601: (const_int 0)))] 1.1.1.2 root 2602: "TARGET_POWER" 1.1 root 2603: "rrib %0,%1,%2") 2604: 1.1.1.2 root 2605: (define_expand "ashrsi3" 2606: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2607: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 2608: (match_operand:SI 2 "reg_or_cint_operand" "")))] 2609: "" 2610: " 2611: { 2612: if (TARGET_POWER) 2613: emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 2614: else 2615: emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 2616: DONE; 2617: }") 2618: 2619: (define_insn "ashrsi3_power" 1.1 root 2620: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2621: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2622: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 2623: (clobber (match_scratch:SI 3 "=q,X"))] 1.1.1.2 root 2624: "TARGET_POWER" 1.1 root 2625: "@ 2626: srea %0,%1,%2 1.1.1.2 root 2627: {srai|srawi} %0,%1,%h2") 2628: 2629: (define_insn "ashrsi3_no_power" 2630: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2631: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2632: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 2633: "! TARGET_POWER" 1.1.1.4 root 2634: "{sra|sraw}%I2 %0,%1,%h2") 1.1 root 2635: 2636: (define_insn "" 2637: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 2638: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2639: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2640: (const_int 0))) 2641: (clobber (match_scratch:SI 3 "=r,r")) 2642: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2643: "TARGET_POWER" 1.1 root 2644: "@ 2645: srea. %3,%1,%2 1.1.1.2 root 2646: {srai.|srawi.} %3,%1,%h2" 2647: [(set_attr "type" "delayed_compare")]) 2648: 2649: (define_insn "" 2650: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 2651: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2652: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2653: (const_int 0))) 2654: (clobber (match_scratch:SI 3 "=r"))] 2655: "! TARGET_POWER" 1.1.1.4 root 2656: "{sra|sraw}%I2. %3,%1,%h2" 1.1 root 2657: [(set_attr "type" "delayed_compare")]) 2658: 2659: (define_insn "" 2660: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 2661: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2662: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2663: (const_int 0))) 2664: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2665: (ashiftrt:SI (match_dup 1) (match_dup 2))) 2666: (clobber (match_scratch:SI 4 "=q,X"))] 1.1.1.2 root 2667: "TARGET_POWER" 1.1 root 2668: "@ 2669: srea. %0,%1,%2 1.1.1.2 root 2670: {srai.|srawi.} %0,%1,%h2" 2671: [(set_attr "type" "delayed_compare")]) 2672: 2673: (define_insn "" 2674: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 2675: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2676: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 2677: (const_int 0))) 2678: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 2679: (ashiftrt:SI (match_dup 1) (match_dup 2)))] 2680: "! TARGET_POWER" 1.1.1.4 root 2681: "{sra|sraw}%I2. %0,%1,%h2" 1.1 root 2682: [(set_attr "type" "delayed_compare")]) 2683: 2684: ;; Floating-point insns, excluding normal data motion. 2685: ;; 1.1.1.2 root 2686: ;; PowerPC has a full set of single-precision floating point instructions. 2687: ;; 2688: ;; For the POWER architecture, we pretend that we have both SFmode and 2689: ;; DFmode insns, while, in fact, all fp insns are actually done in double. 2690: ;; The only conversions we will do will be when storing to memory. In that 2691: ;; case, we will use the "frsp" instruction before storing. 1.1 root 2692: ;; 2693: ;; Note that when we store into a single-precision memory location, we need to 2694: ;; use the frsp insn first. If the register being stored isn't dead, we 2695: ;; need a scratch register for the frsp. But this is difficult when the store 2696: ;; is done by reload. It is not incorrect to do the frsp on the register in 2697: ;; this case, we just lose precision that we would have otherwise gotten but 2698: ;; is not guaranteed. Perhaps this should be tightened up at some point. 2699: 2700: (define_insn "extendsfdf2" 2701: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 2702: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2703: "TARGET_HARD_FLOAT" 1.1 root 2704: "* 2705: { 2706: if (REGNO (operands[0]) == REGNO (operands[1])) 2707: return \"\"; 2708: else 2709: return \"fmr %0,%1\"; 2710: }" 2711: [(set_attr "type" "fp")]) 2712: 2713: (define_insn "truncdfsf2" 2714: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2715: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2716: "TARGET_HARD_FLOAT" 2717: "frsp %0,%1" 2718: [(set_attr "type" "fp")]) 2719: 2720: (define_insn "aux_truncdfsf2" 2721: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2722: (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] 2723: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2724: "frsp %0,%1" 1.1 root 2725: [(set_attr "type" "fp")]) 2726: 2727: (define_insn "negsf2" 2728: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2729: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2730: "TARGET_HARD_FLOAT" 1.1 root 2731: "fneg %0,%1" 2732: [(set_attr "type" "fp")]) 2733: 2734: (define_insn "abssf2" 2735: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2736: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2737: "TARGET_HARD_FLOAT" 1.1 root 2738: "fabs %0,%1" 2739: [(set_attr "type" "fp")]) 2740: 2741: (define_insn "" 2742: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2743: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 root 2744: "TARGET_HARD_FLOAT" 1.1 root 2745: "fnabs %0,%1" 2746: [(set_attr "type" "fp")]) 2747: 1.1.1.2 root 2748: (define_expand "addsf3" 2749: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2750: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2751: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 root 2752: "TARGET_HARD_FLOAT" 1.1.1.2 root 2753: "") 2754: 2755: (define_insn "" 2756: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2757: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2758: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2759: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2760: "fadds %0,%1,%2" 2761: [(set_attr "type" "fp")]) 2762: 2763: (define_insn "" 1.1 root 2764: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2765: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2766: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2767: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2768: "{fa|fadd} %0,%1,%2" 2769: [(set_attr "type" "fp")]) 2770: 2771: (define_expand "subsf3" 2772: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2773: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2774: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 root 2775: "TARGET_HARD_FLOAT" 1.1.1.2 root 2776: "") 2777: 2778: (define_insn "" 2779: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2780: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2781: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2782: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2783: "fsubs %0,%1,%2" 1.1 root 2784: [(set_attr "type" "fp")]) 2785: 1.1.1.2 root 2786: (define_insn "" 1.1 root 2787: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2788: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2789: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2790: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2791: "{fs|fsub} %0,%1,%2" 2792: [(set_attr "type" "fp")]) 2793: 2794: (define_expand "mulsf3" 2795: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2796: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 2797: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 root 2798: "TARGET_HARD_FLOAT" 1.1.1.2 root 2799: "") 2800: 2801: (define_insn "" 2802: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2803: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2804: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2805: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2806: "fmuls %0,%1,%2" 1.1 root 2807: [(set_attr "type" "fp")]) 2808: 1.1.1.2 root 2809: (define_insn "" 1.1 root 2810: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2811: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2812: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2813: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2814: "{fm|fmul} %0,%1,%2" 1.1 root 2815: [(set_attr "type" "fp")]) 2816: 1.1.1.2 root 2817: (define_expand "divsf3" 2818: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2819: (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 2820: (match_operand:SF 2 "gpc_reg_operand" "")))] 1.1.1.4 root 2821: "TARGET_HARD_FLOAT" 1.1.1.2 root 2822: "") 2823: 2824: (define_insn "" 1.1 root 2825: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2826: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2827: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2828: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2829: "fdivs %0,%1,%2" 2830: [(set_attr "type" "sdiv")]) 2831: 2832: (define_insn "" 2833: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2834: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 2835: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 2836: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2837: "{fd|fdiv} %0,%1,%2" 2838: [(set_attr "type" "sdiv")]) 2839: 2840: (define_insn "" 2841: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2842: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2843: (match_operand:SF 2 "gpc_reg_operand" "f")) 2844: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 2845: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2846: "fmadds %0,%1,%2,%3" 1.1 root 2847: [(set_attr "type" "fp")]) 2848: 2849: (define_insn "" 2850: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2851: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2852: (match_operand:SF 2 "gpc_reg_operand" "f")) 2853: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 2854: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2855: "{fma|fmadd} %0,%1,%2,%3" 1.1 root 2856: [(set_attr "type" "fp")]) 2857: 2858: (define_insn "" 2859: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2860: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2861: (match_operand:SF 2 "gpc_reg_operand" "f")) 2862: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 2863: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2864: "fmsubs %0,%1,%2,%3" 2865: [(set_attr "type" "fp")]) 2866: 2867: (define_insn "" 2868: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2869: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2870: (match_operand:SF 2 "gpc_reg_operand" "f")) 2871: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 2872: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2873: "{fms|fmsub} %0,%1,%2,%3" 1.1 root 2874: [(set_attr "type" "fp")]) 2875: 2876: (define_insn "" 2877: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2878: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2879: (match_operand:SF 2 "gpc_reg_operand" "f")) 2880: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 2881: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2882: "fnmadds %0,%1,%2,%3" 2883: [(set_attr "type" "fp")]) 2884: 2885: (define_insn "" 2886: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2887: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2888: (match_operand:SF 2 "gpc_reg_operand" "f")) 2889: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 2890: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2891: "{fnma|fnmadd} %0,%1,%2,%3" 1.1 root 2892: [(set_attr "type" "fp")]) 2893: 2894: (define_insn "" 2895: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2896: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2897: (match_operand:SF 2 "gpc_reg_operand" "f")) 2898: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 2899: "TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2900: "fnmsubs %0,%1,%2,%3" 2901: [(set_attr "type" "fp")]) 2902: 2903: (define_insn "" 2904: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2905: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 2906: (match_operand:SF 2 "gpc_reg_operand" "f")) 2907: (match_operand:SF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 2908: "! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1.1.2 root 2909: "{fnms|fnmsub} %0,%1,%2,%3" 1.1 root 2910: [(set_attr "type" "fp")]) 2911: 1.1.1.2 root 2912: (define_expand "sqrtsf2" 2913: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2914: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.4 root 2915: "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 1.1.1.2 root 2916: "") 2917: 2918: (define_insn "" 2919: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2920: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2921: "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" 1.1.1.2 root 2922: "fsqrts %0,%1" 2923: [(set_attr "type" "ssqrt")]) 2924: 2925: (define_insn "" 2926: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2927: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 2928: "TARGET_POWER2 && TARGET_HARD_FLOAT" 1.1.1.2 root 2929: "fsqrt %0,%1" 2930: [(set_attr "type" "dsqrt")]) 2931: 1.1.1.4 root 2932: ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 2933: ;; fsel instruction and some auxiliary computations. Then we just have a 2934: ;; single DEFINE_INSN for fsel and the define_splits to make them if made by 1.1.1.3 root 2935: ;; combine. 2936: (define_expand "maxsf3" 2937: [(set (match_dup 3) 2938: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 2939: (match_operand:SF 2 "gpc_reg_operand" ""))) 2940: (set (match_operand:SF 0 "gpc_reg_operand" "") 2941: (if_then_else:SF (ge (match_dup 3) 2942: (const_int 0)) 2943: (match_dup 1) 2944: (match_dup 2)))] 1.1.1.4 root 2945: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2946: " 2947: { operands[3] = gen_reg_rtx (SFmode); }") 2948: 2949: (define_split 2950: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2951: (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") 2952: (match_operand:SF 2 "gpc_reg_operand" ""))) 2953: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] 1.1.1.4 root 2954: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2955: [(set (match_dup 3) 2956: (minus:SF (match_dup 1) (match_dup 2))) 1.1.1.4 root 2957: (set (match_dup 0) 1.1.1.3 root 2958: (if_then_else:SF (ge (match_dup 3) 2959: (const_int 0)) 2960: (match_dup 1) 2961: (match_dup 2)))] 2962: "") 2963: 2964: (define_expand "minsf3" 2965: [(set (match_dup 3) 2966: (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") 2967: (match_operand:SF 1 "gpc_reg_operand" ""))) 2968: (set (match_operand:SF 0 "gpc_reg_operand" "") 2969: (if_then_else:SF (ge (match_dup 3) 2970: (const_int 0)) 2971: (match_dup 1) 2972: (match_dup 2)))] 1.1.1.4 root 2973: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2974: " 2975: { operands[3] = gen_reg_rtx (SFmode); }") 2976: 2977: (define_split 2978: [(set (match_operand:SF 0 "gpc_reg_operand" "") 2979: (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") 2980: (match_operand:SF 2 "gpc_reg_operand" ""))) 2981: (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] 1.1.1.4 root 2982: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 2983: [(set (match_dup 3) 2984: (minus:SF (match_dup 2) (match_dup 1))) 1.1.1.4 root 2985: (set (match_dup 0) 1.1.1.3 root 2986: (if_then_else:SF (ge (match_dup 3) 2987: (const_int 0)) 2988: (match_dup 1) 2989: (match_dup 2)))] 2990: "") 2991: 1.1.1.4 root 2992: (define_expand "movsfcc" 2993: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 2994: (if_then_else:SF (match_operand 1 "comparison_operator" "") 2995: (match_operand:SF 2 "gpc_reg_operand" "f") 2996: (match_operand:SF 3 "gpc_reg_operand" "f")))] 2997: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 2998: " 2999: { 3000: rtx temp, op0, op1; 3001: enum rtx_code code = GET_CODE (operands[1]); 3002: if (! rs6000_compare_fp_p) 3003: FAIL; 3004: switch (code) 3005: { 3006: case GE: case EQ: case NE: 3007: op0 = rs6000_compare_op0; 3008: op1 = rs6000_compare_op1; 3009: break; 3010: case GT: 3011: op0 = rs6000_compare_op1; 3012: op1 = rs6000_compare_op0; 3013: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; 3014: break; 3015: case LE: 3016: op0 = rs6000_compare_op1; 3017: op1 = rs6000_compare_op0; 3018: break; 3019: case LT: 3020: op0 = rs6000_compare_op0; 3021: op1 = rs6000_compare_op1; 3022: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; 3023: break; 3024: default: 3025: FAIL; 3026: } 3027: if (GET_MODE (rs6000_compare_op0) == DFmode) 3028: { 3029: temp = gen_reg_rtx (DFmode); 3030: emit_insn (gen_subdf3 (temp, op0, op1)); 3031: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); 3032: if (code == EQ) 3033: { 3034: emit_insn (gen_negdf2 (temp, temp)); 3035: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); 3036: } 3037: if (code == NE) 3038: { 3039: emit_insn (gen_negdf2 (temp, temp)); 3040: emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); 3041: } 3042: } 3043: else 3044: { 3045: temp = gen_reg_rtx (SFmode); 3046: emit_insn (gen_subsf3 (temp, op0, op1)); 3047: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); 3048: if (code == EQ) 3049: { 3050: emit_insn (gen_negsf2 (temp, temp)); 3051: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); 3052: } 3053: if (code == NE) 3054: { 3055: emit_insn (gen_negsf2 (temp, temp)); 3056: emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); 3057: } 3058: } 3059: DONE; 3060: }") 3061: 3062: (define_insn "fselsfsf4" 1.1.1.3 root 3063: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 3064: (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 3065: (const_int 0)) 3066: (match_operand:SF 2 "gpc_reg_operand" "f") 3067: (match_operand:SF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 3068: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 3069: "fsel %0,%1,%2,%3" 3070: [(set_attr "type" "fp")]) 3071: 3072: (define_insn "fseldfsf4" 3073: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 3074: (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 3075: (const_int 0)) 3076: (match_operand:SF 2 "gpc_reg_operand" "f") 3077: (match_operand:SF 3 "gpc_reg_operand" "f")))] 3078: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3079: "fsel %0,%1,%2,%3" 3080: [(set_attr "type" "fp")]) 3081: 1.1 root 3082: (define_insn "negdf2" 3083: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3084: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 3085: "TARGET_HARD_FLOAT" 1.1 root 3086: "fneg %0,%1" 3087: [(set_attr "type" "fp")]) 3088: 3089: (define_insn "absdf2" 3090: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3091: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 3092: "TARGET_HARD_FLOAT" 1.1 root 3093: "fabs %0,%1" 3094: [(set_attr "type" "fp")]) 3095: 3096: (define_insn "" 3097: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3098: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 root 3099: "TARGET_HARD_FLOAT" 1.1 root 3100: "fnabs %0,%1" 3101: [(set_attr "type" "fp")]) 3102: 3103: (define_insn "adddf3" 3104: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3105: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3106: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 3107: "TARGET_HARD_FLOAT" 1.1.1.2 root 3108: "{fa|fadd} %0,%1,%2" 1.1 root 3109: [(set_attr "type" "fp")]) 3110: 3111: (define_insn "subdf3" 3112: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3113: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 3114: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 3115: "TARGET_HARD_FLOAT" 1.1.1.2 root 3116: "{fs|fsub} %0,%1,%2" 1.1 root 3117: [(set_attr "type" "fp")]) 3118: 3119: (define_insn "muldf3" 3120: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3121: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3122: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 3123: "TARGET_HARD_FLOAT" 1.1.1.2 root 3124: "{fm|fmul} %0,%1,%2" 3125: [(set_attr "type" "dmul")]) 1.1 root 3126: 3127: (define_insn "divdf3" 3128: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3129: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 3130: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 3131: "TARGET_HARD_FLOAT" 1.1.1.2 root 3132: "{fd|fdiv} %0,%1,%2" 3133: [(set_attr "type" "ddiv")]) 1.1 root 3134: 3135: (define_insn "" 3136: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3137: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3138: (match_operand:DF 2 "gpc_reg_operand" "f")) 3139: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 3140: "TARGET_HARD_FLOAT" 1.1.1.2 root 3141: "{fma|fmadd} %0,%1,%2,%3" 3142: [(set_attr "type" "dmul")]) 1.1 root 3143: 3144: (define_insn "" 3145: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3146: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3147: (match_operand:DF 2 "gpc_reg_operand" "f")) 3148: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 3149: "TARGET_HARD_FLOAT" 1.1.1.2 root 3150: "{fms|fmsub} %0,%1,%2,%3" 3151: [(set_attr "type" "dmul")]) 1.1 root 3152: 3153: (define_insn "" 3154: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3155: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3156: (match_operand:DF 2 "gpc_reg_operand" "f")) 3157: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 3158: "TARGET_HARD_FLOAT" 1.1.1.2 root 3159: "{fnma|fnmadd} %0,%1,%2,%3" 3160: [(set_attr "type" "dmul")]) 1.1 root 3161: 3162: (define_insn "" 3163: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3164: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 3165: (match_operand:DF 2 "gpc_reg_operand" "f")) 3166: (match_operand:DF 3 "gpc_reg_operand" "f"))))] 1.1.1.4 root 3167: "TARGET_HARD_FLOAT" 1.1.1.2 root 3168: "{fnms|fnmsub} %0,%1,%2,%3" 3169: [(set_attr "type" "dmul")]) 3170: 3171: (define_insn "sqrtdf2" 3172: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3173: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 3174: "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 1.1.1.2 root 3175: "fsqrt %0,%1" 3176: [(set_attr "type" "dsqrt")]) 1.1.1.3 root 3177: 1.1.1.4 root 3178: ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 3179: ;; fsel instruction and some auxiliary computations. Then we just have a 3180: ;; single DEFINE_INSN for fsel and the define_splits to make them if made by 1.1.1.3 root 3181: ;; combine. 3182: 3183: (define_expand "maxdf3" 3184: [(set (match_dup 3) 3185: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") 3186: (match_operand:DF 2 "gpc_reg_operand" ""))) 3187: (set (match_operand:DF 0 "gpc_reg_operand" "") 3188: (if_then_else:DF (ge (match_dup 3) 3189: (const_int 0)) 3190: (match_dup 1) 3191: (match_dup 2)))] 1.1.1.4 root 3192: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3193: " 3194: { operands[3] = gen_reg_rtx (DFmode); }") 3195: 3196: (define_split 3197: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3198: (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") 3199: (match_operand:DF 2 "gpc_reg_operand" ""))) 3200: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] 1.1.1.4 root 3201: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3202: [(set (match_dup 3) 3203: (minus:DF (match_dup 1) (match_dup 2))) 1.1.1.4 root 3204: (set (match_dup 0) 1.1.1.3 root 3205: (if_then_else:DF (ge (match_dup 3) 3206: (const_int 0)) 3207: (match_dup 1) 3208: (match_dup 2)))] 3209: "") 3210: 3211: (define_expand "mindf3" 3212: [(set (match_dup 3) 3213: (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") 3214: (match_operand:DF 1 "gpc_reg_operand" ""))) 3215: (set (match_operand:DF 0 "gpc_reg_operand" "") 3216: (if_then_else:DF (ge (match_dup 3) 3217: (const_int 0)) 3218: (match_dup 1) 3219: (match_dup 2)))] 1.1.1.4 root 3220: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3221: " 3222: { operands[3] = gen_reg_rtx (DFmode); }") 3223: 3224: (define_split 3225: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3226: (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") 3227: (match_operand:DF 2 "gpc_reg_operand" ""))) 3228: (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] 1.1.1.4 root 3229: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 1.1.1.3 root 3230: [(set (match_dup 3) 3231: (minus:DF (match_dup 2) (match_dup 1))) 1.1.1.4 root 3232: (set (match_dup 0) 1.1.1.3 root 3233: (if_then_else:DF (ge (match_dup 3) 3234: (const_int 0)) 3235: (match_dup 1) 3236: (match_dup 2)))] 3237: "") 3238: 1.1.1.4 root 3239: (define_expand "movdfcc" 3240: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3241: (if_then_else:DF (match_operand 1 "comparison_operator" "") 3242: (match_operand:DF 2 "gpc_reg_operand" "f") 3243: (match_operand:DF 3 "gpc_reg_operand" "f")))] 3244: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 3245: " 3246: { 3247: rtx temp, op0, op1; 3248: enum rtx_code code = GET_CODE (operands[1]); 3249: if (! rs6000_compare_fp_p) 3250: FAIL; 3251: switch (code) 3252: { 3253: case GE: case EQ: case NE: 3254: op0 = rs6000_compare_op0; 3255: op1 = rs6000_compare_op1; 3256: break; 3257: case GT: 3258: op0 = rs6000_compare_op1; 3259: op1 = rs6000_compare_op0; 3260: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; 3261: break; 3262: case LE: 3263: op0 = rs6000_compare_op1; 3264: op1 = rs6000_compare_op0; 3265: break; 3266: case LT: 3267: op0 = rs6000_compare_op0; 3268: op1 = rs6000_compare_op1; 3269: temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; 3270: break; 3271: default: 3272: FAIL; 3273: } 3274: if (GET_MODE (rs6000_compare_op0) == DFmode) 3275: { 3276: temp = gen_reg_rtx (DFmode); 3277: emit_insn (gen_subdf3 (temp, op0, op1)); 3278: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); 3279: if (code == EQ) 3280: { 3281: emit_insn (gen_negdf2 (temp, temp)); 3282: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); 3283: } 3284: if (code == NE) 3285: { 3286: emit_insn (gen_negdf2 (temp, temp)); 3287: emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); 3288: } 3289: } 3290: else 3291: { 3292: temp = gen_reg_rtx (SFmode); 3293: emit_insn (gen_subsf3 (temp, op0, op1)); 3294: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); 3295: if (code == EQ) 3296: { 3297: emit_insn (gen_negsf2 (temp, temp)); 3298: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); 3299: } 3300: if (code == NE) 3301: { 3302: emit_insn (gen_negsf2 (temp, temp)); 3303: emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); 3304: } 3305: } 3306: DONE; 3307: }") 3308: 3309: (define_insn "fseldfdf4" 1.1.1.3 root 3310: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3311: (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 3312: (const_int 0)) 3313: (match_operand:DF 2 "gpc_reg_operand" "f") 3314: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.4 root 3315: "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 3316: "fsel %0,%1,%2,%3" 3317: [(set_attr "type" "fp")]) 3318: 3319: (define_insn "fselsfdf4" 3320: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3321: (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 3322: (const_int 0)) 3323: (match_operand:DF 2 "gpc_reg_operand" "f") 3324: (match_operand:DF 3 "gpc_reg_operand" "f")))] 1.1.1.3 root 3325: "TARGET_PPC_GFXOPT" 3326: "fsel %0,%1,%2,%3" 3327: [(set_attr "type" "fp")]) 1.1 root 3328: 3329: ;; Conversions to and from floating-point. 3330: (define_expand "floatsidf2" 1.1.1.4 root 3331: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3332: (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))] 3333: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3334: " 3335: { 1.1.1.4 root 3336: if (operands[0]) 3337: { /* prevent unused warning messages */ 3338: rtx high = force_reg (SImode, GEN_INT (0x43300000)); 3339: rtx low = gen_reg_rtx (SImode); 3340: rtx df = gen_reg_rtx (DFmode); 3341: rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); 3342: 3343: emit_insn (gen_xorsi3 (low, operands[1], GEN_INT (0x80000000))); 3344: emit_insn (gen_move_to_float (df, low, high)); 3345: emit_insn (gen_subdf3 (operands[0], df, adjust)); 3346: DONE; 3347: } 1.1 root 3348: }") 3349: 3350: (define_expand "floatunssidf2" 1.1.1.4 root 3351: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3352: (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))] 3353: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3354: " 3355: { 1.1.1.4 root 3356: if (operands[0]) 3357: { /* prevent unused warning messages */ 3358: rtx high = force_reg (SImode, GEN_INT (0x43300000)); 3359: rtx df = gen_reg_rtx (DFmode); 3360: rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); 1.1 root 3361: 1.1.1.4 root 3362: emit_insn (gen_move_to_float (df, operands[1], high)); 3363: emit_insn (gen_subdf3 (operands[0], df, adjust)); 3364: DONE; 3365: } 1.1 root 3366: }") 3367: 1.1.1.4 root 3368: (define_expand "move_to_float" 3369: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3370: (unspec [(match_operand:SI 1 "gpc_reg_operand" "") 3371: (match_operand:SI 2 "gpc_reg_operand" "") 3372: (match_dup 3)] 2))] 3373: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1 root 3374: " 1.1.1.4 root 3375: { 3376: operands[3] = XEXP (rs6000_stack_temp (DFmode, 8, 1), 0); 1.1 root 3377: }") 3378: 3379: (define_split 1.1.1.4 root 3380: [(set (match_operand:DF 0 "gpc_reg_operand" "") 3381: (unspec [(match_operand:SI 1 "gpc_reg_operand" "") 3382: (match_operand:SI 2 "gpc_reg_operand" "") 3383: (match_operand:SI 3 "offsettable_addr_operand" "")] 2))] 3384: "reload_completed" 3385: [(set (match_dup 4) (match_dup 1)) 3386: (set (match_dup 5) (match_dup 2)) 3387: (set (match_dup 0) (mem:DF (match_dup 3)))] 3388: " 3389: { 3390: rtx word1 = gen_rtx (MEM, SImode, operands[3]); 3391: rtx word2 = gen_rtx (MEM, SImode, plus_constant (operands[3], 4)); 3392: 3393: MEM_IN_STRUCT_P (word1) = 1; 3394: MEM_IN_STRUCT_P (word2) = 1; 1.1 root 3395: 1.1.1.4 root 3396: if (WORDS_BIG_ENDIAN) 1.1 root 3397: { 1.1.1.4 root 3398: operands[4] = word2; 3399: operands[5] = word1; 1.1 root 3400: } 1.1.1.4 root 3401: else 1.1 root 3402: { 1.1.1.4 root 3403: operands[4] = word1; 3404: operands[5] = word2; 1.1 root 3405: } 3406: }") 3407: 3408: (define_insn "" 1.1.1.4 root 3409: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3410: (unspec [(match_operand:SI 1 "gpc_reg_operand" "r") 3411: (match_operand:SI 2 "gpc_reg_operand" "r") 3412: (match_operand:SI 3 "offsettable_addr_operand" "p")] 2))] 3413: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.2 root 3414: "#" 1.1.1.4 root 3415: [(set_attr "length" "12")]) 1.1 root 3416: 3417: (define_expand "fix_truncdfsi2" 3418: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3419: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 root 3420: "TARGET_HARD_FLOAT" 1.1 root 3421: " 3422: { 1.1.1.3 root 3423: if (TARGET_POWER2 || TARGET_POWERPC) 3424: { 1.1.1.4 root 3425: int endian = (WORDS_BIG_ENDIAN == 0); 3426: rtx stack_slot = rs6000_stack_temp (DImode, 8, 1); 3427: rtx temp = gen_reg_rtx (DImode); 1.1.1.3 root 3428: 3429: emit_insn (gen_fpcvtsi (temp, operands[1])); 3430: emit_move_insn (stack_slot, temp); 3431: emit_move_insn (operands[0], 1.1.1.4 root 3432: operand_subword (stack_slot, 1 - endian, 0, DImode)); 1.1.1.3 root 3433: DONE; 3434: } 3435: else 3436: { 3437: emit_insn (gen_trunc_call (operands[0], operands[1], 3438: gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC))); 3439: DONE; 3440: } 1.1 root 3441: }") 3442: 1.1.1.3 root 3443: (define_insn "fpcvtsi" 3444: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 3445: (sign_extend:DI 3446: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] 1.1.1.4 root 3447: "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 1.1.1.3 root 3448: "{fcirz|fctiwz} %0,%1" 3449: [(set_attr "type" "fp")]) 3450: 1.1 root 3451: (define_expand "fixuns_truncdfsi2" 3452: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3453: (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 root 3454: "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" 1.1 root 3455: " 3456: { 3457: emit_insn (gen_trunc_call (operands[0], operands[1], 1.1.1.3 root 3458: gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC))); 1.1 root 3459: DONE; 3460: }") 3461: 3462: (define_expand "trunc_call" 3463: [(parallel [(set (match_operand:SI 0 "" "") 3464: (fix:SI (match_operand:DF 1 "" ""))) 3465: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 root 3466: "TARGET_HARD_FLOAT" 1.1 root 3467: " 3468: { 3469: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); 3470: rtx first = XVECEXP (insns, 0, 0); 3471: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); 3472: 3473: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, 3474: REG_NOTES (first)); 3475: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); 3476: 3477: emit_insn (insns); 3478: DONE; 3479: }") 3480: 3481: (define_expand "trunc_call_rtl" 3482: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) 3483: (use (reg:DF 33)) 3484: (parallel [(set (reg:SI 3) 3485: (call (mem:SI (match_operand 2 "" "")) (const_int 0))) 1.1.1.4 root 3486: (use (const_int 0)) 1.1 root 3487: (clobber (scratch:SI))]) 3488: (set (match_operand:SI 0 "gpc_reg_operand" "") 3489: (reg:SI 3))] 1.1.1.4 root 3490: "TARGET_HARD_FLOAT" 1.1 root 3491: " 1.1.1.4 root 3492: { 1.1 root 3493: rs6000_trunc_used = 1; 3494: }") 1.1.1.3 root 3495: 3496: (define_insn "floatdidf2" 3497: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 3498: (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 3499: "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.3 root 3500: "fcfid %0,%1" 3501: [(set_attr "type" "fp")]) 3502: 3503: (define_insn "fix_truncdfdi2" 3504: [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 3505: (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 1.1.1.4 root 3506: "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 1.1.1.3 root 3507: "fctidz %0,%1" 3508: [(set_attr "type" "fp")]) 1.1 root 3509: 3510: ;; Define the DImode operations that can be done in a small number 1.1.1.4 root 3511: ;; of instructions. The & constraints are to prevent the register 3512: ;; allocator from allocating registers that overlap with the inputs 3513: ;; (for example, having an input in 7,8 and an output in 6,7). We 3514: ;; also allow for the the output being the same as one of the inputs. 3515: 1.1.1.2 root 3516: (define_expand "adddi3" 3517: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3518: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 3519: (match_operand:DI 2 "reg_or_short_operand" "")))] 3520: "" 3521: " 3522: { 1.1.1.3 root 3523: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3524: && short_cint_operand (operands[2], DImode)) 3525: FAIL; 3526: }") 3527: 3528: (define_insn "" 1.1.1.4 root 3529: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") 3530: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") 3531: (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 1.1.1.3 root 3532: "TARGET_POWER && ! TARGET_POWERPC64" 1.1 root 3533: "@ 1.1.1.2 root 3534: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 1.1.1.4 root 3535: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1 3536: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 1.1.1.2 root 3537: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" 3538: [(set_attr "length" "8")]) 1.1 root 3539: 1.1.1.2 root 3540: (define_insn "" 1.1.1.4 root 3541: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 3542: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,0") 3543: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 1.1.1.3 root 3544: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.4 root 3545: "* 3546: { 3547: return (WORDS_BIG_ENDIAN) 3548: ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" 3549: : \"addc %0,%1,%2\;adde %L0,%L1,%L2\"; 3550: }" 1.1.1.2 root 3551: [(set_attr "length" "8")]) 3552: 3553: (define_expand "subdi3" 1.1.1.4 root 3554: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3555: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") 3556: (match_operand:DI 2 "gpc_reg_operand" "")))] 1.1 root 3557: "" 1.1.1.2 root 3558: " 3559: { 1.1.1.3 root 3560: if (! TARGET_POWER && ! TARGET_POWERPC64 1.1.1.2 root 3561: && short_cint_operand (operands[1], DImode)) 3562: FAIL; 3563: }") 3564: 3565: (define_insn "" 1.1.1.4 root 3566: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 3567: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") 3568: (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 1.1.1.3 root 3569: "TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.2 root 3570: "@ 3571: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 1.1.1.4 root 3572: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2 3573: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 3574: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 1.1.1.2 root 3575: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" 3576: [(set_attr "length" "8")]) 3577: 3578: (define_insn "" 1.1.1.4 root 3579: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r") 3580: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,0,r") 3581: (match_operand:DI 2 "gpc_reg_operand" "r,r,0")))] 1.1.1.3 root 3582: "! TARGET_POWER && ! TARGET_POWERPC64" 1.1.1.4 root 3583: "* 3584: { 3585: return (WORDS_BIG_ENDIAN) 3586: ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" 3587: : \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"; 3588: }" 1.1.1.2 root 3589: [(set_attr "length" "8")]) 3590: 3591: (define_expand "negdi2" 3592: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3593: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 3594: "" 3595: "") 1.1 root 3596: 1.1.1.2 root 3597: (define_insn "" 1.1.1.4 root 3598: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 3599: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 1.1.1.3 root 3600: "! TARGET_POWERPC64" 1.1.1.4 root 3601: "* 3602: { 3603: return (WORDS_BIG_ENDIAN) 3604: ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" 3605: : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; 3606: }" 1.1.1.2 root 3607: [(set_attr "length" "8")]) 1.1 root 3608: 1.1.1.3 root 3609: (define_expand "mulsidi3" 3610: [(set (match_operand:DI 0 "gpc_reg_operand" "") 3611: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 3612: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 3613: "" 3614: " 3615: { 3616: if (! TARGET_POWER && ! TARGET_POWERPC) 3617: { 1.1.1.4 root 3618: int endian = (WORDS_BIG_ENDIAN == 0); 1.1.1.3 root 3619: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 3620: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 3621: emit_insn (gen_mull_call ()); 1.1.1.4 root 3622: emit_move_insn (operand_subword (operands[0], endian, 0, DImode), 1.1.1.3 root 3623: gen_rtx (REG, SImode, 3)); 1.1.1.4 root 3624: emit_move_insn (operand_subword (operands[0], 1 - endian, 0, DImode), 1.1.1.3 root 3625: gen_rtx (REG, SImode, 4)); 3626: DONE; 3627: } 3628: else if (TARGET_POWER) 3629: { 3630: emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); 3631: DONE; 3632: } 3633: }") 3634: 3635: (define_insn "mulsidi3_mq" 1.1 root 3636: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1.1.1.3 root 3637: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 3638: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 3639: (clobber (match_scratch:SI 3 "=q"))] 1.1.1.2 root 3640: "TARGET_POWER" 3641: "mul %0,%1,%2\;mfmq %L0" 1.1.1.3 root 3642: [(set_attr "type" "imul") 3643: (set_attr "length" "8")]) 3644: 3645: (define_insn "" 3646: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 3647: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 3648: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 3649: "TARGET_POWERPC && ! TARGET_POWERPC64" 1.1.1.4 root 3650: "* 3651: { 3652: return (WORDS_BIG_ENDIAN) 3653: ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" 3654: : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; 3655: }" 1.1.1.3 root 3656: [(set_attr "type" "imul") 3657: (set_attr "length" "8")]) 3658: 3659: (define_expand "smulsi3_highpart" 3660: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3661: (truncate:SI 3662: (lshiftrt:DI (mult:DI (sign_extend:DI 3663: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3664: (sign_extend:DI 3665: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3666: (const_int 32))))] 3667: "" 3668: " 3669: { 3670: if (! TARGET_POWER && ! TARGET_POWERPC) 3671: { 3672: emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); 3673: emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); 3674: emit_insn (gen_mulh_call ()); 3675: emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); 3676: DONE; 3677: } 3678: else if (TARGET_POWER) 3679: { 3680: emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); 3681: DONE; 3682: } 3683: }") 3684: 3685: (define_insn "smulsi3_highpart_mq" 3686: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3687: (truncate:SI 3688: (lshiftrt:DI (mult:DI (sign_extend:DI 3689: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3690: (sign_extend:DI 3691: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3692: (const_int 32)))) 3693: (clobber (match_scratch:SI 3 "=q"))] 3694: "TARGET_POWER" 3695: "mul %0,%1,%2" 3696: [(set_attr "type" "imul")]) 3697: 3698: (define_insn "" 3699: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3700: (truncate:SI 3701: (lshiftrt:DI (mult:DI (sign_extend:DI 3702: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3703: (sign_extend:DI 3704: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3705: (const_int 32))))] 3706: "TARGET_POWERPC" 3707: "mulhw %0,%1,%2" 3708: [(set_attr "type" "imul")]) 3709: 3710: (define_insn "umulsi3_highpart" 3711: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3712: (truncate:SI 3713: (lshiftrt:DI (mult:DI (zero_extend:DI 3714: (match_operand:SI 1 "gpc_reg_operand" "%r")) 3715: (zero_extend:DI 3716: (match_operand:SI 2 "gpc_reg_operand" "r"))) 3717: (const_int 32))))] 3718: "TARGET_POWERPC" 3719: "mulhwu %0,%1,%2" 3720: [(set_attr "type" "imul")]) 1.1 root 3721: 3722: ;; If operands 0 and 2 are in the same register, we have a problem. But 3723: ;; operands 0 and 1 (the usual case) can be in the same register. That's 3724: ;; why we have the strange constraints below. 3725: (define_insn "ashldi3" 3726: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 3727: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3728: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3729: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3730: "TARGET_POWER" 1.1 root 3731: "@ 1.1.1.2 root 3732: {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 1.1 root 3733: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 3734: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 1.1.1.2 root 3735: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 3736: [(set_attr "length" "8")]) 1.1 root 3737: 3738: (define_insn "lshrdi3" 3739: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") 3740: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 3741: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 3742: (clobber (match_scratch:SI 3 "=X,q,q,q"))] 1.1.1.2 root 3743: "TARGET_POWER" 1.1 root 3744: "@ 1.1.1.2 root 3745: {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2 1.1 root 3746: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 3747: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 1.1.1.2 root 3748: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 3749: [(set_attr "length" "8")]) 1.1 root 3750: 3751: ;; Shift by a variable amount is too complex to be worth open-coding. We 3752: ;; just handle shifts by constants. 3753: 3754: (define_expand "ashrdi3" 1.1.1.3 root 3755: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") 1.1 root 3756: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 3757: (match_operand:SI 2 "general_operand" ""))) 3758: (clobber (match_scratch:SI 3 ""))])] 1.1.1.2 root 3759: "TARGET_POWER" 1.1 root 3760: " 3761: { if (GET_CODE (operands[2]) != CONST_INT) 3762: FAIL; 3763: }") 3764: 3765: (define_insn "" 3766: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3767: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 3768: (match_operand:SI 2 "const_int_operand" "M,i"))) 3769: (clobber (match_scratch:SI 3 "=X,q"))] 1.1.1.2 root 3770: "TARGET_POWER" 1.1 root 3771: "@ 1.1.1.2 root 3772: {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 3773: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 3774: [(set_attr "length" "8")]) 1.1 root 3775: 1.1.1.3 root 3776: ;; PowerPC64 DImode operations. 3777: 3778: (define_insn "ffsdi2" 1.1.1.4 root 3779: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 3780: (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 1.1.1.3 root 3781: "TARGET_POWERPC64" 3782: "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" 3783: [(set_attr "length" "16")]) 3784: 3785: (define_insn "muldi3" 3786: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3787: (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 3788: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3789: "TARGET_POWERPC64" 3790: "mulld %0,%1,%2" 3791: [(set_attr "type" "imul")]) 3792: 3793: (define_insn "smuldi3_highpart" 3794: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3795: (truncate:DI 3796: (lshiftrt:TI (mult:TI (sign_extend:TI 3797: (match_operand:DI 1 "gpc_reg_operand" "%r")) 3798: (sign_extend:TI 3799: (match_operand:DI 2 "gpc_reg_operand" "r"))) 3800: (const_int 64))))] 3801: "TARGET_POWERPC64" 3802: "mulhd %0,%1,%2" 3803: [(set_attr "type" "imul")]) 3804: 3805: (define_insn "umuldi3_highpart" 3806: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3807: (truncate:DI 3808: (lshiftrt:TI (mult:TI (zero_extend:TI 3809: (match_operand:DI 1 "gpc_reg_operand" "%r")) 3810: (zero_extend:TI 3811: (match_operand:DI 2 "gpc_reg_operand" "r"))) 3812: (const_int 64))))] 3813: "TARGET_POWERPC64" 3814: "mulhdu %0,%1,%2" 3815: [(set_attr "type" "imul")]) 3816: 3817: (define_insn "divdi3" 3818: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3819: (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3820: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3821: "TARGET_POWERPC64" 3822: "divd %0,%1,%2" 3823: [(set_attr "type" "idiv")]) 3824: 3825: (define_insn "udivdi3" 3826: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3827: (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3828: (match_operand:DI 2 "gpc_reg_operand" "r")))] 3829: "TARGET_POWERPC64" 3830: "divdu %0,%1,%2" 3831: [(set_attr "type" "idiv")]) 3832: 3833: (define_insn "rotldi3" 3834: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3835: (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3836: (match_operand:DI 2 "reg_or_cint_operand" "ri")))] 3837: "TARGET_POWERPC64" 3838: "rld%I2cl %0,%1,%h2,0") 3839: 3840: (define_insn "" 3841: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 3842: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3843: (match_operand:DI 2 "reg_or_cint_operand" "ri")) 3844: (const_int 0))) 3845: (clobber (match_scratch:DI 3 "=r"))] 3846: "TARGET_POWERPC64" 3847: "rld%I2cl. %3,%1,%h2,0" 3848: [(set_attr "type" "delayed_compare")]) 3849: 3850: (define_insn "" 3851: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 3852: (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3853: (match_operand:DI 2 "reg_or_cint_operand" "ri")) 3854: (const_int 0))) 3855: (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3856: (rotate:DI (match_dup 1) (match_dup 2)))] 3857: "TARGET_POWERPC64" 3858: "rld%I2cl. %0,%1,%h2,0" 3859: [(set_attr "type" "delayed_compare")]) 3860: 1.1 root 3861: ;; Now define ways of moving data around. 1.1.1.4 root 3862: 3863: ;; Elf specific ways of loading addresses for non-PIC code. 3864: ;; The output of this could be r0, but we limit it to base 3865: ;; registers, since almost all uses of this will need it 3866: ;; in a base register shortly. 3867: (define_insn "elf_high" 3868: [(set (match_operand:SI 0 "register_operand" "=b") 3869: (high:SI (match_operand 1 "" "")))] 3870: "TARGET_ELF && !TARGET_64BIT" 3871: "{cau|addis} %0,0,%1@ha") 3872: 3873: (define_insn "elf_low" 3874: [(set (match_operand:SI 0 "register_operand" "=r") 3875: (lo_sum:SI (match_operand:SI 1 "register_operand" "b") 3876: (match_operand 2 "" "")))] 3877: "TARGET_ELF && !TARGET_64BIT" 3878: "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}") 3879: 1.1 root 3880: ;; For SI, we special-case integers that can't be loaded in one insn. We 3881: ;; do the load 16-bits at a time. We could do this by loading from memory, 3882: ;; and this is even supposed to be faster, but it is simpler not to get 3883: ;; integers in the TOC. 3884: (define_expand "movsi" 3885: [(set (match_operand:SI 0 "general_operand" "") 3886: (match_operand:SI 1 "any_operand" ""))] 3887: "" 3888: " 3889: { 3890: if (GET_CODE (operands[0]) != REG) 3891: operands[1] = force_reg (SImode, operands[1]); 3892: 1.1.1.4 root 3893: /* Convert a move of a CONST_DOUBLE into a CONST_INT */ 3894: if (GET_CODE (operands[1]) == CONST_DOUBLE) 3895: operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 3896: 3897: if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT 3898: && CONSTANT_P (operands[1]) 3899: && GET_CODE (operands[1]) != HIGH 3900: && GET_CODE (operands[1]) != CONST_INT) 3901: { 3902: rtx target = (reload_completed || reload_in_progress) 3903: ? operands[0] : gen_reg_rtx (SImode); 3904: 3905: emit_insn (gen_elf_high (target, operands[1])); 3906: emit_insn (gen_elf_low (operands[0], target, operands[1])); 3907: DONE; 3908: } 3909: 3910: if (CONSTANT_P (operands[1]) 3911: && GET_CODE (operands[1]) != CONST_INT 3912: && GET_CODE (operands[1]) != HIGH 1.1.1.2 root 3913: && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) 1.1 root 3914: { 1.1.1.3 root 3915: /* If we are to limit the number of things we put in the TOC and 3916: this is a symbol plus a constant we can add in one insn, 1.1.1.4 root 3917: just put the symbol in the TOC and add the constant. Don't do 1.1.1.3 root 3918: this if reload is in progress. */ 3919: if (GET_CODE (operands[1]) == CONST 3920: && TARGET_NO_SUM_IN_TOC && ! reload_in_progress 3921: && GET_CODE (XEXP (operands[1], 0)) == PLUS 3922: && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) 3923: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF 3924: || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) 3925: && ! side_effects_p (operands[0])) 3926: { 3927: rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); 3928: rtx other = XEXP (XEXP (operands[1], 0), 1); 3929: 3930: emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); 3931: DONE; 3932: } 3933: 1.1 root 3934: operands[1] = force_const_mem (SImode, operands[1]); 3935: if (! memory_address_p (SImode, XEXP (operands[1], 0)) 3936: && ! reload_in_progress) 3937: operands[1] = change_address (operands[1], SImode, 3938: XEXP (operands[1], 0)); 3939: } 3940: 3941: if (GET_CODE (operands[1]) == CONST_INT 3942: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3943: && (INTVAL (operands[1]) & 0xffff) != 0) 3944: { 3945: emit_move_insn (operands[0], 3946: gen_rtx (CONST_INT, VOIDmode, 3947: INTVAL (operands[1]) & 0xffff0000)); 3948: emit_insn (gen_iorsi3 (operands[0], operands[0], 3949: gen_rtx (CONST_INT, VOIDmode, 3950: INTVAL (operands[1]) & 0xffff))); 3951: DONE; 3952: } 3953: }") 3954: 3955: (define_insn "" 1.1.1.3 root 3956: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h") 3957: (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))] 3958: "gpc_reg_operand (operands[0], SImode) 3959: || gpc_reg_operand (operands[1], SImode)" 1.1 root 3960: "@ 1.1.1.3 root 3961: mr %0,%1 1.1.1.2 root 3962: {l%U1%X1|lwz%U1%X1} %0,%1 3963: {st%U0%X0|stw%U0%X0} %1,%0 1.1.1.3 root 3964: {lil|li} %0,%1 3965: {liu|lis} %0,%u1 3966: {cal|la} %0,%1(%*) 1.1 root 3967: mf%1 %0 3968: mt%0 %1 3969: mt%0 %1 3970: cror 0,0,0" 1.1.1.3 root 3971: [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 3972: 1.1 root 3973: ;; Split a load of a large constant into the appropriate two-insn 3974: ;; sequence. 3975: 3976: (define_split 3977: [(set (match_operand:SI 0 "gpc_reg_operand" "") 3978: (match_operand:SI 1 "const_int_operand" ""))] 3979: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 3980: && (INTVAL (operands[1]) & 0xffff) != 0" 3981: [(set (match_dup 0) 3982: (match_dup 2)) 3983: (set (match_dup 0) 3984: (ior:SI (match_dup 0) 3985: (match_dup 3)))] 3986: " 3987: { 3988: operands[2] = gen_rtx (CONST_INT, VOIDmode, 3989: INTVAL (operands[1]) & 0xffff0000); 3990: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); 3991: }") 3992: 3993: (define_insn "" 3994: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 3995: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 3996: (const_int 0))) 3997: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 3998: "" 1.1.1.3 root 3999: "mr. %0,%1" 1.1 root 4000: [(set_attr "type" "compare")]) 4001: 4002: (define_expand "movhi" 4003: [(set (match_operand:HI 0 "general_operand" "") 4004: (match_operand:HI 1 "any_operand" ""))] 4005: "" 4006: " 4007: { 4008: if (GET_CODE (operands[0]) != REG) 4009: operands[1] = force_reg (HImode, operands[1]); 4010: 4011: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 4012: { 4013: operands[1] = force_const_mem (HImode, operands[1]); 4014: if (! memory_address_p (HImode, XEXP (operands[1], 0)) 4015: && ! reload_in_progress) 4016: operands[1] = change_address (operands[1], HImode, 4017: XEXP (operands[1], 0)); 4018: } 4019: }") 4020: 4021: (define_insn "" 1.1.1.3 root 4022: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 4023: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 4024: "gpc_reg_operand (operands[0], HImode) 4025: || gpc_reg_operand (operands[1], HImode)" 1.1 root 4026: "@ 1.1.1.3 root 4027: mr %0,%1 1.1 root 4028: lhz%U1%X1 %0,%1 4029: sth%U0%X0 %1,%0 1.1.1.3 root 4030: {lil|li} %0,%w1 1.1 root 4031: mf%1 %0 4032: mt%0 %1 1.1.1.3 root 4033: mt%0 %1 1.1 root 4034: cror 0,0,0" 1.1.1.3 root 4035: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1.1.2 root 4036: 1.1 root 4037: (define_expand "movqi" 4038: [(set (match_operand:QI 0 "general_operand" "") 4039: (match_operand:QI 1 "any_operand" ""))] 4040: "" 4041: " 4042: { 4043: if (GET_CODE (operands[0]) != REG) 4044: operands[1] = force_reg (QImode, operands[1]); 4045: 4046: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) 4047: { 4048: operands[1] = force_const_mem (QImode, operands[1]); 4049: if (! memory_address_p (QImode, XEXP (operands[1], 0)) 4050: && ! reload_in_progress) 4051: operands[1] = change_address (operands[1], QImode, 4052: XEXP (operands[1], 0)); 4053: } 4054: }") 4055: 4056: (define_insn "" 1.1.1.3 root 4057: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 4058: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 4059: "gpc_reg_operand (operands[0], QImode) 4060: || gpc_reg_operand (operands[1], QImode)" 1.1 root 4061: "@ 1.1.1.3 root 4062: mr %0,%1 1.1 root 4063: lbz%U1%X1 %0,%1 4064: stb%U0%X0 %1,%0 1.1.1.3 root 4065: {lil|li} %0,%1 1.1 root 4066: mf%1 %0 4067: mt%0 %1 1.1.1.3 root 4068: mt%0 %1 1.1 root 4069: cror 0,0,0" 1.1.1.3 root 4070: [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")]) 1.1 root 4071: 4072: ;; Here is how to move condition codes around. When we store CC data in 4073: ;; an integer register or memory, we store just the high-order 4 bits. 4074: ;; This lets us not shift in the most common case of CR0. 4075: (define_expand "movcc" 4076: [(set (match_operand:CC 0 "nonimmediate_operand" "") 4077: (match_operand:CC 1 "nonimmediate_operand" ""))] 4078: "" 4079: "") 4080: 4081: (define_insn "" 4082: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") 4083: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] 4084: "register_operand (operands[0], CCmode) 4085: || register_operand (operands[1], CCmode)" 4086: "@ 4087: mcrf %0,%1 4088: mtcrf 128,%1 1.1.1.2 root 4089: {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 1.1 root 4090: mfcr %0 1.1.1.2 root 4091: mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 1.1.1.3 root 4092: mr %0,%1 1.1.1.2 root 4093: {l%U1%X1|lwz%U1%X1} %0,%1 4094: {st%U0%U1|stw%U0%U1} %1,%0" 4095: [(set_attr "type" "*,*,*,compare,*,*,load,*") 4096: (set_attr "length" "*,*,12,*,8,*,*,*")]) 1.1 root 4097: 1.1.1.4 root 4098: ;; For floating-point, we normally deal with the floating-point registers 4099: ;; unless -msoft-float is used. The sole exception is that parameter passing 4100: ;; can produce floating-point values in fixed-point registers. Unless the 4101: ;; value is a simple constant or already in memory, we deal with this by 4102: ;; allocating memory and copying the value explicitly via that memory location. 1.1 root 4103: (define_expand "movsf" 4104: [(set (match_operand:SF 0 "nonimmediate_operand" "") 4105: (match_operand:SF 1 "any_operand" ""))] 4106: "" 4107: " 4108: { 4109: /* If we are called from reload, we might be getting a SUBREG of a hard 4110: reg. So expand it. */ 4111: if (GET_CODE (operands[0]) == SUBREG 4112: && GET_CODE (SUBREG_REG (operands[0])) == REG 4113: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) 4114: operands[0] = alter_subreg (operands[0]); 4115: if (GET_CODE (operands[1]) == SUBREG 4116: && GET_CODE (SUBREG_REG (operands[1])) == REG 4117: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) 4118: operands[1] = alter_subreg (operands[1]); 4119: 1.1.1.4 root 4120: if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM) 4121: operands[1] = force_reg (SFmode, operands[1]); 4122: 4123: else if (TARGET_HARD_FLOAT) 1.1 root 4124: { 1.1.1.4 root 4125: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) 1.1 root 4126: { 1.1.1.4 root 4127: /* If this is a store to memory or another integer register do the 4128: move directly. Otherwise store to a temporary stack slot and 4129: load from there into a floating point register. */ 4130: 4131: if (GET_CODE (operands[0]) == MEM 4132: || (GET_CODE (operands[0]) == REG 4133: && (REGNO (operands[0]) < 32 4134: || (reload_in_progress 4135: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) 4136: { 4137: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), 4138: operand_subword (operands[1], 0, 0, SFmode)); 4139: DONE; 4140: } 4141: else 4142: { 4143: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); 4144: 4145: emit_move_insn (stack_slot, operands[1]); 4146: emit_move_insn (operands[0], stack_slot); 4147: DONE; 4148: } 1.1 root 4149: } 1.1.1.4 root 4150: 4151: if (GET_CODE (operands[0]) == MEM) 1.1.1.3 root 4152: { 1.1.1.4 root 4153: /* If operands[1] is a register, it may have double-precision data 4154: in it, so truncate it to single precision. We need not do 4155: this for POWERPC. */ 4156: if (! TARGET_POWERPC && TARGET_HARD_FLOAT 4157: && GET_CODE (operands[1]) == REG) 4158: { 4159: rtx newreg 4160: = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); 4161: emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); 4162: operands[1] = newreg; 4163: } 1.1 root 4164: 1.1.1.4 root 4165: operands[1] = force_reg (SFmode, operands[1]); 1.1.1.3 root 4166: } 1.1 root 4167: 1.1.1.4 root 4168: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) 1.1.1.3 root 4169: { 1.1.1.4 root 4170: if (GET_CODE (operands[1]) == MEM 1.1 root 4171: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) 1.1.1.4 root 4172: || GET_CODE (operands[1]) == CONST_DOUBLE 1.1 root 4173: #endif 1.1.1.4 root 4174: || (GET_CODE (operands[1]) == REG 4175: && (REGNO (operands[1]) < 32 4176: || (reload_in_progress 4177: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)))) 4178: { 4179: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), 4180: operand_subword (operands[1], 0, 0, SFmode)); 4181: DONE; 4182: } 4183: else 4184: { 4185: rtx stack_slot = assign_stack_temp (SFmode, 4, 0); 4186: 4187: emit_move_insn (stack_slot, operands[1]); 4188: emit_move_insn (operands[0], stack_slot); 4189: DONE; 4190: } 1.1.1.3 root 4191: } 1.1 root 4192: } 4193: 4194: if (CONSTANT_P (operands[1])) 4195: { 4196: operands[1] = force_const_mem (SFmode, operands[1]); 4197: if (! memory_address_p (SFmode, XEXP (operands[1], 0)) 4198: && ! reload_in_progress) 4199: operands[1] = change_address (operands[1], SFmode, 4200: XEXP (operands[1], 0)); 4201: } 4202: }") 4203: 4204: (define_split 4205: [(set (match_operand:SF 0 "gpc_reg_operand" "") 4206: (match_operand:SF 1 "easy_fp_constant" ""))] 4207: "reload_completed && REGNO (operands[0]) <= 31" 4208: [(set (match_dup 2) (match_dup 3))] 4209: " 4210: { operands[2] = operand_subword (operands[0], 0, 0, SFmode); 4211: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") 1.1.1.4 root 4212: 1.1 root 4213: (define_insn "" 4214: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") 4215: (match_operand:SF 1 "input_operand" "f,m,f"))] 1.1.1.4 root 4216: "(gpc_reg_operand (operands[0], SFmode) 4217: || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" 1.1 root 4218: "@ 4219: fmr %0,%1 4220: lfs%U1%X1 %0,%1 1.1.1.3 root 4221: stfs%U0%X0 %1,%0" 4222: [(set_attr "type" "fp,fpload,*")]) 1.1.1.4 root 4223: 4224: (define_insn "" 4225: [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 4226: (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))] 4227: "(gpc_reg_operand (operands[0], SFmode) 4228: || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" 4229: "@ 4230: mr %0,%1 4231: {l%U1%X1|lwz%U1%X1} %0,%1 4232: {st%U0%X0|stw%U0%X0} %1,%0 4233: {lil|li} %0,%1 4234: {liu|lis} %0,%u1 4235: {cal|la} %0,%1(%*)" 4236: [(set_attr "type" "*,load,*,*,*,*")]) 4237: 1.1 root 4238: 4239: (define_expand "movdf" 4240: [(set (match_operand:DF 0 "nonimmediate_operand" "") 4241: (match_operand:DF 1 "any_operand" ""))] 4242: "" 4243: " 4244: { 1.1.1.2 root 4245: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1 root 4246: { 1.1.1.2 root 4247: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 4248: operand_subword_force (operands[1], 1, DFmode)); 4249: emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), 4250: operand_subword_force (operands[1], 0, DFmode)); 1.1 root 4251: DONE; 4252: } 4253: 1.1.1.2 root 4254: if (GET_CODE (operands[0]) != REG) 4255: operands[1] = force_reg (DFmode, operands[1]); 1.1 root 4256: 1.1.1.2 root 4257: if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) 1.1 root 4258: { 4259: operands[1] = force_const_mem (DFmode, operands[1]); 4260: if (! memory_address_p (DFmode, XEXP (operands[1], 0)) 4261: && ! reload_in_progress) 4262: operands[1] = change_address (operands[1], DFmode, 4263: XEXP (operands[1], 0)); 4264: } 4265: }") 4266: 4267: (define_split 4268: [(set (match_operand:DF 0 "gpc_reg_operand" "") 4269: (match_operand:DF 1 "easy_fp_constant" ""))] 4270: "reload_completed && REGNO (operands[0]) <= 31" 4271: [(set (match_dup 2) (match_dup 3)) 4272: (set (match_dup 4) (match_dup 5))] 4273: " 4274: { operands[2] = operand_subword (operands[0], 0, 0, DFmode); 4275: operands[3] = operand_subword (operands[1], 0, 0, DFmode); 4276: operands[4] = operand_subword (operands[0], 1, 0, DFmode); 4277: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") 1.1.1.2 root 4278: 4279: ;; Don't have reload use general registers to load a constant. First, 4280: ;; it might not work if the output operand has is the equivalent of 4281: ;; a non-offsettable memref, but also it is less efficient than loading 4282: ;; the constant into an FP register, since it will probably be used there. 4283: ;; The "??" is a kludge until we can figure out a more reasonable way 4284: ;; of handling these non-offsettable values. 4285: (define_insn "" 4286: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") 4287: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] 1.1.1.4 root 4288: "! TARGET_POWERPC64 && TARGET_HARD_FLOAT 4289: && (register_operand (operands[0], DFmode) 4290: || register_operand (operands[1], DFmode))" 1.1.1.2 root 4291: "* 4292: { 4293: switch (which_alternative) 4294: { 4295: case 0: 4296: /* We normally copy the low-numbered register first. However, if 4297: the first register operand 0 is the same as the second register of 4298: operand 1, we must copy in the opposite order. */ 4299: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 root 4300: return \"mr %L0,%L1\;mr %0,%1\"; 1.1.1.2 root 4301: else 1.1.1.3 root 4302: return \"mr %0,%1\;mr %L0,%L1\"; 1.1.1.2 root 4303: case 1: 4304: /* If the low-address word is used in the address, we must load it 4305: last. Otherwise, load it first. Note that we cannot have 4306: auto-increment in that case since the address register is known to be 4307: dead. */ 4308: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4309: operands [1], 0)) 4310: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 4311: else 4312: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 4313: case 2: 4314: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 4315: case 3: 4316: return \"#\"; 4317: case 4: 4318: return \"fmr %0,%1\"; 4319: case 5: 4320: return \"lfd%U1%X1 %0,%1\"; 4321: case 6: 4322: return \"stfd%U0%X0 %1,%0\"; 4323: } 4324: }" 4325: [(set_attr "type" "*,load,*,*,fp,fpload,*") 4326: (set_attr "length" "8,8,8,8,*,*,*")]) 1.1.1.3 root 4327: 4328: (define_insn "" 1.1.1.4 root 4329: [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r") 4330: (match_operand:DF 1 "input_operand" "r,o,r,G"))] 4331: "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT 4332: && (register_operand (operands[0], DFmode) 4333: || register_operand (operands[1], DFmode))" 4334: "* 4335: { 4336: switch (which_alternative) 4337: { 4338: case 0: 4339: /* We normally copy the low-numbered register first. However, if 4340: the first register operand 0 is the same as the second register of 4341: operand 1, we must copy in the opposite order. */ 4342: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 4343: return \"mr %L0,%L1\;mr %0,%1\"; 4344: else 4345: return \"mr %0,%1\;mr %L0,%L1\"; 4346: case 1: 4347: /* If the low-address word is used in the address, we must load it 4348: last. Otherwise, load it first. Note that we cannot have 4349: auto-increment in that case since the address register is known to be 4350: dead. */ 4351: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4352: operands [1], 0)) 4353: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 4354: else 4355: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 4356: case 2: 4357: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 4358: case 3: 4359: return \"#\"; 4360: } 4361: }" 4362: [(set_attr "type" "*,load,*,*") 4363: (set_attr "length" "8,8,8,8")]) 4364: 4365: (define_insn "" 1.1.1.3 root 4366: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") 4367: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] 1.1.1.4 root 4368: "TARGET_POWERPC64 && TARGET_HARD_FLOAT 4369: && (register_operand (operands[0], DFmode) 4370: || register_operand (operands[1], DFmode))" 1.1.1.3 root 4371: "@ 4372: mr %0,%1 4373: ld%U1%X1 %0,%1 4374: sd%U0%X0 %1,%0 4375: # 4376: fmr %0,%1 4377: lfd%U1%X1 %0,%1 4378: stfd%U0%X0 %1,%0" 4379: [(set_attr "type" "*,load,*,*,fp,fpload,*")]) 1.1.1.4 root 4380: 4381: (define_insn "" 4382: [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r") 4383: (match_operand:DF 1 "input_operand" "r,o,r,G"))] 4384: "TARGET_POWERPC64 && TARGET_SOFT_FLOAT 4385: && (register_operand (operands[0], DFmode) 4386: || register_operand (operands[1], DFmode))" 4387: "@ 4388: mr %0,%1 4389: ld%U1%X1 %0,%1 4390: sd%U0%X0 %1,%0 4391: #" 4392: [(set_attr "type" "*,load,*,*")]) 1.1 root 4393: 4394: ;; Next come the multi-word integer load and store and the load and store 4395: ;; multiple insns. 4396: (define_expand "movdi" 4397: [(set (match_operand:DI 0 "general_operand" "") 4398: (match_operand:DI 1 "general_operand" ""))] 4399: "" 4400: " 4401: { 1.1.1.4 root 4402: if (GET_CODE (operands[0]) == MEM) 4403: operands[1] = force_reg (DImode, operands[1]); 4404: 1.1 root 4405: if (GET_CODE (operands[1]) == CONST_DOUBLE 4406: || GET_CODE (operands[1]) == CONST_INT) 4407: { 1.1.1.4 root 4408: HOST_WIDE_INT low; 4409: HOST_WIDE_INT high; 4410: 4411: if (GET_CODE (operands[1]) == CONST_DOUBLE) 4412: { 4413: low = CONST_DOUBLE_LOW (operands[1]); 4414: high = CONST_DOUBLE_HIGH (operands[1]); 4415: } 4416: else 4417: { 4418: low = INTVAL (operands[1]); 4419: high = (low < 0) ? ~0 : 0; 4420: } 4421: 4422: emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN), 4423: GEN_INT (low)); 4424: 4425: emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], !WORDS_BIG_ENDIAN), 4426: GEN_INT (high)); 1.1 root 4427: DONE; 4428: } 4429: 1.1.1.3 root 4430: /* Stores between FPR and any non-FPR registers must go through a 4431: temporary stack slot. */ 4432: 4433: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG 4434: && ((FP_REGNO_P (REGNO (operands[0])) 4435: && ! FP_REGNO_P (REGNO (operands[1]))) 4436: || (FP_REGNO_P (REGNO (operands[1])) 4437: && ! FP_REGNO_P (REGNO (operands[0]))))) 4438: { 4439: rtx stack_slot = assign_stack_temp (DImode, 8, 0); 4440: 4441: emit_move_insn (stack_slot, operands[1]); 4442: emit_move_insn (operands[0], stack_slot); 4443: DONE; 4444: } 1.1 root 4445: }") 4446: 4447: (define_insn "" 1.1.1.3 root 4448: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m") 4449: (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))] 4450: "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) 4451: || gpc_reg_operand (operands[1], DImode))" 1.1 root 4452: "* 4453: { 4454: switch (which_alternative) 4455: { 4456: case 0: 4457: /* We normally copy the low-numbered register first. However, if 4458: the first register operand 0 is the same as the second register of 4459: operand 1, we must copy in the opposite order. */ 4460: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 1.1.1.3 root 4461: return \"mr %L0,%L1\;mr %0,%1\"; 1.1 root 4462: else 1.1.1.3 root 4463: return \"mr %0,%1\;mr %L0,%L1\"; 1.1 root 4464: case 1: 4465: /* If the low-address word is used in the address, we must load it 4466: last. Otherwise, load it first. Note that we cannot have 4467: auto-increment in that case since the address register is known to be 4468: dead. */ 4469: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4470: operands [1], 0)) 1.1.1.2 root 4471: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 1.1 root 4472: else 1.1.1.2 root 4473: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 1.1 root 4474: case 2: 1.1.1.2 root 4475: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 1.1.1.3 root 4476: case 3: 4477: return \"fmr %0,%1\"; 4478: case 4: 4479: return \"lfd%U1%X1 %0,%1\"; 4480: case 5: 4481: return \"stfd%U0%X0 %1,%0\"; 1.1 root 4482: } 4483: }" 1.1.1.3 root 4484: [(set_attr "type" "*,load,*,fp,fpload,*") 4485: (set_attr "length" "8,8,8,*,*,*")]) 4486: 4487: (define_insn "" 4488: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h") 4489: (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))] 4490: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) 4491: || gpc_reg_operand (operands[1], DImode))" 4492: "@ 4493: mr %0,%1 4494: ld%U1%X1 %0,%1 4495: sd%U0%X0 %1,%0 4496: li %0,%1 4497: lis %0,%u1 4498: {cal|la} %0,%1(%*) 4499: fmr %0,%1 4500: lfd%U1%X1 %0,%1 4501: stfd%U0%X0 %1,%0 4502: mf%1 %0 4503: mt%0 %1" 4504: [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")]) 1.1 root 4505: 4506: ;; TImode is similar, except that we usually want to compute the address into 4507: ;; a register and use lsi/stsi (the exception is during reload). MQ is also 1.1.1.2 root 4508: ;; clobbered in stsi for POWER, so we need a SCRATCH for it. 1.1 root 4509: (define_expand "movti" 4510: [(parallel [(set (match_operand:TI 0 "general_operand" "") 4511: (match_operand:TI 1 "general_operand" "")) 4512: (clobber (scratch:SI))])] 1.1.1.4 root 4513: "TARGET_STRING || TARGET_POWERPC64" 1.1 root 4514: " 4515: { 4516: if (GET_CODE (operands[0]) == MEM) 4517: operands[1] = force_reg (TImode, operands[1]); 4518: 4519: if (GET_CODE (operands[0]) == MEM 4520: && GET_CODE (XEXP (operands[0], 0)) != REG 4521: && ! reload_in_progress) 4522: operands[0] = change_address (operands[0], TImode, 4523: copy_addr_to_reg (XEXP (operands[0], 0))); 4524: 4525: if (GET_CODE (operands[1]) == MEM 4526: && GET_CODE (XEXP (operands[1], 0)) != REG 4527: && ! reload_in_progress) 4528: operands[1] = change_address (operands[1], TImode, 4529: copy_addr_to_reg (XEXP (operands[1], 0))); 4530: }") 4531: 4532: ;; We say that MQ is clobbered in the last alternative because the first 4533: ;; alternative would never get used otherwise since it would need a reload 4534: ;; while the 2nd alternative would not. We put memory cases first so they 4535: ;; are preferred. Otherwise, we'd try to reload the output instead of 4536: ;; giving the SCRATCH mq. 4537: (define_insn "" 1.1.1.3 root 4538: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 1.1 root 4539: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) 4540: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] 1.1.1.4 root 4541: "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 4542: && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 1.1 root 4543: "* 4544: { 4545: switch (which_alternative) 4546: { 1.1.1.4 root 4547: default: 4548: abort (); 4549: 1.1 root 4550: case 0: 1.1.1.2 root 4551: return \"{stsi|stswi} %1,%P0,16\"; 1.1 root 4552: 4553: case 1: 1.1.1.2 root 4554: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 1.1 root 4555: 4556: case 2: 4557: /* Normally copy registers with lowest numbered register copied first. 4558: But copy in the other order if the first register of the output 4559: is the second, third, or fourth register in the input. */ 4560: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 4561: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 1.1.1.3 root 4562: return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 1.1 root 4563: else 1.1.1.3 root 4564: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 1.1 root 4565: case 3: 4566: /* If the address is not used in the output, we can use lsi. Otherwise, 4567: fall through to generating four loads. */ 4568: if (! reg_overlap_mentioned_p (operands[0], operands[1])) 1.1.1.2 root 4569: return \"{lsi|lswi} %0,%P1,16\"; 1.1 root 4570: /* ... fall through ... */ 4571: case 4: 4572: /* If the address register is the same as the register for the lowest- 4573: addressed word, load it last. Similarly for the next two words. 4574: Otherwise load lowest address to highest. */ 4575: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4576: operands[1], 0)) 1.1.1.2 root 4577: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 1.1 root 4578: else if (refers_to_regno_p (REGNO (operands[0]) + 1, 4579: REGNO (operands[0]) + 2, operands[1], 0)) 1.1.1.2 root 4580: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 1.1 root 4581: else if (refers_to_regno_p (REGNO (operands[0]) + 2, 4582: REGNO (operands[0]) + 3, operands[1], 0)) 1.1.1.2 root 4583: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 1.1 root 4584: else 1.1.1.2 root 4585: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 1.1 root 4586: } 4587: }" 1.1.1.2 root 4588: [(set_attr "type" "*,load,load,*,*") 4589: (set_attr "length" "*,16,16,*,16")]) 1.1.1.3 root 4590: 4591: (define_insn "" 1.1.1.4 root 4592: [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") 4593: (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) 4594: (clobber (match_scratch:SI 2 "=X,X,X"))] 4595: "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64 4596: && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 4597: "* 4598: { 4599: switch (which_alternative) 4600: { 4601: default: 4602: abort (); 4603: 4604: case 0: 4605: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 4606: 4607: case 1: 4608: /* Normally copy registers with lowest numbered register copied first. 4609: But copy in the other order if the first register of the output 4610: is the second, third, or fourth register in the input. */ 4611: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 4612: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 4613: return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 4614: else 4615: return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 4616: case 2: 4617: /* If the address register is the same as the register for the lowest- 4618: addressed word, load it last. Similarly for the next two words. 4619: Otherwise load lowest address to highest. */ 4620: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4621: operands[1], 0)) 4622: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 4623: else if (refers_to_regno_p (REGNO (operands[0]) + 1, 4624: REGNO (operands[0]) + 2, operands[1], 0)) 4625: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 4626: else if (refers_to_regno_p (REGNO (operands[0]) + 2, 4627: REGNO (operands[0]) + 3, operands[1], 0)) 4628: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 4629: else 4630: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 4631: } 4632: }" 4633: [(set_attr "type" "load,*,*") 4634: (set_attr "length" "16,16,16")]) 4635: 4636: (define_insn "" 1.1.1.3 root 4637: [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") 4638: (match_operand:TI 1 "input_operand" "r,m,r"))] 4639: "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 4640: || gpc_reg_operand (operands[1], TImode))" 4641: "* 4642: { 4643: switch (which_alternative) 4644: { 4645: case 0: 4646: /* We normally copy the low-numbered register first. However, if 4647: the first register operand 0 is the same as the second register of 4648: operand 1, we must copy in the opposite order. */ 4649: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 4650: return \"mr %L0,%L1\;mr %0,%1\"; 4651: else 4652: return \"mr %0,%1\;mr %L0,%L1\"; 4653: case 1: 4654: /* If the low-address word is used in the address, we must load it 4655: last. Otherwise, load it first. Note that we cannot have 4656: auto-increment in that case since the address register is known to be 4657: dead. */ 4658: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 4659: operands [1], 0)) 4660: return \"ld %L0,%L1\;ld %0,%1\"; 4661: else 4662: return \"ld%U1 %0,%1\;ld %L0,%L1\"; 4663: case 2: 4664: return \"std%U0 %1,%0\;std %L1,%L0\"; 4665: } 4666: }" 4667: [(set_attr "type" "*,load,*") 4668: (set_attr "length" "8,8,8")]) 1.1 root 4669: 4670: (define_expand "load_multiple" 4671: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4672: (match_operand:SI 1 "" "")) 4673: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 root 4674: "TARGET_STRING" 1.1 root 4675: " 4676: { 4677: int regno; 4678: int count; 4679: rtx from; 4680: int i; 4681: 4682: /* Support only loading a constant number of fixed-point registers from 4683: memory and only bother with this if more than two; the machine 4684: doesn't support more than eight. */ 4685: if (GET_CODE (operands[2]) != CONST_INT 4686: || INTVAL (operands[2]) <= 2 4687: || INTVAL (operands[2]) > 8 4688: || GET_CODE (operands[1]) != MEM 4689: || GET_CODE (operands[0]) != REG 4690: || REGNO (operands[0]) >= 32) 4691: FAIL; 4692: 4693: count = INTVAL (operands[2]); 4694: regno = REGNO (operands[0]); 4695: 4696: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); 4697: from = force_reg (SImode, XEXP (operands[1], 0)); 4698: 4699: for (i = 0; i < count; i++) 4700: XVECEXP (operands[3], 0, i) 4701: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), 4702: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); 4703: }") 4704: 4705: (define_insn "" 4706: [(match_parallel 0 "load_multiple_operation" 4707: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 1.1.1.4 root 4708: (mem:SI (match_operand:SI 2 "register_operand" "b")))])] 4709: "TARGET_STRING" 1.1 root 4710: "* 4711: { 4712: /* We have to handle the case where the pseudo used to contain the address 1.1.1.4 root 4713: is assigned to one of the output registers. */ 4714: int i, j; 4715: int words = XVECLEN (operands[0], 0); 4716: rtx xop[10]; 1.1 root 4717: 1.1.1.4 root 4718: if (XVECLEN (operands[0], 0) == 1) 4719: return \"{l|lwz} %1,0(%2)\"; 4720: 4721: for (i = 0; i < words; i++) 1.1 root 4722: if (refers_to_regno_p (REGNO (operands[1]) + i, 4723: REGNO (operands[1]) + i + 1, operands[2], 0)) 4724: { 1.1.1.4 root 4725: if (i == words-1) 4726: { 4727: xop[0] = operands[1]; 4728: xop[1] = operands[2]; 4729: xop[2] = GEN_INT (4 * (words-1)); 4730: output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); 4731: return \"\"; 4732: } 4733: else if (i == 0) 4734: { 4735: xop[0] = operands[1]; 4736: xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 4737: xop[2] = GEN_INT (4 * (words-1)); 4738: output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); 4739: return \"\"; 4740: } 4741: else 4742: { 4743: for (j = 0; j < words; j++) 4744: if (j != i) 4745: { 4746: xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j); 4747: xop[1] = operands[2]; 4748: xop[2] = GEN_INT (j * 4); 4749: output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); 4750: } 4751: xop[0] = operands[2]; 4752: xop[1] = GEN_INT (i * 4); 4753: output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); 4754: return \"\"; 4755: } 1.1 root 4756: } 4757: 1.1.1.4 root 4758: return \"{lsi|lswi} %1,%2,%N0\"; 1.1 root 4759: }" 1.1.1.2 root 4760: [(set_attr "type" "load") 1.1.1.4 root 4761: (set_attr "length" "32")]) 1.1 root 4762: 1.1.1.2 root 4763: 1.1 root 4764: (define_expand "store_multiple" 4765: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 4766: (match_operand:SI 1 "" "")) 4767: (clobber (scratch:SI)) 4768: (use (match_operand:SI 2 "" ""))])] 1.1.1.4 root 4769: "TARGET_STRING" 1.1 root 4770: " 4771: { 4772: int regno; 4773: int count; 4774: rtx to; 4775: int i; 4776: 4777: /* Support only storing a constant number of fixed-point registers to 4778: memory and only bother with this if more than two; the machine 4779: doesn't support more than eight. */ 4780: if (GET_CODE (operands[2]) != CONST_INT 4781: || INTVAL (operands[2]) <= 2 4782: || INTVAL (operands[2]) > 8 4783: || GET_CODE (operands[0]) != MEM 4784: || GET_CODE (operands[1]) != REG 4785: || REGNO (operands[1]) >= 32) 4786: FAIL; 4787: 4788: count = INTVAL (operands[2]); 4789: regno = REGNO (operands[1]); 4790: 4791: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); 4792: to = force_reg (SImode, XEXP (operands[0], 0)); 4793: 4794: XVECEXP (operands[3], 0, 0) 4795: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); 4796: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, 4797: gen_rtx (SCRATCH, SImode)); 4798: 4799: for (i = 1; i < count; i++) 4800: XVECEXP (operands[3], 0, i + 1) 4801: = gen_rtx (SET, VOIDmode, 4802: gen_rtx (MEM, SImode, plus_constant (to, i * 4)), 4803: gen_rtx (REG, SImode, regno + i)); 4804: }") 4805: 4806: (define_insn "" 4807: [(match_parallel 0 "store_multiple_operation" 4808: [(set (match_operand:SI 1 "indirect_operand" "=Q") 4809: (match_operand:SI 2 "gpc_reg_operand" "r")) 4810: (clobber (match_scratch:SI 3 "=q"))])] 1.1.1.4 root 4811: "TARGET_STRING && TARGET_POWER" 1.1.1.2 root 4812: "{stsi|stswi} %2,%P1,%O0") 1.1.1.4 root 4813: 4814: (define_insn "" 4815: [(match_parallel 0 "store_multiple_operation" 4816: [(set (mem:SI (match_operand:SI 1 "register_operand" "b")) 4817: (match_operand:SI 2 "gpc_reg_operand" "r")) 4818: (clobber (match_scratch:SI 3 "X"))])] 4819: "TARGET_STRING && !TARGET_POWER" 4820: "{stsi|stswi} %2,%1,%O0") 4821: 1.1 root 4822: 1.1.1.4 root 4823: ;; String/block move insn. 4824: ;; Argument 0 is the destination 4825: ;; Argument 1 is the source 4826: ;; Argument 2 is the length 4827: ;; Argument 3 is the alignment 4828: 4829: (define_expand "movstrsi" 1.1.1.5 ! root 4830: [(parallel [(set (match_operand:BLK 0 "" "") ! 4831: (match_operand:BLK 1 "" "")) ! 4832: (use (match_operand:SI 2 "" "")) ! 4833: (use (match_operand:SI 3 "" ""))])] 1.1.1.4 root 4834: "" 4835: " 4836: { 4837: if (expand_block_move (operands)) 4838: DONE; 4839: else 4840: FAIL; 4841: }") 4842: 4843: ;; Move up to 32 bytes at a time. The fixed registers are needed because the 4844: ;; register allocator doesn't have a clue about allocating 8 word registers 4845: (define_expand "movstrsi_8reg" 1.1.1.5 ! root 4846: [(parallel [(set (match_operand 0 "" "") ! 4847: (match_operand 1 "" "")) ! 4848: (use (match_operand 2 "" "")) ! 4849: (use (match_operand 3 "" "")) 1.1.1.4 root 4850: (clobber (reg:SI 5)) 4851: (clobber (reg:SI 6)) 4852: (clobber (reg:SI 7)) 4853: (clobber (reg:SI 8)) 4854: (clobber (reg:SI 9)) 4855: (clobber (reg:SI 10)) 4856: (clobber (reg:SI 11)) 4857: (clobber (reg:SI 12)) 4858: (clobber (match_scratch:SI 4 ""))])] 4859: "TARGET_STRING" 4860: "") 4861: 4862: (define_insn "" 4863: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 4864: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 4865: (use (match_operand:SI 2 "immediate_operand" "i")) 4866: (use (match_operand:SI 3 "immediate_operand" "i")) 4867: (clobber (match_operand:SI 4 "register_operand" "=r")) 4868: (clobber (reg:SI 6)) 4869: (clobber (reg:SI 7)) 4870: (clobber (reg:SI 8)) 4871: (clobber (reg:SI 9)) 4872: (clobber (reg:SI 10)) 4873: (clobber (reg:SI 11)) 4874: (clobber (reg:SI 12)) 4875: (clobber (match_scratch:SI 5 "=q"))] 4876: "TARGET_STRING && TARGET_POWER 4877: && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) 4878: && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 4879: && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 4880: && REGNO (operands[4]) == 5" 4881: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 4882: [(set_attr "type" "load") ! 4883: (set_attr "length" "8")]) 1.1.1.4 root 4884: 4885: (define_insn "" 4886: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 4887: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 4888: (use (match_operand:SI 2 "immediate_operand" "i")) 4889: (use (match_operand:SI 3 "immediate_operand" "i")) 4890: (clobber (match_operand:SI 4 "register_operand" "=r")) 4891: (clobber (reg:SI 6)) 4892: (clobber (reg:SI 7)) 4893: (clobber (reg:SI 8)) 4894: (clobber (reg:SI 9)) 4895: (clobber (reg:SI 10)) 4896: (clobber (reg:SI 11)) 4897: (clobber (reg:SI 12)) 4898: (clobber (match_scratch:SI 5 "X"))] 4899: "TARGET_STRING && !TARGET_POWER 4900: && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) 4901: && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 4902: && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 4903: && REGNO (operands[4]) == 5" 4904: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 4905: [(set_attr "type" "load") ! 4906: (set_attr "length" "8")]) 1.1.1.4 root 4907: 4908: ;; Move up to 24 bytes at a time. The fixed registers are needed because the 4909: ;; register allocator doesn't have a clue about allocating 6 word registers 4910: (define_expand "movstrsi_6reg" 1.1.1.5 ! root 4911: [(parallel [(set (match_operand 0 "" "") ! 4912: (match_operand 1 "" "")) ! 4913: (use (match_operand 2 "" "")) ! 4914: (use (match_operand 3 "" "")) 1.1.1.4 root 4915: (clobber (reg:SI 7)) 4916: (clobber (reg:SI 8)) 4917: (clobber (reg:SI 9)) 4918: (clobber (reg:SI 10)) 4919: (clobber (reg:SI 11)) 4920: (clobber (reg:SI 12)) 4921: (clobber (match_scratch:SI 4 ""))])] 4922: "TARGET_STRING" 4923: "") 4924: 4925: (define_insn "" 4926: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 4927: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 4928: (use (match_operand:SI 2 "immediate_operand" "i")) 4929: (use (match_operand:SI 3 "immediate_operand" "i")) 4930: (clobber (match_operand:SI 4 "register_operand" "=r")) 4931: (clobber (reg:SI 8)) 4932: (clobber (reg:SI 9)) 4933: (clobber (reg:SI 10)) 4934: (clobber (reg:SI 11)) 4935: (clobber (reg:SI 12)) 4936: (clobber (match_scratch:SI 5 "=q"))] 4937: "TARGET_STRING && TARGET_POWER 4938: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 4939: && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) 4940: && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) 4941: && REGNO (operands[4]) == 7" 4942: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 4943: [(set_attr "type" "load") ! 4944: (set_attr "length" "8")]) 1.1.1.4 root 4945: 4946: (define_insn "" 4947: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 4948: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 4949: (use (match_operand:SI 2 "immediate_operand" "i")) 4950: (use (match_operand:SI 3 "immediate_operand" "i")) 4951: (clobber (match_operand:SI 4 "register_operand" "=r")) 4952: (clobber (reg:SI 8)) 4953: (clobber (reg:SI 9)) 4954: (clobber (reg:SI 10)) 4955: (clobber (reg:SI 11)) 4956: (clobber (reg:SI 12)) 4957: (clobber (match_scratch:SI 5 "X"))] 4958: "TARGET_STRING && !TARGET_POWER 4959: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 4960: && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) 4961: && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) 4962: && REGNO (operands[4]) == 7" 4963: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 4964: [(set_attr "type" "load") ! 4965: (set_attr "length" "8")]) 1.1.1.4 root 4966: 4967: ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems 4968: ;; with TImode 4969: (define_expand "movstrsi_4reg" 1.1.1.5 ! root 4970: [(parallel [(set (match_operand 0 "" "") ! 4971: (match_operand 1 "" "")) ! 4972: (use (match_operand 2 "" "")) ! 4973: (use (match_operand 3 "" "")) 1.1.1.4 root 4974: (clobber (reg:SI 9)) 4975: (clobber (reg:SI 10)) 4976: (clobber (reg:SI 11)) 4977: (clobber (reg:SI 12)) 4978: (clobber (match_scratch:SI 4 ""))])] 4979: "TARGET_STRING" 4980: "") 4981: 4982: (define_insn "" 4983: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 4984: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 4985: (use (match_operand:SI 2 "immediate_operand" "i")) 4986: (use (match_operand:SI 3 "immediate_operand" "i")) 4987: (clobber (match_operand:SI 4 "register_operand" "=r")) 4988: (clobber (reg:SI 10)) 4989: (clobber (reg:SI 11)) 4990: (clobber (reg:SI 12)) 4991: (clobber (match_scratch:SI 5 "=q"))] 4992: "TARGET_STRING && TARGET_POWER 4993: && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 4994: && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) 4995: && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) 4996: && REGNO (operands[4]) == 9" 4997: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 4998: [(set_attr "type" "load") ! 4999: (set_attr "length" "8")]) 1.1.1.4 root 5000: 5001: (define_insn "" 5002: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 5003: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 5004: (use (match_operand:SI 2 "immediate_operand" "i")) 5005: (use (match_operand:SI 3 "immediate_operand" "i")) 5006: (clobber (match_operand:SI 4 "register_operand" "=r")) 5007: (clobber (reg:SI 10)) 5008: (clobber (reg:SI 11)) 5009: (clobber (reg:SI 12)) 5010: (clobber (match_scratch:SI 5 "X"))] 5011: "TARGET_STRING && !TARGET_POWER 5012: && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 5013: && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) 5014: && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) 5015: && REGNO (operands[4]) == 9" 5016: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 5017: [(set_attr "type" "load") ! 5018: (set_attr "length" "8")]) 1.1.1.4 root 5019: 5020: ;; Move up to 8 bytes at a time. 5021: (define_expand "movstrsi_2reg" 1.1.1.5 ! root 5022: [(parallel [(set (match_operand 0 "" "") ! 5023: (match_operand 1 "" "")) ! 5024: (use (match_operand 2 "" "")) ! 5025: (use (match_operand 3 "" "")) 1.1.1.4 root 5026: (clobber (match_scratch:DI 4 "")) 5027: (clobber (match_scratch:SI 5 ""))])] 5028: "TARGET_STRING && !TARGET_64BIT" 5029: "") 5030: 5031: (define_insn "" 5032: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 5033: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 5034: (use (match_operand:SI 2 "immediate_operand" "i")) 5035: (use (match_operand:SI 3 "immediate_operand" "i")) 5036: (clobber (match_scratch:DI 4 "=&r")) 5037: (clobber (match_scratch:SI 5 "=q"))] 5038: "TARGET_STRING && TARGET_POWER && !TARGET_64BIT 5039: && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 5040: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 5041: [(set_attr "type" "load") ! 5042: (set_attr "length" "8")]) 1.1.1.4 root 5043: 5044: (define_insn "" 5045: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 5046: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 5047: (use (match_operand:SI 2 "immediate_operand" "i")) 5048: (use (match_operand:SI 3 "immediate_operand" "i")) 5049: (clobber (match_scratch:DI 4 "=&r")) 5050: (clobber (match_scratch:SI 5 "X"))] 5051: "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT 5052: && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 5053: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 5054: [(set_attr "type" "load") ! 5055: (set_attr "length" "8")]) 1.1.1.4 root 5056: 5057: ;; Move up to 4 bytes at a time. 5058: (define_expand "movstrsi_1reg" 1.1.1.5 ! root 5059: [(parallel [(set (match_operand 0 "" "") ! 5060: (match_operand 1 "" "")) ! 5061: (use (match_operand 2 "" "")) ! 5062: (use (match_operand 3 "" "")) 1.1.1.4 root 5063: (clobber (match_scratch:SI 4 "")) 5064: (clobber (match_scratch:SI 5 ""))])] 5065: "TARGET_STRING" 5066: "") 5067: 5068: (define_insn "" 5069: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 5070: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 5071: (use (match_operand:SI 2 "immediate_operand" "i")) 5072: (use (match_operand:SI 3 "immediate_operand" "i")) 5073: (clobber (match_scratch:SI 4 "=&r")) 5074: (clobber (match_scratch:SI 5 "=q"))] 5075: "TARGET_STRING && TARGET_POWER 5076: && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 5077: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 5078: [(set_attr "type" "load") ! 5079: (set_attr "length" "8")]) 1.1.1.4 root 5080: 5081: (define_insn "" 5082: [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) 5083: (mem:BLK (match_operand:SI 1 "register_operand" "b"))) 5084: (use (match_operand:SI 2 "immediate_operand" "i")) 5085: (use (match_operand:SI 3 "immediate_operand" "i")) 5086: (clobber (match_scratch:SI 4 "=&r")) 5087: (clobber (match_scratch:SI 5 "X"))] 5088: "TARGET_STRING && !TARGET_POWER 5089: && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 5090: "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 1.1.1.5 ! root 5091: [(set_attr "type" "load") ! 5092: (set_attr "length" "8")]) 1.1.1.4 root 5093: 5094: 5095: ;; Define insns that do load or store with update. Some of these we can 1.1 root 5096: ;; get by using pre-decrement or pre-increment, but the hardware can also 5097: ;; do cases where the increment is not the size of the object. 5098: ;; 5099: ;; In all these cases, we use operands 0 and 1 for the register being 5100: ;; incremented because those are the operands that local-alloc will 5101: ;; tie and these are the pair most likely to be tieable (and the ones 5102: ;; that will benefit the most). 5103: 5104: (define_insn "" 1.1.1.3 root 5105: [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 5106: (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 5107: (match_operand:DI 2 "reg_or_short_operand" "r,I")))) 5108: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 5109: (plus:DI (match_dup 1) (match_dup 2)))] 5110: "TARGET_POWERPC64" 5111: "@ 5112: ldux %3,%0,%2 5113: ldu %3,%2(%0)" 5114: [(set_attr "type" "load")]) 5115: 5116: (define_insn "" 1.1.1.4 root 5117: [(set (match_operand:DI 3 "gpc_reg_operand" "=r") 5118: (sign_extend:DI 5119: (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") 5120: (match_operand:DI 2 "gpc_reg_operand" "r"))))) 5121: (set (match_operand:DI 0 "gpc_reg_operand" "=b") 5122: (plus:DI (match_dup 1) (match_dup 2)))] 5123: "TARGET_POWERPC64" 5124: "lwaux %3,%0,%2" 5125: [(set_attr "type" "load")]) 5126: 5127: (define_insn "movdi_update" 1.1.1.3 root 5128: [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 5129: (match_operand:DI 2 "reg_or_short_operand" "r,I"))) 5130: (match_operand:DI 3 "gpc_reg_operand" "r,r")) 5131: (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 5132: (plus:DI (match_dup 1) (match_dup 2)))] 5133: "TARGET_POWERPC64" 5134: "@ 5135: stdux %3,%0,%2 5136: stdu %3,%2(%0)") 5137: 5138: (define_insn "" 1.1 root 5139: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5140: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5141: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5142: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5143: (plus:SI (match_dup 1) (match_dup 2)))] 5144: "" 5145: "@ 1.1.1.2 root 5146: {lux|lwzux} %3,%0,%2 5147: {lu|lwzu} %3,%2(%0)" 5148: [(set_attr "type" "load")]) 1.1 root 5149: 1.1.1.4 root 5150: (define_insn "movsi_update" 1.1 root 5151: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5152: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5153: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 5154: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5155: (plus:SI (match_dup 1) (match_dup 2)))] 5156: "" 5157: "@ 1.1.1.2 root 5158: {stux|stwux} %3,%0,%2 5159: {stu|stwu} %3,%2(%0)") 1.1 root 5160: 5161: (define_insn "" 5162: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 5163: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5164: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5165: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5166: (plus:SI (match_dup 1) (match_dup 2)))] 5167: "" 5168: "@ 5169: lhzux %3,%0,%2 5170: lhzu %3,%2(%0)" 1.1.1.2 root 5171: [(set_attr "type" "load")]) 1.1 root 5172: 5173: (define_insn "" 5174: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5175: (zero_extend:SI 5176: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5177: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5178: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5179: (plus:SI (match_dup 1) (match_dup 2)))] 5180: "" 5181: "@ 5182: lhzux %3,%0,%2 5183: lhzu %3,%2(%0)" 1.1.1.2 root 5184: [(set_attr "type" "load")]) 1.1 root 5185: 5186: (define_insn "" 5187: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5188: (sign_extend:SI 5189: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5190: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5191: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5192: (plus:SI (match_dup 1) (match_dup 2)))] 5193: "" 5194: "@ 5195: lhaux %3,%0,%2 5196: lhau %3,%2(%0)" 1.1.1.2 root 5197: [(set_attr "type" "load")]) 1.1 root 5198: 5199: (define_insn "" 5200: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5201: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5202: (match_operand:HI 3 "gpc_reg_operand" "r,r")) 5203: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5204: (plus:SI (match_dup 1) (match_dup 2)))] 5205: "" 5206: "@ 5207: sthux %3,%0,%2 1.1.1.2 root 5208: sthu %3,%2(%0)") 1.1 root 5209: 5210: (define_insn "" 5211: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 5212: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5213: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5214: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5215: (plus:SI (match_dup 1) (match_dup 2)))] 5216: "" 5217: "@ 5218: lbzux %3,%0,%2 5219: lbzu %3,%2(%0)" 1.1.1.2 root 5220: [(set_attr "type" "load")]) 1.1 root 5221: 5222: (define_insn "" 5223: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 5224: (zero_extend:SI 5225: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5226: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 5227: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5228: (plus:SI (match_dup 1) (match_dup 2)))] 5229: "" 5230: "@ 5231: lbzux %3,%0,%2 5232: lbzu %3,%2(%0)" 1.1.1.2 root 5233: [(set_attr "type" "load")]) 1.1 root 5234: 5235: (define_insn "" 5236: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5237: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5238: (match_operand:QI 3 "gpc_reg_operand" "r,r")) 5239: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5240: (plus:SI (match_dup 1) (match_dup 2)))] 5241: "" 5242: "@ 5243: stbux %3,%0,%2 5244: stbu %3,%2(%0)") 5245: 5246: (define_insn "" 5247: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 1.1.1.3 root 5248: (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 1.1 root 5249: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5250: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5251: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 root 5252: "TARGET_HARD_FLOAT" 1.1 root 5253: "@ 5254: lfsux %3,%0,%2 5255: lfsu %3,%2(%0)" 1.1.1.2 root 5256: [(set_attr "type" "fpload")]) 1.1 root 5257: 5258: (define_insn "" 5259: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5260: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5261: (match_operand:SF 3 "gpc_reg_operand" "f,f")) 5262: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5263: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 root 5264: "TARGET_HARD_FLOAT" 1.1 root 5265: "@ 1.1.1.3 root 5266: stfsux %3,%0,%2 5267: stfsu %3,%2(%0)") 1.1 root 5268: 5269: (define_insn "" 5270: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 5271: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5272: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 5273: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5274: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 root 5275: "TARGET_HARD_FLOAT" 1.1 root 5276: "@ 5277: lfdux %3,%0,%2 5278: lfdu %3,%2(%0)" 1.1.1.2 root 5279: [(set_attr "type" "fpload")]) 1.1 root 5280: 5281: (define_insn "" 5282: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 5283: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 5284: (match_operand:DF 3 "gpc_reg_operand" "f,f")) 5285: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 5286: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.4 root 5287: "TARGET_HARD_FLOAT" 1.1 root 5288: "@ 5289: stfdux %3,%0,%2 5290: stfdu %3,%2(%0)") 1.1.1.4 root 5291: 5292: ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. 5293: 5294: (define_peephole 5295: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5296: (match_operand:DF 1 "memory_operand" "")) 5297: (set (match_operand:DF 2 "gpc_reg_operand" "=f") 5298: (match_operand:DF 3 "memory_operand" ""))] 5299: "TARGET_POWER2 5300: && TARGET_HARD_FLOAT 5301: && registers_ok_for_quad_peep (operands[0], operands[2]) 5302: && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) 5303: && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" 5304: "lfq%U1%X1 %0,%1") 5305: 5306: (define_peephole 5307: [(set (match_operand:DF 0 "memory_operand" "") 5308: (match_operand:DF 1 "gpc_reg_operand" "f")) 5309: (set (match_operand:DF 2 "memory_operand" "") 5310: (match_operand:DF 3 "gpc_reg_operand" "f"))] 5311: "TARGET_POWER2 5312: && TARGET_HARD_FLOAT 5313: && registers_ok_for_quad_peep (operands[1], operands[3]) 5314: && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) 5315: && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" 5316: "stfq%U0%X0 %1,%0") 1.1 root 5317: 5318: ;; Next come insns related to the calling sequence. 5319: ;; 5320: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 1.1.1.4 root 5321: ;; We move the back-chain and decrement the stack pointer. 1.1 root 5322: 5323: (define_expand "allocate_stack" 5324: [(set (reg:SI 1) 5325: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] 5326: "" 5327: " 1.1.1.4 root 5328: { rtx chain = gen_reg_rtx (Pmode); 1.1 root 5329: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); 1.1.1.4 root 5330: rtx neg_op0; 1.1 root 5331: 5332: emit_move_insn (chain, stack_bot); 1.1.1.4 root 5333: 5334: if (GET_CODE (operands[0]) != CONST_INT 5335: || INTVAL (operands[0]) < -32767 5336: || INTVAL (operands[0]) > 32768) 5337: { 5338: neg_op0 = gen_reg_rtx (Pmode); 5339: if (TARGET_POWERPC64) 5340: emit_insn (gen_negdi2 (neg_op0, operands[0])); 5341: else 5342: emit_insn (gen_negsi2 (neg_op0, operands[0])); 5343: } 5344: else 5345: neg_op0 = GEN_INT (- INTVAL (operands[0])); 5346: 5347: if (TARGET_POWERPC64) 5348: emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); 5349: else 5350: emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); 5351: 1.1 root 5352: DONE; 5353: }") 5354: 5355: ;; These patterns say how to save and restore the stack pointer. We need not 5356: ;; save the stack pointer at function level since we are careful to 5357: ;; preserve the backchain. At block level, we have to restore the backchain 5358: ;; when we restore the stack pointer. 5359: ;; 5360: ;; For nonlocal gotos, we must save both the stack pointer and its 5361: ;; backchain and restore both. Note that in the nonlocal case, the 5362: ;; save area is a memory location. 5363: 5364: (define_expand "save_stack_function" 5365: [(use (const_int 0))] 5366: "" 5367: "") 5368: 5369: (define_expand "restore_stack_function" 5370: [(use (const_int 0))] 5371: "" 5372: "") 5373: 5374: (define_expand "restore_stack_block" 5375: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) 5376: (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) 5377: (set (mem:SI (match_dup 0)) (match_dup 2))] 5378: "" 5379: " 5380: { operands[2] = gen_reg_rtx (SImode); }") 5381: 5382: (define_expand "save_stack_nonlocal" 5383: [(match_operand:DI 0 "memory_operand" "") 5384: (match_operand:SI 1 "register_operand" "")] 5385: "" 5386: " 5387: { 5388: rtx temp = gen_reg_rtx (SImode); 5389: 5390: /* Copy the backchain to the first word, sp to the second. */ 5391: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); 5392: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); 5393: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); 5394: DONE; 5395: }") 1.1.1.4 root 5396: 1.1 root 5397: (define_expand "restore_stack_nonlocal" 5398: [(match_operand:SI 0 "register_operand" "") 5399: (match_operand:DI 1 "memory_operand" "")] 5400: "" 5401: " 5402: { 5403: rtx temp = gen_reg_rtx (SImode); 5404: 5405: /* Restore the backchain from the first word, sp from the second. */ 5406: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); 5407: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); 5408: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); 5409: DONE; 5410: }") 5411: 5412: ;; A function pointer is a pointer to a data area whose first word contains 5413: ;; the actual address of the function, whose second word contains a pointer 5414: ;; to its TOC, and whose third word contains a value to place in the static 1.1.1.4 root 5415: ;; chain register (r11). Note that if we load the static chain, our 1.1 root 5416: ;; "trampoline" need not have any executable code. 5417: ;; 5418: ;; operands[0] is an SImode pseudo in which we place the address of the 5419: ;; function. 5420: ;; operands[1] is the address of data area of the function to call 5421: 5422: (define_expand "call_via_ptr" 5423: [(set (match_operand:SI 0 "gpc_reg_operand" "") 5424: (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 5425: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 5426: (reg:SI 2)) 5427: (set (reg:SI 2) 5428: (mem:SI (plus:SI (match_dup 1) 5429: (const_int 4)))) 5430: (set (reg:SI 11) 5431: (mem:SI (plus:SI (match_dup 1) 5432: (const_int 8)))) 5433: (use (reg:SI 2)) 5434: (use (reg:SI 11))] 5435: "" 5436: "") 5437: 5438: (define_expand "call" 5439: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) 5440: (match_operand 1 "" "")) 1.1.1.4 root 5441: (use (match_operand 2 "" "")) 1.1 root 5442: (clobber (scratch:SI))])] 5443: "" 5444: " 5445: { 5446: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 5447: abort (); 5448: 5449: operands[0] = XEXP (operands[0], 0); 5450: if (GET_CODE (operands[0]) != SYMBOL_REF) 5451: { 1.1.1.4 root 5452: #ifndef USING_SVR4_H 5453: /* AIX function pointers are really pointers to a three word area */ 1.1 root 5454: rtx temp = gen_reg_rtx (SImode); 5455: 5456: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); 5457: operands[0] = temp; 1.1.1.4 root 5458: #endif /* !USING_SVR4_H */ 1.1 root 5459: } 5460: }") 5461: 5462: (define_expand "call_value" 5463: [(parallel [(set (match_operand 0 "" "") 5464: (call (mem:SI (match_operand:SI 1 "address_operand" "")) 5465: (match_operand 2 "" ""))) 1.1.1.4 root 5466: (use (match_operand 3 "" "")) 1.1 root 5467: (clobber (scratch:SI))])] 5468: "" 5469: " 5470: { 5471: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 5472: abort (); 5473: 5474: operands[1] = XEXP (operands[1], 0); 5475: if (GET_CODE (operands[1]) != SYMBOL_REF) 5476: { 1.1.1.4 root 5477: #ifndef USING_SVR4_H 5478: /* AIX function pointers are really pointers to a three word area */ 1.1 root 5479: rtx temp = gen_reg_rtx (SImode); 5480: 5481: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); 5482: operands[1] = temp; 1.1.1.4 root 5483: #endif /* !USING_SVR4_H */ 1.1 root 5484: } 5485: }") 5486: 1.1.1.2 root 5487: ;; Call to function in current module. No TOC pointer reload needed. 1.1.1.4 root 5488: ;; Operand2 is non-zero if we are using the V.4 calling sequence and 5489: ;; either the function was not prototyped, or it was prototyped as a 5490: ;; variable argument function. It is > 0 if FP registers were passed 5491: ;; and < 0 if they were not. 1.1.1.2 root 5492: 5493: (define_insn "" 1.1.1.4 root 5494: [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 5495: (match_operand 1 "" "g,g")) 5496: (use (match_operand:SI 2 "immediate_operand" "O,n")) 5497: (clobber (match_scratch:SI 3 "=l,l"))] 1.1.1.2 root 5498: "" 1.1.1.4 root 5499: "* 5500: { 5501: if (INTVAL (operands[2]) > 0) 5502: return \"creqv 6,6,6\;bl %z0\"; 5503: 5504: else if (INTVAL (operands[2]) < 0) 5505: return \"crxor 6,6,6\;bl %z0\"; 5506: 5507: return \"bl %z0\"; 5508: }" 5509: [(set_attr "length" "4,8")]) 1.1.1.2 root 5510: 5511: ;; Call to function which may be in another module. Restore the TOC 1.1.1.4 root 5512: ;; pointer (r2) after the call unless this is System V. 5513: ;; Operand2 is non-zero if we are using the V.4 calling sequence and 5514: ;; either the function was not prototyped, or it was prototyped as a 5515: ;; variable argument function. It is > 0 if FP registers were passed 5516: ;; and < 0 if they were not. 1.1.1.2 root 5517: 1.1 root 5518: (define_insn "" 1.1.1.4 root 5519: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s,l,s")) 5520: (match_operand 1 "" "fg,fg,fg,fg")) 5521: (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) 5522: (clobber (match_scratch:SI 3 "=l,l,l,l"))] 1.1 root 5523: "" 1.1.1.4 root 5524: "* 5525: { 5526: if (INTVAL (operands[2]) > 0) 5527: output_asm_insn (\"creqv 6,6,6\", operands); 5528: 5529: else if (INTVAL (operands[2]) < 0) 5530: output_asm_insn (\"crxor 6,6,6\", operands); 5531: 5532: #ifndef USING_SVR4_H 5533: if (GET_CODE (operands[0]) == REG) 5534: return \"{brl|blrl}\;{l|lwz} 2,20(1)\"; 5535: 5536: return \"bl %z0\;%.\"; 5537: 5538: #else 5539: if (GET_CODE (operands[0]) == REG) 5540: return \"{brl|blrl}\"; 5541: 5542: return \"bl %z0\"; 5543: #endif 5544: }" 5545: [(set_attr "length" "8,8,12,12")]) 1.1.1.2 root 5546: 5547: (define_insn "" 1.1.1.4 root 5548: [(set (match_operand 0 "" "=fg,fg") 5549: (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 5550: (match_operand 2 "" "g,g"))) 5551: (use (match_operand:SI 3 "immediate_operand" "O,n")) 5552: (clobber (match_scratch:SI 4 "=l,l"))] 1.1.1.2 root 5553: "" 1.1.1.4 root 5554: "* 5555: { 5556: if (INTVAL (operands[3]) > 0) 5557: return \"creqv 6,6,6\;bl %z1\"; 5558: 5559: else if (INTVAL (operands[3]) < 0) 5560: return \"crxor 6,6,6\;bl %z1\"; 5561: 5562: return \"bl %z1\"; 5563: }" 5564: [(set_attr "length" "4,8")]) 1.1 root 5565: 5566: (define_insn "" 1.1.1.4 root 5567: [(set (match_operand 0 "" "=fg,fg,fg,fg") 5568: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s,l,s")) 5569: (match_operand 2 "" "fg,fg,fg,fg"))) 5570: (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) 5571: (clobber (match_scratch:SI 4 "=l,l,l,l"))] 1.1 root 5572: "" 1.1.1.4 root 5573: "* 5574: { 5575: if (INTVAL (operands[3]) > 0) 5576: output_asm_insn (\"creqv 6,6,6\", operands); 5577: 5578: else if (INTVAL (operands[3]) < 0) 5579: output_asm_insn (\"crxor 6,6,6\", operands); 5580: 5581: #ifndef USING_SVR4_H 5582: if (GET_CODE (operands[1]) == REG) 5583: return \"{brl|blrl}\;{l|lwz} 2,20(1)\"; 5584: 5585: return \"bl %z1\;%.\"; 5586: 5587: #else 5588: if (GET_CODE (operands[1]) == REG) 5589: return \"{brl|blrl}\"; 5590: 5591: return \"bl %z1\"; 5592: #endif 5593: }" 5594: [(set_attr "length" "8,8,12,12")]) 1.1 root 5595: 5596: ;; Call subroutine returning any type. 5597: 5598: (define_expand "untyped_call" 5599: [(parallel [(call (match_operand 0 "" "") 5600: (const_int 0)) 5601: (match_operand 1 "" "") 5602: (match_operand 2 "" "")])] 5603: "" 5604: " 5605: { 5606: int i; 5607: 1.1.1.4 root 5608: emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); 1.1 root 5609: 5610: for (i = 0; i < XVECLEN (operands[2], 0); i++) 5611: { 5612: rtx set = XVECEXP (operands[2], 0, i); 5613: emit_move_insn (SET_DEST (set), SET_SRC (set)); 5614: } 5615: 5616: /* The optimizer does not know that the call sets the function value 5617: registers we stored in the result block. We avoid problems by 5618: claiming that all hard registers are used and clobbered at this 5619: point. */ 5620: emit_insn (gen_blockage ()); 5621: 5622: DONE; 5623: }") 5624: 5625: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 5626: ;; all of memory. This blocks insns from being moved across this point. 5627: 5628: (define_insn "blockage" 5629: [(unspec_volatile [(const_int 0)] 0)] 5630: "" 5631: "") 1.1.1.4 root 5632: 5633: ;; Synchronize instruction/data caches for V.4 trampolines 5634: (define_insn "sync_isync" 5635: [(unspec [(match_operand 0 "memory_operand" "=m")] 1)] 5636: "" 5637: "{dcs|sync}\;{ics|isync}" 5638: [(set_attr "length" "8")]) 5639: 1.1 root 5640: 5641: ;; Compare insns are next. Note that the RS/6000 has two types of compares, 1.1.1.4 root 5642: ;; signed & unsigned, and one type of branch. 1.1 root 5643: ;; 5644: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 5645: ;; insns, and branches. We store the operands of compares until we see 5646: ;; how it is used. 5647: (define_expand "cmpsi" 5648: [(set (cc0) 5649: (compare (match_operand:SI 0 "gpc_reg_operand" "") 5650: (match_operand:SI 1 "reg_or_short_operand" "")))] 5651: "" 5652: " 5653: { 5654: /* Take care of the possibility that operands[1] might be negative but 5655: this might be a logical operation. That insn doesn't exist. */ 5656: if (GET_CODE (operands[1]) == CONST_INT 5657: && INTVAL (operands[1]) < 0) 5658: operands[1] = force_reg (SImode, operands[1]); 5659: 5660: rs6000_compare_op0 = operands[0]; 5661: rs6000_compare_op1 = operands[1]; 5662: rs6000_compare_fp_p = 0; 5663: DONE; 5664: }") 5665: 5666: (define_expand "cmpsf" 5667: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") 5668: (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.4 root 5669: "TARGET_HARD_FLOAT" 1.1 root 5670: " 5671: { 5672: rs6000_compare_op0 = operands[0]; 5673: rs6000_compare_op1 = operands[1]; 5674: rs6000_compare_fp_p = 1; 5675: DONE; 5676: }") 5677: 5678: (define_expand "cmpdf" 5679: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") 5680: (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.4 root 5681: "TARGET_HARD_FLOAT" 1.1 root 5682: " 5683: { 5684: rs6000_compare_op0 = operands[0]; 5685: rs6000_compare_op1 = operands[1]; 5686: rs6000_compare_fp_p = 1; 5687: DONE; 5688: }") 5689: 5690: (define_expand "beq" 5691: [(set (match_dup 2) (match_dup 1)) 5692: (set (pc) 5693: (if_then_else (eq (match_dup 2) 5694: (const_int 0)) 5695: (label_ref (match_operand 0 "" "")) 5696: (pc)))] 5697: "" 5698: " 5699: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5700: operands[1] = gen_rtx (COMPARE, mode, 5701: rs6000_compare_op0, rs6000_compare_op1); 5702: operands[2] = gen_reg_rtx (mode); 5703: }") 5704: 5705: (define_expand "bne" 5706: [(set (match_dup 2) (match_dup 1)) 5707: (set (pc) 5708: (if_then_else (ne (match_dup 2) 5709: (const_int 0)) 5710: (label_ref (match_operand 0 "" "")) 5711: (pc)))] 5712: "" 5713: " 5714: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5715: operands[1] = gen_rtx (COMPARE, mode, 5716: rs6000_compare_op0, rs6000_compare_op1); 5717: operands[2] = gen_reg_rtx (mode); 5718: }") 5719: 5720: (define_expand "blt" 5721: [(set (match_dup 2) (match_dup 1)) 5722: (set (pc) 5723: (if_then_else (lt (match_dup 2) 5724: (const_int 0)) 5725: (label_ref (match_operand 0 "" "")) 5726: (pc)))] 5727: "" 5728: " 5729: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5730: operands[1] = gen_rtx (COMPARE, mode, 5731: rs6000_compare_op0, rs6000_compare_op1); 5732: operands[2] = gen_reg_rtx (mode); 5733: }") 5734: 5735: (define_expand "bgt" 5736: [(set (match_dup 2) (match_dup 1)) 5737: (set (pc) 5738: (if_then_else (gt (match_dup 2) 5739: (const_int 0)) 5740: (label_ref (match_operand 0 "" "")) 5741: (pc)))] 5742: "" 5743: " 5744: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5745: operands[1] = gen_rtx (COMPARE, mode, 5746: rs6000_compare_op0, rs6000_compare_op1); 5747: operands[2] = gen_reg_rtx (mode); 5748: }") 5749: 5750: (define_expand "ble" 5751: [(set (match_dup 2) (match_dup 1)) 5752: (set (pc) 5753: (if_then_else (le (match_dup 2) 5754: (const_int 0)) 5755: (label_ref (match_operand 0 "" "")) 5756: (pc)))] 5757: "" 5758: " 5759: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5760: operands[1] = gen_rtx (COMPARE, mode, 5761: rs6000_compare_op0, rs6000_compare_op1); 5762: operands[2] = gen_reg_rtx (mode); 5763: }") 5764: 5765: (define_expand "bge" 5766: [(set (match_dup 2) (match_dup 1)) 5767: (set (pc) 5768: (if_then_else (ge (match_dup 2) 5769: (const_int 0)) 5770: (label_ref (match_operand 0 "" "")) 5771: (pc)))] 5772: "" 5773: " 5774: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5775: operands[1] = gen_rtx (COMPARE, mode, 5776: rs6000_compare_op0, rs6000_compare_op1); 5777: operands[2] = gen_reg_rtx (mode); 5778: }") 5779: 5780: (define_expand "bgtu" 5781: [(set (match_dup 2) (match_dup 1)) 5782: (set (pc) 5783: (if_then_else (gtu (match_dup 2) 5784: (const_int 0)) 5785: (label_ref (match_operand 0 "" "")) 5786: (pc)))] 5787: "" 5788: " 5789: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5790: rs6000_compare_op0, rs6000_compare_op1); 5791: operands[2] = gen_reg_rtx (CCUNSmode); 5792: }") 5793: 5794: (define_expand "bltu" 5795: [(set (match_dup 2) (match_dup 1)) 5796: (set (pc) 5797: (if_then_else (ltu (match_dup 2) 5798: (const_int 0)) 5799: (label_ref (match_operand 0 "" "")) 5800: (pc)))] 5801: "" 5802: " 5803: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5804: rs6000_compare_op0, rs6000_compare_op1); 5805: operands[2] = gen_reg_rtx (CCUNSmode); 5806: }") 5807: 5808: (define_expand "bgeu" 5809: [(set (match_dup 2) (match_dup 1)) 5810: (set (pc) 5811: (if_then_else (geu (match_dup 2) 5812: (const_int 0)) 5813: (label_ref (match_operand 0 "" "")) 5814: (pc)))] 5815: "" 5816: " 5817: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5818: rs6000_compare_op0, rs6000_compare_op1); 5819: operands[2] = gen_reg_rtx (CCUNSmode); 5820: }") 5821: 5822: (define_expand "bleu" 5823: [(set (match_dup 2) (match_dup 1)) 5824: (set (pc) 5825: (if_then_else (leu (match_dup 2) 5826: (const_int 0)) 5827: (label_ref (match_operand 0 "" "")) 5828: (pc)))] 5829: "" 5830: " 5831: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5832: rs6000_compare_op0, rs6000_compare_op1); 5833: operands[2] = gen_reg_rtx (CCUNSmode); 5834: }") 5835: 5836: ;; For SNE, we would prefer that the xor/abs sequence be used for integers. 5837: ;; For SEQ, likewise, except that comparisons with zero should be done 5838: ;; with an scc insns. However, due to the order that combine see the 5839: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 5840: ;; the cases we don't want to handle. 5841: (define_expand "seq" 5842: [(set (match_dup 2) (match_dup 1)) 5843: (set (match_operand:SI 0 "gpc_reg_operand" "") 5844: (eq:SI (match_dup 2) (const_int 0)))] 5845: "" 5846: " 5847: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5848: operands[1] = gen_rtx (COMPARE, mode, 5849: rs6000_compare_op0, rs6000_compare_op1); 5850: operands[2] = gen_reg_rtx (mode); 5851: }") 5852: 5853: (define_expand "sne" 5854: [(set (match_dup 2) (match_dup 1)) 5855: (set (match_operand:SI 0 "gpc_reg_operand" "") 5856: (ne:SI (match_dup 2) (const_int 0)))] 5857: "" 5858: " 5859: { if (! rs6000_compare_fp_p) 5860: FAIL; 5861: 5862: operands[1] = gen_rtx (COMPARE, CCFPmode, 5863: rs6000_compare_op0, rs6000_compare_op1); 5864: operands[2] = gen_reg_rtx (CCFPmode); 5865: }") 5866: 5867: ;; A > 0 is best done using the portable sequence, so fail in that case. 5868: (define_expand "sgt" 5869: [(set (match_dup 2) (match_dup 1)) 5870: (set (match_operand:SI 0 "gpc_reg_operand" "") 5871: (gt:SI (match_dup 2) (const_int 0)))] 5872: "" 5873: " 5874: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5875: 5876: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5877: FAIL; 5878: 5879: operands[1] = gen_rtx (COMPARE, mode, 5880: rs6000_compare_op0, rs6000_compare_op1); 5881: operands[2] = gen_reg_rtx (mode); 5882: }") 5883: 5884: ;; A < 0 is best done in the portable way for A an integer. 5885: (define_expand "slt" 5886: [(set (match_dup 2) (match_dup 1)) 5887: (set (match_operand:SI 0 "gpc_reg_operand" "") 5888: (lt:SI (match_dup 2) (const_int 0)))] 5889: "" 5890: " 5891: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5892: 5893: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5894: FAIL; 5895: 5896: operands[1] = gen_rtx (COMPARE, mode, 5897: rs6000_compare_op0, rs6000_compare_op1); 5898: operands[2] = gen_reg_rtx (mode); 5899: }") 5900: 5901: (define_expand "sge" 5902: [(set (match_dup 2) (match_dup 1)) 5903: (set (match_operand:SI 0 "gpc_reg_operand" "") 5904: (ge:SI (match_dup 2) (const_int 0)))] 5905: "" 5906: " 5907: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5908: operands[1] = gen_rtx (COMPARE, mode, 5909: rs6000_compare_op0, rs6000_compare_op1); 5910: operands[2] = gen_reg_rtx (mode); 5911: }") 5912: 5913: ;; A <= 0 is best done the portable way for A an integer. 5914: (define_expand "sle" 5915: [(set (match_dup 2) (match_dup 1)) 5916: (set (match_operand:SI 0 "gpc_reg_operand" "") 5917: (le:SI (match_dup 2) (const_int 0)))] 5918: "" 5919: " 5920: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; 5921: 5922: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 5923: FAIL; 5924: 5925: operands[1] = gen_rtx (COMPARE, mode, 5926: rs6000_compare_op0, rs6000_compare_op1); 5927: operands[2] = gen_reg_rtx (mode); 5928: }") 5929: 5930: (define_expand "sgtu" 5931: [(set (match_dup 2) (match_dup 1)) 5932: (set (match_operand:SI 0 "gpc_reg_operand" "") 5933: (gtu:SI (match_dup 2) (const_int 0)))] 5934: "" 5935: " 5936: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5937: rs6000_compare_op0, rs6000_compare_op1); 5938: operands[2] = gen_reg_rtx (CCUNSmode); 5939: }") 5940: 5941: (define_expand "sltu" 5942: [(set (match_dup 2) (match_dup 1)) 5943: (set (match_operand:SI 0 "gpc_reg_operand" "") 5944: (ltu:SI (match_dup 2) (const_int 0)))] 5945: "" 5946: " 5947: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5948: rs6000_compare_op0, rs6000_compare_op1); 5949: operands[2] = gen_reg_rtx (CCUNSmode); 5950: }") 5951: 5952: (define_expand "sgeu" 5953: [(set (match_dup 2) (match_dup 1)) 5954: (set (match_operand:SI 0 "gpc_reg_operand" "") 5955: (geu:SI (match_dup 2) (const_int 0)))] 5956: "" 5957: " 5958: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5959: rs6000_compare_op0, rs6000_compare_op1); 5960: operands[2] = gen_reg_rtx (CCUNSmode); 5961: }") 5962: 5963: (define_expand "sleu" 5964: [(set (match_dup 2) (match_dup 1)) 5965: (set (match_operand:SI 0 "gpc_reg_operand" "") 5966: (leu:SI (match_dup 2) (const_int 0)))] 5967: "" 5968: " 5969: { operands[1] = gen_rtx (COMPARE, CCUNSmode, 5970: rs6000_compare_op0, rs6000_compare_op1); 5971: operands[2] = gen_reg_rtx (CCUNSmode); 5972: }") 5973: 5974: ;; Here are the actual compare insns. 5975: (define_insn "" 5976: [(set (match_operand:CC 0 "cc_reg_operand" "=y") 5977: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 5978: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 5979: "" 1.1.1.2 root 5980: "{cmp%I2|cmpw%I2} %0,%1,%2" 1.1 root 5981: [(set_attr "type" "compare")]) 5982: 5983: ;; If we are comparing a register for equality with a large constant, 5984: ;; we can do this with an XOR followed by a compare. But we need a scratch 5985: ;; register for the result of the XOR. 5986: 5987: (define_split 5988: [(set (match_operand:CC 0 "cc_reg_operand" "") 5989: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 5990: (match_operand:SI 2 "non_short_cint_operand" ""))) 5991: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 5992: "find_single_use (operands[0], insn, 0) 5993: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 5994: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 5995: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 5996: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 5997: " 5998: { 5999: /* Get the constant we are comparing against, C, and see what it looks like 6000: sign-extended to 16 bits. Then see what constant could be XOR'ed 6001: with C to get the sign-extended value. */ 6002: 6003: int c = INTVAL (operands[2]); 6004: int sextc = (c << 16) >> 16; 6005: int xorv = c ^ sextc; 6006: 6007: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); 6008: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); 6009: }") 6010: 6011: (define_insn "" 6012: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 6013: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 6014: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] 6015: "" 1.1.1.2 root 6016: "{cmpl%I2|cmplw%I2} %0,%1,%W2" 1.1 root 6017: [(set_attr "type" "compare")]) 6018: 6019: ;; The following two insns don't exist as single insns, but if we provide 6020: ;; them, we can swap an add and compare, which will enable us to overlap more 6021: ;; of the required delay between a compare and branch. We generate code for 6022: ;; them by splitting. 6023: 6024: (define_insn "" 6025: [(set (match_operand:CC 3 "cc_reg_operand" "=y") 6026: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 6027: (match_operand:SI 2 "short_cint_operand" "i"))) 6028: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6029: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 6030: "" 1.1.1.2 root 6031: "#" 6032: [(set_attr "length" "8")]) 1.1.1.4 root 6033: 1.1 root 6034: (define_insn "" 6035: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 6036: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 6037: (match_operand:SI 2 "u_short_cint_operand" "i"))) 6038: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6039: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 6040: "" 1.1.1.2 root 6041: "#" 6042: [(set_attr "length" "8")]) 1.1.1.4 root 6043: 1.1 root 6044: (define_split 6045: [(set (match_operand:CC 3 "cc_reg_operand" "") 6046: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 6047: (match_operand:SI 2 "short_cint_operand" ""))) 6048: (set (match_operand:SI 0 "gpc_reg_operand" "") 6049: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 6050: "" 6051: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 6052: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 6053: 6054: (define_split 6055: [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 6056: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 6057: (match_operand:SI 2 "u_short_cint_operand" ""))) 6058: (set (match_operand:SI 0 "gpc_reg_operand" "") 6059: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 6060: "" 6061: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 6062: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 6063: 6064: (define_insn "" 6065: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 6066: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 6067: (match_operand:SF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 6068: "TARGET_HARD_FLOAT" 1.1 root 6069: "fcmpu %0,%1,%2" 6070: [(set_attr "type" "fpcompare")]) 6071: 6072: (define_insn "" 6073: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 6074: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 6075: (match_operand:DF 2 "gpc_reg_operand" "f")))] 1.1.1.4 root 6076: "TARGET_HARD_FLOAT" 1.1 root 6077: "fcmpu %0,%1,%2" 6078: [(set_attr "type" "fpcompare")]) 6079: 6080: ;; Now we have the scc insns. We can do some combinations because of the 6081: ;; way the machine works. 6082: ;; 6083: ;; Note that this is probably faster if we can put an insn between the 6084: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 6085: ;; cases the insns below which don't use an intermediate CR field will 6086: ;; be used instead. 6087: (define_insn "" 6088: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6089: (match_operator:SI 1 "scc_comparison_operator" 6090: [(match_operand 2 "cc_reg_operand" "y") 6091: (const_int 0)]))] 6092: "" 1.1.1.2 root 6093: "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" 6094: [(set_attr "length" "12")]) 1.1 root 6095: 6096: (define_insn "" 6097: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6098: (compare:CC (match_operator:SI 1 "scc_comparison_operator" 6099: [(match_operand 2 "cc_reg_operand" "y") 6100: (const_int 0)]) 6101: (const_int 0))) 6102: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 6103: (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 6104: "" 1.1.1.2 root 6105: "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" 6106: [(set_attr "type" "delayed_compare") 6107: (set_attr "length" "12")]) 1.1 root 6108: 6109: (define_insn "" 6110: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6111: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 6112: [(match_operand 2 "cc_reg_operand" "y") 6113: (const_int 0)]) 6114: (match_operand:SI 3 "const_int_operand" "n")))] 6115: "" 6116: "* 6117: { 6118: int is_bit = ccr_bit (operands[1], 1); 6119: int put_bit = 31 - (INTVAL (operands[3]) & 31); 6120: int count; 6121: 6122: if (is_bit >= put_bit) 6123: count = is_bit - put_bit; 6124: else 6125: count = 32 - (put_bit - is_bit); 6126: 6127: operands[4] = gen_rtx (CONST_INT, VOIDmode, count); 6128: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); 6129: 1.1.1.2 root 6130: return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 6131: }" 6132: [(set_attr "length" "12")]) 1.1 root 6133: 6134: (define_insn "" 6135: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6136: (compare:CC 6137: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 6138: [(match_operand 2 "cc_reg_operand" "y") 6139: (const_int 0)]) 6140: (match_operand:SI 3 "const_int_operand" "n")) 6141: (const_int 0))) 6142: (set (match_operand:SI 4 "gpc_reg_operand" "=r") 6143: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 6144: (match_dup 3)))] 6145: "" 6146: "* 6147: { 6148: int is_bit = ccr_bit (operands[1], 1); 6149: int put_bit = 31 - (INTVAL (operands[3]) & 31); 6150: int count; 6151: 6152: if (is_bit >= put_bit) 6153: count = is_bit - put_bit; 6154: else 6155: count = 32 - (put_bit - is_bit); 6156: 6157: operands[5] = gen_rtx (CONST_INT, VOIDmode, count); 6158: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); 6159: 1.1.1.2 root 6160: return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 1.1 root 6161: }" 1.1.1.2 root 6162: [(set_attr "type" "delayed_compare") 6163: (set_attr "length" "12")]) 1.1 root 6164: 6165: ;; If we are comparing the result of two comparisons, this can be done 6166: ;; using creqv or crxor. 6167: 6168: (define_insn "" 6169: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 6170: (compare:CCEQ (match_operator 1 "scc_comparison_operator" 6171: [(match_operand 2 "cc_reg_operand" "y") 6172: (const_int 0)]) 6173: (match_operator 3 "scc_comparison_operator" 6174: [(match_operand 4 "cc_reg_operand" "y") 6175: (const_int 0)])))] 6176: "REGNO (operands[2]) != REGNO (operands[4])" 6177: "* 6178: { 6179: enum rtx_code code1, code2; 6180: 6181: code1 = GET_CODE (operands[1]); 6182: code2 = GET_CODE (operands[3]); 6183: 6184: if ((code1 == EQ || code1 == LT || code1 == GT 6185: || code1 == LTU || code1 == GTU 6186: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) 6187: != 6188: (code2 == EQ || code2 == LT || code2 == GT 6189: || code2 == LTU || code2 == GTU 6190: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) 6191: return \"%C1%C3crxor %E0,%j1,%j3\"; 6192: else 6193: return \"%C1%C3creqv %E0,%j1,%j3\"; 1.1.1.2 root 6194: }" 6195: [(set_attr "length" "12")]) 1.1 root 6196: 6197: ;; There is a 3 cycle delay between consecutive mfcr instructions 6198: ;; so it is useful to combine 2 scc instructions to use only one mfcr. 6199: 6200: (define_peephole 6201: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6202: (match_operator:SI 1 "scc_comparison_operator" 6203: [(match_operand 2 "cc_reg_operand" "y") 6204: (const_int 0)])) 6205: (set (match_operand:SI 3 "gpc_reg_operand" "=r") 6206: (match_operator:SI 4 "scc_comparison_operator" 6207: [(match_operand 5 "cc_reg_operand" "y") 6208: (const_int 0)]))] 6209: "REGNO (operands[2]) != REGNO (operands[5])" 1.1.1.2 root 6210: "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 6211: [(set_attr "length" "20")]) 1.1 root 6212: 6213: ;; There are some scc insns that can be done directly, without a compare. 6214: ;; These are faster because they don't involve the communications between 6215: ;; the FXU and branch units. In fact, we will be replacing all of the 6216: ;; integer scc insns here or in the portable methods in emit_store_flag. 6217: ;; 6218: ;; Also support (neg (scc ..)) since that construct is used to replace 6219: ;; branches, (plus (scc ..) ..) since that construct is common and 6220: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 6221: ;; cases where it is no more expensive than (neg (scc ..)). 6222: 6223: ;; Have reload force a constant into a register for the simple insns that 6224: ;; otherwise won't accept constants. We do this because it is faster than 6225: ;; the cmp/mfcr sequence we would otherwise generate. 6226: 6227: (define_insn "" 6228: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6229: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6230: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) 6231: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 6232: "" 6233: "@ 1.1.1.2 root 6234: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6235: {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 6236: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6237: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 6238: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 6239: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6240: 6241: (define_insn "" 6242: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 root 6243: (compare:CC 1.1 root 6244: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6245: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6246: (const_int 0))) 6247: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6248: (eq:SI (match_dup 1) (match_dup 2))) 6249: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 6250: "" 6251: "@ 1.1.1.2 root 6252: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6253: {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 6254: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6255: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 6256: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" 6257: [(set_attr "type" "compare") 6258: (set_attr "length" "12,8,12,12,12")]) 6259: 6260: ;; We have insns of the form shown by the first define_insn below. If 6261: ;; there is something inside the comparison operation, we must split it. 6262: (define_split 6263: [(set (match_operand:SI 0 "gpc_reg_operand" "") 6264: (plus:SI (match_operator 1 "comparison_operator" 6265: [(match_operand:SI 2 "" "") 6266: (match_operand:SI 3 6267: "reg_or_cint_operand" "")]) 6268: (match_operand:SI 4 "gpc_reg_operand" ""))) 6269: (clobber (match_operand:SI 5 "register_operand" ""))] 6270: "! gpc_reg_operand (operands[2], SImode)" 6271: [(set (match_dup 5) (match_dup 2)) 6272: (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 6273: (match_dup 4)))]) 1.1 root 6274: 6275: (define_insn "" 6276: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6277: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6278: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6279: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) 6280: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6281: "" 6282: "@ 1.1.1.2 root 6283: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6284: {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 6285: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6286: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6287: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 6288: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6289: 6290: (define_insn "" 6291: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 root 6292: (compare:CC 1.1 root 6293: (plus:SI 6294: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6295: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6296: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 6297: (const_int 0))) 6298: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6299: "" 6300: "@ 1.1.1.2 root 6301: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6302: {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 6303: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6304: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6305: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 6306: [(set_attr "type" "compare") 6307: (set_attr "length" "12,8,12,12,12")]) 1.1 root 6308: 6309: (define_insn "" 6310: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") 1.1.1.4 root 6311: (compare:CC 1.1 root 6312: (plus:SI 6313: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 6314: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) 6315: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) 6316: (const_int 0))) 6317: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 6318: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6319: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] 6320: "" 6321: "@ 1.1.1.2 root 6322: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6323: {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 6324: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6325: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6326: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 6327: [(set_attr "type" "compare") 6328: (set_attr "length" "12,8,12,12,12")]) 1.1 root 6329: 6330: (define_insn "" 6331: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 1.1.1.3 root 6332: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 1.1 root 6333: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] 6334: "" 6335: "@ 1.1.1.2 root 6336: xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6337: {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 6338: {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6339: {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6340: {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 6341: [(set_attr "length" "12,8,12,12,12")]) 1.1 root 6342: 1.1.1.4 root 6343: ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, 6344: ;; since it nabs/sr is just as fast. 6345: (define_insn "" 6346: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6347: (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6348: (const_int 31))) 6349: (clobber (match_scratch:SI 2 "=&r"))] 6350: "!TARGET_POWER" 6351: "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" 6352: [(set_attr "length" "8")]) 6353: 1.1 root 6354: ;; This is what (plus (ne X (const_int 0)) Y) looks like. 6355: (define_insn "" 6356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6357: (plus:SI (lshiftrt:SI 6358: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6359: (const_int 31)) 6360: (match_operand:SI 2 "gpc_reg_operand" "r"))) 6361: (clobber (match_scratch:SI 3 "=&r"))] 6362: "" 1.1.1.2 root 6363: "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 6364: [(set_attr "length" "8")]) 1.1 root 6365: 6366: (define_insn "" 6367: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6368: (compare:CC 6369: (plus:SI (lshiftrt:SI 6370: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6371: (const_int 31)) 6372: (match_operand:SI 2 "gpc_reg_operand" "r")) 6373: (const_int 0))) 6374: (clobber (match_scratch:SI 3 "=&r"))] 6375: "" 1.1.1.2 root 6376: "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" 6377: [(set_attr "type" "compare") 6378: (set_attr "length" "8")]) 1.1 root 6379: 6380: (define_insn "" 6381: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6382: (compare:CC 6383: (plus:SI (lshiftrt:SI 6384: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 6385: (const_int 31)) 6386: (match_operand:SI 2 "gpc_reg_operand" "r")) 6387: (const_int 0))) 6388: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6389: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 6390: (match_dup 2))) 6391: (clobber (match_scratch:SI 3 "=&r"))] 6392: "" 1.1.1.2 root 6393: "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" 6394: [(set_attr "type" "compare") 6395: (set_attr "length" "8")]) 1.1 root 6396: 6397: (define_insn "" 6398: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6399: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6400: (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 6401: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 6402: "TARGET_POWER" 1.1 root 6403: "@ 1.1.1.2 root 6404: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 6405: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 6406: [(set_attr "length" "12")]) 1.1 root 6407: 6408: (define_insn "" 6409: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") 6410: (compare:CC 6411: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6412: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6413: (const_int 0))) 6414: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6415: (le:SI (match_dup 1) (match_dup 2))) 6416: (clobber (match_scratch:SI 3 "=r,X"))] 1.1.1.2 root 6417: "TARGET_POWER" 1.1 root 6418: "@ 1.1.1.2 root 6419: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 6420: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" 1.1.1.3 root 6421: [(set_attr "type" "compare,delayed_compare") 1.1.1.2 root 6422: (set_attr "length" "12")]) 1.1 root 6423: 6424: (define_insn "" 6425: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6426: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6427: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6428: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6429: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6430: "TARGET_POWER" 1.1 root 6431: "@ 1.1.1.2 root 6432: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 6433: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" 6434: [(set_attr "length" "12")]) 1.1 root 6435: 6436: (define_insn "" 6437: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6438: (compare:CC 6439: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6440: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6441: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6442: (const_int 0))) 6443: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6444: "TARGET_POWER" 1.1 root 6445: "@ 1.1.1.2 root 6446: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 6447: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" 6448: [(set_attr "type" "compare") 6449: (set_attr "length" "12")]) 1.1 root 6450: 6451: (define_insn "" 6452: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6453: (compare:CC 6454: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6455: (match_operand:SI 2 "reg_or_short_operand" "r,O")) 6456: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6457: (const_int 0))) 6458: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6459: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6460: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1.1.2 root 6461: "TARGET_POWER" 1.1 root 6462: "@ 1.1.1.2 root 6463: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 6464: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" 6465: [(set_attr "type" "compare") 6466: (set_attr "length" "12")]) 1.1 root 6467: 6468: (define_insn "" 6469: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6470: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6471: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 1.1.1.2 root 6472: "TARGET_POWER" 1.1 root 6473: "@ 1.1.1.2 root 6474: doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 6475: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 6476: [(set_attr "length" "12")]) 1.1 root 6477: 6478: (define_insn "" 6479: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6480: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6481: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 6482: "" 1.1.1.2 root 6483: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 6484: [(set_attr "length" "12")]) 1.1 root 6485: 6486: (define_insn "" 6487: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 6488: (compare:CC 6489: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6490: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6491: (const_int 0))) 6492: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6493: (leu:SI (match_dup 1) (match_dup 2)))] 6494: "" 1.1.1.2 root 6495: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 6496: [(set_attr "type" "compare") 6497: (set_attr "length" "12")]) 1.1 root 6498: 6499: (define_insn "" 6500: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6501: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6502: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6503: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6504: (clobber (match_scratch:SI 4 "=&r"))] 6505: "" 1.1.1.2 root 6506: "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" 6507: [(set_attr "length" "8")]) 1.1 root 6508: 6509: (define_insn "" 6510: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6511: (compare:CC 6512: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6513: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6514: (match_operand:SI 3 "gpc_reg_operand" "r")) 6515: (const_int 0))) 6516: (clobber (match_scratch:SI 4 "=&r"))] 6517: "" 1.1.1.2 root 6518: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" 6519: [(set_attr "type" "compare") 6520: (set_attr "length" "8")]) 1.1 root 6521: 6522: (define_insn "" 6523: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6524: (compare:CC 6525: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6526: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6527: (match_operand:SI 3 "gpc_reg_operand" "r")) 6528: (const_int 0))) 6529: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6530: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6531: (clobber (match_scratch:SI 4 "=&r"))] 6532: "" 1.1.1.2 root 6533: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" 6534: [(set_attr "type" "compare") 6535: (set_attr "length" "8")]) 1.1 root 6536: 6537: (define_insn "" 6538: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6539: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6540: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 6541: "" 1.1.1.2 root 6542: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 6543: [(set_attr "length" "12")]) 1.1 root 6544: 6545: (define_insn "" 6546: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6547: (and:SI (neg:SI 6548: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6549: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6550: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6551: (clobber (match_scratch:SI 4 "=&r"))] 6552: "" 1.1.1.2 root 6553: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 6554: [(set_attr "length" "12")]) 1.1 root 6555: 6556: (define_insn "" 6557: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6558: (compare:CC 6559: (and:SI (neg:SI 6560: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6561: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6562: (match_operand:SI 3 "gpc_reg_operand" "r")) 6563: (const_int 0))) 6564: (clobber (match_scratch:SI 4 "=&r"))] 6565: "" 1.1.1.2 root 6566: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 6567: [(set_attr "type" "compare") 6568: (set_attr "length" "12")]) 1.1 root 6569: 6570: (define_insn "" 6571: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6572: (compare:CC 6573: (and:SI (neg:SI 6574: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6575: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6576: (match_operand:SI 3 "gpc_reg_operand" "r")) 6577: (const_int 0))) 6578: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6579: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 6580: (clobber (match_scratch:SI 4 "=&r"))] 6581: "" 1.1.1.2 root 6582: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 6583: [(set_attr "type" "compare") 6584: (set_attr "length" "12")]) 1.1 root 6585: 6586: (define_insn "" 6587: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6588: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6589: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 1.1.1.2 root 6590: "TARGET_POWER" 6591: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 6592: [(set_attr "length" "12")]) 1.1 root 6593: 6594: (define_insn "" 1.1.1.3 root 6595: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1.1 root 6596: (compare:CC 6597: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6598: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6599: (const_int 0))) 6600: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6601: (lt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 6602: "TARGET_POWER" 6603: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 6604: [(set_attr "type" "delayed_compare") 6605: (set_attr "length" "12")]) 1.1 root 6606: 6607: (define_insn "" 6608: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6609: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6610: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6611: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6612: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6613: "TARGET_POWER" 6614: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 6615: [(set_attr "length" "12")]) 1.1 root 6616: 6617: (define_insn "" 1.1.1.3 root 6618: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 1.1 root 6619: (compare:CC 6620: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6621: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6622: (match_operand:SI 3 "gpc_reg_operand" "r")) 6623: (const_int 0))) 6624: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6625: "TARGET_POWER" 6626: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 6627: [(set_attr "type" "compare") 6628: (set_attr "length" "12")]) 1.1 root 6629: 6630: (define_insn "" 1.1.1.3 root 6631: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 1.1 root 6632: (compare:CC 6633: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6634: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6635: (match_operand:SI 3 "gpc_reg_operand" "r")) 6636: (const_int 0))) 6637: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6638: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6639: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6640: "TARGET_POWER" 6641: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 6642: [(set_attr "type" "compare") 6643: (set_attr "length" "12")]) 1.1 root 6644: 6645: (define_insn "" 6646: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6647: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6648: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 6649: "TARGET_POWER" 6650: "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 6651: [(set_attr "length" "12")]) 1.1 root 6652: 6653: (define_insn "" 6654: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6655: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6656: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 6657: "" 6658: "@ 1.1.1.2 root 6659: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 6660: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 6661: [(set_attr "length" "12")]) 1.1 root 6662: 6663: (define_insn "" 6664: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 6665: (compare:CC 6666: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6667: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6668: (const_int 0))) 6669: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6670: (ltu:SI (match_dup 1) (match_dup 2)))] 6671: "" 6672: "@ 1.1.1.2 root 6673: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 6674: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 6675: [(set_attr "type" "compare") 6676: (set_attr "length" "12")]) 1.1 root 6677: 6678: (define_insn "" 6679: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 6680: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 6681: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) 6682: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) 6683: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] 6684: "" 6685: "@ 1.1.1.2 root 6686: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6687: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6688: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 6689: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 6690: [(set_attr "length" "12")]) 1.1 root 6691: 6692: (define_insn "" 1.1.1.2 root 6693: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 6694: (compare:CC 1.1.1.2 root 6695: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6696: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6697: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6698: (const_int 0))) 1.1.1.2 root 6699: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6700: "" 6701: "@ 1.1.1.2 root 6702: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 6703: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" 6704: [(set_attr "type" "compare") 6705: (set_attr "length" "12")]) 1.1 root 6706: 6707: (define_insn "" 1.1.1.2 root 6708: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 6709: (compare:CC 1.1.1.2 root 6710: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6711: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6712: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 6713: (const_int 0))) 1.1.1.2 root 6714: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 6715: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 6716: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 6717: "" 6718: "@ 1.1.1.2 root 6719: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 6720: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 6721: [(set_attr "type" "compare") 6722: (set_attr "length" "12")]) 1.1 root 6723: 6724: (define_insn "" 6725: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6726: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6727: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] 6728: "" 6729: "@ 1.1.1.2 root 6730: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 6731: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 6732: [(set_attr "length" "8")]) 1.1 root 6733: 6734: (define_insn "" 6735: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6736: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6737: (match_operand:SI 2 "reg_or_short_operand" "rI"))) 6738: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 6739: "TARGET_POWER" 6740: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 6741: [(set_attr "length" "12")]) 1.1 root 6742: 6743: (define_insn "" 6744: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6745: (compare:CC 6746: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6747: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6748: (const_int 0))) 6749: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6750: (ge:SI (match_dup 1) (match_dup 2))) 6751: (clobber (match_scratch:SI 3 "=r"))] 1.1.1.2 root 6752: "TARGET_POWER" 6753: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" 6754: [(set_attr "type" "compare") 6755: (set_attr "length" "12")]) 1.1 root 6756: 6757: (define_insn "" 6758: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6759: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6760: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6761: (match_operand:SI 3 "gpc_reg_operand" "r"))) 6762: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6763: "TARGET_POWER" 6764: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" 6765: [(set_attr "length" "12")]) 1.1 root 6766: 6767: (define_insn "" 6768: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6769: (compare:CC 6770: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6771: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6772: (match_operand:SI 3 "gpc_reg_operand" "r")) 6773: (const_int 0))) 6774: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6775: "TARGET_POWER" 6776: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" 6777: [(set_attr "type" "compare") 6778: (set_attr "length" "12")]) 1.1 root 6779: 6780: (define_insn "" 6781: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 6782: (compare:CC 6783: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6784: (match_operand:SI 2 "reg_or_short_operand" "rI")) 6785: (match_operand:SI 3 "gpc_reg_operand" "r")) 6786: (const_int 0))) 6787: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6788: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6789: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 6790: "TARGET_POWER" 6791: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" 6792: [(set_attr "type" "compare") 6793: (set_attr "length" "12")]) 1.1 root 6794: 6795: (define_insn "" 6796: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6797: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6798: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 1.1.1.2 root 6799: "TARGET_POWER" 6800: "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 6801: [(set_attr "length" "12")]) 1.1 root 6802: 6803: ;; This is (and (neg (ge X (const_int 0))) Y). 6804: (define_insn "" 6805: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6806: (and:SI (neg:SI 6807: (lshiftrt:SI 6808: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6809: (const_int 31))) 6810: (match_operand:SI 2 "gpc_reg_operand" "r"))) 6811: (clobber (match_scratch:SI 3 "=&r"))] 6812: "" 1.1.1.2 root 6813: "{srai|srawi} %3,%1,31\;andc %0,%2,%3" 6814: [(set_attr "length" "8")]) 1.1 root 6815: 6816: (define_insn "" 6817: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 6818: (compare:CC 6819: (and:SI (neg:SI 6820: (lshiftrt:SI 6821: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6822: (const_int 31))) 6823: (match_operand:SI 2 "gpc_reg_operand" "r")) 6824: (const_int 0))) 6825: (clobber (match_scratch:SI 3 "=&r"))] 6826: "" 1.1.1.2 root 6827: "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" 6828: [(set_attr "type" "compare") 6829: (set_attr "length" "8")]) 1.1 root 6830: 6831: (define_insn "" 6832: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 6833: (compare:CC 6834: (and:SI (neg:SI 6835: (lshiftrt:SI 6836: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 6837: (const_int 31))) 6838: (match_operand:SI 2 "gpc_reg_operand" "r")) 6839: (const_int 0))) 6840: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6841: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) 6842: (const_int 31))) 6843: (match_dup 2))) 6844: (clobber (match_scratch:SI 3 "=&r"))] 6845: "" 1.1.1.2 root 6846: "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" 6847: [(set_attr "type" "compare") 6848: (set_attr "length" "8")]) 1.1 root 6849: 6850: (define_insn "" 6851: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6852: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6853: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 6854: "" 6855: "@ 1.1.1.2 root 6856: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 6857: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 6858: [(set_attr "length" "12")]) 1.1 root 6859: 6860: (define_insn "" 6861: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") 6862: (compare:CC 6863: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6864: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6865: (const_int 0))) 6866: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6867: (geu:SI (match_dup 1) (match_dup 2)))] 6868: "" 6869: "@ 1.1.1.2 root 6870: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 6871: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" 6872: [(set_attr "type" "compare") 6873: (set_attr "length" "12")]) 1.1 root 6874: 6875: (define_insn "" 6876: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6877: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6878: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6879: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6880: (clobber (match_scratch:SI 4 "=&r,&r"))] 6881: "" 6882: "@ 1.1.1.2 root 6883: {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 6884: {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" 6885: [(set_attr "length" "8")]) 1.1 root 6886: 6887: (define_insn "" 6888: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6889: (compare:CC 6890: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6891: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6892: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6893: (const_int 0))) 6894: (clobber (match_scratch:SI 4 "=&r,&r"))] 6895: "" 6896: "@ 1.1.1.2 root 6897: {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 6898: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 6899: [(set_attr "type" "compare") 6900: (set_attr "length" "8")]) 1.1 root 6901: 6902: (define_insn "" 6903: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6904: (compare:CC 6905: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6906: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 6907: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6908: (const_int 0))) 6909: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6910: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 6911: (clobber (match_scratch:SI 4 "=&r,&r"))] 6912: "" 6913: "@ 1.1.1.2 root 6914: {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 6915: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" 6916: [(set_attr "type" "compare") 6917: (set_attr "length" "8")]) 1.1 root 6918: 6919: (define_insn "" 6920: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6921: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6922: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] 6923: "" 6924: "@ 1.1.1.2 root 6925: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 6926: {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0" 6927: [(set_attr "length" "12")]) 1.1 root 6928: 6929: (define_insn "" 6930: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6931: (and:SI (neg:SI 6932: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6933: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6934: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 6935: (clobber (match_scratch:SI 4 "=&r,&r"))] 6936: "" 6937: "@ 1.1.1.2 root 6938: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 6939: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" 6940: [(set_attr "length" "12")]) 1.1 root 6941: 6942: (define_insn "" 6943: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 6944: (compare:CC 6945: (and:SI (neg:SI 6946: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6947: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6948: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6949: (const_int 0))) 6950: (clobber (match_scratch:SI 4 "=&r,&r"))] 6951: "" 6952: "@ 1.1.1.2 root 6953: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 6954: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" 6955: [(set_attr "type" "compare") 6956: (set_attr "length" "12")]) 1.1 root 6957: 6958: (define_insn "" 6959: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 6960: (compare:CC 6961: (and:SI (neg:SI 6962: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 6963: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 6964: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 6965: (const_int 0))) 6966: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 6967: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 6968: (clobber (match_scratch:SI 4 "=&r,&r"))] 6969: "" 6970: "@ 1.1.1.2 root 6971: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 6972: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" 6973: [(set_attr "type" "compare") 6974: (set_attr "length" "12")]) 1.1 root 6975: 6976: (define_insn "" 6977: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6978: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6979: (const_int 0)))] 6980: "" 1.1.1.2 root 6981: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" 6982: [(set_attr "length" "12")]) 1.1 root 6983: 6984: (define_insn "" 6985: [(set (match_operand:CC 2 "cc_reg_operand" "=x") 6986: (compare:CC 6987: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 6988: (const_int 0)) 6989: (const_int 0))) 6990: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 6991: (gt:SI (match_dup 1) (const_int 0)))] 6992: "" 1.1.1.2 root 6993: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" 6994: [(set_attr "type" "delayed_compare") 6995: (set_attr "length" "12")]) 1.1 root 6996: 6997: (define_insn "" 6998: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6999: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7000: (match_operand:SI 2 "reg_or_short_operand" "r")))] 1.1.1.2 root 7001: "TARGET_POWER" 7002: "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 7003: [(set_attr "length" "12")]) 1.1 root 7004: 7005: (define_insn "" 7006: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 7007: (compare:CC 7008: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7009: (match_operand:SI 2 "reg_or_short_operand" "r")) 7010: (const_int 0))) 7011: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7012: (gt:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 7013: "TARGET_POWER" 7014: "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" 7015: [(set_attr "type" "delayed_compare") 7016: (set_attr "length" "12")]) 1.1 root 7017: 7018: (define_insn "" 7019: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7020: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7021: (const_int 0)) 7022: (match_operand:SI 2 "gpc_reg_operand" "r"))) 7023: (clobber (match_scratch:SI 3 "=&r"))] 7024: "" 1.1.1.2 root 7025: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" 7026: [(set_attr "length" "12")]) 1.1 root 7027: 7028: (define_insn "" 7029: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 7030: (compare:CC 7031: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7032: (const_int 0)) 7033: (match_operand:SI 2 "gpc_reg_operand" "r")) 7034: (const_int 0))) 7035: (clobber (match_scratch:SI 3 "=&r"))] 7036: "" 1.1.1.2 root 7037: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" 7038: [(set_attr "type" "compare") 7039: (set_attr "length" "12")]) 1.1 root 7040: 7041: (define_insn "" 7042: [(set (match_operand:CC 4 "cc_reg_operand" "=x") 7043: (compare:CC 7044: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7045: (const_int 0)) 7046: (match_operand:SI 2 "gpc_reg_operand" "r")) 7047: (const_int 0))) 7048: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7049: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 7050: (clobber (match_scratch:SI 3 "=&r"))] 7051: "" 1.1.1.2 root 7052: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" 7053: [(set_attr "type" "compare") 7054: (set_attr "length" "12")]) 1.1 root 7055: 7056: (define_insn "" 7057: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7058: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7059: (match_operand:SI 2 "reg_or_short_operand" "r")) 7060: (match_operand:SI 3 "gpc_reg_operand" "r"))) 7061: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7062: "TARGET_POWER" 7063: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" 7064: [(set_attr "length" "12")]) 1.1 root 7065: 7066: (define_insn "" 7067: [(set (match_operand:CC 0 "cc_reg_operand" "=x") 7068: (compare:CC 7069: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7070: (match_operand:SI 2 "reg_or_short_operand" "r")) 7071: (match_operand:SI 3 "gpc_reg_operand" "r")) 7072: (const_int 0))) 7073: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7074: "TARGET_POWER" 7075: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" 7076: [(set_attr "type" "compare") 7077: (set_attr "length" "12")]) 1.1 root 7078: 7079: (define_insn "" 7080: [(set (match_operand:CC 5 "cc_reg_operand" "=x") 7081: (compare:CC 7082: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7083: (match_operand:SI 2 "reg_or_short_operand" "r")) 7084: (match_operand:SI 3 "gpc_reg_operand" "r")) 7085: (const_int 0))) 7086: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7087: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 7088: (clobber (match_scratch:SI 4 "=&r"))] 1.1.1.2 root 7089: "TARGET_POWER" 7090: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" 7091: [(set_attr "type" "compare") 7092: (set_attr "length" "12")]) 1.1 root 7093: 7094: (define_insn "" 7095: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7096: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7097: (const_int 0))))] 7098: "" 1.1.1.2 root 7099: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" 7100: [(set_attr "length" "12")]) 1.1 root 7101: 7102: (define_insn "" 7103: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7104: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7105: (match_operand:SI 2 "reg_or_short_operand" "r"))))] 1.1.1.2 root 7106: "TARGET_POWER" 7107: "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 7108: [(set_attr "length" "12")]) 1.1 root 7109: 7110: (define_insn "" 7111: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7112: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7113: (match_operand:SI 2 "reg_or_short_operand" "rI")))] 7114: "" 1.1.1.2 root 7115: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 7116: [(set_attr "length" "12")]) 1.1 root 7117: 7118: (define_insn "" 7119: [(set (match_operand:CC 3 "cc_reg_operand" "=x") 7120: (compare:CC 7121: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7122: (match_operand:SI 2 "reg_or_short_operand" "rI")) 7123: (const_int 0))) 7124: (set (match_operand:SI 0 "gpc_reg_operand" "=r") 7125: (gtu:SI (match_dup 1) (match_dup 2)))] 7126: "" 1.1.1.2 root 7127: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" 7128: [(set_attr "type" "compare") 7129: (set_attr "length" "12")]) 1.1 root 7130: 7131: (define_insn "" 7132: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 7133: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 7134: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) 7135: (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) 7136: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] 7137: "" 7138: "@ 1.1.1.2 root 7139: {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 7140: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 7141: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" 7142: [(set_attr "length" "8,12,12")]) 1.1 root 7143: 7144: (define_insn "" 1.1.1.2 root 7145: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") 1.1 root 7146: (compare:CC 1.1.1.2 root 7147: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 7148: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 7149: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 7150: (const_int 0))) 1.1.1.2 root 7151: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 7152: "" 7153: "@ 1.1.1.2 root 7154: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 7155: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 7156: [(set_attr "type" "compare") 7157: (set_attr "length" "8,12")]) 1.1 root 7158: 7159: (define_insn "" 1.1.1.2 root 7160: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") 1.1 root 7161: (compare:CC 1.1.1.2 root 7162: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 7163: (match_operand:SI 2 "reg_or_short_operand" "I,r")) 7164: (match_operand:SI 3 "gpc_reg_operand" "r,r")) 1.1 root 7165: (const_int 0))) 1.1.1.2 root 7166: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 7167: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 1.1.1.2 root 7168: (clobber (match_scratch:SI 4 "=&r,&r"))] 1.1 root 7169: "" 7170: "@ 1.1.1.2 root 7171: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 7172: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" 7173: [(set_attr "type" "compare") 7174: (set_attr "length" "8,12")]) 1.1 root 7175: 7176: (define_insn "" 7177: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7178: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 7179: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 7180: "" 1.1.1.2 root 7181: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 7182: [(set_attr "length" "8")]) 1.1 root 7183: 7184: ;; Define both directions of branch and return. If we need a reload 7185: ;; register, we'd rather use CR0 since it is much easier to copy a 7186: ;; register CC value to there. 7187: 7188: (define_insn "" 7189: [(set (pc) 7190: (if_then_else (match_operator 1 "branch_comparison_operator" 7191: [(match_operand 2 7192: "cc_reg_operand" "x,?y") 7193: (const_int 0)]) 7194: (label_ref (match_operand 0 "" "")) 7195: (pc)))] 7196: "" 1.1.1.2 root 7197: "* 7198: { 7199: if (get_attr_length (insn) == 8) 7200: return \"%C1bc %t1,%j1,%l0\"; 7201: else 7202: return \"%C1bc %T1,%j1,$+8\;b %l0\"; 7203: }" 7204: [(set_attr "type" "branch")]) 7205: 1.1 root 7206: (define_insn "" 7207: [(set (pc) 7208: (if_then_else (match_operator 0 "branch_comparison_operator" 7209: [(match_operand 1 7210: "cc_reg_operand" "x,?y") 7211: (const_int 0)]) 7212: (return) 7213: (pc)))] 7214: "direct_return ()" 1.1.1.2 root 7215: "{%C0bcr|%C0bclr} %t0,%j0" 7216: [(set_attr "length" "8")]) 1.1 root 7217: 7218: (define_insn "" 7219: [(set (pc) 7220: (if_then_else (match_operator 1 "branch_comparison_operator" 7221: [(match_operand 2 7222: "cc_reg_operand" "x,?y") 7223: (const_int 0)]) 7224: (pc) 7225: (label_ref (match_operand 0 "" ""))))] 7226: "" 1.1.1.2 root 7227: "* 7228: { 7229: if (get_attr_length (insn) == 8) 7230: return \"%C1bc %T1,%j1,%l0\"; 7231: else 7232: return \"%C1bc %t1,%j1,$+8\;b %l0\"; 7233: }" 7234: [(set_attr "type" "branch")]) 1.1 root 7235: 7236: (define_insn "" 7237: [(set (pc) 7238: (if_then_else (match_operator 0 "branch_comparison_operator" 7239: [(match_operand 1 7240: "cc_reg_operand" "x,?y") 7241: (const_int 0)]) 7242: (pc) 7243: (return)))] 7244: "direct_return ()" 1.1.1.2 root 7245: "{%C0bcr|%C0bclr} %T0,%j0" 7246: [(set_attr "length" "8")]) 1.1 root 7247: 7248: ;; Unconditional branch and return. 7249: 7250: (define_insn "jump" 7251: [(set (pc) 7252: (label_ref (match_operand 0 "" "")))] 7253: "" 7254: "b %l0") 7255: 7256: (define_insn "return" 7257: [(return)] 7258: "direct_return ()" 1.1.1.3 root 7259: "{br|blr}" 7260: [(set_attr "type" "jmpreg")]) 1.1 root 7261: 7262: (define_insn "indirect_jump" 7263: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] 7264: "" 7265: "@ 7266: bctr 1.1.1.3 root 7267: {br|blr}" 7268: [(set_attr "type" "jmpreg")]) 1.1 root 7269: 7270: ;; Table jump for switch statements: 7271: (define_expand "tablejump" 7272: [(set (match_dup 3) 7273: (plus:SI (match_operand:SI 0 "" "") 7274: (match_dup 2))) 7275: (parallel [(set (pc) (match_dup 3)) 7276: (use (label_ref (match_operand 1 "" "")))])] 7277: "" 7278: " 7279: { operands[0] = force_reg (SImode, operands[0]); 7280: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); 7281: operands[3] = gen_reg_rtx (SImode); 7282: }") 7283: 7284: (define_insn "" 7285: [(set (pc) 7286: (match_operand:SI 0 "register_operand" "c,l")) 7287: (use (label_ref (match_operand 1 "" "")))] 7288: "" 7289: "@ 7290: bctr 1.1.1.4 root 7291: {br|blr}" 7292: [(set_attr "type" "jmpreg")]) 1.1 root 7293: 7294: (define_insn "nop" 7295: [(const_int 0)] 7296: "" 1.1.1.2 root 7297: "{cror 0,0,0|nop}") 1.1 root 7298: 1.1.1.4 root 7299: ;; Define the subtract-one-and-jump insns, starting with the template 1.1 root 7300: ;; so loop.c knows what to generate. 7301: 7302: (define_expand "decrement_and_branchsi" 1.1.1.4 root 7303: [(parallel [(set (match_operand:SI 0 "register_operand" "") 7304: (plus:SI (match_dup 0) 7305: (const_int -1))) 7306: (set (pc) (if_then_else (ne (match_dup 0) 1.1 root 7307: (const_int 1)) 7308: (label_ref (match_operand 1 "" "")) 7309: (pc))) 1.1.1.4 root 7310: (clobber (match_scratch:CC 2 "")) 7311: (clobber (match_scratch:SI 3 ""))])] 1.1 root 7312: "" 7313: "") 7314: 7315: ;; We need to be able to do this for any operand, including MEM, or we 7316: ;; will cause reload to blow up since we don't allow output reloads on 1.1.1.4 root 7317: ;; JUMP_INSNs. 7318: ;; In order that the length attribute is calculated correctly, the 7319: ;; label MUST be operand 0. 7320: 1.1 root 7321: (define_insn "" 7322: [(set (pc) 1.1.1.4 root 7323: (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7324: (const_int 1)) 1.1.1.4 root 7325: (label_ref (match_operand 0 "" "")) 1.1 root 7326: (pc))) 1.1.1.4 root 7327: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7328: (plus:SI (match_dup 1) 7329: (const_int -1))) 1.1 root 7330: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7331: (clobber (match_scratch:SI 4 "=X,X,r"))] 7332: "" 1.1.1.2 root 7333: "* 7334: { 7335: if (which_alternative != 0) 7336: return \"#\"; 7337: else if (get_attr_length (insn) == 8) 1.1.1.4 root 7338: return \"{bdn|bdnz} %l0\"; 1.1.1.2 root 7339: else 1.1.1.4 root 7340: return \"bdz $+8\;b %l0\"; 1.1.1.2 root 7341: }" 7342: [(set_attr "type" "branch") 7343: (set_attr "length" "*,12,16")]) 1.1.1.4 root 7344: 7345: (define_insn "" 7346: [(set (pc) 7347: (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") 7348: (const_int 1)) 7349: (pc) 7350: (label_ref (match_operand 0 "" "")))) 7351: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7352: (plus:SI (match_dup 1) 7353: (const_int -1))) 7354: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7355: (clobber (match_scratch:SI 4 "=X,X,r"))] 7356: "" 7357: "* 7358: { 7359: if (which_alternative != 0) 7360: return \"#\"; 7361: else if (get_attr_length (insn) == 8) 7362: return \"bdz %l0\"; 7363: else 7364: return \"{bdn|bdnz} $+8\;b %l0\"; 7365: }" 7366: [(set_attr "type" "branch") 7367: (set_attr "length" "*,12,16")]) 7368: 1.1 root 7369: ;; Similar, but we can use GE since we have a REG_NONNEG. 7370: (define_insn "" 7371: [(set (pc) 1.1.1.4 root 7372: (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7373: (const_int 0)) 1.1.1.4 root 7374: (label_ref (match_operand 0 "" "")) 1.1 root 7375: (pc))) 1.1.1.4 root 7376: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7377: (plus:SI (match_dup 1) 7378: (const_int -1))) 7379: (clobber (match_scratch:CC 3 "=X,&x,&X")) 7380: (clobber (match_scratch:SI 4 "=X,X,r"))] 7381: "find_reg_note (insn, REG_NONNEG, 0)" 7382: "* 7383: { 7384: if (which_alternative != 0) 7385: return \"#\"; 7386: else if (get_attr_length (insn) == 8) 7387: return \"{bdn|bdnz} %l0\"; 7388: else 7389: return \"bdz $+8\;b %l0\"; 7390: }" 7391: [(set_attr "type" "branch") 7392: (set_attr "length" "*,12,16")]) 7393: 7394: (define_insn "" 7395: [(set (pc) 7396: (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") 7397: (const_int 0)) 7398: (pc) 7399: (label_ref (match_operand 0 "" "")))) 7400: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7401: (plus:SI (match_dup 1) 7402: (const_int -1))) 1.1 root 7403: (clobber (match_scratch:CC 3 "=X,&x,&X")) 7404: (clobber (match_scratch:SI 4 "=X,X,r"))] 7405: "find_reg_note (insn, REG_NONNEG, 0)" 1.1.1.2 root 7406: "* 7407: { 7408: if (which_alternative != 0) 7409: return \"#\"; 7410: else if (get_attr_length (insn) == 8) 1.1.1.4 root 7411: return \"bdz %l0\"; 1.1.1.2 root 7412: else 1.1.1.4 root 7413: return \"{bdn|bdnz} $+8\;b %l0\"; 1.1.1.2 root 7414: }" 7415: [(set_attr "type" "branch") 7416: (set_attr "length" "*,12,16")]) 1.1.1.4 root 7417: 1.1 root 7418: (define_insn "" 7419: [(set (pc) 1.1.1.4 root 7420: (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") 1.1 root 7421: (const_int 1)) 1.1.1.4 root 7422: (label_ref (match_operand 0 "" "")) 1.1 root 7423: (pc))) 1.1.1.4 root 7424: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7425: (plus:SI (match_dup 1) 7426: (const_int -1))) 7427: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7428: (clobber (match_scratch:SI 4 "=X,X,r"))] 7429: "" 7430: "* 7431: { 7432: if (which_alternative != 0) 7433: return \"#\"; 7434: else if (get_attr_length (insn) == 8) 7435: return \"bdz %l0\"; 7436: else 7437: return \"{bdn|bdnz} $+8\;b %l0\"; 7438: }" 7439: [(set_attr "type" "branch") 7440: (set_attr "length" "*,12,16")]) 7441: 7442: (define_insn "" 7443: [(set (pc) 7444: (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") 7445: (const_int 1)) 7446: (pc) 7447: (label_ref (match_operand 0 "" "")))) 7448: (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 7449: (plus:SI (match_dup 1) 7450: (const_int -1))) 1.1 root 7451: (clobber (match_scratch:CC 3 "=X,&x,&x")) 7452: (clobber (match_scratch:SI 4 "=X,X,r"))] 7453: "" 1.1.1.2 root 7454: "* 7455: { 7456: if (which_alternative != 0) 7457: return \"#\"; 7458: else if (get_attr_length (insn) == 8) 1.1.1.4 root 7459: return \"{bdn|bdnz} %l0\"; 1.1.1.2 root 7460: else 1.1.1.4 root 7461: return \"bdz $+8\;b %l0\"; 1.1.1.2 root 7462: }" 7463: [(set_attr "type" "branch") 7464: (set_attr "length" "*,12,16")]) 1.1 root 7465: 7466: (define_split 7467: [(set (pc) 7468: (if_then_else (match_operator 2 "comparison_operator" 7469: [(match_operand:SI 1 "gpc_reg_operand" "") 7470: (const_int 1)]) 7471: (match_operand 5 "" "") 7472: (match_operand 6 "" ""))) 7473: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1.1.4 root 7474: (plus:SI (match_dup 1) 7475: (const_int -1))) 1.1 root 7476: (clobber (match_scratch:CC 3 "")) 7477: (clobber (match_scratch:SI 4 ""))] 7478: "reload_completed" 7479: [(parallel [(set (match_dup 3) 1.1.1.4 root 7480: (compare:CC (plus:SI (match_dup 1) 7481: (const_int -1)) 1.1 root 7482: (const_int 0))) 1.1.1.4 root 7483: (set (match_dup 0) 7484: (plus:SI (match_dup 1) 7485: (const_int -1)))]) 7486: (set (pc) (if_then_else (match_dup 7) 7487: (match_dup 5) 7488: (match_dup 6)))] 1.1 root 7489: " 7490: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 7491: const0_rtx); }") 7492: 7493: (define_split 7494: [(set (pc) 7495: (if_then_else (match_operator 2 "comparison_operator" 7496: [(match_operand:SI 1 "gpc_reg_operand" "") 7497: (const_int 1)]) 7498: (match_operand 5 "" "") 7499: (match_operand 6 "" ""))) 7500: (set (match_operand:SI 0 "general_operand" "") 7501: (plus:SI (match_dup 1) (const_int -1))) 7502: (clobber (match_scratch:CC 3 "")) 7503: (clobber (match_scratch:SI 4 ""))] 7504: "reload_completed && ! gpc_reg_operand (operands[0], SImode)" 7505: [(parallel [(set (match_dup 3) 1.1.1.4 root 7506: (compare:CC (plus:SI (match_dup 1) 7507: (const_int -1)) 1.1 root 7508: (const_int 0))) 1.1.1.4 root 7509: (set (match_dup 4) 7510: (plus:SI (match_dup 1) 7511: (const_int -1)))]) 7512: (set (match_dup 0) 7513: (match_dup 4)) 7514: (set (pc) (if_then_else (match_dup 7) 7515: (match_dup 5) 7516: (match_dup 6)))] 1.1 root 7517: " 7518: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 7519: const0_rtx); }")
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