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1.1 root 1: /* Copyright (C) 1994 Free Software Foundation, Inc.
2:
3: This file is free software; you can redistribute it and/or modify it
4: under the terms of the GNU General Public License as published by the
5: Free Software Foundation; either version 2, or (at your option) any
6: later version.
7:
8: In addition to the permissions in the GNU General Public License, the
9: Free Software Foundation gives you unlimited permission to link the
10: compiled version of this file with other programs, and to distribute
11: those programs without any restriction coming from the use of this
12: file. (The General Public License restrictions do apply in other
13: respects; for example, they cover modification of the file, and
14: distribution when not linked into another program.)
15:
16: This file is distributed in the hope that it will be useful, but
17: WITHOUT ANY WARRANTY; without even the implied warranty of
18: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19: General Public License for more details.
20:
21: You should have received a copy of the GNU General Public License
22: along with this program; see the file COPYING. If not, write to
23: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24:
25: /* As a special exception, if you link this library with other files,
26: some of which are compiled with GCC, to produce an executable,
27: this library does not by itself cause the resulting executable
28: to be covered by the GNU General Public License.
29: This exception does not however invalidate any other reasons why
30: the executable file might be covered by the GNU General Public License. */
31:
32:
33: !! libgcc1 routines for the Hitachi SH cpu.
34: !! Contributed by Steve Chamberlain.
35: !! [email protected]
36:
37:
38: #ifdef L_ashiftrt
39: .global ___ashiftrt_r4_0
40: .global ___ashiftrt_r4_1
41: .global ___ashiftrt_r4_2
42: .global ___ashiftrt_r4_3
43: .global ___ashiftrt_r4_4
44: .global ___ashiftrt_r4_5
45: .global ___ashiftrt_r4_6
46: .global ___ashiftrt_r4_7
47: .global ___ashiftrt_r4_8
48: .global ___ashiftrt_r4_9
49: .global ___ashiftrt_r4_10
50: .global ___ashiftrt_r4_11
51: .global ___ashiftrt_r4_12
52: .global ___ashiftrt_r4_13
53: .global ___ashiftrt_r4_14
54: .global ___ashiftrt_r4_15
55: .global ___ashiftrt_r4_16
56: .global ___ashiftrt_r4_17
57: .global ___ashiftrt_r4_18
58: .global ___ashiftrt_r4_19
59: .global ___ashiftrt_r4_20
60: .global ___ashiftrt_r4_21
61: .global ___ashiftrt_r4_22
62: .global ___ashiftrt_r4_23
63: .global ___ashiftrt_r4_24
64: .global ___ashiftrt_r4_25
65: .global ___ashiftrt_r4_26
66: .global ___ashiftrt_r4_27
67: .global ___ashiftrt_r4_28
68: .global ___ashiftrt_r4_29
69: .global ___ashiftrt_r4_30
70: .global ___ashiftrt_r4_31
71: .global ___ashiftrt_r4_32
72:
73: ___ashiftrt_r4_32:
74: shar r4
75: ___ashiftrt_r4_31:
76: shar r4
77: ___ashiftrt_r4_30:
78: shar r4
79: ___ashiftrt_r4_29:
80: shar r4
81: ___ashiftrt_r4_28:
82: shar r4
83: ___ashiftrt_r4_27:
84: shar r4
85: ___ashiftrt_r4_26:
86: shar r4
87: ___ashiftrt_r4_25:
88: shar r4
89: ___ashiftrt_r4_24:
90: shar r4
91: ___ashiftrt_r4_23:
92: shar r4
93: ___ashiftrt_r4_22:
94: shar r4
95: ___ashiftrt_r4_21:
96: shar r4
97: ___ashiftrt_r4_20:
98: shar r4
99: ___ashiftrt_r4_19:
100: shar r4
101: ___ashiftrt_r4_18:
102: shar r4
103: ___ashiftrt_r4_17:
104: shar r4
105: ___ashiftrt_r4_16:
106: shar r4
107: ___ashiftrt_r4_15:
108: shar r4
109: ___ashiftrt_r4_14:
110: shar r4
111: ___ashiftrt_r4_13:
112: shar r4
113: ___ashiftrt_r4_12:
114: shar r4
115: ___ashiftrt_r4_11:
116: shar r4
117: ___ashiftrt_r4_10:
118: shar r4
119: ___ashiftrt_r4_9:
120: shar r4
121: ___ashiftrt_r4_8:
122: shar r4
123: ___ashiftrt_r4_7:
124: shar r4
125: ___ashiftrt_r4_6:
126: shar r4
127: ___ashiftrt_r4_5:
128: shar r4
129: ___ashiftrt_r4_4:
130: shar r4
131: ___ashiftrt_r4_3:
132: shar r4
133: ___ashiftrt_r4_2:
134: shar r4
135: ___ashiftrt_r4_1:
136: rts
137: shar r4
138:
139: ___ashiftrt_r4_0:
140: or r0,r0
141: rts
142: #endif
143:
144: #ifdef L_movstr
145: .text
146: ! done all the large groups, do the remainder
147:
148: ! jump to movstr+
149: done:
150: add #64,r5
151: mova ___movstrSI0,r0
152: shll2 r6
153: add r6,r0
154: jmp @r0
155: add #64,r4
156: .align 4
157: .global ___movstrSI64
158: ___movstrSI64:
159: mov.l @(60,r5),r0
160: mov.l r0,@(60,r4)
161: .global ___movstrSI60
162: ___movstrSI60:
163: mov.l @(56,r5),r0
164: mov.l r0,@(56,r4)
165: .global ___movstrSI56
166: ___movstrSI56:
167: mov.l @(52,r5),r0
168: mov.l r0,@(52,r4)
169: .global ___movstrSI52
170: ___movstrSI52:
171: mov.l @(48,r5),r0
172: mov.l r0,@(48,r4)
173: .global ___movstrSI48
174: ___movstrSI48:
175: mov.l @(44,r5),r0
176: mov.l r0,@(44,r4)
177: .global ___movstrSI44
178: ___movstrSI44:
179: mov.l @(40,r5),r0
180: mov.l r0,@(40,r4)
181: .global ___movstrSI40
182: ___movstrSI40:
183: mov.l @(36,r5),r0
184: mov.l r0,@(36,r4)
185: .global ___movstrSI36
186: ___movstrSI36:
187: mov.l @(32,r5),r0
188: mov.l r0,@(32,r4)
189: .global ___movstrSI32
190: ___movstrSI32:
191: mov.l @(28,r5),r0
192: mov.l r0,@(28,r4)
193: .global ___movstrSI28
194: ___movstrSI28:
195: mov.l @(24,r5),r0
196: mov.l r0,@(24,r4)
197: .global ___movstrSI24
198: ___movstrSI24:
199: mov.l @(20,r5),r0
200: mov.l r0,@(20,r4)
201: .global ___movstrSI20
202: ___movstrSI20:
203: mov.l @(16,r5),r0
204: mov.l r0,@(16,r4)
205: .global ___movstrSI16
206: ___movstrSI16:
207: mov.l @(12,r5),r0
208: mov.l r0,@(12,r4)
209: .global ___movstrSI12
210: ___movstrSI12:
211: mov.l @(8,r5),r0
212: mov.l r0,@(8,r4)
213: .global ___movstrSI8
214: ___movstrSI8:
215: mov.l @(4,r5),r0
216: mov.l r0,@(4,r4)
217: .global ___movstrSI4
218: ___movstrSI4:
219: mov.l @(0,r5),r0
220: mov.l r0,@(0,r4)
221: ___movstrSI0:
222: rts
223: or r0,r0,r0
224:
225: .align 4
226:
227: .global ___movstr
228: ___movstr:
229: mov.l @(60,r5),r0
230: mov.l r0,@(60,r4)
231:
232: mov.l @(56,r5),r0
233: mov.l r0,@(56,r4)
234:
235: mov.l @(52,r5),r0
236: mov.l r0,@(52,r4)
237:
238: mov.l @(48,r5),r0
239: mov.l r0,@(48,r4)
240:
241: mov.l @(44,r5),r0
242: mov.l r0,@(44,r4)
243:
244: mov.l @(40,r5),r0
245: mov.l r0,@(40,r4)
246:
247: mov.l @(36,r5),r0
248: mov.l r0,@(36,r4)
249:
250: mov.l @(32,r5),r0
251: mov.l r0,@(32,r4)
252:
253: mov.l @(28,r5),r0
254: mov.l r0,@(28,r4)
255:
256: mov.l @(24,r5),r0
257: mov.l r0,@(24,r4)
258:
259: mov.l @(20,r5),r0
260: mov.l r0,@(20,r4)
261:
262: mov.l @(16,r5),r0
263: mov.l r0,@(16,r4)
264:
265: mov.l @(12,r5),r0
266: mov.l r0,@(12,r4)
267:
268: mov.l @(8,r5),r0
269: mov.l r0,@(8,r4)
270:
271: mov.l @(4,r5),r0
272: mov.l r0,@(4,r4)
273:
274: mov.l @(0,r5),r0
275: mov.l r0,@(0,r4)
276:
277: add #-16,r6
278: cmp/pl r6
279: bf done
280:
281: add #64,r5
282: bra ___movstr
283: add #64,r4
284: #endif
285:
286: #ifdef L_mulsi3
287:
288:
289: .global ___mulsi3
290:
291: ! r4 = aabb
292: ! r5 = ccdd
293: ! r0 = aabb*ccdd via partial products
294: !
295: ! if aa == 0 and cc = 0
296: ! r0 = bb*dd
297: !
298: ! else
299: ! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
300: !
301:
302: ___mulsi3:
303: mulu r4,r5 ! multiply the lsws macl=bb*dd
304: mov r5,r3 ! r3 = ccdd
305: swap.w r4,r2 ! r2 = bbaa
306: xtrct r2,r3 ! r3 = aacc
307: tst r3,r3 ! msws zero ?
308: bf hiset
309: rts ! yes - then weve got the answer
310: sts macl,r0
311:
312: hiset: sts macl,r0 ! r0 = bb*dd
313: mulu r2,r5 | brewing macl = aa*dd
314: sts macl,r1
315: mulu r3,r4 | brewing macl = cc*bb
316: sts macl,r2
317: add r1,r2
318: shll16 r2
319: rts
320: add r2,r0
321:
322:
323: #endif
324: #ifdef L_sdivsi3
325: .title "SH DIVIDE"
326: !! 4 byte integer Divide code for the Hitachi SH
327: !!
328: !! Steve Chamberlain
329: !! [email protected]
330: !!
331: !!
332:
333: !! args in r4 and r5, result in r0 clobber r1,r2,r3
334:
335: .global ___sdivsi3
336: ___sdivsi3:
337: mov r4,r1
338: mov r5,r0
339:
340: tst r0,r0
341: bt div0
342: mov #0,r2
343: div0s r2,r1
344: subc r3,r3
345: subc r2,r1
346: div0s r0,r3
347: rotcl r1
348: div1 r0,r3
349: rotcl r1
350: div1 r0,r3
351: rotcl r1
352: div1 r0,r3
353: rotcl r1
354: div1 r0,r3
355: rotcl r1
356: div1 r0,r3
357: rotcl r1
358: div1 r0,r3
359: rotcl r1
360: div1 r0,r3
361: rotcl r1
362: div1 r0,r3
363: rotcl r1
364: div1 r0,r3
365: rotcl r1
366: div1 r0,r3
367: rotcl r1
368: div1 r0,r3
369: rotcl r1
370: div1 r0,r3
371: rotcl r1
372: div1 r0,r3
373: rotcl r1
374: div1 r0,r3
375: rotcl r1
376: div1 r0,r3
377: rotcl r1
378: div1 r0,r3
379: rotcl r1
380: div1 r0,r3
381: rotcl r1
382: div1 r0,r3
383: rotcl r1
384: div1 r0,r3
385: rotcl r1
386: div1 r0,r3
387: rotcl r1
388: div1 r0,r3
389: rotcl r1
390: div1 r0,r3
391: rotcl r1
392: div1 r0,r3
393: rotcl r1
394: div1 r0,r3
395: rotcl r1
396: div1 r0,r3
397: rotcl r1
398: div1 r0,r3
399: rotcl r1
400: div1 r0,r3
401: rotcl r1
402: div1 r0,r3
403: rotcl r1
404: div1 r0,r3
405: rotcl r1
406: div1 r0,r3
407: rotcl r1
408: div1 r0,r3
409: rotcl r1
410: div1 r0,r3
411: rotcl r1
412: addc r2,r1
413: rts
414: mov r1,r0
415:
416:
417: div0: rts
418: mov #0,r0
419:
420: #endif
421: #ifdef L_udivsi3
422:
423: .title "SH DIVIDE"
424: !! 4 byte integer Divide code for the Hitachi SH
425: !!
426: !! Steve Chamberlain
427: !! [email protected]
428: !!
429: !!
430:
431: !! args in r4 and r5, result in r0, clobbers r4,r6, pr and t bit
432: .global ___udivsi3
433:
434: ___udivsi3:
435: longway:
436: mov #0,r0
437: div0u
438: ! get one bit from the msb of the numerator into the T
439: ! bit and divide it by whats in r5. Put the answer bit
440: ! into the T bit so it can come out again at the bottom
441:
442: rotcl r4 ; div1 r5,r0
443: rotcl r4 ; div1 r5,r0
444: rotcl r4 ; div1 r5,r0
445: rotcl r4 ; div1 r5,r0
446: rotcl r4 ; div1 r5,r0
447: rotcl r4 ; div1 r5,r0
448: rotcl r4 ; div1 r5,r0
449: rotcl r4 ; div1 r5,r0
450:
451: rotcl r4 ; div1 r5,r0
452: rotcl r4 ; div1 r5,r0
453: rotcl r4 ; div1 r5,r0
454: rotcl r4 ; div1 r5,r0
455: rotcl r4 ; div1 r5,r0
456: rotcl r4 ; div1 r5,r0
457: rotcl r4 ; div1 r5,r0
458: rotcl r4 ; div1 r5,r0
459: shortway:
460: rotcl r4 ; div1 r5,r0
461: rotcl r4 ; div1 r5,r0
462: rotcl r4 ; div1 r5,r0
463: rotcl r4 ; div1 r5,r0
464: rotcl r4 ; div1 r5,r0
465: rotcl r4 ; div1 r5,r0
466: rotcl r4 ; div1 r5,r0
467: rotcl r4 ; div1 r5,r0
468:
469: vshortway:
470: rotcl r4 ; div1 r5,r0
471: rotcl r4 ; div1 r5,r0
472: rotcl r4 ; div1 r5,r0
473: rotcl r4 ; div1 r5,r0
474: rotcl r4 ; div1 r5,r0
475: rotcl r4 ; div1 r5,r0
476: rotcl r4 ; div1 r5,r0
477: rotcl r4 ; div1 r5,r0
478: rotcl r4
479: ret: rts
480: mov r4,r0
481:
482: #endif
483:
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