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1.1.1.3 ! root 1: /* Definitions of target machine for GNU compiler, ! 2: for Hitachi Super-H. ! 3: Copyright (C) 1993, 1994 Free Software Foundation, Inc. 1.1 root 4: 5: Contributed by Steve Chamberlain ([email protected]) 6: 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 22: 23: 24: /* Run-time Target Specification. */ 25: #define TARGET_SH 26: 27: #define TARGET_VERSION \ 28: fputs (" (Hitachi SH)", stderr); 29: 30: /* Generate SDB debugging information. */ 31: 32: #define SDB_DEBUGGING_INFO 1 33: 1.1.1.3 ! root 34: /* CYGNUS LOCAL stabs-in-coff */ ! 35: /* Output DBX (stabs) debugging information if doing -gstabs. */ ! 36: ! 37: #define DBX_DEBUGGING_INFO ! 38: ! 39: /* Generate SDB debugging information by default. */ ! 40: ! 41: #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG ! 42: 1.1 root 43: #define SDB_DELIM ";" 44: 1.1.1.2 root 45: #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)" 1.1 root 46: 1.1.1.3 ! root 47: /* Show we can debug even without a frame pointer. */ ! 48: #define CAN_DEBUG_WITHOUT_FP 1.1 root 49: 50: 1.1.1.3 ! root 51: #define CONDITIONAL_REGISTER_USAGE \ ! 52: /* Experimental calling convention with fewer saved registers */ \ ! 53: if (TARGET_NOSAVE) \ ! 54: { \ ! 55: call_used_regs[8] = 1; \ ! 56: call_used_regs[9] = 1; \ ! 57: call_used_regs[10] = 1; \ ! 58: call_used_regs[11] = 1; \ ! 59: } \ ! 60: /* Hitachi saves and restores mac registers on call */ \ ! 61: if (TARGET_HITACHI) \ ! 62: { \ ! 63: call_used_regs[MACH_REG] = 0; \ ! 64: call_used_regs[MACL_REG] = 0; \ ! 65: } ! 66: 1.1 root 67: 68: /* Run-time compilation parameters selecting different hardware subsets. */ 69: 70: extern int target_flags; 1.1.1.3 ! root 71: #define ISIZE_BIT (1<<1) ! 72: #define FAST_BIT (1<<2) ! 73: #define MAC_BIT (1<<3) ! 74: #define RTL_BIT (1<<4) ! 75: #define DT_BIT (1<<5) ! 76: #define DALIGN_BIT (1<<6) ! 77: #define SH0_BIT (1<<7) ! 78: #define SH1_BIT (1<<8) ! 79: #define SH2_BIT (1<<9) ! 80: #define SH3_BIT (1<<10) ! 81: #define C_BIT (1<<11) ! 82: #define R_BIT (1<<12) ! 83: #define SPACE_BIT (1<<13) ! 84: #define BIGTABLE_BIT (1<<14) ! 85: #define TRYR0_BIT (1<<15) ! 86: #define NOSAVE_BIT (1<<16) ! 87: #define SMALLCALL_BIT (1<<17) ! 88: #define CONSTLEN_2_BIT (1<<20) ! 89: #define CONSTLEN_3_BIT (1<<21) ! 90: #define HITACHI_BIT (1<<22) ! 91: #define PARANOID_BIT (1<<23) ! 92: #define RETR2_BIT (1<<24) ! 93: #define CONSTLEN_0_BIT (1<<25) ! 94: #define BSR_BIT (1<<26) ! 95: #define SHORTADDR_BIT (1<<27) ! 96: #define PACKSTRUCT_BIT (1<<28) 1.1.1.2 root 97: 98: /* Nonzero if we should generate code using type 0 insns */ 99: #define TARGET_SH0 (target_flags & SH0_BIT) 100: 101: /* Nonzero if we should generate code using type 1 insns */ 102: #define TARGET_SH1 (target_flags & SH1_BIT) 1.1 root 103: 1.1.1.2 root 104: /* Nonzero if we should generate code using type 2 insns */ 105: #define TARGET_SH2 (target_flags & SH2_BIT) 106: 107: /* Nonzero if we should generate code using type 3 insns */ 108: #define TARGET_SH3 (target_flags & SH3_BIT) 1.1 root 109: 110: /* Nonzero if we should generate faster code rather than smaller code */ 111: #define TARGET_FASTCODE (target_flags & FAST_BIT) 112: 1.1.1.2 root 113: /* Nonzero if we should generate faster code rather than smaller code */ 114: #define TARGET_SMALLCODE (target_flags & SPACE_BIT) 115: 1.1 root 116: /* Nonzero if we should dump out instruction size info */ 117: #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) 118: 119: /* Nonzero if we should try to generate mac instructions */ 120: #define TARGET_MAC (target_flags & MAC_BIT) 121: 122: /* Nonzero if we should dump the rtl in the assembly file. */ 123: #define TARGET_DUMP_RTL (target_flags & RTL_BIT) 124: 1.1.1.2 root 125: /* Nonzero if we should dump the rtl somewher else. */ 126: #define TARGET_DUMP_R (target_flags & R_BIT) 1.1 root 127: 128: /* Nonzero to align doubles on 64 bit boundaries */ 129: #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) 130: 1.1.1.3 ! root 131: /* Nonzero to use long jump tables */ ! 132: #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) 1.1.1.2 root 133: 1.1.1.3 ! root 134: /* Nonzero if combine dumping wanted */ 1.1.1.2 root 135: #define TARGET_CDUMP (target_flags & C_BIT) 136: 1.1.1.3 ! root 137: /* Nonzero if trying to use reg+disp for QIs and HIs. This ! 138: doesn't work yet.*/ ! 139: #define TARGET_TRYR0 (target_flags & TRYR0_BIT) ! 140: ! 141: /* Nonzero if using no save calling convention */ ! 142: #define TARGET_NOSAVE (target_flags & NOSAVE_BIT) ! 143: ! 144: /* Nonzero if using no save calling convention */ ! 145: #define TARGET_SMALLCALL (target_flags & SMALLCALL_BIT) ! 146: ! 147: /* Select max size of computed constant code sequences to be 3 insns */ ! 148: #define TARGET_CLEN3 (target_flags & CONSTLEN_3_BIT) ! 149: ! 150: /* Select max size of computed constant code sequences to be 0 insns - ie don't do it */ ! 151: #define TARGET_CLEN0 (target_flags & CONSTLEN_0_BIT) ! 152: ! 153: /* Nonzero if using Hitachi's calling convention */ ! 154: #define TARGET_HITACHI (target_flags & HITACHI_BIT) ! 155: ! 156: #define TARGET_PARANOID (target_flags & PARANOID_BIT) ! 157: #define TARGET_RETR2 (target_flags & RETR2_BIT) ! 158: #define TARGET_SHORTADDR (target_flags & SHORTADDR_BIT) ! 159: #define TARGET_BSR (target_flags & BSR_BIT) ! 160: ! 161: /* Nonzero if packing structures as small as they'll go (incompatible with Hitachi's compiler) */ ! 162: #define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT) ! 163: ! 164: #define TARGET_SWITCHES \ ! 165: { {"isize", ( ISIZE_BIT) }, \ ! 166: {"space", ( SPACE_BIT) }, \ ! 167: {"0", ( SH0_BIT) }, \ ! 168: {"1", ( SH1_BIT) }, \ ! 169: {"2", ( SH2_BIT) }, \ ! 170: {"3", ( SH3_BIT) }, \ ! 171: {"ac", ( MAC_BIT) }, \ ! 172: {"dalign", ( DALIGN_BIT) }, \ ! 173: {"c", ( C_BIT) }, \ ! 174: {"r", ( RTL_BIT) }, \ ! 175: {"bigtable", ( BIGTABLE_BIT)}, \ ! 176: {"try-r0", ( TRYR0_BIT)}, \ ! 177: {"R", ( R_BIT) }, \ ! 178: {"nosave", ( NOSAVE_BIT) }, \ ! 179: {"clen3", ( CONSTLEN_3_BIT) }, \ ! 180: {"clen0", ( CONSTLEN_0_BIT) }, \ ! 181: {"smallcall", ( SMALLCALL_BIT) }, \ ! 182: {"hitachi", ( HITACHI_BIT) }, \ ! 183: {"paranoid", ( PARANOID_BIT) }, \ ! 184: {"r2", ( RETR2_BIT) }, \ ! 185: {"shortaddr", ( SHORTADDR_BIT) }, \ ! 186: {"bsr", ( BSR_BIT) }, \ ! 187: {"packstruct",( PACKSTRUCT_BIT) }, \ ! 188: {"", TARGET_DEFAULT} \ 1.1 root 189: } 190: 1.1.1.3 ! root 191: #define TARGET_DEFAULT (FAST_BIT) 1.1 root 192: 1.1.1.3 ! root 193: /* Macro to define table for command options with values. */ ! 194: #define TARGET_OPTIONS \ ! 195: { { "maxsi-", &max_si}, \ ! 196: { "maxhi-", &max_hi} } ! 197: ! 198: #define OVERRIDE_OPTIONS \ ! 199: do { \ ! 200: sh_cpu = CPU_SH0; \ ! 201: if (TARGET_SH1) \ ! 202: sh_cpu = CPU_SH1; \ ! 203: if (TARGET_SH2) \ ! 204: sh_cpu = CPU_SH2; \ ! 205: if (TARGET_SH3) \ ! 206: sh_cpu = CPU_SH3; \ ! 207: \ ! 208: /* We *MUST* always define optimize since we *HAVE* to run \ ! 209: shorten branches to get correct code. */ \ ! 210: \ ! 211: optimize = 1; \ ! 212: flag_delayed_branch = 1; \ ! 213: /* But never run scheduling before reload, since than can \ ! 214: break global alloc, and generates slower code anyway due \ ! 215: to the pressure on R0. */ \ ! 216: flag_schedule_insns = 0; \ ! 217: if (max_si) \ ! 218: max_count_si = atoi (max_si); \ ! 219: else \ ! 220: max_count_si = 1010; \ ! 221: if (max_hi) \ ! 222: max_count_hi = atoi (max_hi); \ ! 223: else \ ! 224: max_count_hi = 500; \ ! 225: if (TARGET_BSR) \ ! 226: flag_no_function_cse = 1; \ ! 227: } while (0) 1.1.1.2 root 228: 1.1 root 229: 230: /* Target machine storage Layout. */ 231: 1.1.1.2 root 232: /* Define to use software floating point emulator for REAL_ARITHMETIC and 233: decimal <-> binary conversion. */ 234: #define REAL_ARITHMETIC 235: 1.1 root 236: /* Define this if most significant bit is lowest numbered 237: in instructions that operate on numbered bit-fields. */ 238: #define BITS_BIG_ENDIAN 0 239: 240: /* Define this if most significant byte of a word is the lowest numbered. */ 241: #define BYTES_BIG_ENDIAN 1 242: 243: /* Define this if most significant word of a multiword number is the lowest 244: numbered. */ 245: #define WORDS_BIG_ENDIAN 1 246: 247: /* Number of bits in an addressable storage unit */ 248: #define BITS_PER_UNIT 8 249: 250: /* Width in bits of a "word", which is the contents of a machine register. 251: Note that this is not necessarily the width of data type `int'; 252: if using 16-bit ints on a 68000, this would still be 32. 253: But on a machine with 16-bit registers, this would be 16. */ 254: #define BITS_PER_WORD 32 255: #define MAX_BITS_PER_WORD 32 256: 257: /* Width of a word, in units (bytes). */ 258: #define UNITS_PER_WORD 4 259: 260: /* Width in bits of a pointer. 261: See also the macro `Pmode' defined below. */ 262: #define POINTER_SIZE 32 263: 264: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 265: #define PARM_BOUNDARY 32 266: 267: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 268: #define STACK_BOUNDARY 32 269: 270: /* Allocation boundary (in *bits*) for the code of a function. */ 271: #define FUNCTION_BOUNDARY 16 272: 273: /* Alignment of field after `int : 0' in a structure. */ 274: #define EMPTY_FIELD_BOUNDARY 32 275: 276: /* No data type wants to be aligned rounder than this. */ 277: #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 278: 279: /* The best alignment to use in cases where we have a choice. */ 280: #define FASTEST_ALIGNMENT 32 281: 282: /* Make strings word-aligned so strcpy from constants will be faster. */ 283: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 284: ((TREE_CODE (EXP) == STRING_CST \ 285: && (ALIGN) < FASTEST_ALIGNMENT) \ 1.1.1.3 ! root 286: ? FASTEST_ALIGNMENT : (ALIGN)) 1.1 root 287: 288: /* Make arrays of chars word-aligned for the same reasons. */ 289: #define DATA_ALIGNMENT(TYPE, ALIGN) \ 290: (TREE_CODE (TYPE) == ARRAY_TYPE \ 291: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 292: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 293: 1.1.1.3 ! root 294: /* Number of bits which any structure or union's size must be a ! 295: multiple of. Each structure or union's size is rounded up to a ! 296: multiple of this. */ ! 297: #define STRUCTURE_SIZE_BOUNDARY (TARGET_PACKSTRUCT ? 8 : 32) ! 298: 1.1 root 299: /* Set this nonzero if move instructions will actually fail to work 300: when given unaligned data. */ 301: #define STRICT_ALIGNMENT 1 302: 303: 304: /* Standard register usage. */ 305: 1.1.1.3 ! root 306: /* Register allocation for the Hitachi calling convention: 1.1 root 307: 1.1.1.3 ! root 308: r0 arg return ! 309: r1..r3 scratch ! 310: r4-r7 args in ! 311: r8..r13 call saved ! 312: r14 frame pointer/call saved 1.1 root 313: r15 stack pointer 314: ap arg pointer (doesn't really exist, always eliminated) 315: pr subroutine return address 316: t t bit 317: mach multiply/accumulate result 318: macl 319: */ 320: 321: /* Number of actual hardware registers. 322: The hardware registers are assigned numbers for the compiler 323: from 0 to just below FIRST_PSEUDO_REGISTER. 324: All registers that the compiler knows about must be given numbers, 1.1.1.3 ! root 325: even those that are not normally considered general registers. */ 1.1 root 326: 1.1.1.3 ! root 327: #define AP_REG 16 1.1 root 328: #define PR_REG 17 329: #define T_REG 18 330: #define GBR_REG 19 331: #define MACH_REG 20 332: #define MACL_REG 21 333: 1.1.1.3 ! root 334: #define FIRST_PSEUDO_REGISTER 22 1.1 root 335: 336: /* 1 for registers that have pervasive standard uses 1.1.1.3 ! root 337: and are not available for the register allocator. ! 338: ! 339: mach register is fixed 'cause it's only 10 bits wide */ ! 340: ! 341: /* r0 r1 r2 r3 ! 342: r4 r5 r6 r7 ! 343: r8 r9 r10 r11 ! 344: r12 r13 r14 r15 ! 345: ap pr t gbr ! 346: mh ml */ ! 347: ! 348: #define FIXED_REGISTERS \ ! 349: { 0, 0, 0, 0, \ ! 350: 0, 0, 0, 0, \ ! 351: 0, 0, 0, 0, \ ! 352: 0, 0, 0, 1, \ ! 353: 1, 1, 1, 1, \ ! 354: 1, 1} ! 355: 1.1 root 356: 357: /* 1 for registers not available across function calls. 358: These must include the FIXED_REGISTERS and also any 359: registers that can be used without being saved. 360: The latter must include the registers where values are returned 361: and the register where structure-value addresses are passed. 362: Aside from that, you can include as many other registers as you like. */ 363: 1.1.1.3 ! root 364: /* r0 r1 r2 r3 ! 365: r4 r5 r6 r7 ! 366: r8 r9 r10 r11 ! 367: r12 r13 r14 r15 ! 368: ap pr t gbr ! 369: mh ml */ ! 370: ! 371: #define CALL_USED_REGISTERS \ ! 372: { 1, 1, 1, 1, \ ! 373: 1, 1, 1, 1, \ ! 374: 0, 0, 0, 0, \ ! 375: 0, 0, 0, 1, \ ! 376: 1, 0, 1, 1, \ ! 377: 1, 1} 1.1 root 378: 379: /* Return number of consecutive hard regs needed starting at reg REGNO 380: to hold something of mode MODE. 381: This is ordinarily the length in words of a value of mode MODE 382: but can be less for certain modes in special long registers. 383: 384: On the SH regs are UNITS_PER_WORD bits wide; */ 1.1.1.3 ! root 385: 1.1 root 386: #define HARD_REGNO_NREGS(REGNO, MODE) \ 387: (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 388: 389: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 390: We may keep double values in even registers */ 391: 1.1.1.3 ! root 392: extern int hard_regno_mode_ok[]; 1.1 root 393: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1.1.1.3 ! root 394: (hard_regno_mode_ok[REGNO] & (1<<(int)MODE)) 1.1 root 395: 396: /* Value is 1 if it is a good idea to tie two pseudo registers 397: when one has mode MODE1 and one has mode MODE2. 398: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 399: for any hard reg, then this must be 0 for correct output. */ 400: 401: #define MODES_TIEABLE_P(MODE1, MODE2) \ 402: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 403: 404: /* Specify the registers used for certain standard purposes. 405: The values of these macros are register numbers. */ 406: 407: /* Define this if the program counter is overloaded on a register. */ 408: /* #define PC_REGNUM 15*/ 409: 410: /* Register to use for pushing function arguments. */ 411: #define STACK_POINTER_REGNUM 15 412: 413: /* Base register for access to local variables of the function. */ 414: #define FRAME_POINTER_REGNUM 14 415: 416: /* Value should be nonzero if functions must have frame pointers. 417: Zero means the frame pointer need not be set up (and parms may be accessed 418: via the stack pointer) in functions that seem suitable. */ 1.1.1.2 root 419: 1.1.1.3 ! root 420: #define FRAME_POINTER_REQUIRED 0 1.1 root 421: 422: /* Definitions for register eliminations. 423: 424: We have two registers that can be eliminated on the m88k. First, the 425: frame pointer register can often be eliminated in favor of the stack 426: pointer register. Secondly, the argument pointer register can always be 427: eliminated; it is replaced with either the stack or frame pointer. */ 428: 429: /* This is an array of structures. Each structure initializes one pair 430: of eliminable registers. The "from" register number is given first, 431: followed by "to". Eliminations of the same "from" register are listed 432: in order of preference. */ 433: 1.1.1.3 ! root 434: /* This is an array of structures. Each structure initializes one pair ! 435: of eliminable registers. The "from" register number is given first, ! 436: followed by "to". Eliminations of the same "from" register are listed ! 437: in order of preference. */ ! 438: 1.1 root 439: #define ELIMINABLE_REGS \ 440: {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 441: { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 442: { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} 443: 1.1.1.3 ! root 444: 1.1 root 445: /* Given FROM and TO register numbers, say whether this elimination 446: is allowed. */ 447: #define CAN_ELIMINATE(FROM, TO) \ 448: (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) 449: 450: /* Define the offset between two registers, one to be eliminated, and the other 451: its replacement, at the start of a routine. */ 452: 453: #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 454: OFFSET = initial_elimination_offset (FROM, TO) 455: 456: /* Base register for access to arguments of the function. */ 457: #define ARG_POINTER_REGNUM 16 458: 459: /* Register in which the static-chain is passed to a function. */ 460: #define STATIC_CHAIN_REGNUM 13 461: 1.1.1.2 root 462: /* The register in which a struct value address is passed */ 463: 1.1.1.3 ! root 464: #define STRUCT_VALUE_REGNUM 2 ! 465: ! 466: /* If the structure value address is not passed in a register, define ! 467: `STRUCT_VALUE' as an expression returning an RTX for the place ! 468: where the address is passed. If it returns 0, the address is ! 469: passed as an "invisible" first argument. */ 1.1 root 470: 1.1.1.3 ! root 471: /*#define STRUCT_VALUE ((rtx)0)*/ ! 472: ! 473: ! 474: /* Don't default to pcc-struct-return, because we have already specified ! 475: exactly how to return structures in the RETURN_IN_MEMORY macro. */ ! 476: ! 477: #define DEFAULT_PCC_STRUCT_RETURN 0 1.1 root 478: 479: 480: /* Define the classes of registers for register constraints in the 481: machine description. Also define ranges of constants. 482: 483: One of the classes must always be named ALL_REGS and include all hard regs. 484: If there is more than one class, another class must be named NO_REGS 485: and contain no registers. 486: 487: The name GENERAL_REGS must be the name of a class (or an alias for 488: another name such as ALL_REGS). This is the class of registers 489: that is allowed by "g" or "r" in a register constraint. 490: Also, registers outside this class are allocated only when 491: instructions express preferences for them. 492: 493: The classes must be numbered in nondecreasing order; that is, 494: a larger-numbered class must never be contained completely 495: in a smaller-numbered class. 496: 497: For any two classes, it is very desirable that there be another 498: class that represents their union. */ 499: 500: /* The SH has two sorts of general registers, R0 and the rest. R0 can 501: be used as the destination of some of the arithmetic ops. There are 502: also some special purpose registers; the T bit register, the 503: Procedure Return Register and the Multipy Accumulate Registers */ 504: 505: enum reg_class 506: { 507: NO_REGS, 508: R0_REGS, 509: PR_REGS, 510: T_REGS, 511: MAC_REGS, 1.1.1.3 ! root 512: GENERAL_REGS, 1.1 root 513: ALL_REGS, 514: LIM_REG_CLASSES 515: }; 516: 517: #define N_REG_CLASSES (int) LIM_REG_CLASSES 518: 519: /* Give names of register classes as strings for dump file. */ 520: #define REG_CLASS_NAMES \ 521: { \ 522: "NO_REGS", \ 523: "R0_REGS", \ 524: "PR_REGS", \ 525: "T_REGS", \ 526: "MAC_REGS", \ 1.1.1.3 ! root 527: "GENERAL_REGS", \ 1.1 root 528: "ALL_REGS", \ 529: } 530: 531: /* Define which registers fit in which classes. 532: This is an initializer for a vector of HARD_REG_SET 533: of length N_REG_CLASSES. */ 534: 535: #define REG_CLASS_CONTENTS \ 536: { \ 537: 0x000000, /* NO_REGS */ \ 538: 0x000001, /* R0_REGS */ \ 539: 0x020000, /* PR_REGS */ \ 540: 0x040000, /* T_REGS */ \ 541: 0x300000, /* MAC_REGS */ \ 1.1.1.3 ! root 542: 0x01FFFF, /* GENERAL_REGS */ \ 1.1 root 543: 0x37FFFF /* ALL_REGS */ \ 544: } 545: 546: /* The same information, inverted: 547: Return the class number of the smallest class containing 548: reg number REGNO. This could be a conditional expression 549: or could index an array. */ 550: 551: extern int regno_reg_class[]; 552: #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] 553: 1.1.1.3 ! root 554: /* When defined, the compiler allows registers explicitly used in the ! 555: rtl to be used as spill registers but prevents the compiler from ! 556: extending the lifetime of these registers. */ ! 557: ! 558: #define SMALL_REGISTER_CLASSES ! 559: 1.1 root 560: /* The order in which register should be allocated. */ 561: #define REG_ALLOC_ORDER \ 1.1.1.3 ! root 562: { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 } 1.1 root 563: 564: /* The class value for index registers, and the one for base regs. */ 565: #define INDEX_REG_CLASS R0_REGS 566: #define BASE_REG_CLASS GENERAL_REGS 567: 568: /* Get reg_class from a letter such as appears in the machine 569: description. */ 570: extern enum reg_class reg_class_from_letter[]; 571: 572: #define REG_CLASS_FROM_LETTER(C) \ 573: ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS ) 574: 575: 576: /* The letters I, J, K, L and M in a register constraint string 577: can be used to stand for particular ranges of immediate operands. 578: This macro defines what the ranges are. 579: C is the letter, and VALUE is a constant value. 580: Return 1 if VALUE is in the range specified by C. 581: I: arithmetic operand -127..128, as used in add, sub, etc 1.1.1.2 root 582: L: logical operand 0..255, as used in and, or, etc. 1.1.1.3 ! root 583: J: something ok as a move source - so it must be easy to make 1.1 root 584: M: constant 1 1.1.1.3 ! root 585: N: constant 0 1.1 root 586: K: shift operand 1,2,8 or 16 */ 587: 588: 1.1.1.2 root 589: #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127) 590: #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255) 1.1 root 591: #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) 1.1.1.3 ! root 592: #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) 1.1 root 593: #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) 594: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 595: ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ 1.1.1.3 ! root 596: : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ 1.1 root 597: : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ 598: : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 599: : 0) 600: 601: /* Similar, but for floating constants, and defining letters G and H. 602: Here VALUE is the CONST_DOUBLE rtx itself. */ 603: 604: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 605: ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \ 606: && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \ 607: : 0) 608: 609: /* Given an rtx X being reloaded into a reg required to be 610: in class CLASS, return the class of reg to actually use. 611: In general this is just CLASS; but on some machines 612: in some cases it is preferable to use a more restrictive class. */ 613: 1.1.1.3 ! root 614: #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS 1.1 root 615: 616: /* Return the register class of a scratch register needed to copy IN into 617: or out of a register in CLASS in MODE. If it can be done directly, 618: NO_REGS is returned. */ 619: 620: 621: /* Return the maximum number of consecutive registers 622: needed to represent mode MODE in a register of class CLASS. 623: 624: On SH this is the size of MODE in words */ 625: #define CLASS_MAX_NREGS(CLASS, MODE) \ 626: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 627: 1.1.1.3 ! root 628: 1.1 root 629: 630: /* Stack layout; function entry, exit and calling. */ 631: 632: /* Define the number of register that can hold parameters. 633: These two macros are used only in other macro definitions below. */ 634: #define NPARM_REGS 4 635: #define FIRST_PARM_REG 4 1.1.1.3 ! root 636: #define FIRST_RET_REG (TARGET_RETR2 ? 2 : 0) 1.1 root 637: 638: /* Define this if pushing a word on the stack 639: makes the stack pointer a smaller address. */ 640: #define STACK_GROWS_DOWNWARD 641: 1.1.1.3 ! root 642: /* Define this macro if the addresses of local variable slots are at ! 643: negative offsets from the frame pointer. ! 644: ! 645: The SH only has positive indexes, so grow the frame up ! 646: */ ! 647: /* #define FRAME_GROWS_DOWNWARD */ ! 648: ! 649: /* Offset from the frame pointer to the first local variable slot to ! 650: be allocated. */ 1.1 root 651: #define STARTING_FRAME_OFFSET 0 652: 653: /* If we generate an insn to push BYTES bytes, 654: this says how many the stack pointer really advances by. */ 655: #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 656: 657: /* Offset of first parameter from the argument pointer register value. */ 658: #define FIRST_PARM_OFFSET(FNDECL) 0 659: 660: /* Value is the number of byte of arguments automatically 661: popped when returning from a subroutine call. 662: FUNTYPE is the data type of the function (as a tree), 663: or for a library call it is an identifier node for the subroutine name. 664: SIZE is the number of bytes of arguments passed on the stack. 665: 666: On the SH, the caller does not pop any of its arguments that were passed 667: on the stack. */ 668: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 669: 670: /* Define how to find the value returned by a function. 671: VALTYPE is the data type of the value (as a tree). 672: If the precise function being called is known, FUNC is its FUNCTION_DECL; 673: otherwise, FUNC is 0. */ 1.1.1.3 ! root 674: ! 675: #define FUNCTION_VALUE(VALTYPE, FUNC) \ ! 676: gen_rtx (REG, \ ! 677: TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \ ! 678: FIRST_RET_REG) 1.1 root 679: 680: /* Define how to find the value returned by a library function 681: assuming the value has mode MODE. */ 682: #define LIBCALL_VALUE(MODE) \ 683: gen_rtx (REG, MODE, FIRST_RET_REG) 684: 685: /* 1 if N is a possible register number for a function value. 1.1.1.3 ! root 686: On the SH, only r0 can return results. */ 1.1 root 687: #define FUNCTION_VALUE_REGNO_P(REGNO) \ 688: ((REGNO) == FIRST_RET_REG) 689: 690: /* 1 if N is a possible register number for function argument passing.*/ 691: 692: #define FUNCTION_ARG_REGNO_P(REGNO) \ 693: ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) 694: 695: 696: 697: /* Define a data type for recording info about an argument list 698: during the scan of that argument list. This data type should 699: hold all necessary information about the function itself 700: and about the args processed so far, enough to enable macros 701: such as FUNCTION_ARG to determine where the next arg should go. 702: 703: On SH, this is a single integer, which is a number of words 704: of arguments scanned so far (including the invisible argument, 705: if any, which holds the structure-value-address). 706: Thus NARGREGS or more means all following args should go on the stack. */ 707: 708: #define CUMULATIVE_ARGS int 709: 710: #define ROUND_ADVANCE(SIZE) \ 711: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 712: 713: /* Round a register number up to a proper boundary for an arg of mode 714: MODE. 715: 1.1.1.3 ! root 716: The SH doesn't care about double alignment, so we only ! 717: round doubles to even regs when asked to explicitly. */ 1.1 root 718: 719: #define ROUND_REG(X, MODE) \ 720: ((TARGET_ALIGN_DOUBLE \ 721: && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 722: ? ((X) + ((X) & 1)) : (X)) 723: 724: 725: /* Initialize a variable CUM of type CUMULATIVE_ARGS 726: for a call to a function whose data type is FNTYPE. 727: For a library call, FNTYPE is 0. 728: 729: On SH, the offset always starts at 0: the first parm reg is always 730: the same reg. */ 731: 732: #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ 733: ((CUM) = 0) 734: 735: /* Update the data in CUM to advance over an argument 736: of mode MODE and data type TYPE. 737: (TYPE is null for libcalls where that information may not be 738: available.) */ 739: 740: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 741: ((CUM) = (ROUND_REG ((CUM), (MODE)) \ 742: + ((MODE) != BLKmode \ 743: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 744: : ROUND_ADVANCE (int_size_in_bytes (TYPE))))) 745: 746: /* Define where to put the arguments to a function. 747: Value is zero to push the argument on the stack, 748: or a hard register in which to store the argument. 749: 750: MODE is the argument's machine mode. 751: TYPE is the data type of the argument (as a tree). 752: This is null for libcalls where that information may 753: not be available. 754: CUM is a variable of type CUMULATIVE_ARGS which gives info about 755: the preceding args and about the function being called. 756: NAMED is nonzero if this argument is a named parameter 757: (otherwise it is an extra parameter matching an ellipsis). 758: 759: On SH the first args are normally in registers 760: and the rest are pushed. Any arg that starts within the first 761: NPARM_REGS words is at least partially passed in a register unless 762: its data type forbids. */ 763: 1.1.1.3 ! root 764: ! 765: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ! 766: sh_function_arg (CUM, MODE, TYPE, NAMED) ! 767: ! 768: extern struct rtx_def *sh_function_arg(); 1.1 root 769: 770: /* For an arg passed partly in registers and partly in memory, 771: this is the number of registers used. 772: For args passed entirely in registers or entirely in memory, zero. 1.1.1.3 ! root 773: ! 774: We sometimes split args */ 1.1 root 775: 1.1.1.3 ! root 776: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ! 777: sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED) 1.1 root 778: 779: extern int current_function_anonymous_args; 780: 781: /* Perform any needed actions needed for a function that is receiving a 782: variable number of arguments. */ 783: 784: #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ 785: current_function_anonymous_args = 1; 786: 787: 788: /* Call the function profiler with a given profile label. */ 789: 1.1.1.2 root 790: #define FUNCTION_PROFILER(STREAM,LABELNO) \ 791: { \ 792: fprintf(STREAM, " trapa #5\n"); \ 793: fprintf(STREAM, " .align 2\n"); \ 794: fprintf(STREAM, " .long LP%d\n", (LABELNO)); \ 1.1 root 795: } 796: 797: 798: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 799: the stack pointer does not matter. The value is tested only in 800: functions that have frame pointers. 801: No definition is equivalent to always zero. */ 802: 1.1.1.3 ! root 803: #define EXIT_IGNORE_STACK 1 1.1 root 804: 1.1.1.2 root 805: /* Generate the assembly code for function exit 806: Just dump out any accumulated constant table.*/ 1.1 root 807: 1.1.1.3 ! root 808: #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE) ! 809: 1.1 root 810: 811: /* Output assembler code for a block containing the constant parts 812: of a trampoline, leaving space for the variable parts. 813: 814: On the SH, the trapoline looks like 815: 1 0000 D301 mov.l l1,r3 816: 2 0002 DD02 mov.l l2,r13 817: 3 0004 4D2B jmp @r13 818: 4 0006 200B or r0,r0 819: 5 0008 00000000 l1: .long function 820: 6 000c 00000000 l2: .long area 821: */ 822: #define TRAMPOLINE_TEMPLATE(FILE) \ 823: { \ 824: fprintf ((FILE), " .word 0xd301\n"); \ 825: fprintf ((FILE), " .word 0xdd02\n"); \ 826: fprintf ((FILE), " .word 0x4d2b\n"); \ 827: fprintf ((FILE), " .word 0x200b\n"); \ 828: fprintf ((FILE), " .long 0\n"); \ 829: fprintf ((FILE), " .long 0\n"); \ 830: } 831: 832: /* Length in units of the trampoline for entering a nested function. */ 833: #define TRAMPOLINE_SIZE 16 834: 835: /* Alignment required for a trampoline in units. */ 836: #define TRAMPOLINE_ALIGN 4 837: 838: /* Emit RTL insns to initialize the variable parts of a trampoline. 839: FNADDR is an RTX for the address of the function's pure code. 840: CXT is an RTX for the static chain value for the function. */ 841: 842: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 843: { \ 844: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ 845: (CXT)); \ 846: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ 847: (FNADDR)); \ 848: } 849: 850: 851: /* Addressing modes, and classification of registers for them. */ 1.1.1.3 ! root 852: #define HAVE_POST_INCREMENT 1 1.1 root 853: /*#define HAVE_PRE_INCREMENT 1*/ 854: /*#define HAVE_POST_DECREMENT 1*/ 1.1.1.3 ! root 855: #define HAVE_PRE_DECREMENT 1 1.1 root 856: 857: /* Macros to check register numbers against specific register classes. */ 858: 859: /* These assume that REGNO is a hard or pseudo reg number. 860: They give nonzero only if REGNO is a hard reg of the suitable class 861: or a pseudo reg currently allocated to a suitable hard reg. 862: Since they use reg_renumber, they are safe only once reg_renumber 863: has been allocated, which happens in local-alloc.c. 864: 865: */ 1.1.1.3 ! root 866: 1.1 root 867: #define REGNO_OK_FOR_BASE_P(REGNO) \ 868: ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) 1.1.1.3 ! root 869: #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! 870: ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0) 1.1 root 871: 872: /* Maximum number of registers that can appear in a valid memory 873: address. */ 874: 1.1.1.3 ! root 875: #define MAX_REGS_PER_ADDRESS 2 1.1 root 876: 877: /* Recognize any constant value that is a valid address. */ 878: 879: #define CONSTANT_ADDRESS_P(X) \ 880: (GET_CODE (X) == LABEL_REF) 881: 1.1.1.3 ! root 882: /* Nonzero if the constant value X is a legitimate general operand. */ 1.1 root 883: 1.1.1.3 ! root 884: #define LEGITIMATE_CONSTANT_P(X) \ ! 885: (GET_CODE(X) != CONST_DOUBLE /*&& GET_CODE(X) != LABEL_REF*/) 1.1 root 886: 887: 888: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 889: and check its validity for a certain class. 890: We have two alternate definitions for each of them. 891: The usual definition accepts all pseudo regs; the other rejects 892: them unless they have been allocated suitable hard regs. 893: The symbol REG_OK_STRICT causes the latter definition to be used. */ 894: 1.1.1.3 ! root 895: #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3))) ! 896: #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3))) ! 897: #define MODE_DISP_OK_2(X,MODE) ((GET_MODE_SIZE(MODE)==2) && ((unsigned)INTVAL(X)<32) && TARGET_TRYR0 && (!INTVAL(X) &1)) ! 898: #define MODE_DISP_OK_1(X,MODE) ((GET_MODE_SIZE(MODE)==1) && ((unsigned)INTVAL(X)<16) && TARGET_TRYR0) ! 899: 1.1 root 900: #ifndef REG_OK_STRICT 1.1.1.2 root 901: 1.1.1.3 ! root 902: 1.1 root 903: /* Nonzero if X is a hard reg that can be used as a base reg 904: or if it is a pseudo reg. */ 905: #define REG_OK_FOR_BASE_P(X) \ 1.1.1.3 ! root 906: (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) 1.1 root 907: /* Nonzero if X is a hard reg that can be used as an index 908: or if it is a pseudo reg. */ 1.1.1.3 ! root 909: 1.1 root 910: #define REG_OK_FOR_INDEX_P(X) \ 1.1.1.3 ! root 911: (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER) 1.1.1.2 root 912: 913: #define REG_OK_FOR_PRE_POST_P(X) \ 1.1.1.3 ! root 914: (REG_OK_FOR_BASE_P (X)) 1.1.1.2 root 915: 1.1 root 916: #else 917: /* Nonzero if X is a hard reg that can be used as a base reg. */ 1.1.1.2 root 918: #define REG_OK_FOR_BASE_P(X) \ 919: REGNO_OK_FOR_BASE_P (REGNO (X)) 920: 1.1 root 921: /* Nonzero if X is a hard reg that can be used as an index. */ 1.1.1.2 root 922: #define REG_OK_FOR_INDEX_P(X) \ 923: REGNO_OK_FOR_INDEX_P (REGNO (X)) 924: 1.1 root 925: #define REG_OK_FOR_PRE_POST_P(X) \ 1.1.1.3 ! root 926: (REGNO_OK_FOR_BASE_P (REGNO (X))) 1.1 root 927: #endif 1.1.1.3 ! root 928: ! 929: /* The Q is a pc relative load operand */ ! 930: #define EXTRA_CONSTRAINT_Q(OP) \ ! 931: (GET_CODE (OP) == MEM && \ ! 932: ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ ! 933: || (GET_CODE (XEXP (OP, 0)) == CONST \ ! 934: && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \ ! 935: && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \ ! 936: && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT))) ! 937: ! 938: /* The U is a label ref */ ! 939: #define EXTRA_CONSTRAINT_U(OP) \ ! 940: (GET_CODE (OP) == LABEL_REF) ! 941: ! 942: #define IS_INDEX(OP) \ ! 943: ((GET_CODE (OP) == PLUS && \ ! 944: (INDEX_REGISTER_RTX_P (XEXP (OP, 0)) && BASE_REGISTER_RTX_P (XEXP (OP, 1))) || \ ! 945: (INDEX_REGISTER_RTX_P (XEXP (OP, 1)) && BASE_REGISTER_RTX_P (XEXP (OP, 0))))) ! 946: ! 947: ! 948: ! 949: #define EXTRA_CONSTRAINT(OP, C) \ ! 950: ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ ! 951: : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \ ! 952: : 0) ! 953: 1.1 root 954: 955: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 956: that is a valid memory address for an instruction. 957: The MODE argument is the machine mode for the MEM expression 958: that wants to use this address. 959: 960: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1.1.1.2 root 961: 1.1 root 962: #define BASE_REGISTER_RTX_P(X) \ 963: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 964: 965: #define INDEX_REGISTER_RTX_P(X) \ 966: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 967: 968: 969: /* Jump to LABEL if X is a valid address RTX. This must also take 970: REG_OK_STRICT into account when deciding about valid registers, but it uses 971: the above macros so we are in luck. 972: 973: Allow REG 974: REG+disp 975: REG+r0 976: REG++ 977: --REG 978: */ 979: 1.1.1.2 root 980: /* The SH allows a displacement in a QI or HI amode, but only when the 981: other operand is R0. GCC doesn't handle this very well, so we forgo 982: all of that. 983: 984: A legitimate index for a QI or HI is 0, SI and above can be any 985: number 0..63 */ 1.1 root 986: 1.1.1.3 ! root 987: #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ ! 988: do { \ ! 989: if (GET_CODE (OP) == CONST_INT) \ ! 990: { \ ! 991: if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \ ! 992: if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \ ! 993: if (MODE_DISP_OK_2 (OP, MODE)) goto LABEL; \ ! 994: if (MODE_DISP_OK_1 (OP, MODE)) goto LABEL; \ ! 995: } \ 1.1 root 996: } while(0) 997: 998: 1.1.1.2 root 999: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1000: { \ 1001: if (BASE_REGISTER_RTX_P (X)) \ 1002: goto LABEL; \ 1003: else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 1004: && GET_CODE (XEXP (X, 0)) == REG \ 1005: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1006: goto LABEL; \ 1.1.1.3 ! root 1007: else if (GET_CODE (X) == PLUS) \ 1.1.1.2 root 1008: { \ 1009: rtx xop0 = XEXP(X,0); \ 1010: rtx xop1 = XEXP(X,1); \ 1.1.1.3 ! root 1011: if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ 1.1.1.2 root 1012: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 1.1.1.3 ! root 1013: if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop1)) \ 1.1.1.2 root 1014: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 1.1.1.3 ! root 1015: if (GET_MODE_SIZE(MODE)<= 4) { \ 1.1.1.2 root 1016: if(BASE_REGISTER_RTX_P(xop1) && \ 1017: INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \ 1018: if(INDEX_REGISTER_RTX_P(xop1) && \ 1019: BASE_REGISTER_RTX_P(xop0)) goto LABEL; \ 1020: } \ 1021: } \ 1022: else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ 1023: && GET_CODE (XEXP (X, 0)) == REG \ 1024: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1025: goto LABEL; \ 1026: } 1027: 1028: 1029: /* Try machine-dependent ways of modifying an illegitimate address 1.1 root 1030: to be legitimate. If we find one, return the new, valid address. 1031: This macro is used in only one place: `memory_address' in explow.c. 1032: 1033: OLDX is the address as it was before break_out_memory_refs was called. 1034: In some cases it is useful to look at this to decide what needs to be done. 1035: 1036: MODE and WIN are passed so that this macro can use 1037: GO_IF_LEGITIMATE_ADDRESS. 1038: 1039: It is always safe for this macro to do nothing. It exists to recognize 1040: opportunities to optimize the output. 1041: 1.1.1.3 ! root 1042: */ 1.1 root 1043: 1.1.1.3 ! root 1044: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ; 1.1 root 1045: 1046: /* Go to LABEL if ADDR (a legitimate address expression) 1047: has an effect that depends on the machine mode it is used for. */ 1048: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1049: { \ 1050: if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ 1051: || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ 1052: goto LABEL; \ 1053: } 1054: 1055: /* Specify the machine mode that this machine uses 1056: for the index in the tablejump instruction. */ 1.1.1.3 ! root 1057: #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode) 1.1 root 1058: 1059: /* Define this if the tablejump instruction expects the table 1060: to contain offsets from the address of the table. 1061: Do not define this if the table should contain absolute addresses. */ 1.1.1.3 ! root 1062: #define CASE_VECTOR_PC_RELATIVE 1.1 root 1063: 1064: /* Specify the tree operation to be used to convert reals to integers. */ 1065: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1066: 1067: /* This is the kind of divide that is easiest to do in the general case. */ 1068: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1069: 1070: /* 'char' is signed by default */ 1071: #define DEFAULT_SIGNED_CHAR 1 1072: 1073: /* The type of size_t unsigned int. */ 1074: #define SIZE_TYPE "unsigned int" 1075: 1.1.1.3 ! root 1076: #define WCHAR_TYPE "short unsigned int" ! 1077: #define WCHAR_TYPE_SIZE 16 ! 1078: 1.1 root 1079: /* Don't cse the address of the function being compiled. */ 1.1.1.3 ! root 1080: /*#define NO_RECURSIVE_FUNCTION_CSE 1*/ 1.1 root 1081: 1082: /* Max number of bytes we can move from memory to memory 1083: in one reasonably fast instruction. */ 1084: #define MOVE_MAX 4 1085: 1.1.1.2 root 1086: /* Define if operations between registers always perform the operation 1087: on the full register even if a narrower mode is specified. */ 1088: #define WORD_REGISTER_OPERATIONS 1089: 1090: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1091: will either zero-extend or sign-extend. The value of this macro should 1092: be the code that says which one of the two operations is implicitly 1093: done, NIL if none. */ 1094: #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND 1.1 root 1095: 1096: /* Define this if zero-extension is slow (more than one real instruction). 1097: On the SH, it's only one instruction */ 1098: /* #define SLOW_ZERO_EXTEND */ 1099: 1100: /* Nonzero if access to memory by bytes is slow and undesirable. */ 1101: #define SLOW_BYTE_ACCESS 0 1102: 1103: /* We assume that the store-condition-codes instructions store 0 for false 1104: and some other value for true. This is the value stored for true. */ 1105: 1106: #define STORE_FLAG_VALUE 1 1107: 1108: /* Immediate shift counts are truncated by the output routines (or was it 1109: the assembler?). Shift counts in a register are truncated by ARM. Note 1110: that the native compiler puts too large (> 32) immediate shift counts 1111: into a register and shifts by the register, letting the ARM decide what 1112: to do instead of doing that itself. */ 1113: #define SHIFT_COUNT_TRUNCATED 1 1114: 1115: /* All integers have the same format so truncation is easy. */ 1116: #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1117: 1118: /* Define this if addresses of constant functions 1119: shouldn't be put through pseudo regs where they can be cse'd. 1120: Desirable on machines where ordinary constants are expensive 1121: but a CALL with constant address is cheap. */ 1122: /*#define NO_FUNCTION_CSE 1*/ 1123: 1124: /* Chars and shorts should be passed as ints. */ 1125: #define PROMOTE_PROTOTYPES 1 1126: 1127: /* The machine modes of pointers and functions */ 1128: #define Pmode SImode 1129: #define FUNCTION_MODE Pmode 1130: 1131: /* The relative costs of various types of constants. Note that cse.c defines 1132: REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ 1133: 1134: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 1135: case CONST_INT: \ 1.1.1.3 ! root 1136: if (INTVAL(RTX)==0) return 0; \ 1.1 root 1137: if (CONST_OK_FOR_I (INTVAL(RTX))) \ 1138: return 1; \ 1139: else \ 1.1.1.2 root 1140: return 8; \ 1.1 root 1141: case CONST: \ 1142: case LABEL_REF: \ 1143: case SYMBOL_REF: \ 1.1.1.2 root 1144: return 5; \ 1.1 root 1145: case CONST_DOUBLE: \ 1146: return 10; 1147: 1148: #define RTX_COSTS(X, CODE, OUTER_CODE) \ 1.1.1.3 ! root 1149: case AND: \ ! 1150: return COSTS_N_INSNS (andcosts (X)); \ 1.1 root 1151: case MULT: \ 1.1.1.2 root 1152: return COSTS_N_INSNS (multcosts (X)); \ 1153: case ASHIFT: \ 1154: case ASHIFTRT: \ 1155: return COSTS_N_INSNS (shiftcosts (X)) ; \ 1.1 root 1156: case DIV: \ 1157: case UDIV: \ 1158: case MOD: \ 1159: case UMOD: \ 1160: return COSTS_N_INSNS (100); \ 1161: case FLOAT: \ 1162: case FIX: \ 1163: return 100; 1164: 1.1.1.3 ! root 1165: ! 1166: /* The multiply and divide insns on the SH are actually function calls ! 1167: with some special constraints on arguments and register usage. ! 1168: ! 1169: These macros tell reorg that the references to arguments and ! 1170: register clobbers for insns of type sfunc do not appear to happen ! 1171: until after the millicode call. This allows reorg to put insns ! 1172: which set the argument registers into the delay slot of the millicode ! 1173: call -- thus they act more like traditional CALL_INSNs. ! 1174: ! 1175: get_attr_type will try to recognize the given insn, so make sure to ! 1176: filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns ! 1177: in particular. */ ! 1178: ! 1179: #define INSN_SETS_ARE_DELAYED(X) \ ! 1180: ((GET_CODE (X) == INSN \ ! 1181: && GET_CODE (PATTERN (X)) != SEQUENCE \ ! 1182: && GET_CODE (PATTERN (X)) != USE \ ! 1183: && GET_CODE (PATTERN (X)) != CLOBBER \ ! 1184: && get_attr_type (X) == TYPE_SFUNC)) ! 1185: ! 1186: #define INSN_REFERENCES_ARE_DELAYED(X) \ ! 1187: ((GET_CODE (X) == INSN \ ! 1188: && GET_CODE (PATTERN (X)) != SEQUENCE \ ! 1189: && GET_CODE (PATTERN (X)) != USE \ ! 1190: && GET_CODE (PATTERN (X)) != CLOBBER \ ! 1191: && get_attr_type (X) == TYPE_SFUNC)) ! 1192: 1.1 root 1193: /* Compute extra cost of moving data between one register class 1194: and another. 1195: 1196: On the SH it is hard to move into the T reg, but simple to load 1197: from it. 1198: */ 1199: 1200: #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \ 1.1.1.3 ! root 1201: (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1) 1.1 root 1202: 1203: /* Assembler output control */ 1204: 1205: /* The text to go at the start of the assembler file */ 1.1.1.2 root 1206: #define ASM_FILE_START(STREAM) \ 1207: output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \ 1208: W_options, sizeof W_options / sizeof W_options[0]); 1209: 1210: 1.1.1.3 ! root 1211: #define ASM_FILE_END(STREAM) 1.1 root 1212: 1.1.1.2 root 1213: 1.1.1.3 ! root 1214: #define ASM_APP_ON "" ! 1215: #define ASM_APP_OFF "" ! 1216: #define FILE_ASM_OP "\t.file\n" ! 1217: #define IDENT_ASM_OP "\t.ident\n" ! 1218: ! 1219: /* How to change between sections. */ ! 1220: ! 1221: #define TEXT_SECTION_ASM_OP "\t.text" ! 1222: #define DATA_SECTION_ASM_OP "\t.data" ! 1223: #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n" ! 1224: #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n" ! 1225: #define INIT_SECTION_ASM_OP "\t.section\t.init\n" ! 1226: #define EXTRA_SECTIONS in_ctors, in_dtors 1.1.1.2 root 1227: #define EXTRA_SECTION_FUNCTIONS \ 1228: void \ 1229: ctors_section() \ 1230: { \ 1231: if (in_section != in_ctors) \ 1232: { \ 1233: fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ 1234: in_section = in_ctors; \ 1235: } \ 1236: } \ 1237: void \ 1238: dtors_section() \ 1239: { \ 1240: if (in_section != in_dtors) \ 1241: { \ 1242: fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ 1243: in_section = in_dtors; \ 1244: } \ 1.1.1.3 ! root 1245: } 1.1.1.2 root 1246: 1.1.1.3 ! root 1247: /* Assemble generic sections. ! 1248: This is currently only used to support section attributes. */ ! 1249: ! 1250: #define ASM_OUTPUT_SECTION_NAME(FILE, NAME) \ ! 1251: do { fprintf (FILE, ".section\t%s\n", NAME); } while (0) 1.1.1.2 root 1252: 1253: #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ 1254: do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0) 1255: 1256: #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ 1257: do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0) 1258: 1259: #undef DO_GLOBAL_CTORS_BODY 1.1.1.3 ! root 1260: 1.1.1.2 root 1261: #define DO_GLOBAL_CTORS_BODY \ 1262: { \ 1263: typedef (*pfunc)(); \ 1264: extern pfunc __ctors[]; \ 1265: extern pfunc __ctors_end[]; \ 1266: pfunc *p; \ 1267: for (p = __ctors; p < __ctors_end; p++) \ 1268: { \ 1269: (*p)(); \ 1270: } \ 1271: } 1.1 root 1272: 1.1.1.2 root 1273: #undef DO_GLOBAL_DTORS_BODY 1274: #define DO_GLOBAL_DTORS_BODY \ 1275: { \ 1276: typedef (*pfunc)(); \ 1277: extern pfunc __dtors[]; \ 1278: extern pfunc __dtors_end[]; \ 1279: pfunc *p; \ 1280: for (p = __dtors; p < __dtors_end; p++) \ 1281: { \ 1282: (*p)(); \ 1283: } \ 1284: } 1285: 1286: 1287: #define ASM_OUTPUT_REG_PUSH(file, v) \ 1288: fprintf (file, "\tmov.l r%s,-@r15\n", v); 1289: 1290: #define ASM_OUTPUT_REG_POP(file, v) \ 1291: fprintf (file, "\tmov.l @r15+,r%s\n", v); 1292: 1293: 1.1 root 1294: /* The assembler's names for the registers. RFP need not always be used as 1295: the Real framepointer; it can also be used as a normal general register. 1296: Note that the name `fp' is horribly misleading since `fp' is in fact only 1297: the argument-and-return-context pointer. */ 1298: #define REGISTER_NAMES \ 1299: { \ 1300: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1301: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1302: "ap", "pr", "t", "gbr", "mach","macl" \ 1303: } 1304: 1305: /* DBX register number for a given compiler register number */ 1306: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1307: 1308: /* Output a label definition. */ 1309: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 1310: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1311: 1312: 1313: /* This is how to output an assembler line 1314: that says to advance the location counter 1315: to a multiple of 2**LOG bytes. */ 1316: 1317: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1318: if ((LOG) != 0) \ 1319: fprintf (FILE, "\t.align %d\n", LOG) 1320: 1321: /* Output a function label definition. */ 1322: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ 1323: ASM_OUTPUT_LABEL(STREAM, NAME) 1324: 1325: /* Output a globalising directive for a label. */ 1326: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ 1327: (fprintf (STREAM, "\t.global\t"), \ 1328: assemble_name (STREAM, NAME), \ 1329: fputc ('\n',STREAM)) \ 1330: 1331: /* Output a reference to a label. */ 1332: #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ 1333: fprintf (STREAM, "_%s", NAME) 1334: 1335: /* Make an internal label into a string. */ 1336: #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 1337: sprintf (STRING, "*%s%d", PREFIX, NUM) 1338: 1339: /* Output an internal label definition. */ 1340: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1341: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 1342: 1343: /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1344: 1345: /* Construct a private name. */ 1346: #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 1347: ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 1348: sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 1349: 1.1.1.3 ! root 1350: /* Jump tables must be 32 bit aligned, no matter the size of the element */ 1.1 root 1351: #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ 1.1.1.3 ! root 1352: fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM); 1.1 root 1353: 1.1.1.3 ! root 1354: /* Output a relative address table. */ ! 1355: ! 1356: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ ! 1357: if (TARGET_BIGTABLE) \ ! 1358: fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \ ! 1359: else \ ! 1360: fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \ ! 1361: ! 1362: /* Output an absolute table element */ ! 1363: ! 1364: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ ! 1365: if (TARGET_BIGTABLE) \ ! 1366: fprintf (STREAM, "\t.long L%d\n", VALUE); \ ! 1367: else \ ! 1368: fprintf (STREAM, "\t.word L%d\n", VALUE); \ 1.1 root 1369: 1370: /* Output various types of constants. */ 1371: 1372: 1373: /* This is how to output an assembler line defining a `double' */ 1374: 1.1.1.2 root 1375: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1376: do { char dstr[30]; \ 1377: REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ 1378: fprintf (FILE, "\t.double %s\n", dstr); \ 1379: } while (0) 1380: 1.1 root 1381: 1382: /* This is how to output an assembler line defining a `float' constant. */ 1.1.1.2 root 1383: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1384: do { char dstr[30]; \ 1385: REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ 1386: fprintf (FILE, "\t.float %s\n", dstr); \ 1387: } while (0) 1.1 root 1388: 1389: #define ASM_OUTPUT_INT(STREAM, EXP) \ 1390: (fprintf (STREAM, "\t.long\t"), \ 1391: output_addr_const (STREAM, (EXP)), \ 1392: fputc ('\n', STREAM)) 1393: 1394: #define ASM_OUTPUT_SHORT(STREAM, EXP) \ 1395: (fprintf (STREAM, "\t.short\t"), \ 1396: output_addr_const (STREAM, (EXP)), \ 1397: fputc ('\n', STREAM)) 1398: 1399: #define ASM_OUTPUT_CHAR(STREAM, EXP) \ 1400: (fprintf (STREAM, "\t.byte\t"), \ 1401: output_addr_const (STREAM, (EXP)), \ 1402: fputc ('\n', STREAM)) 1403: 1404: #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ 1405: fprintf (STREAM, "\t.byte\t%d\n", VALUE) \ 1406: 1407: /* This is how to output an assembler line 1408: that says to advance the location counter by SIZE bytes. */ 1409: 1410: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1411: fprintf (FILE, "\t.space %d\n", (SIZE)) 1412: 1413: /* This says how to output an assembler line 1414: to define a global common symbol. */ 1415: 1416: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1417: ( fputs ("\t.comm ", (FILE)), \ 1418: assemble_name ((FILE), (NAME)), \ 1419: fprintf ((FILE), ",%d\n", (SIZE))) 1420: 1421: /* This says how to output an assembler line 1422: to define a local common symbol. */ 1423: 1424: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ 1425: ( fputs ("\t.lcomm ", (FILE)), \ 1426: assemble_name ((FILE), (NAME)), \ 1427: fprintf ((FILE), ",%d\n", (SIZE))) 1428: 1429: 1430: /* The assembler's parentheses characters. */ 1431: #define ASM_OPEN_PAREN "(" 1432: #define ASM_CLOSE_PAREN ")" 1433: 1434: /* Target characters. */ 1435: #define TARGET_BELL 007 1436: #define TARGET_BS 010 1437: #define TARGET_TAB 011 1438: #define TARGET_NEWLINE 012 1439: #define TARGET_VT 013 1440: #define TARGET_FF 014 1441: #define TARGET_CR 015 1442: 1443: 1444: /* Only perform branch elimination (by making instructions conditional) if 1445: we're optimising. Otherwise it's of no use anyway. */ 1446: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1.1.1.2 root 1447: final_prescan_insn (INSN, OPVEC, NOPERANDS) 1.1 root 1448: 1449: /* Print operand X (an rtx) in assembler syntax to file FILE. 1450: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1451: For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1452: 1453: #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE) 1454: 1455: /* Print a memory address as an operand to reference that memory location. */ 1456: 1457: #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X) 1458: 1459: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1.1.1.3 ! root 1460: ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR)=='!' || (CHAR)=='@') 1.1 root 1461: 1462: 1463: extern struct rtx_def *sh_compare_op0; 1464: extern struct rtx_def *sh_compare_op1; 1465: extern struct rtx_def *prepare_scc_operands(); 1.1.1.3 ! root 1466: extern struct rtx_def *table_lab; ! 1467: 1.1 root 1468: 1.1.1.2 root 1469: extern enum attr_cpu sh_cpu; /* target cpu */ 1.1 root 1470: 1471: /* Declare functions defined in sh.c and used in templates. */ 1472: 1473: extern char *output_branch(); 1474: extern char *output_shift(); 1475: extern char *output_movedouble(); 1476: extern char *output_movepcrel(); 1.1.1.3 ! root 1477: extern char *output_jump_label_table(); ! 1478: extern char *output_far_jump(); ! 1479: 1.1 root 1480: 1.1.1.3 ! root 1481: #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) 1.1 root 1482: 1.1.1.3 ! root 1483: /* Generate calls to memcpy, memcmp and memset. */ 1.1.1.2 root 1484: 1.1.1.3 ! root 1485: #define TARGET_MEM_FUNCTIONS 1.1.1.2 root 1486: 1.1.1.3 ! root 1487: #define HANDLE_PRAGMA(finput) return handle_pragma (finput) 1.1.1.2 root 1488: 1.1.1.3 ! root 1489: /* Set when processing a function with pragma interrupt turned on. */ 1.1.1.2 root 1490: 1.1.1.3 ! root 1491: extern int pragma_interrupt; ! 1492: #define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16) 1.1.1.2 root 1493: 1.1.1.3 ! root 1494: char *max_si; ! 1495: char *max_hi; ! 1496: int max_count_si; ! 1497: int max_count_hi;
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