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1.1 ! root 1: ;;- Machine description the Hitachi SH ! 2: ;; Copyright (C) 1993 Free Software Foundation, Inc. ! 3: ;; Contributed by Steve Chamberlain ([email protected]) ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 2, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 22: ! 23: ! 24: ! 25: ;; ------------------------------------------------------------------------- ! 26: ;; Attributes ! 27: ;; ------------------------------------------------------------------------- ! 28: ! 29: (define_attr "type" "cbranch,ctable,jump,arith,other" ! 30: (const_string "other")) ! 31: ! 32: ; If a conditional branch destination is within -100..100 bytes away ! 33: ; from the instruction it can be 2 bytes long. Something in the ! 34: ; range -4000..4000 bytes can be 6 bytes long, all other conditional ! 35: ; branches are 8 bytes long. ! 36: ! 37: ; An unconditional jump which can reach forward or back 4k can be ! 38: ; 6 bytes long (including the delay slot). If it is too big, it ! 39: ; must be 8 bytes long. ! 40: ! 41: ; All other instructions are two bytes long by default. ! 42: ! 43: (define_attr "length" "" ! 44: (cond [(eq_attr "type" "cbranch") ! 45: (if_then_else (and (ge (minus (pc) (match_dup 0)) ! 46: (const_int -100)) ! 47: (le (minus (pc) (match_dup 0)) ! 48: (const_int 100))) ! 49: (const_int 2) ! 50: (if_then_else (and (ge (minus (pc) (match_dup 0)) ! 51: (const_int -4000)) ! 52: (le (minus (pc) (match_dup 0)) ! 53: (const_int 4000))) ! 54: (const_int 6) ! 55: (const_int 8))) ! 56: ! 57: (eq_attr "type" "jump") ! 58: (if_then_else (and (ge (minus (pc) (match_dup 0)) ! 59: (const_int -4000)) ! 60: (le (minus (pc) (match_dup 0)) ! 61: (const_int 4000))) ! 62: (const_int 4) ! 63: (const_int 6)) ! 64: ] (const_int 2))) ! 65: ! 66: ! 67: (define_attr "needs_delay_slot" "yes,no" ! 68: (cond [(eq_attr "type" "jump") (const_string "yes")] ! 69: (const_string "no"))) ! 70: ! 71: (define_attr "dump" "yes,no,must" (const_string "no")) ! 72: (define_attr "constneed" "yes,no" (const_string "no")) ! 73: (define_attr "smallestsize" "" (const_int 2)) ! 74: (define_attr "largestsize" "" (const_int 8)) ! 75: (define_attr "constantsize" "" (const_int 4)) ! 76: ! 77: (define_attr "in_delay_slot" "maybe,yes,no" ! 78: (cond [(eq_attr "type" "cbranch") (const_string "no") ! 79: (eq_attr "type" "jump") (const_string "no") ! 80: (eq_attr "length" "2") (const_string "yes") ! 81: (eq_attr "length" "4,6,8,10,12") (const_string "no") ! 82: ] (const_string "yes"))) ! 83: ! 84: ! 85: (define_delay (eq_attr "needs_delay_slot" "yes") ! 86: [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) ! 87: ! 88: ! 89: ! 90: ;; ------------------------------------------------------------------------- ! 91: ;; SImode signed integer comparisons ! 92: ;; ------------------------------------------------------------------------- ! 93: ! 94: (define_insn "" ! 95: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 96: (eq:SI (reg:SI 18) ! 97: (const_int 1)))] ! 98: "" ! 99: "movt %0 !movt1") ! 100: ! 101: (define_insn "" ! 102: [(set (reg:SI 18) (gt (match_operand:SI 0 "arith_reg_operand" "r") ! 103: (const_int 0)))] ! 104: "" ! 105: "cmp/pl %0") ! 106: ! 107: (define_insn "" ! 108: [(set (reg:SI 18) (ge (match_operand:SI 0 "arith_reg_operand" "r") ! 109: (const_int 0)))] ! 110: "" ! 111: "cmp/pz %0") ! 112: ! 113: (define_insn "cmpeqsi_t" ! 114: [(set (reg:SI 18) (eq (match_operand:SI 0 "arith_reg_operand" "r,z") ! 115: (match_operand:SI 1 "arith_operand" "r,I")))] ! 116: "" ! 117: "cmp/eq %1,%0") ! 118: ! 119: ! 120: (define_insn "cmpgtsi_t" ! 121: [(set (reg:SI 18) (gt (match_operand:SI 0 "arith_reg_operand" "r") ! 122: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 123: "" ! 124: "cmp/gt %1,%0") ! 125: ! 126: (define_insn "cmpgesi_t" ! 127: [(set (reg:SI 18) (ge (match_operand:SI 0 "arith_reg_operand" "r") ! 128: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 129: "" ! 130: "cmp/ge %1,%0") ! 131: ! 132: (define_insn "cmpltsi_t" ! 133: [(set (reg:SI 18) (lt (match_operand:SI 0 "arith_reg_operand" "r") ! 134: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 135: "" ! 136: "cmp/gt %0,%1") ! 137: ! 138: (define_insn "cmplesi_t" ! 139: [(set (reg:SI 18) (le (match_operand:SI 0 "arith_reg_operand" "r") ! 140: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 141: "" ! 142: "cmp/ge %0,%1") ! 143: ! 144: ! 145: ;; ------------------------------------------------------------------------- ! 146: ;; SImode unsigned integer comparisons ! 147: ;; ------------------------------------------------------------------------- ! 148: ! 149: (define_insn "cmpgeusi_t" ! 150: [(set (reg:SI 18) (geu (match_operand:SI 0 "arith_reg_operand" "r") ! 151: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 152: "" ! 153: "cmp/hs %1,%0") ! 154: ! 155: (define_insn "cmpgtusi_t" ! 156: [(set (reg:SI 18) (gtu (match_operand:SI 0 "arith_reg_operand" "r") ! 157: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 158: "" ! 159: "cmp/hi %1,%0") ! 160: ! 161: (define_insn "cmpleusi_t" ! 162: [(set (reg:SI 18) (leu (match_operand:SI 0 "arith_reg_operand" "r") ! 163: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 164: "" ! 165: "cmp/hs %0,%1") ! 166: ! 167: (define_insn "cmpltusi_t" ! 168: [(set (reg:SI 18) (ltu (match_operand:SI 0 "arith_reg_operand" "r") ! 169: (match_operand:SI 1 "arith_reg_operand" "r")))] ! 170: "" ! 171: "cmp/hi %0,%1") ! 172: ! 173: ;; We save the compare operands in the cmpxx patterns and use them when ! 174: ;; we generate the branch. ! 175: ! 176: (define_expand "cmpsi" ! 177: [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_reg_operand" "") ! 178: (match_operand:SI 1 "arith_reg_operand" "")))] ! 179: "" ! 180: " ! 181: { sh_compare_op0 = operands[0]; ! 182: sh_compare_op1 = operands[1]; ! 183: DONE; ! 184: }") ! 185: ! 186: ! 187: ;; ------------------------------------------------------------------------- ! 188: ;; Addition instructions ! 189: ;; ------------------------------------------------------------------------- ! 190: ! 191: (define_insn "adddi3" ! 192: [(set (match_operand:DI 0 "arith_reg_operand" "=&r") ! 193: (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0") ! 194: (match_operand:DI 2 "arith_reg_operand" "r"))) ! 195: (clobber (reg:SI 18))] ! 196: "" ! 197: "clrt\;addc %R2,%R0\;addc %2,%0" ! 198: [(set_attr "length" "6") ! 199: (set_attr "in_delay_slot" "no") ! 200: (set_attr "type" "arith")]) ! 201: ! 202: ! 203: (define_insn "addsi3_i" ! 204: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 205: (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0") ! 206: (match_operand:SI 2 "arith_operand" "rI")))] ! 207: "" ! 208: "add %2,%0" ! 209: [(set_attr "length" "2") ! 210: (set_attr "type" "arith")]) ! 211: ! 212: (define_expand "addsi3" ! 213: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 214: (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0") ! 215: (match_operand:SI 2 "arith_operand" "rI")))] ! 216: "" ! 217: "") ! 218: ! 219: ! 220: ;; ------------------------------------------------------------------------- ! 221: ;; Subtraction instructions ! 222: ;; ------------------------------------------------------------------------- ! 223: ! 224: (define_insn "subdi3" ! 225: [(set (match_operand:DI 0 "arith_reg_operand" "=&r") ! 226: (minus:DI (match_operand:DI 1 "arith_reg_operand" "0") ! 227: (match_operand:DI 2 "arith_reg_operand" "r"))) ! 228: (clobber (reg:SI 18))] ! 229: "" ! 230: "clrt\;subc %R2,%R0\;subc %2,%0" ! 231: [(set_attr "length" "6") ! 232: (set_attr "in_delay_slot" "no") ! 233: (set_attr "type" "arith")]) ! 234: ! 235: (define_insn "subsi3" ! 236: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 237: (minus:SI (match_operand:SI 1 "arith_reg_operand" "0") ! 238: (match_operand:SI 2 "arith_reg_operand" "r")))] ! 239: "" ! 240: "sub %2,%0" ! 241: [(set_attr "type" "arith")]) ! 242: ! 243: ! 244: ;; ------------------------------------------------------------------------- ! 245: ;; Multiplication instructions ! 246: ;; ------------------------------------------------------------------------- ! 247: ! 248: ! 249: (define_insn "" ! 250: [(set (reg:SI 21) ! 251: (mult:SI (zero_extend:SI ! 252: (match_operand:HI 1 "arith_reg_operand" "r")) ! 253: (zero_extend:SI ! 254: (match_operand:HI 2 "arith_reg_operand" "r"))))] ! 255: "" ! 256: "mulu %2,%1") ! 257: ! 258: (define_insn "" ! 259: [(set (reg:SI 21) ! 260: (mult:SI (sign_extend:SI ! 261: (match_operand:HI 1 "arith_reg_operand" "r")) ! 262: (sign_extend:SI ! 263: (match_operand:HI 2 "arith_reg_operand" "r"))))] ! 264: "" ! 265: "muls %2,%1") ! 266: ! 267: (define_expand "mulhisi3" ! 268: [(set (reg:SI 21) ! 269: (mult:SI (sign_extend:SI ! 270: (match_operand:HI 1 "arith_reg_operand" "r")) ! 271: (sign_extend:SI ! 272: (match_operand:HI 2 "arith_reg_operand" "r")))) ! 273: (set (match_operand:SI 0 "arith_reg_operand" "=r") ! 274: (reg:SI 21))] ! 275: "" ! 276: "") ! 277: ! 278: (define_expand "umulhisi3" ! 279: [(set (reg:SI 21) ! 280: (mult:SI (zero_extend:SI ! 281: (match_operand:HI 1 "arith_reg_operand" "r")) ! 282: (zero_extend:SI ! 283: (match_operand:HI 2 "arith_reg_operand" "r")))) ! 284: (set (match_operand:SI 0 "arith_reg_operand" "=r") ! 285: (reg:SI 21))] ! 286: "" ! 287: "") ! 288: ! 289: (define_insn "" ! 290: [(set (reg:SI 21) ! 291: (mult:SI (match_operand:SI 1 "arith_reg_operand" "r") ! 292: (match_operand:SI 2 "arith_reg_operand" "r")))] ! 293: "TARGET_HAS_MULSI3" ! 294: "muls.l %2,%1") ! 295: ! 296: (define_expand "mulsi3" ! 297: [(set (reg:SI 21) ! 298: (mult:SI (match_operand:SI 1 "arith_reg_operand" "r") ! 299: (match_operand:SI 2 "arith_reg_operand" "r"))) ! 300: (set (match_operand:SI 0 "arith_reg_operand" "=r") ! 301: (reg:SI 20))] ! 302: "TARGET_HAS_MULSI3" ! 303: "") ! 304: ! 305: (define_insn "" ! 306: [(set (reg:DI 20) ! 307: (mult:DI (sign_extend:DI ! 308: (match_operand:SI 1 "arith_reg_operand" "r")) ! 309: (sign_extend:DI ! 310: (match_operand:SI 2 "arith_reg_operand" "r"))))] ! 311: "TARGET_HAS_MULSI3" ! 312: "dmuls.l %2,%1") ! 313: ! 314: (define_expand "mulsidi3" ! 315: [(set (reg:DI 20) ! 316: (mult:DI (sign_extend:DI ! 317: (match_operand:SI 1 "arith_reg_operand" "r")) ! 318: (sign_extend:DI ! 319: (match_operand:SI 2 "arith_reg_operand" "r")))) ! 320: (set (match_operand:DI 0 "arith_reg_operand" "=r") ! 321: (reg:DI 20))] ! 322: "TARGET_HAS_MULSI3" ! 323: "") ! 324: ! 325: (define_insn "" ! 326: [(set (reg:DI 20) ! 327: (mult:DI (zero_extend:DI ! 328: (match_operand:SI 1 "arith_reg_operand" "r")) ! 329: (zero_extend:DI ! 330: (match_operand:SI 2 "arith_reg_operand" "r"))))] ! 331: "TARGET_HAS_MULSI3" ! 332: "dmulu.l %2,%1") ! 333: ! 334: (define_expand "umulsidi3" ! 335: [(set (reg:DI 20) ! 336: (mult:DI (zero_extend:DI ! 337: (match_operand:SI 1 "arith_reg_operand" "r")) ! 338: (zero_extend:DI ! 339: (match_operand:SI 2 "arith_reg_operand" "r")))) ! 340: (set (match_operand:DI 0 "arith_reg_operand" "=r") ! 341: (reg:DI 20))] ! 342: "TARGET_HAS_MULSI3" ! 343: "") ! 344: ! 345: ;; ------------------------------------------------------------------------- ! 346: ;; Logical operations ! 347: ;; ------------------------------------------------------------------------- ! 348: ! 349: (define_insn "andsi3" ! 350: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z") ! 351: (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") ! 352: (match_operand:SI 2 "logical_operand" "r,L")))] ! 353: "" ! 354: "and %2,%0" ! 355: [(set_attr "type" "arith")]) ! 356: ! 357: (define_insn "iorsi3" ! 358: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z") ! 359: (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") ! 360: (match_operand:SI 2 "logical_operand" "r,L")))] ! 361: "" ! 362: "or %2,%0") ! 363: ! 364: (define_insn "xorsi3" ! 365: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z") ! 366: (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") ! 367: (match_operand:SI 2 "logical_operand" "r,L")))] ! 368: "" ! 369: "xor %2,%0" ! 370: [(set_attr "type" "arith")]) ! 371: ! 372: ! 373: ;; ------------------------------------------------------------------------- ! 374: ;; Shifts and rotates ! 375: ;; ------------------------------------------------------------------------- ! 376: ! 377: (define_insn "ashlsi3_k" ! 378: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r") ! 379: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0") ! 380: (match_operand:SI 2 "immediate_operand" "L,n")))] ! 381: "" ! 382: "*return output_shift(\"shll\", operands[0], operands[2]);" ! 383: [(set_attr "length" "2,12") ! 384: (set_attr "in_delay_slot" "yes,no") ! 385: (set_attr "type" "arith")]) ! 386: ! 387: (define_expand "ashlsi3" ! 388: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 389: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "") ! 390: (match_operand:SI 2 "immediate_operand" "")))] ! 391: "" ! 392: "if (!ok_shift_value(operands[2])) FAIL;") ! 393: ! 394: (define_insn "ashrsi3_k" ! 395: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 396: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") ! 397: (const_int 1)))] ! 398: "" ! 399: "shar %0" ! 400: [(set_attr "type" "arith")]) ! 401: ! 402: (define_expand "ashrsi3" ! 403: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 404: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r") ! 405: (match_operand:SI 2 "nonmemory_operand" "M")))] ! 406: "" ! 407: " ! 408: { ! 409: if (GET_CODE (operands[2]) != CONST_INT || ! 410: INTVAL (operands[2]) != 1) FAIL; ! 411: } ! 412: ") ! 413: ! 414: (define_insn "lshrsi3_k" ! 415: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 416: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") ! 417: (match_operand:SI 2 "immediate_operand" "L")))] ! 418: "" ! 419: "* return output_shift (\"shlr\", operands[0], operands[2]);" ! 420: [(set_attr "length" "12") ! 421: (set_attr "in_delay_slot" "no") ! 422: (set_attr "type" "arith")]) ! 423: ! 424: (define_expand "lshrsi3" ! 425: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 426: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") ! 427: (match_operand:SI 2 "nonmemory_operand" "")))] ! 428: "" ! 429: "if (!ok_shift_value (operands[2])) FAIL; ") ! 430: ! 431: (define_insn "ashldi3_k" ! 432: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 433: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0") ! 434: (match_operand:DI 2 "immediate_operand" "I"))) ! 435: (clobber (reg:SI 18))] ! 436: "" ! 437: "shll %R0\;rotcl %0" ! 438: [(set_attr "length" "4")]) ! 439: ! 440: (define_expand "ashldi3" ! 441: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "") ! 442: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "") ! 443: (match_operand:DI 2 "immediate_operand" ""))) ! 444: (clobber (reg:SI 18))])] ! 445: ! 446: "" ! 447: "{ if (GET_CODE (operands[2]) != CONST_INT ! 448: || INTVAL (operands[2]) != 1) FAIL;} ") ! 449: ! 450: (define_insn "lshrdi3_k" ! 451: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 452: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") ! 453: (match_operand:DI 2 "immediate_operand" "I"))) ! 454: (clobber (reg:SI 18))] ! 455: "" ! 456: "shlr %0\;rotcr %R0" ! 457: [(set_attr "length" "4")]) ! 458: ! 459: (define_expand "lshrdi3" ! 460: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "") ! 461: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") ! 462: (match_operand:DI 2 "immediate_operand" ""))) ! 463: (clobber (reg:SI 18))])] ! 464: "" ! 465: "{ if (GET_CODE (operands[2]) != CONST_INT ! 466: || INTVAL (operands[2]) != 1) FAIL;} ") ! 467: ! 468: (define_insn "ashrdi3_k" ! 469: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 470: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") ! 471: (match_operand:DI 2 "immediate_operand" ""))) ! 472: (clobber (reg:SI 18))] ! 473: "" ! 474: "shar %0\;rotcr %R0" ! 475: [(set_attr "length" "4")]) ! 476: ! 477: (define_expand "ashrdi3" ! 478: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "") ! 479: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") ! 480: (match_operand:DI 2 "immediate_operand" ""))) ! 481: (clobber (reg:SI 18))])] ! 482: "" ! 483: "{ if (GET_CODE (operands[2]) != CONST_INT ! 484: || INTVAL (operands[2]) != 1) FAIL; } ") ! 485: ! 486: ! 487: ! 488: ;; ------------------------------------------------------------------------- ! 489: ;; Unary arithmetic ! 490: ;; ------------------------------------------------------------------------- ! 491: ! 492: (define_insn "negdi2" ! 493: [(set (match_operand:DI 0 "arith_reg_operand" "=&r") ! 494: (neg:DI (match_operand:DI 1 "arith_reg_operand" "0"))) ! 495: (clobber (reg:SI 18))] ! 496: "" ! 497: "clrt\;negc %R1,%R0\;negc %1,%0" ! 498: [(set_attr "length" "6") ! 499: (set_attr "type" "arith")]) ! 500: ! 501: (define_insn "negsi2" ! 502: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 503: (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))] ! 504: "" ! 505: "neg %1,%0" ! 506: [(set_attr "type" "arith")]) ! 507: ! 508: (define_insn "one_cmplsi2" ! 509: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 510: (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))] ! 511: "" ! 512: "not %1,%0" ! 513: [ (set_attr "type" "arith")]) ! 514: ! 515: ! 516: ;; ------------------------------------------------------------------------- ! 517: ;; Zero extension instructions ! 518: ;; ------------------------------------------------------------------------- ! 519: ! 520: (define_insn "zero_extendhisi2" ! 521: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 522: (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))] ! 523: "" ! 524: "extu.w %1,%0" ! 525: [(set_attr "type" "arith")]) ! 526: ! 527: (define_insn "zero_extendqisi2" ! 528: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 529: (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))] ! 530: "" ! 531: "extu.b %1,%0" ! 532: [(set_attr "type" "arith")]) ! 533: ! 534: (define_insn "zero_extendqihi2" ! 535: [(set (match_operand:HI 0 "arith_reg_operand" "=r") ! 536: (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] ! 537: "" ! 538: "extu.b %1,%0" ! 539: [(set_attr "type" "arith")]) ! 540: ! 541: ! 542: ;; ------------------------------------------------------------------------- ! 543: ;; Sign extension instructions ! 544: ;; ------------------------------------------------------------------------- ! 545: ! 546: (define_insn "extendsidi2" ! 547: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 548: (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "0")))] ! 549: "" ! 550: "mov %1,%0\;shll %0\;subc %0,%0" ! 551: [(set_attr "length" "6")]) ! 552: ! 553: (define_insn "extendhisi2" ! 554: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 555: (sign_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))] ! 556: "" ! 557: "exts.w %1,%0") ! 558: ! 559: (define_insn "extendqisi2" ! 560: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 561: (sign_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))] ! 562: "" ! 563: "exts.b %1,%0") ! 564: ! 565: (define_insn "extendqihi2" ! 566: [(set (match_operand:HI 0 "arith_reg_operand" "=r") ! 567: (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] ! 568: "" ! 569: "exts.b %1,%0") ! 570: ! 571: ! 572: ;; ------------------------------------------------------------------------- ! 573: ;; Move instructions ! 574: ;; ------------------------------------------------------------------------- ! 575: ! 576: (define_insn "" ! 577: [(set (match_operand:SI 0 "push_operand" "=<") ! 578: (match_operand:SI 1 "arith_reg_operand" "r"))] ! 579: "" ! 580: "mov.l %1,%0") ! 581: ! 582: (define_insn "movsi_pcrel" ! 583: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 584: (match_operand:SI 1 "hard_immediate_operand" "i"))] ! 585: "" ! 586: "* return output_movepcrel (insn, operands, SImode);" ! 587: [(set_attr "length" "2") ! 588: (set_attr "in_delay_slot" "no") ! 589: (set_attr "constneed" "yes") ! 590: (set_attr "smallestsize" "2") ! 591: (set_attr "largestsize" "8")]) ! 592: ! 593: (define_insn "movsi_i" ! 594: [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,l,r,r,r,t") ! 595: (match_operand:SI 1 "general_operand" "r,I,m,r,r,l,t,x,r"))] ! 596: "" ! 597: "@ ! 598: mov %1,%0 ! 599: mov %1,%0 ! 600: mov.l %1,%0 ! 601: mov.l %1,%0 ! 602: mov %1,%0 ! 603: mov %1,%0 ! 604: movt %0 ! 605: sts %1,%0 ! 606: tst %1,%1\;bt T%*\;bra F%*\;sett\;T%*:clrt\;F%*:%^" ! 607: [(set_attr "length" "2,2,2,2,2,2,2,2,10")]) ! 608: ! 609: (define_expand "movsi" ! 610: [(set (match_operand:SI 0 "general_operand" "") ! 611: (match_operand:SI 1 "general_operand" ""))] ! 612: "" ! 613: "{ prepare_move_operands(operands, SImode); } ") ! 614: ! 615: (define_insn "movqi_i" ! 616: [(set (match_operand:QI 0 "general_operand" "=r,r,z,m,r,m,r,r") ! 617: (match_operand:QI 1 "general_operand" "r,n,m,z,m,r,x,t"))] ! 618: "" ! 619: "@ ! 620: mov %1,%0 ! 621: mov %1,%0 ! 622: mov.b %1,%0 !4 ! 623: mov.b %1,%0 !5 ! 624: mov.b %1,%0 !6 ! 625: mov.b %1,%0 ! 7 ! 626: sts %1,%0 ! 627: movt %0") ! 628: ! 629: (define_expand "movqi" ! 630: [(set (match_operand:QI 0 "general_operand" "") ! 631: (match_operand:QI 1 "general_operand" ""))] ! 632: "" ! 633: "prepare_move_operands(operands, QImode);") ! 634: ! 635: (define_insn "movhi_pcrel" ! 636: [(set (match_operand:HI 0 "arith_reg_operand" "=r") ! 637: (match_operand:HI 1 "hard_immediate_operand" "i"))] ! 638: "" ! 639: "* return output_movepcrel (insn, operands, SImode);" ! 640: [(set_attr "length" "2") ! 641: (set_attr "in_delay_slot" "no") ! 642: (set_attr "constneed" "yes") ! 643: (set_attr "smallestsize" "2") ! 644: (set_attr "largestsize" "8")]) ! 645: ! 646: (define_insn "movhi_i" ! 647: [(set (match_operand:HI 0 "general_operand" "=r,r,m,z,m,r,r") ! 648: (match_operand:HI 1 "general_operand" "rI,m,r,m,z,x,t"))] ! 649: "" ! 650: "@ ! 651: mov %1,%0 ! 652: mov.w %1,%0 ! 653: mov.w %1,%0 ! 654: mov.w %1,%0 ! 655: mov.w %1,%0 ! 656: sts %1,%0 ! 657: movt %0") ! 658: ! 659: (define_expand "movhi" ! 660: [(set (match_operand:HI 0 "general_operand" "") ! 661: (match_operand:HI 1 "general_operand" ""))] ! 662: "" ! 663: "prepare_move_operands (operands, HImode);") ! 664: ! 665: (define_insn "" ! 666: [(set (match_operand:DI 0 "push_operand" "=<") ! 667: (match_operand:DI 1 "arith_reg_operand" "r"))] ! 668: "" ! 669: "mov.l %R1,%0\;mov.l %1,%0" ! 670: [(set_attr "length" "4")]) ! 671: ! 672: (define_insn "movdi_pcrel" ! 673: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 674: (match_operand:DI 1 "hard_immediate_operand" "i"))] ! 675: "" ! 676: "* return output_movepcrel (insn, operands, DImode);" ! 677: [(set_attr "length" "4") ! 678: (set_attr "in_delay_slot" "no") ! 679: (set_attr "constneed" "yes") ! 680: (set_attr "smallestsize" "4") ! 681: (set_attr "constantsize" "8") ! 682: (set_attr "largestsize" "18")]) ! 683: ! 684: (define_insn "movdi_k" ! 685: [(set (match_operand:DI 0 "general_operand" "=r,r,m,r,r,m,r") ! 686: (match_operand:DI 1 "general_operand" "r,m,r,I,m,r,x"))] ! 687: "" ! 688: "* return output_movedouble(operands, DImode);" ! 689: [(set_attr "length" "4")]) ! 690: ! 691: (define_expand "movdi" ! 692: [(set (match_operand:DI 0 "general_operand" "") ! 693: (match_operand:DI 1 "general_operand" ""))] ! 694: "" ! 695: "prepare_move_operands (operands, DImode);") ! 696: ! 697: (define_insn "" ! 698: [(set (match_operand:DF 0 "push_operand" "=<") ! 699: (match_operand:DF 1 "arith_reg_operand" "r"))] ! 700: "" ! 701: "mov.l %R1,%0\;mov.l %1,%0" ! 702: [(set_attr "length" "4")]) ! 703: ! 704: (define_insn "movdf_pcrel" ! 705: [(set (match_operand:DF 0 "arith_reg_operand" "=r") ! 706: (match_operand:DF 1 "hard_immediate_operand" "i"))] ! 707: "" ! 708: "* return output_movepcrel (insn, operands, DFmode);" ! 709: [(set_attr "length" "4") ! 710: (set_attr "in_delay_slot" "no") ! 711: (set_attr "constneed" "yes") ! 712: (set_attr "smallestsize" "4") ! 713: (set_attr "constantsize" "8") ! 714: (set_attr "largestsize" "18")]) ! 715: ! 716: (define_insn "movdf_k" ! 717: [(set (match_operand:DF 0 "general_operand" "=r,r,m") ! 718: (match_operand:DF 1 "general_operand" "r,m,r"))] ! 719: "" ! 720: "* return output_movedouble(operands, DFmode);" ! 721: [(set_attr "length" "4")]) ! 722: ! 723: (define_expand "movdf" ! 724: [(set (match_operand:DF 0 "general_operand" "") ! 725: (match_operand:DF 1 "general_operand" ""))] ! 726: "" ! 727: "prepare_move_operands(operands, DFmode);") ! 728: ! 729: (define_insn "" ! 730: [(set (match_operand:SF 0 "push_operand" "=<") ! 731: (match_operand:SF 1 "arith_reg_operand" "r"))] ! 732: "" ! 733: "mov.l %1,%0") ! 734: ! 735: (define_insn "movsf_pcrel" ! 736: [(set (match_operand:SF 0 "arith_reg_operand" "=r") ! 737: (match_operand:SF 1 "hard_immediate_operand" "i"))] ! 738: "" ! 739: "* return output_movepcrel (insn, operands, SFmode);" ! 740: [(set_attr "length" "2") ! 741: (set_attr "in_delay_slot" "no") ! 742: (set_attr "constneed" "yes") ! 743: (set_attr "smallestsize" "2") ! 744: (set_attr "largestsize" "8")]) ! 745: ! 746: (define_insn "movsf_i" ! 747: [(set (match_operand:SF 0 "general_operand" "=r,r,r,m,l,r,m,r") ! 748: (match_operand:SF 1 "general_operand" "r,I,m,r,r,l,r,m"))] ! 749: "" ! 750: "@ ! 751: mov %1,%0 ! 752: mov %1,%0 ! 753: mov.l %1,%0 ! 754: mov.l %1,%0 ! 755: mov %1,%0 ! 756: mov %1,%0 ! 757: mov %1,%0 ! 758: mov %1,%0") ! 759: ! 760: (define_expand "movsf" ! 761: [(set (match_operand:SF 0 "general_operand" "") ! 762: (match_operand:SF 1 "general_operand" ""))] ! 763: "" ! 764: "prepare_move_operands(operands, SFmode);") ! 765: ! 766: ! 767: ;; ------------------------------------------------------------------------ ! 768: ;; Define the real conditional branch instructions. ! 769: ;; ------------------------------------------------------------------------ ! 770: ! 771: (define_insn "branch_true" ! 772: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1)) ! 773: (label_ref (match_operand 0 "" "")) ! 774: (pc)))] ! 775: "" ! 776: "* return output_branch (1, insn);" ! 777: [(set_attr "type" "cbranch")]) ! 778: ! 779: (define_insn "branch_false" ! 780: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1)) ! 781: (label_ref (match_operand 0 "" "")) ! 782: (pc)))] ! 783: "" ! 784: "* return output_branch (0, insn);" ! 785: [(set_attr "type" "cbranch")]) ! 786: ! 787: (define_insn "inverse_branch_true" ! 788: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1)) ! 789: (pc) ! 790: (label_ref (match_operand 0 "" ""))))] ! 791: "" ! 792: "* return output_branch (0, insn);" ! 793: [(set_attr "type" "cbranch")]) ! 794: ! 795: (define_insn "inverse_branch_false" ! 796: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1)) ! 797: (pc) ! 798: (label_ref (match_operand 0 "" ""))))] ! 799: "" ! 800: "* return output_branch (1, insn);" ! 801: [(set_attr "type" "cbranch")]) ! 802: ! 803: ! 804: ;; Conditional branch insns ! 805: ! 806: (define_expand "beq" ! 807: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2))) ! 808: (set (pc) ! 809: (if_then_else (eq (reg:SI 18) ! 810: (const_int 1)) ! 811: (label_ref (match_operand 0 "" "")) ! 812: (pc)))] ! 813: "" ! 814: " ! 815: { ! 816: operands[1] = sh_compare_op0; ! 817: operands[2] = sh_compare_op1; ! 818: }") ! 819: ! 820: ! 821: ; There is no bne compare, so we reverse the branch arms. ! 822: ! 823: (define_expand "bne" ! 824: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2))) ! 825: (set (pc) ! 826: (if_then_else (eq (reg:SI 18) ! 827: (const_int 1)) ! 828: (pc) ! 829: (label_ref (match_operand 0 "" ""))))] ! 830: "" ! 831: " ! 832: { ! 833: operands[1] = sh_compare_op0; ! 834: operands[2] = sh_compare_op1; ! 835: }") ! 836: ! 837: (define_expand "bgt" ! 838: [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2))) ! 839: (set (pc) ! 840: (if_then_else (eq (reg:SI 18) ! 841: (const_int 1)) ! 842: (label_ref (match_operand 0 "" "")) ! 843: (pc)))] ! 844: "" ! 845: " ! 846: { ! 847: operands[1] = sh_compare_op0; ! 848: operands[2] = sh_compare_op1; ! 849: }") ! 850: ! 851: (define_expand "blt" ! 852: [(set (reg:SI 18) (lt:SI (match_dup 1) (match_dup 2))) ! 853: (set (pc) ! 854: (if_then_else (eq (reg:SI 18) ! 855: (const_int 1)) ! 856: (label_ref (match_operand 0 "" "")) ! 857: (pc)))] ! 858: "" ! 859: " ! 860: { ! 861: operands[1] = sh_compare_op0; ! 862: operands[2] = sh_compare_op1; ! 863: }") ! 864: ! 865: (define_expand "ble" ! 866: [(set (reg:SI 18) (le:SI (match_dup 1) (match_dup 2))) ! 867: (set (pc) ! 868: (if_then_else (eq (reg:SI 18) ! 869: (const_int 1)) ! 870: (label_ref (match_operand 0 "" "")) ! 871: (pc)))] ! 872: "" ! 873: " ! 874: { ! 875: operands[1] = sh_compare_op0; ! 876: operands[2] = sh_compare_op1; ! 877: }") ! 878: ! 879: (define_expand "bge" ! 880: [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2))) ! 881: (set (pc) ! 882: (if_then_else (eq (reg:SI 18) ! 883: (const_int 1)) ! 884: (label_ref (match_operand 0 "" "")) ! 885: (pc)))] ! 886: "" ! 887: " ! 888: { ! 889: operands[1] = sh_compare_op0; ! 890: operands[2] = sh_compare_op1; ! 891: }") ! 892: ! 893: (define_expand "bgtu" ! 894: [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2))) ! 895: (set (pc) ! 896: (if_then_else (eq (reg:SI 18) ! 897: (const_int 1)) ! 898: (label_ref (match_operand 0 "" "")) ! 899: (pc)))] ! 900: "" ! 901: " ! 902: { ! 903: operands[1] = sh_compare_op0; ! 904: operands[2] = sh_compare_op1; ! 905: }") ! 906: ! 907: (define_expand "bltu" ! 908: [(set (reg:SI 18) (ltu:SI (match_dup 1) (match_dup 2))) ! 909: (set (pc) ! 910: (if_then_else (eq (reg:SI 18) ! 911: (const_int 1)) ! 912: (label_ref (match_operand 0 "" "")) ! 913: (pc)))] ! 914: "" ! 915: " ! 916: { ! 917: operands[1] = sh_compare_op0; ! 918: operands[2] = sh_compare_op1; ! 919: }") ! 920: ! 921: (define_expand "bgeu" ! 922: [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2))) ! 923: (set (pc) ! 924: (if_then_else (eq (reg:SI 18) ! 925: (const_int 1)) ! 926: (label_ref (match_operand 0 "" "")) ! 927: (pc)))] ! 928: "" ! 929: " ! 930: { ! 931: operands[1] = sh_compare_op0; ! 932: operands[2] = sh_compare_op1; ! 933: }") ! 934: ! 935: (define_expand "bleu" ! 936: [(set (reg:SI 18) (leu:SI (match_dup 1) (match_dup 2))) ! 937: (set (pc) ! 938: (if_then_else (eq (reg:SI 18) ! 939: (const_int 1)) ! 940: (label_ref (match_operand 0 "" "")) ! 941: (pc)))] ! 942: "" ! 943: " ! 944: { ! 945: operands[1] = sh_compare_op0; ! 946: operands[2] = sh_compare_op1; ! 947: }") ! 948: ! 949: ! 950: ;; ------------------------------------------------------------------------ ! 951: ;; Jump and linkage insns ! 952: ;; ------------------------------------------------------------------------ ! 953: ! 954: (define_insn "jump_real" ! 955: [(set (pc) ! 956: (label_ref (match_operand 0 "" "")))] ! 957: "" ! 958: "* ! 959: { ! 960: if (get_attr_length(insn) == 6) ! 961: { ! 962: return \"mov.l %I0,r13\;jmp @r13%#\"; ! 963: } ! 964: else ! 965: { ! 966: return \"bra %l0%#\"; ! 967: } ! 968: }" ! 969: [(set_attr "type" "jump") ! 970: (set_attr "needs_delay_slot" "yes")]) ! 971: ! 972: (define_expand "jump" ! 973: [(set (pc) (label_ref (match_operand 0 "" "")))] ! 974: "" ! 975: " ! 976: { ! 977: emit_insn(gen_jump_real(operand0)); ! 978: DONE; ! 979: } ! 980: ") ! 981: ! 982: (define_insn "calli" ! 983: [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) ! 984: (match_operand 1 "" "")) ! 985: (clobber (reg:SI 17))] ! 986: "" ! 987: "jsr @%0%#" ! 988: [(set_attr "needs_delay_slot" "yes") ! 989: (set_attr "in_delay_slot" "no") ! 990: (set_attr "length" "4")]) ! 991: ! 992: (define_insn "call_valuei" ! 993: [(set (match_operand 0 "" "=rf") ! 994: (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) ! 995: (match_operand 2 "" ""))) ! 996: (clobber (reg:SI 17))] ! 997: "" ! 998: "jsr @%1%#" ! 999: [(set_attr "needs_delay_slot" "yes") ! 1000: (set_attr "in_delay_slot" "no") ! 1001: (set_attr "length" "4")]) ! 1002: ! 1003: (define_expand "call" ! 1004: [(parallel[(call (match_operand 0 "arith_reg_operand" "o") ! 1005: (match_operand 1 "" "")) ! 1006: (clobber (reg:SI 17))])] ! 1007: "" ! 1008: " ! 1009: { ! 1010: if (GET_CODE (operands[0]) == MEM) ! 1011: { ! 1012: operands[0] ! 1013: = gen_rtx(MEM,GET_MODE (operands[0]), ! 1014: force_reg (Pmode, ! 1015: XEXP (operands[0], 0))); ! 1016: } ! 1017: }") ! 1018: ! 1019: (define_expand "call_value" ! 1020: [(parallel[(set (match_operand 0 "" "=rf") ! 1021: (call (match_operand 1 "arith_reg_operand" "o") ! 1022: (match_operand 2 "" ""))) ! 1023: (clobber (reg:SI 17))])] ! 1024: "" ! 1025: " ! 1026: { ! 1027: if (GET_CODE (operands[1]) == MEM) ! 1028: { ! 1029: operands[1] ! 1030: = gen_rtx (MEM, GET_MODE (operands[1]), ! 1031: force_reg (Pmode, ! 1032: XEXP (operands[1], 0))); ! 1033: } ! 1034: }") ! 1035: ! 1036: (define_insn "indirect_jump" ! 1037: [(set (pc) ! 1038: (match_operand:SI 0 "arith_reg_operand" "r"))] ! 1039: "" ! 1040: "jmp @%0" ! 1041: [(set_attr "needs_delay_slot" "yes") ! 1042: (set_attr "in_delay_slot" "no") ! 1043: (set_attr "length" "4")]) ! 1044: ! 1045: ! 1046: ! 1047: ;; ------------------------------------------------------------------------ ! 1048: ;; Misc insns ! 1049: ;; ------------------------------------------------------------------------ ! 1050: ! 1051: ! 1052: (define_insn "nop" ! 1053: [(const_int 0)] ! 1054: "" ! 1055: "or r0,r0") ! 1056: ! 1057: (define_insn "tablejump" ! 1058: [(set (pc) ! 1059: (match_operand:SI 0 "arith_reg_operand" "r")) ! 1060: (use (label_ref (match_operand 1 "" "")))] ! 1061: "" ! 1062: "!table jump\;jmp @%0\;or r0,r0\;%!" ! 1063: [(set_attr "needs_delay_slot" "no") ! 1064: (set_attr "in_delay_slot" "no") ! 1065: (set_attr "type" "jump") ! 1066: (set_attr "dump" "no")]) ! 1067: ! 1068: ;; ------------------------------------------------------------------------ ! 1069: ;; Scc instructions ! 1070: ;; ------------------------------------------------------------------------ ! 1071: ! 1072: (define_insn "" ! 1073: [(set (match_operand:SI 0 "arith_reg_operand" "=r") ! 1074: (eq (reg:SI 18) (const_int 1)))] ! 1075: "" ! 1076: "movt %0 ! ") ! 1077: ! 1078: (define_expand "seq" ! 1079: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1080: (match_dup 1))] ! 1081: "" ! 1082: "operands[1] = prepare_scc_operands (EQ);") ! 1083: ! 1084: (define_expand "slt" ! 1085: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1086: (match_dup 1))] ! 1087: "" ! 1088: "operands[1] = prepare_scc_operands (LT);") ! 1089: ! 1090: (define_expand "sle" ! 1091: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1092: (match_dup 1))] ! 1093: "" ! 1094: "operands[1] = prepare_scc_operands (LE);") ! 1095: ! 1096: (define_expand "sgt" ! 1097: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1098: (match_dup 1))] ! 1099: "" ! 1100: "operands[1] = prepare_scc_operands (GT);") ! 1101: ! 1102: (define_expand "sge" ! 1103: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1104: (match_dup 1))] ! 1105: "" ! 1106: "operands[1] = prepare_scc_operands (GE);") ! 1107: ! 1108: (define_expand "sgtu" ! 1109: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1110: (match_dup 1))] ! 1111: "" ! 1112: "operands[1] = prepare_scc_operands (GTU);") ! 1113: ! 1114: (define_expand "sltu" ! 1115: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1116: (match_dup 1))] ! 1117: "" ! 1118: "operands[1] = prepare_scc_operands (LTU);") ! 1119: ! 1120: (define_expand "sleu" ! 1121: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1122: (match_dup 1))] ! 1123: "" ! 1124: "operands[1] = prepare_scc_operands (LEU);") ! 1125: ! 1126: (define_expand "sgeu" ! 1127: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1128: (match_dup 1))] ! 1129: "" ! 1130: "operands[1] = prepare_scc_operands (GEU);") ! 1131: ! 1132: (define_expand "sne" ! 1133: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1134: (match_dup 1)) ! 1135: (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))] ! 1136: "" ! 1137: "operands[1] = prepare_scc_operands (EQ);") ! 1138: ! 1139: (define_insn "anddi3" ! 1140: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 1141: (and:DI (match_operand:DI 1 "arith_reg_operand" "%0") ! 1142: (match_operand:DI 2 "arith_reg_operand" "r")))] ! 1143: "" ! 1144: "and %2,%0\;and %R2,%R0" ! 1145: [(set_attr "length" "4")]) ! 1146: ! 1147: (define_insn "iordi3" ! 1148: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 1149: (ior:DI (match_operand:DI 1 "arith_reg_operand" "%0") ! 1150: (match_operand:DI 2 "arith_reg_operand" "r")))] ! 1151: "" ! 1152: "or %2,%0\;or %R2,%R0" ! 1153: [(set_attr "length" "4")]) ! 1154: ! 1155: (define_insn "xordi3" ! 1156: [(set (match_operand:DI 0 "arith_reg_operand" "=r") ! 1157: (xor:DI (match_operand:DI 1 "arith_reg_operand" "%0") ! 1158: (match_operand:DI 2 "arith_reg_operand" "r")))] ! 1159: "" ! 1160: "xor %2,%0\;xor %R2,%R0" ! 1161: [(set_attr "length" "4")]) ! 1162: ! 1163: ! 1164: ;; ------------------------------------------------------------------------ ! 1165: ;; Block move ! 1166: ;; ------------------------------------------------------------------------ ! 1167: ! 1168: (define_expand "movstrsi" ! 1169: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) ! 1170: (mem:BLK (match_operand:BLK 1 "general_operand" ""))) ! 1171: (use (match_operand:SI 2 "general_operand" "")) ! 1172: (use (match_operand:SI 3 "immediate_operand" "")) ! 1173: ])] ! 1174: "" ! 1175: " ! 1176: { ! 1177: rtx src_ptr = copy_to_mode_reg(Pmode,XEXP(operands[1], 0)); ! 1178: rtx dst_ptr = copy_to_mode_reg(Pmode,XEXP(operands[0], 0)); ! 1179: int maxsize = GET_CODE (operands[2]) == CONST_INT ! 1180: ? MAX (INTVAL (operands[2]), INTVAL (operands[3])) : 1; ! 1181: enum machine_mode mode = ! 1182: (maxsize >= 4) ? SImode : ! 1183: (maxsize >= 2) ? HImode : ! 1184: QImode; ! 1185: ! 1186: rtx tmpreg = gen_reg_rtx(mode); ! 1187: rtx increment = GEN_INT(GET_MODE_SIZE(mode)); ! 1188: rtx length = operands[2]; ! 1189: rtx label = gen_label_rtx(); ! 1190: rtx end_src_ptr = gen_reg_rtx(Pmode); ! 1191: ! 1192: /* If done first rtl emmiting stage we can't generate a loop */ ! 1193: /* if (!rtx_equal_function_value_matters) ! 1194: FAIL;*/ ! 1195: ! 1196: if (GET_CODE (length) != CONST_INT) ! 1197: length = convert_to_mode (Pmode, length, 1); ! 1198: ! 1199: if (!arith_operand (length, SImode)) ! 1200: length = force_reg (SImode, length); ! 1201: ! 1202: emit_insn(gen_rtx(SET, ! 1203: VOIDmode, ! 1204: end_src_ptr, ! 1205: gen_rtx(PLUS, Pmode, src_ptr, length))); ! 1206: ! 1207: ! 1208: emit_label(label); ! 1209: emit_move_insn(tmpreg, gen_rtx(MEM, mode, src_ptr)); ! 1210: ! 1211: ! 1212: emit_insn(gen_rtx(SET, ! 1213: VOIDmode, ! 1214: src_ptr, ! 1215: gen_rtx(PLUS, Pmode, src_ptr, increment))); ! 1216: ! 1217: emit_move_insn(gen_rtx(MEM, mode, dst_ptr), tmpreg); ! 1218: ! 1219: emit_insn(gen_rtx(SET, ! 1220: VOIDmode, ! 1221: dst_ptr, ! 1222: gen_rtx(PLUS, Pmode, dst_ptr, increment))); ! 1223: ! 1224: sh_compare_op0 = src_ptr; ! 1225: sh_compare_op1 = end_src_ptr; ! 1226: ! 1227: emit_insn(gen_cmpeqsi_t(src_ptr, end_src_ptr)); ! 1228: emit_jump_insn(gen_bne(label)); ! 1229: emit_insn(gen_rtx(SET, VOIDmode, dst_ptr, dst_ptr)); ! 1230: ! 1231: DONE; ! 1232: } ! 1233: ") ! 1234: ! 1235: ! 1236: ! 1237: ! 1238: ! 1239: ;; ------------------------------------------------------------------------- ! 1240: ;; Peepholes ! 1241: ;; ------------------------------------------------------------------------- ! 1242: ! 1243: ! 1244: (define_peephole ! 1245: [(set (match_operand:QI 0 "arith_reg_operand" "") ! 1246: (mem:QI (match_operand:SI 1 "arith_reg_operand" ""))) ! 1247: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] ! 1248: "REGNO(operands[1]) != REGNO(operands[0])" ! 1249: "mov.b @%1+,%0") ! 1250: ! 1251: (define_peephole ! 1252: [(set (match_operand:HI 0 "arith_reg_operand" "") ! 1253: (mem:HI (match_operand:SI 1 "arith_reg_operand" ""))) ! 1254: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))] ! 1255: "REGNO(operands[1]) != REGNO(operands[0])" ! 1256: "mov.w @%1+,%0") ! 1257: ! 1258: (define_peephole ! 1259: [(set (match_operand:SI 0 "arith_reg_operand" "") ! 1260: (mem:SI (match_operand:SI 1 "arith_reg_operand" ""))) ! 1261: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))] ! 1262: "REGNO(operands[1]) != REGNO(operands[0])" ! 1263: "mov.l @%1+,%0") ! 1264: ! 1265:
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