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1.1 root 1: ;;- Machine description the Hitachi SH
2: ;; Copyright (C) 1993 Free Software Foundation, Inc.
3: ;; Contributed by Steve Chamberlain ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22:
1.1.1.3 ! root 23: ;; Special constraints for SH machine description:
! 24: ;;
! 25: ;; t -- T
! 26: ;; x -- mac
! 27: ;; l -- pr
! 28: ;; z -- r0
! 29: ;;
! 30: ;; Special formats used for outputting SH instructions:
! 31: ;;
! 32: ;; %. -- print a .s if insn needs delay slot
! 33: ;; %* -- print a local label
! 34: ;; %^ -- increment the local label number
! 35: ;; %# -- output a nop if there is nothing to put in the delay slot
! 36: ;; %R -- print the next register or memory location along, ie the lsw in
! 37: ;; a double word value
! 38: ;; %O -- print a constant without the #
! 39: ;; %M -- print a constant as its negative
! 40: ;;
! 41: ;;
! 42: ;; Special predicates:
! 43: ;;
! 44: ;; arith_operand -- operand is valid source for arithmetic op
! 45: ;; arith_reg_operand -- operand is valid register for arithmetic op
! 46: ;; byte_index_operand -- operand is ok as an index in a mov.b
! 47: ;; general_movdst_operand -- operand is valid move destination
! 48: ;; general_movsrc_operand -- operand is valid move source
! 49: ;; logical_operand -- operand is valid source for logical op
! 50: ;; pop_operand -- operand is a pop from the stack
! 51: ;; system_reg_operand -- operand is MACL, MACH, or PR
1.1 root 52: ;; -------------------------------------------------------------------------
53: ;; Attributes
54: ;; -------------------------------------------------------------------------
55:
1.1.1.2 root 56: ; Target CPU.
57:
58: (define_attr "cpu" "sh0,sh1,sh2,sh3"
59: (const (symbol_ref "sh_cpu")))
60:
1.1.1.3 ! root 61: (define_attr "interrupt_function" "no,yes"
! 62: (const (symbol_ref "pragma_interrupt")))
! 63: ;;
! 64: ;; cbranch conditional branch instructions
! 65: ;; jump unconditional jumps
! 66: ;; arith ordinary arithmetic
! 67: ;; load from memory
! 68: ;; store to memory
! 69: ;; move register to register
! 70: ;; smpy single precision integer multiply
! 71: ;; dmpy double precision integer multiply
! 72: ;; return rts
! 73: ;; pload load of pr reg (can't be put into delay slot of rts)
! 74: ;; pcloadsi pc relative load of SI value
! 75: ;; pcloadhi pc relative load of HI value
! 76: ;; rte return from exception
! 77: ;; sfunc special function call with known used registers
! 78:
! 79: (define_attr "type"
! 80: "cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pcloadsi,pcloadhi,rte,sfunc"
1.1 root 81: (const_string "other"))
82:
1.1.1.3 ! root 83: ; If a conditional branch destination is within -120..120 bytes away
1.1 root 84: ; from the instruction it can be 2 bytes long. Something in the
1.1.1.3 ! root 85: ; range -4090..4090 bytes can be 6 bytes long, all other conditional
1.1 root 86: ; branches are 8 bytes long.
87:
88: ; An unconditional jump which can reach forward or back 4k can be
89: ; 6 bytes long (including the delay slot). If it is too big, it
1.1.1.3 ! root 90: ; must be 10 bytes long.
1.1 root 91:
1.1.1.3 ! root 92: ; If a pcrel instruction is within 500 bytes of the constant, then the insn is
! 93: ; 2 bytes long, otherwise 12 bytes
1.1 root 94: ; All other instructions are two bytes long by default.
95:
96: (define_attr "length" ""
97: (cond [(eq_attr "type" "cbranch")
1.1.1.3 ! root 98: (if_then_else (and (ge (minus (pc) (match_dup 0))
! 99: (const_int -122))
! 100: (le (minus (pc) (match_dup 0))
! 101: (const_int 122)))
! 102: (const_int 2)
! 103: (if_then_else (and (ge (minus (pc) (match_dup 0))
! 104: (const_int -4090))
! 105: (le (minus (pc) (match_dup 0))
! 106: (const_int 4090)))
! 107: (const_int 6)
! 108: (const_int 16)))
1.1 root 109:
110: (eq_attr "type" "jump")
1.1.1.3 ! root 111: (if_then_else (and (ge (minus (pc) (match_dup 0))
! 112: (const_int -4090))
! 113: (le (minus (pc) (match_dup 0))
! 114: (const_int 4090)))
! 115: (const_int 4)
! 116: (const_int 10))
! 117: (eq_attr "type" "pcloadsi")
! 118: (if_then_else (gt (pc) (minus (match_dup 0) (const_int 1000)))
! 119: (const_int 2)
! 120: (const_int 12))
! 121: (eq_attr "type" "pcloadhi")
! 122: (if_then_else (gt (pc) (minus (match_dup 0) (const_int 500)))
! 123: (const_int 2)
! 124: (const_int 12))
! 125:
1.1 root 126: ] (const_int 2)))
1.1.1.2 root 127:
128: ;; (define_function_unit {name} {num-units} {n-users} {test}
129: ;; {ready-delay} {issue-delay} [{conflict-list}])
1.1 root 130:
1.1.1.3 ! root 131: (define_function_unit "memory" 1 0 (eq_attr "type" "load,pcloadsi,pcloadhi") 2 0)
! 132: (define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 3 0)
! 133: (define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 5 0)
1.1 root 134:
135: (define_attr "needs_delay_slot" "yes,no"
1.1.1.3 ! root 136: (cond [(eq_attr "type" "jump") (const_string "yes")
1.1.1.2 root 137: (eq_attr "type" "return") (const_string "yes")]
1.1 root 138: (const_string "no")))
139:
1.1.1.2 root 140: (define_delay
1.1.1.3 ! root 141: (eq_attr "needs_delay_slot" "yes")
1.1.1.2 root 142: [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
143:
1.1.1.3 ! root 144: (define_delay
! 145: (eq_attr "type" "return")
! 146: [(and (eq_attr "in_delay_slot" "yes")
! 147: (ior (eq_attr "interrupt_function" "no")
! 148: (eq_attr "hit_stack" "no"))) (nil) (nil)])
! 149:
! 150: (define_attr "hit_stack" "yes,no" (const_string "no"))
1.1.1.2 root 151:
1.1.1.3 ! root 152: (define_delay
! 153: (and (eq_attr "type" "cbranch")
! 154: (eq_attr "cpu" "sh2"))
! 155: [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
1.1 root 156:
157: (define_attr "in_delay_slot" "maybe,yes,no"
158: (cond [(eq_attr "type" "cbranch") (const_string "no")
159: (eq_attr "type" "jump") (const_string "no")
1.1.1.2 root 160: (eq_attr "type" "pload") (const_string "no")
1.1.1.3 ! root 161: (eq_attr "type" "pcloadsi") (const_string "no")
! 162: (eq_attr "type" "pcloadhi") (const_string "no")
1.1.1.2 root 163: (eq_attr "type" "return") (const_string "no")
1.1 root 164: (eq_attr "length" "2") (const_string "yes")
165: (eq_attr "length" "4,6,8,10,12") (const_string "no")
166: ] (const_string "yes")))
167:
168:
169:
170: ;; -------------------------------------------------------------------------
171: ;; SImode signed integer comparisons
172: ;; -------------------------------------------------------------------------
173:
174: (define_insn ""
175: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
176: (eq:SI (reg:SI 18)
177: (const_int 1)))]
178: ""
179: "movt %0 !movt1")
1.1.1.3 ! root 180:
1.1 root 181: (define_insn ""
1.1.1.3 ! root 182: [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r")
! 183: (const_int 0)))]
1.1 root 184: ""
185: "cmp/pl %0")
186:
187: (define_insn ""
1.1.1.3 ! root 188: [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r")
! 189: (const_int 0)))]
1.1 root 190: ""
191: "cmp/pz %0")
192:
1.1.1.3 ! root 193: (define_insn "cmpeq_0"
! 194: [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r")
! 195: (const_int 0)))]
1.1 root 196: ""
1.1.1.3 ! root 197: "tst %0,%0 ! t0")
1.1 root 198:
1.1.1.3 ! root 199: (define_insn "cmpeqsi_t"
! 200: [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_operand" "r,N,z,r")
! 201: (match_operand:SI 1 "arith_operand" "N,r,rI,r")))]
! 202: ""
! 203: "@
! 204: tst %0,%0 !t1
! 205: tst %1,%1 !t2
! 206: cmp/eq %1,%0
! 207: cmp/eq %1,%0")
1.1 root 208:
209: (define_insn "cmpgtsi_t"
1.1.1.3 ! root 210: [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
! 211: (match_operand:SI 1 "arith_operand" "N,r")))]
1.1 root 212: ""
1.1.1.3 ! root 213: "@
! 214: cmp/pl %0
! 215: cmp/gt %1,%0")
1.1 root 216:
217: (define_insn "cmpgesi_t"
1.1.1.3 ! root 218: [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
! 219: (match_operand:SI 1 "arith_operand" "N,r")))]
1.1 root 220: ""
1.1.1.3 ! root 221: "@
! 222: cmp/pz %0
! 223: cmp/ge %1,%0")
1.1 root 224:
225:
226: ;; -------------------------------------------------------------------------
227: ;; SImode unsigned integer comparisons
228: ;; -------------------------------------------------------------------------
229:
230: (define_insn "cmpgeusi_t"
1.1.1.3 ! root 231: [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
! 232: (match_operand:SI 1 "arith_operand" "N,r")))]
1.1 root 233: ""
1.1.1.3 ! root 234: "@
! 235: cmp/pz %1
! 236: cmp/hs %1,%0")
1.1 root 237:
238: (define_insn "cmpgtusi_t"
1.1.1.3 ! root 239: [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_operand" "r,r")
! 240: (match_operand:SI 1 "arith_operand" "N,r")))]
1.1 root 241: ""
1.1.1.3 ! root 242: "@
! 243: cmp/pl %1
! 244: cmp/hi %1,%0")
1.1 root 245:
246: ;; We save the compare operands in the cmpxx patterns and use them when
247: ;; we generate the branch.
248:
249: (define_expand "cmpsi"
1.1.1.3 ! root 250: [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
! 251: (match_operand:SI 1 "arith_operand" "")))]
1.1 root 252: ""
253: "
1.1.1.3 ! root 254: {
! 255: sh_compare_op0 = operands[0];
1.1 root 256: sh_compare_op1 = operands[1];
257: DONE;
258: }")
259:
260:
261: ;; -------------------------------------------------------------------------
262: ;; Addition instructions
263: ;; -------------------------------------------------------------------------
264:
1.1.1.3 ! root 265: ;; this should be a define split.
! 266:
1.1 root 267: (define_insn "adddi3"
1.1.1.3 ! root 268: [(set (match_operand:DI 0 "register_operand" "=r")
! 269: (plus:DI (match_operand:DI 1 "register_operand" "%0")
! 270: (match_operand:DI 2 "register_operand" "r")))
1.1 root 271: (clobber (reg:SI 18))]
272: ""
273: "clrt\;addc %R2,%R0\;addc %2,%0"
1.1.1.3 ! root 274: [(set_attr "length" "6")])
1.1 root 275:
276:
1.1.1.3 ! root 277: (define_insn "addsi3_real"
1.1 root 278: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
279: (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
280: (match_operand:SI 2 "arith_operand" "rI")))]
281: ""
282: "add %2,%0"
283: [(set_attr "length" "2")
284: (set_attr "type" "arith")])
285:
286: (define_expand "addsi3"
287: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1.1.1.3 ! root 288: (plus:SI (match_operand:SI 1 "arith_operand" "%0")
1.1 root 289: (match_operand:SI 2 "arith_operand" "rI")))]
290: ""
291: "")
292:
293:
294: ;; -------------------------------------------------------------------------
295: ;; Subtraction instructions
296: ;; -------------------------------------------------------------------------
297:
1.1.1.3 ! root 298:
1.1 root 299: (define_insn "subdi3"
1.1.1.3 ! root 300: [(set (match_operand:DI 0 "register_operand" "=r")
! 301: (minus:DI (match_operand:DI 1 "register_operand" "0")
! 302: (match_operand:DI 2 "register_operand" "r")))
1.1 root 303: (clobber (reg:SI 18))]
304: ""
305: "clrt\;subc %R2,%R0\;subc %2,%0"
1.1.1.3 ! root 306: [(set_attr "length" "6")])
1.1 root 307:
308: (define_insn "subsi3"
1.1.1.3 ! root 309: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 310: (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 311: (match_operand:SI 2 "arith_operand" "r")))]
1.1 root 312: ""
1.1.1.3 ! root 313: "sub %2,%0"
1.1 root 314: [(set_attr "type" "arith")])
315:
316:
317: ;; -------------------------------------------------------------------------
1.1.1.3 ! root 318: ;; Division instructions
1.1 root 319: ;; -------------------------------------------------------------------------
320:
321:
1.1.1.3 ! root 322: ;; we take advantage of the library routines which don't clobber as many
! 323: ;; registers as a normal function call would.
! 324:
! 325:
! 326: (define_insn ""
! 327: [(set (reg:SI 0)
! 328: (udiv:SI (reg:SI 4) (reg:SI 5)))
! 329: (clobber (reg:SI 18))
! 330: (clobber (reg:SI 17))
! 331: (clobber (reg:SI 6))
! 332: (clobber (reg:SI 4))
! 333: (use (match_operand:SI 0 "register_operand" "r"))]
! 334: ""
! 335: "jsr @%0%#"
! 336: [(set_attr "type" "sfunc")
! 337: (set_attr "length" "4")
! 338: (set_attr "needs_delay_slot" "yes")])
! 339:
! 340: (define_expand "udivsi3"
! 341: [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "g"))
! 342: (set (reg:SI 5) (match_operand:SI 2 "general_operand" "g"))
! 343: (set (match_dup 3) (symbol_ref:SI "__udivsi3"))
! 344: (parallel[(set (reg:SI 0)
! 345: (udiv:SI (reg:SI 4)
! 346: (reg:SI 5)))
! 347: (clobber (reg:SI 18))
! 348: (clobber (reg:SI 17))
! 349: (clobber (reg:SI 6))
! 350: (clobber (reg:SI 4))
! 351: (use (match_dup 3))])
! 352: (set (match_operand:SI 0 "general_operand" "=g")
! 353: (reg:SI 0))]
! 354: ""
! 355: "operands[3] = gen_reg_rtx(SImode);")
! 356:
! 357:
! 358: (define_insn ""
! 359: [(set (reg:SI 0)
! 360: (div:SI (reg:SI 4) (reg:SI 5)))
! 361: (clobber (reg:SI 18))
! 362: (clobber (reg:SI 17))
! 363: (clobber (reg:SI 1))
! 364: (clobber (reg:SI 2))
! 365: (clobber (reg:SI 3))
! 366: (use (match_operand:SI 0 "register_operand" "r"))]
! 367: ""
! 368: "jsr @%0%#"
! 369: [(set_attr "type" "sfunc")
! 370: (set_attr "length" "4")
! 371: (set_attr "needs_delay_slot" "yes")])
! 372:
! 373: (define_expand "divsi3"
! 374: [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "g"))
! 375: (set (reg:SI 5) (match_operand:SI 2 "general_operand" "g"))
! 376: (set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
! 377: (parallel[(set (reg:SI 0)
! 378: (div:SI (reg:SI 4)
! 379: (reg:SI 5)))
! 380: (clobber (reg:SI 18))
! 381: (clobber (reg:SI 17))
! 382: (clobber (reg:SI 1))
! 383: (clobber (reg:SI 2))
! 384: (clobber (reg:SI 3))
! 385: (use (match_dup 3))])
! 386: (set (match_operand:SI 0 "general_operand" "=g")
! 387: (reg:SI 0))]
! 388: ""
! 389: "operands[3] = gen_reg_rtx(SImode);")
! 390:
! 391:
! 392: ;; -------------------------------------------------------------------------
! 393: ;; Multiplication instructions
! 394: ;; -------------------------------------------------------------------------
! 395:
1.1 root 396: (define_insn ""
397: [(set (reg:SI 21)
1.1.1.3 ! root 398: (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))
! 399: (zero_extend:SI (match_operand:HI 2 "arith_reg_operand" "r"))))]
1.1 root 400: ""
1.1.1.2 root 401: "mulu %2,%1"
402: [(set_attr "type" "smpy")])
1.1 root 403:
404: (define_insn ""
405: [(set (reg:SI 21)
406: (mult:SI (sign_extend:SI
407: (match_operand:HI 1 "arith_reg_operand" "r"))
408: (sign_extend:SI
409: (match_operand:HI 2 "arith_reg_operand" "r"))))]
410: ""
1.1.1.2 root 411: "muls %2,%1"
412: [(set_attr "type" "smpy")])
1.1 root 413:
414: (define_expand "mulhisi3"
415: [(set (reg:SI 21)
416: (mult:SI (sign_extend:SI
1.1.1.3 ! root 417: (match_operand:HI 1 "mac_operand" "r"))
1.1 root 418: (sign_extend:SI
1.1.1.3 ! root 419: (match_operand:HI 2 "mac_operand" "r"))))
1.1 root 420: (set (match_operand:SI 0 "arith_reg_operand" "=r")
421: (reg:SI 21))]
422: ""
423: "")
424:
425: (define_expand "umulhisi3"
426: [(set (reg:SI 21)
427: (mult:SI (zero_extend:SI
428: (match_operand:HI 1 "arith_reg_operand" "r"))
429: (zero_extend:SI
430: (match_operand:HI 2 "arith_reg_operand" "r"))))
431: (set (match_operand:SI 0 "arith_reg_operand" "=r")
432: (reg:SI 21))]
433: ""
434: "")
435:
1.1.1.3 ! root 436: ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
! 437: ;; a call to a routine which clobbers known registers.
! 438:
! 439: (define_insn ""
! 440: [(set (reg:SI 0)
! 441: (mult:SI (reg:SI 4) (reg:SI 5)))
! 442: (clobber (reg:SI 21))
! 443: (clobber (reg:SI 18))
! 444: (clobber (reg:SI 17))
! 445: (clobber (reg:SI 3))
! 446: (clobber (reg:SI 2))
! 447: (clobber (reg:SI 1))
! 448: (use (match_operand:SI 0 "register_operand" "r"))]
! 449: ""
! 450: "jsr @%0%#"
! 451: [(set_attr "type" "sfunc")
! 452: (set_attr "length" "4")
! 453: (set_attr "needs_delay_slot" "yes")])
! 454:
! 455: (define_expand "mulsi3_call"
! 456: [(set (reg:SI 4) (match_operand:SI 1 "general_operand" "g"))
! 457: (set (reg:SI 5) (match_operand:SI 2 "general_operand" "g"))
! 458: (set (match_dup 3) (symbol_ref:SI "__mulsi3"))
! 459: (parallel[(set (reg:SI 0)
! 460: (mult:SI (reg:SI 4)
! 461: (reg:SI 5)))
! 462: (clobber (reg:SI 21))
! 463: (clobber (reg:SI 18))
! 464: (clobber (reg:SI 17))
! 465: (clobber (reg:SI 3))
! 466: (clobber (reg:SI 2))
! 467: (clobber (reg:SI 1))
! 468: (use (match_dup 3))])
! 469: (set (match_operand:SI 0 "general_operand" "=g")
! 470: (reg:SI 0))]
! 471: ""
! 472: "operands[3] = gen_reg_rtx(SImode);")
! 473:
! 474: (define_insn "mul_l"
! 475: [(set (reg:SI 21)
! 476: (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
! 477: (match_operand:SI 1 "arith_reg_operand" "r")))]
! 478: "TARGET_SH2"
! 479: "mul.l %1,%0"
! 480: [(set_attr "type" "smpy")])
! 481:
! 482: (define_expand "mulsi3"
! 483: [(set (reg:SI 21)
! 484: (mult:SI (match_operand:SI 1 "arith_reg_operand" "r")
! 485: (match_operand:SI 2 "arith_reg_operand" "r")))
! 486: (set (match_operand:SI 0 "arith_reg_operand" "=r")
! 487: (reg:SI 21))]
! 488: "TARGET_SH2"
! 489: "")
! 490:
! 491: (define_insn ""
! 492: [(set (reg:DI 20)
! 493: (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
! 494: (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
! 495: "TARGET_SH2"
! 496: "dmuls.l %2,%1"
! 497: [(set_attr "type" "dmpy")])
! 498:
! 499: (define_expand "mulsidi3"
! 500: [(set (reg:DI 20)
! 501: (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
! 502: (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
! 503: (set (match_operand:DI 0 "arith_reg_operand" "=r")
! 504: (reg:DI 20))]
! 505: "TARGET_SH2"
! 506: "")
! 507:
! 508: (define_insn ""
! 509: [(set (reg:DI 20)
! 510: (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
! 511: (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
! 512: "TARGET_SH2"
! 513: "dmulu.l %2,%1"
! 514: [(set_attr "type" "dmpy")])
! 515:
! 516: (define_expand "umulsidi3"
! 517: [(set (reg:DI 20)
! 518: (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
! 519: (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
! 520: (set (match_operand:DI 0 "arith_reg_operand" "=r")
! 521: (reg:DI 20))]
! 522: "TARGET_SH2"
! 523: "")
! 524:
1.1 root 525:
526: ;; -------------------------------------------------------------------------
527: ;; Logical operations
528: ;; -------------------------------------------------------------------------
529:
1.1.1.3 ! root 530: (define_insn "and_ffff"
! 531: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 532: (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
! 533: (const_int 65535)))]
! 534: ""
! 535: "extu.w %1,%0"
! 536: [(set_attr "type" "arith")])
! 537:
! 538: (define_insn "and_ff"
! 539: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 540: (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
! 541: (const_int 255)))]
! 542: ""
! 543: "extu.b %1,%0"
! 544: [(set_attr "type" "arith")])
! 545:
! 546: (define_insn ""
1.1 root 547: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
548: (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
549: (match_operand:SI 2 "logical_operand" "r,L")))]
550: ""
551: "and %2,%0"
552: [(set_attr "type" "arith")])
553:
1.1.1.3 ! root 554: (define_expand "andsi3"
! 555: [(set (match_operand:SI 0 "arith_reg_operand" "")
! 556: (and:SI (match_operand:SI 1 "arith_reg_operand" "")
! 557: (match_operand:SI 2 "logical_operand" "")))]
! 558: ""
! 559: "")
! 560:
1.1 root 561: (define_insn "iorsi3"
562: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
563: (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
564: (match_operand:SI 2 "logical_operand" "r,L")))]
565: ""
566: "or %2,%0")
567:
568: (define_insn "xorsi3"
1.1.1.3 ! root 569: [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1.1 root 570: (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1.1.1.3 ! root 571: (match_operand:SI 2 "logical_operand" "L,r")))]
1.1 root 572: ""
573: "xor %2,%0"
574: [(set_attr "type" "arith")])
575:
576:
577: ;; -------------------------------------------------------------------------
578: ;; Shifts and rotates
579: ;; -------------------------------------------------------------------------
580:
1.1.1.2 root 581: (define_insn "rotlsi3_k"
582: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
583: (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
584: (const_int 1)))
585: (clobber (reg:SI 18))]
586: ""
587: "rotl %0")
588:
589: (define_expand "rotlsi3"
590: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
591: (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
592: (match_operand:SI 2 "immediate_operand" "")))
593: (clobber (reg:SI 18))])]
594: ""
595: "{ if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) != 1) FAIL;}")
596:
597: (define_insn "rotrsi3_k"
598: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
599: (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
600: (const_int 1)))
601: (clobber (reg:SI 18))]
602: ""
603: "rotr %0")
604:
605: (define_expand "rotrsi3"
606: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
607: (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "")
608: (match_operand:SI 2 "immediate_operand" "")))
609: (clobber (reg:SI 18))])]
610: ""
611: "{ if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) != 1) FAIL;}")
612:
1.1.1.3 ! root 613:
! 614: ;;
! 615: ;; shift left
! 616:
1.1 root 617: (define_insn "ashlsi3_k"
618: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
619: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
1.1.1.3 ! root 620: (match_operand:SI 2 "immediate_operand" "M,K")))
1.1.1.2 root 621: (clobber (reg:SI 18))]
1.1.1.3 ! root 622: "CONST_OK_FOR_K (INTVAL (operands[2]))"
! 623: "@
! 624: shll %0
! 625: shll%O2 %0")
! 626:
! 627: ; seperate pattern for shifts by any N. Look at pnum_clobbers
! 628: ; to see if this is being recognised inside combine. If so, dont
! 629: ; match, since combine will try and merge shifts, which will break
! 630: ; scheduling
! 631:
! 632: (define_insn "ashlsi3_n"
! 633: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 634: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 635: (match_operand:SI 2 "immediate_operand" "n")))
! 636: (clobber (reg:SI 18))]
! 637: "fake_shift()"
1.1.1.2 root 638: "*return output_shift(\"shll\", operands[0], operands[2], ASHIFT);"
1.1.1.3 ! root 639: [(set_attr "length" "12")
! 640: (set_attr "in_delay_slot" "no")
1.1 root 641: (set_attr "type" "arith")])
642:
643: (define_expand "ashlsi3"
1.1.1.2 root 644: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
645: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
646: (match_operand:SI 2 "immediate_operand" "")))
647: (clobber (reg:SI 18))])]
1.1 root 648: ""
1.1.1.3 ! root 649: "if (gen_shifty_op (ASHIFT, operands)) DONE; else FAIL;")
! 650:
! 651: ;
! 652: ; arithmetic shift right
! 653: ;
1.1 root 654:
655: (define_insn "ashrsi3_k"
656: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
657: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1.1.1.3 ! root 658: (match_operand:SI 2 "immediate_operand" "M")))
1.1.1.2 root 659: (clobber (reg:SI 18))]
1.1.1.3 ! root 660: "INTVAL(operands[2]) == 1"
1.1 root 661: "shar %0"
662: [(set_attr "type" "arith")])
663:
1.1.1.3 ! root 664: (define_insn "ashrsi3_16"
! 665: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 666: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 667: (match_operand:SI 2 "immediate_operand" "i")))
! 668: (clobber (reg:SI 18))]
! 669: "INTVAL(operands[2]) == 16"
! 670: "shlr16 %0\;exts.w %0,%0"
! 671: [(set_attr "type" "arith")
! 672: (set_attr "length" "4")])
! 673:
! 674: ; an arithmetic shift right by 16 is better as a logical shift and a
! 675: ; sign extend
! 676:
! 677: ;(define_split
! 678: ; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 679: ; (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 680: ; (const_int 16)))
! 681: ; (clobber (reg:SI 18))]
! 682: ; ""
! 683: ; [(set (match_dup 3) (match_dup 0))
! 684: ; (set (match_dup 3) (lshiftrt:SI (match_dup 3) (const_int 16)))
! 685: ; (set (match_dup 0) (sign_extend:SI (subreg:HI (match_dup 3) 0)))]
! 686: ; "operands[3] = gen_reg_rtx (SImode);")
! 687:
! 688: (define_insn "ashrsi3_n"
! 689: [(set (reg:SI 4)
! 690: (ashiftrt:SI (reg:SI 4)
! 691: (match_operand:SI 0 "immediate_operand" "i")))
! 692: (clobber (reg:SI 18))
! 693: (clobber (reg:SI 17))
! 694: (use (match_operand:SI 1 "arith_reg_operand" "r"))]
! 695: ""
! 696: "jsr @%1%#"
! 697: [(set_attr "type" "sfunc")
! 698: (set_attr "in_delay_slot" "no")
! 699: (set_attr "length" "4")
! 700: (set_attr "needs_delay_slot" "yes")])
! 701:
1.1 root 702: (define_expand "ashrsi3"
1.1.1.2 root 703: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "=r")
704: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
705: (match_operand:SI 2 "nonmemory_operand" "M")))
706: (clobber (reg:SI 18))])]
1.1 root 707: ""
1.1.1.3 ! root 708: "if (gen_shifty_op (ASHIFTRT, operands)) DONE; else FAIL;")
! 709:
! 710: ; logical shift right
! 711: ;
1.1 root 712:
713: (define_insn "lshrsi3_k"
1.1.1.2 root 714: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
715: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
1.1.1.3 ! root 716: (match_operand:SI 2 "immediate_operand" "M,K")))
1.1.1.2 root 717: (clobber (reg:SI 18))]
1.1.1.3 ! root 718: "CONST_OK_FOR_K (INTVAL (operands[2]))"
! 719: "@
! 720: shlr %0
! 721: shlr%O2 %0")
! 722:
! 723: ; seperate pattern for shifts by any N.
! 724:
! 725: (define_insn "lshrsi3_n"
! 726: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 727: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
! 728: (match_operand:SI 2 "immediate_operand" "n")))
! 729: (clobber (reg:SI 18))]
! 730: "fake_shift()"
1.1.1.2 root 731: "* return output_shift (\"shlr\", operands[0], operands[2], LSHIFTRT);"
1.1.1.3 ! root 732: [(set_attr "length" "12")
! 733: (set_attr "in_delay_slot" "no")
1.1 root 734: (set_attr "type" "arith")])
735:
736: (define_expand "lshrsi3"
1.1.1.2 root 737: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
738: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1.1.1.3 ! root 739: (match_operand:SI 2 "immediate_operand" "")))
1.1.1.2 root 740: (clobber (reg:SI 18))])]
1.1 root 741: ""
1.1.1.3 ! root 742: "if (gen_shifty_op (LSHIFTRT, operands)) DONE; else FAIL;")
1.1 root 743:
744: (define_insn "ashldi3_k"
745: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
746: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1.1.1.3 ! root 747: (const_int 1)))
1.1 root 748: (clobber (reg:SI 18))]
749: ""
750: "shll %R0\;rotcl %0"
751: [(set_attr "length" "4")])
752:
753: (define_expand "ashldi3"
754: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
755: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
756: (match_operand:DI 2 "immediate_operand" "")))
757: (clobber (reg:SI 18))])]
758:
759: ""
760: "{ if (GET_CODE (operands[2]) != CONST_INT
761: || INTVAL (operands[2]) != 1) FAIL;} ")
762:
763: (define_insn "lshrdi3_k"
764: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1.1.1.2 root 765: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1.1.1.3 ! root 766: (const_int 1)))
1.1.1.2 root 767: (clobber (reg:SI 18))]
1.1 root 768: ""
769: "shlr %0\;rotcr %R0"
770: [(set_attr "length" "4")])
771:
772: (define_expand "lshrdi3"
773: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
774: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
775: (match_operand:DI 2 "immediate_operand" "")))
776: (clobber (reg:SI 18))])]
777: ""
778: "{ if (GET_CODE (operands[2]) != CONST_INT
779: || INTVAL (operands[2]) != 1) FAIL;} ")
780:
781: (define_insn "ashrdi3_k"
782: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
783: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1.1.1.3 ! root 784: (const_int 1)))
1.1 root 785: (clobber (reg:SI 18))]
786: ""
787: "shar %0\;rotcr %R0"
788: [(set_attr "length" "4")])
789:
790: (define_expand "ashrdi3"
791: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
792: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
793: (match_operand:DI 2 "immediate_operand" "")))
794: (clobber (reg:SI 18))])]
795: ""
796: "{ if (GET_CODE (operands[2]) != CONST_INT
797: || INTVAL (operands[2]) != 1) FAIL; } ")
798:
799:
800: ;; -------------------------------------------------------------------------
801: ;; Unary arithmetic
802: ;; -------------------------------------------------------------------------
803:
1.1.1.3 ! root 804:
! 805: (define_insn "negc"
! 806: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 807: (neg:SI (plus:SI (reg:SI 18) (match_operand:SI 1 "arith_reg_operand" "r"))))]
1.1 root 808: ""
1.1.1.3 ! root 809: "negc %1,%0"
! 810: [(set_attr "length" "2")
1.1 root 811: (set_attr "type" "arith")])
812:
1.1.1.3 ! root 813: (define_expand "negdi2"
! 814: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! 815: (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))
! 816: (clobber (reg:SI 18))]
! 817: ""
! 818: "{
! 819: rtx low_src = operand_subword (operands[1], 1, 0, DImode);
! 820: rtx high_src = operand_subword (operands[1], 0, 0, DImode);
! 821:
! 822: rtx low_dst = operand_subword (operands[0], 1, 1, DImode);
! 823: rtx high_dst = operand_subword (operands[0], 0, 1, DImode);
! 824:
! 825: emit_insn (gen_clrt ());
! 826: emit_insn (gen_negc (low_dst, low_src));
! 827: emit_insn (gen_negc (high_dst, high_src));
! 828: DONE;
! 829: }
! 830: ")
! 831:
! 832:
1.1 root 833: (define_insn "negsi2"
834: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
835: (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
836: ""
837: "neg %1,%0"
838: [(set_attr "type" "arith")])
839:
840: (define_insn "one_cmplsi2"
841: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
842: (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
843: ""
844: "not %1,%0"
1.1.1.3 ! root 845: [(set_attr "type" "arith")])
1.1 root 846:
847:
848: ;; -------------------------------------------------------------------------
849: ;; Zero extension instructions
850: ;; -------------------------------------------------------------------------
851:
852: (define_insn "zero_extendhisi2"
853: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
854: (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
855: ""
856: "extu.w %1,%0"
857: [(set_attr "type" "arith")])
858:
859: (define_insn "zero_extendqisi2"
860: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
861: (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
862: ""
863: "extu.b %1,%0"
864: [(set_attr "type" "arith")])
865:
866: (define_insn "zero_extendqihi2"
867: [(set (match_operand:HI 0 "arith_reg_operand" "=r")
868: (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
869: ""
870: "extu.b %1,%0"
871: [(set_attr "type" "arith")])
872:
873:
874: ;; -------------------------------------------------------------------------
875: ;; Sign extension instructions
876: ;; -------------------------------------------------------------------------
877:
878: (define_insn "extendsidi2"
1.1.1.3 ! root 879: [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
! 880: (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "0,r")))
! 881: (clobber (reg:SI 18))]
1.1 root 882: ""
1.1.1.3 ! root 883: "@
! 884: mov %1,%0\;shll %0\;subc %0,%0 ! b sidi2
! 885: mov %1,%0\;mov %1,%R0\;shll %0\;subc %0,%0 ! a sidi2"
! 886: [(set_attr "length" "6,8")])
1.1 root 887:
888: (define_insn "extendhisi2"
1.1.1.3 ! root 889: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z,r")
! 890: (sign_extend:SI (match_operand:HI 1 "arith_operand" "r,u,m")))]
1.1 root 891: ""
1.1.1.3 ! root 892: "@
! 893: exts.w %1,%0
! 894: mov.w %1,%0
! 895: mov.w %1,%0"
! 896: [(set_attr "type" "arith,load,load")])
1.1 root 897:
898: (define_insn "extendqisi2"
1.1.1.3 ! root 899: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z,r")
! 900: (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,U,m")))]
1.1 root 901: ""
1.1.1.3 ! root 902: "@
! 903: exts.b %1,%0
! 904: mov.b %1,%0 !p9
! 905: mov.b %1,%0 !p8"
! 906: [(set_attr "type" "arith,load,load")])
1.1 root 907:
908: (define_insn "extendqihi2"
1.1.1.3 ! root 909: [(set (match_operand:HI 0 "arith_reg_operand" "=r,z,r")
! 910: (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,U,m")))]
1.1 root 911: ""
1.1.1.3 ! root 912: "@
! 913: exts.b %1,%0
! 914: mov.b %1,%0 !p7
! 915: mov.b %1,%0 ! p6"
! 916: [(set_attr "type" "arith,load,load")])
1.1 root 917:
918:
919: ;; -------------------------------------------------------------------------
920: ;; Move instructions
921: ;; -------------------------------------------------------------------------
922:
1.1.1.3 ! root 923: ;; define push and pop so it is easy for sh.c
! 924:
! 925: (define_insn "push"
! 926: [(set (mem:SI (pre_dec:SI (reg:SI 15)))
! 927: (match_operand:SI 0 "register_operand" "r,lx"))]
! 928: ""
! 929: "@
! 930: mov.l %0,@-r15
! 931: sts.l %0,@-r15 ! push"
! 932: [(set_attr "type" "store")
! 933: (set_attr "hit_stack" "yes")])
! 934:
! 935: (define_insn "pop"
! 936: [(set (match_operand:SI 0 "register_operand" "=r,lx")
! 937: (mem:SI (post_inc:SI (reg:SI 15))))]
! 938: ""
! 939: "@
! 940: mov.l @r15+,%0
! 941: lds.l @r15+,%0"
! 942: [(set_attr "type" "load,pload")
! 943: (set_attr "hit_stack" "yes")])
! 944:
1.1 root 945: (define_insn ""
1.1.1.2 root 946: [(set (match_operand:SI 0 "push_operand" "=<,<")
1.1.1.3 ! root 947: (match_operand:SI 1 "arith_reg_operand" "r,xl"))]
1.1.1.2 root 948: ""
949: "@
950: mov.l %1,%0
1.1.1.3 ! root 951: sts.l %1,%0"
1.1.1.2 root 952: [(set_attr "type" "store")])
1.1 root 953:
1.1.1.2 root 954: (define_insn ""
1.1.1.3 ! root 955: [(set (match_operand:SI 0 "arith_reg_operand" "=r,xl")
1.1.1.2 root 956: (match_operand:SI 1 "pop_operand" "=>,>"))]
1.1 root 957: ""
1.1.1.2 root 958: "@
959: mov.l %1,%0
1.1.1.3 ! root 960: lds.l %1,%0"
! 961: [(set_attr "type" "load")])
1.1.1.2 root 962:
1.1.1.3 ! root 963: (define_insn "clrt"
! 964: [(set (reg:SI 18) (const_int 0))]
1.1.1.2 root 965: ""
1.1.1.3 ! root 966: "clrt")
1.1.1.2 root 967:
1.1.1.3 ! root 968: ;(define_insn "movsi_pi"
! 969: ; [(set (match_operand:SI 0 "general_movdst_operand" "=r")
! 970: ; (mem:SI (post_inc (match_operand:SI 1 "register_operand" "r"))))]
! 971: ; ""
! 972: ; "mov.l @%1,%0\;add #4,%1"
! 973: ; [(set_attr "length" "4")])
1.1.1.2 root 974:
975:
1.1 root 976: (define_insn "movsi_i"
1.1.1.3 ! root 977: [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,<m,<,xl,xl,t,r")
! 978: (match_operand:SI 1 "general_movsrc_operand" "Q,rI,>m,xl,t,r,xl,r,>,r,i"))]
1.1 root 979: ""
980: "@
1.1.1.3 ! root 981: mov.l %1,%0
1.1 root 982: mov %1,%0
983: mov.l %1,%0
1.1.1.3 ! root 984: sts %1,%0
! 985: movt %0
1.1 root 986: mov.l %1,%0
1.1.1.3 ! root 987: sts.l %1,%0
1.1.1.2 root 988: lds %1,%0
1.1.1.3 ! root 989: lds.l %1,%0
1.1.1.2 root 990: tst %1,%1\;bt T%*\;bra F%*\;sett\;T%*:clrt\;F%*:%^
1.1.1.3 ! root 991: fake %1,%0"
! 992: [(set_attr "type" "pcloadsi,move,load,move,store,store,move,load,move,move,move")])
! 993:
1.1 root 994: (define_expand "movsi"
1.1.1.3 ! root 995: [(set (match_operand:SI 0 "general_movdst_operand" "")
! 996: (match_operand:SI 1 "general_movsrc_operand" ""))]
1.1 root 997: ""
1.1.1.3 ! root 998:
! 999: "{ if (prepare_move_operands(operands, SImode)) DONE; } ")
! 1000:
1.1 root 1001:
1002: (define_insn "movqi_i"
1.1.1.3 ! root 1003: [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,>m,r,r,l")
! 1004: (match_operand:QI 1 "general_movsrc_operand" "ri,<m,r,t,l,r"))]
! 1005: "arith_reg_operand (operands[0], QImode)
! 1006: || arith_reg_operand (operands[1], QImode)"
1.1 root 1007: "@
1008: mov %1,%0
1.1.1.3 ! root 1009: mov.b %1,%0
! 1010: mov.b %1,%0
! 1011: movt %0
1.1 root 1012: sts %1,%0
1.1.1.3 ! root 1013: lds %1,%0"
! 1014: [(set_attr "length" "2,2,2,2,2,2")
! 1015: (set_attr "type" "move,load,store,move,move,move")])
1.1 root 1016:
1017: (define_expand "movqi"
1018: [(set (match_operand:QI 0 "general_operand" "")
1019: (match_operand:QI 1 "general_operand" ""))]
1020: ""
1.1.1.3 ! root 1021: "if (prepare_move_operands(operands, QImode)) DONE; ")
1.1 root 1022:
1023: (define_insn "movhi_i"
1.1.1.3 ! root 1024: [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,<m,r,r,l")
! 1025: (match_operand:HI 1 "general_movsrc_operand" "Q,rI,>m,t,r,i,l,r"))]
1.1 root 1026: ""
1027: "@
1028: mov.w %1,%0
1.1.1.3 ! root 1029: mov %1,%0
1.1 root 1030: mov.w %1,%0
1.1.1.3 ! root 1031: movt %0
1.1 root 1032: mov.w %1,%0
1.1.1.3 ! root 1033: fake %1,%0
1.1 root 1034: sts %1,%0
1.1.1.3 ! root 1035: lds %1,%0"
! 1036: [(set_attr "length" "*,2,2,2,2,2,2,2")
! 1037: (set_attr "type" "pcloadhi,move,load,move,store,move,move,move")])
1.1 root 1038:
1039: (define_expand "movhi"
1.1.1.3 ! root 1040: [(set (match_operand:HI 0 "general_movdst_operand" "")
! 1041: (match_operand:HI 1 "general_movsrc_operand" ""))]
1.1 root 1042: ""
1.1.1.3 ! root 1043: "if (prepare_move_operands (operands, HImode)) DONE;")
! 1044:
1.1 root 1045: (define_insn ""
1046: [(set (match_operand:DI 0 "push_operand" "=<")
1047: (match_operand:DI 1 "arith_reg_operand" "r"))]
1048: ""
1049: "mov.l %R1,%0\;mov.l %1,%0"
1.1.1.2 root 1050: [(set_attr "length" "4")
1051: (set_attr "type" "store")])
1.1 root 1052:
1.1.1.3 ! root 1053: (define_insn ""
! 1054: [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r")
! 1055: (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i"))]
! 1056: "register_operand (operands[0], DImode)
! 1057: || register_operand (operands[1], DImode)"
! 1058: "* return output_movedouble (insn, operands, DImode);"
! 1059: [(set_attr "length" "*,4,4,4,4")
! 1060: (set_attr "type" "pcloadsi,move,load,store,move")])
! 1061:
! 1062: ;; If the output is a register and the input is memory, we have to be careful
! 1063: ;; and see which word needs to be loaded first.
! 1064: ;;
! 1065: (define_split
! 1066: [(set (match_operand:DI 0 "general_movdst_operand" "")
! 1067: (match_operand:DI 1 "general_movsrc_operand" ""))]
! 1068: "! (GET_CODE (operands[0]) == REG
! 1069: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
! 1070: && ! (GET_CODE (operands[1]) == REG
! 1071: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
! 1072: && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
! 1073: && ! reload_completed
! 1074: && reg_overlap_mentioned_p (operands[0], operands[1]))
! 1075: && ! EXTRA_CONSTRAINT_Q (operands[1])"
! 1076: [(set (match_dup 2) (match_dup 3))
! 1077: (set (match_dup 4) (match_dup 5))]
! 1078: "
! 1079: { if (GET_CODE (operands[0]) != REG
! 1080: || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
! 1081: operands[1], 0))
! 1082: {
! 1083: operands[2] = operand_subword (operands[0], 0, 0, DImode);
! 1084: operands[3] = operand_subword (operands[1], 0, 0, DImode);
! 1085: operands[4] = operand_subword (operands[0], 1, 0, DImode);
! 1086: operands[5] = operand_subword (operands[1], 1, 0, DImode);
! 1087: }
! 1088: else
! 1089: {
! 1090: operands[2] = operand_subword (operands[0], 1, 0, DImode);
! 1091: operands[3] = operand_subword (operands[1], 1, 0, DImode);
! 1092: operands[4] = operand_subword (operands[0], 0, 0, DImode);
! 1093: operands[5] = operand_subword (operands[1], 0, 0, DImode);
! 1094: }
1.1.1.2 root 1095:
1.1.1.3 ! root 1096: if (operands[2] == 0 || operands[3] == 0
! 1097: || operands[4] == 0 || operands[5] == 0)
! 1098: FAIL;
! 1099: }")
1.1 root 1100:
1.1.1.3 ! root 1101:
1.1 root 1102: (define_expand "movdi"
1.1.1.3 ! root 1103: [(set (match_operand:DI 0 "general_movdst_operand" "")
! 1104: (match_operand:DI 1 "general_movsrc_operand" ""))]
1.1 root 1105: ""
1.1.1.3 ! root 1106: "if ( prepare_move_operands(operands, DImode)) DONE; ")
1.1 root 1107:
1108: (define_insn ""
1109: [(set (match_operand:DF 0 "push_operand" "=<")
1110: (match_operand:DF 1 "arith_reg_operand" "r"))]
1111: ""
1.1.1.3 ! root 1112: "mov.l %R1,%0\;mov.l %1,%0"
1.1.1.2 root 1113: [(set_attr "length" "4")
1114: (set_attr "type" "store")])
1.1 root 1115:
1116: (define_insn "movdf_k"
1.1.1.3 ! root 1117: [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,m")
! 1118: (match_operand:DF 1 "general_movsrc_operand" "r,m,r"))]
! 1119: "register_operand (operands[0], DFmode)
! 1120: || register_operand (operands[1], DFmode)"
! 1121: "* return output_movedouble (insn, operands, DFmode);"
1.1.1.2 root 1122: [(set_attr "length" "4")
1123: (set_attr "type" "move,load,store")])
1.1 root 1124:
1.1.1.3 ! root 1125: ;; If the output is a register and the input is memory, we have to be careful
! 1126: ;; and see which word needs to be loaded first.
! 1127: ;;
! 1128: (define_split
! 1129: [(set (match_operand:DF 0 "general_movdst_operand" "")
! 1130: (match_operand:DF 1 "general_movsrc_operand" ""))]
! 1131: "! (GET_CODE (operands[0]) == REG
! 1132: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
! 1133: && ! (GET_CODE (operands[1]) == REG
! 1134: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
! 1135: && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
! 1136: && ! reload_completed
! 1137: && reg_overlap_mentioned_p (operands[0], operands[1]))"
! 1138: [(set (match_dup 2) (match_dup 3))
! 1139: (set (match_dup 4) (match_dup 5))]
! 1140: "
! 1141: { if (GET_CODE (operands[0]) != REG
! 1142: || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
! 1143: operands[1], 0))
! 1144: {
! 1145: operands[2] = operand_subword (operands[0], 0, 0, DFmode);
! 1146: operands[3] = operand_subword (operands[1], 0, 0, DFmode);
! 1147: operands[4] = operand_subword (operands[0], 1, 0, DFmode);
! 1148: operands[5] = operand_subword (operands[1], 1, 0, DFmode);
! 1149: }
! 1150: else
! 1151: {
! 1152: operands[2] = operand_subword (operands[0], 1, 0, DFmode);
! 1153: operands[3] = operand_subword (operands[1], 1, 0, DFmode);
! 1154: operands[4] = operand_subword (operands[0], 0, 0, DFmode);
! 1155: operands[5] = operand_subword (operands[1], 0, 0, DFmode);
! 1156: }
! 1157:
! 1158: if (operands[2] == 0 || operands[3] == 0
! 1159: || operands[4] == 0 || operands[5] == 0)
! 1160: FAIL;
! 1161: }")
! 1162:
! 1163:
1.1 root 1164: (define_expand "movdf"
1.1.1.3 ! root 1165: [(set (match_operand:DF 0 "general_movdst_operand" "")
! 1166: (match_operand:DF 1 "general_movsrc_operand" ""))]
1.1 root 1167: ""
1.1.1.3 ! root 1168: "{ if (prepare_move_operands(operands, DFmode)) DONE; } ")
1.1 root 1169:
1170: (define_insn ""
1171: [(set (match_operand:SF 0 "push_operand" "=<")
1172: (match_operand:SF 1 "arith_reg_operand" "r"))]
1173: ""
1.1.1.2 root 1174: "mov.l %1,%0"
1175: [(set_attr "type" "store")])
1.1 root 1176:
1177: (define_insn "movsf_i"
1.1.1.3 ! root 1178: [(set (match_operand:SF 0 "general_movdst_operand" "=>,r,r,r,r,m,l,r")
! 1179: (match_operand:SF 1 "general_movsrc_operand" "r,<,r,I,m,r,r,l"))]
1.1 root 1180: ""
1181: "@
1.1.1.3 ! root 1182: mov.l %1,@%N0\;add #4,%N0 !bad
! 1183: add #-4,%1\;mov.l @%N1,%0 !bad
1.1 root 1184: mov %1,%0
1185: mov %1,%0
1186: mov.l %1,%0
1187: mov.l %1,%0
1.1.1.2 root 1188: lds %1,%0
1.1.1.3 ! root 1189: sts %1,%0"
! 1190: [(set_attr "type" "store,load,move,move,load,store,move,move")
! 1191: (set_attr "length" "4,4,*,*,*,*,*,*")])
1.1 root 1192:
1193: (define_expand "movsf"
1.1.1.3 ! root 1194: [(set (match_operand:SF 0 "general_movdst_operand" "")
! 1195: (match_operand:SF 1 "general_movsrc_operand" ""))]
1.1 root 1196: ""
1.1.1.3 ! root 1197: "if (prepare_move_operands (operands, SFmode)) DONE;")
1.1 root 1198:
1199:
1200: ;; ------------------------------------------------------------------------
1201: ;; Define the real conditional branch instructions.
1202: ;; ------------------------------------------------------------------------
1203:
1204: (define_insn "branch_true"
1205: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
1206: (label_ref (match_operand 0 "" ""))
1207: (pc)))]
1208: ""
1209: "* return output_branch (1, insn);"
1210: [(set_attr "type" "cbranch")])
1211:
1212: (define_insn "branch_false"
1213: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
1214: (label_ref (match_operand 0 "" ""))
1215: (pc)))]
1216: ""
1217: "* return output_branch (0, insn);"
1218: [(set_attr "type" "cbranch")])
1219:
1220: (define_insn "inverse_branch_true"
1221: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
1222: (pc)
1223: (label_ref (match_operand 0 "" ""))))]
1224: ""
1225: "* return output_branch (0, insn);"
1226: [(set_attr "type" "cbranch")])
1227:
1228: (define_insn "inverse_branch_false"
1229: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
1230: (pc)
1231: (label_ref (match_operand 0 "" ""))))]
1232: ""
1233: "* return output_branch (1, insn);"
1234: [(set_attr "type" "cbranch")])
1235:
1236:
1237: ;; Conditional branch insns
1238:
1239: (define_expand "beq"
1240: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
1241: (set (pc)
1242: (if_then_else (eq (reg:SI 18)
1243: (const_int 1))
1244: (label_ref (match_operand 0 "" ""))
1245: (pc)))]
1246: ""
1.1.1.3 ! root 1247: "from_compare (operands, EQ);")
1.1 root 1248:
1249: ; There is no bne compare, so we reverse the branch arms.
1250:
1251: (define_expand "bne"
1252: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
1253: (set (pc)
1254: (if_then_else (eq (reg:SI 18)
1255: (const_int 1))
1256: (pc)
1257: (label_ref (match_operand 0 "" ""))))]
1258: ""
1.1.1.3 ! root 1259: "from_compare (operands, NE);")
1.1 root 1260:
1261: (define_expand "bgt"
1262: [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
1263: (set (pc)
1264: (if_then_else (eq (reg:SI 18)
1265: (const_int 1))
1266: (label_ref (match_operand 0 "" ""))
1.1.1.3 ! root 1267: (pc))) ]
1.1 root 1268: ""
1.1.1.3 ! root 1269: "from_compare (operands, GT);")
1.1 root 1270:
1271: (define_expand "blt"
1.1.1.3 ! root 1272: [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
1.1 root 1273: (set (pc)
1.1.1.3 ! root 1274: (if_then_else (eq (reg:SI 18)(const_int 1))
! 1275: (pc)
! 1276: (label_ref (match_operand 0 "" ""))))]
1.1 root 1277: ""
1.1.1.3 ! root 1278: "from_compare (operands, LT);")
1.1 root 1279:
1280: (define_expand "ble"
1.1.1.3 ! root 1281: [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
! 1282: (set (pc)
1.1 root 1283: (if_then_else (eq (reg:SI 18)
1284: (const_int 1))
1.1.1.3 ! root 1285: (pc)
! 1286: (label_ref (match_operand 0 "" ""))))
! 1287: ]
1.1 root 1288: ""
1.1.1.3 ! root 1289: "from_compare (operands, LE);")
1.1 root 1290:
1291: (define_expand "bge"
1292: [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
1293: (set (pc)
1294: (if_then_else (eq (reg:SI 18)
1295: (const_int 1))
1296: (label_ref (match_operand 0 "" ""))
1.1.1.3 ! root 1297: (pc))) ]
1.1 root 1298: ""
1.1.1.3 ! root 1299: "from_compare (operands, GE);")
1.1 root 1300:
1301: (define_expand "bgtu"
1302: [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
1303: (set (pc)
1304: (if_then_else (eq (reg:SI 18)
1.1.1.3 ! root 1305: (const_int 1))
1.1 root 1306: (label_ref (match_operand 0 "" ""))
1307: (pc)))]
1308: ""
1.1.1.3 ! root 1309: "from_compare (operands, GTU); ")
1.1 root 1310:
1311: (define_expand "bltu"
1.1.1.3 ! root 1312: [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
1.1 root 1313: (set (pc)
1.1.1.3 ! root 1314: (if_then_else (eq (reg:SI 18)
! 1315: (const_int 1))
! 1316: (pc)
! 1317: (label_ref (match_operand 0 "" ""))))]
1.1 root 1318: ""
1.1.1.3 ! root 1319: "from_compare (operands, LTU);")
1.1 root 1320:
1321: (define_expand "bgeu"
1322: [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
1323: (set (pc)
1324: (if_then_else (eq (reg:SI 18)
1.1.1.3 ! root 1325: (const_int 1))
1.1 root 1326: (label_ref (match_operand 0 "" ""))
1.1.1.3 ! root 1327: (pc)))
! 1328: ]
1.1 root 1329: ""
1.1.1.3 ! root 1330: "from_compare (operands, GEU);")
1.1 root 1331:
1332: (define_expand "bleu"
1.1.1.3 ! root 1333: [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
1.1 root 1334: (set (pc)
1335: (if_then_else (eq (reg:SI 18)
1.1.1.3 ! root 1336: (const_int 1))
! 1337: (pc)
! 1338: (label_ref (match_operand 0 "" ""))))]
1.1 root 1339: ""
1.1.1.3 ! root 1340: "from_compare (operands, LEU);")
1.1 root 1341:
1342:
1343: ;; ------------------------------------------------------------------------
1344: ;; Jump and linkage insns
1345: ;; ------------------------------------------------------------------------
1346:
1.1.1.3 ! root 1347: (define_insn "jump"
1.1 root 1348: [(set (pc)
1349: (label_ref (match_operand 0 "" "")))]
1350: ""
1351: "*
1352: {
1.1.1.3 ! root 1353: if (get_attr_length(insn) == 10)
1.1 root 1354: {
1.1.1.3 ! root 1355: return output_far_jump(insn, operands[0]);
1.1 root 1356: }
1357: else
1358: {
1359: return \"bra %l0%#\";
1360: }
1361: }"
1362: [(set_attr "type" "jump")
1363: (set_attr "needs_delay_slot" "yes")])
1364:
1.1.1.3 ! root 1365:
! 1366: (define_insn "bsr"
! 1367: [(call (mem:SI (match_operand 0 "bsr_operand" "i"))
! 1368: (match_operand 1 "" ""))
! 1369: (clobber (reg:SI 17))]
! 1370: "TARGET_BSR"
! 1371: "bsr %O0%#"
! 1372: [(set_attr "needs_delay_slot" "yes")
! 1373: (set_attr "in_delay_slot" "no")
! 1374: (set_attr "length" "4")])
1.1 root 1375:
1376: (define_insn "calli"
1377: [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
1378: (match_operand 1 "" ""))
1379: (clobber (reg:SI 17))]
1380: ""
1381: "jsr @%0%#"
1382: [(set_attr "needs_delay_slot" "yes")
1383: (set_attr "in_delay_slot" "no")
1384: (set_attr "length" "4")])
1385:
1.1.1.3 ! root 1386: (define_insn "bsr_value"
! 1387: [(set (match_operand 0 "" "=rf")
! 1388: (call (mem:SI (match_operand 1 "bsr_operand" "i"))
! 1389: (match_operand 2 "" "")))
! 1390: (clobber (reg:SI 17))]
! 1391: "TARGET_BSR"
! 1392: "bsr %O1%#"
! 1393: [(set_attr "needs_delay_slot" "yes")
! 1394: (set_attr "in_delay_slot" "no")
! 1395: (set_attr "length" "4")])
! 1396:
1.1 root 1397: (define_insn "call_valuei"
1398: [(set (match_operand 0 "" "=rf")
1399: (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
1400: (match_operand 2 "" "")))
1401: (clobber (reg:SI 17))]
1402: ""
1403: "jsr @%1%#"
1404: [(set_attr "needs_delay_slot" "yes")
1405: (set_attr "in_delay_slot" "no")
1406: (set_attr "length" "4")])
1407:
1408: (define_expand "call"
1409: [(parallel[(call (match_operand 0 "arith_reg_operand" "o")
1410: (match_operand 1 "" ""))
1411: (clobber (reg:SI 17))])]
1412: ""
1.1.1.3 ! root 1413: "expand_acall(0, operands); DONE;")
1.1 root 1414:
1415: (define_expand "call_value"
1416: [(parallel[(set (match_operand 0 "" "=rf")
1417: (call (match_operand 1 "arith_reg_operand" "o")
1418: (match_operand 2 "" "")))
1419: (clobber (reg:SI 17))])]
1420: ""
1.1.1.3 ! root 1421: "expand_acall(1, operands); DONE; ")
1.1 root 1422:
1423: (define_insn "indirect_jump"
1424: [(set (pc)
1425: (match_operand:SI 0 "arith_reg_operand" "r"))]
1426: ""
1.1.1.2 root 1427: "jmp @%0%#"
1.1 root 1428: [(set_attr "needs_delay_slot" "yes")
1429: (set_attr "in_delay_slot" "no")
1430: (set_attr "length" "4")])
1431:
1432:
1433: ;; ------------------------------------------------------------------------
1434: ;; Misc insns
1435: ;; ------------------------------------------------------------------------
1436:
1.1.1.3 ! root 1437: (define_insn "dect"
! 1438: [(parallel[
! 1439: (set (reg:SI 18)
! 1440: (eq:SI (match_operand:SI 0 "register_operand" "=r")
! 1441: (const_int 1)))
! 1442:
! 1443: (set (match_dup 0)
! 1444: (plus:SI (match_dup 0)
! 1445: (const_int -1)))])]
! 1446: "TARGET_SH2"
! 1447: "dt %0")
1.1 root 1448:
1449: (define_insn "nop"
1450: [(const_int 0)]
1451: ""
1452: "or r0,r0")
1453:
1.1.1.3 ! root 1454: ; experimental use of auto inc and dec made these...
! 1455: ; can be deleted
! 1456:
! 1457: (define_insn "fake"
! 1458: [(set (match_operand:QI 0 "register_operand" "=r")
! 1459: (mem:QI (pre_dec:SI (match_operand:SI 1 "register_operand" "r"))))]
! 1460: ""
! 1461: "add #-1,%1\;mov.b @%1,%0 !bad"
! 1462: [(set_attr "length" "4")])
! 1463:
! 1464: ;; Load address of a label. This is only generated by the casesi expand.
! 1465:
! 1466: (define_insn "mova"
! 1467: [(set (reg:SI 0)
! 1468: (label_ref (match_operand 0 "" "")))]
! 1469: ""
! 1470: "mova %O0,r0"
! 1471: [(set_attr "in_delay_slot" "no")])
! 1472:
! 1473: ;; case instruction for switch statements.
! 1474:
! 1475: ;; Operand 0 is index
! 1476: ;; operand 1 is the minimum bound
! 1477: ;; operand 2 is the maximum bound - minimum bound + 1
! 1478: ;; operand 3 is CODE_LABEL for the table;
! 1479: ;; operand 4 is the CODE_LABEL to go to if index out of range.
! 1480:
! 1481: (define_expand "casesi"
! 1482: [(set (match_dup 5) (match_operand:SI 0 "arith_reg_operand" ""))
! 1483: (set (match_dup 5) (minus:SI (match_dup 5)
! 1484: (match_operand:SI 1 "arith_operand" "")))
! 1485: (set (reg:SI 18)
! 1486: (gtu:SI (match_dup 5)
! 1487: (match_operand:SI 2 "arith_operand" "")))
! 1488: (set (pc)
! 1489: (if_then_else (eq (reg:SI 18)
! 1490: (const_int 1))
! 1491: (label_ref (match_operand 4 "" ""))
! 1492: (pc)))
! 1493: (set (match_dup 6) (match_dup 5))
! 1494: (parallel[(set (match_dup 6) (ashift:SI (match_dup 6) (match_dup 7)))
! 1495: (clobber (reg:SI 18))])
! 1496: (set (reg:SI 0) (label_ref (match_operand 3 "" "")))
! 1497: (parallel[(set (reg:SI 0) (plus:SI (reg:SI 0)
! 1498: (mem:HI (plus:SI (reg:SI 0)
! 1499: (match_dup 6)))))
! 1500: (set (match_dup 6) (mem:HI (plus:SI (reg:SI 0) (match_dup 6))))])
! 1501: (set (pc) (reg:SI 0))]
! 1502: ""
! 1503: "
! 1504: {
! 1505: operands[1] = copy_to_mode_reg (SImode, operands[1]);
! 1506: operands[2] = copy_to_mode_reg (SImode, operands[2]);
! 1507: operands[5] = gen_reg_rtx (SImode);
! 1508: operands[6] = gen_reg_rtx (SImode);
! 1509: operands[7] = GEN_INT (TARGET_BIGTABLE ? 2 : 1);
! 1510: }")
! 1511:
! 1512: (define_insn "casesi_worker"
! 1513: [(set (reg:SI 0)
! 1514: (plus:SI (reg:SI 0)
! 1515: (mem:HI (plus:SI (reg:SI 0)
! 1516: (match_operand:SI 0 "register_operand" "=r")))))
! 1517: (set (match_dup 0) (mem:HI (plus:SI (reg:SI 0)
! 1518: (match_dup 0))))]
1.1 root 1519: ""
1.1.1.3 ! root 1520: "*
! 1521: if (TARGET_BIGTABLE)
! 1522: return \"mov.l @(r0,%0),%0\;add %0,r0\";
! 1523: else
! 1524: return \"mov.w @(r0,%0),%0\;add %0,r0\";"
1.1 root 1525: [(set_attr "needs_delay_slot" "no")
1526: (set_attr "in_delay_slot" "no")
1.1.1.3 ! root 1527: (set_attr "length" "4")])
! 1528:
1.1.1.2 root 1529:
1530: (define_insn "return"
1.1.1.3 ! root 1531: [(return)]
! 1532: "reload_completed"
! 1533: "%@ %#"
! 1534: [(set_attr "type" "return")])
1.1.1.2 root 1535:
1536: (define_expand "prologue"
1537: [(const_int 0)]
1538: ""
1539: "sh_expand_prologue (); DONE;")
1540:
1541: (define_expand "epilogue"
1542: [(return)]
1543: ""
1544: "sh_expand_epilogue ();")
1545:
1546: (define_insn "blockage"
1547: [(unspec_volatile [(const_int 0)] 0)]
1548: ""
1549: ""
1550: [(set_attr "length" "0")])
1551:
1.1 root 1552:
1553: ;; ------------------------------------------------------------------------
1554: ;; Scc instructions
1555: ;; ------------------------------------------------------------------------
1556:
1.1.1.3 ! root 1557: (define_insn "movt"
1.1 root 1558: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1.1.1.3 ! root 1559: (eq:SI (reg:SI 18) (const_int 1)))]
1.1 root 1560: ""
1561: "movt %0 ! ")
1562:
1563: (define_expand "seq"
1564: [(set (match_operand:SI 0 "arith_reg_operand" "")
1565: (match_dup 1))]
1566: ""
1567: "operands[1] = prepare_scc_operands (EQ);")
1568:
1569: (define_expand "slt"
1570: [(set (match_operand:SI 0 "arith_reg_operand" "")
1571: (match_dup 1))]
1572: ""
1573: "operands[1] = prepare_scc_operands (LT);")
1574:
1575: (define_expand "sle"
1576: [(set (match_operand:SI 0 "arith_reg_operand" "")
1577: (match_dup 1))]
1578: ""
1579: "operands[1] = prepare_scc_operands (LE);")
1580:
1581: (define_expand "sgt"
1582: [(set (match_operand:SI 0 "arith_reg_operand" "")
1583: (match_dup 1))]
1584: ""
1585: "operands[1] = prepare_scc_operands (GT);")
1586:
1587: (define_expand "sge"
1588: [(set (match_operand:SI 0 "arith_reg_operand" "")
1589: (match_dup 1))]
1590: ""
1591: "operands[1] = prepare_scc_operands (GE);")
1592:
1593: (define_expand "sgtu"
1594: [(set (match_operand:SI 0 "arith_reg_operand" "")
1595: (match_dup 1))]
1596: ""
1597: "operands[1] = prepare_scc_operands (GTU);")
1598:
1599: (define_expand "sltu"
1600: [(set (match_operand:SI 0 "arith_reg_operand" "")
1601: (match_dup 1))]
1602: ""
1603: "operands[1] = prepare_scc_operands (LTU);")
1604:
1605: (define_expand "sleu"
1606: [(set (match_operand:SI 0 "arith_reg_operand" "")
1607: (match_dup 1))]
1608: ""
1609: "operands[1] = prepare_scc_operands (LEU);")
1610:
1611: (define_expand "sgeu"
1612: [(set (match_operand:SI 0 "arith_reg_operand" "")
1613: (match_dup 1))]
1614: ""
1615: "operands[1] = prepare_scc_operands (GEU);")
1616:
1617: (define_expand "sne"
1618: [(set (match_operand:SI 0 "arith_reg_operand" "")
1619: (match_dup 1))
1620: (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))]
1621: ""
1622: "operands[1] = prepare_scc_operands (EQ);")
1623:
1624: ;; -------------------------------------------------------------------------
1625: ;; Peepholes
1626: ;; -------------------------------------------------------------------------
1627:
1628:
1629: (define_peephole
1630: [(set (match_operand:QI 0 "arith_reg_operand" "")
1631: (mem:QI (match_operand:SI 1 "arith_reg_operand" "")))
1632: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
1.1.1.3 ! root 1633: "REGNO (operands[1]) != REGNO (operands[0])"
1.1 root 1634: "mov.b @%1+,%0")
1635:
1636: (define_peephole
1637: [(set (match_operand:HI 0 "arith_reg_operand" "")
1638: (mem:HI (match_operand:SI 1 "arith_reg_operand" "")))
1639: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))]
1.1.1.3 ! root 1640: "REGNO (operands[1]) != REGNO (operands[0])"
1.1 root 1641: "mov.w @%1+,%0")
1642:
1643: (define_peephole
1644: [(set (match_operand:SI 0 "arith_reg_operand" "")
1645: (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
1646: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
1.1.1.3 ! root 1647: "REGNO (operands[1]) != REGNO (operands[0])"
1.1 root 1648: "mov.l @%1+,%0")
1649:
1.1.1.2 root 1650: (define_peephole
1651: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.3 ! root 1652: (match_operand:QI 1 "memory_operand" "g"))
1.1.1.2 root 1653: (set (match_operand:SI 2 "register_operand" "=r")
1654: (sign_extend:SI (match_dup 0)))]
1.1.1.3 ! root 1655: "REGNO (operands[0]) == REGNO (operands[2])"
! 1656: "mov.b %1,%0 !p 5")
1.1.1.2 root 1657:
1658: (define_peephole
1659: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.3 ! root 1660: (match_operand:QI 1 "general_movsrc_operand" "g"))
1.1.1.2 root 1661: (set (match_operand:SI 2 "register_operand" "=r")
1662: (sign_extend:SI (match_dup 0)))]
1.1.1.3 ! root 1663: "REGNO (operands[0]) != REGNO (operands[2])
! 1664: && 0 && dead_or_set_p (insn, operands[0])"
! 1665: "mov.b %1,%2 ! p4")
1.1.1.2 root 1666:
1.1.1.3 ! root 1667:
! 1668: ;; -------------------------------------------------------------------------
! 1669: ;; Peepholes
! 1670: ;; -------------------------------------------------------------------------
1.1.1.2 root 1671:
1.1.1.3 ! root 1672: (define_peephole
! 1673: [(set (reg:SI 0) (label_ref (match_operand 0 "" "")))
! 1674: (set (match_operand:SI 1 "register_operand" "=r")
! 1675: (reg:SI 0))
! 1676: (set (reg:SI 0) (label_ref (match_dup 0)))
! 1677: (set (match_operand:SI 2 "register_operand" "=r")
! 1678: (reg:SI 0))]
! 1679: ""
! 1680: "mova %O0,r0\;mov r0,%1\;mov r0,%2"
! 1681: [(set_attr "length" "6")
! 1682: (set_attr "in_delay_slot" "no")])
1.1.1.2 root 1683:
1.1.1.3 ! root 1684:
! 1685: ;; -------------------------------------------------------------------------
! 1686: ;; Combine patterns
! 1687: ;; -------------------------------------------------------------------------
! 1688:
! 1689: (define_insn ""
1.1.1.2 root 1690: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.3 ! root 1691: (plus:SI (match_operand:HI 1 "register_operand" "%0")
! 1692: (match_operand:SI 2 "register_operand" "r")))]
! 1693: ""
! 1694: "add %2,%0 ! why")
! 1695:
! 1696: (define_insn "addc_2"
! 1697: [(set (match_operand:SI 0 "arith_reg_operand" "=&r")
! 1698: (plus:SI (reg:SI 18)
! 1699: (match_operand:SI 1 "arith_reg_operand" "r")))
! 1700: (clobber (reg:SI 18))]
! 1701: ""
! 1702: "mov #0,%0\;addc %1,%0 ! addc1"
! 1703: [(set_attr "length" "4")])
! 1704:
! 1705: (define_insn "combine_1"
! 1706: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! 1707: (sign_extend:SI (mem:QI (match_operand:SI 1 "arith_reg_operand" "r"))))]
! 1708: ""
! 1709: "mov.b @%1,%0 ! why"
! 1710: [(set_attr "type" "load")])
1.1.1.2 root 1711:
1.1.1.3 ! root 1712: (define_insn "combine_2"
! 1713: [(set (reg:SI 18)
! 1714: (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
! 1715: (match_operand:SI 1 "arith_operand" "L,r"))
! 1716: (const_int 0)))]
! 1717: ""
! 1718: "tst %1,%0 !t2c")
! 1719:
! 1720: (define_split
! 1721: [(set (pc)
! 1722: (if_then_else
! 1723: (match_operator 2 "equality_operator" [(match_operand:SI 0 "arith_reg_operand" "r")
! 1724: (const_int 0)])
! 1725: (label_ref (match_operand 1 "" ""))
! 1726: (pc)))
! 1727: (clobber (reg:SI 18))]
! 1728: ""
! 1729: [(set (reg:SI 18) (eq:SI (and:SI (match_dup 0) (match_dup 0))
! 1730: (const_int 0)))
! 1731: (set (pc)
! 1732: (if_then_else (match_op_dup 2 [(reg:SI 18) (const_int 1)])
! 1733: (label_ref (match_dup 1))
! 1734: (pc)))]
! 1735: "")
! 1736:
! 1737: ;; -------------------------------------------------------------------------
! 1738: ;; Instructions to cope with inline literal tables
! 1739: ;; -------------------------------------------------------------------------
! 1740:
! 1741: ; 2 byte integer in line
! 1742:
! 1743: (define_insn "consttable_2"
! 1744: [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
! 1745: ""
! 1746: "*
! 1747: {
! 1748: assemble_integer (operands[0], 2, 1);
! 1749: return \"\";
! 1750: }"
! 1751: [(set_attr "length" "2")
! 1752: (set_attr "in_delay_slot" "no")])
! 1753:
! 1754: ; 4 byte integer in line
! 1755:
! 1756: (define_insn "consttable_4"
! 1757: [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
! 1758: ""
! 1759: "*
! 1760: {
! 1761: assemble_integer (operands[0], 4, 1);
! 1762: return \"\";
! 1763: }"
! 1764: [(set_attr "length" "4")
! 1765: (set_attr "in_delay_slot" "no")])
! 1766:
! 1767: ; 8 byte integer in line
! 1768:
! 1769: (define_insn "consttable_8"
! 1770: [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
! 1771: ""
! 1772: "*
! 1773: {
! 1774: assemble_integer (operands[0], 8, 1);
! 1775: return \"\";
! 1776: }"
! 1777: [(set_attr "length" "8")
! 1778: (set_attr "in_delay_slot" "no")])
! 1779:
! 1780: ; align to a two byte boundary
! 1781:
! 1782: (define_insn "align_2"
! 1783: [(unspec_volatile [(const_int 0)] 10)]
! 1784: ""
! 1785: ".align 1"
! 1786: [(set_attr "length" "0")
! 1787: (set_attr "in_delay_slot" "no")])
! 1788:
! 1789: ; align to a four byte boundary
! 1790:
! 1791: (define_insn "align_4"
! 1792: [(unspec_volatile [(const_int 0)] 5)]
! 1793: ""
! 1794: ".align 2"
! 1795: [(set_attr "in_delay_slot" "no")])
! 1796:
! 1797: ; emitted at the end of the literal table, used to emit the
! 1798: ; 32bit branch labels if needed.
! 1799:
! 1800: (define_insn "consttable_end"
! 1801: [(unspec_volatile [(const_int 0)] 11)]
! 1802: ""
! 1803: "* return output_jump_label_table ();"
! 1804: [(set_attr "in_delay_slot" "no")])
! 1805:
! 1806:
! 1807: ;(define_split
! 1808: ; [(set (subreg:SI (match_operand:QI 0 "register_operand" "=r") 0)
! 1809: ; (plus:SI (subreg:SI (match_operand:QI 1 "general_operand" "g") 0)
! 1810: ; (subreg:SI (match_operand:QI 2 "general_operand" "g") 0)))]
! 1811: ; ""
! 1812: ; [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
! 1813: ; (set (match_dup 1) (subreg:SI (match_dup 3) 0))]
! 1814: ; "operands[3] = gen_reg_rtx(SImode);")
! 1815:
! 1816:
! 1817: ; byte arithmetic involving constants which need to be sign extended can be
! 1818: ; fixed up...
! 1819:
! 1820:
! 1821: (define_split
! 1822: [(set (subreg:SI (match_operand:QI 0 "register_operand" "=r") 0)
! 1823: (plus:SI (subreg:SI (match_operand:QI 1 "register_operand" "0") 0)
! 1824: (subreg:SI (match_operand 2 "immediate_operand" "n") 0)))]
! 1825: ""
! 1826: [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
! 1827: (set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))]
! 1828: "{ int i = INTVAL(operands[2]) & 0xff;
! 1829: if (i > 127) i = i - 256;
! 1830: operands[3] = GEN_INT(i);
! 1831: operands[4] = gen_reg_rtx(SImode);} ")
! 1832:
! 1833:
! 1834: ;; these instructions don't really exist - they are needed
! 1835: ;; before machine_dependent_reorg
! 1836:
! 1837: (define_insn "movsi_k"
! 1838: [(set (match_operand:SI 0 "register_operand" "=r")
! 1839: (match_operand:SI 1 "immediate_operand" ""))]
! 1840: ""
! 1841: "! this is a fake")
! 1842:
! 1843:
! 1844: (define_insn "movhi_k"
! 1845: [(set (match_operand:HI 0 "register_operand" "=r")
! 1846: (match_operand:HI 1 "immediate_operand" ""))]
! 1847: ""
! 1848: "! this is a fake")
! 1849:
! 1850: (define_insn "movdi_k"
! 1851: [(set (match_operand:DI 0 "register_operand" "=r")
! 1852: (match_operand:DI 1 "immediate_operand" ""))]
! 1853: ""
! 1854: "! this is a fake")
! 1855:
! 1856: ;; -------------------------------------------------------------------------
! 1857: ;; Misc
! 1858: ;; -------------------------------------------------------------------------
! 1859:
! 1860:
! 1861: ;; String/block move insn.
! 1862:
! 1863: (define_expand "movstrsi"
! 1864: [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
! 1865: (mem:BLK (match_operand:BLK 1 "" "")))
! 1866: (use (match_operand:SI 2 "nonmemory_operand" ""))
! 1867: (use (match_operand:SI 3 "immediate_operand" ""))
! 1868: (clobber (reg:SI 17))
! 1869: (clobber (reg:SI 4))
! 1870: (clobber (reg:SI 5))
! 1871: (clobber (reg:SI 0))])]
! 1872: ""
! 1873: "
! 1874: {
! 1875: if(expand_block_move (operands))
! 1876: DONE;
! 1877: else FAIL;
! 1878: }")
! 1879:
! 1880: (define_insn "block_move_real"
! 1881: [(parallel [(set (mem:BLK (reg:SI 4))
! 1882: (mem:BLK (reg:SI 5)))
! 1883: (use (match_operand:SI 0 "arith_reg_operand" "r"))
! 1884: (clobber (reg:SI 17))
! 1885: (clobber (reg:SI 4))
! 1886: (clobber (reg:SI 5))
! 1887: (clobber (reg:SI 0))])]
! 1888: ""
! 1889: "jsr @%0%#"
! 1890: [(set_attr "length" "4")
! 1891: (set_attr "type" "sfunc")
! 1892: (set_attr "needs_delay_slot" "yes")])
1.1.1.2 root 1893:
1.1.1.3 ! root 1894: (define_insn "block_lump_real"
! 1895: [(parallel [(set (mem:BLK (reg:SI 4))
! 1896: (mem:BLK (reg:SI 5)))
! 1897: (use (match_operand:SI 0 "arith_reg_operand" "r"))
! 1898: (use (reg:SI 6))
! 1899: (clobber (reg:SI 17))
! 1900: (clobber (reg:SI 4))
! 1901: (clobber (reg:SI 5))
! 1902: (clobber (reg:SI 6))
! 1903: (clobber (reg:SI 0))])]
! 1904: ""
! 1905: "jsr @%0%#"
! 1906: [(set_attr "length" "4")
! 1907: (set_attr "type" "sfunc")
! 1908: (set_attr "needs_delay_slot" "yes")])
! 1909:
! 1910: (define_insn "mac"
! 1911: [(set (reg:SI 21)
! 1912: (mult:SI (sign_extend:SI (mem:HI (post_inc:SI
! 1913: (match_operand:SI 0 "arith_reg_operand" "r"))))
! 1914: (sign_extend:SI (mem:HI (post_inc:SI
! 1915: (match_operand:SI 1 "arith_reg_operand" "r"))))))]
! 1916: ""
! 1917: "mac.w @%0+,@%1+")
1.1.1.2 root 1918:
1.1 root 1919:
1.1.1.3 ! root 1920:
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