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1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3: Contributed by Michael Tiemann ([email protected]).
4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21: /* Note that some other tm.h files include this one and then override
22: many of the definitions that relate to assembler syntax. */
23:
24: #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
25:
1.1.1.2 root 26: /* Provide required defaults for linker -e and -d switches. */
1.1 root 27:
1.1.1.3 ! root 28: #define LINK_SPEC \
! 29: "%{!nostdlib:%{!e*:-e start}} -dc -dp %{static:-Bstatic} %{assert*}"
1.1 root 30:
31: /* Special flags to the Sun-4 assembler when using pipe for input. */
32:
33: #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
34:
1.1.1.3 ! root 35: /* Define macros to distinguish architectures. */
! 36: #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparcv8__}"
! 37:
1.1.1.2 root 38: /* Prevent error on `-sun4' and `-target sun4' options. */
39: /* This used to translate -dalign to -malign, but that is no good
40: because it can't turn off the usual meaning of making debugging dumps. */
1.1 root 41:
1.1.1.2 root 42: #define CC1_SPEC "%{sun4:} %{target:}"
1.1 root 43:
1.1.1.3 ! root 44: #if 0
! 45: /* Sparc ABI says that long double is 4 words.
! 46: ??? This doesn't work yet. */
! 47: #define LONG_DOUBLE_TYPE_SIZE 128
! 48: #endif
! 49:
1.1 root 50: #define PTRDIFF_TYPE "int"
51: #define SIZE_TYPE "int"
52: #define WCHAR_TYPE "short unsigned int"
53: #define WCHAR_TYPE_SIZE 16
54:
1.1.1.2 root 55: /* Omit frame pointer at high optimization levels. */
1.1 root 56:
57: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
58: { \
59: if (OPTIMIZE >= 2) \
60: { \
61: flag_omit_frame_pointer = 1; \
62: } \
63: }
64:
65: /* These compiler options take an argument. We ignore -target for now. */
66:
67: #define WORD_SWITCH_TAKES_ARG(STR) \
68: (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
69: || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
1.1.1.2 root 70: || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
1.1 root 71:
72: /* Names to predefine in the preprocessor for this target machine. */
73:
74: #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
75:
76: /* Print subsidiary information on the compiler version in use. */
77:
78: #define TARGET_VERSION fprintf (stderr, " (sparc)");
79:
80: /* Generate DBX debugging information. */
81:
82: #define DBX_DEBUGGING_INFO
83:
84: /* Run-time compilation parameters selecting different hardware subsets. */
85:
86: extern int target_flags;
87:
88: /* Nonzero if we should generate code to use the fpu. */
89: #define TARGET_FPU (target_flags & 1)
90:
91: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
92: use fast return insns, but lose some generality. */
93: #define TARGET_EPILOGUE (target_flags & 2)
94:
1.1.1.2 root 95: /* Nonzero means that reference doublewords as if they were guaranteed
96: to be aligned...if they aren't, too bad for the user!
1.1.1.3 ! root 97: Like -dalign in Sun cc. */
1.1.1.2 root 98: #define TARGET_HOPE_ALIGN (target_flags & 16)
99:
1.1.1.3 ! root 100: /* Nonzero means make sure all doubles are on 8-byte boundaries.
! 101: This option results in a calling convention that is incompatible with
! 102: every other sparc compiler in the world, and thus should only ever be
! 103: used for experimenting. Also, varargs won't work with it, but it doesn't
! 104: seem worth trying to fix. */
1.1.1.2 root 105: #define TARGET_FORCE_ALIGN (target_flags & 32)
1.1 root 106:
1.1.1.3 ! root 107: /* Nonzero means that we should generate code for a v8 sparc. */
! 108: #define TARGET_V8 (target_flags & 64)
! 109:
! 110: /* Nonzero means that we should generate code for a sparclite. */
! 111: #define TARGET_SPARCLITE (target_flags & 128)
! 112:
1.1 root 113: /* Macro to define tables used to set the flags.
114: This is a list in braces of pairs in braces,
115: each pair being { "NAME", VALUE }
116: where VALUE is the bits to set or minus the bits to clear.
117: An empty string NAME is used to identify the default VALUE. */
118:
119: #define TARGET_SWITCHES \
120: { {"fpu", 1}, \
121: {"soft-float", -1}, \
122: {"epilogue", 2}, \
123: {"no-epilogue", -2}, \
1.1.1.2 root 124: {"hope-align", 16}, \
125: {"force-align", 48}, \
1.1.1.3 ! root 126: {"v8", 64}, \
! 127: {"no-v8", -64}, \
! 128: {"sparclite", 128}, \
! 129: {"no-sparclite", -128}, \
1.1.1.2 root 130: { "", TARGET_DEFAULT}}
1.1 root 131:
132: #define TARGET_DEFAULT 3
133:
134: /* target machine storage layout */
135:
136: /* Define this if most significant bit is lowest numbered
137: in instructions that operate on numbered bit-fields. */
138: #define BITS_BIG_ENDIAN 1
139:
140: /* Define this if most significant byte of a word is the lowest numbered. */
141: /* This is true on the SPARC. */
142: #define BYTES_BIG_ENDIAN 1
143:
144: /* Define this if most significant word of a multiword number is the lowest
145: numbered. */
146: /* Doubles are stored in memory with the high order word first. This
147: matters when cross-compiling. */
148: #define WORDS_BIG_ENDIAN 1
149:
1.1.1.2 root 150: /* number of bits in an addressable storage unit */
1.1 root 151: #define BITS_PER_UNIT 8
152:
153: /* Width in bits of a "word", which is the contents of a machine register.
154: Note that this is not necessarily the width of data type `int';
155: if using 16-bit ints on a 68000, this would still be 32.
156: But on a machine with 16-bit registers, this would be 16. */
157: #define BITS_PER_WORD 32
158: #define MAX_BITS_PER_WORD 32
159:
160: /* Width of a word, in units (bytes). */
161: #define UNITS_PER_WORD 4
162:
163: /* Width in bits of a pointer.
164: See also the macro `Pmode' defined below. */
165: #define POINTER_SIZE 32
166:
167: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
168: #define PARM_BOUNDARY 32
169:
170: /* Boundary (in *bits*) on which stack pointer should be aligned. */
171: #define STACK_BOUNDARY 64
172:
173: /* Allocation boundary (in *bits*) for the code of a function. */
174: #define FUNCTION_BOUNDARY 32
175:
176: /* Alignment of field after `int : 0' in a structure. */
177: #define EMPTY_FIELD_BOUNDARY 32
178:
179: /* Every structure's size must be a multiple of this. */
180: #define STRUCTURE_SIZE_BOUNDARY 8
181:
182: /* A bitfield declared as `int' forces `int' alignment for the struct. */
183: #define PCC_BITFIELD_TYPE_MATTERS 1
184:
185: /* No data type wants to be aligned rounder than this. */
186: #define BIGGEST_ALIGNMENT 64
187:
1.1.1.3 ! root 188: /* The best alignment to use in cases where we have a choice. */
! 189: #define FASTEST_ALIGNMENT 64
! 190:
1.1 root 191: /* Make strings word-aligned so strcpy from constants will be faster. */
192: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
193: (TREE_CODE (EXP) == STRING_CST \
1.1.1.3 ! root 194: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
1.1 root 195:
196: /* Make arrays of chars word-aligned for the same reasons. */
197: #define DATA_ALIGNMENT(TYPE, ALIGN) \
198: (TREE_CODE (TYPE) == ARRAY_TYPE \
199: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
1.1.1.3 ! root 200: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
1.1 root 201:
1.1.1.2 root 202: /* Set this nonzero if move instructions will actually fail to work
1.1 root 203: when given unaligned data. */
1.1.1.2 root 204: #define STRICT_ALIGNMENT 1
1.1 root 205:
206: /* Things that must be doubleword aligned cannot go in the text section,
207: because the linker fails to align the text section enough!
208: Put them in the data section. */
209: #define MAX_TEXT_ALIGN 32
210:
211: #define SELECT_SECTION(T,RELOC) \
212: { \
213: if (TREE_CODE (T) == VAR_DECL) \
214: { \
215: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
216: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
217: && ! (flag_pic && (RELOC))) \
218: text_section (); \
219: else \
220: data_section (); \
221: } \
222: else if (TREE_CODE (T) == CONSTRUCTOR) \
223: { \
224: if (flag_pic != 0 && (RELOC) != 0) \
225: data_section (); \
226: } \
227: else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
228: { \
229: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
230: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
231: data_section (); \
232: else \
233: text_section (); \
234: } \
235: }
236:
237: /* Use text section for a constant
238: unless we need more alignment than that offers. */
239: #define SELECT_RTX_SECTION(MODE, X) \
240: { \
241: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
242: && ! (flag_pic && symbolic_operand (X))) \
243: text_section (); \
244: else \
245: data_section (); \
246: }
247:
248: /* Standard register usage. */
249:
250: /* Number of actual hardware registers.
251: The hardware registers are assigned numbers for the compiler
252: from 0 to just below FIRST_PSEUDO_REGISTER.
253: All registers that the compiler knows about must be given numbers,
254: even those that are not normally considered general registers.
255:
256: SPARC has 32 integer registers and 32 floating point registers. */
257:
258: #define FIRST_PSEUDO_REGISTER 64
259:
260: /* 1 for registers that have pervasive standard uses
261: and are not available for the register allocator.
262: 0 is used for the condition code and not to represent %g0, which is
263: hardwired to 0, so reg 0 is *not* fixed.
1.1.1.3 ! root 264: g1 through g4 are free to use as temporaries.
! 265: g5 through g7 are reserved for the operating system. */
1.1 root 266: #define FIXED_REGISTERS \
1.1.1.3 ! root 267: {0, 0, 0, 0, 0, 1, 1, 1, \
1.1 root 268: 0, 0, 0, 0, 0, 0, 1, 0, \
269: 0, 0, 0, 0, 0, 0, 0, 0, \
270: 0, 0, 0, 0, 0, 0, 1, 1, \
271: \
272: 0, 0, 0, 0, 0, 0, 0, 0, \
273: 0, 0, 0, 0, 0, 0, 0, 0, \
274: 0, 0, 0, 0, 0, 0, 0, 0, \
275: 0, 0, 0, 0, 0, 0, 0, 0}
276:
277: /* 1 for registers not available across function calls.
278: These must include the FIXED_REGISTERS and also any
279: registers that can be used without being saved.
280: The latter must include the registers where values are returned
281: and the register where structure-value addresses are passed.
282: Aside from that, you can include as many other registers as you like. */
283: #define CALL_USED_REGISTERS \
284: {1, 1, 1, 1, 1, 1, 1, 1, \
285: 1, 1, 1, 1, 1, 1, 1, 1, \
286: 0, 0, 0, 0, 0, 0, 0, 0, \
287: 0, 0, 0, 0, 0, 0, 1, 1, \
288: \
289: 1, 1, 1, 1, 1, 1, 1, 1, \
290: 1, 1, 1, 1, 1, 1, 1, 1, \
291: 1, 1, 1, 1, 1, 1, 1, 1, \
292: 1, 1, 1, 1, 1, 1, 1, 1}
293:
294: /* Return number of consecutive hard regs needed starting at reg REGNO
295: to hold something of mode MODE.
296: This is ordinarily the length in words of a value of mode MODE
297: but can be less for certain modes in special long registers.
298:
299: On SPARC, ordinary registers hold 32 bits worth;
300: this means both integer and floating point registers.
301:
302: We use vectors to keep this information about registers. */
303:
304: /* How many hard registers it takes to make a register of this mode. */
305: extern int hard_regno_nregs[];
306:
307: #define HARD_REGNO_NREGS(REGNO, MODE) \
308: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
309:
310: /* Value is 1 if register/mode pair is acceptable on sparc. */
311: extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
312:
313: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
314: On SPARC, the cpu registers can hold any mode but the float registers
315: can only hold SFmode or DFmode. See sparc.c for how we
316: initialize this. */
317: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
318: ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
319:
320: /* Value is 1 if it is a good idea to tie two pseudo registers
321: when one has mode MODE1 and one has mode MODE2.
322: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
323: for any hard reg, then this must be 0 for correct output. */
324: #define MODES_TIEABLE_P(MODE1, MODE2) \
325: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
326:
327: /* Specify the registers used for certain standard purposes.
328: The values of these macros are register numbers. */
329:
330: /* SPARC pc isn't overloaded on a register that the compiler knows about. */
331: /* #define PC_REGNUM */
332:
333: /* Register to use for pushing function arguments. */
334: #define STACK_POINTER_REGNUM 14
335:
336: /* Actual top-of-stack address is 92 greater than the contents
337: of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
338: for the ins and local registers, 4 byte for structure return address, and
339: 24 bytes for the 6 register parameters. */
340: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
341:
342: /* Base register for access to local variables of the function. */
343: #define FRAME_POINTER_REGNUM 30
344:
345: #if 0
346: /* Register that is used for the return address. */
347: #define RETURN_ADDR_REGNUM 15
348: #endif
349:
350: /* Value should be nonzero if functions must have frame pointers.
351: Zero means the frame pointer need not be set up (and parms
352: may be accessed via the stack pointer) in functions that seem suitable.
353: This is computed in `reload', in reload1.c.
354:
355: Used in flow.c, global-alloc.c, and reload1.c. */
356: extern int leaf_function;
357:
358: #define FRAME_POINTER_REQUIRED \
359: (! (leaf_function_p () && only_leaf_regs_used ()))
360:
361: /* C statement to store the difference between the frame pointer
362: and the stack pointer values immediately after the function prologue.
363:
364: Note, we always pretend that this is a leaf function because if
365: it's not, there's no point in trying to eliminate the
366: frame pointer. If it is a leaf function, we guessed right! */
367: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
368: do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
369:
370: /* Base register for access to arguments of the function. */
371: #define ARG_POINTER_REGNUM 30
372:
373: /* Register in which static-chain is passed to a function. */
374: /* ??? */
375: #define STATIC_CHAIN_REGNUM 1
376:
377: /* Register which holds offset table for position-independent
378: data references. */
379:
380: #define PIC_OFFSET_TABLE_REGNUM 23
381:
382: #define INITIALIZE_PIC initialize_pic ()
383: #define FINALIZE_PIC finalize_pic ()
384:
1.1.1.3 ! root 385: /* Sparc ABI says that quad-precision floats and all structures are returned
! 386: in memory. We go along regarding floats, but for structures
! 387: we follow GCC's normal policy. Use -fpcc-struct-value
! 388: if you want to follow the ABI. */
! 389: #define RETURN_IN_MEMORY(TYPE) \
! 390: (TYPE_MODE (TYPE) == TFmode)
! 391:
1.1 root 392: /* Functions which return large structures get the address
393: to place the wanted value at offset 64 from the frame.
394: Must reserve 64 bytes for the in and local registers. */
395: /* Used only in other #defines in this file. */
396: #define STRUCT_VALUE_OFFSET 64
397:
398: #define STRUCT_VALUE \
399: gen_rtx (MEM, Pmode, \
400: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
401: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
402: #define STRUCT_VALUE_INCOMING \
403: gen_rtx (MEM, Pmode, \
404: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
405: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
406:
407: /* Define the classes of registers for register constraints in the
408: machine description. Also define ranges of constants.
409:
410: One of the classes must always be named ALL_REGS and include all hard regs.
411: If there is more than one class, another class must be named NO_REGS
412: and contain no registers.
413:
414: The name GENERAL_REGS must be the name of a class (or an alias for
415: another name such as ALL_REGS). This is the class of registers
416: that is allowed by "g" or "r" in a register constraint.
417: Also, registers outside this class are allocated only when
418: instructions express preferences for them.
419:
420: The classes must be numbered in nondecreasing order; that is,
421: a larger-numbered class must never be contained completely
422: in a smaller-numbered class.
423:
424: For any two classes, it is very desirable that there be another
425: class that represents their union. */
426:
427: /* The SPARC has two kinds of registers, general and floating point. */
428:
429: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
430:
431: #define N_REG_CLASSES (int) LIM_REG_CLASSES
432:
433: /* Give names of register classes as strings for dump file. */
434:
435: #define REG_CLASS_NAMES \
436: {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
437:
438: /* Define which registers fit in which classes.
439: This is an initializer for a vector of HARD_REG_SET
440: of length N_REG_CLASSES. */
441:
442: #if 0 && defined (__GNUC__)
443: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
444: #else
445: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
446: #endif
447:
448: /* The same information, inverted:
449: Return the class number of the smallest class containing
450: reg number REGNO. This could be a conditional expression
451: or could index an array. */
452:
453: #define REGNO_REG_CLASS(REGNO) \
454: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
455:
456: /* This is the order in which to allocate registers
457: normally. */
458: #define REG_ALLOC_ORDER \
1.1.1.2 root 459: { 8, 9, 10, 11, 12, 13, 2, 3, \
460: 15, 16, 17, 18, 19, 20, 21, 22, \
461: 23, 24, 25, 26, 27, 28, 29, 31, \
1.1 root 462: 32, 33, 34, 35, 36, 37, 38, 39, \
463: 40, 41, 42, 43, 44, 45, 46, 47, \
464: 48, 49, 50, 51, 52, 53, 54, 55, \
465: 56, 57, 58, 59, 60, 61, 62, 63, \
1.1.1.3 ! root 466: 1, 4, 5, 6, 7, 0, 14, 30}
1.1 root 467:
468: /* This is the order in which to allocate registers for
469: leaf functions. If all registers can fit in the "i" registers,
470: then we have the possibility of having a leaf function. */
471: #define REG_LEAF_ALLOC_ORDER \
472: { 2, 3, 24, 25, 26, 27, 28, 29, \
473: 15, 8, 9, 10, 11, 12, 13, \
474: 16, 17, 18, 19, 20, 21, 22, 23, \
475: 32, 33, 34, 35, 36, 37, 38, 39, \
476: 40, 41, 42, 43, 44, 45, 46, 47, \
477: 48, 49, 50, 51, 52, 53, 54, 55, \
478: 56, 57, 58, 59, 60, 61, 62, 63, \
1.1.1.3 ! root 479: 1, 4, 5, 6, 7, 0, 14, 30, 31}
1.1 root 480:
481: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
482:
483: #define LEAF_REGISTERS \
484: { 1, 1, 1, 1, 1, 1, 1, 1, \
485: 0, 0, 0, 0, 0, 0, 1, 0, \
486: 0, 0, 0, 0, 0, 0, 0, 0, \
487: 1, 1, 1, 1, 1, 1, 0, 1, \
488: 1, 1, 1, 1, 1, 1, 1, 1, \
489: 1, 1, 1, 1, 1, 1, 1, 1, \
490: 1, 1, 1, 1, 1, 1, 1, 1, \
1.1.1.3 ! root 491: 1, 1, 1, 1, 1, 1, 1, 1}
1.1 root 492:
493: extern char leaf_reg_remap[];
494: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
495: extern char leaf_reg_backmap[];
496: #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
497:
498: #define REG_USED_SO_FAR(REGNO) \
499: ((REGNO) >= 24 && (REGNO) < 30 \
500: ? (regs_ever_live[24] \
501: || regs_ever_live[25] \
502: || regs_ever_live[26] \
503: || regs_ever_live[27] \
504: || regs_ever_live[28] \
505: || regs_ever_live[29]) : 0)
506:
507: /* The class value for index registers, and the one for base regs. */
508: #define INDEX_REG_CLASS GENERAL_REGS
509: #define BASE_REG_CLASS GENERAL_REGS
510:
511: /* Get reg_class from a letter such as appears in the machine description. */
512:
513: #define REG_CLASS_FROM_LETTER(C) \
514: ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
515:
516: /* The letters I, J, K, L and M in a register constraint string
517: can be used to stand for particular ranges of immediate operands.
518: This macro defines what the ranges are.
519: C is the letter, and VALUE is a constant value.
520: Return 1 if VALUE is in the range specified by C.
521:
522: For SPARC, `I' is used for the range of constants an insn
523: can actually contain.
524: `J' is used for the range which is just zero (since that is R0).
525: `K' is used for the 5-bit operand of a compare insns. */
526:
527: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
528:
529: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
530: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
531: : (C) == 'J' ? (VALUE) == 0 \
532: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
533: : 0)
534:
535: /* Similar, but for floating constants, and defining letters G and H.
536: Here VALUE is the CONST_DOUBLE rtx itself. */
537:
538: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
539: ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
540: && CONST_DOUBLE_LOW (VALUE) == 0 \
541: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
542: : 0)
543:
544: /* Given an rtx X being reloaded into a reg required to be
545: in class CLASS, return the class of reg to actually use.
546: In general this is just CLASS; but on some machines
547: in some cases it is preferable to use a more restrictive class. */
1.1.1.3 ! root 548: /* We can't load constants into FP registers. We can't load any FP constant
! 549: if an 'E' constraint fails to match it. */
! 550: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
! 551: (CONSTANT_P (X) \
! 552: && ((CLASS) == FP_REGS \
! 553: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
! 554: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
! 555: || HOST_BITS_PER_INT != BITS_PER_WORD))) \
! 556: ? NO_REGS : (CLASS))
1.1 root 557:
558: /* Return the register class of a scratch register needed to load IN into
559: a register of class CLASS in MODE.
560:
561: On the SPARC, when PIC, we need a temporary when loading some addresses
562: into a register. */
563:
564: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
565: (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
566:
567: /* Return the maximum number of consecutive registers
568: needed to represent mode MODE in a register of class CLASS. */
569: /* On SPARC, this is the size of MODE in words. */
570: #define CLASS_MAX_NREGS(CLASS, MODE) \
571: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
572:
573: /* Stack layout; function entry, exit and calling. */
574:
575: /* Define the number of register that can hold parameters.
576: These two macros are used only in other macro definitions below. */
577: #define NPARM_REGS 6
578:
579: /* Define this if pushing a word on the stack
580: makes the stack pointer a smaller address. */
581: #define STACK_GROWS_DOWNWARD
582:
583: /* Define this if the nominal address of the stack frame
584: is at the high-address end of the local variables;
585: that is, each additional local variable allocated
586: goes at a more negative offset in the frame. */
587: #define FRAME_GROWS_DOWNWARD
588:
589: /* Offset within stack frame to start allocating local variables at.
590: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
591: first local allocated. Otherwise, it is the offset to the BEGINNING
592: of the first local allocated. */
593: #define STARTING_FRAME_OFFSET (-16)
594:
595: /* If we generate an insn to push BYTES bytes,
596: this says how many the stack pointer really advances by.
597: On SPARC, don't define this because there are no push insns. */
598: /* #define PUSH_ROUNDING(BYTES) */
599:
600: /* Offset of first parameter from the argument pointer register value.
601: This is 64 for the ins and locals, plus 4 for the struct-return reg
1.1.1.3 ! root 602: even if this function isn't going to use it.
! 603: If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the
! 604: stack remains aligned. */
! 605: #define FIRST_PARM_OFFSET(FNDECL) \
! 606: (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0))
1.1 root 607:
608: /* When a parameter is passed in a register, stack space is still
609: allocated for it. */
610: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
611:
612: /* Keep the stack pointer constant throughout the function.
1.1.1.2 root 613: This is both an optimization and a necessity: longjmp
1.1 root 614: doesn't behave itself when the stack pointer moves within
615: the function! */
616: #define ACCUMULATE_OUTGOING_ARGS
617:
618: /* Value is the number of bytes of arguments automatically
619: popped when returning from a subroutine call.
620: FUNTYPE is the data type of the function (as a tree),
621: or for a library call it is an identifier node for the subroutine name.
622: SIZE is the number of bytes of arguments passed on the stack. */
623:
624: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
625:
626: /* Some subroutine macros specific to this machine. */
627: #define BASE_RETURN_VALUE_REG(MODE) \
628: ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
629: #define BASE_OUTGOING_VALUE_REG(MODE) \
630: ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
631: #define BASE_PASSING_ARG_REG(MODE) (8)
632: #define BASE_INCOMING_ARG_REG(MODE) (24)
633:
634: /* Define how to find the value returned by a function.
635: VALTYPE is the data type of the value (as a tree).
636: If the precise function being called is known, FUNC is its FUNCTION_DECL;
637: otherwise, FUNC is 0. */
638:
639: /* On SPARC the value is found in the first "output" register. */
640:
641: #define FUNCTION_VALUE(VALTYPE, FUNC) \
642: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
643:
644: /* But the called function leaves it in the first "input" register. */
645:
646: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
647: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
648:
649: /* Define how to find the value returned by a library function
650: assuming the value has mode MODE. */
651:
652: #define LIBCALL_VALUE(MODE) \
653: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
654:
655: /* 1 if N is a possible register number for a function value
656: as seen by the caller.
657: On SPARC, the first "output" reg is used for integer values,
658: and the first floating point register is used for floating point values. */
659:
660: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
661:
662: /* 1 if N is a possible register number for function argument passing.
663: On SPARC, these are the "output" registers. */
664:
665: #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
666:
667: /* Define a data type for recording info about an argument list
668: during the scan of that argument list. This data type should
669: hold all necessary information about the function itself
670: and about the args processed so far, enough to enable macros
671: such as FUNCTION_ARG to determine where the next arg should go.
672:
673: On SPARC, this is a single integer, which is a number of words
674: of arguments scanned so far (including the invisible argument,
675: if any, which holds the structure-value-address).
676: Thus 7 or more means all following args should go on the stack. */
677:
678: #define CUMULATIVE_ARGS int
679:
680: #define ROUND_ADVANCE(SIZE) \
1.1.1.2 root 681: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
682:
683: /* Round a register number up to a proper boundary for an arg of mode MODE.
684: Note that we need an odd/even pair for a two-word arg,
685: since that will become 8-byte aligned when stored in memory. */
686: #define ROUND_REG(X, MODE) \
687: (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
688: ? ((X) + ! ((X) & 1)) : (X))
1.1 root 689:
690: /* Initialize a variable CUM of type CUMULATIVE_ARGS
691: for a call to a function whose data type is FNTYPE.
692: For a library call, FNTYPE is 0.
693:
694: On SPARC, the offset always starts at 0: the first parm reg is always
695: the same reg. */
696:
697: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
698:
699: /* Update the data in CUM to advance over an argument
700: of mode MODE and data type TYPE.
701: (TYPE is null for libcalls where that information may not be available.) */
702:
703: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 704: ((CUM) = (ROUND_REG ((CUM), (MODE)) \
705: + ((MODE) != BLKmode \
706: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
707: : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
1.1 root 708:
709: /* Determine where to put an argument to a function.
710: Value is zero to push the argument on the stack,
711: or a hard register in which to store the argument.
712:
713: MODE is the argument's machine mode.
714: TYPE is the data type of the argument (as a tree).
715: This is null for libcalls where that information may
716: not be available.
717: CUM is a variable of type CUMULATIVE_ARGS which gives info about
718: the preceding args and about the function being called.
719: NAMED is nonzero if this argument is a named parameter
720: (otherwise it is an extra parameter matching an ellipsis). */
721:
722: /* On SPARC the first six args are normally in registers
723: and the rest are pushed. Any arg that starts within the first 6 words
724: is at least partially passed in a register unless its data type forbids. */
725:
726: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 727: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 728: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 729: && ((TYPE)==0 || (MODE) != BLKmode \
730: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
731: ? gen_rtx (REG, (MODE), \
732: (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
733: : 0)
1.1 root 734:
735: /* Define where a function finds its arguments.
736: This is different from FUNCTION_ARG because of register windows. */
737:
738: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 739: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 740: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 741: && ((TYPE)==0 || (MODE) != BLKmode \
742: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
743: ? gen_rtx (REG, (MODE), \
744: (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
745: : 0)
1.1 root 746:
747: /* For an arg passed partly in registers and partly in memory,
748: this is the number of registers used.
749: For args passed entirely in registers or entirely in memory, zero.
750: Any arg that starts in the first 6 regs but won't entirely fit in them
751: needs partial registers on the Sparc. */
752:
753: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 754: ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 755: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 756: && ((TYPE)==0 || (MODE) != BLKmode \
757: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
758: && (ROUND_REG ((CUM), (MODE)) \
1.1 root 759: + ((MODE) == BLKmode \
760: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1.1.1.2 root 761: : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
762: ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
1.1 root 763: : 0)
764:
1.1.1.3 ! root 765: /* The SPARC ABI stipulates passing struct arguments (of any size) and
! 766: quad-precision floats by invisible reference. */
1.1 root 767: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1.1.1.3 ! root 768: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
! 769: || TREE_CODE (TYPE) == UNION_TYPE)) \
! 770: || (MODE == TFmode))
1.1 root 771:
1.1.1.2 root 772: /* If defined, a C expression that gives the alignment boundary, in
773: bits, of an argument with the specified mode and type. If it is
774: not defined, `PARM_BOUNDARY' is used for all arguments.
775:
776: This definition does nothing special unless TARGET_FORCE_ALIGN;
777: in that case, it aligns each arg to the natural boundary. */
778:
779: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
780: (! TARGET_FORCE_ALIGN \
781: ? PARM_BOUNDARY \
782: : (((TYPE) != 0) \
783: ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
784: ? PARM_BOUNDARY \
785: : TYPE_ALIGN (TYPE)) \
786: : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
787: ? PARM_BOUNDARY \
788: : GET_MODE_ALIGNMENT (MODE))))
789:
1.1 root 790: /* Define the information needed to generate branch and scc insns. This is
791: stored from the compare operation. Note that we can't use "rtx" here
792: since it hasn't been defined! */
793:
794: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
795:
796: /* Define the function that build the compare insn for scc and bcc. */
797:
798: extern struct rtx_def *gen_compare_reg ();
799:
1.1.1.3 ! root 800: /* Generate the special assembly code needed to tell the assembler whatever
! 801: it might need to know about the return value of a function.
! 802:
! 803: For Sparc assemblers, we need to output a .proc pseudo-op which conveys
! 804: information to the assembler relating to peephole optimization (done in
! 805: the assembler). */
! 806:
! 807: #define ASM_DECLARE_RESULT(FILE, RESULT) \
! 808: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
! 809:
1.1 root 810: /* Output the label for a function definition. */
811:
1.1.1.3 ! root 812: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
! 813: do { \
! 814: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
! 815: ASM_OUTPUT_LABEL (FILE, NAME); \
! 816: } while (0)
1.1 root 817:
818: /* Two views of the size of the current frame. */
819: extern int actual_fsize;
820: extern int apparent_fsize;
821:
822: /* This macro generates the assembly code for function entry.
823: FILE is a stdio stream to output the code to.
824: SIZE is an int: how many units of temporary storage to allocate.
825: Refer to the array `regs_ever_live' to determine which registers
826: to save; `regs_ever_live[I]' is nonzero if register number I
827: is ever used in the function. This macro is responsible for
828: knowing which registers should not be saved even if used. */
829:
830: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
831: of memory. If any fpu reg is used in the function, we allocate
832: such a block here, at the bottom of the frame, just in case it's needed.
833:
834: If this function is a leaf procedure, then we may choose not
835: to do a "save" insn. The decision about whether or not
836: to do this is made in regclass.c. */
837:
838: #define FUNCTION_PROLOGUE(FILE, SIZE) \
839: output_function_prologue (FILE, SIZE, leaf_function)
840:
841: /* Output assembler code to FILE to increment profiler label # LABELNO
842: for profiling a function entry. */
843:
844: #define FUNCTION_PROFILER(FILE, LABELNO) \
845: fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
846: (LABELNO), (LABELNO))
847:
848: /* Output assembler code to FILE to initialize this source file's
849: basic block profiling info, if that has not already been done. */
850:
851: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
852: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
853: (LABELNO), (LABELNO))
854:
855: /* Output assembler code to FILE to increment the entry-count for
856: the BLOCKNO'th basic block in this source file. */
857:
858: #define BLOCK_PROFILER(FILE, BLOCKNO) \
859: { \
860: int blockn = (BLOCKNO); \
861: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
862: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
863: 4 * blockn, 4 * blockn, 4 * blockn); \
864: }
865:
866: /* Output rtl to increment the entry-count for the LABELNO'th instrumented
867: arc in this source file. */
868:
869: #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
870: output_arc_profiler (ARCNO, INSERT_AFTER)
871:
872: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
873: the stack pointer does not matter. The value is tested only in
874: functions that have frame pointers.
875: No definition is equivalent to always zero. */
876:
877: extern int current_function_calls_alloca;
878: extern int current_function_outgoing_args_size;
879:
880: #define EXIT_IGNORE_STACK \
881: (get_frame_size () != 0 \
882: || current_function_calls_alloca || current_function_outgoing_args_size)
883:
884: /* This macro generates the assembly code for function exit,
885: on machines that need it. If FUNCTION_EPILOGUE is not defined
886: then individual return instructions are generated for each
887: return statement. Args are same as for FUNCTION_PROLOGUE.
888:
889: The function epilogue should not depend on the current stack pointer!
890: It should use the frame pointer only. This is mandatory because
891: of alloca; we also take advantage of it to omit stack adjustments
892: before returning. */
893:
894: /* This declaration is needed due to traditional/ANSI
895: incompatibilities which cannot be #ifdefed away
896: because they occur inside of macros. Sigh. */
897: extern union tree_node *current_function_decl;
898:
899: #define FUNCTION_EPILOGUE(FILE, SIZE) \
1.1.1.3 ! root 900: output_function_epilogue (FILE, SIZE, leaf_function)
1.1 root 901:
902: #define DELAY_SLOTS_FOR_EPILOGUE 1
903: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
904: eligible_for_epilogue_delay (trial, slots_filled)
905:
906: /* Output assembler code for a block containing the constant parts
907: of a trampoline, leaving space for the variable parts. */
908:
909: /* On the sparc, the trampoline contains five instructions:
910: sethi #TOP_OF_FUNCTION,%g2
911: or #BOTTOM_OF_FUNCTION,%g2,%g2
912: sethi #TOP_OF_STATIC,%g1
913: jmp g2
914: or #BOTTOM_OF_STATIC,%g1,%g1 */
915: #define TRAMPOLINE_TEMPLATE(FILE) \
916: { \
917: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
918: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
919: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
920: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
921: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
922: }
923:
924: /* Length in units of the trampoline for entering a nested function. */
925:
926: #define TRAMPOLINE_SIZE 20
927:
928: /* Emit RTL insns to initialize the variable parts of a trampoline.
929: FNADDR is an RTX for the address of the function's pure code.
930: CXT is an RTX for the static chain value for the function.
931:
932: This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
933: (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
934: (to store insns). This is a bit excessive. Perhaps a different
935: mechanism would be better here. */
936:
937: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
938: { \
939: rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
940: size_int (10), 0, 1); \
941: rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
942: size_int (10), 0, 1); \
943: rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
944: rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
945: rtx g1_sethi = gen_rtx (HIGH, SImode, \
946: gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
947: rtx g2_sethi = gen_rtx (HIGH, SImode, \
948: gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
949: rtx g1_ori = gen_rtx (HIGH, SImode, \
950: gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
951: rtx g2_ori = gen_rtx (HIGH, SImode, \
952: gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
953: rtx tem = gen_reg_rtx (SImode); \
954: emit_move_insn (tem, g2_sethi); \
955: emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
956: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
957: emit_move_insn (tem, g2_ori); \
958: emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
959: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
960: emit_move_insn (tem, g1_sethi); \
961: emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
962: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
963: emit_move_insn (tem, g1_ori); \
964: emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
965: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
966: }
967:
968: /* Emit code for a call to builtin_saveregs. We must emit USE insns which
969: reference the 6 input registers. Ordinarily they are not call used
970: registers, but they are for _builtin_saveregs, so we must make this
971: explicit. */
972:
973: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
974: (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
975: emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
976: expand_call (exp, target, ignore))
977:
978: /* Addressing modes, and classification of registers for them. */
979:
980: /* #define HAVE_POST_INCREMENT */
981: /* #define HAVE_POST_DECREMENT */
982:
983: /* #define HAVE_PRE_DECREMENT */
984: /* #define HAVE_PRE_INCREMENT */
985:
986: /* Macros to check register numbers against specific register classes. */
987:
988: /* These assume that REGNO is a hard or pseudo reg number.
989: They give nonzero only if REGNO is a hard reg of the suitable class
990: or a pseudo reg currently allocated to a suitable hard reg.
991: Since they use reg_renumber, they are safe only once reg_renumber
992: has been allocated, which happens in local-alloc.c. */
993:
994: #define REGNO_OK_FOR_INDEX_P(REGNO) \
995: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
996: #define REGNO_OK_FOR_BASE_P(REGNO) \
997: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
998: #define REGNO_OK_FOR_FP_P(REGNO) \
999: (((REGNO) ^ 0x20) < 32 \
1000: || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1001:
1002: /* Now macros that check whether X is a register and also,
1003: strictly, whether it is in a specified class.
1004:
1005: These macros are specific to the SPARC, and may be used only
1006: in code for printing assembler insns and in conditions for
1007: define_optimization. */
1008:
1009: /* 1 if X is an fp register. */
1010:
1011: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1012:
1013: /* Maximum number of registers that can appear in a valid memory address. */
1014:
1015: #define MAX_REGS_PER_ADDRESS 2
1016:
1017: /* Recognize any constant value that is a valid address. */
1018:
1019: #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1020:
1021: /* Nonzero if the constant value X is a legitimate general operand.
1022: Anything can be made to work except floating point constants. */
1023:
1024: #define LEGITIMATE_CONSTANT_P(X) \
1025: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1026:
1027: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1028: and check its validity for a certain class.
1029: We have two alternate definitions for each of them.
1030: The usual definition accepts all pseudo regs; the other rejects
1031: them unless they have been allocated suitable hard regs.
1032: The symbol REG_OK_STRICT causes the latter definition to be used.
1033:
1034: Most source files want to accept pseudo regs in the hope that
1035: they will get allocated to the class that the insn wants them to be in.
1036: Source files for reload pass need to be strict.
1037: After reload, it makes no difference, since pseudo regs have
1038: been eliminated by then. */
1039:
1040: /* Optional extra constraints for this machine. Borrowed from romp.h.
1041:
1042: For the SPARC, `Q' means that this is a memory operand but not a
1043: symbolic memory operand. Note that an unassigned pseudo register
1044: is such a memory operand. Needed because reload will generate
1045: these things in insns and then not re-recognize the insns, causing
1046: constrain_operands to fail.
1047:
1048: `R' handles the LO_SUM which can be an address for `Q'.
1049:
1050: `S' handles constraints for calls. */
1051:
1052: #ifndef REG_OK_STRICT
1053:
1054: /* Nonzero if X is a hard reg that can be used as an index
1055: or if it is a pseudo reg. */
1056: #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1057: /* Nonzero if X is a hard reg that can be used as a base reg
1058: or if it is a pseudo reg. */
1059: #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1060:
1061: #define EXTRA_CONSTRAINT(OP, C) \
1.1.1.3 ! root 1062: ((C) == 'Q' \
! 1063: ? ((GET_CODE (OP) == MEM \
! 1064: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
! 1065: && ! symbolic_memory_operand (OP, VOIDmode)) \
! 1066: || (reload_in_progress && GET_CODE (OP) == REG \
! 1067: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
! 1068: : (C) == 'R' \
! 1069: ? (GET_CODE (OP) == LO_SUM \
! 1070: && GET_CODE (XEXP (OP, 0)) == REG \
! 1071: && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
! 1072: : (C) == 'S' \
! 1073: ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
! 1074: : 0)
1.1 root 1075:
1076: #else
1077:
1078: /* Nonzero if X is a hard reg that can be used as an index. */
1079: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1080: /* Nonzero if X is a hard reg that can be used as a base reg. */
1081: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1082:
1083: #define EXTRA_CONSTRAINT(OP, C) \
1084: ((C) == 'Q' ? \
1085: (GET_CODE (OP) == REG ? \
1086: (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1087: && reg_renumber[REGNO (OP)] < 0) \
1088: : GET_CODE (OP) == MEM) \
1089: : ((C) == 'R' ? \
1090: (GET_CODE (OP) == LO_SUM \
1091: && GET_CODE (XEXP (OP, 0)) == REG \
1092: && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1093: : ((C) == 'S' \
1094: ? (CONSTANT_P (OP) \
1095: || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1096: || strict_memory_address_p (Pmode, OP)) : 0)))
1097: #endif
1098:
1099: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1100: that is a valid memory address for an instruction.
1101: The MODE argument is the machine mode for the MEM expression
1102: that wants to use this address.
1103:
1104: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1105: ordinarily. This changes a bit when generating PIC.
1106:
1107: If you change this, execute "rm explow.o recog.o reload.o". */
1108:
1.1.1.3 ! root 1109: #define RTX_OK_FOR_BASE_P(X) \
! 1110: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
! 1111: || (GET_CODE (X) == SUBREG \
! 1112: && GET_CODE (SUBREG_REG (X)) == REG \
! 1113: && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
! 1114:
! 1115: #define RTX_OK_FOR_INDEX_P(X) \
! 1116: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
! 1117: || (GET_CODE (X) == SUBREG \
! 1118: && GET_CODE (SUBREG_REG (X)) == REG \
! 1119: && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
! 1120:
! 1121: #define RTX_OK_FOR_OFFSET_P(X) \
! 1122: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
! 1123:
1.1 root 1124: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1.1.1.3 ! root 1125: { if (RTX_OK_FOR_BASE_P (X)) \
! 1126: goto ADDR; \
1.1 root 1127: else if (GET_CODE (X) == PLUS) \
1128: { \
1.1.1.3 ! root 1129: register rtx op0 = XEXP (X, 0); \
! 1130: register rtx op1 = XEXP (X, 1); \
! 1131: if (flag_pic && op0 == pic_offset_table_rtx) \
1.1 root 1132: { \
1.1.1.3 ! root 1133: if (RTX_OK_FOR_BASE_P (op1)) \
1.1 root 1134: goto ADDR; \
1135: else if (flag_pic == 1 \
1.1.1.3 ! root 1136: && GET_CODE (op1) != REG \
! 1137: && GET_CODE (op1) != LO_SUM \
! 1138: && GET_CODE (op1) != MEM) \
1.1 root 1139: goto ADDR; \
1140: } \
1.1.1.3 ! root 1141: else if (RTX_OK_FOR_BASE_P (op0)) \
1.1 root 1142: { \
1.1.1.3 ! root 1143: if (RTX_OK_FOR_INDEX_P (op1) \
! 1144: || RTX_OK_FOR_OFFSET_P (op1)) \
1.1 root 1145: goto ADDR; \
1146: } \
1.1.1.3 ! root 1147: else if (RTX_OK_FOR_BASE_P (op1)) \
1.1 root 1148: { \
1.1.1.3 ! root 1149: if (RTX_OK_FOR_INDEX_P (op0) \
! 1150: || RTX_OK_FOR_OFFSET_P (op0)) \
1.1 root 1151: goto ADDR; \
1152: } \
1153: } \
1.1.1.3 ! root 1154: else if (GET_CODE (X) == LO_SUM) \
! 1155: { \
! 1156: register rtx op0 = XEXP (X, 0); \
! 1157: register rtx op1 = XEXP (X, 1); \
! 1158: if (RTX_OK_FOR_BASE_P (op0) \
! 1159: && CONSTANT_P (op1)) \
! 1160: goto ADDR; \
! 1161: } \
1.1 root 1162: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1163: goto ADDR; \
1164: }
1165:
1166: /* Try machine-dependent ways of modifying an illegitimate address
1167: to be legitimate. If we find one, return the new, valid address.
1168: This macro is used in only one place: `memory_address' in explow.c.
1169:
1170: OLDX is the address as it was before break_out_memory_refs was called.
1171: In some cases it is useful to look at this to decide what needs to be done.
1172:
1173: MODE and WIN are passed so that this macro can use
1174: GO_IF_LEGITIMATE_ADDRESS.
1175:
1176: It is always safe for this macro to do nothing. It exists to recognize
1177: opportunities to optimize the output. */
1178:
1179: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1180: extern struct rtx_def *legitimize_pic_address ();
1181: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1182: { rtx sparc_x = (X); \
1183: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1184: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1185: force_operand (XEXP (X, 0), 0)); \
1186: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1187: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1188: force_operand (XEXP (X, 1), 0)); \
1189: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1190: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1191: XEXP (X, 1)); \
1192: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1193: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1194: force_operand (XEXP (X, 1), 0)); \
1195: if (sparc_x != (X) && memory_address_p (MODE, X)) \
1196: goto WIN; \
1197: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1198: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1199: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1200: copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1201: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1202: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1203: copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1204: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1205: || GET_CODE (X) == LABEL_REF) \
1206: (X) = gen_rtx (LO_SUM, Pmode, \
1207: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1208: if (memory_address_p (MODE, X)) \
1209: goto WIN; }
1210:
1211: /* Go to LABEL if ADDR (a legitimate address expression)
1212: has an effect that depends on the machine mode it is used for.
1213: On the SPARC this is never true. */
1214:
1215: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1216:
1217: /* Specify the machine mode that this machine uses
1218: for the index in the tablejump instruction. */
1219: #define CASE_VECTOR_MODE SImode
1220:
1221: /* Define this if the tablejump instruction expects the table
1222: to contain offsets from the address of the table.
1223: Do not define this if the table should contain absolute addresses. */
1224: /* #define CASE_VECTOR_PC_RELATIVE */
1225:
1226: /* Specify the tree operation to be used to convert reals to integers. */
1227: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1228:
1229: /* This is the kind of divide that is easiest to do in the general case. */
1230: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1231:
1232: /* Define this as 1 if `char' should by default be signed; else as 0. */
1233: #define DEFAULT_SIGNED_CHAR 1
1234:
1235: /* Max number of bytes we can move from memory to memory
1236: in one reasonably fast instruction. */
1.1.1.3 ! root 1237: #define MOVE_MAX 8
1.1 root 1238:
1239: /* Define if normal loads of shorter-than-word items from memory clears
1240: the rest of the bigs in the register. */
1241: #define BYTE_LOADS_ZERO_EXTEND
1242:
1243: /* Nonzero if access to memory by bytes is slow and undesirable.
1244: For RISC chips, it means that access to memory by bytes is no
1245: better than access by words when possible, so grab a whole word
1246: and maybe make use of that. */
1247: #define SLOW_BYTE_ACCESS 1
1248:
1249: /* We assume that the store-condition-codes instructions store 0 for false
1250: and some other value for true. This is the value stored for true. */
1251:
1252: #define STORE_FLAG_VALUE 1
1253:
1254: /* When a prototype says `char' or `short', really pass an `int'. */
1255: #define PROMOTE_PROTOTYPES
1256:
1257: /* Define if shifts truncate the shift count
1258: which implies one can omit a sign-extension or zero-extension
1259: of a shift count. */
1260: #define SHIFT_COUNT_TRUNCATED
1261:
1262: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1263: is done just by pretending it is already truncated. */
1264: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1265:
1266: /* Specify the machine mode that pointers have.
1267: After generation of rtl, the compiler makes no further distinction
1268: between pointers and any other objects of this machine mode. */
1269: #define Pmode SImode
1270:
1.1.1.2 root 1271: /* Generate calls to memcpy, memcmp and memset. */
1272: #define TARGET_MEM_FUNCTIONS
1273:
1.1 root 1274: /* Add any extra modes needed to represent the condition code.
1275:
1276: On the Sparc, we have a "no-overflow" mode which is used when an add or
1277: subtract insn is used to set the condition code. Different branches are
1278: used in this case for some operations.
1279:
1.1.1.3 ! root 1280: We also have two modes to indicate that the relevant condition code is
! 1281: in the floating-point condition code register. One for comparisons which
! 1282: will generate an exception if the result is unordered (CCFPEmode) and
! 1283: one for comparisons which will never trap (CCFPmode). This really should
! 1284: be a separate register, but we don't want to go to 65 registers. */
! 1285: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1.1 root 1286:
1287: /* Define the names for the modes specified above. */
1.1.1.3 ! root 1288: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1.1 root 1289:
1290: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1.1.1.3 ! root 1291: return the mode to be used for the comparison. For floating-point,
! 1292: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1.1 root 1293: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1294: needed. */
1295: #define SELECT_CC_MODE(OP,X) \
1.1.1.3 ! root 1296: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
! 1297: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
! 1298: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
! 1299: ? CC_NOOVmode : CCmode))
1.1 root 1300:
1301: /* A function address in a call instruction
1302: is a byte address (for indexing purposes)
1303: so give the MEM rtx a byte's mode. */
1304: #define FUNCTION_MODE SImode
1305:
1306: /* Define this if addresses of constant functions
1307: shouldn't be put through pseudo regs where they can be cse'd.
1308: Desirable on machines where ordinary constants are expensive
1309: but a CALL with constant address is cheap. */
1310: #define NO_FUNCTION_CSE
1311:
1312: /* alloca should avoid clobbering the old register save area. */
1313: #define SETJMP_VIA_SAVE_AREA
1314:
1315: /* Define subroutines to call to handle multiply and divide.
1316: Use the subroutines that Sun's library provides.
1317: The `*' prevents an underscore from being prepended by the compiler. */
1318:
1319: #define DIVSI3_LIBCALL "*.div"
1320: #define UDIVSI3_LIBCALL "*.udiv"
1321: #define MODSI3_LIBCALL "*.rem"
1322: #define UMODSI3_LIBCALL "*.urem"
1323: /* .umul is a little faster than .mul. */
1324: #define MULSI3_LIBCALL "*.umul"
1325:
1326: /* Compute the cost of computing a constant rtl expression RTX
1327: whose rtx-code is CODE. The body of this macro is a portion
1328: of a switch statement. If the code is computed here,
1329: return it with a return statement. Otherwise, break from the switch. */
1330:
1.1.1.3 ! root 1331: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1.1 root 1332: case CONST_INT: \
1333: if (INTVAL (RTX) == 0) \
1334: return 0; \
1335: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1336: return 1; \
1337: case HIGH: \
1338: return 2; \
1339: case CONST: \
1340: case LABEL_REF: \
1341: case SYMBOL_REF: \
1342: return 4; \
1343: case CONST_DOUBLE: \
1344: if (GET_MODE (RTX) == DImode) \
1345: if ((XINT (RTX, 3) == 0 \
1346: && (unsigned) XINT (RTX, 2) < 0x1000) \
1347: || (XINT (RTX, 3) == -1 \
1348: && XINT (RTX, 2) < 0 \
1349: && XINT (RTX, 2) >= -0x1000)) \
1350: return 1; \
1351: return 8;
1352:
1353: /* SPARC offers addressing modes which are "as cheap as a register".
1354: See sparc.c (or gcc.texinfo) for details. */
1355:
1356: #define ADDRESS_COST(RTX) \
1357: (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1358:
1359: /* Compute extra cost of moving data between one register class
1360: and another. */
1361: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1362: (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1363: || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1364:
1365: /* Provide the costs of a rtl expression. This is in the body of a
1366: switch on CODE. The purpose for the cost of MULT is to encourage
1367: `synth_mult' to find a synthetic multiply when reasonable.
1368:
1369: If we need more than 12 insns to do a multiply, then go out-of-line,
1370: since the call overhead will be < 10% of the cost of the multiply. */
1371:
1.1.1.3 ! root 1372: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1.1 root 1373: case MULT: \
1374: return COSTS_N_INSNS (25); \
1375: case DIV: \
1376: case UDIV: \
1377: case MOD: \
1378: case UMOD: \
1379: return COSTS_N_INSNS (20); \
1380: /* Make FLOAT more expensive than CONST_DOUBLE, \
1381: so that cse will favor the latter. */ \
1382: case FLOAT: \
1383: return 19;
1384:
1385: /* Conditional branches with empty delay slots have a length of two. */
1386: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1387: if (GET_CODE (INSN) == CALL_INSN \
1388: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1389: LENGTH += 1;
1390:
1391: /* Control the assembler format that we output. */
1392:
1393: /* Output at beginning of assembler file. */
1394:
1395: #define ASM_FILE_START(file)
1396:
1397: /* Output to assembler file text saying following lines
1398: may contain character constants, extra white space, comments, etc. */
1399:
1400: #define ASM_APP_ON ""
1401:
1402: /* Output to assembler file text saying following lines
1403: no longer contain unusual constructs. */
1404:
1405: #define ASM_APP_OFF ""
1406:
1407: /* Output before read-only data. */
1408:
1409: #define TEXT_SECTION_ASM_OP ".text"
1410:
1411: /* Output before writable data. */
1412:
1413: #define DATA_SECTION_ASM_OP ".data"
1414:
1415: /* How to refer to registers in assembler output.
1416: This sequence is indexed by compiler's hard-register-number (see above). */
1417:
1418: #define REGISTER_NAMES \
1419: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1420: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1421: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1422: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1423: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1424: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1425: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1426: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1427:
1.1.1.3 ! root 1428: /* Define additional names for use in asm clobbers and asm declarations.
! 1429:
! 1430: We define the fake Condition Code register as an alias for reg 0 (which
! 1431: is our `condition code' register), so that condition codes can easily
! 1432: be clobbered by an asm. No such register actually exists. Condition
! 1433: codes are partly stored in the PSR and partly in the FSR. */
! 1434:
! 1435: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
! 1436:
1.1 root 1437: /* How to renumber registers for dbx and gdb. */
1438:
1439: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1440:
1441: /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1442: since the length can run past this up to a continuation point. */
1443: #define DBX_CONTIN_LENGTH 1500
1444:
1445: /* This is how to output a note to DBX telling it the line number
1446: to which the following sequence of instructions corresponds.
1447:
1448: This is needed for SunOS 4.0, and should not hurt for 3.2
1449: versions either. */
1450: #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1451: { static int sym_lineno = 1; \
1452: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1453: line, sym_lineno, sym_lineno); \
1454: sym_lineno += 1; }
1455:
1456: /* This is how to output the definition of a user-level label named NAME,
1457: such as the label on a static function or variable NAME. */
1458:
1459: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1460: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1461:
1462: /* This is how to output a command to make the user-level label named NAME
1463: defined for reference from other files. */
1464:
1465: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1466: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1467:
1468: /* This is how to output a reference to a user-level label named NAME.
1469: `assemble_name' uses this. */
1470:
1471: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1472: fprintf (FILE, "_%s", NAME)
1473:
1474: /* This is how to output an internal numbered label where
1475: PREFIX is the class of label and NUM is the number within the class. */
1476:
1477: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1478: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1479:
1480: /* This is how to store into the string LABEL
1481: the symbol_ref name of an internal numbered label where
1482: PREFIX is the class of label and NUM is the number within the class.
1483: This is suitable for output with `assemble_name'. */
1484:
1485: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1486: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1487:
1488: /* This is how to output an assembler line defining a `double' constant. */
1489:
1.1.1.2 root 1490: /* Assemblers (both gas 1.35 and as in 4.0.3)
1491: seem to treat -0.0 as if it were 0.0.
1492: They reject 99e9999, but accept inf. */
1.1 root 1493: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1494: { \
1495: if (REAL_VALUE_ISINF (VALUE)) \
1.1.1.2 root 1496: fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1497: else if (REAL_VALUE_ISNAN (VALUE) \
1498: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1.1 root 1499: { \
1500: union { double d; long l[2];} t; \
1501: t.d = (VALUE); \
1502: fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1503: } \
1504: else \
1505: fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1506: }
1507:
1508: /* This is how to output an assembler line defining a `float' constant. */
1509:
1510: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1511: { \
1512: if (REAL_VALUE_ISINF (VALUE)) \
1.1.1.2 root 1513: fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1514: else if (REAL_VALUE_ISNAN (VALUE) \
1515: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1.1 root 1516: { \
1517: union { float f; long l;} t; \
1518: t.f = (VALUE); \
1519: fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1520: } \
1521: else \
1522: fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1523: }
1524:
1525: /* This is how to output an assembler line defining an `int' constant. */
1526:
1527: #define ASM_OUTPUT_INT(FILE,VALUE) \
1528: ( fprintf (FILE, "\t.word "), \
1529: output_addr_const (FILE, (VALUE)), \
1530: fprintf (FILE, "\n"))
1531:
1532: /* This is how to output an assembler line defining a DImode constant. */
1533: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1534: output_double_int (FILE, VALUE)
1535:
1536: /* Likewise for `char' and `short' constants. */
1537:
1538: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1539: ( fprintf (FILE, "\t.half "), \
1540: output_addr_const (FILE, (VALUE)), \
1541: fprintf (FILE, "\n"))
1542:
1543: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1544: ( fprintf (FILE, "\t.byte "), \
1545: output_addr_const (FILE, (VALUE)), \
1546: fprintf (FILE, "\n"))
1547:
1548: /* This is how to output an assembler line for a numeric constant byte. */
1549:
1550: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1551: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1552:
1553: /* This is how to output an element of a case-vector that is absolute. */
1554:
1555: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1.1.1.3 ! root 1556: do { \
! 1557: char label[30]; \
! 1558: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
! 1559: fprintf (FILE, "\t.word\t"); \
! 1560: assemble_name (FILE, label); \
! 1561: fprintf (FILE, "\n"); \
! 1562: } while (0)
1.1 root 1563:
1564: /* This is how to output an element of a case-vector that is relative.
1565: (SPARC uses such vectors only when generating PIC.) */
1566:
1.1.1.3 ! root 1567: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
! 1568: do { \
! 1569: char label[30]; \
! 1570: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
! 1571: fprintf (FILE, "\t.word\t"); \
! 1572: assemble_name (FILE, label); \
! 1573: fprintf (FILE, "-1b\n"); \
! 1574: } while (0)
1.1 root 1575:
1576: /* This is how to output an assembler line
1577: that says to advance the location counter
1578: to a multiple of 2**LOG bytes. */
1579:
1580: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1581: if ((LOG) != 0) \
1582: fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1583:
1584: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1585: fprintf (FILE, "\t.skip %u\n", (SIZE))
1586:
1587: /* This says how to output an assembler line
1588: to define a global common symbol. */
1589:
1590: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1591: ( fputs ("\t.global ", (FILE)), \
1592: assemble_name ((FILE), (NAME)), \
1593: fputs ("\n\t.common ", (FILE)), \
1594: assemble_name ((FILE), (NAME)), \
1595: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1596:
1597: /* This says how to output an assembler line
1598: to define a local common symbol. */
1599:
1600: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1601: ( fputs ("\n\t.reserve ", (FILE)), \
1602: assemble_name ((FILE), (NAME)), \
1603: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1604:
1605: /* Store in OUTPUT a string (made with alloca) containing
1606: an assembler-name for a local static variable named NAME.
1607: LABELNO is an integer which is different for each call. */
1608:
1609: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1610: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1611: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1612:
1613: /* Define the parentheses used to group arithmetic operations
1614: in assembler code. */
1615:
1616: #define ASM_OPEN_PAREN "("
1617: #define ASM_CLOSE_PAREN ")"
1618:
1619: /* Define results of standard character escape sequences. */
1620: #define TARGET_BELL 007
1621: #define TARGET_BS 010
1622: #define TARGET_TAB 011
1623: #define TARGET_NEWLINE 012
1624: #define TARGET_VT 013
1625: #define TARGET_FF 014
1626: #define TARGET_CR 015
1627:
1628: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1629: ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1630:
1631: /* Print operand X (an rtx) in assembler syntax to file FILE.
1632: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1633: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1634:
1635: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1636:
1637: /* Print a memory address as an operand to reference that memory location. */
1638:
1639: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1640: { register rtx base, index = 0; \
1641: int offset = 0; \
1642: register rtx addr = ADDR; \
1643: if (GET_CODE (addr) == REG) \
1644: fputs (reg_names[REGNO (addr)], FILE); \
1645: else if (GET_CODE (addr) == PLUS) \
1646: { \
1647: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1648: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1649: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1650: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1651: else \
1652: base = XEXP (addr, 0), index = XEXP (addr, 1); \
1653: fputs (reg_names[REGNO (base)], FILE); \
1654: if (index == 0) \
1655: fprintf (FILE, "%+d", offset); \
1656: else if (GET_CODE (index) == REG) \
1657: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1658: else if (GET_CODE (index) == SYMBOL_REF) \
1659: fputc ('+', FILE), output_addr_const (FILE, index); \
1660: else abort (); \
1661: } \
1662: else if (GET_CODE (addr) == MINUS \
1663: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1664: { \
1665: output_addr_const (FILE, XEXP (addr, 0)); \
1666: fputs ("-(", FILE); \
1667: output_addr_const (FILE, XEXP (addr, 1)); \
1668: fputs ("-.)", FILE); \
1669: } \
1670: else if (GET_CODE (addr) == LO_SUM) \
1671: { \
1672: output_operand (XEXP (addr, 0), 0); \
1673: fputs ("+%lo(", FILE); \
1674: output_address (XEXP (addr, 1)); \
1675: fputc (')', FILE); \
1676: } \
1677: else if (flag_pic && GET_CODE (addr) == CONST \
1678: && GET_CODE (XEXP (addr, 0)) == MINUS \
1679: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1680: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1681: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1682: { \
1683: addr = XEXP (addr, 0); \
1684: output_addr_const (FILE, XEXP (addr, 0)); \
1685: /* Group the args of the second CONST in parenthesis. */ \
1686: fputs ("-(", FILE); \
1687: /* Skip past the second CONST--it does nothing for us. */\
1688: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1689: /* Close the parenthesis. */ \
1690: fputc (')', FILE); \
1691: } \
1692: else \
1693: { \
1694: output_addr_const (FILE, addr); \
1695: } \
1696: }
1697:
1698: /* Declare functions defined in sparc.c and used in templates. */
1699:
1700: extern char *singlemove_string ();
1701: extern char *output_move_double ();
1.1.1.3 ! root 1702: extern char *output_move_quad ();
1.1 root 1703: extern char *output_fp_move_double ();
1.1.1.3 ! root 1704: extern char *output_fp_move_quad ();
1.1 root 1705: extern char *output_block_move ();
1706: extern char *output_scc_insn ();
1707: extern char *output_cbranch ();
1708: extern char *output_return ();
1709: extern char *output_floatsisf2 ();
1710: extern char *output_floatsidf2 ();
1.1.1.3 ! root 1711: extern char *output_floatsitf2 ();
1.1 root 1712:
1713: /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1714:
1715: extern int flag_pic;
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