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1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3: Contributed by Michael Tiemann ([email protected]).
4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21: /* Note that some other tm.h files include this one and then override
22: many of the definitions that relate to assembler syntax. */
23:
24: #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
25:
1.1.1.2 root 26: /* Provide required defaults for linker -e and -d switches. */
1.1 root 27:
1.1.1.3 root 28: #define LINK_SPEC \
1.1.1.4 ! root 29: "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
1.1 root 30:
31: /* Special flags to the Sun-4 assembler when using pipe for input. */
32:
33: #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
34:
1.1.1.3 root 35: /* Define macros to distinguish architectures. */
1.1.1.4 ! root 36: #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
1.1.1.3 root 37:
1.1.1.2 root 38: /* Prevent error on `-sun4' and `-target sun4' options. */
39: /* This used to translate -dalign to -malign, but that is no good
40: because it can't turn off the usual meaning of making debugging dumps. */
1.1 root 41:
1.1.1.2 root 42: #define CC1_SPEC "%{sun4:} %{target:}"
1.1 root 43:
1.1.1.3 root 44: #if 0
45: /* Sparc ABI says that long double is 4 words.
46: ??? This doesn't work yet. */
47: #define LONG_DOUBLE_TYPE_SIZE 128
48: #endif
49:
1.1 root 50: #define PTRDIFF_TYPE "int"
51: #define SIZE_TYPE "int"
52: #define WCHAR_TYPE "short unsigned int"
53: #define WCHAR_TYPE_SIZE 16
54:
1.1.1.2 root 55: /* Omit frame pointer at high optimization levels. */
1.1 root 56:
57: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
58: { \
59: if (OPTIMIZE >= 2) \
60: { \
61: flag_omit_frame_pointer = 1; \
62: } \
63: }
64:
65: /* These compiler options take an argument. We ignore -target for now. */
66:
67: #define WORD_SWITCH_TAKES_ARG(STR) \
1.1.1.4 ! root 68: (!strcmp (STR, "Tdata") || !strcmp (STR, "Ttext") \
! 69: || !strcmp (STR, "Tbss") || !strcmp (STR, "include") \
1.1 root 70: || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
1.1.1.2 root 71: || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
1.1 root 72:
73: /* Names to predefine in the preprocessor for this target machine. */
74:
75: #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
76:
77: /* Print subsidiary information on the compiler version in use. */
78:
79: #define TARGET_VERSION fprintf (stderr, " (sparc)");
80:
81: /* Generate DBX debugging information. */
82:
83: #define DBX_DEBUGGING_INFO
84:
85: /* Run-time compilation parameters selecting different hardware subsets. */
86:
87: extern int target_flags;
88:
89: /* Nonzero if we should generate code to use the fpu. */
90: #define TARGET_FPU (target_flags & 1)
91:
92: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
93: use fast return insns, but lose some generality. */
94: #define TARGET_EPILOGUE (target_flags & 2)
95:
1.1.1.2 root 96: /* Nonzero means that reference doublewords as if they were guaranteed
97: to be aligned...if they aren't, too bad for the user!
1.1.1.3 root 98: Like -dalign in Sun cc. */
1.1.1.2 root 99: #define TARGET_HOPE_ALIGN (target_flags & 16)
100:
1.1.1.3 root 101: /* Nonzero means make sure all doubles are on 8-byte boundaries.
102: This option results in a calling convention that is incompatible with
103: every other sparc compiler in the world, and thus should only ever be
104: used for experimenting. Also, varargs won't work with it, but it doesn't
105: seem worth trying to fix. */
1.1.1.2 root 106: #define TARGET_FORCE_ALIGN (target_flags & 32)
1.1 root 107:
1.1.1.3 root 108: /* Nonzero means that we should generate code for a v8 sparc. */
109: #define TARGET_V8 (target_flags & 64)
110:
111: /* Nonzero means that we should generate code for a sparclite. */
112: #define TARGET_SPARCLITE (target_flags & 128)
113:
1.1 root 114: /* Macro to define tables used to set the flags.
115: This is a list in braces of pairs in braces,
116: each pair being { "NAME", VALUE }
117: where VALUE is the bits to set or minus the bits to clear.
118: An empty string NAME is used to identify the default VALUE. */
119:
120: #define TARGET_SWITCHES \
121: { {"fpu", 1}, \
122: {"soft-float", -1}, \
123: {"epilogue", 2}, \
124: {"no-epilogue", -2}, \
1.1.1.2 root 125: {"hope-align", 16}, \
126: {"force-align", 48}, \
1.1.1.3 root 127: {"v8", 64}, \
128: {"no-v8", -64}, \
129: {"sparclite", 128}, \
130: {"no-sparclite", -128}, \
1.1.1.2 root 131: { "", TARGET_DEFAULT}}
1.1 root 132:
133: #define TARGET_DEFAULT 3
134:
135: /* target machine storage layout */
136:
137: /* Define this if most significant bit is lowest numbered
138: in instructions that operate on numbered bit-fields. */
139: #define BITS_BIG_ENDIAN 1
140:
141: /* Define this if most significant byte of a word is the lowest numbered. */
142: /* This is true on the SPARC. */
143: #define BYTES_BIG_ENDIAN 1
144:
145: /* Define this if most significant word of a multiword number is the lowest
146: numbered. */
147: /* Doubles are stored in memory with the high order word first. This
148: matters when cross-compiling. */
149: #define WORDS_BIG_ENDIAN 1
150:
1.1.1.2 root 151: /* number of bits in an addressable storage unit */
1.1 root 152: #define BITS_PER_UNIT 8
153:
154: /* Width in bits of a "word", which is the contents of a machine register.
155: Note that this is not necessarily the width of data type `int';
156: if using 16-bit ints on a 68000, this would still be 32.
157: But on a machine with 16-bit registers, this would be 16. */
158: #define BITS_PER_WORD 32
159: #define MAX_BITS_PER_WORD 32
160:
161: /* Width of a word, in units (bytes). */
162: #define UNITS_PER_WORD 4
163:
164: /* Width in bits of a pointer.
165: See also the macro `Pmode' defined below. */
166: #define POINTER_SIZE 32
167:
168: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
169: #define PARM_BOUNDARY 32
170:
171: /* Boundary (in *bits*) on which stack pointer should be aligned. */
172: #define STACK_BOUNDARY 64
173:
1.1.1.4 ! root 174: /* ALIGN FRAMES on double word boundaries */
! 175:
! 176: #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
! 177:
1.1 root 178: /* Allocation boundary (in *bits*) for the code of a function. */
179: #define FUNCTION_BOUNDARY 32
180:
181: /* Alignment of field after `int : 0' in a structure. */
182: #define EMPTY_FIELD_BOUNDARY 32
183:
184: /* Every structure's size must be a multiple of this. */
185: #define STRUCTURE_SIZE_BOUNDARY 8
186:
187: /* A bitfield declared as `int' forces `int' alignment for the struct. */
188: #define PCC_BITFIELD_TYPE_MATTERS 1
189:
190: /* No data type wants to be aligned rounder than this. */
191: #define BIGGEST_ALIGNMENT 64
192:
1.1.1.3 root 193: /* The best alignment to use in cases where we have a choice. */
194: #define FASTEST_ALIGNMENT 64
195:
1.1 root 196: /* Make strings word-aligned so strcpy from constants will be faster. */
197: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1.1.1.4 ! root 198: ((TREE_CODE (EXP) == STRING_CST \
! 199: && (ALIGN) < FASTEST_ALIGNMENT) \
! 200: ? FASTEST_ALIGNMENT : (ALIGN))
1.1 root 201:
202: /* Make arrays of chars word-aligned for the same reasons. */
203: #define DATA_ALIGNMENT(TYPE, ALIGN) \
204: (TREE_CODE (TYPE) == ARRAY_TYPE \
205: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
1.1.1.3 root 206: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
1.1 root 207:
1.1.1.2 root 208: /* Set this nonzero if move instructions will actually fail to work
1.1 root 209: when given unaligned data. */
1.1.1.2 root 210: #define STRICT_ALIGNMENT 1
1.1 root 211:
212: /* Things that must be doubleword aligned cannot go in the text section,
213: because the linker fails to align the text section enough!
214: Put them in the data section. */
215: #define MAX_TEXT_ALIGN 32
216:
217: #define SELECT_SECTION(T,RELOC) \
218: { \
219: if (TREE_CODE (T) == VAR_DECL) \
220: { \
221: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
222: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
223: && ! (flag_pic && (RELOC))) \
224: text_section (); \
225: else \
226: data_section (); \
227: } \
228: else if (TREE_CODE (T) == CONSTRUCTOR) \
229: { \
230: if (flag_pic != 0 && (RELOC) != 0) \
231: data_section (); \
232: } \
233: else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
234: { \
235: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
236: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
237: data_section (); \
238: else \
239: text_section (); \
240: } \
241: }
242:
243: /* Use text section for a constant
244: unless we need more alignment than that offers. */
245: #define SELECT_RTX_SECTION(MODE, X) \
246: { \
247: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
248: && ! (flag_pic && symbolic_operand (X))) \
249: text_section (); \
250: else \
251: data_section (); \
252: }
253:
254: /* Standard register usage. */
255:
256: /* Number of actual hardware registers.
257: The hardware registers are assigned numbers for the compiler
258: from 0 to just below FIRST_PSEUDO_REGISTER.
259: All registers that the compiler knows about must be given numbers,
260: even those that are not normally considered general registers.
261:
262: SPARC has 32 integer registers and 32 floating point registers. */
263:
264: #define FIRST_PSEUDO_REGISTER 64
265:
266: /* 1 for registers that have pervasive standard uses
267: and are not available for the register allocator.
268: 0 is used for the condition code and not to represent %g0, which is
269: hardwired to 0, so reg 0 is *not* fixed.
1.1.1.3 root 270: g1 through g4 are free to use as temporaries.
271: g5 through g7 are reserved for the operating system. */
1.1 root 272: #define FIXED_REGISTERS \
1.1.1.3 root 273: {0, 0, 0, 0, 0, 1, 1, 1, \
1.1 root 274: 0, 0, 0, 0, 0, 0, 1, 0, \
275: 0, 0, 0, 0, 0, 0, 0, 0, \
276: 0, 0, 0, 0, 0, 0, 1, 1, \
277: \
278: 0, 0, 0, 0, 0, 0, 0, 0, \
279: 0, 0, 0, 0, 0, 0, 0, 0, \
280: 0, 0, 0, 0, 0, 0, 0, 0, \
281: 0, 0, 0, 0, 0, 0, 0, 0}
282:
283: /* 1 for registers not available across function calls.
284: These must include the FIXED_REGISTERS and also any
285: registers that can be used without being saved.
286: The latter must include the registers where values are returned
287: and the register where structure-value addresses are passed.
288: Aside from that, you can include as many other registers as you like. */
289: #define CALL_USED_REGISTERS \
290: {1, 1, 1, 1, 1, 1, 1, 1, \
291: 1, 1, 1, 1, 1, 1, 1, 1, \
292: 0, 0, 0, 0, 0, 0, 0, 0, \
293: 0, 0, 0, 0, 0, 0, 1, 1, \
294: \
295: 1, 1, 1, 1, 1, 1, 1, 1, \
296: 1, 1, 1, 1, 1, 1, 1, 1, \
297: 1, 1, 1, 1, 1, 1, 1, 1, \
298: 1, 1, 1, 1, 1, 1, 1, 1}
299:
300: /* Return number of consecutive hard regs needed starting at reg REGNO
301: to hold something of mode MODE.
302: This is ordinarily the length in words of a value of mode MODE
303: but can be less for certain modes in special long registers.
304:
305: On SPARC, ordinary registers hold 32 bits worth;
306: this means both integer and floating point registers.
307:
308: We use vectors to keep this information about registers. */
309:
310: /* How many hard registers it takes to make a register of this mode. */
311: extern int hard_regno_nregs[];
312:
313: #define HARD_REGNO_NREGS(REGNO, MODE) \
314: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
315:
316: /* Value is 1 if register/mode pair is acceptable on sparc. */
317: extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
318:
319: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
320: On SPARC, the cpu registers can hold any mode but the float registers
321: can only hold SFmode or DFmode. See sparc.c for how we
322: initialize this. */
323: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
324: ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
325:
326: /* Value is 1 if it is a good idea to tie two pseudo registers
327: when one has mode MODE1 and one has mode MODE2.
328: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
329: for any hard reg, then this must be 0 for correct output. */
330: #define MODES_TIEABLE_P(MODE1, MODE2) \
331: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
332:
333: /* Specify the registers used for certain standard purposes.
334: The values of these macros are register numbers. */
335:
336: /* SPARC pc isn't overloaded on a register that the compiler knows about. */
337: /* #define PC_REGNUM */
338:
339: /* Register to use for pushing function arguments. */
340: #define STACK_POINTER_REGNUM 14
341:
342: /* Actual top-of-stack address is 92 greater than the contents
343: of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
344: for the ins and local registers, 4 byte for structure return address, and
345: 24 bytes for the 6 register parameters. */
346: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
347:
348: /* Base register for access to local variables of the function. */
349: #define FRAME_POINTER_REGNUM 30
350:
351: #if 0
352: /* Register that is used for the return address. */
353: #define RETURN_ADDR_REGNUM 15
354: #endif
355:
356: /* Value should be nonzero if functions must have frame pointers.
357: Zero means the frame pointer need not be set up (and parms
358: may be accessed via the stack pointer) in functions that seem suitable.
359: This is computed in `reload', in reload1.c.
360:
1.1.1.4 ! root 361: Used in flow.c, global.c, and reload1.c. */
1.1 root 362: extern int leaf_function;
363:
364: #define FRAME_POINTER_REQUIRED \
365: (! (leaf_function_p () && only_leaf_regs_used ()))
366:
367: /* C statement to store the difference between the frame pointer
368: and the stack pointer values immediately after the function prologue.
369:
370: Note, we always pretend that this is a leaf function because if
371: it's not, there's no point in trying to eliminate the
372: frame pointer. If it is a leaf function, we guessed right! */
373: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
374: do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
375:
376: /* Base register for access to arguments of the function. */
377: #define ARG_POINTER_REGNUM 30
378:
379: /* Register in which static-chain is passed to a function. */
380: /* ??? */
381: #define STATIC_CHAIN_REGNUM 1
382:
383: /* Register which holds offset table for position-independent
384: data references. */
385:
386: #define PIC_OFFSET_TABLE_REGNUM 23
387:
388: #define INITIALIZE_PIC initialize_pic ()
389: #define FINALIZE_PIC finalize_pic ()
390:
1.1.1.3 root 391: /* Sparc ABI says that quad-precision floats and all structures are returned
392: in memory. We go along regarding floats, but for structures
393: we follow GCC's normal policy. Use -fpcc-struct-value
394: if you want to follow the ABI. */
395: #define RETURN_IN_MEMORY(TYPE) \
396: (TYPE_MODE (TYPE) == TFmode)
397:
1.1 root 398: /* Functions which return large structures get the address
399: to place the wanted value at offset 64 from the frame.
400: Must reserve 64 bytes for the in and local registers. */
401: /* Used only in other #defines in this file. */
402: #define STRUCT_VALUE_OFFSET 64
403:
404: #define STRUCT_VALUE \
405: gen_rtx (MEM, Pmode, \
406: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
407: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
408: #define STRUCT_VALUE_INCOMING \
409: gen_rtx (MEM, Pmode, \
410: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
411: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
412:
413: /* Define the classes of registers for register constraints in the
414: machine description. Also define ranges of constants.
415:
416: One of the classes must always be named ALL_REGS and include all hard regs.
417: If there is more than one class, another class must be named NO_REGS
418: and contain no registers.
419:
420: The name GENERAL_REGS must be the name of a class (or an alias for
421: another name such as ALL_REGS). This is the class of registers
422: that is allowed by "g" or "r" in a register constraint.
423: Also, registers outside this class are allocated only when
424: instructions express preferences for them.
425:
426: The classes must be numbered in nondecreasing order; that is,
427: a larger-numbered class must never be contained completely
428: in a smaller-numbered class.
429:
430: For any two classes, it is very desirable that there be another
431: class that represents their union. */
432:
433: /* The SPARC has two kinds of registers, general and floating point. */
434:
435: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
436:
437: #define N_REG_CLASSES (int) LIM_REG_CLASSES
438:
439: /* Give names of register classes as strings for dump file. */
440:
441: #define REG_CLASS_NAMES \
442: {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
443:
444: /* Define which registers fit in which classes.
445: This is an initializer for a vector of HARD_REG_SET
446: of length N_REG_CLASSES. */
447:
448: #if 0 && defined (__GNUC__)
449: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
450: #else
451: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
452: #endif
453:
454: /* The same information, inverted:
455: Return the class number of the smallest class containing
456: reg number REGNO. This could be a conditional expression
457: or could index an array. */
458:
459: #define REGNO_REG_CLASS(REGNO) \
460: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
461:
462: /* This is the order in which to allocate registers
463: normally. */
464: #define REG_ALLOC_ORDER \
1.1.1.2 root 465: { 8, 9, 10, 11, 12, 13, 2, 3, \
466: 15, 16, 17, 18, 19, 20, 21, 22, \
467: 23, 24, 25, 26, 27, 28, 29, 31, \
1.1 root 468: 32, 33, 34, 35, 36, 37, 38, 39, \
469: 40, 41, 42, 43, 44, 45, 46, 47, \
470: 48, 49, 50, 51, 52, 53, 54, 55, \
471: 56, 57, 58, 59, 60, 61, 62, 63, \
1.1.1.3 root 472: 1, 4, 5, 6, 7, 0, 14, 30}
1.1 root 473:
474: /* This is the order in which to allocate registers for
475: leaf functions. If all registers can fit in the "i" registers,
476: then we have the possibility of having a leaf function. */
477: #define REG_LEAF_ALLOC_ORDER \
478: { 2, 3, 24, 25, 26, 27, 28, 29, \
479: 15, 8, 9, 10, 11, 12, 13, \
480: 16, 17, 18, 19, 20, 21, 22, 23, \
481: 32, 33, 34, 35, 36, 37, 38, 39, \
482: 40, 41, 42, 43, 44, 45, 46, 47, \
483: 48, 49, 50, 51, 52, 53, 54, 55, \
484: 56, 57, 58, 59, 60, 61, 62, 63, \
1.1.1.3 root 485: 1, 4, 5, 6, 7, 0, 14, 30, 31}
1.1 root 486:
487: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
488:
489: #define LEAF_REGISTERS \
490: { 1, 1, 1, 1, 1, 1, 1, 1, \
491: 0, 0, 0, 0, 0, 0, 1, 0, \
492: 0, 0, 0, 0, 0, 0, 0, 0, \
493: 1, 1, 1, 1, 1, 1, 0, 1, \
494: 1, 1, 1, 1, 1, 1, 1, 1, \
495: 1, 1, 1, 1, 1, 1, 1, 1, \
496: 1, 1, 1, 1, 1, 1, 1, 1, \
1.1.1.3 root 497: 1, 1, 1, 1, 1, 1, 1, 1}
1.1 root 498:
499: extern char leaf_reg_remap[];
500: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
501: extern char leaf_reg_backmap[];
502: #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
503:
504: #define REG_USED_SO_FAR(REGNO) \
505: ((REGNO) >= 24 && (REGNO) < 30 \
506: ? (regs_ever_live[24] \
507: || regs_ever_live[25] \
508: || regs_ever_live[26] \
509: || regs_ever_live[27] \
510: || regs_ever_live[28] \
511: || regs_ever_live[29]) : 0)
512:
513: /* The class value for index registers, and the one for base regs. */
514: #define INDEX_REG_CLASS GENERAL_REGS
515: #define BASE_REG_CLASS GENERAL_REGS
516:
517: /* Get reg_class from a letter such as appears in the machine description. */
518:
519: #define REG_CLASS_FROM_LETTER(C) \
520: ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
521:
522: /* The letters I, J, K, L and M in a register constraint string
523: can be used to stand for particular ranges of immediate operands.
524: This macro defines what the ranges are.
525: C is the letter, and VALUE is a constant value.
526: Return 1 if VALUE is in the range specified by C.
527:
528: For SPARC, `I' is used for the range of constants an insn
529: can actually contain.
530: `J' is used for the range which is just zero (since that is R0).
531: `K' is used for the 5-bit operand of a compare insns. */
532:
533: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
534:
535: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
536: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
537: : (C) == 'J' ? (VALUE) == 0 \
538: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
539: : 0)
540:
541: /* Similar, but for floating constants, and defining letters G and H.
542: Here VALUE is the CONST_DOUBLE rtx itself. */
543:
544: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
545: ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
546: && CONST_DOUBLE_LOW (VALUE) == 0 \
547: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
548: : 0)
549:
550: /* Given an rtx X being reloaded into a reg required to be
551: in class CLASS, return the class of reg to actually use.
552: In general this is just CLASS; but on some machines
553: in some cases it is preferable to use a more restrictive class. */
1.1.1.3 root 554: /* We can't load constants into FP registers. We can't load any FP constant
555: if an 'E' constraint fails to match it. */
556: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
557: (CONSTANT_P (X) \
558: && ((CLASS) == FP_REGS \
559: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
560: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
561: || HOST_BITS_PER_INT != BITS_PER_WORD))) \
562: ? NO_REGS : (CLASS))
1.1 root 563:
564: /* Return the register class of a scratch register needed to load IN into
565: a register of class CLASS in MODE.
566:
567: On the SPARC, when PIC, we need a temporary when loading some addresses
1.1.1.4 ! root 568: into a register.
1.1 root 569:
1.1.1.4 ! root 570: Also, we need a temporary when loading/storing a HImode/QImode value
! 571: between memory and the FPU registers. This can happen when combine puts
! 572: a paradoxical subreg in a float/fix conversion insn. */
! 573:
! 574: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
! 575: (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS \
! 576: : ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
! 577: && (GET_CODE (IN) == MEM \
! 578: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
! 579: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
! 580:
! 581: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
! 582: ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
! 583: && (GET_CODE (IN) == MEM \
! 584: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
! 585: && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
! 586:
! 587: /* On SPARC it is not possible to directly move data between
! 588: GENERAL_REGS and FP_REGS. */
! 589: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
! 590: (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
! 591: || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
1.1 root 592:
593: /* Return the maximum number of consecutive registers
594: needed to represent mode MODE in a register of class CLASS. */
595: /* On SPARC, this is the size of MODE in words. */
596: #define CLASS_MAX_NREGS(CLASS, MODE) \
597: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
598:
599: /* Stack layout; function entry, exit and calling. */
600:
601: /* Define the number of register that can hold parameters.
602: These two macros are used only in other macro definitions below. */
603: #define NPARM_REGS 6
604:
605: /* Define this if pushing a word on the stack
606: makes the stack pointer a smaller address. */
607: #define STACK_GROWS_DOWNWARD
608:
609: /* Define this if the nominal address of the stack frame
610: is at the high-address end of the local variables;
611: that is, each additional local variable allocated
612: goes at a more negative offset in the frame. */
613: #define FRAME_GROWS_DOWNWARD
614:
615: /* Offset within stack frame to start allocating local variables at.
616: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
617: first local allocated. Otherwise, it is the offset to the BEGINNING
618: of the first local allocated. */
619: #define STARTING_FRAME_OFFSET (-16)
620:
621: /* If we generate an insn to push BYTES bytes,
622: this says how many the stack pointer really advances by.
623: On SPARC, don't define this because there are no push insns. */
624: /* #define PUSH_ROUNDING(BYTES) */
625:
626: /* Offset of first parameter from the argument pointer register value.
627: This is 64 for the ins and locals, plus 4 for the struct-return reg
1.1.1.3 root 628: even if this function isn't going to use it.
629: If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the
630: stack remains aligned. */
631: #define FIRST_PARM_OFFSET(FNDECL) \
632: (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0))
1.1 root 633:
634: /* When a parameter is passed in a register, stack space is still
635: allocated for it. */
636: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
637:
638: /* Keep the stack pointer constant throughout the function.
1.1.1.2 root 639: This is both an optimization and a necessity: longjmp
1.1 root 640: doesn't behave itself when the stack pointer moves within
641: the function! */
642: #define ACCUMULATE_OUTGOING_ARGS
643:
644: /* Value is the number of bytes of arguments automatically
645: popped when returning from a subroutine call.
646: FUNTYPE is the data type of the function (as a tree),
647: or for a library call it is an identifier node for the subroutine name.
648: SIZE is the number of bytes of arguments passed on the stack. */
649:
650: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
651:
652: /* Some subroutine macros specific to this machine. */
653: #define BASE_RETURN_VALUE_REG(MODE) \
654: ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
655: #define BASE_OUTGOING_VALUE_REG(MODE) \
656: ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
657: #define BASE_PASSING_ARG_REG(MODE) (8)
658: #define BASE_INCOMING_ARG_REG(MODE) (24)
659:
660: /* Define how to find the value returned by a function.
661: VALTYPE is the data type of the value (as a tree).
662: If the precise function being called is known, FUNC is its FUNCTION_DECL;
663: otherwise, FUNC is 0. */
664:
665: /* On SPARC the value is found in the first "output" register. */
666:
667: #define FUNCTION_VALUE(VALTYPE, FUNC) \
668: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
669:
670: /* But the called function leaves it in the first "input" register. */
671:
672: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
673: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
674:
675: /* Define how to find the value returned by a library function
676: assuming the value has mode MODE. */
677:
678: #define LIBCALL_VALUE(MODE) \
679: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
680:
681: /* 1 if N is a possible register number for a function value
682: as seen by the caller.
683: On SPARC, the first "output" reg is used for integer values,
684: and the first floating point register is used for floating point values. */
685:
686: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
687:
688: /* 1 if N is a possible register number for function argument passing.
689: On SPARC, these are the "output" registers. */
690:
691: #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
692:
693: /* Define a data type for recording info about an argument list
694: during the scan of that argument list. This data type should
695: hold all necessary information about the function itself
696: and about the args processed so far, enough to enable macros
697: such as FUNCTION_ARG to determine where the next arg should go.
698:
699: On SPARC, this is a single integer, which is a number of words
700: of arguments scanned so far (including the invisible argument,
701: if any, which holds the structure-value-address).
702: Thus 7 or more means all following args should go on the stack. */
703:
704: #define CUMULATIVE_ARGS int
705:
706: #define ROUND_ADVANCE(SIZE) \
1.1.1.2 root 707: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
708:
709: /* Round a register number up to a proper boundary for an arg of mode MODE.
710: Note that we need an odd/even pair for a two-word arg,
711: since that will become 8-byte aligned when stored in memory. */
712: #define ROUND_REG(X, MODE) \
713: (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
714: ? ((X) + ! ((X) & 1)) : (X))
1.1 root 715:
716: /* Initialize a variable CUM of type CUMULATIVE_ARGS
717: for a call to a function whose data type is FNTYPE.
718: For a library call, FNTYPE is 0.
719:
720: On SPARC, the offset always starts at 0: the first parm reg is always
721: the same reg. */
722:
723: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
724:
725: /* Update the data in CUM to advance over an argument
726: of mode MODE and data type TYPE.
727: (TYPE is null for libcalls where that information may not be available.) */
728:
729: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 730: ((CUM) = (ROUND_REG ((CUM), (MODE)) \
731: + ((MODE) != BLKmode \
732: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
733: : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
1.1 root 734:
735: /* Determine where to put an argument to a function.
736: Value is zero to push the argument on the stack,
737: or a hard register in which to store the argument.
738:
739: MODE is the argument's machine mode.
740: TYPE is the data type of the argument (as a tree).
741: This is null for libcalls where that information may
742: not be available.
743: CUM is a variable of type CUMULATIVE_ARGS which gives info about
744: the preceding args and about the function being called.
745: NAMED is nonzero if this argument is a named parameter
746: (otherwise it is an extra parameter matching an ellipsis). */
747:
748: /* On SPARC the first six args are normally in registers
749: and the rest are pushed. Any arg that starts within the first 6 words
750: is at least partially passed in a register unless its data type forbids. */
751:
752: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 753: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 754: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 755: && ((TYPE)==0 || (MODE) != BLKmode \
756: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
757: ? gen_rtx (REG, (MODE), \
758: (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
759: : 0)
1.1 root 760:
761: /* Define where a function finds its arguments.
762: This is different from FUNCTION_ARG because of register windows. */
763:
764: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 765: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 766: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 767: && ((TYPE)==0 || (MODE) != BLKmode \
768: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
769: ? gen_rtx (REG, (MODE), \
770: (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
771: : 0)
1.1 root 772:
773: /* For an arg passed partly in registers and partly in memory,
774: this is the number of registers used.
775: For args passed entirely in registers or entirely in memory, zero.
776: Any arg that starts in the first 6 regs but won't entirely fit in them
777: needs partial registers on the Sparc. */
778:
779: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1.1.1.2 root 780: ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
1.1 root 781: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1.1.1.2 root 782: && ((TYPE)==0 || (MODE) != BLKmode \
783: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
784: && (ROUND_REG ((CUM), (MODE)) \
1.1 root 785: + ((MODE) == BLKmode \
786: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1.1.1.2 root 787: : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
788: ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
1.1 root 789: : 0)
790:
1.1.1.3 root 791: /* The SPARC ABI stipulates passing struct arguments (of any size) and
792: quad-precision floats by invisible reference. */
1.1 root 793: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1.1.1.3 root 794: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
795: || TREE_CODE (TYPE) == UNION_TYPE)) \
796: || (MODE == TFmode))
1.1 root 797:
1.1.1.2 root 798: /* If defined, a C expression that gives the alignment boundary, in
799: bits, of an argument with the specified mode and type. If it is
800: not defined, `PARM_BOUNDARY' is used for all arguments.
801:
802: This definition does nothing special unless TARGET_FORCE_ALIGN;
803: in that case, it aligns each arg to the natural boundary. */
804:
805: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
806: (! TARGET_FORCE_ALIGN \
807: ? PARM_BOUNDARY \
808: : (((TYPE) != 0) \
809: ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
810: ? PARM_BOUNDARY \
811: : TYPE_ALIGN (TYPE)) \
812: : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
813: ? PARM_BOUNDARY \
814: : GET_MODE_ALIGNMENT (MODE))))
815:
1.1 root 816: /* Define the information needed to generate branch and scc insns. This is
817: stored from the compare operation. Note that we can't use "rtx" here
818: since it hasn't been defined! */
819:
820: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
821:
822: /* Define the function that build the compare insn for scc and bcc. */
823:
824: extern struct rtx_def *gen_compare_reg ();
825:
1.1.1.3 root 826: /* Generate the special assembly code needed to tell the assembler whatever
827: it might need to know about the return value of a function.
828:
829: For Sparc assemblers, we need to output a .proc pseudo-op which conveys
830: information to the assembler relating to peephole optimization (done in
831: the assembler). */
832:
833: #define ASM_DECLARE_RESULT(FILE, RESULT) \
834: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
835:
1.1 root 836: /* Output the label for a function definition. */
837:
1.1.1.3 root 838: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
839: do { \
840: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
841: ASM_OUTPUT_LABEL (FILE, NAME); \
842: } while (0)
1.1 root 843:
844: /* Two views of the size of the current frame. */
845: extern int actual_fsize;
846: extern int apparent_fsize;
847:
848: /* This macro generates the assembly code for function entry.
849: FILE is a stdio stream to output the code to.
850: SIZE is an int: how many units of temporary storage to allocate.
851: Refer to the array `regs_ever_live' to determine which registers
852: to save; `regs_ever_live[I]' is nonzero if register number I
853: is ever used in the function. This macro is responsible for
854: knowing which registers should not be saved even if used. */
855:
856: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
857: of memory. If any fpu reg is used in the function, we allocate
858: such a block here, at the bottom of the frame, just in case it's needed.
859:
860: If this function is a leaf procedure, then we may choose not
861: to do a "save" insn. The decision about whether or not
862: to do this is made in regclass.c. */
863:
864: #define FUNCTION_PROLOGUE(FILE, SIZE) \
865: output_function_prologue (FILE, SIZE, leaf_function)
866:
867: /* Output assembler code to FILE to increment profiler label # LABELNO
868: for profiling a function entry. */
869:
1.1.1.4 ! root 870: #define FUNCTION_PROFILER(FILE, LABELNO) \
! 871: do { \
! 872: fputs ("\tsethi %hi(", (FILE)); \
! 873: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
! 874: fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
! 875: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
! 876: fputs ("),%o0,%o0\n", (FILE)); \
! 877: } while (0)
1.1 root 878:
879: /* Output assembler code to FILE to initialize this source file's
880: basic block profiling info, if that has not already been done. */
1.1.1.4 ! root 881: /* FIXME -- this does not parameterize how it generates labels (like the
! 882: above FUNCTION_PROFILER). Broken on Solaris-2. [email protected] */
1.1 root 883:
884: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
885: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
886: (LABELNO), (LABELNO))
887:
888: /* Output assembler code to FILE to increment the entry-count for
889: the BLOCKNO'th basic block in this source file. */
890:
891: #define BLOCK_PROFILER(FILE, BLOCKNO) \
892: { \
893: int blockn = (BLOCKNO); \
894: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
895: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
896: 4 * blockn, 4 * blockn, 4 * blockn); \
897: }
898:
899: /* Output rtl to increment the entry-count for the LABELNO'th instrumented
900: arc in this source file. */
901:
902: #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
903: output_arc_profiler (ARCNO, INSERT_AFTER)
904:
905: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
906: the stack pointer does not matter. The value is tested only in
907: functions that have frame pointers.
908: No definition is equivalent to always zero. */
909:
910: extern int current_function_calls_alloca;
911: extern int current_function_outgoing_args_size;
912:
913: #define EXIT_IGNORE_STACK \
914: (get_frame_size () != 0 \
915: || current_function_calls_alloca || current_function_outgoing_args_size)
916:
917: /* This macro generates the assembly code for function exit,
918: on machines that need it. If FUNCTION_EPILOGUE is not defined
919: then individual return instructions are generated for each
920: return statement. Args are same as for FUNCTION_PROLOGUE.
921:
922: The function epilogue should not depend on the current stack pointer!
923: It should use the frame pointer only. This is mandatory because
924: of alloca; we also take advantage of it to omit stack adjustments
925: before returning. */
926:
927: /* This declaration is needed due to traditional/ANSI
928: incompatibilities which cannot be #ifdefed away
929: because they occur inside of macros. Sigh. */
930: extern union tree_node *current_function_decl;
931:
932: #define FUNCTION_EPILOGUE(FILE, SIZE) \
1.1.1.3 root 933: output_function_epilogue (FILE, SIZE, leaf_function)
1.1 root 934:
935: #define DELAY_SLOTS_FOR_EPILOGUE 1
936: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
937: eligible_for_epilogue_delay (trial, slots_filled)
938:
939: /* Output assembler code for a block containing the constant parts
940: of a trampoline, leaving space for the variable parts. */
941:
942: /* On the sparc, the trampoline contains five instructions:
943: sethi #TOP_OF_FUNCTION,%g2
944: or #BOTTOM_OF_FUNCTION,%g2,%g2
945: sethi #TOP_OF_STATIC,%g1
946: jmp g2
947: or #BOTTOM_OF_STATIC,%g1,%g1 */
948: #define TRAMPOLINE_TEMPLATE(FILE) \
949: { \
950: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
951: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
952: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
953: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
954: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
955: }
956:
957: /* Length in units of the trampoline for entering a nested function. */
958:
959: #define TRAMPOLINE_SIZE 20
960:
961: /* Emit RTL insns to initialize the variable parts of a trampoline.
962: FNADDR is an RTX for the address of the function's pure code.
963: CXT is an RTX for the static chain value for the function.
964:
965: This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
966: (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
967: (to store insns). This is a bit excessive. Perhaps a different
968: mechanism would be better here. */
969:
970: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
971: { \
972: rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
973: size_int (10), 0, 1); \
974: rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
975: size_int (10), 0, 1); \
976: rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
977: rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
978: rtx g1_sethi = gen_rtx (HIGH, SImode, \
979: gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
980: rtx g2_sethi = gen_rtx (HIGH, SImode, \
981: gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
982: rtx g1_ori = gen_rtx (HIGH, SImode, \
983: gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
984: rtx g2_ori = gen_rtx (HIGH, SImode, \
985: gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
986: rtx tem = gen_reg_rtx (SImode); \
987: emit_move_insn (tem, g2_sethi); \
988: emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
989: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
990: emit_move_insn (tem, g2_ori); \
991: emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
992: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
993: emit_move_insn (tem, g1_sethi); \
994: emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
995: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
996: emit_move_insn (tem, g1_ori); \
997: emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
998: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
999: }
1000:
1001: /* Emit code for a call to builtin_saveregs. We must emit USE insns which
1002: reference the 6 input registers. Ordinarily they are not call used
1003: registers, but they are for _builtin_saveregs, so we must make this
1004: explicit. */
1005:
1006: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
1007: (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
1008: emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
1009: expand_call (exp, target, ignore))
1010:
1011: /* Addressing modes, and classification of registers for them. */
1012:
1013: /* #define HAVE_POST_INCREMENT */
1014: /* #define HAVE_POST_DECREMENT */
1015:
1016: /* #define HAVE_PRE_DECREMENT */
1017: /* #define HAVE_PRE_INCREMENT */
1018:
1019: /* Macros to check register numbers against specific register classes. */
1020:
1021: /* These assume that REGNO is a hard or pseudo reg number.
1022: They give nonzero only if REGNO is a hard reg of the suitable class
1023: or a pseudo reg currently allocated to a suitable hard reg.
1024: Since they use reg_renumber, they are safe only once reg_renumber
1025: has been allocated, which happens in local-alloc.c. */
1026:
1027: #define REGNO_OK_FOR_INDEX_P(REGNO) \
1028: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1029: #define REGNO_OK_FOR_BASE_P(REGNO) \
1030: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1031: #define REGNO_OK_FOR_FP_P(REGNO) \
1032: (((REGNO) ^ 0x20) < 32 \
1033: || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1034:
1035: /* Now macros that check whether X is a register and also,
1036: strictly, whether it is in a specified class.
1037:
1038: These macros are specific to the SPARC, and may be used only
1039: in code for printing assembler insns and in conditions for
1040: define_optimization. */
1041:
1042: /* 1 if X is an fp register. */
1043:
1044: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1045:
1046: /* Maximum number of registers that can appear in a valid memory address. */
1047:
1048: #define MAX_REGS_PER_ADDRESS 2
1049:
1050: /* Recognize any constant value that is a valid address. */
1051:
1052: #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1053:
1054: /* Nonzero if the constant value X is a legitimate general operand.
1055: Anything can be made to work except floating point constants. */
1056:
1057: #define LEGITIMATE_CONSTANT_P(X) \
1058: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1059:
1060: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1061: and check its validity for a certain class.
1062: We have two alternate definitions for each of them.
1063: The usual definition accepts all pseudo regs; the other rejects
1064: them unless they have been allocated suitable hard regs.
1065: The symbol REG_OK_STRICT causes the latter definition to be used.
1066:
1067: Most source files want to accept pseudo regs in the hope that
1068: they will get allocated to the class that the insn wants them to be in.
1069: Source files for reload pass need to be strict.
1070: After reload, it makes no difference, since pseudo regs have
1071: been eliminated by then. */
1072:
1073: /* Optional extra constraints for this machine. Borrowed from romp.h.
1074:
1075: For the SPARC, `Q' means that this is a memory operand but not a
1076: symbolic memory operand. Note that an unassigned pseudo register
1077: is such a memory operand. Needed because reload will generate
1078: these things in insns and then not re-recognize the insns, causing
1079: constrain_operands to fail.
1080:
1081: `R' handles the LO_SUM which can be an address for `Q'.
1082:
1083: `S' handles constraints for calls. */
1084:
1085: #ifndef REG_OK_STRICT
1086:
1087: /* Nonzero if X is a hard reg that can be used as an index
1088: or if it is a pseudo reg. */
1089: #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1090: /* Nonzero if X is a hard reg that can be used as a base reg
1091: or if it is a pseudo reg. */
1092: #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1093:
1094: #define EXTRA_CONSTRAINT(OP, C) \
1.1.1.3 root 1095: ((C) == 'Q' \
1096: ? ((GET_CODE (OP) == MEM \
1097: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1098: && ! symbolic_memory_operand (OP, VOIDmode)) \
1099: || (reload_in_progress && GET_CODE (OP) == REG \
1100: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1101: : (C) == 'R' \
1102: ? (GET_CODE (OP) == LO_SUM \
1103: && GET_CODE (XEXP (OP, 0)) == REG \
1104: && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1105: : (C) == 'S' \
1106: ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1.1.1.4 ! root 1107: : (C) == 'T' \
! 1108: ? (mem_aligned_8 (OP)) \
! 1109: : (C) == 'U' \
! 1110: ? (register_ok_for_ldd (OP)) \
1.1.1.3 root 1111: : 0)
1.1.1.4 ! root 1112:
1.1 root 1113: #else
1114:
1115: /* Nonzero if X is a hard reg that can be used as an index. */
1116: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1117: /* Nonzero if X is a hard reg that can be used as a base reg. */
1118: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1119:
1120: #define EXTRA_CONSTRAINT(OP, C) \
1121: ((C) == 'Q' ? \
1122: (GET_CODE (OP) == REG ? \
1123: (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1124: && reg_renumber[REGNO (OP)] < 0) \
1125: : GET_CODE (OP) == MEM) \
1126: : ((C) == 'R' ? \
1127: (GET_CODE (OP) == LO_SUM \
1128: && GET_CODE (XEXP (OP, 0)) == REG \
1129: && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1130: : ((C) == 'S' \
1131: ? (CONSTANT_P (OP) \
1132: || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1.1.1.4 ! root 1133: || strict_memory_address_p (Pmode, OP)) \
! 1134: : ((C) == 'T' ? \
! 1135: mem_aligned_8 (OP) && strict_memory_address_p (Pmode, OP) \
! 1136: : ((C) == 'U' ? \
! 1137: register_ok_for_ldd (OP) : 0)))))
1.1 root 1138: #endif
1139:
1140: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1141: that is a valid memory address for an instruction.
1142: The MODE argument is the machine mode for the MEM expression
1143: that wants to use this address.
1144:
1145: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1146: ordinarily. This changes a bit when generating PIC.
1147:
1148: If you change this, execute "rm explow.o recog.o reload.o". */
1149:
1.1.1.3 root 1150: #define RTX_OK_FOR_BASE_P(X) \
1151: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1152: || (GET_CODE (X) == SUBREG \
1153: && GET_CODE (SUBREG_REG (X)) == REG \
1154: && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1155:
1156: #define RTX_OK_FOR_INDEX_P(X) \
1157: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1158: || (GET_CODE (X) == SUBREG \
1159: && GET_CODE (SUBREG_REG (X)) == REG \
1160: && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1161:
1162: #define RTX_OK_FOR_OFFSET_P(X) \
1163: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1164:
1.1 root 1165: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1.1.1.3 root 1166: { if (RTX_OK_FOR_BASE_P (X)) \
1167: goto ADDR; \
1.1 root 1168: else if (GET_CODE (X) == PLUS) \
1169: { \
1.1.1.3 root 1170: register rtx op0 = XEXP (X, 0); \
1171: register rtx op1 = XEXP (X, 1); \
1172: if (flag_pic && op0 == pic_offset_table_rtx) \
1.1 root 1173: { \
1.1.1.3 root 1174: if (RTX_OK_FOR_BASE_P (op1)) \
1.1 root 1175: goto ADDR; \
1176: else if (flag_pic == 1 \
1.1.1.3 root 1177: && GET_CODE (op1) != REG \
1178: && GET_CODE (op1) != LO_SUM \
1179: && GET_CODE (op1) != MEM) \
1.1 root 1180: goto ADDR; \
1181: } \
1.1.1.3 root 1182: else if (RTX_OK_FOR_BASE_P (op0)) \
1.1 root 1183: { \
1.1.1.3 root 1184: if (RTX_OK_FOR_INDEX_P (op1) \
1185: || RTX_OK_FOR_OFFSET_P (op1)) \
1.1 root 1186: goto ADDR; \
1187: } \
1.1.1.3 root 1188: else if (RTX_OK_FOR_BASE_P (op1)) \
1.1 root 1189: { \
1.1.1.3 root 1190: if (RTX_OK_FOR_INDEX_P (op0) \
1191: || RTX_OK_FOR_OFFSET_P (op0)) \
1.1 root 1192: goto ADDR; \
1193: } \
1194: } \
1.1.1.3 root 1195: else if (GET_CODE (X) == LO_SUM) \
1196: { \
1197: register rtx op0 = XEXP (X, 0); \
1198: register rtx op1 = XEXP (X, 1); \
1199: if (RTX_OK_FOR_BASE_P (op0) \
1200: && CONSTANT_P (op1)) \
1201: goto ADDR; \
1202: } \
1.1 root 1203: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1204: goto ADDR; \
1205: }
1206:
1207: /* Try machine-dependent ways of modifying an illegitimate address
1208: to be legitimate. If we find one, return the new, valid address.
1209: This macro is used in only one place: `memory_address' in explow.c.
1210:
1211: OLDX is the address as it was before break_out_memory_refs was called.
1212: In some cases it is useful to look at this to decide what needs to be done.
1213:
1214: MODE and WIN are passed so that this macro can use
1215: GO_IF_LEGITIMATE_ADDRESS.
1216:
1217: It is always safe for this macro to do nothing. It exists to recognize
1218: opportunities to optimize the output. */
1219:
1220: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1221: extern struct rtx_def *legitimize_pic_address ();
1222: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1223: { rtx sparc_x = (X); \
1224: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1225: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1226: force_operand (XEXP (X, 0), 0)); \
1227: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1228: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1229: force_operand (XEXP (X, 1), 0)); \
1230: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1231: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1232: XEXP (X, 1)); \
1233: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1234: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1235: force_operand (XEXP (X, 1), 0)); \
1236: if (sparc_x != (X) && memory_address_p (MODE, X)) \
1237: goto WIN; \
1238: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1239: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1240: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1241: copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1242: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1243: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1244: copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1245: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1246: || GET_CODE (X) == LABEL_REF) \
1247: (X) = gen_rtx (LO_SUM, Pmode, \
1248: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1249: if (memory_address_p (MODE, X)) \
1250: goto WIN; }
1251:
1252: /* Go to LABEL if ADDR (a legitimate address expression)
1253: has an effect that depends on the machine mode it is used for.
1254: On the SPARC this is never true. */
1255:
1256: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1257:
1258: /* Specify the machine mode that this machine uses
1259: for the index in the tablejump instruction. */
1260: #define CASE_VECTOR_MODE SImode
1261:
1262: /* Define this if the tablejump instruction expects the table
1263: to contain offsets from the address of the table.
1264: Do not define this if the table should contain absolute addresses. */
1265: /* #define CASE_VECTOR_PC_RELATIVE */
1266:
1267: /* Specify the tree operation to be used to convert reals to integers. */
1268: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1269:
1270: /* This is the kind of divide that is easiest to do in the general case. */
1271: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1272:
1273: /* Define this as 1 if `char' should by default be signed; else as 0. */
1274: #define DEFAULT_SIGNED_CHAR 1
1275:
1276: /* Max number of bytes we can move from memory to memory
1277: in one reasonably fast instruction. */
1.1.1.3 root 1278: #define MOVE_MAX 8
1.1 root 1279:
1.1.1.4 ! root 1280: #if 0 /* Sun 4 has matherr, so this is no good. */
! 1281: /* This is the value of the error code EDOM for this machine,
! 1282: used by the sqrt instruction. */
! 1283: #define TARGET_EDOM 33
! 1284:
! 1285: /* This is how to refer to the variable errno. */
! 1286: #define GEN_ERRNO_RTX \
! 1287: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
! 1288: #endif /* 0 */
! 1289:
1.1 root 1290: /* Define if normal loads of shorter-than-word items from memory clears
1291: the rest of the bigs in the register. */
1292: #define BYTE_LOADS_ZERO_EXTEND
1293:
1294: /* Nonzero if access to memory by bytes is slow and undesirable.
1295: For RISC chips, it means that access to memory by bytes is no
1296: better than access by words when possible, so grab a whole word
1297: and maybe make use of that. */
1298: #define SLOW_BYTE_ACCESS 1
1299:
1300: /* We assume that the store-condition-codes instructions store 0 for false
1301: and some other value for true. This is the value stored for true. */
1302:
1303: #define STORE_FLAG_VALUE 1
1304:
1305: /* When a prototype says `char' or `short', really pass an `int'. */
1306: #define PROMOTE_PROTOTYPES
1307:
1308: /* Define if shifts truncate the shift count
1309: which implies one can omit a sign-extension or zero-extension
1310: of a shift count. */
1311: #define SHIFT_COUNT_TRUNCATED
1312:
1313: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1314: is done just by pretending it is already truncated. */
1315: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1316:
1317: /* Specify the machine mode that pointers have.
1318: After generation of rtl, the compiler makes no further distinction
1319: between pointers and any other objects of this machine mode. */
1320: #define Pmode SImode
1321:
1.1.1.2 root 1322: /* Generate calls to memcpy, memcmp and memset. */
1323: #define TARGET_MEM_FUNCTIONS
1324:
1.1 root 1325: /* Add any extra modes needed to represent the condition code.
1326:
1327: On the Sparc, we have a "no-overflow" mode which is used when an add or
1328: subtract insn is used to set the condition code. Different branches are
1329: used in this case for some operations.
1330:
1.1.1.3 root 1331: We also have two modes to indicate that the relevant condition code is
1332: in the floating-point condition code register. One for comparisons which
1333: will generate an exception if the result is unordered (CCFPEmode) and
1334: one for comparisons which will never trap (CCFPmode). This really should
1335: be a separate register, but we don't want to go to 65 registers. */
1336: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1.1 root 1337:
1338: /* Define the names for the modes specified above. */
1.1.1.3 root 1339: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1.1 root 1340:
1341: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1.1.1.3 root 1342: return the mode to be used for the comparison. For floating-point,
1343: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1.1 root 1344: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1345: needed. */
1.1.1.4 ! root 1346: #define SELECT_CC_MODE(OP,X,Y) \
1.1.1.3 root 1347: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1348: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1349: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1350: ? CC_NOOVmode : CCmode))
1.1 root 1351:
1352: /* A function address in a call instruction
1353: is a byte address (for indexing purposes)
1354: so give the MEM rtx a byte's mode. */
1355: #define FUNCTION_MODE SImode
1356:
1357: /* Define this if addresses of constant functions
1358: shouldn't be put through pseudo regs where they can be cse'd.
1359: Desirable on machines where ordinary constants are expensive
1360: but a CALL with constant address is cheap. */
1361: #define NO_FUNCTION_CSE
1362:
1363: /* alloca should avoid clobbering the old register save area. */
1364: #define SETJMP_VIA_SAVE_AREA
1365:
1366: /* Define subroutines to call to handle multiply and divide.
1367: Use the subroutines that Sun's library provides.
1368: The `*' prevents an underscore from being prepended by the compiler. */
1369:
1370: #define DIVSI3_LIBCALL "*.div"
1371: #define UDIVSI3_LIBCALL "*.udiv"
1372: #define MODSI3_LIBCALL "*.rem"
1373: #define UMODSI3_LIBCALL "*.urem"
1374: /* .umul is a little faster than .mul. */
1375: #define MULSI3_LIBCALL "*.umul"
1376:
1377: /* Compute the cost of computing a constant rtl expression RTX
1378: whose rtx-code is CODE. The body of this macro is a portion
1379: of a switch statement. If the code is computed here,
1380: return it with a return statement. Otherwise, break from the switch. */
1381:
1.1.1.3 root 1382: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1.1 root 1383: case CONST_INT: \
1384: if (INTVAL (RTX) == 0) \
1385: return 0; \
1386: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1387: return 1; \
1388: case HIGH: \
1389: return 2; \
1390: case CONST: \
1391: case LABEL_REF: \
1392: case SYMBOL_REF: \
1393: return 4; \
1394: case CONST_DOUBLE: \
1395: if (GET_MODE (RTX) == DImode) \
1396: if ((XINT (RTX, 3) == 0 \
1397: && (unsigned) XINT (RTX, 2) < 0x1000) \
1398: || (XINT (RTX, 3) == -1 \
1399: && XINT (RTX, 2) < 0 \
1400: && XINT (RTX, 2) >= -0x1000)) \
1401: return 1; \
1402: return 8;
1403:
1404: /* SPARC offers addressing modes which are "as cheap as a register".
1405: See sparc.c (or gcc.texinfo) for details. */
1406:
1407: #define ADDRESS_COST(RTX) \
1408: (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1409:
1410: /* Compute extra cost of moving data between one register class
1411: and another. */
1412: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1413: (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1414: || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1415:
1416: /* Provide the costs of a rtl expression. This is in the body of a
1417: switch on CODE. The purpose for the cost of MULT is to encourage
1418: `synth_mult' to find a synthetic multiply when reasonable.
1419:
1420: If we need more than 12 insns to do a multiply, then go out-of-line,
1421: since the call overhead will be < 10% of the cost of the multiply. */
1422:
1.1.1.3 root 1423: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1.1 root 1424: case MULT: \
1425: return COSTS_N_INSNS (25); \
1426: case DIV: \
1427: case UDIV: \
1428: case MOD: \
1429: case UMOD: \
1430: return COSTS_N_INSNS (20); \
1431: /* Make FLOAT more expensive than CONST_DOUBLE, \
1432: so that cse will favor the latter. */ \
1433: case FLOAT: \
1434: return 19;
1435:
1436: /* Conditional branches with empty delay slots have a length of two. */
1437: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1438: if (GET_CODE (INSN) == CALL_INSN \
1439: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1440: LENGTH += 1;
1441:
1442: /* Control the assembler format that we output. */
1443:
1444: /* Output at beginning of assembler file. */
1445:
1446: #define ASM_FILE_START(file)
1447:
1448: /* Output to assembler file text saying following lines
1449: may contain character constants, extra white space, comments, etc. */
1450:
1451: #define ASM_APP_ON ""
1452:
1453: /* Output to assembler file text saying following lines
1454: no longer contain unusual constructs. */
1455:
1456: #define ASM_APP_OFF ""
1457:
1.1.1.4 ! root 1458: #define ASM_LONG ".word"
! 1459: #define ASM_SHORT ".half"
! 1460: #define ASM_BYTE_OP ".byte"
! 1461:
1.1 root 1462: /* Output before read-only data. */
1463:
1464: #define TEXT_SECTION_ASM_OP ".text"
1465:
1466: /* Output before writable data. */
1467:
1468: #define DATA_SECTION_ASM_OP ".data"
1469:
1470: /* How to refer to registers in assembler output.
1471: This sequence is indexed by compiler's hard-register-number (see above). */
1472:
1473: #define REGISTER_NAMES \
1474: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1475: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1476: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1477: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1478: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1479: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1480: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1481: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1482:
1.1.1.3 root 1483: /* Define additional names for use in asm clobbers and asm declarations.
1484:
1485: We define the fake Condition Code register as an alias for reg 0 (which
1486: is our `condition code' register), so that condition codes can easily
1487: be clobbered by an asm. No such register actually exists. Condition
1488: codes are partly stored in the PSR and partly in the FSR. */
1489:
1490: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1491:
1.1 root 1492: /* How to renumber registers for dbx and gdb. */
1493:
1494: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1495:
1496: /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1497: since the length can run past this up to a continuation point. */
1498: #define DBX_CONTIN_LENGTH 1500
1499:
1500: /* This is how to output a note to DBX telling it the line number
1501: to which the following sequence of instructions corresponds.
1502:
1503: This is needed for SunOS 4.0, and should not hurt for 3.2
1504: versions either. */
1505: #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1506: { static int sym_lineno = 1; \
1507: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1508: line, sym_lineno, sym_lineno); \
1509: sym_lineno += 1; }
1510:
1511: /* This is how to output the definition of a user-level label named NAME,
1512: such as the label on a static function or variable NAME. */
1513:
1514: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1515: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1516:
1517: /* This is how to output a command to make the user-level label named NAME
1518: defined for reference from other files. */
1519:
1520: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1521: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1522:
1523: /* This is how to output a reference to a user-level label named NAME.
1524: `assemble_name' uses this. */
1525:
1526: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1527: fprintf (FILE, "_%s", NAME)
1528:
1.1.1.4 ! root 1529: /* This is how to output a definition of an internal numbered label where
1.1 root 1530: PREFIX is the class of label and NUM is the number within the class. */
1531:
1532: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1533: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1534:
1.1.1.4 ! root 1535: /* This is how to output a reference to an internal numbered label where
! 1536: PREFIX is the class of label and NUM is the number within the class. */
! 1537: /* FIXME: This should be used throughout gcc, and documented in the texinfo
! 1538: files. There is no reason you should have to allocate a buffer and
! 1539: `sprintf' to reference an internal label (as opposed to defining it). */
! 1540:
! 1541: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
! 1542: fprintf (FILE, "%s%d", PREFIX, NUM)
! 1543:
1.1 root 1544: /* This is how to store into the string LABEL
1545: the symbol_ref name of an internal numbered label where
1546: PREFIX is the class of label and NUM is the number within the class.
1547: This is suitable for output with `assemble_name'. */
1548:
1549: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1550: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1551:
1552: /* This is how to output an assembler line defining a `double' constant. */
1553:
1.1.1.2 root 1554: /* Assemblers (both gas 1.35 and as in 4.0.3)
1555: seem to treat -0.0 as if it were 0.0.
1556: They reject 99e9999, but accept inf. */
1.1 root 1557: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1558: { \
1.1.1.4 ! root 1559: if (REAL_VALUE_ISINF (VALUE) \
! 1560: || REAL_VALUE_ISNAN (VALUE) \
! 1561: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1.1 root 1562: { \
1.1.1.4 ! root 1563: long t[2]; \
! 1564: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
! 1565: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
! 1566: ASM_LONG, t[0], ASM_LONG, t[1]); \
1.1 root 1567: } \
1568: else \
1569: fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1570: }
1571:
1572: /* This is how to output an assembler line defining a `float' constant. */
1573:
1574: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1575: { \
1.1.1.4 ! root 1576: if (REAL_VALUE_ISINF (VALUE) \
! 1577: || REAL_VALUE_ISNAN (VALUE) \
! 1578: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1.1 root 1579: { \
1.1.1.4 ! root 1580: long t; \
! 1581: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
! 1582: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1.1 root 1583: } \
1584: else \
1585: fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1586: }
1587:
1588: /* This is how to output an assembler line defining an `int' constant. */
1589:
1590: #define ASM_OUTPUT_INT(FILE,VALUE) \
1.1.1.4 ! root 1591: ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1.1 root 1592: output_addr_const (FILE, (VALUE)), \
1593: fprintf (FILE, "\n"))
1594:
1595: /* This is how to output an assembler line defining a DImode constant. */
1596: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1597: output_double_int (FILE, VALUE)
1598:
1599: /* Likewise for `char' and `short' constants. */
1600:
1601: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1.1.1.4 ! root 1602: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1.1 root 1603: output_addr_const (FILE, (VALUE)), \
1604: fprintf (FILE, "\n"))
1605:
1606: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1.1.1.4 ! root 1607: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1.1 root 1608: output_addr_const (FILE, (VALUE)), \
1609: fprintf (FILE, "\n"))
1610:
1611: /* This is how to output an assembler line for a numeric constant byte. */
1612:
1613: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1.1.1.4 ! root 1614: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1.1 root 1615:
1616: /* This is how to output an element of a case-vector that is absolute. */
1617:
1618: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1.1.1.3 root 1619: do { \
1620: char label[30]; \
1621: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1622: fprintf (FILE, "\t.word\t"); \
1623: assemble_name (FILE, label); \
1624: fprintf (FILE, "\n"); \
1625: } while (0)
1.1 root 1626:
1627: /* This is how to output an element of a case-vector that is relative.
1628: (SPARC uses such vectors only when generating PIC.) */
1629:
1.1.1.3 root 1630: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1631: do { \
1632: char label[30]; \
1633: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1634: fprintf (FILE, "\t.word\t"); \
1635: assemble_name (FILE, label); \
1636: fprintf (FILE, "-1b\n"); \
1637: } while (0)
1.1 root 1638:
1639: /* This is how to output an assembler line
1640: that says to advance the location counter
1641: to a multiple of 2**LOG bytes. */
1642:
1643: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1644: if ((LOG) != 0) \
1645: fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1646:
1647: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1648: fprintf (FILE, "\t.skip %u\n", (SIZE))
1649:
1650: /* This says how to output an assembler line
1651: to define a global common symbol. */
1652:
1653: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1654: ( fputs ("\t.global ", (FILE)), \
1655: assemble_name ((FILE), (NAME)), \
1656: fputs ("\n\t.common ", (FILE)), \
1657: assemble_name ((FILE), (NAME)), \
1658: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1659:
1660: /* This says how to output an assembler line
1661: to define a local common symbol. */
1662:
1663: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1664: ( fputs ("\n\t.reserve ", (FILE)), \
1665: assemble_name ((FILE), (NAME)), \
1666: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1667:
1668: /* Store in OUTPUT a string (made with alloca) containing
1669: an assembler-name for a local static variable named NAME.
1670: LABELNO is an integer which is different for each call. */
1671:
1672: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1673: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1674: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1675:
1676: /* Define the parentheses used to group arithmetic operations
1677: in assembler code. */
1678:
1679: #define ASM_OPEN_PAREN "("
1680: #define ASM_CLOSE_PAREN ")"
1681:
1682: /* Define results of standard character escape sequences. */
1683: #define TARGET_BELL 007
1684: #define TARGET_BS 010
1685: #define TARGET_TAB 011
1686: #define TARGET_NEWLINE 012
1687: #define TARGET_VT 013
1688: #define TARGET_FF 014
1689: #define TARGET_CR 015
1690:
1691: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1.1.1.4 ! root 1692: ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
! 1693: || (CHAR) == '(')
1.1 root 1694:
1695: /* Print operand X (an rtx) in assembler syntax to file FILE.
1696: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1697: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1698:
1699: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1700:
1701: /* Print a memory address as an operand to reference that memory location. */
1702:
1703: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1704: { register rtx base, index = 0; \
1705: int offset = 0; \
1706: register rtx addr = ADDR; \
1707: if (GET_CODE (addr) == REG) \
1708: fputs (reg_names[REGNO (addr)], FILE); \
1709: else if (GET_CODE (addr) == PLUS) \
1710: { \
1711: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1712: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1713: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1714: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1715: else \
1716: base = XEXP (addr, 0), index = XEXP (addr, 1); \
1717: fputs (reg_names[REGNO (base)], FILE); \
1718: if (index == 0) \
1719: fprintf (FILE, "%+d", offset); \
1720: else if (GET_CODE (index) == REG) \
1721: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1722: else if (GET_CODE (index) == SYMBOL_REF) \
1723: fputc ('+', FILE), output_addr_const (FILE, index); \
1724: else abort (); \
1725: } \
1726: else if (GET_CODE (addr) == MINUS \
1727: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1728: { \
1729: output_addr_const (FILE, XEXP (addr, 0)); \
1730: fputs ("-(", FILE); \
1731: output_addr_const (FILE, XEXP (addr, 1)); \
1732: fputs ("-.)", FILE); \
1733: } \
1734: else if (GET_CODE (addr) == LO_SUM) \
1735: { \
1736: output_operand (XEXP (addr, 0), 0); \
1737: fputs ("+%lo(", FILE); \
1738: output_address (XEXP (addr, 1)); \
1739: fputc (')', FILE); \
1740: } \
1741: else if (flag_pic && GET_CODE (addr) == CONST \
1742: && GET_CODE (XEXP (addr, 0)) == MINUS \
1743: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1744: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1745: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1746: { \
1747: addr = XEXP (addr, 0); \
1748: output_addr_const (FILE, XEXP (addr, 0)); \
1749: /* Group the args of the second CONST in parenthesis. */ \
1750: fputs ("-(", FILE); \
1751: /* Skip past the second CONST--it does nothing for us. */\
1752: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1753: /* Close the parenthesis. */ \
1754: fputc (')', FILE); \
1755: } \
1756: else \
1757: { \
1758: output_addr_const (FILE, addr); \
1759: } \
1760: }
1761:
1762: /* Declare functions defined in sparc.c and used in templates. */
1763:
1764: extern char *singlemove_string ();
1765: extern char *output_move_double ();
1.1.1.3 root 1766: extern char *output_move_quad ();
1.1 root 1767: extern char *output_fp_move_double ();
1.1.1.3 root 1768: extern char *output_fp_move_quad ();
1.1 root 1769: extern char *output_block_move ();
1770: extern char *output_scc_insn ();
1771: extern char *output_cbranch ();
1772: extern char *output_return ();
1773:
1774: /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1775:
1776: extern int flag_pic;
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