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1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3: Contributed by Michael Tiemann ([email protected]).
4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21: /* Note that some other tm.h files include this one and then override
22: many of the definitions that relate to assembler syntax. */
23:
24: #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \
25: %{a:/usr/lib/bb_link.o}"
26:
27: /* Provide required defaults for linker -e and -d switches. */
28:
29: #define LINK_SPEC \
30: "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
31:
32: /* Special flags to the Sun-4 assembler when using pipe for input. */
33:
34: #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}"
35:
36: /* Define macros to distinguish architectures. */
37: #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
38:
39: /* Prevent error on `-sun4' and `-target sun4' options. */
40: /* This used to translate -dalign to -malign, but that is no good
41: because it can't turn off the usual meaning of making debugging dumps. */
42:
43: #define CC1_SPEC "%{sun4:} %{target:}"
44:
45: #if 0
46: /* ??? This fails because REAL_VALUE_TYPE is `double' making it impossible to
47: represent and output `long double' constants. This causes problems during
48: a bootstrap with enquire/float.h, and hence must be disabled for now.
49: To fix, we need to implement code for TFmode just like the existing XFmode
50: support in real.[ch]. */
51: /* Sparc ABI says that long double is 4 words. */
52:
53: #define LONG_DOUBLE_TYPE_SIZE 128
54: #endif
55:
56: #define PTRDIFF_TYPE "int"
57: /* In 2.4 it should work to delete this.
58: #define SIZE_TYPE "int" */
59: #define WCHAR_TYPE "short unsigned int"
60: #define WCHAR_TYPE_SIZE 16
61:
62: /* Omit frame pointer at high optimization levels. */
63:
64: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
65: { \
66: if (OPTIMIZE >= 2) \
67: { \
68: flag_omit_frame_pointer = 1; \
69: } \
70: }
71:
72: /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
73: code into the rtl. Also, if we are profiling, we cannot eliminate
74: the frame pointer (because the return address will get smashed). */
75:
76: #define OVERRIDE_OPTIONS \
77: do { if (profile_flag || profile_block_flag) \
78: flag_omit_frame_pointer = 0, flag_pic = 0; } while (0)
79:
80: /* These compiler options take an argument. We ignore -target for now. */
81:
82: #define WORD_SWITCH_TAKES_ARG(STR) \
83: (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
84: || !strcmp (STR, "target") || !strcmp (STR, "assert"))
85:
86: /* Names to predefine in the preprocessor for this target machine. */
87:
88: /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile
89: new versions, which have an incompatible va-sparc.h file. This matters
90: because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the
91: wrong varargs file when it is compiled with a different version of gcc. */
92:
93: #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__"
94:
95: /* Print subsidiary information on the compiler version in use. */
96:
97: #define TARGET_VERSION fprintf (stderr, " (sparc)");
98:
99: /* Generate DBX debugging information. */
100:
101: #define DBX_DEBUGGING_INFO
102:
103: /* Run-time compilation parameters selecting different hardware subsets. */
104:
105: extern int target_flags;
106:
107: /* Nonzero if we should generate code to use the fpu. */
108: #define TARGET_FPU (target_flags & 1)
109:
110: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
111: use fast return insns, but lose some generality. */
112: #define TARGET_EPILOGUE (target_flags & 2)
113:
114: /* Nonzero if we should assume that double pointers might be unaligned.
115: This can happen when linking gcc compiled code with other compilers,
116: because the ABI only guarantees 4 byte alignment. */
117: #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
118:
119: /* Nonzero means that we should generate code for a v8 sparc. */
120: #define TARGET_V8 (target_flags & 64)
121:
122: /* Nonzero means that we should generate code for a sparclite. */
123: #define TARGET_SPARCLITE (target_flags & 128)
124:
125: /* Nonzero means that we should generate code using a flat register window
126: model, i.e. no save/restore instructions are generated, in the most
127: efficient manner. This code is not compatible with normal sparc code. */
128: /* This is not a user selectable option yet, because it requires changes
129: that are not yet switchable via command line arguments. */
130: #define TARGET_FRW (target_flags & 256)
131:
132: /* Nonzero means that we should generate code using a flat register window
133: model, i.e. no save/restore instructions are generated, but which is
134: compatible with normal sparc code. This is the same as above, except
135: that the frame pointer is %l6 instead of %fp. This code is not as efficient
136: as TARGET_FRW, because it has one less allocatable register. */
137: /* This is not a user selectable option yet, because it requires changes
138: that are not yet switchable via command line arguments. */
139: #define TARGET_FRW_COMPAT (target_flags & 512)
140:
141: /* Macro to define tables used to set the flags.
142: This is a list in braces of pairs in braces,
143: each pair being { "NAME", VALUE }
144: where VALUE is the bits to set or minus the bits to clear.
145: An empty string NAME is used to identify the default VALUE. */
146:
147: #define TARGET_SWITCHES \
148: { {"fpu", 1}, \
149: {"no-fpu", -1}, \
150: {"hard-float", 1}, \
151: {"soft-float", -1}, \
152: {"epilogue", 2}, \
153: {"no-epilogue", -2}, \
154: {"unaligned-doubles", 4}, \
155: {"no-unaligned-doubles", -4},\
156: {"v8", 64}, \
157: {"no-v8", -64}, \
158: {"sparclite", 128}, \
159: {"sparclite", -1}, \
160: {"no-sparclite", -128}, \
161: {"no-sparclite", 1}, \
162: /* {"frw", 256}, */ \
163: /* {"no-frw", -256}, */ \
164: /* {"frw-compat", 256+512}, */ \
165: /* {"no-frw-compat", -(256+512)}, */ \
166: { "", TARGET_DEFAULT}}
167:
168: #define TARGET_DEFAULT 3
169:
170: /* target machine storage layout */
171:
172: /* Define this if most significant bit is lowest numbered
173: in instructions that operate on numbered bit-fields. */
174: #define BITS_BIG_ENDIAN 1
175:
176: /* Define this if most significant byte of a word is the lowest numbered. */
177: /* This is true on the SPARC. */
178: #define BYTES_BIG_ENDIAN 1
179:
180: /* Define this if most significant word of a multiword number is the lowest
181: numbered. */
182: /* Doubles are stored in memory with the high order word first. This
183: matters when cross-compiling. */
184: #define WORDS_BIG_ENDIAN 1
185:
186: /* number of bits in an addressable storage unit */
187: #define BITS_PER_UNIT 8
188:
189: /* Width in bits of a "word", which is the contents of a machine register.
190: Note that this is not necessarily the width of data type `int';
191: if using 16-bit ints on a 68000, this would still be 32.
192: But on a machine with 16-bit registers, this would be 16. */
193: #define BITS_PER_WORD 32
194: #define MAX_BITS_PER_WORD 32
195:
196: /* Width of a word, in units (bytes). */
197: #define UNITS_PER_WORD 4
198:
199: /* Width in bits of a pointer.
200: See also the macro `Pmode' defined below. */
201: #define POINTER_SIZE 32
202:
203: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
204: #define PARM_BOUNDARY 32
205:
206: /* Boundary (in *bits*) on which stack pointer should be aligned. */
207: #define STACK_BOUNDARY 64
208:
209: /* ALIGN FRAMES on double word boundaries */
210:
211: #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
212:
213: /* Allocation boundary (in *bits*) for the code of a function. */
214: #define FUNCTION_BOUNDARY 32
215:
216: /* Alignment of field after `int : 0' in a structure. */
217: #define EMPTY_FIELD_BOUNDARY 32
218:
219: /* Every structure's size must be a multiple of this. */
220: #define STRUCTURE_SIZE_BOUNDARY 8
221:
222: /* A bitfield declared as `int' forces `int' alignment for the struct. */
223: #define PCC_BITFIELD_TYPE_MATTERS 1
224:
225: /* No data type wants to be aligned rounder than this. */
226: #define BIGGEST_ALIGNMENT 64
227:
228: /* The best alignment to use in cases where we have a choice. */
229: #define FASTEST_ALIGNMENT 64
230:
231: /* Make strings word-aligned so strcpy from constants will be faster. */
232: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
233: ((TREE_CODE (EXP) == STRING_CST \
234: && (ALIGN) < FASTEST_ALIGNMENT) \
235: ? FASTEST_ALIGNMENT : (ALIGN))
236:
237: /* Make arrays of chars word-aligned for the same reasons. */
238: #define DATA_ALIGNMENT(TYPE, ALIGN) \
239: (TREE_CODE (TYPE) == ARRAY_TYPE \
240: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
241: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
242:
243: /* Set this nonzero if move instructions will actually fail to work
244: when given unaligned data. */
245: #define STRICT_ALIGNMENT 1
246:
247: /* Things that must be doubleword aligned cannot go in the text section,
248: because the linker fails to align the text section enough!
249: Put them in the data section. */
250: #define MAX_TEXT_ALIGN 32
251:
252: #define SELECT_SECTION(T,RELOC) \
253: { \
254: if (TREE_CODE (T) == VAR_DECL) \
255: { \
256: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
257: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
258: && ! (flag_pic && (RELOC))) \
259: text_section (); \
260: else \
261: data_section (); \
262: } \
263: else if (TREE_CODE (T) == CONSTRUCTOR) \
264: { \
265: if (flag_pic != 0 && (RELOC) != 0) \
266: data_section (); \
267: } \
268: else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
269: { \
270: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
271: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
272: data_section (); \
273: else \
274: text_section (); \
275: } \
276: }
277:
278: /* Use text section for a constant
279: unless we need more alignment than that offers. */
280: #define SELECT_RTX_SECTION(MODE, X) \
281: { \
282: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
283: && ! (flag_pic && symbolic_operand (X))) \
284: text_section (); \
285: else \
286: data_section (); \
287: }
288:
289: /* Standard register usage. */
290:
291: /* Number of actual hardware registers.
292: The hardware registers are assigned numbers for the compiler
293: from 0 to just below FIRST_PSEUDO_REGISTER.
294: All registers that the compiler knows about must be given numbers,
295: even those that are not normally considered general registers.
296:
297: SPARC has 32 integer registers and 32 floating point registers. */
298:
299: #define FIRST_PSEUDO_REGISTER 64
300:
301: /* 1 for registers that have pervasive standard uses
302: and are not available for the register allocator.
303: g0 is used for the condition code and not to represent %g0, which is
304: hardwired to 0, so reg 0 is *not* fixed.
305: g1 through g4 are free to use as temporaries.
306: g5 through g7 are reserved for the operating system. */
307: #define FIXED_REGISTERS \
308: {0, 0, 0, 0, 0, 1, 1, 1, \
309: 0, 0, 0, 0, 0, 0, 1, 0, \
310: 0, 0, 0, 0, 0, 0, 0, 0, \
311: 0, 0, 0, 0, 0, 0, 1, 1, \
312: \
313: 0, 0, 0, 0, 0, 0, 0, 0, \
314: 0, 0, 0, 0, 0, 0, 0, 0, \
315: 0, 0, 0, 0, 0, 0, 0, 0, \
316: 0, 0, 0, 0, 0, 0, 0, 0}
317:
318: /* 1 for registers not available across function calls.
319: These must include the FIXED_REGISTERS and also any
320: registers that can be used without being saved.
321: The latter must include the registers where values are returned
322: and the register where structure-value addresses are passed.
323: Aside from that, you can include as many other registers as you like. */
324: #define CALL_USED_REGISTERS \
325: {1, 1, 1, 1, 1, 1, 1, 1, \
326: 1, 1, 1, 1, 1, 1, 1, 1, \
327: 0, 0, 0, 0, 0, 0, 0, 0, \
328: 0, 0, 0, 0, 0, 0, 1, 1, \
329: \
330: 1, 1, 1, 1, 1, 1, 1, 1, \
331: 1, 1, 1, 1, 1, 1, 1, 1, \
332: 1, 1, 1, 1, 1, 1, 1, 1, \
333: 1, 1, 1, 1, 1, 1, 1, 1}
334:
335: /* If !TARGET_FPU, then make the fp registers fixed so that they won't
336: be allocated. */
337:
338: #define CONDITIONAL_REGISTER_USAGE \
339: do \
340: { \
341: if (! TARGET_FPU) \
342: { \
343: int regno; \
344: for (regno = 32; regno < 64; regno++) \
345: fixed_regs[regno] = 1; \
346: } \
347: } \
348: while (0)
349:
350: /* Return number of consecutive hard regs needed starting at reg REGNO
351: to hold something of mode MODE.
352: This is ordinarily the length in words of a value of mode MODE
353: but can be less for certain modes in special long registers.
354:
355: On SPARC, ordinary registers hold 32 bits worth;
356: this means both integer and floating point registers.
357:
358: We use vectors to keep this information about registers. */
359:
360: /* How many hard registers it takes to make a register of this mode. */
361: extern int hard_regno_nregs[];
362:
363: #define HARD_REGNO_NREGS(REGNO, MODE) \
364: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
365:
366: /* Value is 1 if register/mode pair is acceptable on sparc. */
367: extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
368:
369: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
370: On SPARC, the cpu registers can hold any mode but the float registers
371: can only hold SFmode or DFmode. See sparc.c for how we
372: initialize this. */
373: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
374: ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
375:
376: /* Value is 1 if it is a good idea to tie two pseudo registers
377: when one has mode MODE1 and one has mode MODE2.
378: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
379: for any hard reg, then this must be 0 for correct output. */
380: #define MODES_TIEABLE_P(MODE1, MODE2) \
381: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
382:
383: /* Specify the registers used for certain standard purposes.
384: The values of these macros are register numbers. */
385:
386: /* SPARC pc isn't overloaded on a register that the compiler knows about. */
387: /* #define PC_REGNUM */
388:
389: /* Register to use for pushing function arguments. */
390: #define STACK_POINTER_REGNUM 14
391:
392: /* Actual top-of-stack address is 92 greater than the contents
393: of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
394: for the ins and local registers, 4 byte for structure return address, and
395: 24 bytes for the 6 register parameters. */
396: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
397:
398: /* Base register for access to local variables of the function. */
399: #define FRAME_POINTER_REGNUM 30
400:
401: #if 0
402: /* Register that is used for the return address. */
403: #define RETURN_ADDR_REGNUM 15
404: #endif
405:
406: /* Value should be nonzero if functions must have frame pointers.
407: Zero means the frame pointer need not be set up (and parms
408: may be accessed via the stack pointer) in functions that seem suitable.
409: This is computed in `reload', in reload1.c.
410:
411: Used in flow.c, global.c, and reload1.c. */
412: extern int leaf_function;
413:
414: #define FRAME_POINTER_REQUIRED \
415: (! (leaf_function_p () && only_leaf_regs_used ()))
416:
417: /* C statement to store the difference between the frame pointer
418: and the stack pointer values immediately after the function prologue.
419:
420: Note, we always pretend that this is a leaf function because if
421: it's not, there's no point in trying to eliminate the
422: frame pointer. If it is a leaf function, we guessed right! */
423: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
424: ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \
425: : compute_frame_size (get_frame_size (), 1)))
426:
427: /* Base register for access to arguments of the function. */
428: #define ARG_POINTER_REGNUM 30
429:
430: /* Register in which static-chain is passed to a function. */
431: /* ??? */
432: #define STATIC_CHAIN_REGNUM 1
433:
434: /* Register which holds offset table for position-independent
435: data references. */
436:
437: #define PIC_OFFSET_TABLE_REGNUM 23
438:
439: #define INITIALIZE_PIC initialize_pic ()
440: #define FINALIZE_PIC finalize_pic ()
441:
442: /* Sparc ABI says that quad-precision floats and all structures are returned
443: in memory. */
444: #define RETURN_IN_MEMORY(TYPE) \
445: (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
446:
447: /* Functions which return large structures get the address
448: to place the wanted value at offset 64 from the frame.
449: Must reserve 64 bytes for the in and local registers. */
450: /* Used only in other #defines in this file. */
451: #define STRUCT_VALUE_OFFSET 64
452:
453: #define STRUCT_VALUE \
454: gen_rtx (MEM, Pmode, \
455: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
456: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
457: #define STRUCT_VALUE_INCOMING \
458: gen_rtx (MEM, Pmode, \
459: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
460: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
461:
462: /* Define the classes of registers for register constraints in the
463: machine description. Also define ranges of constants.
464:
465: One of the classes must always be named ALL_REGS and include all hard regs.
466: If there is more than one class, another class must be named NO_REGS
467: and contain no registers.
468:
469: The name GENERAL_REGS must be the name of a class (or an alias for
470: another name such as ALL_REGS). This is the class of registers
471: that is allowed by "g" or "r" in a register constraint.
472: Also, registers outside this class are allocated only when
473: instructions express preferences for them.
474:
475: The classes must be numbered in nondecreasing order; that is,
476: a larger-numbered class must never be contained completely
477: in a smaller-numbered class.
478:
479: For any two classes, it is very desirable that there be another
480: class that represents their union. */
481:
482: /* The SPARC has two kinds of registers, general and floating point. */
483:
484: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
485:
486: #define N_REG_CLASSES (int) LIM_REG_CLASSES
487:
488: /* Give names of register classes as strings for dump file. */
489:
490: #define REG_CLASS_NAMES \
491: {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
492:
493: /* Define which registers fit in which classes.
494: This is an initializer for a vector of HARD_REG_SET
495: of length N_REG_CLASSES. */
496:
497: #if 0 && defined (__GNUC__)
498: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
499: #else
500: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
501: #endif
502:
503: /* The same information, inverted:
504: Return the class number of the smallest class containing
505: reg number REGNO. This could be a conditional expression
506: or could index an array. */
507:
508: #define REGNO_REG_CLASS(REGNO) \
509: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
510:
511: /* This is the order in which to allocate registers
512: normally.
513:
514: We put %f0/%f1 last among the float registers, so as to make it more
515: likely that a pseduo-register which dies in the float return register
516: will get allocated to the float return register, thus saving a move
517: instruction at the end of the function. */
518: #define REG_ALLOC_ORDER \
519: { 8, 9, 10, 11, 12, 13, 2, 3, \
520: 15, 16, 17, 18, 19, 20, 21, 22, \
521: 23, 24, 25, 26, 27, 28, 29, 31, \
522: 34, 35, 36, 37, 38, 39, \
523: 40, 41, 42, 43, 44, 45, 46, 47, \
524: 48, 49, 50, 51, 52, 53, 54, 55, \
525: 56, 57, 58, 59, 60, 61, 62, 63, \
526: 32, 33, \
527: 1, 4, 5, 6, 7, 0, 14, 30}
528:
529: /* This is the order in which to allocate registers for
530: leaf functions. If all registers can fit in the "i" registers,
531: then we have the possibility of having a leaf function. */
532: #define REG_LEAF_ALLOC_ORDER \
533: { 2, 3, 24, 25, 26, 27, 28, 29, \
534: 15, 8, 9, 10, 11, 12, 13, \
535: 16, 17, 18, 19, 20, 21, 22, 23, \
536: 34, 35, 36, 37, 38, 39, \
537: 40, 41, 42, 43, 44, 45, 46, 47, \
538: 48, 49, 50, 51, 52, 53, 54, 55, \
539: 56, 57, 58, 59, 60, 61, 62, 63, \
540: 32, 33, \
541: 1, 4, 5, 6, 7, 0, 14, 30, 31}
542:
543: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
544:
545: #define LEAF_REGISTERS \
546: { 1, 1, 1, 1, 1, 1, 1, 1, \
547: 0, 0, 0, 0, 0, 0, 1, 0, \
548: 0, 0, 0, 0, 0, 0, 0, 0, \
549: 1, 1, 1, 1, 1, 1, 0, 1, \
550: 1, 1, 1, 1, 1, 1, 1, 1, \
551: 1, 1, 1, 1, 1, 1, 1, 1, \
552: 1, 1, 1, 1, 1, 1, 1, 1, \
553: 1, 1, 1, 1, 1, 1, 1, 1}
554:
555: extern char leaf_reg_remap[];
556: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
557: extern char leaf_reg_backmap[];
558: #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
559:
560: /* The class value for index registers, and the one for base regs. */
561: #define INDEX_REG_CLASS GENERAL_REGS
562: #define BASE_REG_CLASS GENERAL_REGS
563:
564: /* Get reg_class from a letter such as appears in the machine description. */
565:
566: #define REG_CLASS_FROM_LETTER(C) \
567: ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
568:
569: /* The letters I, J, K, L and M in a register constraint string
570: can be used to stand for particular ranges of immediate operands.
571: This macro defines what the ranges are.
572: C is the letter, and VALUE is a constant value.
573: Return 1 if VALUE is in the range specified by C.
574:
575: For SPARC, `I' is used for the range of constants an insn
576: can actually contain.
577: `J' is used for the range which is just zero (since that is R0).
578: `K' is used for constants which can be loaded with a single sethi insn. */
579:
580: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
581:
582: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
583: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
584: : (C) == 'J' ? (VALUE) == 0 \
585: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
586: : 0)
587:
588: /* Similar, but for floating constants, and defining letters G and H.
589: Here VALUE is the CONST_DOUBLE rtx itself. */
590:
591: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
592: ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
593: && CONST_DOUBLE_LOW (VALUE) == 0 \
594: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
595: : 0)
596:
597: /* Given an rtx X being reloaded into a reg required to be
598: in class CLASS, return the class of reg to actually use.
599: In general this is just CLASS; but on some machines
600: in some cases it is preferable to use a more restrictive class. */
601: /* We can't load constants into FP registers. We can't load any FP constant
602: if an 'E' constraint fails to match it. */
603: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
604: (CONSTANT_P (X) \
605: && ((CLASS) == FP_REGS \
606: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
607: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
608: || HOST_BITS_PER_INT != BITS_PER_WORD))) \
609: ? NO_REGS : (CLASS))
610:
611: /* Return the register class of a scratch register needed to load IN into
612: a register of class CLASS in MODE.
613:
614: On the SPARC, when PIC, we need a temporary when loading some addresses
615: into a register.
616:
617: Also, we need a temporary when loading/storing a HImode/QImode value
618: between memory and the FPU registers. This can happen when combine puts
619: a paradoxical subreg in a float/fix conversion insn. */
620:
621: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
622: (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS \
623: : ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
624: && (GET_CODE (IN) == MEM \
625: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
626: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
627:
628: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
629: ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
630: && (GET_CODE (IN) == MEM \
631: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
632: && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
633:
634: /* On SPARC it is not possible to directly move data between
635: GENERAL_REGS and FP_REGS. */
636: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
637: (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
638: || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
639:
640: /* Return the stack location to use for secondary memory needed reloads. */
641: #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
642: gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, GEN_INT (-8)))
643:
644: /* Return the maximum number of consecutive registers
645: needed to represent mode MODE in a register of class CLASS. */
646: /* On SPARC, this is the size of MODE in words. */
647: #define CLASS_MAX_NREGS(CLASS, MODE) \
648: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
649:
650: /* Stack layout; function entry, exit and calling. */
651:
652: /* Define the number of register that can hold parameters.
653: These two macros are used only in other macro definitions below. */
654: #define NPARM_REGS 6
655:
656: /* Define this if pushing a word on the stack
657: makes the stack pointer a smaller address. */
658: #define STACK_GROWS_DOWNWARD
659:
660: /* Define this if the nominal address of the stack frame
661: is at the high-address end of the local variables;
662: that is, each additional local variable allocated
663: goes at a more negative offset in the frame. */
664: #define FRAME_GROWS_DOWNWARD
665:
666: /* Offset within stack frame to start allocating local variables at.
667: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
668: first local allocated. Otherwise, it is the offset to the BEGINNING
669: of the first local allocated. */
670: #define STARTING_FRAME_OFFSET (-8)
671:
672: /* If we generate an insn to push BYTES bytes,
673: this says how many the stack pointer really advances by.
674: On SPARC, don't define this because there are no push insns. */
675: /* #define PUSH_ROUNDING(BYTES) */
676:
677: /* Offset of first parameter from the argument pointer register value.
678: This is 64 for the ins and locals, plus 4 for the struct-return reg
679: even if this function isn't going to use it. */
680: #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
681:
682: /* When a parameter is passed in a register, stack space is still
683: allocated for it. */
684: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
685:
686: /* Keep the stack pointer constant throughout the function.
687: This is both an optimization and a necessity: longjmp
688: doesn't behave itself when the stack pointer moves within
689: the function! */
690: #define ACCUMULATE_OUTGOING_ARGS
691:
692: /* Value is the number of bytes of arguments automatically
693: popped when returning from a subroutine call.
694: FUNTYPE is the data type of the function (as a tree),
695: or for a library call it is an identifier node for the subroutine name.
696: SIZE is the number of bytes of arguments passed on the stack. */
697:
698: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
699:
700: /* Some subroutine macros specific to this machine.
701: When !TARGET_FPU, put float return values in the general registers,
702: since we don't have any fp registers. */
703: #define BASE_RETURN_VALUE_REG(MODE) \
704: (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
705: #define BASE_OUTGOING_VALUE_REG(MODE) \
706: (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
707: : (TARGET_FRW ? 8 : 24))
708: #define BASE_PASSING_ARG_REG(MODE) (8)
709: #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
710:
711: /* Define this macro if the target machine has "register windows". This
712: C expression returns the register number as seen by the called function
713: corresponding to register number OUT as seen by the calling function.
714: Return OUT if register number OUT is not an outbound register. */
715:
716: #define INCOMING_REGNO(OUT) \
717: ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
718:
719: /* Define this macro if the target machine has "register windows". This
720: C expression returns the register number as seen by the calling function
721: corresponding to register number IN as seen by the called function.
722: Return IN if register number IN is not an inbound register. */
723:
724: #define OUTGOING_REGNO(IN) \
725: ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
726:
727: /* Define how to find the value returned by a function.
728: VALTYPE is the data type of the value (as a tree).
729: If the precise function being called is known, FUNC is its FUNCTION_DECL;
730: otherwise, FUNC is 0. */
731:
732: /* On SPARC the value is found in the first "output" register. */
733:
734: #define FUNCTION_VALUE(VALTYPE, FUNC) \
735: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
736:
737: /* But the called function leaves it in the first "input" register. */
738:
739: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
740: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
741:
742: /* Define how to find the value returned by a library function
743: assuming the value has mode MODE. */
744:
745: #define LIBCALL_VALUE(MODE) \
746: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
747:
748: /* 1 if N is a possible register number for a function value
749: as seen by the caller.
750: On SPARC, the first "output" reg is used for integer values,
751: and the first floating point register is used for floating point values. */
752:
753: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
754:
755: /* 1 if N is a possible register number for function argument passing.
756: On SPARC, these are the "output" registers. */
757:
758: #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
759:
760: /* Define a data type for recording info about an argument list
761: during the scan of that argument list. This data type should
762: hold all necessary information about the function itself
763: and about the args processed so far, enough to enable macros
764: such as FUNCTION_ARG to determine where the next arg should go.
765:
766: On SPARC, this is a single integer, which is a number of words
767: of arguments scanned so far (including the invisible argument,
768: if any, which holds the structure-value-address).
769: Thus 7 or more means all following args should go on the stack. */
770:
771: #define CUMULATIVE_ARGS int
772:
773: #define ROUND_ADVANCE(SIZE) \
774: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
775:
776: /* Initialize a variable CUM of type CUMULATIVE_ARGS
777: for a call to a function whose data type is FNTYPE.
778: For a library call, FNTYPE is 0.
779:
780: On SPARC, the offset always starts at 0: the first parm reg is always
781: the same reg. */
782:
783: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
784:
785: /* Update the data in CUM to advance over an argument
786: of mode MODE and data type TYPE.
787: (TYPE is null for libcalls where that information may not be available.) */
788:
789: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
790: ((CUM) += ((MODE) != BLKmode \
791: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
792: : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
793:
794: /* Determine where to put an argument to a function.
795: Value is zero to push the argument on the stack,
796: or a hard register in which to store the argument.
797:
798: MODE is the argument's machine mode.
799: TYPE is the data type of the argument (as a tree).
800: This is null for libcalls where that information may
801: not be available.
802: CUM is a variable of type CUMULATIVE_ARGS which gives info about
803: the preceding args and about the function being called.
804: NAMED is nonzero if this argument is a named parameter
805: (otherwise it is an extra parameter matching an ellipsis). */
806:
807: /* On SPARC the first six args are normally in registers
808: and the rest are pushed. Any arg that starts within the first 6 words
809: is at least partially passed in a register unless its data type forbids. */
810:
811: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
812: ((CUM) < NPARM_REGS \
813: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
814: && ((TYPE)==0 || (MODE) != BLKmode \
815: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
816: ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
817: : 0)
818:
819: /* Define where a function finds its arguments.
820: This is different from FUNCTION_ARG because of register windows. */
821:
822: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
823: ((CUM) < NPARM_REGS \
824: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
825: && ((TYPE)==0 || (MODE) != BLKmode \
826: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
827: ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
828: : 0)
829:
830: /* For an arg passed partly in registers and partly in memory,
831: this is the number of registers used.
832: For args passed entirely in registers or entirely in memory, zero.
833: Any arg that starts in the first 6 regs but won't entirely fit in them
834: needs partial registers on the Sparc. */
835:
836: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
837: ((CUM) < NPARM_REGS \
838: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
839: && ((TYPE)==0 || (MODE) != BLKmode \
840: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
841: && ((CUM) + ((MODE) == BLKmode \
842: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
843: : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
844: ? (NPARM_REGS - (CUM)) \
845: : 0)
846:
847: /* The SPARC ABI stipulates passing struct arguments (of any size) and
848: quad-precision floats by invisible reference. */
849: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
850: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
851: || TREE_CODE (TYPE) == UNION_TYPE)) \
852: || (MODE == TFmode))
853:
854: /* Define the information needed to generate branch and scc insns. This is
855: stored from the compare operation. Note that we can't use "rtx" here
856: since it hasn't been defined! */
857:
858: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
859:
860: /* Define the function that build the compare insn for scc and bcc. */
861:
862: extern struct rtx_def *gen_compare_reg ();
863:
864: /* Generate the special assembly code needed to tell the assembler whatever
865: it might need to know about the return value of a function.
866:
867: For Sparc assemblers, we need to output a .proc pseudo-op which conveys
868: information to the assembler relating to peephole optimization (done in
869: the assembler). */
870:
871: #define ASM_DECLARE_RESULT(FILE, RESULT) \
872: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
873:
874: /* Output the label for a function definition. */
875:
876: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
877: do { \
878: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
879: ASM_OUTPUT_LABEL (FILE, NAME); \
880: } while (0)
881:
882: /* Two views of the size of the current frame. */
883: extern int actual_fsize;
884: extern int apparent_fsize;
885:
886: /* This macro generates the assembly code for function entry.
887: FILE is a stdio stream to output the code to.
888: SIZE is an int: how many units of temporary storage to allocate.
889: Refer to the array `regs_ever_live' to determine which registers
890: to save; `regs_ever_live[I]' is nonzero if register number I
891: is ever used in the function. This macro is responsible for
892: knowing which registers should not be saved even if used. */
893:
894: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
895: of memory. If any fpu reg is used in the function, we allocate
896: such a block here, at the bottom of the frame, just in case it's needed.
897:
898: If this function is a leaf procedure, then we may choose not
899: to do a "save" insn. The decision about whether or not
900: to do this is made in regclass.c. */
901:
902: #define FUNCTION_PROLOGUE(FILE, SIZE) \
903: (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\
904: : output_function_prologue (FILE, SIZE, leaf_function))
905:
906: /* Output assembler code to FILE to increment profiler label # LABELNO
907: for profiling a function entry. */
908:
909: #define FUNCTION_PROFILER(FILE, LABELNO) \
910: do { \
911: fputs ("\tsethi %hi(", (FILE)); \
912: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
913: fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
914: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
915: fputs ("),%o0,%o0\n", (FILE)); \
916: } while (0)
917:
918: /* Output assembler code to FILE to initialize this source file's
919: basic block profiling info, if that has not already been done. */
920: /* FIXME -- this does not parameterize how it generates labels (like the
921: above FUNCTION_PROFILER). Broken on Solaris-2. [email protected] */
922:
923: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
924: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
925: (LABELNO), (LABELNO))
926:
927: /* Output assembler code to FILE to increment the entry-count for
928: the BLOCKNO'th basic block in this source file. */
929:
930: #define BLOCK_PROFILER(FILE, BLOCKNO) \
931: { \
932: int blockn = (BLOCKNO); \
933: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
934: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
935: 4 * blockn, 4 * blockn, 4 * blockn); \
936: }
937:
938: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
939: the stack pointer does not matter. The value is tested only in
940: functions that have frame pointers.
941: No definition is equivalent to always zero. */
942:
943: extern int current_function_calls_alloca;
944: extern int current_function_outgoing_args_size;
945:
946: #define EXIT_IGNORE_STACK \
947: (get_frame_size () != 0 \
948: || current_function_calls_alloca || current_function_outgoing_args_size)
949:
950: /* This macro generates the assembly code for function exit,
951: on machines that need it. If FUNCTION_EPILOGUE is not defined
952: then individual return instructions are generated for each
953: return statement. Args are same as for FUNCTION_PROLOGUE.
954:
955: The function epilogue should not depend on the current stack pointer!
956: It should use the frame pointer only. This is mandatory because
957: of alloca; we also take advantage of it to omit stack adjustments
958: before returning. */
959:
960: /* This declaration is needed due to traditional/ANSI
961: incompatibilities which cannot be #ifdefed away
962: because they occur inside of macros. Sigh. */
963: extern union tree_node *current_function_decl;
964:
965: #define FUNCTION_EPILOGUE(FILE, SIZE) \
966: (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\
967: : output_function_epilogue (FILE, SIZE, leaf_function))
968:
969: #define DELAY_SLOTS_FOR_EPILOGUE \
970: (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1)
971: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
972: (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
973: : eligible_for_epilogue_delay (trial, slots_filled))
974:
975: /* Output assembler code for a block containing the constant parts
976: of a trampoline, leaving space for the variable parts. */
977:
978: /* On the sparc, the trampoline contains five instructions:
979: sethi #TOP_OF_FUNCTION,%g2
980: or #BOTTOM_OF_FUNCTION,%g2,%g2
981: sethi #TOP_OF_STATIC,%g1
982: jmp g2
983: or #BOTTOM_OF_STATIC,%g1,%g1 */
984: #define TRAMPOLINE_TEMPLATE(FILE) \
985: { \
986: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
987: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
988: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
989: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
990: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
991: }
992:
993: /* Length in units of the trampoline for entering a nested function. */
994:
995: #define TRAMPOLINE_SIZE 20
996:
997: /* Emit RTL insns to initialize the variable parts of a trampoline.
998: FNADDR is an RTX for the address of the function's pure code.
999: CXT is an RTX for the static chain value for the function.
1000:
1001: This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
1002: (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
1003: (to store insns). This is a bit excessive. Perhaps a different
1004: mechanism would be better here. */
1005:
1006: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1007: { \
1008: rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1009: size_int (10), 0, 1); \
1010: rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1011: size_int (10), 0, 1); \
1012: rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1013: rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1014: rtx g1_sethi = gen_rtx (HIGH, SImode, \
1015: gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1016: rtx g2_sethi = gen_rtx (HIGH, SImode, \
1017: gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1018: rtx g1_ori = gen_rtx (HIGH, SImode, \
1019: gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1020: rtx g2_ori = gen_rtx (HIGH, SImode, \
1021: gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1022: rtx tem = gen_reg_rtx (SImode); \
1023: emit_move_insn (tem, g2_sethi); \
1024: emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1025: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1026: emit_move_insn (tem, g2_ori); \
1027: emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1028: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1029: emit_move_insn (tem, g1_sethi); \
1030: emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1031: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1032: emit_move_insn (tem, g1_ori); \
1033: emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1034: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1035: }
1036:
1037: /* Generate necessary RTL for __builtin_saveregs().
1038: ARGLIST is the argument list; see expr.c. */
1039: extern struct rtx_def *sparc_builtin_saveregs ();
1040: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1041:
1042: /* Generate RTL to flush the register windows so as to make arbitrary frames
1043: available. */
1044: #define SETUP_FRAME_ADDRESSES() \
1045: emit_insn (gen_flush_register_windows ())
1046:
1047: /* Given an rtx for the address of a frame,
1048: return an rtx for the address of the word in the frame
1049: that holds the dynamic chain--the previous frame's address. */
1050: #define DYNAMIC_CHAIN_ADDRESS(frame) \
1051: gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1052:
1053: /* The return address isn't on the stack, it is in a register, so we can't
1054: access it from the current frame pointer. We can access it from the
1055: previous frame pointer though by reading a value from the register window
1056: save area. */
1057: #define RETURN_ADDR_IN_PREVIOUS_FRAME
1058:
1059: /* The current return address is in %i7. The return address of anything
1060: farther back is in the register window save area at [%fp+60]. */
1061: /* ??? This ignores the fact that the actual return address is +8 for normal
1062: returns, and +12 for structure returns. */
1063: #define RETURN_ADDR_RTX(count, frame) \
1064: ((count == -1) \
1065: ? gen_rtx (REG, Pmode, 31) \
1066: : copy_to_reg (gen_rtx (MEM, Pmode, \
1067: memory_address (Pmode, plus_constant (frame, 60)))))
1068:
1069: /* Addressing modes, and classification of registers for them. */
1070:
1071: /* #define HAVE_POST_INCREMENT */
1072: /* #define HAVE_POST_DECREMENT */
1073:
1074: /* #define HAVE_PRE_DECREMENT */
1075: /* #define HAVE_PRE_INCREMENT */
1076:
1077: /* Macros to check register numbers against specific register classes. */
1078:
1079: /* These assume that REGNO is a hard or pseudo reg number.
1080: They give nonzero only if REGNO is a hard reg of the suitable class
1081: or a pseudo reg currently allocated to a suitable hard reg.
1082: Since they use reg_renumber, they are safe only once reg_renumber
1083: has been allocated, which happens in local-alloc.c. */
1084:
1085: #define REGNO_OK_FOR_INDEX_P(REGNO) \
1086: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1087: #define REGNO_OK_FOR_BASE_P(REGNO) \
1088: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1089: #define REGNO_OK_FOR_FP_P(REGNO) \
1090: (((REGNO) ^ 0x20) < 32 \
1091: || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1092:
1093: /* Now macros that check whether X is a register and also,
1094: strictly, whether it is in a specified class.
1095:
1096: These macros are specific to the SPARC, and may be used only
1097: in code for printing assembler insns and in conditions for
1098: define_optimization. */
1099:
1100: /* 1 if X is an fp register. */
1101:
1102: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1103:
1104: /* Maximum number of registers that can appear in a valid memory address. */
1105:
1106: #define MAX_REGS_PER_ADDRESS 2
1107:
1108: /* Recognize any constant value that is a valid address. */
1109:
1110: #define CONSTANT_ADDRESS_P(X) \
1111: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1112: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1113: || GET_CODE (X) == HIGH)
1114:
1115: /* Nonzero if the constant value X is a legitimate general operand.
1116: Anything can be made to work except floating point constants. */
1117:
1118: #define LEGITIMATE_CONSTANT_P(X) \
1119: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1120:
1121: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1122: and check its validity for a certain class.
1123: We have two alternate definitions for each of them.
1124: The usual definition accepts all pseudo regs; the other rejects
1125: them unless they have been allocated suitable hard regs.
1126: The symbol REG_OK_STRICT causes the latter definition to be used.
1127:
1128: Most source files want to accept pseudo regs in the hope that
1129: they will get allocated to the class that the insn wants them to be in.
1130: Source files for reload pass need to be strict.
1131: After reload, it makes no difference, since pseudo regs have
1132: been eliminated by then. */
1133:
1134: /* Optional extra constraints for this machine. Borrowed from romp.h.
1135:
1136: For the SPARC, `Q' means that this is a memory operand but not a
1137: symbolic memory operand. Note that an unassigned pseudo register
1138: is such a memory operand. Needed because reload will generate
1139: these things in insns and then not re-recognize the insns, causing
1140: constrain_operands to fail.
1141:
1142: `S' handles constraints for calls. */
1143:
1144: #ifndef REG_OK_STRICT
1145:
1146: /* Nonzero if X is a hard reg that can be used as an index
1147: or if it is a pseudo reg. */
1148: #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1149: /* Nonzero if X is a hard reg that can be used as a base reg
1150: or if it is a pseudo reg. */
1151: #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1152:
1153: #define EXTRA_CONSTRAINT(OP, C) \
1154: ((C) == 'Q' \
1155: ? ((GET_CODE (OP) == MEM \
1156: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1157: && ! symbolic_memory_operand (OP, VOIDmode)) \
1158: || (reload_in_progress && GET_CODE (OP) == REG \
1159: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1160: : (C) == 'S' \
1161: ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1162: : (C) == 'T' \
1163: ? (mem_aligned_8 (OP)) \
1164: : (C) == 'U' \
1165: ? (register_ok_for_ldd (OP)) \
1166: : 0)
1167:
1168: #else
1169:
1170: /* Nonzero if X is a hard reg that can be used as an index. */
1171: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1172: /* Nonzero if X is a hard reg that can be used as a base reg. */
1173: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1174:
1175: #define EXTRA_CONSTRAINT(OP, C) \
1176: ((C) == 'Q' \
1177: ? (GET_CODE (OP) == REG \
1178: ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1179: && reg_renumber[REGNO (OP)] < 0) \
1180: : GET_CODE (OP) == MEM) \
1181: : (C) == 'S' \
1182: ? (CONSTANT_P (OP) \
1183: || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0) \
1184: || strict_memory_address_p (Pmode, OP)) \
1185: : (C) == 'T' \
1186: ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, OP) \
1187: : (C) == 'U' \
1188: ? register_ok_for_ldd (OP) : 0)
1189: #endif
1190:
1191: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1192: that is a valid memory address for an instruction.
1193: The MODE argument is the machine mode for the MEM expression
1194: that wants to use this address.
1195:
1196: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1197: ordinarily. This changes a bit when generating PIC.
1198:
1199: If you change this, execute "rm explow.o recog.o reload.o". */
1200:
1201: #define RTX_OK_FOR_BASE_P(X) \
1202: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1203: || (GET_CODE (X) == SUBREG \
1204: && GET_CODE (SUBREG_REG (X)) == REG \
1205: && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1206:
1207: #define RTX_OK_FOR_INDEX_P(X) \
1208: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1209: || (GET_CODE (X) == SUBREG \
1210: && GET_CODE (SUBREG_REG (X)) == REG \
1211: && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1212:
1213: #define RTX_OK_FOR_OFFSET_P(X) \
1214: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1215:
1216: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1217: { if (RTX_OK_FOR_BASE_P (X)) \
1218: goto ADDR; \
1219: else if (GET_CODE (X) == PLUS) \
1220: { \
1221: register rtx op0 = XEXP (X, 0); \
1222: register rtx op1 = XEXP (X, 1); \
1223: if (flag_pic && op0 == pic_offset_table_rtx) \
1224: { \
1225: if (RTX_OK_FOR_BASE_P (op1)) \
1226: goto ADDR; \
1227: else if (flag_pic == 1 \
1228: && GET_CODE (op1) != REG \
1229: && GET_CODE (op1) != LO_SUM \
1230: && GET_CODE (op1) != MEM) \
1231: goto ADDR; \
1232: } \
1233: else if (RTX_OK_FOR_BASE_P (op0)) \
1234: { \
1235: if (RTX_OK_FOR_INDEX_P (op1) \
1236: || RTX_OK_FOR_OFFSET_P (op1)) \
1237: goto ADDR; \
1238: } \
1239: else if (RTX_OK_FOR_BASE_P (op1)) \
1240: { \
1241: if (RTX_OK_FOR_INDEX_P (op0) \
1242: || RTX_OK_FOR_OFFSET_P (op0)) \
1243: goto ADDR; \
1244: } \
1245: } \
1246: else if (GET_CODE (X) == LO_SUM) \
1247: { \
1248: register rtx op0 = XEXP (X, 0); \
1249: register rtx op1 = XEXP (X, 1); \
1250: if (RTX_OK_FOR_BASE_P (op0) \
1251: && CONSTANT_P (op1)) \
1252: goto ADDR; \
1253: } \
1254: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1255: goto ADDR; \
1256: }
1257:
1258: /* Try machine-dependent ways of modifying an illegitimate address
1259: to be legitimate. If we find one, return the new, valid address.
1260: This macro is used in only one place: `memory_address' in explow.c.
1261:
1262: OLDX is the address as it was before break_out_memory_refs was called.
1263: In some cases it is useful to look at this to decide what needs to be done.
1264:
1265: MODE and WIN are passed so that this macro can use
1266: GO_IF_LEGITIMATE_ADDRESS.
1267:
1268: It is always safe for this macro to do nothing. It exists to recognize
1269: opportunities to optimize the output. */
1270:
1271: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1272: extern struct rtx_def *legitimize_pic_address ();
1273: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1274: { rtx sparc_x = (X); \
1275: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1276: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1277: force_operand (XEXP (X, 0), NULL_RTX)); \
1278: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1279: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1280: force_operand (XEXP (X, 1), NULL_RTX)); \
1281: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1282: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1283: XEXP (X, 1)); \
1284: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1285: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1286: force_operand (XEXP (X, 1), NULL_RTX)); \
1287: if (sparc_x != (X) && memory_address_p (MODE, X)) \
1288: goto WIN; \
1289: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1290: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1291: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1292: copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1293: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1294: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1295: copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1296: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1297: || GET_CODE (X) == LABEL_REF) \
1298: (X) = gen_rtx (LO_SUM, Pmode, \
1299: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1300: if (memory_address_p (MODE, X)) \
1301: goto WIN; }
1302:
1303: /* Go to LABEL if ADDR (a legitimate address expression)
1304: has an effect that depends on the machine mode it is used for.
1305: On the SPARC this is never true. */
1306:
1307: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1308:
1309: /* Specify the machine mode that this machine uses
1310: for the index in the tablejump instruction. */
1311: #define CASE_VECTOR_MODE SImode
1312:
1313: /* Define this if the tablejump instruction expects the table
1314: to contain offsets from the address of the table.
1315: Do not define this if the table should contain absolute addresses. */
1316: /* #define CASE_VECTOR_PC_RELATIVE */
1317:
1318: /* Specify the tree operation to be used to convert reals to integers. */
1319: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1320:
1321: /* This is the kind of divide that is easiest to do in the general case. */
1322: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1323:
1324: /* Define this as 1 if `char' should by default be signed; else as 0. */
1325: #define DEFAULT_SIGNED_CHAR 1
1326:
1327: /* Max number of bytes we can move from memory to memory
1328: in one reasonably fast instruction. */
1329: #define MOVE_MAX 8
1330:
1331: #if 0 /* Sun 4 has matherr, so this is no good. */
1332: /* This is the value of the error code EDOM for this machine,
1333: used by the sqrt instruction. */
1334: #define TARGET_EDOM 33
1335:
1336: /* This is how to refer to the variable errno. */
1337: #define GEN_ERRNO_RTX \
1338: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1339: #endif /* 0 */
1340:
1341: /* Define if normal loads of shorter-than-word items from memory clears
1342: the rest of the bigs in the register. */
1343: #define BYTE_LOADS_ZERO_EXTEND
1344:
1345: /* Nonzero if access to memory by bytes is slow and undesirable.
1346: For RISC chips, it means that access to memory by bytes is no
1347: better than access by words when possible, so grab a whole word
1348: and maybe make use of that. */
1349: #define SLOW_BYTE_ACCESS 1
1350:
1351: /* We assume that the store-condition-codes instructions store 0 for false
1352: and some other value for true. This is the value stored for true. */
1353:
1354: #define STORE_FLAG_VALUE 1
1355:
1356: /* When a prototype says `char' or `short', really pass an `int'. */
1357: #define PROMOTE_PROTOTYPES
1358:
1359: /* Define if shifts truncate the shift count
1360: which implies one can omit a sign-extension or zero-extension
1361: of a shift count. */
1362: #define SHIFT_COUNT_TRUNCATED
1363:
1364: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1365: is done just by pretending it is already truncated. */
1366: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1367:
1368: /* Specify the machine mode that pointers have.
1369: After generation of rtl, the compiler makes no further distinction
1370: between pointers and any other objects of this machine mode. */
1371: #define Pmode SImode
1372:
1373: /* Generate calls to memcpy, memcmp and memset. */
1374: #define TARGET_MEM_FUNCTIONS
1375:
1376: /* Add any extra modes needed to represent the condition code.
1377:
1378: On the Sparc, we have a "no-overflow" mode which is used when an add or
1379: subtract insn is used to set the condition code. Different branches are
1380: used in this case for some operations.
1381:
1382: We also have two modes to indicate that the relevant condition code is
1383: in the floating-point condition code register. One for comparisons which
1384: will generate an exception if the result is unordered (CCFPEmode) and
1385: one for comparisons which will never trap (CCFPmode). This really should
1386: be a separate register, but we don't want to go to 65 registers. */
1387: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1388:
1389: /* Define the names for the modes specified above. */
1390: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1391:
1392: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1393: return the mode to be used for the comparison. For floating-point,
1394: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1395: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1396: needed. */
1397: #define SELECT_CC_MODE(OP,X,Y) \
1398: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1399: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1400: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1401: ? CC_NOOVmode : CCmode))
1402:
1403: /* A function address in a call instruction
1404: is a byte address (for indexing purposes)
1405: so give the MEM rtx a byte's mode. */
1406: #define FUNCTION_MODE SImode
1407:
1408: /* Define this if addresses of constant functions
1409: shouldn't be put through pseudo regs where they can be cse'd.
1410: Desirable on machines where ordinary constants are expensive
1411: but a CALL with constant address is cheap. */
1412: #define NO_FUNCTION_CSE
1413:
1414: /* alloca should avoid clobbering the old register save area. */
1415: #define SETJMP_VIA_SAVE_AREA
1416:
1417: /* Define subroutines to call to handle multiply and divide.
1418: Use the subroutines that Sun's library provides.
1419: The `*' prevents an underscore from being prepended by the compiler. */
1420:
1421: #define DIVSI3_LIBCALL "*.div"
1422: #define UDIVSI3_LIBCALL "*.udiv"
1423: #define MODSI3_LIBCALL "*.rem"
1424: #define UMODSI3_LIBCALL "*.urem"
1425: /* .umul is a little faster than .mul. */
1426: #define MULSI3_LIBCALL "*.umul"
1427:
1428: /* Compute the cost of computing a constant rtl expression RTX
1429: whose rtx-code is CODE. The body of this macro is a portion
1430: of a switch statement. If the code is computed here,
1431: return it with a return statement. Otherwise, break from the switch. */
1432:
1433: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1434: case CONST_INT: \
1435: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1436: return 0; \
1437: case HIGH: \
1438: return 2; \
1439: case CONST: \
1440: case LABEL_REF: \
1441: case SYMBOL_REF: \
1442: return 4; \
1443: case CONST_DOUBLE: \
1444: if (GET_MODE (RTX) == DImode) \
1445: if ((XINT (RTX, 3) == 0 \
1446: && (unsigned) XINT (RTX, 2) < 0x1000) \
1447: || (XINT (RTX, 3) == -1 \
1448: && XINT (RTX, 2) < 0 \
1449: && XINT (RTX, 2) >= -0x1000)) \
1450: return 0; \
1451: return 8;
1452:
1453: /* SPARC offers addressing modes which are "as cheap as a register".
1454: See sparc.c (or gcc.texinfo) for details. */
1455:
1456: #define ADDRESS_COST(RTX) \
1457: (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1458:
1459: /* Compute extra cost of moving data between one register class
1460: and another. */
1461: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1462: (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1463: || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1464:
1465: /* Provide the costs of a rtl expression. This is in the body of a
1466: switch on CODE. The purpose for the cost of MULT is to encourage
1467: `synth_mult' to find a synthetic multiply when reasonable.
1468:
1469: If we need more than 12 insns to do a multiply, then go out-of-line,
1470: since the call overhead will be < 10% of the cost of the multiply. */
1471:
1472: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1473: case MULT: \
1474: return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
1475: case DIV: \
1476: case UDIV: \
1477: case MOD: \
1478: case UMOD: \
1479: return COSTS_N_INSNS (25); \
1480: /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1481: so that cse will favor the latter. */ \
1482: case FLOAT: \
1483: case FIX: \
1484: return 19;
1485:
1486: /* Conditional branches with empty delay slots have a length of two. */
1487: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1488: if (GET_CODE (INSN) == CALL_INSN \
1489: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1490: LENGTH += 1;
1491:
1492: /* Control the assembler format that we output. */
1493:
1494: /* Output at beginning of assembler file. */
1495:
1496: #define ASM_FILE_START(file)
1497:
1498: /* Output to assembler file text saying following lines
1499: may contain character constants, extra white space, comments, etc. */
1500:
1501: #define ASM_APP_ON ""
1502:
1503: /* Output to assembler file text saying following lines
1504: no longer contain unusual constructs. */
1505:
1506: #define ASM_APP_OFF ""
1507:
1508: #define ASM_LONG ".word"
1509: #define ASM_SHORT ".half"
1510: #define ASM_BYTE_OP ".byte"
1511:
1512: /* Output before read-only data. */
1513:
1514: #define TEXT_SECTION_ASM_OP ".text"
1515:
1516: /* Output before writable data. */
1517:
1518: #define DATA_SECTION_ASM_OP ".data"
1519:
1520: /* How to refer to registers in assembler output.
1521: This sequence is indexed by compiler's hard-register-number (see above). */
1522:
1523: #define REGISTER_NAMES \
1524: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1525: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1526: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1527: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1528: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1529: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1530: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1531: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1532:
1533: /* Define additional names for use in asm clobbers and asm declarations.
1534:
1535: We define the fake Condition Code register as an alias for reg 0 (which
1536: is our `condition code' register), so that condition codes can easily
1537: be clobbered by an asm. No such register actually exists. Condition
1538: codes are partly stored in the PSR and partly in the FSR. */
1539:
1540: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1541:
1542: /* How to renumber registers for dbx and gdb. */
1543:
1544: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1545:
1546: /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1547: since the length can run past this up to a continuation point. */
1548: #define DBX_CONTIN_LENGTH 1500
1549:
1550: /* This is how to output a note to DBX telling it the line number
1551: to which the following sequence of instructions corresponds.
1552:
1553: This is needed for SunOS 4.0, and should not hurt for 3.2
1554: versions either. */
1555: #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1556: { static int sym_lineno = 1; \
1557: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1558: line, sym_lineno, sym_lineno); \
1559: sym_lineno += 1; }
1560:
1561: /* This is how to output the definition of a user-level label named NAME,
1562: such as the label on a static function or variable NAME. */
1563:
1564: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1565: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1566:
1567: /* This is how to output a command to make the user-level label named NAME
1568: defined for reference from other files. */
1569:
1570: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1571: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1572:
1573: /* This is how to output a reference to a user-level label named NAME.
1574: `assemble_name' uses this. */
1575:
1576: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1577: fprintf (FILE, "_%s", NAME)
1578:
1579: /* This is how to output a definition of an internal numbered label where
1580: PREFIX is the class of label and NUM is the number within the class. */
1581:
1582: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1583: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1584:
1585: /* This is how to output a reference to an internal numbered label where
1586: PREFIX is the class of label and NUM is the number within the class. */
1587: /* FIXME: This should be used throughout gcc, and documented in the texinfo
1588: files. There is no reason you should have to allocate a buffer and
1589: `sprintf' to reference an internal label (as opposed to defining it). */
1590:
1591: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1592: fprintf (FILE, "%s%d", PREFIX, NUM)
1593:
1594: /* This is how to store into the string LABEL
1595: the symbol_ref name of an internal numbered label where
1596: PREFIX is the class of label and NUM is the number within the class.
1597: This is suitable for output with `assemble_name'. */
1598:
1599: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1600: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1601:
1602: /* This is how to output an assembler line defining a `double' constant. */
1603:
1604: /* Assemblers (both gas 1.35 and as in 4.0.3)
1605: seem to treat -0.0 as if it were 0.0.
1606: They reject 99e9999, but accept inf. */
1607: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1608: { \
1609: if (REAL_VALUE_ISINF (VALUE) \
1610: || REAL_VALUE_ISNAN (VALUE) \
1611: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1612: { \
1613: long t[2]; \
1614: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1615: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1616: ASM_LONG, t[0], ASM_LONG, t[1]); \
1617: } \
1618: else \
1619: fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1620: }
1621:
1622: /* This is how to output an assembler line defining a `float' constant. */
1623:
1624: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1625: { \
1626: if (REAL_VALUE_ISINF (VALUE) \
1627: || REAL_VALUE_ISNAN (VALUE) \
1628: || REAL_VALUE_MINUS_ZERO (VALUE)) \
1629: { \
1630: long t; \
1631: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1632: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1633: } \
1634: else \
1635: fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1636: }
1637:
1638: /* This is how to output an assembler line defining a `long double'
1639: constant. */
1640:
1641: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1642: { \
1643: long t[4]; \
1644: REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1645: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1646: ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1647: }
1648:
1649: /* This is how to output an assembler line defining an `int' constant. */
1650:
1651: #define ASM_OUTPUT_INT(FILE,VALUE) \
1652: ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1653: output_addr_const (FILE, (VALUE)), \
1654: fprintf (FILE, "\n"))
1655:
1656: /* This is how to output an assembler line defining a DImode constant. */
1657: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1658: output_double_int (FILE, VALUE)
1659:
1660: /* Likewise for `char' and `short' constants. */
1661:
1662: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1663: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1664: output_addr_const (FILE, (VALUE)), \
1665: fprintf (FILE, "\n"))
1666:
1667: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1668: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1669: output_addr_const (FILE, (VALUE)), \
1670: fprintf (FILE, "\n"))
1671:
1672: /* This is how to output an assembler line for a numeric constant byte. */
1673:
1674: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1675: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1676:
1677: /* This is how to output an element of a case-vector that is absolute. */
1678:
1679: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1680: do { \
1681: char label[30]; \
1682: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1683: fprintf (FILE, "\t.word\t"); \
1684: assemble_name (FILE, label); \
1685: fprintf (FILE, "\n"); \
1686: } while (0)
1687:
1688: /* This is how to output an element of a case-vector that is relative.
1689: (SPARC uses such vectors only when generating PIC.) */
1690:
1691: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1692: do { \
1693: char label[30]; \
1694: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1695: fprintf (FILE, "\t.word\t"); \
1696: assemble_name (FILE, label); \
1697: fprintf (FILE, "-1b\n"); \
1698: } while (0)
1699:
1700: /* This is how to output an assembler line
1701: that says to advance the location counter
1702: to a multiple of 2**LOG bytes. */
1703:
1704: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1705: if ((LOG) != 0) \
1706: fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1707:
1708: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1709: fprintf (FILE, "\t.skip %u\n", (SIZE))
1710:
1711: /* This says how to output an assembler line
1712: to define a global common symbol. */
1713:
1714: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1715: ( fputs ("\t.global ", (FILE)), \
1716: assemble_name ((FILE), (NAME)), \
1717: fputs ("\n\t.common ", (FILE)), \
1718: assemble_name ((FILE), (NAME)), \
1719: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1720:
1721: /* This says how to output an assembler line
1722: to define a local common symbol. */
1723:
1724: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1725: ( fputs ("\n\t.reserve ", (FILE)), \
1726: assemble_name ((FILE), (NAME)), \
1727: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1728:
1729: /* Store in OUTPUT a string (made with alloca) containing
1730: an assembler-name for a local static variable named NAME.
1731: LABELNO is an integer which is different for each call. */
1732:
1733: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1734: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1735: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1736:
1737: #define IDENT_ASM_OP ".ident"
1738:
1739: /* Output #ident as a .ident. */
1740:
1741: #define ASM_OUTPUT_IDENT(FILE, NAME) \
1742: fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1743:
1744: /* Define the parentheses used to group arithmetic operations
1745: in assembler code. */
1746:
1747: #define ASM_OPEN_PAREN "("
1748: #define ASM_CLOSE_PAREN ")"
1749:
1750: /* Define results of standard character escape sequences. */
1751: #define TARGET_BELL 007
1752: #define TARGET_BS 010
1753: #define TARGET_TAB 011
1754: #define TARGET_NEWLINE 012
1755: #define TARGET_VT 013
1756: #define TARGET_FF 014
1757: #define TARGET_CR 015
1758:
1759: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1760: ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1761:
1762: /* Print operand X (an rtx) in assembler syntax to file FILE.
1763: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1764: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1765:
1766: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1767:
1768: /* Print a memory address as an operand to reference that memory location. */
1769:
1770: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1771: { register rtx base, index = 0; \
1772: int offset = 0; \
1773: register rtx addr = ADDR; \
1774: if (GET_CODE (addr) == REG) \
1775: fputs (reg_names[REGNO (addr)], FILE); \
1776: else if (GET_CODE (addr) == PLUS) \
1777: { \
1778: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1779: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1780: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1781: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1782: else \
1783: base = XEXP (addr, 0), index = XEXP (addr, 1); \
1784: fputs (reg_names[REGNO (base)], FILE); \
1785: if (index == 0) \
1786: fprintf (FILE, "%+d", offset); \
1787: else if (GET_CODE (index) == REG) \
1788: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1789: else if (GET_CODE (index) == SYMBOL_REF) \
1790: fputc ('+', FILE), output_addr_const (FILE, index); \
1791: else abort (); \
1792: } \
1793: else if (GET_CODE (addr) == MINUS \
1794: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1795: { \
1796: output_addr_const (FILE, XEXP (addr, 0)); \
1797: fputs ("-(", FILE); \
1798: output_addr_const (FILE, XEXP (addr, 1)); \
1799: fputs ("-.)", FILE); \
1800: } \
1801: else if (GET_CODE (addr) == LO_SUM) \
1802: { \
1803: output_operand (XEXP (addr, 0), 0); \
1804: fputs ("+%lo(", FILE); \
1805: output_address (XEXP (addr, 1)); \
1806: fputc (')', FILE); \
1807: } \
1808: else if (flag_pic && GET_CODE (addr) == CONST \
1809: && GET_CODE (XEXP (addr, 0)) == MINUS \
1810: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1811: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1812: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1813: { \
1814: addr = XEXP (addr, 0); \
1815: output_addr_const (FILE, XEXP (addr, 0)); \
1816: /* Group the args of the second CONST in parenthesis. */ \
1817: fputs ("-(", FILE); \
1818: /* Skip past the second CONST--it does nothing for us. */\
1819: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1820: /* Close the parenthesis. */ \
1821: fputc (')', FILE); \
1822: } \
1823: else \
1824: { \
1825: output_addr_const (FILE, addr); \
1826: } \
1827: }
1828:
1829: /* Declare functions defined in sparc.c and used in templates. */
1830:
1831: extern char *singlemove_string ();
1832: extern char *output_move_double ();
1833: extern char *output_move_quad ();
1834: extern char *output_fp_move_double ();
1835: extern char *output_fp_move_quad ();
1836: extern char *output_block_move ();
1837: extern char *output_scc_insn ();
1838: extern char *output_cbranch ();
1839: extern char *output_return ();
1840:
1841: /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1842:
1843: extern int flag_pic;
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