![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to sparc.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc / config / sparc|
Return to sparc.h CVS log | Up to [GCC 2.x] / gcc / config / sparc |
1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC. 1.1.1.3 ! root 2: Copyright (C) 1987, 1988, 1989, 1992, 1994 Free Software Foundation, Inc. 1.1 root 3: Contributed by Michael Tiemann ([email protected]). 1.1.1.3 ! root 4: 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, ! 5: at Cygnus Support. 1.1 root 6: 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 22: 23: /* Note that some other tm.h files include this one and then override 24: many of the definitions that relate to assembler syntax. */ 25: 1.1.1.3 ! root 26: /* Sparc64 support has been added by trying to allow for a day when one ! 27: compiler can handle both v8 and v9. There are a few cases where this ! 28: isn't doable, but keep them to a minimum! Two macros are used to help out: ! 29: TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness. ! 30: SPARCV9 is defined when compiling for sparc64 only. ! 31: In places where it is possible to choose between the two at runtime, use ! 32: TARGET_V9. In places where it is currently not possible to select ! 33: between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a ! 34: minimum. No attempt is made to support both v8 and v9 in the v9 compiler. ! 35: ! 36: If a combination v8/v9 compiler is too slow, it should always be possible ! 37: to #define TARGET_V9 as 0 (and potentially other v9-only options), and ! 38: #undef SPARCV9. */ ! 39: ! 40: /* What architecture we're compiling for. This must coincide with the ! 41: `arch_type' attribute in the .md file. The names were chosen to avoid ! 42: potential misunderstandings with the various 32 bit flavors (v7, v8, etc.): ! 43: if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that ! 44: could be misleading and ARCH_NOTV9 sounds klunky. */ ! 45: enum arch_type { ARCH_32BIT, ARCH_64BIT }; ! 46: extern enum arch_type sparc_arch_type; ! 47: ! 48: /* Names to predefine in the preprocessor for this target machine. */ ! 49: ! 50: /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses ! 51: the right varags.h file when bootstrapping. */ ! 52: ! 53: #ifdef SPARCV9 ! 54: #define CPP_PREDEFINES \ ! 55: "-Dsparc -Dsun -Dunix -D__sparc_v9__ \ ! 56: -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" ! 57: #else ! 58: #define CPP_PREDEFINES \ ! 59: "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ ! 60: -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" ! 61: #endif ! 62: ! 63: #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}" 1.1 root 64: 65: /* Provide required defaults for linker -e and -d switches. */ 66: 67: #define LINK_SPEC \ 68: "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" 69: 70: /* Special flags to the Sun-4 assembler when using pipe for input. */ 71: 1.1.1.3 ! root 72: #define ASM_SPEC " %| %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}}" 1.1 root 73: 74: /* Define macros to distinguish architectures. */ 1.1.1.3 ! root 75: ! 76: #ifdef SPARCV9 ! 77: #define CPP_SPEC "\ ! 78: %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ ! 79: %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ ! 80: " ! 81: #else ! 82: #define CPP_SPEC "\ ! 83: %{msparclite:-D__sparclite__} \ ! 84: %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ ! 85: %{mv8:-D__sparc_v8__} \ ! 86: %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ ! 87: " ! 88: #endif 1.1 root 89: 90: /* Prevent error on `-sun4' and `-target sun4' options. */ 91: /* This used to translate -dalign to -malign, but that is no good 92: because it can't turn off the usual meaning of making debugging dumps. */ 93: 94: #define CC1_SPEC "%{sun4:} %{target:}" 95: 1.1.1.3 ! root 96: #ifdef SPARCV9 ! 97: #define PTRDIFF_TYPE "long long int" ! 98: #define SIZE_TYPE "long long unsigned int" ! 99: #else 1.1 root 100: #define PTRDIFF_TYPE "int" 101: /* In 2.4 it should work to delete this. 102: #define SIZE_TYPE "int" */ 1.1.1.3 ! root 103: #endif ! 104: ! 105: /* ??? This should be 32 bits for v9 but what can we do? */ 1.1 root 106: #define WCHAR_TYPE "short unsigned int" 107: #define WCHAR_TYPE_SIZE 16 1.1.1.3 ! root 108: #define MAX_WCHAR_TYPE_SIZE 16 1.1 root 109: 1.1.1.3 ! root 110: /* Show we can debug even without a frame pointer. */ ! 111: #define CAN_DEBUG_WITHOUT_FP 1.1 root 112: 113: /* To make profiling work with -f{pic,PIC}, we need to emit the profiling 114: code into the rtl. Also, if we are profiling, we cannot eliminate 115: the frame pointer (because the return address will get smashed). */ 116: 1.1.1.3 ! root 117: void sparc_override_options (); ! 118: 1.1 root 119: #define OVERRIDE_OPTIONS \ 1.1.1.3 ! root 120: do { \ ! 121: if (profile_flag || profile_block_flag) \ ! 122: { \ ! 123: if (flag_pic) \ ! 124: { \ ! 125: char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \ ! 126: warning ("%s and profiling conflict: disabling %s", \ ! 127: pic_string, pic_string); \ ! 128: flag_pic = 0; \ ! 129: } \ ! 130: flag_omit_frame_pointer = 0; \ ! 131: } \ ! 132: SUBTARGET_OVERRIDE_OPTIONS \ ! 133: sparc_override_options (); \ ! 134: } while (0) 1.1.1.2 root 135: 136: /* This is meant to be redefined in the host dependent files */ 137: #define SUBTARGET_OVERRIDE_OPTIONS 1.1 root 138: 139: /* These compiler options take an argument. We ignore -target for now. */ 140: 141: #define WORD_SWITCH_TAKES_ARG(STR) \ 142: (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ 143: || !strcmp (STR, "target") || !strcmp (STR, "assert")) 144: 145: /* Print subsidiary information on the compiler version in use. */ 146: 147: #define TARGET_VERSION fprintf (stderr, " (sparc)"); 148: 149: /* Generate DBX debugging information. */ 150: 151: #define DBX_DEBUGGING_INFO 1.1.1.3 ! root 152: 1.1 root 153: /* Run-time compilation parameters selecting different hardware subsets. */ 154: 155: extern int target_flags; 156: 157: /* Nonzero if we should generate code to use the fpu. */ 1.1.1.3 ! root 158: #define MASK_FPU 1 ! 159: #define TARGET_FPU (target_flags & MASK_FPU) 1.1 root 160: 161: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we 162: use fast return insns, but lose some generality. */ 1.1.1.3 ! root 163: #define MASK_EPILOGUE 2 ! 164: #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) 1.1 root 165: 166: /* Nonzero if we should assume that double pointers might be unaligned. 167: This can happen when linking gcc compiled code with other compilers, 168: because the ABI only guarantees 4 byte alignment. */ 1.1.1.3 ! root 169: #define MASK_UNALIGNED_DOUBLES 4 ! 170: #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) ! 171: ! 172: /* ??? Bits 0x18 are currently unused. */ ! 173: ! 174: /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */ ! 175: #define MASK_SUPERSPARC 0x20 ! 176: #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC) 1.1 root 177: 178: /* Nonzero means that we should generate code for a v8 sparc. */ 1.1.1.3 ! root 179: #define MASK_V8 0x40 ! 180: #define TARGET_V8 (target_flags & MASK_V8) 1.1 root 181: 1.1.1.2 root 182: /* Nonzero means that we should generate code for a sparclite. 183: This enables the sparclite specific instructions, but does not affect 184: whether FPU instructions are emitted. */ 1.1.1.3 ! root 185: #define MASK_SPARCLITE 0x80 ! 186: #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) 1.1 root 187: 188: /* Nonzero means that we should generate code using a flat register window 189: model, i.e. no save/restore instructions are generated, in the most 190: efficient manner. This code is not compatible with normal sparc code. */ 191: /* This is not a user selectable option yet, because it requires changes 192: that are not yet switchable via command line arguments. */ 1.1.1.3 ! root 193: /* ??? This flag is deprecated and may disappear at some point. */ ! 194: #define MASK_FRW 0x100 ! 195: #define TARGET_FRW (target_flags & MASK_FRW) 1.1 root 196: 197: /* Nonzero means that we should generate code using a flat register window 198: model, i.e. no save/restore instructions are generated, but which is 199: compatible with normal sparc code. This is the same as above, except 1.1.1.3 ! root 200: that the frame pointer is %i7 instead of %fp. */ ! 201: /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will ! 202: go away, but until that time only use this one when necessary. ! 203: -mflat sets both. */ ! 204: #define MASK_FLAT 0x200 ! 205: #define TARGET_FLAT (target_flags & MASK_FLAT) ! 206: ! 207: /* Nonzero means use the registers that the Sparc ABI reserves for ! 208: application software. This is the default for v8, but not v9. */ ! 209: #define MASK_APP_REGS 0x400 ! 210: #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) ! 211: ! 212: /* Option to select how quad word floating point is implemented. ! 213: When TARGET_HARD_QUAD is true, we use the hardware quad instructions. ! 214: Otherwise, we use the SPARC ABI quad library functions. */ ! 215: #define MASK_HARD_QUAD 0x800 ! 216: #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) ! 217: ! 218: /* Nonzero if we're compiling for 64 bit sparc. */ ! 219: #define MASK_V9 0x1000 ! 220: #define TARGET_V9 (target_flags & MASK_V9) ! 221: ! 222: /* Nonzero if ints are 64 bits. ! 223: This automatically implies longs are 64 bits too. ! 224: This option is for v9 only. */ ! 225: #define MASK_INT64 0x2000 ! 226: #define TARGET_INT64 (target_flags & MASK_INT64) ! 227: ! 228: /* Nonzero if longs are 64 bits. ! 229: This option is for v9 only. */ ! 230: #define MASK_LONG64 0x4000 ! 231: #define TARGET_LONG64 (target_flags & MASK_LONG64) ! 232: ! 233: /* Nonzero if pointers are 64 bits. ! 234: This is not a user selectable option, though it may be one day - ! 235: so it is used to determine pointer size instead of an architecture flag. */ ! 236: #define MASK_PTR64 0x8000 ! 237: #define TARGET_PTR64 (target_flags & MASK_PTR64) ! 238: ! 239: /* Nonzero if we are generating code to be tested in a 32 bit environment. ! 240: Hence, we assume the upper 32 bits of symbolic addresses are zero, and ! 241: avoid generating %uhi and %ulo terms. ! 242: Pointers are still 64 bits though! This option is for v9 only. */ ! 243: /* ??? This option is deprecated. Try to use -mmedlow. */ ! 244: #define MASK_ENV32 0x10000 ! 245: #define TARGET_ENV32 (target_flags & MASK_ENV32) ! 246: ! 247: /* Memory models. ! 248: Two memory models are supported: ! 249: TARGET_MEDLOW: 32 bit address space, top 32 bits = 0 ! 250: (pointers still 64 bits) ! 251: TARGET_MEDANY: 32 bit address space, data segment loaded anywhere ! 252: (use %g4 as offset). ! 253: TARGET_FULLANY: not supported yet. ! 254: These options are for v9 only. All mask values are nonzero so the v8 ! 255: compiler can assume this stuff won't interfere. */ ! 256: #define MASK_MEDLOW 0x20000 ! 257: #define MASK_MEDANY 0x40000 ! 258: #define MASK_FULLANY 0x60000 ! 259: #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) ! 260: #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) ! 261: #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) ! 262: #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) ! 263: ! 264: /* ??? There are hardcoded references to this reg in the .md file. */ ! 265: #define MEDANY_BASE_REG "%g4" ! 266: ! 267: /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by ! 268: adding 2047 to %sp. This option is for v9 only and is the default. */ ! 269: #define MASK_STACK_BIAS 0x80000 ! 270: #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) 1.1 root 271: 272: /* Macro to define tables used to set the flags. 273: This is a list in braces of pairs in braces, 274: each pair being { "NAME", VALUE } 275: where VALUE is the bits to set or minus the bits to clear. 276: An empty string NAME is used to identify the default VALUE. */ 277: 1.1.1.2 root 278: /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 1.1.1.3 ! root 279: The Fujitsu MB86934 is the recent sparclite chip, with an fpu. 1.1.1.2 root 280: We use -mf930 and -mf934 options to choose which. 281: ??? These should perhaps be -mcpu= options. */ 282: 1.1 root 283: #define TARGET_SWITCHES \ 1.1.1.3 ! root 284: { {"fpu", MASK_FPU}, \ ! 285: {"no-fpu", -MASK_FPU}, \ ! 286: {"hard-float", MASK_FPU}, \ ! 287: {"soft-float", -MASK_FPU}, \ ! 288: {"epilogue", MASK_EPILOGUE}, \ ! 289: {"no-epilogue", -MASK_EPILOGUE}, \ ! 290: {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ ! 291: {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ ! 292: {"supersparc", MASK_SUPERSPARC+MASK_V8}, \ ! 293: {"cypress", -MASK_SUPERSPARC-MASK_V8}, \ ! 294: {"v8", MASK_V8}, \ ! 295: {"no-v8", -MASK_V8}, \ ! 296: {"sparclite", MASK_SPARCLITE}, \ ! 297: {"no-sparclite", -MASK_SPARCLITE}, \ ! 298: {"f930", MASK_SPARCLITE}, \ ! 299: {"f930", -MASK_FPU}, \ ! 300: {"f934", MASK_SPARCLITE}, \ ! 301: {"flat", MASK_FRW+MASK_FLAT}, \ ! 302: {"no-flat", -(MASK_FRW+MASK_FLAT)}, \ ! 303: {"app-regs", MASK_APP_REGS}, \ ! 304: {"no-app-regs", -MASK_APP_REGS}, \ ! 305: {"hard-quad-float", MASK_HARD_QUAD}, \ ! 306: {"soft-quad-float", -MASK_HARD_QUAD}, \ ! 307: SUBTARGET_SWITCHES \ ! 308: V9_SWITCHES \ 1.1 root 309: { "", TARGET_DEFAULT}} 310: 1.1.1.3 ! root 311: #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) 1.1.1.2 root 312: 313: /* This is meant to be redefined in the host dependent files */ 314: #define SUBTARGET_SWITCHES 1.1 root 315: 1.1.1.3 ! root 316: /* ??? Until we support a combination v8/v9 compiler, the v9 specific options ! 317: are only defined for the v9 compiler. */ ! 318: #ifdef SPARCV9 ! 319: #define V9_SWITCHES \ ! 320: /* {"v9", MASK_V9}, */ \ ! 321: {"int64", MASK_INT64+MASK_LONG64}, \ ! 322: {"int32", -MASK_INT64}, \ ! 323: {"int32", MASK_LONG64}, \ ! 324: {"long64", -MASK_INT64}, \ ! 325: {"long64", MASK_LONG64}, \ ! 326: {"long32", -(MASK_INT64+MASK_LONG64)}, \ ! 327: /* {"ptr64", MASK_PTR64}, */ \ ! 328: /* {"ptr32", -MASK_PTR64}, */ \ ! 329: {"stack-bias", MASK_STACK_BIAS}, \ ! 330: {"no-stack-bias", -MASK_STACK_BIAS}, \ ! 331: {"medlow", -MASK_CODE_MODEL}, \ ! 332: {"medlow", MASK_MEDLOW}, \ ! 333: {"medany", -MASK_CODE_MODEL}, \ ! 334: {"medany", MASK_MEDANY}, ! 335: #else ! 336: #define V9_SWITCHES 1.1.1.2 root 337: #endif 1.1.1.3 ! root 338: ! 339: /* target machine storage layout */ 1.1.1.2 root 340: 341: /* Define for cross-compilation to a sparc target with no TFmode from a host 342: with a different float format (e.g. VAX). */ 343: #define REAL_ARITHMETIC 344: 1.1 root 345: /* Define this if most significant bit is lowest numbered 346: in instructions that operate on numbered bit-fields. */ 347: #define BITS_BIG_ENDIAN 1 348: 349: /* Define this if most significant byte of a word is the lowest numbered. */ 350: /* This is true on the SPARC. */ 351: #define BYTES_BIG_ENDIAN 1 352: 353: /* Define this if most significant word of a multiword number is the lowest 354: numbered. */ 355: /* Doubles are stored in memory with the high order word first. This 356: matters when cross-compiling. */ 357: #define WORDS_BIG_ENDIAN 1 358: 359: /* number of bits in an addressable storage unit */ 360: #define BITS_PER_UNIT 8 361: 362: /* Width in bits of a "word", which is the contents of a machine register. 363: Note that this is not necessarily the width of data type `int'; 364: if using 16-bit ints on a 68000, this would still be 32. 365: But on a machine with 16-bit registers, this would be 16. */ 1.1.1.3 ! root 366: #define BITS_PER_WORD (TARGET_V9 ? 64 : 32) ! 367: #define MAX_BITS_PER_WORD 64 1.1 root 368: 369: /* Width of a word, in units (bytes). */ 1.1.1.3 ! root 370: #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4) ! 371: #define MAX_UNITS_PER_WORD 8 ! 372: ! 373: /* Now define the sizes of the C data types. */ ! 374: ! 375: #define SHORT_TYPE_SIZE 16 ! 376: #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) ! 377: #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) ! 378: #define LONG_LONG_TYPE_SIZE 64 ! 379: #define FLOAT_TYPE_SIZE 32 ! 380: #define DOUBLE_TYPE_SIZE 64 ! 381: ! 382: #define MAX_INT_TYPE_SIZE 64 ! 383: #define MAX_LONG_TYPE_SIZE 64 ! 384: ! 385: #ifdef SPARCV9 ! 386: /* ??? This does not work in SunOS 4.x, so it is not enabled here. ! 387: Instead, it is enabled in sol2.h, because it does work under Solaris. */ ! 388: /* Define for support of TFmode long double and REAL_ARITHMETIC. ! 389: Sparc ABI says that long double is 4 words. */ ! 390: #define LONG_DOUBLE_TYPE_SIZE 128 ! 391: #endif 1.1 root 392: 393: /* Width in bits of a pointer. 394: See also the macro `Pmode' defined below. */ 1.1.1.3 ! root 395: #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 1.1 root 396: 397: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1.1.1.3 ! root 398: #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 399: 400: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 1.1.1.3 ! root 401: #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64) 1.1 root 402: 403: /* ALIGN FRAMES on double word boundaries */ 404: 1.1.1.3 ! root 405: #define SPARC_STACK_ALIGN(LOC) \ ! 406: (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 1.1 root 407: 408: /* Allocation boundary (in *bits*) for the code of a function. */ 409: #define FUNCTION_BOUNDARY 32 410: 411: /* Alignment of field after `int : 0' in a structure. */ 1.1.1.3 ! root 412: /* ??? Should this be based on TARGET_INT64? */ ! 413: #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 414: 415: /* Every structure's size must be a multiple of this. */ 416: #define STRUCTURE_SIZE_BOUNDARY 8 417: 418: /* A bitfield declared as `int' forces `int' alignment for the struct. */ 419: #define PCC_BITFIELD_TYPE_MATTERS 1 420: 421: /* No data type wants to be aligned rounder than this. */ 1.1.1.3 ! root 422: #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64) 1.1 root 423: 424: /* The best alignment to use in cases where we have a choice. */ 425: #define FASTEST_ALIGNMENT 64 426: 427: /* Make strings word-aligned so strcpy from constants will be faster. */ 428: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 429: ((TREE_CODE (EXP) == STRING_CST \ 430: && (ALIGN) < FASTEST_ALIGNMENT) \ 431: ? FASTEST_ALIGNMENT : (ALIGN)) 432: 433: /* Make arrays of chars word-aligned for the same reasons. */ 434: #define DATA_ALIGNMENT(TYPE, ALIGN) \ 435: (TREE_CODE (TYPE) == ARRAY_TYPE \ 436: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 437: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 438: 439: /* Set this nonzero if move instructions will actually fail to work 440: when given unaligned data. */ 441: #define STRICT_ALIGNMENT 1 442: 443: /* Things that must be doubleword aligned cannot go in the text section, 444: because the linker fails to align the text section enough! 1.1.1.3 ! root 445: Put them in the data section. This macro is only used in this file. */ 1.1 root 446: #define MAX_TEXT_ALIGN 32 447: 1.1.1.3 ! root 448: /* This is defined differently for v9 in a cover file. */ 1.1 root 449: #define SELECT_SECTION(T,RELOC) \ 450: { \ 451: if (TREE_CODE (T) == VAR_DECL) \ 452: { \ 453: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ 1.1.1.3 ! root 454: && DECL_INITIAL (T) \ ! 455: && (DECL_INITIAL (T) == error_mark_node \ ! 456: || TREE_CONSTANT (DECL_INITIAL (T))) \ 1.1 root 457: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ 458: && ! (flag_pic && (RELOC))) \ 459: text_section (); \ 460: else \ 461: data_section (); \ 462: } \ 463: else if (TREE_CODE (T) == CONSTRUCTOR) \ 464: { \ 465: if (flag_pic != 0 && (RELOC) != 0) \ 466: data_section (); \ 467: } \ 468: else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \ 469: { \ 470: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ 471: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \ 472: data_section (); \ 473: else \ 474: text_section (); \ 475: } \ 476: } 477: 478: /* Use text section for a constant 479: unless we need more alignment than that offers. */ 1.1.1.3 ! root 480: /* This is defined differently for v9 in a cover file. */ 1.1 root 481: #define SELECT_RTX_SECTION(MODE, X) \ 482: { \ 483: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ 484: && ! (flag_pic && symbolic_operand (X))) \ 485: text_section (); \ 486: else \ 487: data_section (); \ 488: } 489: 490: /* Standard register usage. */ 491: 492: /* Number of actual hardware registers. 493: The hardware registers are assigned numbers for the compiler 494: from 0 to just below FIRST_PSEUDO_REGISTER. 495: All registers that the compiler knows about must be given numbers, 496: even those that are not normally considered general registers. 497: 1.1.1.3 ! root 498: SPARC has 32 integer registers and 32 floating point registers. ! 499: 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not ! 500: accessible. We still account for them to simplify register computations ! 501: (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so ! 502: 32+32+32+4 == 100. ! 503: Register 0 is used as the integer condition code register. */ 1.1 root 504: 1.1.1.3 ! root 505: #ifdef SPARCV9 ! 506: #define FIRST_PSEUDO_REGISTER 100 ! 507: #else 1.1 root 508: #define FIRST_PSEUDO_REGISTER 64 1.1.1.3 ! root 509: #endif 1.1 root 510: 511: /* 1 for registers that have pervasive standard uses 512: and are not available for the register allocator. 513: g0 is used for the condition code and not to represent %g0, which is 514: hardwired to 0, so reg 0 is *not* fixed. 1.1.1.3 ! root 515: On non-v9 systems: ! 516: g1 is free to use as temporary. ! 517: g2-g4 are reserved for applications. Gcc normally uses them as ! 518: temporaries, but this can be disabled via the -mno-app-regs option. ! 519: g5 through g7 are reserved for the operating system. ! 520: On v9 systems: ! 521: g1 and g5 are free to use as temporaries. ! 522: g2-g4 are reserved for applications (the compiler will not normally use ! 523: them, but they can be used as temporaries with -mapp-regs). ! 524: g6-g7 are reserved for the operating system. ! 525: ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must ! 526: currently be a fixed register until this pattern is rewritten. ! 527: Register 1 is also used when restoring call-preserved registers in large ! 528: stack frames. */ ! 529: ! 530: #ifdef SPARCV9 ! 531: #define FIXED_REGISTERS \ ! 532: {0, 1, 1, 1, 1, 0, 1, 1, \ ! 533: 0, 0, 0, 0, 0, 0, 1, 0, \ ! 534: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 535: 0, 0, 0, 0, 0, 0, 1, 1, \ ! 536: \ ! 537: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 538: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 539: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 540: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 541: \ ! 542: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 543: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 544: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 545: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 546: \ ! 547: 0, 0, 0, 0} ! 548: #else 1.1 root 549: #define FIXED_REGISTERS \ 550: {0, 0, 0, 0, 0, 1, 1, 1, \ 551: 0, 0, 0, 0, 0, 0, 1, 0, \ 552: 0, 0, 0, 0, 0, 0, 0, 0, \ 553: 0, 0, 0, 0, 0, 0, 1, 1, \ 554: \ 555: 0, 0, 0, 0, 0, 0, 0, 0, \ 556: 0, 0, 0, 0, 0, 0, 0, 0, \ 557: 0, 0, 0, 0, 0, 0, 0, 0, \ 558: 0, 0, 0, 0, 0, 0, 0, 0} 1.1.1.3 ! root 559: #endif 1.1 root 560: 561: /* 1 for registers not available across function calls. 562: These must include the FIXED_REGISTERS and also any 563: registers that can be used without being saved. 564: The latter must include the registers where values are returned 565: and the register where structure-value addresses are passed. 566: Aside from that, you can include as many other registers as you like. */ 1.1.1.3 ! root 567: ! 568: #ifdef SPARCV9 ! 569: #define CALL_USED_REGISTERS \ ! 570: {1, 1, 1, 1, 1, 1, 1, 1, \ ! 571: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 572: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 573: 0, 0, 0, 0, 0, 0, 1, 1, \ ! 574: \ ! 575: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 576: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 577: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 578: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 579: \ ! 580: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 581: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 582: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 583: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 584: \ ! 585: 1, 1, 1, 1} ! 586: #else 1.1 root 587: #define CALL_USED_REGISTERS \ 588: {1, 1, 1, 1, 1, 1, 1, 1, \ 589: 1, 1, 1, 1, 1, 1, 1, 1, \ 590: 0, 0, 0, 0, 0, 0, 0, 0, \ 591: 0, 0, 0, 0, 0, 0, 1, 1, \ 592: \ 593: 1, 1, 1, 1, 1, 1, 1, 1, \ 594: 1, 1, 1, 1, 1, 1, 1, 1, \ 595: 1, 1, 1, 1, 1, 1, 1, 1, \ 596: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 ! root 597: #endif 1.1 root 598: 599: /* If !TARGET_FPU, then make the fp registers fixed so that they won't 1.1.1.3 ! root 600: be allocated. On v9, also make the fp cc regs fixed. */ 1.1 root 601: 602: #define CONDITIONAL_REGISTER_USAGE \ 603: do \ 604: { \ 605: if (! TARGET_FPU) \ 606: { \ 607: int regno; \ 1.1.1.3 ! root 608: for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1.1 root 609: fixed_regs[regno] = 1; \ 610: } \ 1.1.1.3 ! root 611: if (! TARGET_APP_REGS) \ ! 612: { \ ! 613: fixed_regs[2] = 1; \ ! 614: fixed_regs[3] = 1; \ ! 615: fixed_regs[4] = 1; \ ! 616: } \ ! 617: else \ ! 618: { \ ! 619: fixed_regs[2] = 0; \ ! 620: fixed_regs[3] = 0; \ ! 621: fixed_regs[4] = TARGET_MEDANY != 0; \ ! 622: } \ ! 623: if (TARGET_FLAT) \ ! 624: { \ ! 625: /* Let the compiler believe the frame pointer is still \ ! 626: %fp, but output it as %i7. */ \ ! 627: fixed_regs[31] = 1; \ ! 628: reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ ! 629: /* ??? This is a hack to disable leaf functions. */ \ ! 630: global_regs[7] = 1; \ ! 631: } \ ! 632: if (profile_block_flag) \ ! 633: { \ ! 634: /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ ! 635: uses them. */ \ ! 636: fixed_regs[1] = 1; \ ! 637: fixed_regs[2] = 1; \ ! 638: } \ 1.1 root 639: } \ 640: while (0) 641: 642: /* Return number of consecutive hard regs needed starting at reg REGNO 643: to hold something of mode MODE. 644: This is ordinarily the length in words of a value of mode MODE 645: but can be less for certain modes in special long registers. 646: 647: On SPARC, ordinary registers hold 32 bits worth; 648: this means both integer and floating point registers. 1.1.1.3 ! root 649: On v9, integer regs hold 64 bits worth; floating point regs hold ! 650: 32 bits worth (this includes the new fp regs as even the odd ones are ! 651: included in the hard register count). */ ! 652: ! 653: #define HARD_REGNO_NREGS(REGNO, MODE) \ ! 654: (TARGET_V9 \ ! 655: ? ((REGNO) < 32 \ ! 656: ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ ! 657: : (GET_MODE_SIZE (MODE) + 3) / 4) \ ! 658: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1.1 root 659: 660: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1.1.1.3 ! root 661: See sparc.c for how we initialize this. */ ! 662: extern int *hard_regno_mode_classes; ! 663: extern int sparc_mode_class[]; 1.1 root 664: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1.1.1.3 ! root 665: ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 1.1 root 666: 667: /* Value is 1 if it is a good idea to tie two pseudo registers 668: when one has mode MODE1 and one has mode MODE2. 669: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1.1.1.3 ! root 670: for any hard reg, then this must be 0 for correct output. ! 671: ! 672: For V9: SFmode can't be combined with other float modes, because they can't ! 673: be allocated to the %d registers. Also, DFmode won't fit in odd %f ! 674: registers, but SFmode will. */ 1.1 root 675: #define MODES_TIEABLE_P(MODE1, MODE2) \ 1.1.1.3 ! root 676: ((MODE1) == (MODE2) \ ! 677: || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ ! 678: && (! TARGET_V9 \ ! 679: || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ ! 680: || (MODE1 != SFmode && MODE2 != SFmode))))) 1.1 root 681: 682: /* Specify the registers used for certain standard purposes. 683: The values of these macros are register numbers. */ 684: 685: /* SPARC pc isn't overloaded on a register that the compiler knows about. */ 686: /* #define PC_REGNUM */ 687: 688: /* Register to use for pushing function arguments. */ 689: #define STACK_POINTER_REGNUM 14 690: 1.1.1.3 ! root 691: /* Actual top-of-stack address is 92/136 greater than the contents of the ! 692: stack pointer register for !v9/v9. That is: ! 693: - !v9: 64 bytes for the in and local registers, 4 bytes for structure return ! 694: address, and 24 bytes for the 6 register parameters. ! 695: - v9: 128 bytes for the in and local registers + 8 bytes reserved. */ 1.1 root 696: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) 697: 1.1.1.3 ! root 698: /* The stack bias (amount by which the hardware register is offset by). */ ! 699: #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) ! 700: 1.1 root 701: /* Base register for access to local variables of the function. */ 702: #define FRAME_POINTER_REGNUM 30 703: 704: #if 0 705: /* Register that is used for the return address. */ 706: #define RETURN_ADDR_REGNUM 15 707: #endif 708: 709: /* Value should be nonzero if functions must have frame pointers. 710: Zero means the frame pointer need not be set up (and parms 711: may be accessed via the stack pointer) in functions that seem suitable. 712: This is computed in `reload', in reload1.c. 1.1.1.3 ! root 713: Used in flow.c, global.c, and reload1.c. 1.1 root 714: 1.1.1.3 ! root 715: Being a non-leaf function does not mean a frame pointer is needed in the ! 716: flat window model. However, the debugger won't be able to backtrace through ! 717: us with out it. */ 1.1 root 718: #define FRAME_POINTER_REQUIRED \ 1.1.1.3 ! root 719: (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs \ ! 720: || !leaf_function_p ()) \ ! 721: : ! (leaf_function_p () && only_leaf_regs_used ())) 1.1 root 722: 723: /* C statement to store the difference between the frame pointer 724: and the stack pointer values immediately after the function prologue. 725: 726: Note, we always pretend that this is a leaf function because if 727: it's not, there's no point in trying to eliminate the 728: frame pointer. If it is a leaf function, we guessed right! */ 729: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 1.1.1.3 ! root 730: ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \ 1.1 root 731: : compute_frame_size (get_frame_size (), 1))) 732: 733: /* Base register for access to arguments of the function. */ 1.1.1.3 ! root 734: #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 1.1 root 735: 1.1.1.2 root 736: /* Register in which static-chain is passed to a function. This must 1.1.1.3 ! root 737: not be a register used by the prologue. ! 738: ??? v9: Since %g2 is reserved but %g5 is available, perhaps use %g5. */ 1.1.1.2 root 739: #define STATIC_CHAIN_REGNUM 2 1.1 root 740: 741: /* Register which holds offset table for position-independent 742: data references. */ 743: 744: #define PIC_OFFSET_TABLE_REGNUM 23 745: 746: #define INITIALIZE_PIC initialize_pic () 747: #define FINALIZE_PIC finalize_pic () 748: 749: /* Sparc ABI says that quad-precision floats and all structures are returned 1.1.1.3 ! root 750: in memory. ! 751: For v9, all aggregates are returned in memory. */ ! 752: #define RETURN_IN_MEMORY(TYPE) \ ! 753: (TYPE_MODE (TYPE) == BLKmode \ ! 754: || (! TARGET_V9 && (TYPE_MODE (TYPE) == TFmode \ ! 755: || TYPE_MODE (TYPE) == TCmode))) 1.1 root 756: 757: /* Functions which return large structures get the address 758: to place the wanted value at offset 64 from the frame. 1.1.1.3 ! root 759: Must reserve 64 bytes for the in and local registers. ! 760: v9: Functions which return large structures get the address to place the ! 761: wanted value from an invisible first argument. */ 1.1 root 762: /* Used only in other #defines in this file. */ 763: #define STRUCT_VALUE_OFFSET 64 764: 765: #define STRUCT_VALUE \ 1.1.1.3 ! root 766: (TARGET_V9 \ ! 767: ? 0 \ ! 768: : gen_rtx (MEM, Pmode, \ ! 769: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ ! 770: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 771: #define STRUCT_VALUE_INCOMING \ 1.1.1.3 ! root 772: (TARGET_V9 \ ! 773: ? 0 \ ! 774: : gen_rtx (MEM, Pmode, \ ! 775: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ ! 776: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 777: 778: /* Define the classes of registers for register constraints in the 779: machine description. Also define ranges of constants. 780: 781: One of the classes must always be named ALL_REGS and include all hard regs. 782: If there is more than one class, another class must be named NO_REGS 783: and contain no registers. 784: 785: The name GENERAL_REGS must be the name of a class (or an alias for 786: another name such as ALL_REGS). This is the class of registers 787: that is allowed by "g" or "r" in a register constraint. 788: Also, registers outside this class are allocated only when 789: instructions express preferences for them. 790: 791: The classes must be numbered in nondecreasing order; that is, 792: a larger-numbered class must never be contained completely 793: in a smaller-numbered class. 794: 795: For any two classes, it is very desirable that there be another 796: class that represents their union. */ 797: 1.1.1.3 ! root 798: /* The SPARC has two kinds of registers, general and floating point. 1.1 root 799: 1.1.1.3 ! root 800: For v9 we must distinguish between the upper and lower floating point ! 801: registers because the upper ones can't hold SFmode values. ! 802: HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) ! 803: satisfying a group need for a class will also satisfy a single need for ! 804: that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp ! 805: regs. ! 806: ! 807: It is important that one class contains all the general and all the standard ! 808: fp regs. Otherwise find_reg() won't properly allocate int regs for moves, ! 809: because reg_class_record() will bias the selection in favor of fp regs, ! 810: because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, ! 811: because FP_REGS > GENERAL_REGS. ! 812: ! 813: It is also important that one class contain all the general and all the ! 814: fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS ! 815: but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause ! 816: allocate_reload_reg() to bypass it causing an abort because the compiler ! 817: thinks it doesn't have a spill reg when in fact it does. ! 818: ! 819: v9 also has 4 floating point condition code registers. Since we don't ! 820: have a class that is the union of FPCC_REGS with either of the others, ! 821: it is important that it appear first. Otherwise the compiler will die ! 822: trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its ! 823: constraints. */ ! 824: ! 825: #ifdef SPARCV9 ! 826: enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, ! 827: GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ! 828: ALL_REGS, LIM_REG_CLASSES }; ! 829: #else 1.1 root 830: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; 1.1.1.3 ! root 831: #endif 1.1 root 832: 833: #define N_REG_CLASSES (int) LIM_REG_CLASSES 834: 835: /* Give names of register classes as strings for dump file. */ 836: 1.1.1.3 ! root 837: #ifdef SPARCV9 ! 838: #define REG_CLASS_NAMES \ ! 839: { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \ ! 840: "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" } ! 841: #else 1.1 root 842: #define REG_CLASS_NAMES \ 1.1.1.3 ! root 843: { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } ! 844: #endif 1.1 root 845: 846: /* Define which registers fit in which classes. 847: This is an initializer for a vector of HARD_REG_SET 848: of length N_REG_CLASSES. */ 849: 1.1.1.3 ! root 850: #ifdef SPARCV9 ! 851: #define REG_CLASS_CONTENTS \ ! 852: {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \ ! 853: {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \ ! 854: {-2, -1, -1, 0xf}} ! 855: #else 1.1 root 856: #if 0 && defined (__GNUC__) 857: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} 858: #else 859: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} 860: #endif 1.1.1.3 ! root 861: #endif 1.1 root 862: 863: /* The same information, inverted: 864: Return the class number of the smallest class containing 865: reg number REGNO. This could be a conditional expression 866: or could index an array. */ 867: 1.1.1.3 ! root 868: #ifdef SPARCV9 ! 869: #define REGNO_REG_CLASS(REGNO) \ ! 870: ((REGNO) == 0 ? NO_REGS \ ! 871: : (REGNO) < 32 ? GENERAL_REGS \ ! 872: : (REGNO) < 64 ? FP_REGS \ ! 873: : (REGNO) < 96 ? EXTRA_FP_REGS \ ! 874: : FPCC_REGS) ! 875: #else 1.1 root 876: #define REGNO_REG_CLASS(REGNO) \ 877: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) 1.1.1.3 ! root 878: #endif 1.1 root 879: 1.1.1.3 ! root 880: /* This is the order in which to allocate registers normally. 1.1 root 881: 882: We put %f0/%f1 last among the float registers, so as to make it more 1.1.1.2 root 883: likely that a pseudo-register which dies in the float return register 1.1 root 884: will get allocated to the float return register, thus saving a move 1.1.1.3 ! root 885: instruction at the end of the function. ! 886: ! 887: On v9, the float registers are ordered a little "funny" because some ! 888: of them (%f16-%f47) are call-preserved. */ ! 889: #ifdef SPARCV9 ! 890: #define REG_ALLOC_ORDER \ ! 891: { 8, 9, 10, 11, 12, 13, \ ! 892: 15, 16, 17, 18, 19, 20, 21, 22, \ ! 893: 23, 24, 25, 26, 27, 28, 29, 31, \ ! 894: 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ ! 895: 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ ! 896: 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ ! 897: 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ ! 898: 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ ! 899: 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ ! 900: 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ ! 901: 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ ! 902: 32, 33, /* %f0,%f1 */ \ ! 903: 96, 97, 98, 99, /* %fcc0-3 */ \ ! 904: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30} ! 905: #else 1.1 root 906: #define REG_ALLOC_ORDER \ 907: { 8, 9, 10, 11, 12, 13, 2, 3, \ 908: 15, 16, 17, 18, 19, 20, 21, 22, \ 909: 23, 24, 25, 26, 27, 28, 29, 31, \ 910: 34, 35, 36, 37, 38, 39, \ 911: 40, 41, 42, 43, 44, 45, 46, 47, \ 912: 48, 49, 50, 51, 52, 53, 54, 55, \ 913: 56, 57, 58, 59, 60, 61, 62, 63, \ 914: 32, 33, \ 915: 1, 4, 5, 6, 7, 0, 14, 30} 1.1.1.3 ! root 916: #endif 1.1 root 917: 918: /* This is the order in which to allocate registers for 919: leaf functions. If all registers can fit in the "i" registers, 1.1.1.3 ! root 920: then we have the possibility of having a leaf function. ! 921: v9: The floating point registers are ordered a little "funny" because some ! 922: of them (%f16-%f47) are call-preserved. */ ! 923: #ifdef SPARCV9 ! 924: #define REG_LEAF_ALLOC_ORDER \ ! 925: { 24, 25, 26, 27, 28, 29, \ ! 926: 15, 8, 9, 10, 11, 12, 13, \ ! 927: 16, 17, 18, 19, 20, 21, 22, 23, \ ! 928: 34, 35, 36, 37, 38, 39, \ ! 929: 40, 41, 42, 43, 44, 45, 46, 47, \ ! 930: 80, 81, 82, 83, 84, 85, 86, 87, \ ! 931: 88, 89, 90, 91, 92, 93, 94, 95, \ ! 932: 48, 49, 50, 51, 52, 53, 54, 55, \ ! 933: 56, 57, 58, 59, 60, 61, 62, 63, \ ! 934: 64, 65, 66, 67, 68, 69, 70, 71, \ ! 935: 72, 73, 74, 75, 76, 77, 78, 79, \ ! 936: 32, 33, \ ! 937: 96, 97, 98, 99, \ ! 938: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31} ! 939: #else 1.1 root 940: #define REG_LEAF_ALLOC_ORDER \ 941: { 2, 3, 24, 25, 26, 27, 28, 29, \ 942: 15, 8, 9, 10, 11, 12, 13, \ 943: 16, 17, 18, 19, 20, 21, 22, 23, \ 944: 34, 35, 36, 37, 38, 39, \ 945: 40, 41, 42, 43, 44, 45, 46, 47, \ 946: 48, 49, 50, 51, 52, 53, 54, 55, \ 947: 56, 57, 58, 59, 60, 61, 62, 63, \ 948: 32, 33, \ 949: 1, 4, 5, 6, 7, 0, 14, 30, 31} 1.1.1.3 ! root 950: #endif 1.1 root 951: 952: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 953: 1.1.1.3 ! root 954: /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when ! 955: -mflat is used. Function only_leaf_regs_used will return 0 if a global ! 956: register is used and is not permitted in a leaf function. We make %g7 ! 957: a global reg if -mflat and voila. Since %g7 is a system register and is ! 958: fixed it won't be used by gcc anyway. */ ! 959: #ifdef SPARCV9 1.1 root 960: #define LEAF_REGISTERS \ 1.1.1.3 ! root 961: { 1, 1, 1, 1, 1, 1, 1, 0, \ ! 962: 0, 0, 0, 0, 0, 0, 1, 0, \ ! 963: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 964: 1, 1, 1, 1, 1, 1, 0, 1, \ ! 965: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 966: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 967: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 968: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 969: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 970: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 971: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 972: 1, 1, 1, 1, 1, 1, 1, 1, \ ! 973: 1, 1, 1, 1} ! 974: #else ! 975: #define LEAF_REGISTERS \ ! 976: { 1, 1, 1, 1, 1, 1, 1, 0, \ 1.1 root 977: 0, 0, 0, 0, 0, 0, 1, 0, \ 978: 0, 0, 0, 0, 0, 0, 0, 0, \ 979: 1, 1, 1, 1, 1, 1, 0, 1, \ 980: 1, 1, 1, 1, 1, 1, 1, 1, \ 981: 1, 1, 1, 1, 1, 1, 1, 1, \ 982: 1, 1, 1, 1, 1, 1, 1, 1, \ 983: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 ! root 984: #endif 1.1 root 985: 986: extern char leaf_reg_remap[]; 987: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 988: 989: /* The class value for index registers, and the one for base regs. */ 990: #define INDEX_REG_CLASS GENERAL_REGS 991: #define BASE_REG_CLASS GENERAL_REGS 992: 1.1.1.3 ! root 993: /* Local macro to handle the two v9 classes of FP regs. */ ! 994: #ifdef SPARCV9 ! 995: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) ! 996: #else ! 997: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS) ! 998: #endif ! 999: 1.1 root 1000: /* Get reg_class from a letter such as appears in the machine description. */ 1001: 1.1.1.3 ! root 1002: #ifdef SPARCV9 1.1 root 1003: #define REG_CLASS_FROM_LETTER(C) \ 1.1.1.3 ! root 1004: ((C) == 'f' ? FP_REGS \ ! 1005: : (C) == 'e' ? EXTRA_FP_REGS \ ! 1006: : (C) == 'c' ? FPCC_REGS \ ! 1007: : NO_REGS) ! 1008: #else ! 1009: /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for ! 1010: v8 and v9. */ ! 1011: #define REG_CLASS_FROM_LETTER(C) \ ! 1012: ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS) ! 1013: #endif 1.1 root 1014: 1015: /* The letters I, J, K, L and M in a register constraint string 1016: can be used to stand for particular ranges of immediate operands. 1017: This macro defines what the ranges are. 1018: C is the letter, and VALUE is a constant value. 1019: Return 1 if VALUE is in the range specified by C. 1020: 1021: For SPARC, `I' is used for the range of constants an insn 1022: can actually contain. 1023: `J' is used for the range which is just zero (since that is R0). 1024: `K' is used for constants which can be loaded with a single sethi insn. */ 1025: 1026: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) 1027: 1028: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1029: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ 1030: : (C) == 'J' ? (VALUE) == 0 \ 1031: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ 1032: : 0) 1033: 1034: /* Similar, but for floating constants, and defining letters G and H. 1035: Here VALUE is the CONST_DOUBLE rtx itself. */ 1036: 1037: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1.1.1.2 root 1038: ((C) == 'G' ? fp_zero_operand (VALUE) \ 1.1 root 1039: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1040: : 0) 1041: 1042: /* Given an rtx X being reloaded into a reg required to be 1043: in class CLASS, return the class of reg to actually use. 1044: In general this is just CLASS; but on some machines 1045: in some cases it is preferable to use a more restrictive class. */ 1046: /* We can't load constants into FP registers. We can't load any FP constant 1047: if an 'E' constraint fails to match it. */ 1048: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1049: (CONSTANT_P (X) \ 1.1.1.3 ! root 1050: && (FP_REG_CLASS_P (CLASS) \ 1.1 root 1051: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1052: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ 1053: || HOST_BITS_PER_INT != BITS_PER_WORD))) \ 1054: ? NO_REGS : (CLASS)) 1055: 1056: /* Return the register class of a scratch register needed to load IN into 1057: a register of class CLASS in MODE. 1058: 1059: On the SPARC, when PIC, we need a temporary when loading some addresses 1060: into a register. 1061: 1062: Also, we need a temporary when loading/storing a HImode/QImode value 1063: between memory and the FPU registers. This can happen when combine puts 1064: a paradoxical subreg in a float/fix conversion insn. */ 1065: 1066: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 ! root 1067: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ ! 1068: && (GET_CODE (IN) == MEM \ ! 1069: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ ! 1070: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1071: 1072: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 ! root 1073: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ ! 1074: && (GET_CODE (IN) == MEM \ ! 1075: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ ! 1076: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1077: 1078: /* On SPARC it is not possible to directly move data between 1079: GENERAL_REGS and FP_REGS. */ 1.1.1.3 ! root 1080: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ ! 1081: (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1.1 root 1082: 1.1.1.3 ! root 1083: /* Return the stack location to use for secondary memory needed reloads. ! 1084: We want to use the reserved location just below the frame pointer. ! 1085: However, we must ensure that there is a frame, so use assign_stack_local ! 1086: if the frame size is zero. */ 1.1 root 1087: #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1.1.1.3 ! root 1088: (get_frame_size () == 0 \ ! 1089: ? assign_stack_local (mode, GET_MODE_SIZE (mode), 0) \ ! 1090: : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ ! 1091: GEN_INT (STARTING_FRAME_OFFSET)))) ! 1092: ! 1093: /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9 ! 1094: because the movsi and movsf patterns don't handle r/f moves. ! 1095: For v8 we copy the default definition. */ ! 1096: #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ ! 1097: (TARGET_V9 \ ! 1098: ? (GET_MODE_BITSIZE (mode) < 32 \ ! 1099: ? mode_for_size (32, GET_MODE_CLASS (mode), 0) \ ! 1100: : MODE) \ ! 1101: : (GET_MODE_BITSIZE (mode) < BITS_PER_WORD \ ! 1102: ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0) \ ! 1103: : MODE)) 1.1 root 1104: 1105: /* Return the maximum number of consecutive registers 1106: needed to represent mode MODE in a register of class CLASS. */ 1107: /* On SPARC, this is the size of MODE in words. */ 1108: #define CLASS_MAX_NREGS(CLASS, MODE) \ 1.1.1.3 ! root 1109: (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ ! 1110: : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1 root 1111: 1112: /* Stack layout; function entry, exit and calling. */ 1113: 1114: /* Define the number of register that can hold parameters. 1.1.1.3 ! root 1115: These two macros are used only in other macro definitions below. ! 1116: MODE is the mode of the argument. ! 1117: !v9: All args are passed in %o0-%o5. ! 1118: v9: Non-float args are passed in %o0-5 and float args are passed in ! 1119: %f0-%f15. */ ! 1120: #define NPARM_REGS(MODE) \ ! 1121: (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6) 1.1 root 1122: 1123: /* Define this if pushing a word on the stack 1124: makes the stack pointer a smaller address. */ 1125: #define STACK_GROWS_DOWNWARD 1126: 1127: /* Define this if the nominal address of the stack frame 1128: is at the high-address end of the local variables; 1129: that is, each additional local variable allocated 1130: goes at a more negative offset in the frame. */ 1131: #define FRAME_GROWS_DOWNWARD 1132: 1133: /* Offset within stack frame to start allocating local variables at. 1134: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1135: first local allocated. Otherwise, it is the offset to the BEGINNING 1136: of the first local allocated. */ 1.1.1.3 ! root 1137: /* This allows space for one TFmode floating point value. */ ! 1138: #define STARTING_FRAME_OFFSET \ ! 1139: (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \ ! 1140: : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1.1 root 1141: 1142: /* If we generate an insn to push BYTES bytes, 1143: this says how many the stack pointer really advances by. 1144: On SPARC, don't define this because there are no push insns. */ 1145: /* #define PUSH_ROUNDING(BYTES) */ 1146: 1147: /* Offset of first parameter from the argument pointer register value. 1.1.1.3 ! root 1148: !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg ! 1149: even if this function isn't going to use it. ! 1150: v9: This is 128 for the ins and locals, plus a reserved space of 8. */ ! 1151: #define FIRST_PARM_OFFSET(FNDECL) \ ! 1152: (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \ ! 1153: : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) 1.1 root 1154: 1155: /* When a parameter is passed in a register, stack space is still 1156: allocated for it. */ 1.1.1.3 ! root 1157: #ifndef SPARCV9 ! 1158: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD) ! 1159: #endif 1.1 root 1160: 1161: /* Keep the stack pointer constant throughout the function. 1162: This is both an optimization and a necessity: longjmp 1163: doesn't behave itself when the stack pointer moves within 1164: the function! */ 1165: #define ACCUMULATE_OUTGOING_ARGS 1166: 1167: /* Value is the number of bytes of arguments automatically 1168: popped when returning from a subroutine call. 1169: FUNTYPE is the data type of the function (as a tree), 1170: or for a library call it is an identifier node for the subroutine name. 1171: SIZE is the number of bytes of arguments passed on the stack. */ 1172: 1173: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 1174: 1175: /* Some subroutine macros specific to this machine. 1176: When !TARGET_FPU, put float return values in the general registers, 1177: since we don't have any fp registers. */ 1178: #define BASE_RETURN_VALUE_REG(MODE) \ 1.1.1.3 ! root 1179: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ ! 1180: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) 1.1 root 1181: #define BASE_OUTGOING_VALUE_REG(MODE) \ 1.1.1.3 ! root 1182: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ ! 1183: : TARGET_FRW ? 8 : 24) \ ! 1184: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ ! 1185: : (TARGET_FRW ? 8 : 24))) ! 1186: #define BASE_PASSING_ARG_REG(MODE) \ ! 1187: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ ! 1188: : (8)) ! 1189: #define BASE_INCOMING_ARG_REG(MODE) \ ! 1190: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ ! 1191: : TARGET_FRW ? 8 : 24) \ ! 1192: : (TARGET_FRW ? 8 : 24)) 1.1 root 1193: 1194: /* Define this macro if the target machine has "register windows". This 1195: C expression returns the register number as seen by the called function 1196: corresponding to register number OUT as seen by the calling function. 1197: Return OUT if register number OUT is not an outbound register. */ 1198: 1199: #define INCOMING_REGNO(OUT) \ 1200: ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1201: 1202: /* Define this macro if the target machine has "register windows". This 1203: C expression returns the register number as seen by the calling function 1204: corresponding to register number IN as seen by the called function. 1205: Return IN if register number IN is not an inbound register. */ 1206: 1207: #define OUTGOING_REGNO(IN) \ 1208: ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1209: 1210: /* Define how to find the value returned by a function. 1211: VALTYPE is the data type of the value (as a tree). 1212: If the precise function being called is known, FUNC is its FUNCTION_DECL; 1213: otherwise, FUNC is 0. */ 1214: 1215: /* On SPARC the value is found in the first "output" register. */ 1216: 1217: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1218: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 1219: 1220: /* But the called function leaves it in the first "input" register. */ 1221: 1222: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1223: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) 1224: 1225: /* Define how to find the value returned by a library function 1226: assuming the value has mode MODE. */ 1227: 1228: #define LIBCALL_VALUE(MODE) \ 1229: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) 1230: 1231: /* 1 if N is a possible register number for a function value 1232: as seen by the caller. 1233: On SPARC, the first "output" reg is used for integer values, 1234: and the first floating point register is used for floating point values. */ 1235: 1236: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1237: 1.1.1.2 root 1238: /* Define the size of space to allocate for the return value of an 1239: untyped_call. */ 1240: 1241: #define APPLY_RESULT_SIZE 16 1242: 1.1 root 1243: /* 1 if N is a possible register number for function argument passing. 1.1.1.3 ! root 1244: On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */ 1.1 root 1245: 1.1.1.3 ! root 1246: #define FUNCTION_ARG_REGNO_P(N) \ ! 1247: (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \ ! 1248: : ((N) < 14 && (N) > 7)) 1.1 root 1249: 1250: /* Define a data type for recording info about an argument list 1251: during the scan of that argument list. This data type should 1252: hold all necessary information about the function itself 1253: and about the args processed so far, enough to enable macros 1254: such as FUNCTION_ARG to determine where the next arg should go. 1255: 1.1.1.3 ! root 1256: On SPARC (!v9), this is a single integer, which is a number of words 1.1 root 1257: of arguments scanned so far (including the invisible argument, 1258: if any, which holds the structure-value-address). 1.1.1.3 ! root 1259: Thus 7 or more means all following args should go on the stack. 1.1 root 1260: 1.1.1.3 ! root 1261: For v9, we record how many of each type has been passed. Different ! 1262: types get passed differently. ! 1263: ! 1264: - Float args are passed in %f0-15, after which they go to the stack ! 1265: where floats and doubles are passed 8 byte aligned and long doubles ! 1266: are passed 16 byte aligned. ! 1267: - All aggregates are passed by reference. The callee copies ! 1268: the structure if necessary, except if stdarg/varargs and the struct ! 1269: matches the ellipse in which case the caller makes a copy. ! 1270: - Any non-float argument might be split between memory and reg %o5. ! 1271: ??? I don't think this can ever happen now that structs are no ! 1272: longer passed in regs. ! 1273: ! 1274: For v9 return values: ! 1275: ! 1276: - For all aggregates, the caller allocates space for the return value, ! 1277: and passes the pointer as an implicit first argument, which is ! 1278: allocated like all other arguments. ! 1279: - The unimp instruction stuff for structure returns is gone. */ ! 1280: ! 1281: #ifdef SPARCV9 ! 1282: enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 }; ! 1283: struct sparc_args { ! 1284: int arg_count[2]; /* must be int! (for __builtin_args_info) */ ! 1285: }; ! 1286: #define CUMULATIVE_ARGS struct sparc_args ! 1287: ! 1288: /* Return index into CUMULATIVE_ARGS. */ ! 1289: ! 1290: #define GET_SPARC_ARG_CLASS(MODE) \ ! 1291: (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT) ! 1292: ! 1293: /* Round a register number up to a proper boundary for an arg of mode MODE. ! 1294: This macro is only used in this file. ! 1295: ! 1296: The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */ ! 1297: ! 1298: #define ROUND_REG(CUM, MODE) \ ! 1299: (GET_MODE_CLASS (MODE) != MODE_FLOAT \ ! 1300: ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ ! 1301: : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ ! 1302: + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \ ! 1303: & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4)) ! 1304: ! 1305: #define ROUND_ADVANCE(SIZE) \ ! 1306: (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) ! 1307: ! 1308: #else /* ! SPARCV9 */ 1.1 root 1309: #define CUMULATIVE_ARGS int 1310: 1.1.1.3 ! root 1311: #define ROUND_REG(CUM, MODE) (CUM) ! 1312: 1.1 root 1313: #define ROUND_ADVANCE(SIZE) \ 1314: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1.1.3 ! root 1315: #endif /* ! SPARCV9 */ 1.1 root 1316: 1317: /* Initialize a variable CUM of type CUMULATIVE_ARGS 1318: for a call to a function whose data type is FNTYPE. 1319: For a library call, FNTYPE is 0. 1320: 1321: On SPARC, the offset always starts at 0: the first parm reg is always 1322: the same reg. */ 1323: 1.1.1.3 ! root 1324: #ifdef SPARCV9 ! 1325: extern int sparc_arg_count,sparc_n_named_args; ! 1326: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ! 1327: do { \ ! 1328: (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \ ! 1329: (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \ ! 1330: sparc_arg_count = 0; \ ! 1331: sparc_n_named_args = \ ! 1332: ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \ ! 1333: ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \ ! 1334: + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \ ! 1335: || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \ ! 1336: /* Can't tell, treat 'em all as named. */ \ ! 1337: : 10000); \ ! 1338: } while (0) ! 1339: #else 1.1 root 1340: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) 1.1.1.3 ! root 1341: #endif 1.1 root 1342: 1343: /* Update the data in CUM to advance over an argument 1344: of mode MODE and data type TYPE. 1345: (TYPE is null for libcalls where that information may not be available.) */ 1346: 1.1.1.3 ! root 1347: #ifdef SPARCV9 ! 1348: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ! 1349: do { \ ! 1350: (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \ ! 1351: ROUND_REG ((CUM), (MODE)) \ ! 1352: + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ ! 1353: ? GET_MODE_SIZE (MODE) / 4 \ ! 1354: : ROUND_ADVANCE ((MODE) == BLKmode \ ! 1355: ? GET_MODE_SIZE (Pmode) \ ! 1356: : GET_MODE_SIZE (MODE))); \ ! 1357: sparc_arg_count++; \ ! 1358: } while (0) ! 1359: #else 1.1 root 1360: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1361: ((CUM) += ((MODE) != BLKmode \ 1362: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 1363: : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) 1.1.1.3 ! root 1364: #endif ! 1365: ! 1366: /* Return boolean indicating arg of mode MODE will be passed in a reg. ! 1367: This macro is only used in this file. */ ! 1368: ! 1369: #ifdef SPARCV9 ! 1370: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ ! 1371: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ ! 1372: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ ! 1373: && ((TYPE)==0 || (MODE) != BLKmode)) ! 1374: #else ! 1375: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ ! 1376: ((CUM) < NPARM_REGS (SImode) \ ! 1377: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ ! 1378: && ((TYPE)==0 || (MODE) != BLKmode \ ! 1379: || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0))) ! 1380: #endif 1.1 root 1381: 1382: /* Determine where to put an argument to a function. 1383: Value is zero to push the argument on the stack, 1384: or a hard register in which to store the argument. 1385: 1386: MODE is the argument's machine mode. 1387: TYPE is the data type of the argument (as a tree). 1388: This is null for libcalls where that information may 1389: not be available. 1390: CUM is a variable of type CUMULATIVE_ARGS which gives info about 1391: the preceding args and about the function being called. 1392: NAMED is nonzero if this argument is a named parameter 1393: (otherwise it is an extra parameter matching an ellipsis). */ 1394: 1395: /* On SPARC the first six args are normally in registers 1396: and the rest are pushed. Any arg that starts within the first 6 words 1.1.1.3 ! root 1397: is at least partially passed in a register unless its data type forbids. ! 1398: For v9, the first 6 int args are passed in regs and the first N ! 1399: float args are passed in regs (where N is such that %f0-15 are filled). ! 1400: The rest are pushed. Any arg that starts within the first 6 words 1.1 root 1401: is at least partially passed in a register unless its data type forbids. */ 1402: 1403: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 ! root 1404: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ ! 1405: ? gen_rtx (REG, (MODE), \ ! 1406: (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ ! 1407: : 0) 1.1 root 1408: 1409: /* Define where a function finds its arguments. 1410: This is different from FUNCTION_ARG because of register windows. */ 1411: 1412: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 ! root 1413: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ ! 1414: ? gen_rtx (REG, (MODE), \ ! 1415: (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ ! 1416: : 0) 1.1 root 1417: 1418: /* For an arg passed partly in registers and partly in memory, 1419: this is the number of registers used. 1420: For args passed entirely in registers or entirely in memory, zero. 1421: Any arg that starts in the first 6 regs but won't entirely fit in them 1.1.1.3 ! root 1422: needs partial registers on the Sparc (!v9). On v9, there are no arguments ! 1423: that are passed partially in registers (??? complex values?). */ 1.1 root 1424: 1.1.1.3 ! root 1425: #ifndef SPARCV9 1.1 root 1426: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 ! root 1427: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ ! 1428: && ((CUM) + ((MODE) == BLKmode \ ! 1429: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ ! 1430: : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\ ! 1431: ? (NPARM_REGS (SImode) - (CUM)) \ 1.1 root 1432: : 0) 1.1.1.3 ! root 1433: #endif 1.1 root 1434: 1435: /* The SPARC ABI stipulates passing struct arguments (of any size) and 1.1.1.3 ! root 1436: (!v9) quad-precision floats by invisible reference. ! 1437: For Pascal, also pass arrays by reference. */ 1.1 root 1438: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1439: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ 1.1.1.3 ! root 1440: || TREE_CODE (TYPE) == UNION_TYPE \ ! 1441: || TREE_CODE (TYPE) == ARRAY_TYPE)) \ ! 1442: || (!TARGET_V9 && MODE == TFmode)) ! 1443: ! 1444: /* A C expression that indicates when it is the called function's ! 1445: responsibility to make copies of arguments passed by reference. ! 1446: If the callee can determine that the argument won't be modified, it can ! 1447: avoid the copy. */ ! 1448: /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't ! 1449: include the last named argument so we keep track of the args ourselves. */ ! 1450: ! 1451: #ifdef SPARCV9 ! 1452: #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ ! 1453: (sparc_arg_count < sparc_n_named_args) ! 1454: #endif ! 1455: ! 1456: /* Initialize data used by insn expanders. This is called from ! 1457: init_emit, once for each function, before code is generated. ! 1458: For v9, clear the temp slot used by float/int DImode conversions. ! 1459: ??? There is the 16 bytes at [%fp-16], however we'd like to delete this ! 1460: space at some point. ! 1461: ??? Use assign_stack_temp? */ ! 1462: ! 1463: extern void sparc64_init_expanders (); ! 1464: extern struct rtx_def *sparc64_fpconv_stack_temp (); ! 1465: #ifdef SPARCV9 ! 1466: #define INIT_EXPANDERS sparc64_init_expanders () ! 1467: #endif 1.1 root 1468: 1469: /* Define the information needed to generate branch and scc insns. This is 1470: stored from the compare operation. Note that we can't use "rtx" here 1471: since it hasn't been defined! */ 1472: 1473: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; 1474: 1475: /* Define the function that build the compare insn for scc and bcc. */ 1476: 1477: extern struct rtx_def *gen_compare_reg (); 1.1.1.3 ! root 1478: ! 1479: /* This function handles all v9 scc insns */ ! 1480: ! 1481: extern int gen_v9_scc (); ! 1482: ! 1483: /* ??? This is a hack until conditional move support is complete. */ ! 1484: #define HAVE_conditional_move (TARGET_V9) 1.1 root 1485: 1486: /* Generate the special assembly code needed to tell the assembler whatever 1487: it might need to know about the return value of a function. 1488: 1489: For Sparc assemblers, we need to output a .proc pseudo-op which conveys 1490: information to the assembler relating to peephole optimization (done in 1491: the assembler). */ 1492: 1493: #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1494: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) 1495: 1496: /* Output the label for a function definition. */ 1497: 1498: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1499: do { \ 1500: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1501: ASM_OUTPUT_LABEL (FILE, NAME); \ 1502: } while (0) 1503: 1504: /* This macro generates the assembly code for function entry. 1505: FILE is a stdio stream to output the code to. 1506: SIZE is an int: how many units of temporary storage to allocate. 1507: Refer to the array `regs_ever_live' to determine which registers 1508: to save; `regs_ever_live[I]' is nonzero if register number I 1509: is ever used in the function. This macro is responsible for 1510: knowing which registers should not be saved even if used. */ 1511: 1512: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block 1513: of memory. If any fpu reg is used in the function, we allocate 1514: such a block here, at the bottom of the frame, just in case it's needed. 1515: 1516: If this function is a leaf procedure, then we may choose not 1517: to do a "save" insn. The decision about whether or not 1518: to do this is made in regclass.c. */ 1519: 1.1.1.3 ! root 1520: extern int leaf_function; 1.1 root 1521: #define FUNCTION_PROLOGUE(FILE, SIZE) \ 1.1.1.3 ! root 1522: (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \ 1.1 root 1523: : output_function_prologue (FILE, SIZE, leaf_function)) 1524: 1525: /* Output assembler code to FILE to increment profiler label # LABELNO 1526: for profiling a function entry. */ 1527: 1528: #define FUNCTION_PROFILER(FILE, LABELNO) \ 1529: do { \ 1530: fputs ("\tsethi %hi(", (FILE)); \ 1531: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1.1.1.3 ! root 1532: fputs ("),%o0\n", (FILE)); \ ! 1533: if (TARGET_MEDANY) \ ! 1534: fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \ ! 1535: MEDANY_BASE_REG); \ ! 1536: fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \ 1.1 root 1537: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1538: fputs ("),%o0,%o0\n", (FILE)); \ 1539: } while (0) 1540: 1541: /* Output assembler code to FILE to initialize this source file's 1542: basic block profiling info, if that has not already been done. */ 1543: 1544: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ 1.1.1.3 ! root 1545: do { \ ! 1546: if (TARGET_MEDANY) \ ! 1547: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ ! 1548: MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \ ! 1549: else \ ! 1550: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ ! 1551: (LABELNO), (LABELNO)); \ ! 1552: } while (0) 1.1 root 1553: 1554: /* Output assembler code to FILE to increment the entry-count for 1555: the BLOCKNO'th basic block in this source file. */ 1556: 1557: #define BLOCK_PROFILER(FILE, BLOCKNO) \ 1.1.1.3 ! root 1558: { \ ! 1559: int blockn = (BLOCKNO); \ ! 1560: if (TARGET_MEDANY) \ ! 1561: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ ! 1562: 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ ! 1563: else \ ! 1564: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ ! 1565: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ ! 1566: 4 * blockn, 4 * blockn, 4 * blockn); \ 1.1 root 1567: } 1568: 1569: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1570: the stack pointer does not matter. The value is tested only in 1571: functions that have frame pointers. 1572: No definition is equivalent to always zero. */ 1573: 1574: extern int current_function_calls_alloca; 1575: extern int current_function_outgoing_args_size; 1576: 1577: #define EXIT_IGNORE_STACK \ 1578: (get_frame_size () != 0 \ 1579: || current_function_calls_alloca || current_function_outgoing_args_size) 1580: 1581: /* This macro generates the assembly code for function exit, 1582: on machines that need it. If FUNCTION_EPILOGUE is not defined 1583: then individual return instructions are generated for each 1584: return statement. Args are same as for FUNCTION_PROLOGUE. 1585: 1586: The function epilogue should not depend on the current stack pointer! 1587: It should use the frame pointer only. This is mandatory because 1588: of alloca; we also take advantage of it to omit stack adjustments 1589: before returning. */ 1590: 1591: /* This declaration is needed due to traditional/ANSI 1592: incompatibilities which cannot be #ifdefed away 1593: because they occur inside of macros. Sigh. */ 1594: extern union tree_node *current_function_decl; 1595: 1596: #define FUNCTION_EPILOGUE(FILE, SIZE) \ 1.1.1.3 ! root 1597: (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \ 1.1 root 1598: : output_function_epilogue (FILE, SIZE, leaf_function)) 1599: 1600: #define DELAY_SLOTS_FOR_EPILOGUE \ 1.1.1.3 ! root 1601: (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1) 1.1 root 1602: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ 1.1.1.3 ! root 1603: (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ 1.1 root 1604: : eligible_for_epilogue_delay (trial, slots_filled)) 1.1.1.2 root 1605: 1.1 root 1606: /* Output assembler code for a block containing the constant parts 1607: of a trampoline, leaving space for the variable parts. */ 1608: 1609: /* On the sparc, the trampoline contains five instructions: 1.1.1.2 root 1610: sethi #TOP_OF_FUNCTION,%g1 1611: or #BOTTOM_OF_FUNCTION,%g1,%g1 1612: sethi #TOP_OF_STATIC,%g2 1613: jmp g1 1614: or #BOTTOM_OF_STATIC,%g2,%g2 */ 1.1 root 1615: #define TRAMPOLINE_TEMPLATE(FILE) \ 1616: { \ 1617: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1618: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1619: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1.1.1.2 root 1620: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \ 1.1 root 1621: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1622: } 1623: 1624: /* Length in units of the trampoline for entering a nested function. */ 1625: 1626: #define TRAMPOLINE_SIZE 20 1627: 1628: /* Emit RTL insns to initialize the variable parts of a trampoline. 1629: FNADDR is an RTX for the address of the function's pure code. 1.1.1.3 ! root 1630: CXT is an RTX for the static chain value for the function. */ 1.1.1.2 root 1631: 1.1.1.3 ! root 1632: void sparc_initialize_trampoline (); ! 1633: void sparc64_initialize_trampoline (); ! 1634: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ ! 1635: do { \ ! 1636: if (TARGET_V9) \ ! 1637: sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ ! 1638: else \ ! 1639: sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \ ! 1640: } while (0) 1.1.1.2 root 1641: 1.1 root 1642: /* Generate necessary RTL for __builtin_saveregs(). 1643: ARGLIST is the argument list; see expr.c. */ 1644: extern struct rtx_def *sparc_builtin_saveregs (); 1645: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) 1646: 1647: /* Generate RTL to flush the register windows so as to make arbitrary frames 1648: available. */ 1649: #define SETUP_FRAME_ADDRESSES() \ 1650: emit_insn (gen_flush_register_windows ()) 1651: 1652: /* Given an rtx for the address of a frame, 1653: return an rtx for the address of the word in the frame 1.1.1.3 ! root 1654: that holds the dynamic chain--the previous frame's address. ! 1655: ??? -mflat support? */ 1.1 root 1656: #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1.1.1.3 ! root 1657: gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD)) 1.1 root 1658: 1659: /* The return address isn't on the stack, it is in a register, so we can't 1660: access it from the current frame pointer. We can access it from the 1661: previous frame pointer though by reading a value from the register window 1662: save area. */ 1663: #define RETURN_ADDR_IN_PREVIOUS_FRAME 1664: 1665: /* The current return address is in %i7. The return address of anything 1666: farther back is in the register window save area at [%fp+60]. */ 1667: /* ??? This ignores the fact that the actual return address is +8 for normal 1668: returns, and +12 for structure returns. */ 1669: #define RETURN_ADDR_RTX(count, frame) \ 1670: ((count == -1) \ 1671: ? gen_rtx (REG, Pmode, 31) \ 1672: : copy_to_reg (gen_rtx (MEM, Pmode, \ 1.1.1.3 ! root 1673: memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))) 1.1 root 1674: 1675: /* Addressing modes, and classification of registers for them. */ 1676: 1677: /* #define HAVE_POST_INCREMENT */ 1678: /* #define HAVE_POST_DECREMENT */ 1679: 1680: /* #define HAVE_PRE_DECREMENT */ 1681: /* #define HAVE_PRE_INCREMENT */ 1682: 1683: /* Macros to check register numbers against specific register classes. */ 1684: 1685: /* These assume that REGNO is a hard or pseudo reg number. 1686: They give nonzero only if REGNO is a hard reg of the suitable class 1687: or a pseudo reg currently allocated to a suitable hard reg. 1688: Since they use reg_renumber, they are safe only once reg_renumber 1689: has been allocated, which happens in local-alloc.c. */ 1690: 1691: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1692: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1693: #define REGNO_OK_FOR_BASE_P(REGNO) \ 1694: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1695: #define REGNO_OK_FOR_FP_P(REGNO) \ 1.1.1.3 ! root 1696: (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \ ! 1697: || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32))) ! 1698: #define REGNO_OK_FOR_CCFP_P(REGNO) \ ! 1699: (TARGET_V9 \ ! 1700: && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4)) 1.1 root 1701: 1702: /* Now macros that check whether X is a register and also, 1703: strictly, whether it is in a specified class. 1704: 1705: These macros are specific to the SPARC, and may be used only 1706: in code for printing assembler insns and in conditions for 1707: define_optimization. */ 1708: 1709: /* 1 if X is an fp register. */ 1710: 1711: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1712: 1713: /* Maximum number of registers that can appear in a valid memory address. */ 1714: 1715: #define MAX_REGS_PER_ADDRESS 2 1716: 1.1.1.2 root 1717: /* Recognize any constant value that is a valid address. 1718: When PIC, we do not accept an address that would require a scratch reg 1719: to load into a register. */ 1.1 root 1720: 1721: #define CONSTANT_ADDRESS_P(X) \ 1722: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1.1.1.2 root 1723: || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 1724: || (GET_CODE (X) == CONST \ 1725: && ! (flag_pic && pic_address_needs_scratch (X)))) 1726: 1727: /* Define this, so that when PIC, reload won't try to reload invalid 1728: addresses which require two reload registers. */ 1729: 1730: #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) 1.1 root 1731: 1732: /* Nonzero if the constant value X is a legitimate general operand. 1733: Anything can be made to work except floating point constants. */ 1734: 1735: #define LEGITIMATE_CONSTANT_P(X) \ 1736: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) 1737: 1738: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1739: and check its validity for a certain class. 1740: We have two alternate definitions for each of them. 1741: The usual definition accepts all pseudo regs; the other rejects 1742: them unless they have been allocated suitable hard regs. 1743: The symbol REG_OK_STRICT causes the latter definition to be used. 1744: 1745: Most source files want to accept pseudo regs in the hope that 1746: they will get allocated to the class that the insn wants them to be in. 1747: Source files for reload pass need to be strict. 1748: After reload, it makes no difference, since pseudo regs have 1749: been eliminated by then. */ 1750: 1751: /* Optional extra constraints for this machine. Borrowed from romp.h. 1752: 1753: For the SPARC, `Q' means that this is a memory operand but not a 1754: symbolic memory operand. Note that an unassigned pseudo register 1755: is such a memory operand. Needed because reload will generate 1756: these things in insns and then not re-recognize the insns, causing 1757: constrain_operands to fail. 1758: 1.1.1.3 ! root 1759: `S' handles constraints for calls. ??? So where is it? */ 1.1 root 1760: 1761: #ifndef REG_OK_STRICT 1762: 1763: /* Nonzero if X is a hard reg that can be used as an index 1764: or if it is a pseudo reg. */ 1.1.1.3 ! root 1765: #define REG_OK_FOR_INDEX_P(X) \ ! 1766: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) 1.1 root 1767: /* Nonzero if X is a hard reg that can be used as a base reg 1768: or if it is a pseudo reg. */ 1.1.1.3 ! root 1769: #define REG_OK_FOR_BASE_P(X) \ ! 1770: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) ! 1771: ! 1772: /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ 1.1 root 1773: 1774: #define EXTRA_CONSTRAINT(OP, C) \ 1775: ((C) == 'Q' \ 1776: ? ((GET_CODE (OP) == MEM \ 1.1.1.3 ! root 1777: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ 1.1 root 1778: && ! symbolic_memory_operand (OP, VOIDmode)) \ 1779: || (reload_in_progress && GET_CODE (OP) == REG \ 1780: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ 1.1.1.3 ! root 1781: : ! TARGET_V9 && (C) == 'T' \ 1.1 root 1782: ? (mem_aligned_8 (OP)) \ 1.1.1.3 ! root 1783: : ! TARGET_V9 && (C) == 'U' \ 1.1 root 1784: ? (register_ok_for_ldd (OP)) \ 1785: : 0) 1786: 1787: #else 1788: 1789: /* Nonzero if X is a hard reg that can be used as an index. */ 1790: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1791: /* Nonzero if X is a hard reg that can be used as a base reg. */ 1792: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1793: 1794: #define EXTRA_CONSTRAINT(OP, C) \ 1795: ((C) == 'Q' \ 1796: ? (GET_CODE (OP) == REG \ 1797: ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ 1798: && reg_renumber[REGNO (OP)] < 0) \ 1799: : GET_CODE (OP) == MEM) \ 1.1.1.3 ! root 1800: : ! TARGET_V9 && (C) == 'T' \ 1.1.1.2 root 1801: ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ 1.1.1.3 ! root 1802: : ! TARGET_V9 && (C) == 'U' \ 1.1.1.2 root 1803: ? (GET_CODE (OP) == REG \ 1804: && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ 1805: || reg_renumber[REGNO (OP)] > 0) \ 1806: && register_ok_for_ldd (OP)) : 0) 1.1 root 1807: #endif 1808: 1809: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1810: that is a valid memory address for an instruction. 1811: The MODE argument is the machine mode for the MEM expression 1812: that wants to use this address. 1813: 1814: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1815: ordinarily. This changes a bit when generating PIC. 1816: 1817: If you change this, execute "rm explow.o recog.o reload.o". */ 1818: 1819: #define RTX_OK_FOR_BASE_P(X) \ 1820: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1821: || (GET_CODE (X) == SUBREG \ 1822: && GET_CODE (SUBREG_REG (X)) == REG \ 1823: && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1824: 1825: #define RTX_OK_FOR_INDEX_P(X) \ 1826: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1827: || (GET_CODE (X) == SUBREG \ 1828: && GET_CODE (SUBREG_REG (X)) == REG \ 1829: && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1830: 1831: #define RTX_OK_FOR_OFFSET_P(X) \ 1832: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) 1833: 1834: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1835: { if (RTX_OK_FOR_BASE_P (X)) \ 1836: goto ADDR; \ 1837: else if (GET_CODE (X) == PLUS) \ 1838: { \ 1839: register rtx op0 = XEXP (X, 0); \ 1840: register rtx op1 = XEXP (X, 1); \ 1841: if (flag_pic && op0 == pic_offset_table_rtx) \ 1842: { \ 1843: if (RTX_OK_FOR_BASE_P (op1)) \ 1844: goto ADDR; \ 1845: else if (flag_pic == 1 \ 1846: && GET_CODE (op1) != REG \ 1847: && GET_CODE (op1) != LO_SUM \ 1.1.1.2 root 1848: && GET_CODE (op1) != MEM \ 1849: && (GET_CODE (op1) != CONST_INT \ 1850: || SMALL_INT (op1))) \ 1.1 root 1851: goto ADDR; \ 1852: } \ 1853: else if (RTX_OK_FOR_BASE_P (op0)) \ 1854: { \ 1855: if (RTX_OK_FOR_INDEX_P (op1) \ 1856: || RTX_OK_FOR_OFFSET_P (op1)) \ 1857: goto ADDR; \ 1858: } \ 1859: else if (RTX_OK_FOR_BASE_P (op1)) \ 1860: { \ 1861: if (RTX_OK_FOR_INDEX_P (op0) \ 1862: || RTX_OK_FOR_OFFSET_P (op0)) \ 1863: goto ADDR; \ 1864: } \ 1865: } \ 1866: else if (GET_CODE (X) == LO_SUM) \ 1867: { \ 1868: register rtx op0 = XEXP (X, 0); \ 1869: register rtx op1 = XEXP (X, 1); \ 1870: if (RTX_OK_FOR_BASE_P (op0) \ 1.1.1.3 ! root 1871: && CONSTANT_P (op1) \ ! 1872: /* We can't allow TFmode, because an offset \ ! 1873: greater than or equal to the alignment (8) \ ! 1874: may cause the LO_SUM to overflow. */ \ ! 1875: && MODE != TFmode) \ 1.1 root 1876: goto ADDR; \ 1877: } \ 1878: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ 1879: goto ADDR; \ 1880: } 1881: 1882: /* Try machine-dependent ways of modifying an illegitimate address 1883: to be legitimate. If we find one, return the new, valid address. 1884: This macro is used in only one place: `memory_address' in explow.c. 1885: 1886: OLDX is the address as it was before break_out_memory_refs was called. 1887: In some cases it is useful to look at this to decide what needs to be done. 1888: 1889: MODE and WIN are passed so that this macro can use 1890: GO_IF_LEGITIMATE_ADDRESS. 1891: 1892: It is always safe for this macro to do nothing. It exists to recognize 1893: opportunities to optimize the output. */ 1894: 1895: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 1896: extern struct rtx_def *legitimize_pic_address (); 1897: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1898: { rtx sparc_x = (X); \ 1899: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ 1900: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1901: force_operand (XEXP (X, 0), NULL_RTX)); \ 1902: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ 1903: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1904: force_operand (XEXP (X, 1), NULL_RTX)); \ 1905: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ 1906: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ 1907: XEXP (X, 1)); \ 1908: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ 1909: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1910: force_operand (XEXP (X, 1), NULL_RTX)); \ 1911: if (sparc_x != (X) && memory_address_p (MODE, X)) \ 1912: goto WIN; \ 1.1.1.2 root 1913: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ 1.1 root 1914: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ 1915: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1916: copy_to_mode_reg (Pmode, XEXP (X, 1))); \ 1917: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ 1918: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1919: copy_to_mode_reg (Pmode, XEXP (X, 0))); \ 1920: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 1921: || GET_CODE (X) == LABEL_REF) \ 1922: (X) = gen_rtx (LO_SUM, Pmode, \ 1923: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ 1924: if (memory_address_p (MODE, X)) \ 1925: goto WIN; } 1926: 1927: /* Go to LABEL if ADDR (a legitimate address expression) 1928: has an effect that depends on the machine mode it is used for. 1929: On the SPARC this is never true. */ 1930: 1931: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) 1.1.1.3 ! root 1932: ! 1933: /* If we are referencing a function make the SYMBOL_REF special. ! 1934: In the Medium/Anywhere code model, %g4 points to the data segment so we ! 1935: must not add it to function addresses. */ ! 1936: ! 1937: #define ENCODE_SECTION_INFO(DECL) \ ! 1938: do { \ ! 1939: if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ ! 1940: SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ ! 1941: } while (0) 1.1 root 1942: 1943: /* Specify the machine mode that this machine uses 1944: for the index in the tablejump instruction. */ 1.1.1.3 ! root 1945: #define CASE_VECTOR_MODE Pmode 1.1 root 1946: 1947: /* Define this if the tablejump instruction expects the table 1948: to contain offsets from the address of the table. 1949: Do not define this if the table should contain absolute addresses. */ 1950: /* #define CASE_VECTOR_PC_RELATIVE */ 1951: 1952: /* Specify the tree operation to be used to convert reals to integers. */ 1953: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1954: 1955: /* This is the kind of divide that is easiest to do in the general case. */ 1956: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1957: 1958: /* Define this as 1 if `char' should by default be signed; else as 0. */ 1959: #define DEFAULT_SIGNED_CHAR 1 1960: 1961: /* Max number of bytes we can move from memory to memory 1962: in one reasonably fast instruction. */ 1963: #define MOVE_MAX 8 1964: 1965: #if 0 /* Sun 4 has matherr, so this is no good. */ 1966: /* This is the value of the error code EDOM for this machine, 1967: used by the sqrt instruction. */ 1968: #define TARGET_EDOM 33 1969: 1970: /* This is how to refer to the variable errno. */ 1971: #define GEN_ERRNO_RTX \ 1972: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) 1973: #endif /* 0 */ 1974: 1.1.1.2 root 1975: /* Define if operations between registers always perform the operation 1976: on the full register even if a narrower mode is specified. */ 1977: #define WORD_REGISTER_OPERATIONS 1978: 1979: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1980: will either zero-extend or sign-extend. The value of this macro should 1981: be the code that says which one of the two operations is implicitly 1982: done, NIL if none. */ 1983: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1.1 root 1984: 1985: /* Nonzero if access to memory by bytes is slow and undesirable. 1986: For RISC chips, it means that access to memory by bytes is no 1987: better than access by words when possible, so grab a whole word 1988: and maybe make use of that. */ 1989: #define SLOW_BYTE_ACCESS 1 1990: 1991: /* We assume that the store-condition-codes instructions store 0 for false 1992: and some other value for true. This is the value stored for true. */ 1993: 1994: #define STORE_FLAG_VALUE 1 1995: 1996: /* When a prototype says `char' or `short', really pass an `int'. */ 1997: #define PROMOTE_PROTOTYPES 1998: 1.1.1.2 root 1999: /* Define this to be nonzero if shift instructions ignore all but the low-order 2000: few bits. */ 2001: #define SHIFT_COUNT_TRUNCATED 1 1.1 root 2002: 2003: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2004: is done just by pretending it is already truncated. */ 2005: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2006: 2007: /* Specify the machine mode that pointers have. 2008: After generation of rtl, the compiler makes no further distinction 2009: between pointers and any other objects of this machine mode. */ 1.1.1.3 ! root 2010: #define Pmode (TARGET_PTR64 ? DImode : SImode) 1.1 root 2011: 2012: /* Generate calls to memcpy, memcmp and memset. */ 2013: #define TARGET_MEM_FUNCTIONS 2014: 2015: /* Add any extra modes needed to represent the condition code. 2016: 2017: On the Sparc, we have a "no-overflow" mode which is used when an add or 2018: subtract insn is used to set the condition code. Different branches are 2019: used in this case for some operations. 2020: 2021: We also have two modes to indicate that the relevant condition code is 2022: in the floating-point condition code register. One for comparisons which 2023: will generate an exception if the result is unordered (CCFPEmode) and 2024: one for comparisons which will never trap (CCFPmode). This really should 1.1.1.3 ! root 2025: be a separate register, but we don't want to go to 65 registers. ! 2026: ! 2027: CCXmode and CCX_NOOVmode are only used by v9. */ ! 2028: ! 2029: #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode 1.1 root 2030: 2031: /* Define the names for the modes specified above. */ 1.1.1.3 ! root 2032: ! 2033: #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" 1.1 root 2034: 2035: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2036: return the mode to be used for the comparison. For floating-point, 2037: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a 1.1.1.2 root 2038: PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2039: processing is needed. */ 1.1 root 2040: #define SELECT_CC_MODE(OP,X,Y) \ 2041: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1.1.1.2 root 2042: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ 2043: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 2044: || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ 1.1.1.3 ! root 2045: ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ ! 2046: : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode))) ! 2047: ! 2048: /* Return non-zero if SELECT_CC_MODE will never return MODE for a ! 2049: floating point inequality comparison. */ ! 2050: ! 2051: #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 1.1 root 2052: 2053: /* A function address in a call instruction 2054: is a byte address (for indexing purposes) 2055: so give the MEM rtx a byte's mode. */ 2056: #define FUNCTION_MODE SImode 2057: 2058: /* Define this if addresses of constant functions 2059: shouldn't be put through pseudo regs where they can be cse'd. 2060: Desirable on machines where ordinary constants are expensive 2061: but a CALL with constant address is cheap. */ 2062: #define NO_FUNCTION_CSE 2063: 2064: /* alloca should avoid clobbering the old register save area. */ 2065: #define SETJMP_VIA_SAVE_AREA 2066: 2067: /* Define subroutines to call to handle multiply and divide. 2068: Use the subroutines that Sun's library provides. 2069: The `*' prevents an underscore from being prepended by the compiler. */ 2070: 2071: #define DIVSI3_LIBCALL "*.div" 2072: #define UDIVSI3_LIBCALL "*.udiv" 2073: #define MODSI3_LIBCALL "*.rem" 2074: #define UMODSI3_LIBCALL "*.urem" 2075: /* .umul is a little faster than .mul. */ 2076: #define MULSI3_LIBCALL "*.umul" 2077: 1.1.1.3 ! root 2078: /* Define library calls for quad FP operations. These are all part of the ! 2079: SPARC ABI. */ ! 2080: #define ADDTF3_LIBCALL "_Q_add" ! 2081: #define SUBTF3_LIBCALL "_Q_sub" ! 2082: #define MULTF3_LIBCALL "_Q_mul" ! 2083: #define DIVTF3_LIBCALL "_Q_div" ! 2084: #define FLOATSITF2_LIBCALL "_Q_itoq" ! 2085: #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" ! 2086: #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" ! 2087: #define EXTENDSFTF2_LIBCALL "_Q_stoq" ! 2088: #define TRUNCTFSF2_LIBCALL "_Q_qtos" ! 2089: #define EXTENDDFTF2_LIBCALL "_Q_dtoq" ! 2090: #define TRUNCTFDF2_LIBCALL "_Q_qtod" ! 2091: #define EQTF2_LIBCALL "_Q_feq" ! 2092: #define NETF2_LIBCALL "_Q_fne" ! 2093: #define GTTF2_LIBCALL "_Q_fgt" ! 2094: #define GETF2_LIBCALL "_Q_fge" ! 2095: #define LTTF2_LIBCALL "_Q_flt" ! 2096: #define LETF2_LIBCALL "_Q_fle" ! 2097: ! 2098: /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because ! 2099: with soft-float, the SFmode and DFmode sqrt instructions will be absent, ! 2100: and the compiler will notice and try to use the TFmode sqrt instruction ! 2101: for calls to the builtin function sqrt, but this fails. */ ! 2102: #define INIT_TARGET_OPTABS \ ! 2103: do { \ ! 2104: INIT_SUBTARGET_OPTABS; \ ! 2105: if (TARGET_FPU) \ ! 2106: sqrt_optab->handlers[(int) TFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \ ! 2107: } while (0) ! 2108: ! 2109: /* This is meant to be redefined in the host dependent files */ ! 2110: #define INIT_SUBTARGET_OPTABS ! 2111: 1.1 root 2112: /* Compute the cost of computing a constant rtl expression RTX 2113: whose rtx-code is CODE. The body of this macro is a portion 2114: of a switch statement. If the code is computed here, 2115: return it with a return statement. Otherwise, break from the switch. */ 2116: 2117: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 2118: case CONST_INT: \ 2119: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ 2120: return 0; \ 2121: case HIGH: \ 2122: return 2; \ 2123: case CONST: \ 2124: case LABEL_REF: \ 2125: case SYMBOL_REF: \ 2126: return 4; \ 2127: case CONST_DOUBLE: \ 2128: if (GET_MODE (RTX) == DImode) \ 2129: if ((XINT (RTX, 3) == 0 \ 2130: && (unsigned) XINT (RTX, 2) < 0x1000) \ 2131: || (XINT (RTX, 3) == -1 \ 2132: && XINT (RTX, 2) < 0 \ 2133: && XINT (RTX, 2) >= -0x1000)) \ 2134: return 0; \ 2135: return 8; 2136: 1.1.1.3 ! root 2137: /* Compute the cost of an address. For the sparc, all valid addresses are ! 2138: the same cost. ! 2139: ??? Is this true for v9? */ 1.1 root 2140: 1.1.1.3 ! root 2141: #define ADDRESS_COST(RTX) 1 1.1 root 2142: 2143: /* Compute extra cost of moving data between one register class 1.1.1.3 ! root 2144: and another. ! 2145: ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */ 1.1 root 2146: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 1.1.1.3 ! root 2147: (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \ ! 2148: || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2) 1.1 root 2149: 2150: /* Provide the costs of a rtl expression. This is in the body of a 2151: switch on CODE. The purpose for the cost of MULT is to encourage 2152: `synth_mult' to find a synthetic multiply when reasonable. 2153: 2154: If we need more than 12 insns to do a multiply, then go out-of-line, 2155: since the call overhead will be < 10% of the cost of the multiply. */ 2156: 2157: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 2158: case MULT: \ 1.1.1.3 ! root 2159: return (TARGET_V8 || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ 1.1 root 2160: case DIV: \ 2161: case UDIV: \ 2162: case MOD: \ 2163: case UMOD: \ 2164: return COSTS_N_INSNS (25); \ 2165: /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ 2166: so that cse will favor the latter. */ \ 2167: case FLOAT: \ 2168: case FIX: \ 2169: return 19; 2170: 1.1.1.3 ! root 2171: /* Adjust the cost of dependencies. */ ! 2172: #define ADJUST_COST(INSN,LINK,DEP,COST) \ ! 2173: if (TARGET_SUPERSPARC) \ ! 2174: (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST) ! 2175: 1.1 root 2176: /* Conditional branches with empty delay slots have a length of two. */ 2177: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2178: if (GET_CODE (INSN) == CALL_INSN \ 2179: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ 2180: LENGTH += 1; 2181: 2182: /* Control the assembler format that we output. */ 2183: 2184: /* Output at beginning of assembler file. */ 2185: 2186: #define ASM_FILE_START(file) 2187: 2188: /* Output to assembler file text saying following lines 2189: may contain character constants, extra white space, comments, etc. */ 2190: 2191: #define ASM_APP_ON "" 2192: 2193: /* Output to assembler file text saying following lines 2194: no longer contain unusual constructs. */ 2195: 2196: #define ASM_APP_OFF "" 2197: 1.1.1.3 ! root 2198: /* ??? Try to make the style consistent here (_OP?). */ ! 2199: ! 2200: #define ASM_LONGLONG ".xword" 1.1 root 2201: #define ASM_LONG ".word" 2202: #define ASM_SHORT ".half" 2203: #define ASM_BYTE_OP ".byte" 1.1.1.3 ! root 2204: #define ASM_FLOAT ".single" ! 2205: #define ASM_DOUBLE ".double" ! 2206: #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ 1.1 root 2207: 2208: /* Output before read-only data. */ 2209: 2210: #define TEXT_SECTION_ASM_OP ".text" 2211: 2212: /* Output before writable data. */ 2213: 2214: #define DATA_SECTION_ASM_OP ".data" 2215: 2216: /* How to refer to registers in assembler output. 2217: This sequence is indexed by compiler's hard-register-number (see above). */ 2218: 1.1.1.3 ! root 2219: #ifdef SPARCV9 ! 2220: #define REGISTER_NAMES \ ! 2221: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ ! 2222: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ ! 2223: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ ! 2224: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ ! 2225: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ ! 2226: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ ! 2227: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ ! 2228: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ ! 2229: "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ ! 2230: "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ ! 2231: "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ ! 2232: "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ ! 2233: "%fcc0", "%fcc1", "%fcc2", "%fcc3"} ! 2234: #else 1.1 root 2235: #define REGISTER_NAMES \ 2236: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2237: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2238: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2239: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2240: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2241: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2242: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2243: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} 1.1.1.3 ! root 2244: #endif 1.1 root 2245: 2246: /* Define additional names for use in asm clobbers and asm declarations. 2247: 2248: We define the fake Condition Code register as an alias for reg 0 (which 2249: is our `condition code' register), so that condition codes can easily 2250: be clobbered by an asm. No such register actually exists. Condition 2251: codes are partly stored in the PSR and partly in the FSR. */ 2252: 2253: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} 2254: 2255: /* How to renumber registers for dbx and gdb. */ 2256: 2257: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 2258: 2259: /* On Sun 4, this limit is 2048. We use 1500 to be safe, 2260: since the length can run past this up to a continuation point. */ 2261: #define DBX_CONTIN_LENGTH 1500 2262: 2263: /* This is how to output a note to DBX telling it the line number 2264: to which the following sequence of instructions corresponds. 2265: 2266: This is needed for SunOS 4.0, and should not hurt for 3.2 2267: versions either. */ 2268: #define ASM_OUTPUT_SOURCE_LINE(file, line) \ 2269: { static int sym_lineno = 1; \ 2270: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ 2271: line, sym_lineno, sym_lineno); \ 2272: sym_lineno += 1; } 2273: 2274: /* This is how to output the definition of a user-level label named NAME, 2275: such as the label on a static function or variable NAME. */ 2276: 2277: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 2278: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 2279: 2280: /* This is how to output a command to make the user-level label named NAME 2281: defined for reference from other files. */ 2282: 2283: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 2284: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) 2285: 2286: /* This is how to output a reference to a user-level label named NAME. 2287: `assemble_name' uses this. */ 2288: 2289: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2290: fprintf (FILE, "_%s", NAME) 2291: 2292: /* This is how to output a definition of an internal numbered label where 2293: PREFIX is the class of label and NUM is the number within the class. */ 2294: 2295: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 2296: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 2297: 2298: /* This is how to output a reference to an internal numbered label where 2299: PREFIX is the class of label and NUM is the number within the class. */ 2300: /* FIXME: This should be used throughout gcc, and documented in the texinfo 2301: files. There is no reason you should have to allocate a buffer and 2302: `sprintf' to reference an internal label (as opposed to defining it). */ 2303: 2304: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ 2305: fprintf (FILE, "%s%d", PREFIX, NUM) 2306: 2307: /* This is how to store into the string LABEL 2308: the symbol_ref name of an internal numbered label where 2309: PREFIX is the class of label and NUM is the number within the class. 2310: This is suitable for output with `assemble_name'. */ 2311: 2312: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2313: sprintf (LABEL, "*%s%d", PREFIX, NUM) 2314: 2315: /* This is how to output an assembler line defining a `double' constant. */ 2316: 2317: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 2318: { \ 1.1.1.2 root 2319: long t[2]; \ 2320: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ 2321: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2322: ASM_LONG, t[0], ASM_LONG, t[1]); \ 1.1 root 2323: } 2324: 2325: /* This is how to output an assembler line defining a `float' constant. */ 2326: 2327: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 2328: { \ 1.1.1.2 root 2329: long t; \ 2330: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ 2331: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ 2332: } \ 1.1 root 2333: 2334: /* This is how to output an assembler line defining a `long double' 2335: constant. */ 2336: 2337: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ 2338: { \ 2339: long t[4]; \ 2340: REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ 2341: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2342: ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ 2343: } 2344: 2345: /* This is how to output an assembler line defining an `int' constant. */ 2346: 2347: #define ASM_OUTPUT_INT(FILE,VALUE) \ 2348: ( fprintf (FILE, "\t%s\t", ASM_LONG), \ 2349: output_addr_const (FILE, (VALUE)), \ 2350: fprintf (FILE, "\n")) 2351: 2352: /* This is how to output an assembler line defining a DImode constant. */ 2353: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ 2354: output_double_int (FILE, VALUE) 2355: 2356: /* Likewise for `char' and `short' constants. */ 2357: 2358: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 2359: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ 2360: output_addr_const (FILE, (VALUE)), \ 2361: fprintf (FILE, "\n")) 2362: 2363: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 2364: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ 2365: output_addr_const (FILE, (VALUE)), \ 2366: fprintf (FILE, "\n")) 2367: 2368: /* This is how to output an assembler line for a numeric constant byte. */ 2369: 2370: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 2371: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) 2372: 2373: /* This is how to output an element of a case-vector that is absolute. */ 2374: 2375: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2376: do { \ 2377: char label[30]; \ 2378: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 ! root 2379: if (Pmode == SImode) \ ! 2380: fprintf (FILE, "\t.word\t"); \ ! 2381: else if (TARGET_ENV32) \ ! 2382: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ ! 2383: else \ ! 2384: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2385: assemble_name (FILE, label); \ 2386: fprintf (FILE, "\n"); \ 2387: } while (0) 2388: 2389: /* This is how to output an element of a case-vector that is relative. 2390: (SPARC uses such vectors only when generating PIC.) */ 2391: 2392: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 2393: do { \ 2394: char label[30]; \ 2395: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 ! root 2396: if (Pmode == SImode) \ ! 2397: fprintf (FILE, "\t.word\t"); \ ! 2398: else if (TARGET_ENV32) \ ! 2399: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ ! 2400: else \ ! 2401: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2402: assemble_name (FILE, label); \ 2403: fprintf (FILE, "-1b\n"); \ 2404: } while (0) 2405: 2406: /* This is how to output an assembler line 2407: that says to advance the location counter 2408: to a multiple of 2**LOG bytes. */ 2409: 2410: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2411: if ((LOG) != 0) \ 2412: fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2413: 2414: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2415: fprintf (FILE, "\t.skip %u\n", (SIZE)) 2416: 2417: /* This says how to output an assembler line 2418: to define a global common symbol. */ 2419: 2420: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1.1.1.3 ! root 2421: ( fputs ("\t.common ", (FILE)), \ 1.1 root 2422: assemble_name ((FILE), (NAME)), \ 1.1.1.3 ! root 2423: fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) 1.1 root 2424: 1.1.1.3 ! root 2425: /* This says how to output an assembler line to define a local common ! 2426: symbol. */ 1.1 root 2427: 1.1.1.3 ! root 2428: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ ! 2429: ( fputs ("\t.reserve ", (FILE)), \ ! 2430: assemble_name ((FILE), (NAME)), \ ! 2431: fprintf ((FILE), ",%u,\"bss\",%u\n", \ ! 2432: (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1.1 root 2433: 2434: /* Store in OUTPUT a string (made with alloca) containing 2435: an assembler-name for a local static variable named NAME. 2436: LABELNO is an integer which is different for each call. */ 2437: 2438: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2439: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2440: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2441: 2442: #define IDENT_ASM_OP ".ident" 2443: 2444: /* Output #ident as a .ident. */ 2445: 2446: #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2447: fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); 2448: 2449: /* Define the parentheses used to group arithmetic operations 2450: in assembler code. */ 2451: 2452: #define ASM_OPEN_PAREN "(" 2453: #define ASM_CLOSE_PAREN ")" 2454: 2455: /* Define results of standard character escape sequences. */ 2456: #define TARGET_BELL 007 2457: #define TARGET_BS 010 2458: #define TARGET_TAB 011 2459: #define TARGET_NEWLINE 012 2460: #define TARGET_VT 013 2461: #define TARGET_FF 014 2462: #define TARGET_CR 015 2463: 2464: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2465: ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') 2466: 2467: /* Print operand X (an rtx) in assembler syntax to file FILE. 2468: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2469: For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2470: 2471: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2472: 2473: /* Print a memory address as an operand to reference that memory location. */ 2474: 2475: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2476: { register rtx base, index = 0; \ 2477: int offset = 0; \ 2478: register rtx addr = ADDR; \ 2479: if (GET_CODE (addr) == REG) \ 2480: fputs (reg_names[REGNO (addr)], FILE); \ 2481: else if (GET_CODE (addr) == PLUS) \ 2482: { \ 2483: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2484: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2485: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2486: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2487: else \ 2488: base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2489: fputs (reg_names[REGNO (base)], FILE); \ 2490: if (index == 0) \ 2491: fprintf (FILE, "%+d", offset); \ 2492: else if (GET_CODE (index) == REG) \ 2493: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2494: else if (GET_CODE (index) == SYMBOL_REF) \ 2495: fputc ('+', FILE), output_addr_const (FILE, index); \ 2496: else abort (); \ 2497: } \ 2498: else if (GET_CODE (addr) == MINUS \ 2499: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2500: { \ 2501: output_addr_const (FILE, XEXP (addr, 0)); \ 2502: fputs ("-(", FILE); \ 2503: output_addr_const (FILE, XEXP (addr, 1)); \ 2504: fputs ("-.)", FILE); \ 2505: } \ 2506: else if (GET_CODE (addr) == LO_SUM) \ 2507: { \ 2508: output_operand (XEXP (addr, 0), 0); \ 2509: fputs ("+%lo(", FILE); \ 2510: output_address (XEXP (addr, 1)); \ 2511: fputc (')', FILE); \ 2512: } \ 2513: else if (flag_pic && GET_CODE (addr) == CONST \ 2514: && GET_CODE (XEXP (addr, 0)) == MINUS \ 2515: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2516: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2517: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2518: { \ 2519: addr = XEXP (addr, 0); \ 2520: output_addr_const (FILE, XEXP (addr, 0)); \ 2521: /* Group the args of the second CONST in parenthesis. */ \ 2522: fputs ("-(", FILE); \ 2523: /* Skip past the second CONST--it does nothing for us. */\ 2524: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2525: /* Close the parenthesis. */ \ 2526: fputc (')', FILE); \ 2527: } \ 2528: else \ 2529: { \ 2530: output_addr_const (FILE, addr); \ 2531: } \ 2532: } 2533: 2534: /* Declare functions defined in sparc.c and used in templates. */ 2535: 2536: extern char *singlemove_string (); 2537: extern char *output_move_double (); 2538: extern char *output_move_quad (); 2539: extern char *output_fp_move_double (); 2540: extern char *output_fp_move_quad (); 2541: extern char *output_block_move (); 2542: extern char *output_scc_insn (); 2543: extern char *output_cbranch (); 1.1.1.3 ! root 2544: extern char *output_v9branch (); 1.1 root 2545: extern char *output_return (); 2546: 2547: /* Defined in flags.h, but insn-emit.c does not include flags.h. */ 2548: 2549: extern int flag_pic;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.