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1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC. 1.1.1.4 ! root 2: Copyright (C) 1987, 88, 89, 92, 94, 1995 Free Software Foundation, Inc. 1.1 root 3: Contributed by Michael Tiemann ([email protected]). 1.1.1.3 root 4: 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5: at Cygnus Support. 1.1 root 6: 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 21: the Free Software Foundation, 59 Temple Place - Suite 330, ! 22: Boston, MA 02111-1307, USA. */ 1.1 root 23: 24: /* Note that some other tm.h files include this one and then override 25: many of the definitions that relate to assembler syntax. */ 26: 1.1.1.3 root 27: /* Sparc64 support has been added by trying to allow for a day when one 28: compiler can handle both v8 and v9. There are a few cases where this 29: isn't doable, but keep them to a minimum! Two macros are used to help out: 30: TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness. 31: SPARCV9 is defined when compiling for sparc64 only. 32: In places where it is possible to choose between the two at runtime, use 33: TARGET_V9. In places where it is currently not possible to select 34: between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a 35: minimum. No attempt is made to support both v8 and v9 in the v9 compiler. 36: 37: If a combination v8/v9 compiler is too slow, it should always be possible 38: to #define TARGET_V9 as 0 (and potentially other v9-only options), and 39: #undef SPARCV9. */ 40: 41: /* What architecture we're compiling for. This must coincide with the 42: `arch_type' attribute in the .md file. The names were chosen to avoid 43: potential misunderstandings with the various 32 bit flavors (v7, v8, etc.): 44: if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that 45: could be misleading and ARCH_NOTV9 sounds klunky. */ 46: enum arch_type { ARCH_32BIT, ARCH_64BIT }; 47: extern enum arch_type sparc_arch_type; 48: 49: /* Names to predefine in the preprocessor for this target machine. */ 50: 51: /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses 52: the right varags.h file when bootstrapping. */ 53: 54: #ifdef SPARCV9 55: #define CPP_PREDEFINES \ 56: "-Dsparc -Dsun -Dunix -D__sparc_v9__ \ 57: -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" 58: #else 59: #define CPP_PREDEFINES \ 60: "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ 61: -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" 62: #endif 63: 1.1.1.4 ! root 64: #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" 1.1 root 65: 66: /* Provide required defaults for linker -e and -d switches. */ 67: 68: #define LINK_SPEC \ 1.1.1.4 ! root 69: "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ ! 70: %{assert*} %{shared:-assert pure-text}" 1.1 root 71: 72: /* Special flags to the Sun-4 assembler when using pipe for input. */ 73: 1.1.1.4 ! root 74: #define ASM_SPEC \ ! 75: " %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L}" 1.1 root 76: 77: /* Define macros to distinguish architectures. */ 1.1.1.3 root 78: 79: #ifdef SPARCV9 80: #define CPP_SPEC "\ 81: %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ 82: %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ 83: " 84: #else 85: #define CPP_SPEC "\ 86: %{msparclite:-D__sparclite__} \ 87: %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 88: %{mv8:-D__sparc_v8__} \ 89: %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 90: " 91: #endif 1.1 root 92: 93: /* Prevent error on `-sun4' and `-target sun4' options. */ 94: /* This used to translate -dalign to -malign, but that is no good 95: because it can't turn off the usual meaning of making debugging dumps. */ 96: 97: #define CC1_SPEC "%{sun4:} %{target:}" 98: 1.1.1.3 root 99: #ifdef SPARCV9 100: #define PTRDIFF_TYPE "long long int" 101: #define SIZE_TYPE "long long unsigned int" 102: #else 1.1 root 103: #define PTRDIFF_TYPE "int" 104: /* In 2.4 it should work to delete this. 105: #define SIZE_TYPE "int" */ 1.1.1.3 root 106: #endif 107: 108: /* ??? This should be 32 bits for v9 but what can we do? */ 1.1 root 109: #define WCHAR_TYPE "short unsigned int" 110: #define WCHAR_TYPE_SIZE 16 1.1.1.3 root 111: #define MAX_WCHAR_TYPE_SIZE 16 1.1 root 112: 1.1.1.3 root 113: /* Show we can debug even without a frame pointer. */ 114: #define CAN_DEBUG_WITHOUT_FP 1.1 root 115: 116: /* To make profiling work with -f{pic,PIC}, we need to emit the profiling 117: code into the rtl. Also, if we are profiling, we cannot eliminate 118: the frame pointer (because the return address will get smashed). */ 119: 1.1.1.3 root 120: void sparc_override_options (); 121: 1.1 root 122: #define OVERRIDE_OPTIONS \ 1.1.1.3 root 123: do { \ 124: if (profile_flag || profile_block_flag) \ 125: { \ 126: if (flag_pic) \ 127: { \ 128: char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \ 129: warning ("%s and profiling conflict: disabling %s", \ 130: pic_string, pic_string); \ 131: flag_pic = 0; \ 132: } \ 133: flag_omit_frame_pointer = 0; \ 134: } \ 1.1.1.4 ! root 135: SUBTARGET_OVERRIDE_OPTIONS; \ 1.1.1.3 root 136: sparc_override_options (); \ 137: } while (0) 1.1.1.2 root 138: 1.1.1.4 ! root 139: /* This is meant to be redefined in the host dependent files. */ 1.1.1.2 root 140: #define SUBTARGET_OVERRIDE_OPTIONS 1.1 root 141: 142: /* These compiler options take an argument. We ignore -target for now. */ 143: 144: #define WORD_SWITCH_TAKES_ARG(STR) \ 145: (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ 146: || !strcmp (STR, "target") || !strcmp (STR, "assert")) 147: 148: /* Print subsidiary information on the compiler version in use. */ 149: 150: #define TARGET_VERSION fprintf (stderr, " (sparc)"); 151: 152: /* Generate DBX debugging information. */ 153: 154: #define DBX_DEBUGGING_INFO 1.1.1.3 root 155: 1.1 root 156: /* Run-time compilation parameters selecting different hardware subsets. */ 157: 158: extern int target_flags; 159: 160: /* Nonzero if we should generate code to use the fpu. */ 1.1.1.3 root 161: #define MASK_FPU 1 162: #define TARGET_FPU (target_flags & MASK_FPU) 1.1 root 163: 164: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we 165: use fast return insns, but lose some generality. */ 1.1.1.3 root 166: #define MASK_EPILOGUE 2 167: #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) 1.1 root 168: 169: /* Nonzero if we should assume that double pointers might be unaligned. 170: This can happen when linking gcc compiled code with other compilers, 171: because the ABI only guarantees 4 byte alignment. */ 1.1.1.3 root 172: #define MASK_UNALIGNED_DOUBLES 4 173: #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) 174: 175: /* ??? Bits 0x18 are currently unused. */ 176: 177: /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */ 178: #define MASK_SUPERSPARC 0x20 179: #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC) 1.1 root 180: 181: /* Nonzero means that we should generate code for a v8 sparc. */ 1.1.1.3 root 182: #define MASK_V8 0x40 183: #define TARGET_V8 (target_flags & MASK_V8) 1.1 root 184: 1.1.1.2 root 185: /* Nonzero means that we should generate code for a sparclite. 186: This enables the sparclite specific instructions, but does not affect 187: whether FPU instructions are emitted. */ 1.1.1.3 root 188: #define MASK_SPARCLITE 0x80 189: #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) 1.1 root 190: 191: /* Nonzero means that we should generate code using a flat register window 192: model, i.e. no save/restore instructions are generated, in the most 193: efficient manner. This code is not compatible with normal sparc code. */ 194: /* This is not a user selectable option yet, because it requires changes 195: that are not yet switchable via command line arguments. */ 1.1.1.3 root 196: /* ??? This flag is deprecated and may disappear at some point. */ 197: #define MASK_FRW 0x100 198: #define TARGET_FRW (target_flags & MASK_FRW) 1.1 root 199: 200: /* Nonzero means that we should generate code using a flat register window 201: model, i.e. no save/restore instructions are generated, but which is 202: compatible with normal sparc code. This is the same as above, except 1.1.1.3 root 203: that the frame pointer is %i7 instead of %fp. */ 204: /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will 205: go away, but until that time only use this one when necessary. 206: -mflat sets both. */ 207: #define MASK_FLAT 0x200 208: #define TARGET_FLAT (target_flags & MASK_FLAT) 209: 210: /* Nonzero means use the registers that the Sparc ABI reserves for 211: application software. This is the default for v8, but not v9. */ 212: #define MASK_APP_REGS 0x400 213: #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) 214: 215: /* Option to select how quad word floating point is implemented. 216: When TARGET_HARD_QUAD is true, we use the hardware quad instructions. 217: Otherwise, we use the SPARC ABI quad library functions. */ 218: #define MASK_HARD_QUAD 0x800 219: #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) 220: 221: /* Nonzero if we're compiling for 64 bit sparc. */ 222: #define MASK_V9 0x1000 223: #define TARGET_V9 (target_flags & MASK_V9) 224: 225: /* Nonzero if ints are 64 bits. 226: This automatically implies longs are 64 bits too. 227: This option is for v9 only. */ 228: #define MASK_INT64 0x2000 229: #define TARGET_INT64 (target_flags & MASK_INT64) 230: 231: /* Nonzero if longs are 64 bits. 232: This option is for v9 only. */ 233: #define MASK_LONG64 0x4000 234: #define TARGET_LONG64 (target_flags & MASK_LONG64) 235: 236: /* Nonzero if pointers are 64 bits. 237: This is not a user selectable option, though it may be one day - 238: so it is used to determine pointer size instead of an architecture flag. */ 239: #define MASK_PTR64 0x8000 240: #define TARGET_PTR64 (target_flags & MASK_PTR64) 241: 242: /* Nonzero if we are generating code to be tested in a 32 bit environment. 243: Hence, we assume the upper 32 bits of symbolic addresses are zero, and 244: avoid generating %uhi and %ulo terms. 245: Pointers are still 64 bits though! This option is for v9 only. */ 246: /* ??? This option is deprecated. Try to use -mmedlow. */ 247: #define MASK_ENV32 0x10000 248: #define TARGET_ENV32 (target_flags & MASK_ENV32) 249: 250: /* Memory models. 251: Two memory models are supported: 252: TARGET_MEDLOW: 32 bit address space, top 32 bits = 0 253: (pointers still 64 bits) 254: TARGET_MEDANY: 32 bit address space, data segment loaded anywhere 255: (use %g4 as offset). 256: TARGET_FULLANY: not supported yet. 257: These options are for v9 only. All mask values are nonzero so the v8 258: compiler can assume this stuff won't interfere. */ 259: #define MASK_MEDLOW 0x20000 260: #define MASK_MEDANY 0x40000 261: #define MASK_FULLANY 0x60000 262: #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) 263: #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) 264: #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) 265: #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) 266: 267: /* ??? There are hardcoded references to this reg in the .md file. */ 268: #define MEDANY_BASE_REG "%g4" 269: 270: /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by 271: adding 2047 to %sp. This option is for v9 only and is the default. */ 272: #define MASK_STACK_BIAS 0x80000 273: #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) 1.1 root 274: 275: /* Macro to define tables used to set the flags. 276: This is a list in braces of pairs in braces, 277: each pair being { "NAME", VALUE } 278: where VALUE is the bits to set or minus the bits to clear. 279: An empty string NAME is used to identify the default VALUE. */ 280: 1.1.1.2 root 281: /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 1.1.1.3 root 282: The Fujitsu MB86934 is the recent sparclite chip, with an fpu. 1.1.1.2 root 283: We use -mf930 and -mf934 options to choose which. 284: ??? These should perhaps be -mcpu= options. */ 285: 1.1 root 286: #define TARGET_SWITCHES \ 1.1.1.3 root 287: { {"fpu", MASK_FPU}, \ 288: {"no-fpu", -MASK_FPU}, \ 289: {"hard-float", MASK_FPU}, \ 290: {"soft-float", -MASK_FPU}, \ 291: {"epilogue", MASK_EPILOGUE}, \ 292: {"no-epilogue", -MASK_EPILOGUE}, \ 293: {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ 294: {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ 295: {"supersparc", MASK_SUPERSPARC+MASK_V8}, \ 296: {"cypress", -MASK_SUPERSPARC-MASK_V8}, \ 297: {"v8", MASK_V8}, \ 298: {"no-v8", -MASK_V8}, \ 299: {"sparclite", MASK_SPARCLITE}, \ 300: {"no-sparclite", -MASK_SPARCLITE}, \ 301: {"f930", MASK_SPARCLITE}, \ 302: {"f930", -MASK_FPU}, \ 303: {"f934", MASK_SPARCLITE}, \ 304: {"flat", MASK_FRW+MASK_FLAT}, \ 305: {"no-flat", -(MASK_FRW+MASK_FLAT)}, \ 306: {"app-regs", MASK_APP_REGS}, \ 307: {"no-app-regs", -MASK_APP_REGS}, \ 308: {"hard-quad-float", MASK_HARD_QUAD}, \ 309: {"soft-quad-float", -MASK_HARD_QUAD}, \ 310: SUBTARGET_SWITCHES \ 311: V9_SWITCHES \ 1.1 root 312: { "", TARGET_DEFAULT}} 313: 1.1.1.3 root 314: #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) 1.1.1.2 root 315: 316: /* This is meant to be redefined in the host dependent files */ 317: #define SUBTARGET_SWITCHES 1.1 root 318: 1.1.1.3 root 319: /* ??? Until we support a combination v8/v9 compiler, the v9 specific options 320: are only defined for the v9 compiler. */ 321: #ifdef SPARCV9 322: #define V9_SWITCHES \ 323: /* {"v9", MASK_V9}, */ \ 324: {"int64", MASK_INT64+MASK_LONG64}, \ 325: {"int32", -MASK_INT64}, \ 326: {"int32", MASK_LONG64}, \ 327: {"long64", -MASK_INT64}, \ 328: {"long64", MASK_LONG64}, \ 329: {"long32", -(MASK_INT64+MASK_LONG64)}, \ 330: /* {"ptr64", MASK_PTR64}, */ \ 331: /* {"ptr32", -MASK_PTR64}, */ \ 332: {"stack-bias", MASK_STACK_BIAS}, \ 333: {"no-stack-bias", -MASK_STACK_BIAS}, \ 334: {"medlow", -MASK_CODE_MODEL}, \ 335: {"medlow", MASK_MEDLOW}, \ 336: {"medany", -MASK_CODE_MODEL}, \ 337: {"medany", MASK_MEDANY}, 338: #else 339: #define V9_SWITCHES 1.1.1.2 root 340: #endif 1.1.1.3 root 341: 342: /* target machine storage layout */ 1.1.1.2 root 343: 344: /* Define for cross-compilation to a sparc target with no TFmode from a host 345: with a different float format (e.g. VAX). */ 346: #define REAL_ARITHMETIC 347: 1.1 root 348: /* Define this if most significant bit is lowest numbered 349: in instructions that operate on numbered bit-fields. */ 350: #define BITS_BIG_ENDIAN 1 351: 352: /* Define this if most significant byte of a word is the lowest numbered. */ 353: /* This is true on the SPARC. */ 354: #define BYTES_BIG_ENDIAN 1 355: 356: /* Define this if most significant word of a multiword number is the lowest 357: numbered. */ 358: /* Doubles are stored in memory with the high order word first. This 359: matters when cross-compiling. */ 360: #define WORDS_BIG_ENDIAN 1 361: 362: /* number of bits in an addressable storage unit */ 363: #define BITS_PER_UNIT 8 364: 365: /* Width in bits of a "word", which is the contents of a machine register. 366: Note that this is not necessarily the width of data type `int'; 367: if using 16-bit ints on a 68000, this would still be 32. 368: But on a machine with 16-bit registers, this would be 16. */ 1.1.1.3 root 369: #define BITS_PER_WORD (TARGET_V9 ? 64 : 32) 370: #define MAX_BITS_PER_WORD 64 1.1 root 371: 372: /* Width of a word, in units (bytes). */ 1.1.1.3 root 373: #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4) 1.1.1.4 ! root 374: #define MIN_UNITS_PER_WORD 4 1.1.1.3 root 375: 376: /* Now define the sizes of the C data types. */ 377: 378: #define SHORT_TYPE_SIZE 16 379: #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) 380: #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 381: #define LONG_LONG_TYPE_SIZE 64 382: #define FLOAT_TYPE_SIZE 32 383: #define DOUBLE_TYPE_SIZE 64 384: 385: #define MAX_INT_TYPE_SIZE 64 386: #define MAX_LONG_TYPE_SIZE 64 387: 388: #ifdef SPARCV9 389: /* ??? This does not work in SunOS 4.x, so it is not enabled here. 390: Instead, it is enabled in sol2.h, because it does work under Solaris. */ 391: /* Define for support of TFmode long double and REAL_ARITHMETIC. 392: Sparc ABI says that long double is 4 words. */ 393: #define LONG_DOUBLE_TYPE_SIZE 128 394: #endif 1.1 root 395: 396: /* Width in bits of a pointer. 397: See also the macro `Pmode' defined below. */ 1.1.1.3 root 398: #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 1.1 root 399: 400: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1.1.1.3 root 401: #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 402: 403: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 1.1.1.3 root 404: #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64) 1.1 root 405: 406: /* ALIGN FRAMES on double word boundaries */ 407: 1.1.1.3 root 408: #define SPARC_STACK_ALIGN(LOC) \ 409: (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 1.1 root 410: 411: /* Allocation boundary (in *bits*) for the code of a function. */ 412: #define FUNCTION_BOUNDARY 32 413: 414: /* Alignment of field after `int : 0' in a structure. */ 1.1.1.3 root 415: /* ??? Should this be based on TARGET_INT64? */ 416: #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 417: 418: /* Every structure's size must be a multiple of this. */ 419: #define STRUCTURE_SIZE_BOUNDARY 8 420: 421: /* A bitfield declared as `int' forces `int' alignment for the struct. */ 422: #define PCC_BITFIELD_TYPE_MATTERS 1 423: 424: /* No data type wants to be aligned rounder than this. */ 1.1.1.3 root 425: #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64) 1.1 root 426: 427: /* The best alignment to use in cases where we have a choice. */ 428: #define FASTEST_ALIGNMENT 64 429: 430: /* Make strings word-aligned so strcpy from constants will be faster. */ 431: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 432: ((TREE_CODE (EXP) == STRING_CST \ 433: && (ALIGN) < FASTEST_ALIGNMENT) \ 434: ? FASTEST_ALIGNMENT : (ALIGN)) 435: 436: /* Make arrays of chars word-aligned for the same reasons. */ 437: #define DATA_ALIGNMENT(TYPE, ALIGN) \ 438: (TREE_CODE (TYPE) == ARRAY_TYPE \ 439: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 440: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 441: 442: /* Set this nonzero if move instructions will actually fail to work 443: when given unaligned data. */ 444: #define STRICT_ALIGNMENT 1 445: 446: /* Things that must be doubleword aligned cannot go in the text section, 447: because the linker fails to align the text section enough! 1.1.1.3 root 448: Put them in the data section. This macro is only used in this file. */ 1.1 root 449: #define MAX_TEXT_ALIGN 32 450: 1.1.1.4 ! root 451: /* This forces all variables and constants to the data section when PIC. ! 452: This is because the SunOS 4 shared library scheme thinks everything in ! 453: text is a function, and patches the address to point to a loader stub. */ ! 454: /* This is defined to zero for every system which doesn't use the a.out object ! 455: file format. */ ! 456: #ifndef SUNOS4_SHARED_LIBRARIES ! 457: #define SUNOS4_SHARED_LIBRARIES 0 ! 458: #endif ! 459: 1.1.1.3 root 460: /* This is defined differently for v9 in a cover file. */ 1.1 root 461: #define SELECT_SECTION(T,RELOC) \ 462: { \ 463: if (TREE_CODE (T) == VAR_DECL) \ 464: { \ 465: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ 1.1.1.3 root 466: && DECL_INITIAL (T) \ 467: && (DECL_INITIAL (T) == error_mark_node \ 468: || TREE_CONSTANT (DECL_INITIAL (T))) \ 1.1 root 469: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ 1.1.1.4 ! root 470: && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 471: text_section (); \ 472: else \ 473: data_section (); \ 474: } \ 475: else if (TREE_CODE (T) == CONSTRUCTOR) \ 476: { \ 1.1.1.4 ! root 477: if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ 1.1 root 478: data_section (); \ 479: } \ 1.1.1.4 ! root 480: else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ 1.1 root 481: { \ 482: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ 1.1.1.4 ! root 483: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ ! 484: || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 485: data_section (); \ 486: else \ 487: text_section (); \ 488: } \ 489: } 490: 491: /* Use text section for a constant 492: unless we need more alignment than that offers. */ 1.1.1.3 root 493: /* This is defined differently for v9 in a cover file. */ 1.1 root 494: #define SELECT_RTX_SECTION(MODE, X) \ 495: { \ 496: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ 1.1.1.4 ! root 497: && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 498: text_section (); \ 499: else \ 500: data_section (); \ 501: } 502: 503: /* Standard register usage. */ 504: 505: /* Number of actual hardware registers. 506: The hardware registers are assigned numbers for the compiler 507: from 0 to just below FIRST_PSEUDO_REGISTER. 508: All registers that the compiler knows about must be given numbers, 509: even those that are not normally considered general registers. 510: 1.1.1.3 root 511: SPARC has 32 integer registers and 32 floating point registers. 512: 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 513: accessible. We still account for them to simplify register computations 514: (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 515: 32+32+32+4 == 100. 516: Register 0 is used as the integer condition code register. */ 1.1 root 517: 1.1.1.3 root 518: #ifdef SPARCV9 519: #define FIRST_PSEUDO_REGISTER 100 520: #else 1.1 root 521: #define FIRST_PSEUDO_REGISTER 64 1.1.1.3 root 522: #endif 1.1 root 523: 524: /* 1 for registers that have pervasive standard uses 525: and are not available for the register allocator. 526: g0 is used for the condition code and not to represent %g0, which is 527: hardwired to 0, so reg 0 is *not* fixed. 1.1.1.3 root 528: On non-v9 systems: 529: g1 is free to use as temporary. 530: g2-g4 are reserved for applications. Gcc normally uses them as 531: temporaries, but this can be disabled via the -mno-app-regs option. 532: g5 through g7 are reserved for the operating system. 533: On v9 systems: 534: g1 and g5 are free to use as temporaries. 535: g2-g4 are reserved for applications (the compiler will not normally use 536: them, but they can be used as temporaries with -mapp-regs). 537: g6-g7 are reserved for the operating system. 538: ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 539: currently be a fixed register until this pattern is rewritten. 540: Register 1 is also used when restoring call-preserved registers in large 541: stack frames. */ 542: 543: #ifdef SPARCV9 544: #define FIXED_REGISTERS \ 545: {0, 1, 1, 1, 1, 0, 1, 1, \ 546: 0, 0, 0, 0, 0, 0, 1, 0, \ 547: 0, 0, 0, 0, 0, 0, 0, 0, \ 548: 0, 0, 0, 0, 0, 0, 1, 1, \ 549: \ 550: 0, 0, 0, 0, 0, 0, 0, 0, \ 551: 0, 0, 0, 0, 0, 0, 0, 0, \ 552: 0, 0, 0, 0, 0, 0, 0, 0, \ 553: 0, 0, 0, 0, 0, 0, 0, 0, \ 554: \ 555: 0, 0, 0, 0, 0, 0, 0, 0, \ 556: 0, 0, 0, 0, 0, 0, 0, 0, \ 557: 0, 0, 0, 0, 0, 0, 0, 0, \ 558: 0, 0, 0, 0, 0, 0, 0, 0, \ 559: \ 560: 0, 0, 0, 0} 561: #else 1.1 root 562: #define FIXED_REGISTERS \ 563: {0, 0, 0, 0, 0, 1, 1, 1, \ 564: 0, 0, 0, 0, 0, 0, 1, 0, \ 565: 0, 0, 0, 0, 0, 0, 0, 0, \ 566: 0, 0, 0, 0, 0, 0, 1, 1, \ 567: \ 568: 0, 0, 0, 0, 0, 0, 0, 0, \ 569: 0, 0, 0, 0, 0, 0, 0, 0, \ 570: 0, 0, 0, 0, 0, 0, 0, 0, \ 571: 0, 0, 0, 0, 0, 0, 0, 0} 1.1.1.3 root 572: #endif 1.1 root 573: 574: /* 1 for registers not available across function calls. 575: These must include the FIXED_REGISTERS and also any 576: registers that can be used without being saved. 577: The latter must include the registers where values are returned 578: and the register where structure-value addresses are passed. 579: Aside from that, you can include as many other registers as you like. */ 1.1.1.3 root 580: 581: #ifdef SPARCV9 582: #define CALL_USED_REGISTERS \ 583: {1, 1, 1, 1, 1, 1, 1, 1, \ 584: 1, 1, 1, 1, 1, 1, 1, 1, \ 585: 0, 0, 0, 0, 0, 0, 0, 0, \ 586: 0, 0, 0, 0, 0, 0, 1, 1, \ 587: \ 588: 1, 1, 1, 1, 1, 1, 1, 1, \ 589: 1, 1, 1, 1, 1, 1, 1, 1, \ 590: 0, 0, 0, 0, 0, 0, 0, 0, \ 591: 0, 0, 0, 0, 0, 0, 0, 0, \ 592: \ 593: 0, 0, 0, 0, 0, 0, 0, 0, \ 594: 0, 0, 0, 0, 0, 0, 0, 0, \ 595: 1, 1, 1, 1, 1, 1, 1, 1, \ 596: 1, 1, 1, 1, 1, 1, 1, 1, \ 597: \ 598: 1, 1, 1, 1} 599: #else 1.1 root 600: #define CALL_USED_REGISTERS \ 601: {1, 1, 1, 1, 1, 1, 1, 1, \ 602: 1, 1, 1, 1, 1, 1, 1, 1, \ 603: 0, 0, 0, 0, 0, 0, 0, 0, \ 604: 0, 0, 0, 0, 0, 0, 1, 1, \ 605: \ 606: 1, 1, 1, 1, 1, 1, 1, 1, \ 607: 1, 1, 1, 1, 1, 1, 1, 1, \ 608: 1, 1, 1, 1, 1, 1, 1, 1, \ 609: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 root 610: #endif 1.1 root 611: 612: /* If !TARGET_FPU, then make the fp registers fixed so that they won't 1.1.1.3 root 613: be allocated. On v9, also make the fp cc regs fixed. */ 1.1 root 614: 615: #define CONDITIONAL_REGISTER_USAGE \ 616: do \ 617: { \ 618: if (! TARGET_FPU) \ 619: { \ 620: int regno; \ 1.1.1.3 root 621: for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1.1 root 622: fixed_regs[regno] = 1; \ 623: } \ 1.1.1.3 root 624: if (! TARGET_APP_REGS) \ 625: { \ 626: fixed_regs[2] = 1; \ 627: fixed_regs[3] = 1; \ 628: fixed_regs[4] = 1; \ 629: } \ 630: else \ 631: { \ 632: fixed_regs[2] = 0; \ 633: fixed_regs[3] = 0; \ 634: fixed_regs[4] = TARGET_MEDANY != 0; \ 635: } \ 636: if (TARGET_FLAT) \ 637: { \ 638: /* Let the compiler believe the frame pointer is still \ 639: %fp, but output it as %i7. */ \ 640: fixed_regs[31] = 1; \ 641: reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ 642: /* ??? This is a hack to disable leaf functions. */ \ 643: global_regs[7] = 1; \ 644: } \ 645: if (profile_block_flag) \ 646: { \ 647: /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ 648: uses them. */ \ 649: fixed_regs[1] = 1; \ 650: fixed_regs[2] = 1; \ 651: } \ 1.1 root 652: } \ 653: while (0) 654: 655: /* Return number of consecutive hard regs needed starting at reg REGNO 656: to hold something of mode MODE. 657: This is ordinarily the length in words of a value of mode MODE 658: but can be less for certain modes in special long registers. 659: 660: On SPARC, ordinary registers hold 32 bits worth; 661: this means both integer and floating point registers. 1.1.1.3 root 662: On v9, integer regs hold 64 bits worth; floating point regs hold 663: 32 bits worth (this includes the new fp regs as even the odd ones are 664: included in the hard register count). */ 665: 666: #define HARD_REGNO_NREGS(REGNO, MODE) \ 667: (TARGET_V9 \ 668: ? ((REGNO) < 32 \ 669: ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 670: : (GET_MODE_SIZE (MODE) + 3) / 4) \ 671: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1.1 root 672: 673: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1.1.1.3 root 674: See sparc.c for how we initialize this. */ 675: extern int *hard_regno_mode_classes; 676: extern int sparc_mode_class[]; 1.1 root 677: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1.1.1.3 root 678: ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 1.1 root 679: 680: /* Value is 1 if it is a good idea to tie two pseudo registers 681: when one has mode MODE1 and one has mode MODE2. 682: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1.1.1.3 root 683: for any hard reg, then this must be 0 for correct output. 684: 685: For V9: SFmode can't be combined with other float modes, because they can't 686: be allocated to the %d registers. Also, DFmode won't fit in odd %f 687: registers, but SFmode will. */ 1.1 root 688: #define MODES_TIEABLE_P(MODE1, MODE2) \ 1.1.1.3 root 689: ((MODE1) == (MODE2) \ 690: || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 691: && (! TARGET_V9 \ 692: || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 693: || (MODE1 != SFmode && MODE2 != SFmode))))) 1.1 root 694: 695: /* Specify the registers used for certain standard purposes. 696: The values of these macros are register numbers. */ 697: 698: /* SPARC pc isn't overloaded on a register that the compiler knows about. */ 699: /* #define PC_REGNUM */ 700: 701: /* Register to use for pushing function arguments. */ 702: #define STACK_POINTER_REGNUM 14 703: 1.1.1.3 root 704: /* Actual top-of-stack address is 92/136 greater than the contents of the 705: stack pointer register for !v9/v9. That is: 706: - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 707: address, and 24 bytes for the 6 register parameters. 708: - v9: 128 bytes for the in and local registers + 8 bytes reserved. */ 1.1 root 709: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) 710: 1.1.1.3 root 711: /* The stack bias (amount by which the hardware register is offset by). */ 712: #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) 713: 1.1 root 714: /* Base register for access to local variables of the function. */ 715: #define FRAME_POINTER_REGNUM 30 716: 717: #if 0 718: /* Register that is used for the return address. */ 719: #define RETURN_ADDR_REGNUM 15 720: #endif 721: 722: /* Value should be nonzero if functions must have frame pointers. 723: Zero means the frame pointer need not be set up (and parms 724: may be accessed via the stack pointer) in functions that seem suitable. 725: This is computed in `reload', in reload1.c. 1.1.1.3 root 726: Used in flow.c, global.c, and reload1.c. 1.1 root 727: 1.1.1.3 root 728: Being a non-leaf function does not mean a frame pointer is needed in the 729: flat window model. However, the debugger won't be able to backtrace through 730: us with out it. */ 1.1 root 731: #define FRAME_POINTER_REQUIRED \ 1.1.1.3 root 732: (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs \ 733: || !leaf_function_p ()) \ 734: : ! (leaf_function_p () && only_leaf_regs_used ())) 1.1 root 735: 736: /* C statement to store the difference between the frame pointer 737: and the stack pointer values immediately after the function prologue. 738: 739: Note, we always pretend that this is a leaf function because if 740: it's not, there's no point in trying to eliminate the 741: frame pointer. If it is a leaf function, we guessed right! */ 742: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 1.1.1.3 root 743: ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \ 1.1 root 744: : compute_frame_size (get_frame_size (), 1))) 745: 746: /* Base register for access to arguments of the function. */ 1.1.1.3 root 747: #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 1.1 root 748: 1.1.1.2 root 749: /* Register in which static-chain is passed to a function. This must 1.1.1.4 ! root 750: not be a register used by the prologue. */ ! 751: #define STATIC_CHAIN_REGNUM (TARGET_V9 ? 5 : 2) 1.1 root 752: 753: /* Register which holds offset table for position-independent 754: data references. */ 755: 756: #define PIC_OFFSET_TABLE_REGNUM 23 757: 758: #define INITIALIZE_PIC initialize_pic () 759: #define FINALIZE_PIC finalize_pic () 760: 761: /* Sparc ABI says that quad-precision floats and all structures are returned 1.1.1.3 root 762: in memory. 763: For v9, all aggregates are returned in memory. */ 764: #define RETURN_IN_MEMORY(TYPE) \ 765: (TYPE_MODE (TYPE) == BLKmode \ 766: || (! TARGET_V9 && (TYPE_MODE (TYPE) == TFmode \ 767: || TYPE_MODE (TYPE) == TCmode))) 1.1 root 768: 769: /* Functions which return large structures get the address 770: to place the wanted value at offset 64 from the frame. 1.1.1.3 root 771: Must reserve 64 bytes for the in and local registers. 772: v9: Functions which return large structures get the address to place the 773: wanted value from an invisible first argument. */ 1.1 root 774: /* Used only in other #defines in this file. */ 775: #define STRUCT_VALUE_OFFSET 64 776: 777: #define STRUCT_VALUE \ 1.1.1.3 root 778: (TARGET_V9 \ 779: ? 0 \ 780: : gen_rtx (MEM, Pmode, \ 781: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ 782: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 783: #define STRUCT_VALUE_INCOMING \ 1.1.1.3 root 784: (TARGET_V9 \ 785: ? 0 \ 786: : gen_rtx (MEM, Pmode, \ 787: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ 788: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 789: 790: /* Define the classes of registers for register constraints in the 791: machine description. Also define ranges of constants. 792: 793: One of the classes must always be named ALL_REGS and include all hard regs. 794: If there is more than one class, another class must be named NO_REGS 795: and contain no registers. 796: 797: The name GENERAL_REGS must be the name of a class (or an alias for 798: another name such as ALL_REGS). This is the class of registers 799: that is allowed by "g" or "r" in a register constraint. 800: Also, registers outside this class are allocated only when 801: instructions express preferences for them. 802: 803: The classes must be numbered in nondecreasing order; that is, 804: a larger-numbered class must never be contained completely 805: in a smaller-numbered class. 806: 807: For any two classes, it is very desirable that there be another 808: class that represents their union. */ 809: 1.1.1.3 root 810: /* The SPARC has two kinds of registers, general and floating point. 1.1 root 811: 1.1.1.3 root 812: For v9 we must distinguish between the upper and lower floating point 813: registers because the upper ones can't hold SFmode values. 814: HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 815: satisfying a group need for a class will also satisfy a single need for 816: that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 817: regs. 818: 819: It is important that one class contains all the general and all the standard 820: fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 821: because reg_class_record() will bias the selection in favor of fp regs, 822: because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 823: because FP_REGS > GENERAL_REGS. 824: 825: It is also important that one class contain all the general and all the 826: fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS 827: but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause 828: allocate_reload_reg() to bypass it causing an abort because the compiler 829: thinks it doesn't have a spill reg when in fact it does. 830: 831: v9 also has 4 floating point condition code registers. Since we don't 832: have a class that is the union of FPCC_REGS with either of the others, 833: it is important that it appear first. Otherwise the compiler will die 834: trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 835: constraints. */ 836: 837: #ifdef SPARCV9 838: enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, 839: GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 840: ALL_REGS, LIM_REG_CLASSES }; 841: #else 1.1 root 842: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; 1.1.1.3 root 843: #endif 1.1 root 844: 845: #define N_REG_CLASSES (int) LIM_REG_CLASSES 846: 847: /* Give names of register classes as strings for dump file. */ 848: 1.1.1.3 root 849: #ifdef SPARCV9 850: #define REG_CLASS_NAMES \ 851: { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \ 852: "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" } 853: #else 1.1 root 854: #define REG_CLASS_NAMES \ 1.1.1.3 root 855: { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } 856: #endif 1.1 root 857: 858: /* Define which registers fit in which classes. 859: This is an initializer for a vector of HARD_REG_SET 860: of length N_REG_CLASSES. */ 861: 1.1.1.3 root 862: #ifdef SPARCV9 863: #define REG_CLASS_CONTENTS \ 864: {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \ 865: {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \ 866: {-2, -1, -1, 0xf}} 867: #else 1.1 root 868: #if 0 && defined (__GNUC__) 869: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} 870: #else 871: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} 872: #endif 1.1.1.3 root 873: #endif 1.1 root 874: 875: /* The same information, inverted: 876: Return the class number of the smallest class containing 877: reg number REGNO. This could be a conditional expression 878: or could index an array. */ 879: 1.1.1.3 root 880: #ifdef SPARCV9 881: #define REGNO_REG_CLASS(REGNO) \ 882: ((REGNO) == 0 ? NO_REGS \ 883: : (REGNO) < 32 ? GENERAL_REGS \ 884: : (REGNO) < 64 ? FP_REGS \ 885: : (REGNO) < 96 ? EXTRA_FP_REGS \ 886: : FPCC_REGS) 887: #else 1.1 root 888: #define REGNO_REG_CLASS(REGNO) \ 889: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) 1.1.1.3 root 890: #endif 1.1 root 891: 1.1.1.3 root 892: /* This is the order in which to allocate registers normally. 1.1 root 893: 894: We put %f0/%f1 last among the float registers, so as to make it more 1.1.1.2 root 895: likely that a pseudo-register which dies in the float return register 1.1 root 896: will get allocated to the float return register, thus saving a move 1.1.1.3 root 897: instruction at the end of the function. 898: 899: On v9, the float registers are ordered a little "funny" because some 900: of them (%f16-%f47) are call-preserved. */ 901: #ifdef SPARCV9 902: #define REG_ALLOC_ORDER \ 903: { 8, 9, 10, 11, 12, 13, \ 904: 15, 16, 17, 18, 19, 20, 21, 22, \ 905: 23, 24, 25, 26, 27, 28, 29, 31, \ 906: 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ 907: 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 908: 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 909: 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 910: 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 911: 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 912: 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 913: 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 914: 32, 33, /* %f0,%f1 */ \ 915: 96, 97, 98, 99, /* %fcc0-3 */ \ 916: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30} 917: #else 1.1 root 918: #define REG_ALLOC_ORDER \ 919: { 8, 9, 10, 11, 12, 13, 2, 3, \ 920: 15, 16, 17, 18, 19, 20, 21, 22, \ 921: 23, 24, 25, 26, 27, 28, 29, 31, \ 922: 34, 35, 36, 37, 38, 39, \ 923: 40, 41, 42, 43, 44, 45, 46, 47, \ 924: 48, 49, 50, 51, 52, 53, 54, 55, \ 925: 56, 57, 58, 59, 60, 61, 62, 63, \ 926: 32, 33, \ 927: 1, 4, 5, 6, 7, 0, 14, 30} 1.1.1.3 root 928: #endif 1.1 root 929: 930: /* This is the order in which to allocate registers for 931: leaf functions. If all registers can fit in the "i" registers, 1.1.1.3 root 932: then we have the possibility of having a leaf function. 933: v9: The floating point registers are ordered a little "funny" because some 934: of them (%f16-%f47) are call-preserved. */ 935: #ifdef SPARCV9 936: #define REG_LEAF_ALLOC_ORDER \ 937: { 24, 25, 26, 27, 28, 29, \ 938: 15, 8, 9, 10, 11, 12, 13, \ 939: 16, 17, 18, 19, 20, 21, 22, 23, \ 940: 34, 35, 36, 37, 38, 39, \ 941: 40, 41, 42, 43, 44, 45, 46, 47, \ 942: 80, 81, 82, 83, 84, 85, 86, 87, \ 943: 88, 89, 90, 91, 92, 93, 94, 95, \ 944: 48, 49, 50, 51, 52, 53, 54, 55, \ 945: 56, 57, 58, 59, 60, 61, 62, 63, \ 946: 64, 65, 66, 67, 68, 69, 70, 71, \ 947: 72, 73, 74, 75, 76, 77, 78, 79, \ 948: 32, 33, \ 949: 96, 97, 98, 99, \ 950: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31} 951: #else 1.1 root 952: #define REG_LEAF_ALLOC_ORDER \ 953: { 2, 3, 24, 25, 26, 27, 28, 29, \ 954: 15, 8, 9, 10, 11, 12, 13, \ 955: 16, 17, 18, 19, 20, 21, 22, 23, \ 956: 34, 35, 36, 37, 38, 39, \ 957: 40, 41, 42, 43, 44, 45, 46, 47, \ 958: 48, 49, 50, 51, 52, 53, 54, 55, \ 959: 56, 57, 58, 59, 60, 61, 62, 63, \ 960: 32, 33, \ 961: 1, 4, 5, 6, 7, 0, 14, 30, 31} 1.1.1.3 root 962: #endif 1.1 root 963: 964: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 965: 1.1.1.3 root 966: /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when 967: -mflat is used. Function only_leaf_regs_used will return 0 if a global 968: register is used and is not permitted in a leaf function. We make %g7 969: a global reg if -mflat and voila. Since %g7 is a system register and is 970: fixed it won't be used by gcc anyway. */ 971: #ifdef SPARCV9 1.1 root 972: #define LEAF_REGISTERS \ 1.1.1.3 root 973: { 1, 1, 1, 1, 1, 1, 1, 0, \ 974: 0, 0, 0, 0, 0, 0, 1, 0, \ 975: 0, 0, 0, 0, 0, 0, 0, 0, \ 976: 1, 1, 1, 1, 1, 1, 0, 1, \ 977: 1, 1, 1, 1, 1, 1, 1, 1, \ 978: 1, 1, 1, 1, 1, 1, 1, 1, \ 979: 1, 1, 1, 1, 1, 1, 1, 1, \ 980: 1, 1, 1, 1, 1, 1, 1, 1, \ 981: 1, 1, 1, 1, 1, 1, 1, 1, \ 982: 1, 1, 1, 1, 1, 1, 1, 1, \ 983: 1, 1, 1, 1, 1, 1, 1, 1, \ 984: 1, 1, 1, 1, 1, 1, 1, 1, \ 985: 1, 1, 1, 1} 986: #else 987: #define LEAF_REGISTERS \ 988: { 1, 1, 1, 1, 1, 1, 1, 0, \ 1.1 root 989: 0, 0, 0, 0, 0, 0, 1, 0, \ 990: 0, 0, 0, 0, 0, 0, 0, 0, \ 991: 1, 1, 1, 1, 1, 1, 0, 1, \ 992: 1, 1, 1, 1, 1, 1, 1, 1, \ 993: 1, 1, 1, 1, 1, 1, 1, 1, \ 994: 1, 1, 1, 1, 1, 1, 1, 1, \ 995: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 root 996: #endif 1.1 root 997: 998: extern char leaf_reg_remap[]; 999: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1000: 1001: /* The class value for index registers, and the one for base regs. */ 1002: #define INDEX_REG_CLASS GENERAL_REGS 1003: #define BASE_REG_CLASS GENERAL_REGS 1004: 1.1.1.3 root 1005: /* Local macro to handle the two v9 classes of FP regs. */ 1006: #ifdef SPARCV9 1007: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1008: #else 1009: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS) 1010: #endif 1011: 1.1 root 1012: /* Get reg_class from a letter such as appears in the machine description. */ 1013: 1.1.1.3 root 1014: #ifdef SPARCV9 1.1 root 1015: #define REG_CLASS_FROM_LETTER(C) \ 1.1.1.3 root 1016: ((C) == 'f' ? FP_REGS \ 1017: : (C) == 'e' ? EXTRA_FP_REGS \ 1018: : (C) == 'c' ? FPCC_REGS \ 1019: : NO_REGS) 1020: #else 1021: /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for 1022: v8 and v9. */ 1023: #define REG_CLASS_FROM_LETTER(C) \ 1024: ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS) 1025: #endif 1.1 root 1026: 1027: /* The letters I, J, K, L and M in a register constraint string 1028: can be used to stand for particular ranges of immediate operands. 1029: This macro defines what the ranges are. 1030: C is the letter, and VALUE is a constant value. 1031: Return 1 if VALUE is in the range specified by C. 1032: 1033: For SPARC, `I' is used for the range of constants an insn 1034: can actually contain. 1035: `J' is used for the range which is just zero (since that is R0). 1036: `K' is used for constants which can be loaded with a single sethi insn. */ 1037: 1038: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) 1039: 1040: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1041: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ 1042: : (C) == 'J' ? (VALUE) == 0 \ 1043: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ 1044: : 0) 1045: 1046: /* Similar, but for floating constants, and defining letters G and H. 1047: Here VALUE is the CONST_DOUBLE rtx itself. */ 1048: 1049: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1.1.1.2 root 1050: ((C) == 'G' ? fp_zero_operand (VALUE) \ 1.1 root 1051: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1052: : 0) 1053: 1054: /* Given an rtx X being reloaded into a reg required to be 1055: in class CLASS, return the class of reg to actually use. 1056: In general this is just CLASS; but on some machines 1057: in some cases it is preferable to use a more restrictive class. */ 1058: /* We can't load constants into FP registers. We can't load any FP constant 1059: if an 'E' constraint fails to match it. */ 1060: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1061: (CONSTANT_P (X) \ 1.1.1.3 root 1062: && (FP_REG_CLASS_P (CLASS) \ 1.1 root 1063: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1064: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ 1065: || HOST_BITS_PER_INT != BITS_PER_WORD))) \ 1066: ? NO_REGS : (CLASS)) 1067: 1068: /* Return the register class of a scratch register needed to load IN into 1069: a register of class CLASS in MODE. 1070: 1071: On the SPARC, when PIC, we need a temporary when loading some addresses 1072: into a register. 1073: 1074: Also, we need a temporary when loading/storing a HImode/QImode value 1075: between memory and the FPU registers. This can happen when combine puts 1076: a paradoxical subreg in a float/fix conversion insn. */ 1077: 1078: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 root 1079: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ 1080: && (GET_CODE (IN) == MEM \ 1081: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1082: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1083: 1084: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 root 1085: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ 1086: && (GET_CODE (IN) == MEM \ 1087: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1088: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1089: 1090: /* On SPARC it is not possible to directly move data between 1091: GENERAL_REGS and FP_REGS. */ 1.1.1.3 root 1092: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1093: (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1.1 root 1094: 1.1.1.3 root 1095: /* Return the stack location to use for secondary memory needed reloads. 1096: We want to use the reserved location just below the frame pointer. 1097: However, we must ensure that there is a frame, so use assign_stack_local 1098: if the frame size is zero. */ 1.1 root 1099: #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1.1.1.3 root 1100: (get_frame_size () == 0 \ 1.1.1.4 ! root 1101: ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1.1.1.3 root 1102: : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ 1103: GEN_INT (STARTING_FRAME_OFFSET)))) 1104: 1105: /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9 1106: because the movsi and movsf patterns don't handle r/f moves. 1107: For v8 we copy the default definition. */ 1108: #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1109: (TARGET_V9 \ 1.1.1.4 ! root 1110: ? (GET_MODE_BITSIZE (MODE) < 32 \ ! 1111: ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1.1.1.3 root 1112: : MODE) \ 1.1.1.4 ! root 1113: : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ ! 1114: ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1.1.1.3 root 1115: : MODE)) 1.1 root 1116: 1117: /* Return the maximum number of consecutive registers 1118: needed to represent mode MODE in a register of class CLASS. */ 1119: /* On SPARC, this is the size of MODE in words. */ 1120: #define CLASS_MAX_NREGS(CLASS, MODE) \ 1.1.1.3 root 1121: (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1122: : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1 root 1123: 1124: /* Stack layout; function entry, exit and calling. */ 1125: 1126: /* Define the number of register that can hold parameters. 1.1.1.3 root 1127: These two macros are used only in other macro definitions below. 1128: MODE is the mode of the argument. 1129: !v9: All args are passed in %o0-%o5. 1130: v9: Non-float args are passed in %o0-5 and float args are passed in 1131: %f0-%f15. */ 1132: #define NPARM_REGS(MODE) \ 1133: (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6) 1.1 root 1134: 1135: /* Define this if pushing a word on the stack 1136: makes the stack pointer a smaller address. */ 1137: #define STACK_GROWS_DOWNWARD 1138: 1139: /* Define this if the nominal address of the stack frame 1140: is at the high-address end of the local variables; 1141: that is, each additional local variable allocated 1142: goes at a more negative offset in the frame. */ 1143: #define FRAME_GROWS_DOWNWARD 1144: 1145: /* Offset within stack frame to start allocating local variables at. 1146: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1147: first local allocated. Otherwise, it is the offset to the BEGINNING 1148: of the first local allocated. */ 1.1.1.3 root 1149: /* This allows space for one TFmode floating point value. */ 1150: #define STARTING_FRAME_OFFSET \ 1151: (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \ 1152: : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1.1 root 1153: 1154: /* If we generate an insn to push BYTES bytes, 1155: this says how many the stack pointer really advances by. 1156: On SPARC, don't define this because there are no push insns. */ 1157: /* #define PUSH_ROUNDING(BYTES) */ 1158: 1159: /* Offset of first parameter from the argument pointer register value. 1.1.1.3 root 1160: !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1161: even if this function isn't going to use it. 1162: v9: This is 128 for the ins and locals, plus a reserved space of 8. */ 1163: #define FIRST_PARM_OFFSET(FNDECL) \ 1164: (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \ 1165: : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) 1.1 root 1166: 1167: /* When a parameter is passed in a register, stack space is still 1168: allocated for it. */ 1.1.1.3 root 1169: #ifndef SPARCV9 1170: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD) 1171: #endif 1.1 root 1172: 1173: /* Keep the stack pointer constant throughout the function. 1174: This is both an optimization and a necessity: longjmp 1175: doesn't behave itself when the stack pointer moves within 1176: the function! */ 1177: #define ACCUMULATE_OUTGOING_ARGS 1178: 1179: /* Value is the number of bytes of arguments automatically 1180: popped when returning from a subroutine call. 1.1.1.4 ! root 1181: FUNDECL is the declaration node of the function (as a tree), 1.1 root 1182: FUNTYPE is the data type of the function (as a tree), 1183: or for a library call it is an identifier node for the subroutine name. 1184: SIZE is the number of bytes of arguments passed on the stack. */ 1185: 1.1.1.4 ! root 1186: #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1.1 root 1187: 1188: /* Some subroutine macros specific to this machine. 1189: When !TARGET_FPU, put float return values in the general registers, 1190: since we don't have any fp registers. */ 1191: #define BASE_RETURN_VALUE_REG(MODE) \ 1.1.1.3 root 1192: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ 1193: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) 1.1 root 1194: #define BASE_OUTGOING_VALUE_REG(MODE) \ 1.1.1.3 root 1195: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ 1196: : TARGET_FRW ? 8 : 24) \ 1197: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ 1198: : (TARGET_FRW ? 8 : 24))) 1199: #define BASE_PASSING_ARG_REG(MODE) \ 1200: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ 1201: : (8)) 1202: #define BASE_INCOMING_ARG_REG(MODE) \ 1203: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ 1204: : TARGET_FRW ? 8 : 24) \ 1205: : (TARGET_FRW ? 8 : 24)) 1.1 root 1206: 1207: /* Define this macro if the target machine has "register windows". This 1208: C expression returns the register number as seen by the called function 1209: corresponding to register number OUT as seen by the calling function. 1210: Return OUT if register number OUT is not an outbound register. */ 1211: 1212: #define INCOMING_REGNO(OUT) \ 1213: ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1214: 1215: /* Define this macro if the target machine has "register windows". This 1216: C expression returns the register number as seen by the calling function 1217: corresponding to register number IN as seen by the called function. 1218: Return IN if register number IN is not an inbound register. */ 1219: 1220: #define OUTGOING_REGNO(IN) \ 1221: ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1222: 1223: /* Define how to find the value returned by a function. 1224: VALTYPE is the data type of the value (as a tree). 1225: If the precise function being called is known, FUNC is its FUNCTION_DECL; 1226: otherwise, FUNC is 0. */ 1227: 1228: /* On SPARC the value is found in the first "output" register. */ 1229: 1230: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1231: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 1232: 1233: /* But the called function leaves it in the first "input" register. */ 1234: 1235: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1236: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) 1237: 1238: /* Define how to find the value returned by a library function 1239: assuming the value has mode MODE. */ 1240: 1241: #define LIBCALL_VALUE(MODE) \ 1242: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) 1243: 1244: /* 1 if N is a possible register number for a function value 1245: as seen by the caller. 1246: On SPARC, the first "output" reg is used for integer values, 1247: and the first floating point register is used for floating point values. */ 1248: 1249: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1250: 1.1.1.2 root 1251: /* Define the size of space to allocate for the return value of an 1252: untyped_call. */ 1253: 1254: #define APPLY_RESULT_SIZE 16 1255: 1.1 root 1256: /* 1 if N is a possible register number for function argument passing. 1.1.1.3 root 1257: On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */ 1.1 root 1258: 1.1.1.3 root 1259: #define FUNCTION_ARG_REGNO_P(N) \ 1260: (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \ 1261: : ((N) < 14 && (N) > 7)) 1.1 root 1262: 1263: /* Define a data type for recording info about an argument list 1264: during the scan of that argument list. This data type should 1265: hold all necessary information about the function itself 1266: and about the args processed so far, enough to enable macros 1267: such as FUNCTION_ARG to determine where the next arg should go. 1268: 1.1.1.3 root 1269: On SPARC (!v9), this is a single integer, which is a number of words 1.1 root 1270: of arguments scanned so far (including the invisible argument, 1271: if any, which holds the structure-value-address). 1.1.1.3 root 1272: Thus 7 or more means all following args should go on the stack. 1.1 root 1273: 1.1.1.3 root 1274: For v9, we record how many of each type has been passed. Different 1275: types get passed differently. 1276: 1277: - Float args are passed in %f0-15, after which they go to the stack 1278: where floats and doubles are passed 8 byte aligned and long doubles 1279: are passed 16 byte aligned. 1280: - All aggregates are passed by reference. The callee copies 1281: the structure if necessary, except if stdarg/varargs and the struct 1282: matches the ellipse in which case the caller makes a copy. 1283: - Any non-float argument might be split between memory and reg %o5. 1284: ??? I don't think this can ever happen now that structs are no 1285: longer passed in regs. 1286: 1287: For v9 return values: 1288: 1289: - For all aggregates, the caller allocates space for the return value, 1290: and passes the pointer as an implicit first argument, which is 1291: allocated like all other arguments. 1292: - The unimp instruction stuff for structure returns is gone. */ 1293: 1294: #ifdef SPARCV9 1295: enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 }; 1296: struct sparc_args { 1297: int arg_count[2]; /* must be int! (for __builtin_args_info) */ 1298: }; 1299: #define CUMULATIVE_ARGS struct sparc_args 1300: 1301: /* Return index into CUMULATIVE_ARGS. */ 1302: 1303: #define GET_SPARC_ARG_CLASS(MODE) \ 1304: (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT) 1305: 1306: /* Round a register number up to a proper boundary for an arg of mode MODE. 1307: This macro is only used in this file. 1308: 1309: The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */ 1310: 1311: #define ROUND_REG(CUM, MODE) \ 1312: (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 1313: ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ 1314: : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ 1315: + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \ 1316: & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4)) 1317: 1318: #define ROUND_ADVANCE(SIZE) \ 1319: (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1320: 1321: #else /* ! SPARCV9 */ 1.1 root 1322: #define CUMULATIVE_ARGS int 1323: 1.1.1.3 root 1324: #define ROUND_REG(CUM, MODE) (CUM) 1325: 1.1 root 1326: #define ROUND_ADVANCE(SIZE) \ 1327: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1.1.3 root 1328: #endif /* ! SPARCV9 */ 1.1 root 1329: 1330: /* Initialize a variable CUM of type CUMULATIVE_ARGS 1331: for a call to a function whose data type is FNTYPE. 1332: For a library call, FNTYPE is 0. 1333: 1334: On SPARC, the offset always starts at 0: the first parm reg is always 1335: the same reg. */ 1336: 1.1.1.3 root 1337: #ifdef SPARCV9 1338: extern int sparc_arg_count,sparc_n_named_args; 1339: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ 1340: do { \ 1341: (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \ 1342: (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \ 1343: sparc_arg_count = 0; \ 1344: sparc_n_named_args = \ 1345: ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \ 1346: ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \ 1347: + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \ 1348: || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \ 1349: /* Can't tell, treat 'em all as named. */ \ 1350: : 10000); \ 1351: } while (0) 1352: #else 1.1 root 1353: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) 1.1.1.3 root 1354: #endif 1.1 root 1355: 1356: /* Update the data in CUM to advance over an argument 1357: of mode MODE and data type TYPE. 1358: (TYPE is null for libcalls where that information may not be available.) */ 1359: 1.1.1.3 root 1360: #ifdef SPARCV9 1361: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1362: do { \ 1363: (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \ 1364: ROUND_REG ((CUM), (MODE)) \ 1365: + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1366: ? GET_MODE_SIZE (MODE) / 4 \ 1367: : ROUND_ADVANCE ((MODE) == BLKmode \ 1368: ? GET_MODE_SIZE (Pmode) \ 1369: : GET_MODE_SIZE (MODE))); \ 1370: sparc_arg_count++; \ 1371: } while (0) 1372: #else 1.1 root 1373: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1374: ((CUM) += ((MODE) != BLKmode \ 1375: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 1376: : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) 1.1.1.3 root 1377: #endif 1378: 1379: /* Return boolean indicating arg of mode MODE will be passed in a reg. 1380: This macro is only used in this file. */ 1381: 1382: #ifdef SPARCV9 1383: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1384: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ 1385: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ 1386: && ((TYPE)==0 || (MODE) != BLKmode)) 1387: #else 1388: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1389: ((CUM) < NPARM_REGS (SImode) \ 1390: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ 1391: && ((TYPE)==0 || (MODE) != BLKmode \ 1392: || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0))) 1393: #endif 1.1 root 1394: 1395: /* Determine where to put an argument to a function. 1396: Value is zero to push the argument on the stack, 1397: or a hard register in which to store the argument. 1398: 1399: MODE is the argument's machine mode. 1400: TYPE is the data type of the argument (as a tree). 1401: This is null for libcalls where that information may 1402: not be available. 1403: CUM is a variable of type CUMULATIVE_ARGS which gives info about 1404: the preceding args and about the function being called. 1405: NAMED is nonzero if this argument is a named parameter 1406: (otherwise it is an extra parameter matching an ellipsis). */ 1407: 1408: /* On SPARC the first six args are normally in registers 1409: and the rest are pushed. Any arg that starts within the first 6 words 1.1.1.3 root 1410: is at least partially passed in a register unless its data type forbids. 1411: For v9, the first 6 int args are passed in regs and the first N 1412: float args are passed in regs (where N is such that %f0-15 are filled). 1413: The rest are pushed. Any arg that starts within the first 6 words 1.1 root 1414: is at least partially passed in a register unless its data type forbids. */ 1415: 1416: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1417: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1418: ? gen_rtx (REG, (MODE), \ 1419: (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ 1420: : 0) 1.1 root 1421: 1422: /* Define where a function finds its arguments. 1423: This is different from FUNCTION_ARG because of register windows. */ 1424: 1425: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1426: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1427: ? gen_rtx (REG, (MODE), \ 1428: (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ 1429: : 0) 1.1 root 1430: 1431: /* For an arg passed partly in registers and partly in memory, 1432: this is the number of registers used. 1433: For args passed entirely in registers or entirely in memory, zero. 1434: Any arg that starts in the first 6 regs but won't entirely fit in them 1.1.1.3 root 1435: needs partial registers on the Sparc (!v9). On v9, there are no arguments 1436: that are passed partially in registers (??? complex values?). */ 1.1 root 1437: 1.1.1.3 root 1438: #ifndef SPARCV9 1.1 root 1439: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1440: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1441: && ((CUM) + ((MODE) == BLKmode \ 1442: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 1443: : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\ 1444: ? (NPARM_REGS (SImode) - (CUM)) \ 1.1 root 1445: : 0) 1.1.1.3 root 1446: #endif 1.1 root 1447: 1448: /* The SPARC ABI stipulates passing struct arguments (of any size) and 1.1.1.3 root 1449: (!v9) quad-precision floats by invisible reference. 1450: For Pascal, also pass arrays by reference. */ 1.1 root 1451: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1452: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ 1.1.1.3 root 1453: || TREE_CODE (TYPE) == UNION_TYPE \ 1454: || TREE_CODE (TYPE) == ARRAY_TYPE)) \ 1455: || (!TARGET_V9 && MODE == TFmode)) 1456: 1457: /* A C expression that indicates when it is the called function's 1458: responsibility to make copies of arguments passed by reference. 1459: If the callee can determine that the argument won't be modified, it can 1460: avoid the copy. */ 1461: /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't 1462: include the last named argument so we keep track of the args ourselves. */ 1463: 1464: #ifdef SPARCV9 1465: #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ 1466: (sparc_arg_count < sparc_n_named_args) 1467: #endif 1468: 1469: /* Initialize data used by insn expanders. This is called from 1470: init_emit, once for each function, before code is generated. 1471: For v9, clear the temp slot used by float/int DImode conversions. 1472: ??? There is the 16 bytes at [%fp-16], however we'd like to delete this 1473: space at some point. 1474: ??? Use assign_stack_temp? */ 1475: 1476: extern void sparc64_init_expanders (); 1477: extern struct rtx_def *sparc64_fpconv_stack_temp (); 1478: #ifdef SPARCV9 1479: #define INIT_EXPANDERS sparc64_init_expanders () 1480: #endif 1.1 root 1481: 1482: /* Define the information needed to generate branch and scc insns. This is 1483: stored from the compare operation. Note that we can't use "rtx" here 1484: since it hasn't been defined! */ 1485: 1486: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; 1487: 1488: /* Define the function that build the compare insn for scc and bcc. */ 1489: 1490: extern struct rtx_def *gen_compare_reg (); 1.1.1.3 root 1491: 1492: /* This function handles all v9 scc insns */ 1493: 1494: extern int gen_v9_scc (); 1.1 root 1495: 1496: /* Generate the special assembly code needed to tell the assembler whatever 1497: it might need to know about the return value of a function. 1498: 1499: For Sparc assemblers, we need to output a .proc pseudo-op which conveys 1500: information to the assembler relating to peephole optimization (done in 1501: the assembler). */ 1502: 1503: #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1504: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) 1505: 1506: /* Output the label for a function definition. */ 1507: 1508: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1509: do { \ 1510: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1511: ASM_OUTPUT_LABEL (FILE, NAME); \ 1512: } while (0) 1513: 1514: /* This macro generates the assembly code for function entry. 1515: FILE is a stdio stream to output the code to. 1516: SIZE is an int: how many units of temporary storage to allocate. 1517: Refer to the array `regs_ever_live' to determine which registers 1518: to save; `regs_ever_live[I]' is nonzero if register number I 1519: is ever used in the function. This macro is responsible for 1520: knowing which registers should not be saved even if used. */ 1521: 1522: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block 1523: of memory. If any fpu reg is used in the function, we allocate 1524: such a block here, at the bottom of the frame, just in case it's needed. 1525: 1526: If this function is a leaf procedure, then we may choose not 1527: to do a "save" insn. The decision about whether or not 1528: to do this is made in regclass.c. */ 1529: 1.1.1.3 root 1530: extern int leaf_function; 1.1 root 1531: #define FUNCTION_PROLOGUE(FILE, SIZE) \ 1.1.1.3 root 1532: (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \ 1.1 root 1533: : output_function_prologue (FILE, SIZE, leaf_function)) 1534: 1535: /* Output assembler code to FILE to increment profiler label # LABELNO 1536: for profiling a function entry. */ 1537: 1538: #define FUNCTION_PROFILER(FILE, LABELNO) \ 1539: do { \ 1540: fputs ("\tsethi %hi(", (FILE)); \ 1541: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1.1.1.3 root 1542: fputs ("),%o0\n", (FILE)); \ 1543: if (TARGET_MEDANY) \ 1544: fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \ 1545: MEDANY_BASE_REG); \ 1546: fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \ 1.1 root 1547: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1548: fputs ("),%o0,%o0\n", (FILE)); \ 1549: } while (0) 1550: 1551: /* Output assembler code to FILE to initialize this source file's 1552: basic block profiling info, if that has not already been done. */ 1553: 1554: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ 1.1.1.3 root 1555: do { \ 1556: if (TARGET_MEDANY) \ 1557: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ 1558: MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \ 1559: else \ 1560: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ 1561: (LABELNO), (LABELNO)); \ 1562: } while (0) 1.1 root 1563: 1564: /* Output assembler code to FILE to increment the entry-count for 1565: the BLOCKNO'th basic block in this source file. */ 1566: 1567: #define BLOCK_PROFILER(FILE, BLOCKNO) \ 1.1.1.3 root 1568: { \ 1569: int blockn = (BLOCKNO); \ 1570: if (TARGET_MEDANY) \ 1571: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ 1572: 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ 1573: else \ 1574: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ 1575: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ 1576: 4 * blockn, 4 * blockn, 4 * blockn); \ 1.1 root 1577: } 1578: 1579: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1580: the stack pointer does not matter. The value is tested only in 1581: functions that have frame pointers. 1582: No definition is equivalent to always zero. */ 1583: 1584: extern int current_function_calls_alloca; 1585: extern int current_function_outgoing_args_size; 1586: 1587: #define EXIT_IGNORE_STACK \ 1588: (get_frame_size () != 0 \ 1589: || current_function_calls_alloca || current_function_outgoing_args_size) 1590: 1591: /* This macro generates the assembly code for function exit, 1592: on machines that need it. If FUNCTION_EPILOGUE is not defined 1593: then individual return instructions are generated for each 1594: return statement. Args are same as for FUNCTION_PROLOGUE. 1595: 1596: The function epilogue should not depend on the current stack pointer! 1597: It should use the frame pointer only. This is mandatory because 1598: of alloca; we also take advantage of it to omit stack adjustments 1599: before returning. */ 1600: 1601: /* This declaration is needed due to traditional/ANSI 1602: incompatibilities which cannot be #ifdefed away 1603: because they occur inside of macros. Sigh. */ 1604: extern union tree_node *current_function_decl; 1605: 1606: #define FUNCTION_EPILOGUE(FILE, SIZE) \ 1.1.1.3 root 1607: (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \ 1.1 root 1608: : output_function_epilogue (FILE, SIZE, leaf_function)) 1609: 1610: #define DELAY_SLOTS_FOR_EPILOGUE \ 1.1.1.3 root 1611: (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1) 1.1 root 1612: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ 1.1.1.3 root 1613: (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ 1.1 root 1614: : eligible_for_epilogue_delay (trial, slots_filled)) 1.1.1.2 root 1615: 1.1 root 1616: /* Output assembler code for a block containing the constant parts 1617: of a trampoline, leaving space for the variable parts. */ 1618: 1.1.1.4 ! root 1619: /* On 32 bit sparcs, the trampoline contains five instructions: 1.1.1.2 root 1620: sethi #TOP_OF_FUNCTION,%g1 1621: or #BOTTOM_OF_FUNCTION,%g1,%g1 1622: sethi #TOP_OF_STATIC,%g2 1623: jmp g1 1.1.1.4 ! root 1624: or #BOTTOM_OF_STATIC,%g2,%g2 ! 1625: ! 1626: On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate ! 1627: constants (plus some padding): ! 1628: rd %pc,%g1 ! 1629: ldx[%g1+20],%g5 ! 1630: ldx[%g1+28],%g1 ! 1631: jmp %g1 ! 1632: nop ! 1633: nop ! 1634: .xword context ! 1635: .xword function */ ! 1636: ! 1637: #define TRAMPOLINE_TEMPLATE(FILE) \ ! 1638: do { \ ! 1639: if (TARGET_V9) \ ! 1640: { \ ! 1641: fprintf (FILE, "\trd %%pc,%%g1\n"); \ ! 1642: fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \ ! 1643: fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \ ! 1644: fprintf (FILE, "\tjmp %%g1\n"); \ ! 1645: fprintf (FILE, "\tnop\n"); \ ! 1646: fprintf (FILE, "\tnop\n"); \ ! 1647: /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \ ! 1648: fprintf (FILE, "\t.word 0,0,0,0\n"); \ ! 1649: } \ ! 1650: else \ ! 1651: { \ ! 1652: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1653: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1654: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1655: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \ ! 1656: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1657: } \ ! 1658: } while (0) 1.1 root 1659: 1660: /* Length in units of the trampoline for entering a nested function. */ 1661: 1.1.1.4 ! root 1662: #define TRAMPOLINE_SIZE (TARGET_V9 ? 40 : 20) 1.1 root 1663: 1664: /* Emit RTL insns to initialize the variable parts of a trampoline. 1665: FNADDR is an RTX for the address of the function's pure code. 1.1.1.3 root 1666: CXT is an RTX for the static chain value for the function. */ 1.1.1.2 root 1667: 1.1.1.3 root 1668: void sparc_initialize_trampoline (); 1669: void sparc64_initialize_trampoline (); 1670: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1671: do { \ 1672: if (TARGET_V9) \ 1673: sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1674: else \ 1675: sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1676: } while (0) 1.1.1.2 root 1677: 1.1 root 1678: /* Generate necessary RTL for __builtin_saveregs(). 1679: ARGLIST is the argument list; see expr.c. */ 1680: extern struct rtx_def *sparc_builtin_saveregs (); 1681: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) 1682: 1683: /* Generate RTL to flush the register windows so as to make arbitrary frames 1684: available. */ 1685: #define SETUP_FRAME_ADDRESSES() \ 1686: emit_insn (gen_flush_register_windows ()) 1687: 1688: /* Given an rtx for the address of a frame, 1689: return an rtx for the address of the word in the frame 1.1.1.3 root 1690: that holds the dynamic chain--the previous frame's address. 1691: ??? -mflat support? */ 1.1 root 1692: #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1.1.1.3 root 1693: gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD)) 1.1 root 1694: 1695: /* The return address isn't on the stack, it is in a register, so we can't 1696: access it from the current frame pointer. We can access it from the 1697: previous frame pointer though by reading a value from the register window 1698: save area. */ 1699: #define RETURN_ADDR_IN_PREVIOUS_FRAME 1700: 1.1.1.4 ! root 1701: /* This is the offset of the return address to the true next instruction to be ! 1702: executed for normal void functions. */ ! 1703: #define NORMAL_RETURN_ADDR_OFFSET (8) ! 1704: 1.1 root 1705: /* The current return address is in %i7. The return address of anything 1706: farther back is in the register window save area at [%fp+60]. */ 1707: /* ??? This ignores the fact that the actual return address is +8 for normal 1708: returns, and +12 for structure returns. */ 1709: #define RETURN_ADDR_RTX(count, frame) \ 1710: ((count == -1) \ 1711: ? gen_rtx (REG, Pmode, 31) \ 1.1.1.4 ! root 1712: : gen_rtx (MEM, Pmode, \ ! 1713: memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))) 1.1 root 1714: 1715: /* Addressing modes, and classification of registers for them. */ 1716: 1717: /* #define HAVE_POST_INCREMENT */ 1718: /* #define HAVE_POST_DECREMENT */ 1719: 1720: /* #define HAVE_PRE_DECREMENT */ 1721: /* #define HAVE_PRE_INCREMENT */ 1722: 1723: /* Macros to check register numbers against specific register classes. */ 1724: 1725: /* These assume that REGNO is a hard or pseudo reg number. 1726: They give nonzero only if REGNO is a hard reg of the suitable class 1727: or a pseudo reg currently allocated to a suitable hard reg. 1728: Since they use reg_renumber, they are safe only once reg_renumber 1729: has been allocated, which happens in local-alloc.c. */ 1730: 1731: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1732: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1733: #define REGNO_OK_FOR_BASE_P(REGNO) \ 1734: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1735: #define REGNO_OK_FOR_FP_P(REGNO) \ 1.1.1.3 root 1736: (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \ 1737: || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32))) 1738: #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1739: (TARGET_V9 \ 1740: && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4)) 1.1 root 1741: 1742: /* Now macros that check whether X is a register and also, 1743: strictly, whether it is in a specified class. 1744: 1745: These macros are specific to the SPARC, and may be used only 1746: in code for printing assembler insns and in conditions for 1747: define_optimization. */ 1748: 1749: /* 1 if X is an fp register. */ 1750: 1751: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1752: 1753: /* Maximum number of registers that can appear in a valid memory address. */ 1754: 1755: #define MAX_REGS_PER_ADDRESS 2 1756: 1.1.1.2 root 1757: /* Recognize any constant value that is a valid address. 1758: When PIC, we do not accept an address that would require a scratch reg 1759: to load into a register. */ 1.1 root 1760: 1761: #define CONSTANT_ADDRESS_P(X) \ 1762: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1.1.1.2 root 1763: || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 1764: || (GET_CODE (X) == CONST \ 1765: && ! (flag_pic && pic_address_needs_scratch (X)))) 1766: 1767: /* Define this, so that when PIC, reload won't try to reload invalid 1768: addresses which require two reload registers. */ 1769: 1770: #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) 1.1 root 1771: 1772: /* Nonzero if the constant value X is a legitimate general operand. 1773: Anything can be made to work except floating point constants. */ 1774: 1775: #define LEGITIMATE_CONSTANT_P(X) \ 1776: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) 1777: 1778: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1779: and check its validity for a certain class. 1780: We have two alternate definitions for each of them. 1781: The usual definition accepts all pseudo regs; the other rejects 1782: them unless they have been allocated suitable hard regs. 1783: The symbol REG_OK_STRICT causes the latter definition to be used. 1784: 1785: Most source files want to accept pseudo regs in the hope that 1786: they will get allocated to the class that the insn wants them to be in. 1787: Source files for reload pass need to be strict. 1788: After reload, it makes no difference, since pseudo regs have 1789: been eliminated by then. */ 1790: 1791: /* Optional extra constraints for this machine. Borrowed from romp.h. 1792: 1793: For the SPARC, `Q' means that this is a memory operand but not a 1794: symbolic memory operand. Note that an unassigned pseudo register 1795: is such a memory operand. Needed because reload will generate 1796: these things in insns and then not re-recognize the insns, causing 1797: constrain_operands to fail. 1798: 1.1.1.3 root 1799: `S' handles constraints for calls. ??? So where is it? */ 1.1 root 1800: 1801: #ifndef REG_OK_STRICT 1802: 1803: /* Nonzero if X is a hard reg that can be used as an index 1804: or if it is a pseudo reg. */ 1.1.1.3 root 1805: #define REG_OK_FOR_INDEX_P(X) \ 1806: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) 1.1 root 1807: /* Nonzero if X is a hard reg that can be used as a base reg 1808: or if it is a pseudo reg. */ 1.1.1.3 root 1809: #define REG_OK_FOR_BASE_P(X) \ 1810: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) 1811: 1812: /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ 1.1 root 1813: 1814: #define EXTRA_CONSTRAINT(OP, C) \ 1815: ((C) == 'Q' \ 1816: ? ((GET_CODE (OP) == MEM \ 1.1.1.3 root 1817: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ 1.1 root 1818: && ! symbolic_memory_operand (OP, VOIDmode)) \ 1819: || (reload_in_progress && GET_CODE (OP) == REG \ 1820: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ 1.1.1.3 root 1821: : ! TARGET_V9 && (C) == 'T' \ 1.1 root 1822: ? (mem_aligned_8 (OP)) \ 1.1.1.3 root 1823: : ! TARGET_V9 && (C) == 'U' \ 1.1 root 1824: ? (register_ok_for_ldd (OP)) \ 1825: : 0) 1826: 1827: #else 1828: 1829: /* Nonzero if X is a hard reg that can be used as an index. */ 1830: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1831: /* Nonzero if X is a hard reg that can be used as a base reg. */ 1832: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1833: 1834: #define EXTRA_CONSTRAINT(OP, C) \ 1835: ((C) == 'Q' \ 1836: ? (GET_CODE (OP) == REG \ 1837: ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ 1838: && reg_renumber[REGNO (OP)] < 0) \ 1839: : GET_CODE (OP) == MEM) \ 1.1.1.3 root 1840: : ! TARGET_V9 && (C) == 'T' \ 1.1.1.2 root 1841: ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ 1.1.1.3 root 1842: : ! TARGET_V9 && (C) == 'U' \ 1.1.1.2 root 1843: ? (GET_CODE (OP) == REG \ 1844: && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ 1845: || reg_renumber[REGNO (OP)] > 0) \ 1846: && register_ok_for_ldd (OP)) : 0) 1.1 root 1847: #endif 1848: 1849: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1850: that is a valid memory address for an instruction. 1851: The MODE argument is the machine mode for the MEM expression 1852: that wants to use this address. 1853: 1854: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1855: ordinarily. This changes a bit when generating PIC. 1856: 1857: If you change this, execute "rm explow.o recog.o reload.o". */ 1858: 1859: #define RTX_OK_FOR_BASE_P(X) \ 1860: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1861: || (GET_CODE (X) == SUBREG \ 1862: && GET_CODE (SUBREG_REG (X)) == REG \ 1863: && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1864: 1865: #define RTX_OK_FOR_INDEX_P(X) \ 1866: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1867: || (GET_CODE (X) == SUBREG \ 1868: && GET_CODE (SUBREG_REG (X)) == REG \ 1869: && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1870: 1871: #define RTX_OK_FOR_OFFSET_P(X) \ 1872: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) 1873: 1874: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1875: { if (RTX_OK_FOR_BASE_P (X)) \ 1876: goto ADDR; \ 1877: else if (GET_CODE (X) == PLUS) \ 1878: { \ 1879: register rtx op0 = XEXP (X, 0); \ 1880: register rtx op1 = XEXP (X, 1); \ 1881: if (flag_pic && op0 == pic_offset_table_rtx) \ 1882: { \ 1883: if (RTX_OK_FOR_BASE_P (op1)) \ 1884: goto ADDR; \ 1885: else if (flag_pic == 1 \ 1886: && GET_CODE (op1) != REG \ 1887: && GET_CODE (op1) != LO_SUM \ 1.1.1.2 root 1888: && GET_CODE (op1) != MEM \ 1889: && (GET_CODE (op1) != CONST_INT \ 1890: || SMALL_INT (op1))) \ 1.1 root 1891: goto ADDR; \ 1892: } \ 1893: else if (RTX_OK_FOR_BASE_P (op0)) \ 1894: { \ 1895: if (RTX_OK_FOR_INDEX_P (op1) \ 1896: || RTX_OK_FOR_OFFSET_P (op1)) \ 1897: goto ADDR; \ 1898: } \ 1899: else if (RTX_OK_FOR_BASE_P (op1)) \ 1900: { \ 1901: if (RTX_OK_FOR_INDEX_P (op0) \ 1902: || RTX_OK_FOR_OFFSET_P (op0)) \ 1903: goto ADDR; \ 1904: } \ 1905: } \ 1906: else if (GET_CODE (X) == LO_SUM) \ 1907: { \ 1908: register rtx op0 = XEXP (X, 0); \ 1909: register rtx op1 = XEXP (X, 1); \ 1910: if (RTX_OK_FOR_BASE_P (op0) \ 1.1.1.3 root 1911: && CONSTANT_P (op1) \ 1912: /* We can't allow TFmode, because an offset \ 1913: greater than or equal to the alignment (8) \ 1914: may cause the LO_SUM to overflow. */ \ 1915: && MODE != TFmode) \ 1.1 root 1916: goto ADDR; \ 1917: } \ 1918: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ 1919: goto ADDR; \ 1920: } 1921: 1922: /* Try machine-dependent ways of modifying an illegitimate address 1923: to be legitimate. If we find one, return the new, valid address. 1924: This macro is used in only one place: `memory_address' in explow.c. 1925: 1926: OLDX is the address as it was before break_out_memory_refs was called. 1927: In some cases it is useful to look at this to decide what needs to be done. 1928: 1929: MODE and WIN are passed so that this macro can use 1930: GO_IF_LEGITIMATE_ADDRESS. 1931: 1932: It is always safe for this macro to do nothing. It exists to recognize 1933: opportunities to optimize the output. */ 1934: 1935: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 1936: extern struct rtx_def *legitimize_pic_address (); 1937: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1938: { rtx sparc_x = (X); \ 1939: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ 1940: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1941: force_operand (XEXP (X, 0), NULL_RTX)); \ 1942: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ 1943: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1944: force_operand (XEXP (X, 1), NULL_RTX)); \ 1945: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ 1946: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ 1947: XEXP (X, 1)); \ 1948: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ 1949: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1950: force_operand (XEXP (X, 1), NULL_RTX)); \ 1951: if (sparc_x != (X) && memory_address_p (MODE, X)) \ 1952: goto WIN; \ 1.1.1.2 root 1953: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ 1.1 root 1954: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ 1955: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1956: copy_to_mode_reg (Pmode, XEXP (X, 1))); \ 1957: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ 1958: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1959: copy_to_mode_reg (Pmode, XEXP (X, 0))); \ 1960: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 1961: || GET_CODE (X) == LABEL_REF) \ 1962: (X) = gen_rtx (LO_SUM, Pmode, \ 1963: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ 1964: if (memory_address_p (MODE, X)) \ 1965: goto WIN; } 1966: 1967: /* Go to LABEL if ADDR (a legitimate address expression) 1968: has an effect that depends on the machine mode it is used for. 1969: On the SPARC this is never true. */ 1970: 1971: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) 1.1.1.3 root 1972: 1973: /* If we are referencing a function make the SYMBOL_REF special. 1974: In the Medium/Anywhere code model, %g4 points to the data segment so we 1975: must not add it to function addresses. */ 1976: 1977: #define ENCODE_SECTION_INFO(DECL) \ 1978: do { \ 1979: if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ 1980: SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ 1981: } while (0) 1.1 root 1982: 1983: /* Specify the machine mode that this machine uses 1984: for the index in the tablejump instruction. */ 1.1.1.3 root 1985: #define CASE_VECTOR_MODE Pmode 1.1 root 1986: 1987: /* Define this if the tablejump instruction expects the table 1988: to contain offsets from the address of the table. 1989: Do not define this if the table should contain absolute addresses. */ 1990: /* #define CASE_VECTOR_PC_RELATIVE */ 1991: 1992: /* Specify the tree operation to be used to convert reals to integers. */ 1993: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1994: 1995: /* This is the kind of divide that is easiest to do in the general case. */ 1996: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1997: 1998: /* Define this as 1 if `char' should by default be signed; else as 0. */ 1999: #define DEFAULT_SIGNED_CHAR 1 2000: 2001: /* Max number of bytes we can move from memory to memory 2002: in one reasonably fast instruction. */ 2003: #define MOVE_MAX 8 2004: 2005: #if 0 /* Sun 4 has matherr, so this is no good. */ 2006: /* This is the value of the error code EDOM for this machine, 2007: used by the sqrt instruction. */ 2008: #define TARGET_EDOM 33 2009: 2010: /* This is how to refer to the variable errno. */ 2011: #define GEN_ERRNO_RTX \ 2012: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) 2013: #endif /* 0 */ 2014: 1.1.1.2 root 2015: /* Define if operations between registers always perform the operation 2016: on the full register even if a narrower mode is specified. */ 2017: #define WORD_REGISTER_OPERATIONS 2018: 2019: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2020: will either zero-extend or sign-extend. The value of this macro should 2021: be the code that says which one of the two operations is implicitly 2022: done, NIL if none. */ 2023: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1.1 root 2024: 2025: /* Nonzero if access to memory by bytes is slow and undesirable. 2026: For RISC chips, it means that access to memory by bytes is no 2027: better than access by words when possible, so grab a whole word 2028: and maybe make use of that. */ 2029: #define SLOW_BYTE_ACCESS 1 2030: 2031: /* We assume that the store-condition-codes instructions store 0 for false 2032: and some other value for true. This is the value stored for true. */ 2033: 2034: #define STORE_FLAG_VALUE 1 2035: 2036: /* When a prototype says `char' or `short', really pass an `int'. */ 2037: #define PROMOTE_PROTOTYPES 2038: 1.1.1.2 root 2039: /* Define this to be nonzero if shift instructions ignore all but the low-order 2040: few bits. */ 2041: #define SHIFT_COUNT_TRUNCATED 1 1.1 root 2042: 2043: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2044: is done just by pretending it is already truncated. */ 2045: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2046: 2047: /* Specify the machine mode that pointers have. 2048: After generation of rtl, the compiler makes no further distinction 2049: between pointers and any other objects of this machine mode. */ 1.1.1.3 root 2050: #define Pmode (TARGET_PTR64 ? DImode : SImode) 1.1 root 2051: 2052: /* Generate calls to memcpy, memcmp and memset. */ 2053: #define TARGET_MEM_FUNCTIONS 2054: 2055: /* Add any extra modes needed to represent the condition code. 2056: 2057: On the Sparc, we have a "no-overflow" mode which is used when an add or 2058: subtract insn is used to set the condition code. Different branches are 2059: used in this case for some operations. 2060: 2061: We also have two modes to indicate that the relevant condition code is 2062: in the floating-point condition code register. One for comparisons which 2063: will generate an exception if the result is unordered (CCFPEmode) and 2064: one for comparisons which will never trap (CCFPmode). This really should 1.1.1.3 root 2065: be a separate register, but we don't want to go to 65 registers. 2066: 2067: CCXmode and CCX_NOOVmode are only used by v9. */ 2068: 2069: #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode 1.1 root 2070: 2071: /* Define the names for the modes specified above. */ 1.1.1.3 root 2072: 2073: #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" 1.1 root 2074: 2075: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2076: return the mode to be used for the comparison. For floating-point, 2077: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a 1.1.1.2 root 2078: PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2079: processing is needed. */ 1.1 root 2080: #define SELECT_CC_MODE(OP,X,Y) \ 2081: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1.1.1.2 root 2082: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ 2083: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 2084: || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ 1.1.1.3 root 2085: ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ 2086: : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode))) 2087: 2088: /* Return non-zero if SELECT_CC_MODE will never return MODE for a 2089: floating point inequality comparison. */ 2090: 2091: #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 1.1 root 2092: 2093: /* A function address in a call instruction 2094: is a byte address (for indexing purposes) 2095: so give the MEM rtx a byte's mode. */ 2096: #define FUNCTION_MODE SImode 2097: 2098: /* Define this if addresses of constant functions 2099: shouldn't be put through pseudo regs where they can be cse'd. 2100: Desirable on machines where ordinary constants are expensive 2101: but a CALL with constant address is cheap. */ 2102: #define NO_FUNCTION_CSE 2103: 2104: /* alloca should avoid clobbering the old register save area. */ 2105: #define SETJMP_VIA_SAVE_AREA 2106: 2107: /* Define subroutines to call to handle multiply and divide. 2108: Use the subroutines that Sun's library provides. 2109: The `*' prevents an underscore from being prepended by the compiler. */ 2110: 2111: #define DIVSI3_LIBCALL "*.div" 2112: #define UDIVSI3_LIBCALL "*.udiv" 2113: #define MODSI3_LIBCALL "*.rem" 2114: #define UMODSI3_LIBCALL "*.urem" 2115: /* .umul is a little faster than .mul. */ 2116: #define MULSI3_LIBCALL "*.umul" 2117: 1.1.1.3 root 2118: /* Define library calls for quad FP operations. These are all part of the 2119: SPARC ABI. */ 2120: #define ADDTF3_LIBCALL "_Q_add" 2121: #define SUBTF3_LIBCALL "_Q_sub" 1.1.1.4 ! root 2122: #define NEGTF2_LIBCALL "_Q_neg" 1.1.1.3 root 2123: #define MULTF3_LIBCALL "_Q_mul" 2124: #define DIVTF3_LIBCALL "_Q_div" 2125: #define FLOATSITF2_LIBCALL "_Q_itoq" 2126: #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" 2127: #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" 2128: #define EXTENDSFTF2_LIBCALL "_Q_stoq" 2129: #define TRUNCTFSF2_LIBCALL "_Q_qtos" 2130: #define EXTENDDFTF2_LIBCALL "_Q_dtoq" 2131: #define TRUNCTFDF2_LIBCALL "_Q_qtod" 2132: #define EQTF2_LIBCALL "_Q_feq" 2133: #define NETF2_LIBCALL "_Q_fne" 2134: #define GTTF2_LIBCALL "_Q_fgt" 2135: #define GETF2_LIBCALL "_Q_fge" 2136: #define LTTF2_LIBCALL "_Q_flt" 2137: #define LETF2_LIBCALL "_Q_fle" 2138: 2139: /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because 2140: with soft-float, the SFmode and DFmode sqrt instructions will be absent, 2141: and the compiler will notice and try to use the TFmode sqrt instruction 2142: for calls to the builtin function sqrt, but this fails. */ 1.1.1.4 ! root 2143: #define INIT_TARGET_OPTABS \ ! 2144: do { \ ! 2145: add_optab->handlers[(int) TFmode].libfunc \ ! 2146: = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \ ! 2147: sub_optab->handlers[(int) TFmode].libfunc \ ! 2148: = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \ ! 2149: neg_optab->handlers[(int) TFmode].libfunc \ ! 2150: = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \ ! 2151: smul_optab->handlers[(int) TFmode].libfunc \ ! 2152: = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \ ! 2153: flodiv_optab->handlers[(int) TFmode].libfunc \ ! 2154: = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \ ! 2155: eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \ ! 2156: netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \ ! 2157: gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \ ! 2158: getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \ ! 2159: lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \ ! 2160: letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \ ! 2161: trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \ ! 2162: trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \ ! 2163: extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \ ! 2164: extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \ ! 2165: floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \ ! 2166: fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \ ! 2167: fixunstfsi_libfunc \ ! 2168: = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \ ! 2169: if (TARGET_FPU) \ ! 2170: sqrt_optab->handlers[(int) TFmode].libfunc \ ! 2171: = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \ ! 2172: INIT_SUBTARGET_OPTABS; \ 1.1.1.3 root 2173: } while (0) 2174: 2175: /* This is meant to be redefined in the host dependent files */ 2176: #define INIT_SUBTARGET_OPTABS 2177: 1.1 root 2178: /* Compute the cost of computing a constant rtl expression RTX 2179: whose rtx-code is CODE. The body of this macro is a portion 2180: of a switch statement. If the code is computed here, 2181: return it with a return statement. Otherwise, break from the switch. */ 2182: 2183: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 2184: case CONST_INT: \ 2185: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ 2186: return 0; \ 2187: case HIGH: \ 2188: return 2; \ 2189: case CONST: \ 2190: case LABEL_REF: \ 2191: case SYMBOL_REF: \ 2192: return 4; \ 2193: case CONST_DOUBLE: \ 2194: if (GET_MODE (RTX) == DImode) \ 2195: if ((XINT (RTX, 3) == 0 \ 2196: && (unsigned) XINT (RTX, 2) < 0x1000) \ 2197: || (XINT (RTX, 3) == -1 \ 2198: && XINT (RTX, 2) < 0 \ 2199: && XINT (RTX, 2) >= -0x1000)) \ 2200: return 0; \ 2201: return 8; 2202: 1.1.1.3 root 2203: /* Compute the cost of an address. For the sparc, all valid addresses are 2204: the same cost. 2205: ??? Is this true for v9? */ 1.1 root 2206: 1.1.1.3 root 2207: #define ADDRESS_COST(RTX) 1 1.1 root 2208: 2209: /* Compute extra cost of moving data between one register class 1.1.1.3 root 2210: and another. 2211: ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */ 1.1 root 2212: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 1.1.1.3 root 2213: (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \ 2214: || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2) 1.1 root 2215: 2216: /* Provide the costs of a rtl expression. This is in the body of a 2217: switch on CODE. The purpose for the cost of MULT is to encourage 2218: `synth_mult' to find a synthetic multiply when reasonable. 2219: 2220: If we need more than 12 insns to do a multiply, then go out-of-line, 2221: since the call overhead will be < 10% of the cost of the multiply. */ 2222: 2223: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 2224: case MULT: \ 1.1.1.4 ! root 2225: return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ 1.1 root 2226: case DIV: \ 2227: case UDIV: \ 2228: case MOD: \ 2229: case UMOD: \ 2230: return COSTS_N_INSNS (25); \ 2231: /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ 2232: so that cse will favor the latter. */ \ 2233: case FLOAT: \ 2234: case FIX: \ 2235: return 19; 2236: 1.1.1.3 root 2237: /* Adjust the cost of dependencies. */ 2238: #define ADJUST_COST(INSN,LINK,DEP,COST) \ 2239: if (TARGET_SUPERSPARC) \ 2240: (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST) 2241: 1.1 root 2242: /* Conditional branches with empty delay slots have a length of two. */ 2243: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2244: if (GET_CODE (INSN) == CALL_INSN \ 2245: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ 2246: LENGTH += 1; 2247: 2248: /* Control the assembler format that we output. */ 2249: 2250: /* Output at beginning of assembler file. */ 2251: 2252: #define ASM_FILE_START(file) 2253: 2254: /* Output to assembler file text saying following lines 2255: may contain character constants, extra white space, comments, etc. */ 2256: 2257: #define ASM_APP_ON "" 2258: 2259: /* Output to assembler file text saying following lines 2260: no longer contain unusual constructs. */ 2261: 2262: #define ASM_APP_OFF "" 2263: 1.1.1.3 root 2264: /* ??? Try to make the style consistent here (_OP?). */ 2265: 2266: #define ASM_LONGLONG ".xword" 1.1 root 2267: #define ASM_LONG ".word" 2268: #define ASM_SHORT ".half" 2269: #define ASM_BYTE_OP ".byte" 1.1.1.3 root 2270: #define ASM_FLOAT ".single" 2271: #define ASM_DOUBLE ".double" 2272: #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ 1.1 root 2273: 2274: /* Output before read-only data. */ 2275: 2276: #define TEXT_SECTION_ASM_OP ".text" 2277: 2278: /* Output before writable data. */ 2279: 2280: #define DATA_SECTION_ASM_OP ".data" 2281: 2282: /* How to refer to registers in assembler output. 2283: This sequence is indexed by compiler's hard-register-number (see above). */ 2284: 1.1.1.3 root 2285: #ifdef SPARCV9 2286: #define REGISTER_NAMES \ 2287: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2288: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2289: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2290: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2291: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2292: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2293: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2294: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2295: "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2296: "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2297: "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2298: "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2299: "%fcc0", "%fcc1", "%fcc2", "%fcc3"} 2300: #else 1.1 root 2301: #define REGISTER_NAMES \ 2302: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2303: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2304: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2305: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2306: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2307: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2308: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2309: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} 1.1.1.3 root 2310: #endif 1.1 root 2311: 2312: /* Define additional names for use in asm clobbers and asm declarations. 2313: 2314: We define the fake Condition Code register as an alias for reg 0 (which 2315: is our `condition code' register), so that condition codes can easily 2316: be clobbered by an asm. No such register actually exists. Condition 2317: codes are partly stored in the PSR and partly in the FSR. */ 2318: 2319: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} 2320: 2321: /* How to renumber registers for dbx and gdb. */ 2322: 2323: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 2324: 2325: /* On Sun 4, this limit is 2048. We use 1500 to be safe, 2326: since the length can run past this up to a continuation point. */ 2327: #define DBX_CONTIN_LENGTH 1500 2328: 2329: /* This is how to output a note to DBX telling it the line number 2330: to which the following sequence of instructions corresponds. 2331: 2332: This is needed for SunOS 4.0, and should not hurt for 3.2 2333: versions either. */ 2334: #define ASM_OUTPUT_SOURCE_LINE(file, line) \ 2335: { static int sym_lineno = 1; \ 2336: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ 2337: line, sym_lineno, sym_lineno); \ 2338: sym_lineno += 1; } 2339: 2340: /* This is how to output the definition of a user-level label named NAME, 2341: such as the label on a static function or variable NAME. */ 2342: 2343: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 2344: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 2345: 2346: /* This is how to output a command to make the user-level label named NAME 2347: defined for reference from other files. */ 2348: 2349: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 2350: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) 2351: 2352: /* This is how to output a reference to a user-level label named NAME. 2353: `assemble_name' uses this. */ 2354: 2355: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2356: fprintf (FILE, "_%s", NAME) 2357: 2358: /* This is how to output a definition of an internal numbered label where 2359: PREFIX is the class of label and NUM is the number within the class. */ 2360: 2361: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 2362: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 2363: 2364: /* This is how to output a reference to an internal numbered label where 2365: PREFIX is the class of label and NUM is the number within the class. */ 2366: /* FIXME: This should be used throughout gcc, and documented in the texinfo 2367: files. There is no reason you should have to allocate a buffer and 2368: `sprintf' to reference an internal label (as opposed to defining it). */ 2369: 2370: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ 2371: fprintf (FILE, "%s%d", PREFIX, NUM) 2372: 2373: /* This is how to store into the string LABEL 2374: the symbol_ref name of an internal numbered label where 2375: PREFIX is the class of label and NUM is the number within the class. 2376: This is suitable for output with `assemble_name'. */ 2377: 2378: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2379: sprintf (LABEL, "*%s%d", PREFIX, NUM) 2380: 2381: /* This is how to output an assembler line defining a `double' constant. */ 2382: 2383: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 2384: { \ 1.1.1.2 root 2385: long t[2]; \ 2386: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ 2387: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2388: ASM_LONG, t[0], ASM_LONG, t[1]); \ 1.1 root 2389: } 2390: 2391: /* This is how to output an assembler line defining a `float' constant. */ 2392: 2393: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 2394: { \ 1.1.1.2 root 2395: long t; \ 2396: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ 2397: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ 2398: } \ 1.1 root 2399: 2400: /* This is how to output an assembler line defining a `long double' 2401: constant. */ 2402: 2403: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ 2404: { \ 2405: long t[4]; \ 2406: REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ 2407: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2408: ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ 2409: } 2410: 2411: /* This is how to output an assembler line defining an `int' constant. */ 2412: 2413: #define ASM_OUTPUT_INT(FILE,VALUE) \ 2414: ( fprintf (FILE, "\t%s\t", ASM_LONG), \ 2415: output_addr_const (FILE, (VALUE)), \ 2416: fprintf (FILE, "\n")) 2417: 2418: /* This is how to output an assembler line defining a DImode constant. */ 2419: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ 2420: output_double_int (FILE, VALUE) 2421: 2422: /* Likewise for `char' and `short' constants. */ 2423: 2424: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 2425: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ 2426: output_addr_const (FILE, (VALUE)), \ 2427: fprintf (FILE, "\n")) 2428: 2429: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 2430: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ 2431: output_addr_const (FILE, (VALUE)), \ 2432: fprintf (FILE, "\n")) 2433: 2434: /* This is how to output an assembler line for a numeric constant byte. */ 2435: 2436: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 2437: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) 2438: 2439: /* This is how to output an element of a case-vector that is absolute. */ 2440: 2441: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2442: do { \ 2443: char label[30]; \ 2444: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 root 2445: if (Pmode == SImode) \ 2446: fprintf (FILE, "\t.word\t"); \ 2447: else if (TARGET_ENV32) \ 2448: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ 2449: else \ 2450: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2451: assemble_name (FILE, label); \ 2452: fprintf (FILE, "\n"); \ 2453: } while (0) 2454: 2455: /* This is how to output an element of a case-vector that is relative. 2456: (SPARC uses such vectors only when generating PIC.) */ 2457: 2458: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 2459: do { \ 2460: char label[30]; \ 2461: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 root 2462: if (Pmode == SImode) \ 2463: fprintf (FILE, "\t.word\t"); \ 2464: else if (TARGET_ENV32) \ 2465: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ 2466: else \ 2467: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2468: assemble_name (FILE, label); \ 2469: fprintf (FILE, "-1b\n"); \ 2470: } while (0) 2471: 2472: /* This is how to output an assembler line 2473: that says to advance the location counter 2474: to a multiple of 2**LOG bytes. */ 2475: 2476: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2477: if ((LOG) != 0) \ 2478: fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2479: 2480: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2481: fprintf (FILE, "\t.skip %u\n", (SIZE)) 2482: 2483: /* This says how to output an assembler line 2484: to define a global common symbol. */ 2485: 2486: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1.1.1.3 root 2487: ( fputs ("\t.common ", (FILE)), \ 1.1 root 2488: assemble_name ((FILE), (NAME)), \ 1.1.1.3 root 2489: fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) 1.1 root 2490: 1.1.1.3 root 2491: /* This says how to output an assembler line to define a local common 2492: symbol. */ 1.1 root 2493: 1.1.1.3 root 2494: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2495: ( fputs ("\t.reserve ", (FILE)), \ 2496: assemble_name ((FILE), (NAME)), \ 2497: fprintf ((FILE), ",%u,\"bss\",%u\n", \ 2498: (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1.1 root 2499: 2500: /* Store in OUTPUT a string (made with alloca) containing 2501: an assembler-name for a local static variable named NAME. 2502: LABELNO is an integer which is different for each call. */ 2503: 2504: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2505: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2506: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2507: 2508: #define IDENT_ASM_OP ".ident" 2509: 2510: /* Output #ident as a .ident. */ 2511: 2512: #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2513: fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); 2514: 2515: /* Define the parentheses used to group arithmetic operations 2516: in assembler code. */ 2517: 2518: #define ASM_OPEN_PAREN "(" 2519: #define ASM_CLOSE_PAREN ")" 2520: 2521: /* Define results of standard character escape sequences. */ 2522: #define TARGET_BELL 007 2523: #define TARGET_BS 010 2524: #define TARGET_TAB 011 2525: #define TARGET_NEWLINE 012 2526: #define TARGET_VT 013 2527: #define TARGET_FF 014 2528: #define TARGET_CR 015 2529: 2530: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2531: ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') 2532: 2533: /* Print operand X (an rtx) in assembler syntax to file FILE. 2534: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2535: For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2536: 2537: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2538: 2539: /* Print a memory address as an operand to reference that memory location. */ 2540: 2541: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2542: { register rtx base, index = 0; \ 2543: int offset = 0; \ 2544: register rtx addr = ADDR; \ 2545: if (GET_CODE (addr) == REG) \ 2546: fputs (reg_names[REGNO (addr)], FILE); \ 2547: else if (GET_CODE (addr) == PLUS) \ 2548: { \ 2549: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2550: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2551: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2552: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2553: else \ 2554: base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2555: fputs (reg_names[REGNO (base)], FILE); \ 2556: if (index == 0) \ 2557: fprintf (FILE, "%+d", offset); \ 2558: else if (GET_CODE (index) == REG) \ 2559: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 1.1.1.4 ! root 2560: else if (GET_CODE (index) == SYMBOL_REF \ ! 2561: || GET_CODE (index) == CONST) \ 1.1 root 2562: fputc ('+', FILE), output_addr_const (FILE, index); \ 2563: else abort (); \ 2564: } \ 2565: else if (GET_CODE (addr) == MINUS \ 2566: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2567: { \ 2568: output_addr_const (FILE, XEXP (addr, 0)); \ 2569: fputs ("-(", FILE); \ 2570: output_addr_const (FILE, XEXP (addr, 1)); \ 2571: fputs ("-.)", FILE); \ 2572: } \ 2573: else if (GET_CODE (addr) == LO_SUM) \ 2574: { \ 2575: output_operand (XEXP (addr, 0), 0); \ 2576: fputs ("+%lo(", FILE); \ 2577: output_address (XEXP (addr, 1)); \ 2578: fputc (')', FILE); \ 2579: } \ 2580: else if (flag_pic && GET_CODE (addr) == CONST \ 2581: && GET_CODE (XEXP (addr, 0)) == MINUS \ 2582: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2583: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2584: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2585: { \ 2586: addr = XEXP (addr, 0); \ 2587: output_addr_const (FILE, XEXP (addr, 0)); \ 2588: /* Group the args of the second CONST in parenthesis. */ \ 2589: fputs ("-(", FILE); \ 2590: /* Skip past the second CONST--it does nothing for us. */\ 2591: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2592: /* Close the parenthesis. */ \ 2593: fputc (')', FILE); \ 2594: } \ 2595: else \ 2596: { \ 2597: output_addr_const (FILE, addr); \ 2598: } \ 2599: } 2600: 2601: /* Declare functions defined in sparc.c and used in templates. */ 2602: 2603: extern char *singlemove_string (); 2604: extern char *output_move_double (); 2605: extern char *output_move_quad (); 2606: extern char *output_fp_move_double (); 2607: extern char *output_fp_move_quad (); 2608: extern char *output_block_move (); 2609: extern char *output_scc_insn (); 2610: extern char *output_cbranch (); 1.1.1.3 root 2611: extern char *output_v9branch (); 1.1 root 2612: extern char *output_return (); 2613: 2614: /* Defined in flags.h, but insn-emit.c does not include flags.h. */ 2615: 2616: extern int flag_pic;
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