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1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC. 1.1.1.4 root 2: Copyright (C) 1987, 88, 89, 92, 94, 1995 Free Software Foundation, Inc. 1.1 root 3: Contributed by Michael Tiemann ([email protected]). 1.1.1.3 root 4: 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5: at Cygnus Support. 1.1 root 6: 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 root 21: the Free Software Foundation, 59 Temple Place - Suite 330, 22: Boston, MA 02111-1307, USA. */ 1.1 root 23: 24: /* Note that some other tm.h files include this one and then override 25: many of the definitions that relate to assembler syntax. */ 26: 1.1.1.3 root 27: /* Sparc64 support has been added by trying to allow for a day when one 28: compiler can handle both v8 and v9. There are a few cases where this 29: isn't doable, but keep them to a minimum! Two macros are used to help out: 30: TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness. 31: SPARCV9 is defined when compiling for sparc64 only. 32: In places where it is possible to choose between the two at runtime, use 33: TARGET_V9. In places where it is currently not possible to select 34: between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a 35: minimum. No attempt is made to support both v8 and v9 in the v9 compiler. 36: 37: If a combination v8/v9 compiler is too slow, it should always be possible 38: to #define TARGET_V9 as 0 (and potentially other v9-only options), and 39: #undef SPARCV9. */ 40: 41: /* What architecture we're compiling for. This must coincide with the 42: `arch_type' attribute in the .md file. The names were chosen to avoid 43: potential misunderstandings with the various 32 bit flavors (v7, v8, etc.): 44: if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that 45: could be misleading and ARCH_NOTV9 sounds klunky. */ 46: enum arch_type { ARCH_32BIT, ARCH_64BIT }; 47: extern enum arch_type sparc_arch_type; 48: 49: /* Names to predefine in the preprocessor for this target machine. */ 50: 51: /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses 52: the right varags.h file when bootstrapping. */ 53: 54: #ifdef SPARCV9 55: #define CPP_PREDEFINES \ 56: "-Dsparc -Dsun -Dunix -D__sparc_v9__ \ 57: -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" 58: #else 59: #define CPP_PREDEFINES \ 60: "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ 61: -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" 62: #endif 63: 1.1.1.4 root 64: #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" 1.1 root 65: 66: /* Provide required defaults for linker -e and -d switches. */ 67: 68: #define LINK_SPEC \ 1.1.1.4 root 69: "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ 70: %{assert*} %{shared:-assert pure-text}" 1.1 root 71: 72: /* Special flags to the Sun-4 assembler when using pipe for input. */ 73: 1.1.1.4 root 74: #define ASM_SPEC \ 75: " %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L}" 1.1 root 76: 77: /* Define macros to distinguish architectures. */ 1.1.1.3 root 78: 79: #ifdef SPARCV9 80: #define CPP_SPEC "\ 81: %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ 82: %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ 83: " 84: #else 85: #define CPP_SPEC "\ 86: %{msparclite:-D__sparclite__} \ 87: %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 88: %{mv8:-D__sparc_v8__} \ 89: %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 90: " 91: #endif 1.1 root 92: 93: /* Prevent error on `-sun4' and `-target sun4' options. */ 94: /* This used to translate -dalign to -malign, but that is no good 95: because it can't turn off the usual meaning of making debugging dumps. */ 96: 97: #define CC1_SPEC "%{sun4:} %{target:}" 98: 1.1.1.3 root 99: #ifdef SPARCV9 100: #define PTRDIFF_TYPE "long long int" 101: #define SIZE_TYPE "long long unsigned int" 102: #else 1.1 root 103: #define PTRDIFF_TYPE "int" 104: /* In 2.4 it should work to delete this. 105: #define SIZE_TYPE "int" */ 1.1.1.3 root 106: #endif 107: 108: /* ??? This should be 32 bits for v9 but what can we do? */ 1.1 root 109: #define WCHAR_TYPE "short unsigned int" 110: #define WCHAR_TYPE_SIZE 16 1.1.1.3 root 111: #define MAX_WCHAR_TYPE_SIZE 16 1.1 root 112: 1.1.1.3 root 113: /* Show we can debug even without a frame pointer. */ 114: #define CAN_DEBUG_WITHOUT_FP 1.1 root 115: 116: /* To make profiling work with -f{pic,PIC}, we need to emit the profiling 117: code into the rtl. Also, if we are profiling, we cannot eliminate 118: the frame pointer (because the return address will get smashed). */ 119: 1.1.1.3 root 120: void sparc_override_options (); 121: 1.1 root 122: #define OVERRIDE_OPTIONS \ 1.1.1.3 root 123: do { \ 124: if (profile_flag || profile_block_flag) \ 125: { \ 126: if (flag_pic) \ 127: { \ 128: char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \ 129: warning ("%s and profiling conflict: disabling %s", \ 130: pic_string, pic_string); \ 131: flag_pic = 0; \ 132: } \ 133: flag_omit_frame_pointer = 0; \ 134: } \ 1.1.1.4 root 135: SUBTARGET_OVERRIDE_OPTIONS; \ 1.1.1.3 root 136: sparc_override_options (); \ 137: } while (0) 1.1.1.2 root 138: 1.1.1.4 root 139: /* This is meant to be redefined in the host dependent files. */ 1.1.1.2 root 140: #define SUBTARGET_OVERRIDE_OPTIONS 1.1 root 141: 142: /* These compiler options take an argument. We ignore -target for now. */ 143: 144: #define WORD_SWITCH_TAKES_ARG(STR) \ 145: (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ 146: || !strcmp (STR, "target") || !strcmp (STR, "assert")) 147: 148: /* Print subsidiary information on the compiler version in use. */ 149: 150: #define TARGET_VERSION fprintf (stderr, " (sparc)"); 151: 152: /* Generate DBX debugging information. */ 153: 154: #define DBX_DEBUGGING_INFO 1.1.1.3 root 155: 1.1 root 156: /* Run-time compilation parameters selecting different hardware subsets. */ 157: 158: extern int target_flags; 159: 160: /* Nonzero if we should generate code to use the fpu. */ 1.1.1.3 root 161: #define MASK_FPU 1 162: #define TARGET_FPU (target_flags & MASK_FPU) 1.1 root 163: 164: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we 165: use fast return insns, but lose some generality. */ 1.1.1.3 root 166: #define MASK_EPILOGUE 2 167: #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) 1.1 root 168: 169: /* Nonzero if we should assume that double pointers might be unaligned. 170: This can happen when linking gcc compiled code with other compilers, 171: because the ABI only guarantees 4 byte alignment. */ 1.1.1.3 root 172: #define MASK_UNALIGNED_DOUBLES 4 173: #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) 174: 175: /* ??? Bits 0x18 are currently unused. */ 176: 177: /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */ 178: #define MASK_SUPERSPARC 0x20 179: #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC) 1.1 root 180: 181: /* Nonzero means that we should generate code for a v8 sparc. */ 1.1.1.3 root 182: #define MASK_V8 0x40 183: #define TARGET_V8 (target_flags & MASK_V8) 1.1 root 184: 1.1.1.2 root 185: /* Nonzero means that we should generate code for a sparclite. 186: This enables the sparclite specific instructions, but does not affect 187: whether FPU instructions are emitted. */ 1.1.1.3 root 188: #define MASK_SPARCLITE 0x80 189: #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) 1.1 root 190: 191: /* Nonzero means that we should generate code using a flat register window 192: model, i.e. no save/restore instructions are generated, in the most 193: efficient manner. This code is not compatible with normal sparc code. */ 194: /* This is not a user selectable option yet, because it requires changes 195: that are not yet switchable via command line arguments. */ 1.1.1.3 root 196: /* ??? This flag is deprecated and may disappear at some point. */ 197: #define MASK_FRW 0x100 198: #define TARGET_FRW (target_flags & MASK_FRW) 1.1 root 199: 200: /* Nonzero means that we should generate code using a flat register window 201: model, i.e. no save/restore instructions are generated, but which is 202: compatible with normal sparc code. This is the same as above, except 1.1.1.3 root 203: that the frame pointer is %i7 instead of %fp. */ 204: /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will 205: go away, but until that time only use this one when necessary. 206: -mflat sets both. */ 207: #define MASK_FLAT 0x200 208: #define TARGET_FLAT (target_flags & MASK_FLAT) 209: 210: /* Nonzero means use the registers that the Sparc ABI reserves for 211: application software. This is the default for v8, but not v9. */ 212: #define MASK_APP_REGS 0x400 213: #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) 214: 215: /* Option to select how quad word floating point is implemented. 216: When TARGET_HARD_QUAD is true, we use the hardware quad instructions. 217: Otherwise, we use the SPARC ABI quad library functions. */ 218: #define MASK_HARD_QUAD 0x800 219: #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) 220: 221: /* Nonzero if we're compiling for 64 bit sparc. */ 222: #define MASK_V9 0x1000 223: #define TARGET_V9 (target_flags & MASK_V9) 224: 225: /* Nonzero if ints are 64 bits. 226: This automatically implies longs are 64 bits too. 227: This option is for v9 only. */ 228: #define MASK_INT64 0x2000 229: #define TARGET_INT64 (target_flags & MASK_INT64) 230: 231: /* Nonzero if longs are 64 bits. 232: This option is for v9 only. */ 233: #define MASK_LONG64 0x4000 234: #define TARGET_LONG64 (target_flags & MASK_LONG64) 235: 236: /* Nonzero if pointers are 64 bits. 237: This is not a user selectable option, though it may be one day - 238: so it is used to determine pointer size instead of an architecture flag. */ 239: #define MASK_PTR64 0x8000 240: #define TARGET_PTR64 (target_flags & MASK_PTR64) 241: 242: /* Nonzero if we are generating code to be tested in a 32 bit environment. 243: Hence, we assume the upper 32 bits of symbolic addresses are zero, and 244: avoid generating %uhi and %ulo terms. 245: Pointers are still 64 bits though! This option is for v9 only. */ 246: /* ??? This option is deprecated. Try to use -mmedlow. */ 247: #define MASK_ENV32 0x10000 248: #define TARGET_ENV32 (target_flags & MASK_ENV32) 249: 250: /* Memory models. 251: Two memory models are supported: 252: TARGET_MEDLOW: 32 bit address space, top 32 bits = 0 253: (pointers still 64 bits) 254: TARGET_MEDANY: 32 bit address space, data segment loaded anywhere 255: (use %g4 as offset). 256: TARGET_FULLANY: not supported yet. 257: These options are for v9 only. All mask values are nonzero so the v8 258: compiler can assume this stuff won't interfere. */ 259: #define MASK_MEDLOW 0x20000 260: #define MASK_MEDANY 0x40000 261: #define MASK_FULLANY 0x60000 262: #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) 263: #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) 264: #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) 265: #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) 266: 267: /* ??? There are hardcoded references to this reg in the .md file. */ 268: #define MEDANY_BASE_REG "%g4" 269: 270: /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by 271: adding 2047 to %sp. This option is for v9 only and is the default. */ 272: #define MASK_STACK_BIAS 0x80000 273: #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) 1.1 root 274: 275: /* Macro to define tables used to set the flags. 276: This is a list in braces of pairs in braces, 277: each pair being { "NAME", VALUE } 278: where VALUE is the bits to set or minus the bits to clear. 279: An empty string NAME is used to identify the default VALUE. */ 280: 1.1.1.2 root 281: /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 1.1.1.3 root 282: The Fujitsu MB86934 is the recent sparclite chip, with an fpu. 1.1.1.2 root 283: We use -mf930 and -mf934 options to choose which. 284: ??? These should perhaps be -mcpu= options. */ 285: 1.1 root 286: #define TARGET_SWITCHES \ 1.1.1.3 root 287: { {"fpu", MASK_FPU}, \ 288: {"no-fpu", -MASK_FPU}, \ 289: {"hard-float", MASK_FPU}, \ 290: {"soft-float", -MASK_FPU}, \ 291: {"epilogue", MASK_EPILOGUE}, \ 292: {"no-epilogue", -MASK_EPILOGUE}, \ 293: {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ 294: {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ 295: {"supersparc", MASK_SUPERSPARC+MASK_V8}, \ 296: {"cypress", -MASK_SUPERSPARC-MASK_V8}, \ 297: {"v8", MASK_V8}, \ 298: {"no-v8", -MASK_V8}, \ 299: {"sparclite", MASK_SPARCLITE}, \ 300: {"no-sparclite", -MASK_SPARCLITE}, \ 301: {"f930", MASK_SPARCLITE}, \ 302: {"f930", -MASK_FPU}, \ 303: {"f934", MASK_SPARCLITE}, \ 304: {"flat", MASK_FRW+MASK_FLAT}, \ 305: {"no-flat", -(MASK_FRW+MASK_FLAT)}, \ 306: {"app-regs", MASK_APP_REGS}, \ 307: {"no-app-regs", -MASK_APP_REGS}, \ 308: {"hard-quad-float", MASK_HARD_QUAD}, \ 309: {"soft-quad-float", -MASK_HARD_QUAD}, \ 310: SUBTARGET_SWITCHES \ 311: V9_SWITCHES \ 1.1 root 312: { "", TARGET_DEFAULT}} 313: 1.1.1.3 root 314: #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) 1.1.1.2 root 315: 316: /* This is meant to be redefined in the host dependent files */ 317: #define SUBTARGET_SWITCHES 1.1 root 318: 1.1.1.3 root 319: /* ??? Until we support a combination v8/v9 compiler, the v9 specific options 320: are only defined for the v9 compiler. */ 321: #ifdef SPARCV9 322: #define V9_SWITCHES \ 323: /* {"v9", MASK_V9}, */ \ 324: {"int64", MASK_INT64+MASK_LONG64}, \ 325: {"int32", -MASK_INT64}, \ 326: {"int32", MASK_LONG64}, \ 327: {"long64", -MASK_INT64}, \ 328: {"long64", MASK_LONG64}, \ 329: {"long32", -(MASK_INT64+MASK_LONG64)}, \ 330: /* {"ptr64", MASK_PTR64}, */ \ 331: /* {"ptr32", -MASK_PTR64}, */ \ 332: {"stack-bias", MASK_STACK_BIAS}, \ 333: {"no-stack-bias", -MASK_STACK_BIAS}, \ 334: {"medlow", -MASK_CODE_MODEL}, \ 335: {"medlow", MASK_MEDLOW}, \ 336: {"medany", -MASK_CODE_MODEL}, \ 337: {"medany", MASK_MEDANY}, 338: #else 339: #define V9_SWITCHES 1.1.1.2 root 340: #endif 1.1.1.3 root 341: 342: /* target machine storage layout */ 1.1.1.2 root 343: 344: /* Define for cross-compilation to a sparc target with no TFmode from a host 345: with a different float format (e.g. VAX). */ 346: #define REAL_ARITHMETIC 347: 1.1 root 348: /* Define this if most significant bit is lowest numbered 349: in instructions that operate on numbered bit-fields. */ 350: #define BITS_BIG_ENDIAN 1 351: 352: /* Define this if most significant byte of a word is the lowest numbered. */ 353: /* This is true on the SPARC. */ 354: #define BYTES_BIG_ENDIAN 1 355: 356: /* Define this if most significant word of a multiword number is the lowest 357: numbered. */ 358: /* Doubles are stored in memory with the high order word first. This 359: matters when cross-compiling. */ 360: #define WORDS_BIG_ENDIAN 1 361: 362: /* number of bits in an addressable storage unit */ 363: #define BITS_PER_UNIT 8 364: 365: /* Width in bits of a "word", which is the contents of a machine register. 366: Note that this is not necessarily the width of data type `int'; 367: if using 16-bit ints on a 68000, this would still be 32. 368: But on a machine with 16-bit registers, this would be 16. */ 1.1.1.3 root 369: #define BITS_PER_WORD (TARGET_V9 ? 64 : 32) 370: #define MAX_BITS_PER_WORD 64 1.1 root 371: 372: /* Width of a word, in units (bytes). */ 1.1.1.3 root 373: #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4) 1.1.1.4 root 374: #define MIN_UNITS_PER_WORD 4 1.1.1.3 root 375: 376: /* Now define the sizes of the C data types. */ 377: 378: #define SHORT_TYPE_SIZE 16 379: #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) 380: #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 381: #define LONG_LONG_TYPE_SIZE 64 382: #define FLOAT_TYPE_SIZE 32 383: #define DOUBLE_TYPE_SIZE 64 384: 385: #define MAX_INT_TYPE_SIZE 64 386: #define MAX_LONG_TYPE_SIZE 64 387: 388: #ifdef SPARCV9 389: /* ??? This does not work in SunOS 4.x, so it is not enabled here. 390: Instead, it is enabled in sol2.h, because it does work under Solaris. */ 391: /* Define for support of TFmode long double and REAL_ARITHMETIC. 392: Sparc ABI says that long double is 4 words. */ 393: #define LONG_DOUBLE_TYPE_SIZE 128 394: #endif 1.1 root 395: 396: /* Width in bits of a pointer. 397: See also the macro `Pmode' defined below. */ 1.1.1.3 root 398: #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 1.1 root 399: 400: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1.1.1.3 root 401: #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 402: 403: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 1.1.1.3 root 404: #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64) 1.1 root 405: 406: /* ALIGN FRAMES on double word boundaries */ 407: 1.1.1.3 root 408: #define SPARC_STACK_ALIGN(LOC) \ 409: (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 1.1 root 410: 411: /* Allocation boundary (in *bits*) for the code of a function. */ 412: #define FUNCTION_BOUNDARY 32 413: 414: /* Alignment of field after `int : 0' in a structure. */ 1.1.1.3 root 415: /* ??? Should this be based on TARGET_INT64? */ 416: #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32) 1.1 root 417: 418: /* Every structure's size must be a multiple of this. */ 419: #define STRUCTURE_SIZE_BOUNDARY 8 420: 421: /* A bitfield declared as `int' forces `int' alignment for the struct. */ 422: #define PCC_BITFIELD_TYPE_MATTERS 1 423: 424: /* No data type wants to be aligned rounder than this. */ 1.1.1.3 root 425: #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64) 1.1 root 426: 427: /* The best alignment to use in cases where we have a choice. */ 428: #define FASTEST_ALIGNMENT 64 429: 430: /* Make strings word-aligned so strcpy from constants will be faster. */ 431: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 432: ((TREE_CODE (EXP) == STRING_CST \ 433: && (ALIGN) < FASTEST_ALIGNMENT) \ 434: ? FASTEST_ALIGNMENT : (ALIGN)) 435: 436: /* Make arrays of chars word-aligned for the same reasons. */ 437: #define DATA_ALIGNMENT(TYPE, ALIGN) \ 438: (TREE_CODE (TYPE) == ARRAY_TYPE \ 439: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 440: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 441: 442: /* Set this nonzero if move instructions will actually fail to work 443: when given unaligned data. */ 444: #define STRICT_ALIGNMENT 1 445: 446: /* Things that must be doubleword aligned cannot go in the text section, 447: because the linker fails to align the text section enough! 1.1.1.3 root 448: Put them in the data section. This macro is only used in this file. */ 1.1 root 449: #define MAX_TEXT_ALIGN 32 450: 1.1.1.4 root 451: /* This forces all variables and constants to the data section when PIC. 452: This is because the SunOS 4 shared library scheme thinks everything in 453: text is a function, and patches the address to point to a loader stub. */ 454: /* This is defined to zero for every system which doesn't use the a.out object 455: file format. */ 456: #ifndef SUNOS4_SHARED_LIBRARIES 457: #define SUNOS4_SHARED_LIBRARIES 0 458: #endif 459: 1.1.1.3 root 460: /* This is defined differently for v9 in a cover file. */ 1.1 root 461: #define SELECT_SECTION(T,RELOC) \ 462: { \ 463: if (TREE_CODE (T) == VAR_DECL) \ 464: { \ 465: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ 1.1.1.3 root 466: && DECL_INITIAL (T) \ 467: && (DECL_INITIAL (T) == error_mark_node \ 468: || TREE_CONSTANT (DECL_INITIAL (T))) \ 1.1 root 469: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ 1.1.1.4 root 470: && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 471: text_section (); \ 472: else \ 473: data_section (); \ 474: } \ 475: else if (TREE_CODE (T) == CONSTRUCTOR) \ 476: { \ 1.1.1.4 root 477: if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ 1.1 root 478: data_section (); \ 479: } \ 1.1.1.4 root 480: else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ 1.1 root 481: { \ 482: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ 1.1.1.4 root 483: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ 484: || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 485: data_section (); \ 486: else \ 487: text_section (); \ 488: } \ 489: } 490: 491: /* Use text section for a constant 492: unless we need more alignment than that offers. */ 1.1.1.3 root 493: /* This is defined differently for v9 in a cover file. */ 1.1 root 494: #define SELECT_RTX_SECTION(MODE, X) \ 495: { \ 496: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ 1.1.1.4 root 497: && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ 1.1 root 498: text_section (); \ 499: else \ 500: data_section (); \ 501: } 502: 503: /* Standard register usage. */ 504: 505: /* Number of actual hardware registers. 506: The hardware registers are assigned numbers for the compiler 507: from 0 to just below FIRST_PSEUDO_REGISTER. 508: All registers that the compiler knows about must be given numbers, 509: even those that are not normally considered general registers. 510: 1.1.1.3 root 511: SPARC has 32 integer registers and 32 floating point registers. 512: 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 513: accessible. We still account for them to simplify register computations 514: (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 515: 32+32+32+4 == 100. 516: Register 0 is used as the integer condition code register. */ 1.1 root 517: 1.1.1.3 root 518: #ifdef SPARCV9 519: #define FIRST_PSEUDO_REGISTER 100 520: #else 1.1 root 521: #define FIRST_PSEUDO_REGISTER 64 1.1.1.3 root 522: #endif 1.1 root 523: 524: /* 1 for registers that have pervasive standard uses 525: and are not available for the register allocator. 526: g0 is used for the condition code and not to represent %g0, which is 527: hardwired to 0, so reg 0 is *not* fixed. 1.1.1.3 root 528: On non-v9 systems: 529: g1 is free to use as temporary. 530: g2-g4 are reserved for applications. Gcc normally uses them as 531: temporaries, but this can be disabled via the -mno-app-regs option. 532: g5 through g7 are reserved for the operating system. 533: On v9 systems: 534: g1 and g5 are free to use as temporaries. 535: g2-g4 are reserved for applications (the compiler will not normally use 536: them, but they can be used as temporaries with -mapp-regs). 537: g6-g7 are reserved for the operating system. 538: ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 539: currently be a fixed register until this pattern is rewritten. 540: Register 1 is also used when restoring call-preserved registers in large 541: stack frames. */ 542: 543: #ifdef SPARCV9 544: #define FIXED_REGISTERS \ 545: {0, 1, 1, 1, 1, 0, 1, 1, \ 546: 0, 0, 0, 0, 0, 0, 1, 0, \ 547: 0, 0, 0, 0, 0, 0, 0, 0, \ 548: 0, 0, 0, 0, 0, 0, 1, 1, \ 549: \ 550: 0, 0, 0, 0, 0, 0, 0, 0, \ 551: 0, 0, 0, 0, 0, 0, 0, 0, \ 552: 0, 0, 0, 0, 0, 0, 0, 0, \ 553: 0, 0, 0, 0, 0, 0, 0, 0, \ 554: \ 555: 0, 0, 0, 0, 0, 0, 0, 0, \ 556: 0, 0, 0, 0, 0, 0, 0, 0, \ 557: 0, 0, 0, 0, 0, 0, 0, 0, \ 558: 0, 0, 0, 0, 0, 0, 0, 0, \ 559: \ 560: 0, 0, 0, 0} 561: #else 1.1 root 562: #define FIXED_REGISTERS \ 563: {0, 0, 0, 0, 0, 1, 1, 1, \ 564: 0, 0, 0, 0, 0, 0, 1, 0, \ 565: 0, 0, 0, 0, 0, 0, 0, 0, \ 566: 0, 0, 0, 0, 0, 0, 1, 1, \ 567: \ 568: 0, 0, 0, 0, 0, 0, 0, 0, \ 569: 0, 0, 0, 0, 0, 0, 0, 0, \ 570: 0, 0, 0, 0, 0, 0, 0, 0, \ 571: 0, 0, 0, 0, 0, 0, 0, 0} 1.1.1.3 root 572: #endif 1.1 root 573: 574: /* 1 for registers not available across function calls. 575: These must include the FIXED_REGISTERS and also any 576: registers that can be used without being saved. 577: The latter must include the registers where values are returned 578: and the register where structure-value addresses are passed. 579: Aside from that, you can include as many other registers as you like. */ 1.1.1.3 root 580: 581: #ifdef SPARCV9 582: #define CALL_USED_REGISTERS \ 583: {1, 1, 1, 1, 1, 1, 1, 1, \ 584: 1, 1, 1, 1, 1, 1, 1, 1, \ 585: 0, 0, 0, 0, 0, 0, 0, 0, \ 586: 0, 0, 0, 0, 0, 0, 1, 1, \ 587: \ 588: 1, 1, 1, 1, 1, 1, 1, 1, \ 589: 1, 1, 1, 1, 1, 1, 1, 1, \ 590: 0, 0, 0, 0, 0, 0, 0, 0, \ 591: 0, 0, 0, 0, 0, 0, 0, 0, \ 592: \ 593: 0, 0, 0, 0, 0, 0, 0, 0, \ 594: 0, 0, 0, 0, 0, 0, 0, 0, \ 595: 1, 1, 1, 1, 1, 1, 1, 1, \ 596: 1, 1, 1, 1, 1, 1, 1, 1, \ 597: \ 598: 1, 1, 1, 1} 599: #else 1.1 root 600: #define CALL_USED_REGISTERS \ 601: {1, 1, 1, 1, 1, 1, 1, 1, \ 602: 1, 1, 1, 1, 1, 1, 1, 1, \ 603: 0, 0, 0, 0, 0, 0, 0, 0, \ 604: 0, 0, 0, 0, 0, 0, 1, 1, \ 605: \ 606: 1, 1, 1, 1, 1, 1, 1, 1, \ 607: 1, 1, 1, 1, 1, 1, 1, 1, \ 608: 1, 1, 1, 1, 1, 1, 1, 1, \ 609: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 root 610: #endif 1.1 root 611: 612: /* If !TARGET_FPU, then make the fp registers fixed so that they won't 1.1.1.3 root 613: be allocated. On v9, also make the fp cc regs fixed. */ 1.1 root 614: 615: #define CONDITIONAL_REGISTER_USAGE \ 616: do \ 617: { \ 618: if (! TARGET_FPU) \ 619: { \ 620: int regno; \ 1.1.1.3 root 621: for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1.1 root 622: fixed_regs[regno] = 1; \ 623: } \ 1.1.1.5 ! root 624: /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \ ! 625: fixed_regs[2] |= ! TARGET_APP_REGS; \ ! 626: fixed_regs[3] |= ! TARGET_APP_REGS; \ ! 627: fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \ 1.1.1.3 root 628: if (TARGET_FLAT) \ 629: { \ 630: /* Let the compiler believe the frame pointer is still \ 631: %fp, but output it as %i7. */ \ 632: fixed_regs[31] = 1; \ 633: reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ 634: /* ??? This is a hack to disable leaf functions. */ \ 635: global_regs[7] = 1; \ 636: } \ 637: if (profile_block_flag) \ 638: { \ 639: /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ 640: uses them. */ \ 641: fixed_regs[1] = 1; \ 642: fixed_regs[2] = 1; \ 643: } \ 1.1 root 644: } \ 645: while (0) 646: 647: /* Return number of consecutive hard regs needed starting at reg REGNO 648: to hold something of mode MODE. 649: This is ordinarily the length in words of a value of mode MODE 650: but can be less for certain modes in special long registers. 651: 652: On SPARC, ordinary registers hold 32 bits worth; 653: this means both integer and floating point registers. 1.1.1.3 root 654: On v9, integer regs hold 64 bits worth; floating point regs hold 655: 32 bits worth (this includes the new fp regs as even the odd ones are 656: included in the hard register count). */ 657: 658: #define HARD_REGNO_NREGS(REGNO, MODE) \ 659: (TARGET_V9 \ 660: ? ((REGNO) < 32 \ 661: ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 662: : (GET_MODE_SIZE (MODE) + 3) / 4) \ 663: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1.1 root 664: 665: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1.1.1.3 root 666: See sparc.c for how we initialize this. */ 667: extern int *hard_regno_mode_classes; 668: extern int sparc_mode_class[]; 1.1 root 669: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1.1.1.3 root 670: ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 1.1 root 671: 672: /* Value is 1 if it is a good idea to tie two pseudo registers 673: when one has mode MODE1 and one has mode MODE2. 674: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1.1.1.3 root 675: for any hard reg, then this must be 0 for correct output. 676: 677: For V9: SFmode can't be combined with other float modes, because they can't 678: be allocated to the %d registers. Also, DFmode won't fit in odd %f 679: registers, but SFmode will. */ 1.1 root 680: #define MODES_TIEABLE_P(MODE1, MODE2) \ 1.1.1.3 root 681: ((MODE1) == (MODE2) \ 682: || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 683: && (! TARGET_V9 \ 684: || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 685: || (MODE1 != SFmode && MODE2 != SFmode))))) 1.1 root 686: 687: /* Specify the registers used for certain standard purposes. 688: The values of these macros are register numbers. */ 689: 690: /* SPARC pc isn't overloaded on a register that the compiler knows about. */ 691: /* #define PC_REGNUM */ 692: 693: /* Register to use for pushing function arguments. */ 694: #define STACK_POINTER_REGNUM 14 695: 1.1.1.3 root 696: /* Actual top-of-stack address is 92/136 greater than the contents of the 697: stack pointer register for !v9/v9. That is: 698: - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 699: address, and 24 bytes for the 6 register parameters. 700: - v9: 128 bytes for the in and local registers + 8 bytes reserved. */ 1.1 root 701: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) 702: 1.1.1.3 root 703: /* The stack bias (amount by which the hardware register is offset by). */ 704: #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) 705: 1.1 root 706: /* Base register for access to local variables of the function. */ 707: #define FRAME_POINTER_REGNUM 30 708: 709: #if 0 710: /* Register that is used for the return address. */ 711: #define RETURN_ADDR_REGNUM 15 712: #endif 713: 714: /* Value should be nonzero if functions must have frame pointers. 715: Zero means the frame pointer need not be set up (and parms 716: may be accessed via the stack pointer) in functions that seem suitable. 717: This is computed in `reload', in reload1.c. 1.1.1.3 root 718: Used in flow.c, global.c, and reload1.c. 1.1 root 719: 1.1.1.3 root 720: Being a non-leaf function does not mean a frame pointer is needed in the 721: flat window model. However, the debugger won't be able to backtrace through 722: us with out it. */ 1.1 root 723: #define FRAME_POINTER_REQUIRED \ 1.1.1.3 root 724: (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs \ 725: || !leaf_function_p ()) \ 726: : ! (leaf_function_p () && only_leaf_regs_used ())) 1.1 root 727: 728: /* C statement to store the difference between the frame pointer 729: and the stack pointer values immediately after the function prologue. 730: 731: Note, we always pretend that this is a leaf function because if 732: it's not, there's no point in trying to eliminate the 733: frame pointer. If it is a leaf function, we guessed right! */ 734: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 1.1.1.3 root 735: ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \ 1.1 root 736: : compute_frame_size (get_frame_size (), 1))) 737: 738: /* Base register for access to arguments of the function. */ 1.1.1.3 root 739: #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 1.1 root 740: 1.1.1.2 root 741: /* Register in which static-chain is passed to a function. This must 1.1.1.4 root 742: not be a register used by the prologue. */ 743: #define STATIC_CHAIN_REGNUM (TARGET_V9 ? 5 : 2) 1.1 root 744: 745: /* Register which holds offset table for position-independent 746: data references. */ 747: 748: #define PIC_OFFSET_TABLE_REGNUM 23 749: 750: #define INITIALIZE_PIC initialize_pic () 751: #define FINALIZE_PIC finalize_pic () 752: 753: /* Sparc ABI says that quad-precision floats and all structures are returned 1.1.1.3 root 754: in memory. 755: For v9, all aggregates are returned in memory. */ 756: #define RETURN_IN_MEMORY(TYPE) \ 757: (TYPE_MODE (TYPE) == BLKmode \ 758: || (! TARGET_V9 && (TYPE_MODE (TYPE) == TFmode \ 759: || TYPE_MODE (TYPE) == TCmode))) 1.1 root 760: 761: /* Functions which return large structures get the address 762: to place the wanted value at offset 64 from the frame. 1.1.1.3 root 763: Must reserve 64 bytes for the in and local registers. 764: v9: Functions which return large structures get the address to place the 765: wanted value from an invisible first argument. */ 1.1 root 766: /* Used only in other #defines in this file. */ 767: #define STRUCT_VALUE_OFFSET 64 768: 769: #define STRUCT_VALUE \ 1.1.1.3 root 770: (TARGET_V9 \ 771: ? 0 \ 772: : gen_rtx (MEM, Pmode, \ 773: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ 774: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 775: #define STRUCT_VALUE_INCOMING \ 1.1.1.3 root 776: (TARGET_V9 \ 777: ? 0 \ 778: : gen_rtx (MEM, Pmode, \ 779: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ 780: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) 1.1 root 781: 782: /* Define the classes of registers for register constraints in the 783: machine description. Also define ranges of constants. 784: 785: One of the classes must always be named ALL_REGS and include all hard regs. 786: If there is more than one class, another class must be named NO_REGS 787: and contain no registers. 788: 789: The name GENERAL_REGS must be the name of a class (or an alias for 790: another name such as ALL_REGS). This is the class of registers 791: that is allowed by "g" or "r" in a register constraint. 792: Also, registers outside this class are allocated only when 793: instructions express preferences for them. 794: 795: The classes must be numbered in nondecreasing order; that is, 796: a larger-numbered class must never be contained completely 797: in a smaller-numbered class. 798: 799: For any two classes, it is very desirable that there be another 800: class that represents their union. */ 801: 1.1.1.3 root 802: /* The SPARC has two kinds of registers, general and floating point. 1.1 root 803: 1.1.1.3 root 804: For v9 we must distinguish between the upper and lower floating point 805: registers because the upper ones can't hold SFmode values. 806: HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 807: satisfying a group need for a class will also satisfy a single need for 808: that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 809: regs. 810: 811: It is important that one class contains all the general and all the standard 812: fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 813: because reg_class_record() will bias the selection in favor of fp regs, 814: because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 815: because FP_REGS > GENERAL_REGS. 816: 817: It is also important that one class contain all the general and all the 818: fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS 819: but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause 820: allocate_reload_reg() to bypass it causing an abort because the compiler 821: thinks it doesn't have a spill reg when in fact it does. 822: 823: v9 also has 4 floating point condition code registers. Since we don't 824: have a class that is the union of FPCC_REGS with either of the others, 825: it is important that it appear first. Otherwise the compiler will die 826: trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 827: constraints. */ 828: 829: #ifdef SPARCV9 830: enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, 831: GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 832: ALL_REGS, LIM_REG_CLASSES }; 833: #else 1.1 root 834: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; 1.1.1.3 root 835: #endif 1.1 root 836: 837: #define N_REG_CLASSES (int) LIM_REG_CLASSES 838: 839: /* Give names of register classes as strings for dump file. */ 840: 1.1.1.3 root 841: #ifdef SPARCV9 842: #define REG_CLASS_NAMES \ 843: { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \ 844: "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" } 845: #else 1.1 root 846: #define REG_CLASS_NAMES \ 1.1.1.3 root 847: { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } 848: #endif 1.1 root 849: 850: /* Define which registers fit in which classes. 851: This is an initializer for a vector of HARD_REG_SET 852: of length N_REG_CLASSES. */ 853: 1.1.1.3 root 854: #ifdef SPARCV9 855: #define REG_CLASS_CONTENTS \ 856: {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \ 857: {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \ 858: {-2, -1, -1, 0xf}} 859: #else 1.1 root 860: #if 0 && defined (__GNUC__) 861: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} 862: #else 863: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} 864: #endif 1.1.1.3 root 865: #endif 1.1 root 866: 867: /* The same information, inverted: 868: Return the class number of the smallest class containing 869: reg number REGNO. This could be a conditional expression 870: or could index an array. */ 871: 1.1.1.3 root 872: #ifdef SPARCV9 873: #define REGNO_REG_CLASS(REGNO) \ 874: ((REGNO) == 0 ? NO_REGS \ 875: : (REGNO) < 32 ? GENERAL_REGS \ 876: : (REGNO) < 64 ? FP_REGS \ 877: : (REGNO) < 96 ? EXTRA_FP_REGS \ 878: : FPCC_REGS) 879: #else 1.1 root 880: #define REGNO_REG_CLASS(REGNO) \ 881: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) 1.1.1.3 root 882: #endif 1.1 root 883: 1.1.1.3 root 884: /* This is the order in which to allocate registers normally. 1.1 root 885: 886: We put %f0/%f1 last among the float registers, so as to make it more 1.1.1.2 root 887: likely that a pseudo-register which dies in the float return register 1.1 root 888: will get allocated to the float return register, thus saving a move 1.1.1.3 root 889: instruction at the end of the function. 890: 891: On v9, the float registers are ordered a little "funny" because some 892: of them (%f16-%f47) are call-preserved. */ 893: #ifdef SPARCV9 894: #define REG_ALLOC_ORDER \ 895: { 8, 9, 10, 11, 12, 13, \ 896: 15, 16, 17, 18, 19, 20, 21, 22, \ 897: 23, 24, 25, 26, 27, 28, 29, 31, \ 898: 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ 899: 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 900: 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 901: 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 902: 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 903: 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 904: 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 905: 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 906: 32, 33, /* %f0,%f1 */ \ 907: 96, 97, 98, 99, /* %fcc0-3 */ \ 908: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30} 909: #else 1.1 root 910: #define REG_ALLOC_ORDER \ 911: { 8, 9, 10, 11, 12, 13, 2, 3, \ 912: 15, 16, 17, 18, 19, 20, 21, 22, \ 913: 23, 24, 25, 26, 27, 28, 29, 31, \ 914: 34, 35, 36, 37, 38, 39, \ 915: 40, 41, 42, 43, 44, 45, 46, 47, \ 916: 48, 49, 50, 51, 52, 53, 54, 55, \ 917: 56, 57, 58, 59, 60, 61, 62, 63, \ 918: 32, 33, \ 919: 1, 4, 5, 6, 7, 0, 14, 30} 1.1.1.3 root 920: #endif 1.1 root 921: 922: /* This is the order in which to allocate registers for 923: leaf functions. If all registers can fit in the "i" registers, 1.1.1.3 root 924: then we have the possibility of having a leaf function. 925: v9: The floating point registers are ordered a little "funny" because some 926: of them (%f16-%f47) are call-preserved. */ 927: #ifdef SPARCV9 928: #define REG_LEAF_ALLOC_ORDER \ 929: { 24, 25, 26, 27, 28, 29, \ 930: 15, 8, 9, 10, 11, 12, 13, \ 931: 16, 17, 18, 19, 20, 21, 22, 23, \ 932: 34, 35, 36, 37, 38, 39, \ 933: 40, 41, 42, 43, 44, 45, 46, 47, \ 934: 80, 81, 82, 83, 84, 85, 86, 87, \ 935: 88, 89, 90, 91, 92, 93, 94, 95, \ 936: 48, 49, 50, 51, 52, 53, 54, 55, \ 937: 56, 57, 58, 59, 60, 61, 62, 63, \ 938: 64, 65, 66, 67, 68, 69, 70, 71, \ 939: 72, 73, 74, 75, 76, 77, 78, 79, \ 940: 32, 33, \ 941: 96, 97, 98, 99, \ 942: 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31} 943: #else 1.1 root 944: #define REG_LEAF_ALLOC_ORDER \ 945: { 2, 3, 24, 25, 26, 27, 28, 29, \ 946: 15, 8, 9, 10, 11, 12, 13, \ 947: 16, 17, 18, 19, 20, 21, 22, 23, \ 948: 34, 35, 36, 37, 38, 39, \ 949: 40, 41, 42, 43, 44, 45, 46, 47, \ 950: 48, 49, 50, 51, 52, 53, 54, 55, \ 951: 56, 57, 58, 59, 60, 61, 62, 63, \ 952: 32, 33, \ 953: 1, 4, 5, 6, 7, 0, 14, 30, 31} 1.1.1.3 root 954: #endif 1.1 root 955: 956: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 957: 1.1.1.3 root 958: /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when 959: -mflat is used. Function only_leaf_regs_used will return 0 if a global 960: register is used and is not permitted in a leaf function. We make %g7 961: a global reg if -mflat and voila. Since %g7 is a system register and is 962: fixed it won't be used by gcc anyway. */ 963: #ifdef SPARCV9 1.1 root 964: #define LEAF_REGISTERS \ 1.1.1.3 root 965: { 1, 1, 1, 1, 1, 1, 1, 0, \ 966: 0, 0, 0, 0, 0, 0, 1, 0, \ 967: 0, 0, 0, 0, 0, 0, 0, 0, \ 968: 1, 1, 1, 1, 1, 1, 0, 1, \ 969: 1, 1, 1, 1, 1, 1, 1, 1, \ 970: 1, 1, 1, 1, 1, 1, 1, 1, \ 971: 1, 1, 1, 1, 1, 1, 1, 1, \ 972: 1, 1, 1, 1, 1, 1, 1, 1, \ 973: 1, 1, 1, 1, 1, 1, 1, 1, \ 974: 1, 1, 1, 1, 1, 1, 1, 1, \ 975: 1, 1, 1, 1, 1, 1, 1, 1, \ 976: 1, 1, 1, 1, 1, 1, 1, 1, \ 977: 1, 1, 1, 1} 978: #else 979: #define LEAF_REGISTERS \ 980: { 1, 1, 1, 1, 1, 1, 1, 0, \ 1.1 root 981: 0, 0, 0, 0, 0, 0, 1, 0, \ 982: 0, 0, 0, 0, 0, 0, 0, 0, \ 983: 1, 1, 1, 1, 1, 1, 0, 1, \ 984: 1, 1, 1, 1, 1, 1, 1, 1, \ 985: 1, 1, 1, 1, 1, 1, 1, 1, \ 986: 1, 1, 1, 1, 1, 1, 1, 1, \ 987: 1, 1, 1, 1, 1, 1, 1, 1} 1.1.1.3 root 988: #endif 1.1 root 989: 990: extern char leaf_reg_remap[]; 991: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 992: 993: /* The class value for index registers, and the one for base regs. */ 994: #define INDEX_REG_CLASS GENERAL_REGS 995: #define BASE_REG_CLASS GENERAL_REGS 996: 1.1.1.3 root 997: /* Local macro to handle the two v9 classes of FP regs. */ 998: #ifdef SPARCV9 999: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1000: #else 1001: #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS) 1002: #endif 1003: 1.1 root 1004: /* Get reg_class from a letter such as appears in the machine description. */ 1005: 1.1.1.3 root 1006: #ifdef SPARCV9 1.1 root 1007: #define REG_CLASS_FROM_LETTER(C) \ 1.1.1.3 root 1008: ((C) == 'f' ? FP_REGS \ 1009: : (C) == 'e' ? EXTRA_FP_REGS \ 1010: : (C) == 'c' ? FPCC_REGS \ 1011: : NO_REGS) 1012: #else 1013: /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for 1014: v8 and v9. */ 1015: #define REG_CLASS_FROM_LETTER(C) \ 1016: ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS) 1017: #endif 1.1 root 1018: 1019: /* The letters I, J, K, L and M in a register constraint string 1020: can be used to stand for particular ranges of immediate operands. 1021: This macro defines what the ranges are. 1022: C is the letter, and VALUE is a constant value. 1023: Return 1 if VALUE is in the range specified by C. 1024: 1025: For SPARC, `I' is used for the range of constants an insn 1026: can actually contain. 1027: `J' is used for the range which is just zero (since that is R0). 1028: `K' is used for constants which can be loaded with a single sethi insn. */ 1029: 1030: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) 1031: 1032: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1033: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ 1034: : (C) == 'J' ? (VALUE) == 0 \ 1035: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ 1036: : 0) 1037: 1038: /* Similar, but for floating constants, and defining letters G and H. 1039: Here VALUE is the CONST_DOUBLE rtx itself. */ 1040: 1041: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1.1.1.2 root 1042: ((C) == 'G' ? fp_zero_operand (VALUE) \ 1.1 root 1043: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1044: : 0) 1045: 1046: /* Given an rtx X being reloaded into a reg required to be 1047: in class CLASS, return the class of reg to actually use. 1048: In general this is just CLASS; but on some machines 1049: in some cases it is preferable to use a more restrictive class. */ 1050: /* We can't load constants into FP registers. We can't load any FP constant 1051: if an 'E' constraint fails to match it. */ 1052: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1053: (CONSTANT_P (X) \ 1.1.1.3 root 1054: && (FP_REG_CLASS_P (CLASS) \ 1.1 root 1055: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1056: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ 1057: || HOST_BITS_PER_INT != BITS_PER_WORD))) \ 1058: ? NO_REGS : (CLASS)) 1059: 1060: /* Return the register class of a scratch register needed to load IN into 1061: a register of class CLASS in MODE. 1062: 1063: On the SPARC, when PIC, we need a temporary when loading some addresses 1064: into a register. 1065: 1066: Also, we need a temporary when loading/storing a HImode/QImode value 1067: between memory and the FPU registers. This can happen when combine puts 1068: a paradoxical subreg in a float/fix conversion insn. */ 1069: 1070: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 root 1071: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ 1072: && (GET_CODE (IN) == MEM \ 1073: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1074: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1075: 1076: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1.1.1.3 root 1077: ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ 1078: && (GET_CODE (IN) == MEM \ 1079: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1080: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) 1.1 root 1081: 1082: /* On SPARC it is not possible to directly move data between 1083: GENERAL_REGS and FP_REGS. */ 1.1.1.3 root 1084: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1085: (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1.1 root 1086: 1.1.1.3 root 1087: /* Return the stack location to use for secondary memory needed reloads. 1088: We want to use the reserved location just below the frame pointer. 1089: However, we must ensure that there is a frame, so use assign_stack_local 1090: if the frame size is zero. */ 1.1 root 1091: #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1.1.1.3 root 1092: (get_frame_size () == 0 \ 1.1.1.4 root 1093: ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1.1.1.3 root 1094: : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ 1095: GEN_INT (STARTING_FRAME_OFFSET)))) 1096: 1097: /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9 1098: because the movsi and movsf patterns don't handle r/f moves. 1099: For v8 we copy the default definition. */ 1100: #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1101: (TARGET_V9 \ 1.1.1.4 root 1102: ? (GET_MODE_BITSIZE (MODE) < 32 \ 1103: ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1.1.1.3 root 1104: : MODE) \ 1.1.1.4 root 1105: : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1106: ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1.1.1.3 root 1107: : MODE)) 1.1 root 1108: 1109: /* Return the maximum number of consecutive registers 1110: needed to represent mode MODE in a register of class CLASS. */ 1111: /* On SPARC, this is the size of MODE in words. */ 1112: #define CLASS_MAX_NREGS(CLASS, MODE) \ 1.1.1.3 root 1113: (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1114: : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1 root 1115: 1116: /* Stack layout; function entry, exit and calling. */ 1117: 1118: /* Define the number of register that can hold parameters. 1.1.1.3 root 1119: These two macros are used only in other macro definitions below. 1120: MODE is the mode of the argument. 1121: !v9: All args are passed in %o0-%o5. 1122: v9: Non-float args are passed in %o0-5 and float args are passed in 1123: %f0-%f15. */ 1124: #define NPARM_REGS(MODE) \ 1125: (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6) 1.1 root 1126: 1127: /* Define this if pushing a word on the stack 1128: makes the stack pointer a smaller address. */ 1129: #define STACK_GROWS_DOWNWARD 1130: 1131: /* Define this if the nominal address of the stack frame 1132: is at the high-address end of the local variables; 1133: that is, each additional local variable allocated 1134: goes at a more negative offset in the frame. */ 1135: #define FRAME_GROWS_DOWNWARD 1136: 1137: /* Offset within stack frame to start allocating local variables at. 1138: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1139: first local allocated. Otherwise, it is the offset to the BEGINNING 1140: of the first local allocated. */ 1.1.1.3 root 1141: /* This allows space for one TFmode floating point value. */ 1142: #define STARTING_FRAME_OFFSET \ 1143: (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \ 1144: : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1.1 root 1145: 1146: /* If we generate an insn to push BYTES bytes, 1147: this says how many the stack pointer really advances by. 1148: On SPARC, don't define this because there are no push insns. */ 1149: /* #define PUSH_ROUNDING(BYTES) */ 1150: 1151: /* Offset of first parameter from the argument pointer register value. 1.1.1.3 root 1152: !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1153: even if this function isn't going to use it. 1154: v9: This is 128 for the ins and locals, plus a reserved space of 8. */ 1155: #define FIRST_PARM_OFFSET(FNDECL) \ 1156: (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \ 1157: : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) 1.1 root 1158: 1159: /* When a parameter is passed in a register, stack space is still 1160: allocated for it. */ 1.1.1.3 root 1161: #ifndef SPARCV9 1162: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD) 1163: #endif 1.1 root 1164: 1165: /* Keep the stack pointer constant throughout the function. 1166: This is both an optimization and a necessity: longjmp 1167: doesn't behave itself when the stack pointer moves within 1168: the function! */ 1169: #define ACCUMULATE_OUTGOING_ARGS 1170: 1171: /* Value is the number of bytes of arguments automatically 1172: popped when returning from a subroutine call. 1.1.1.4 root 1173: FUNDECL is the declaration node of the function (as a tree), 1.1 root 1174: FUNTYPE is the data type of the function (as a tree), 1175: or for a library call it is an identifier node for the subroutine name. 1176: SIZE is the number of bytes of arguments passed on the stack. */ 1177: 1.1.1.4 root 1178: #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1.1 root 1179: 1180: /* Some subroutine macros specific to this machine. 1181: When !TARGET_FPU, put float return values in the general registers, 1182: since we don't have any fp registers. */ 1183: #define BASE_RETURN_VALUE_REG(MODE) \ 1.1.1.3 root 1184: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ 1185: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) 1.1 root 1186: #define BASE_OUTGOING_VALUE_REG(MODE) \ 1.1.1.3 root 1187: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ 1188: : TARGET_FRW ? 8 : 24) \ 1189: : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ 1190: : (TARGET_FRW ? 8 : 24))) 1191: #define BASE_PASSING_ARG_REG(MODE) \ 1192: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ 1193: : (8)) 1194: #define BASE_INCOMING_ARG_REG(MODE) \ 1195: (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ 1196: : TARGET_FRW ? 8 : 24) \ 1197: : (TARGET_FRW ? 8 : 24)) 1.1 root 1198: 1199: /* Define this macro if the target machine has "register windows". This 1200: C expression returns the register number as seen by the called function 1201: corresponding to register number OUT as seen by the calling function. 1202: Return OUT if register number OUT is not an outbound register. */ 1203: 1204: #define INCOMING_REGNO(OUT) \ 1205: ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1206: 1207: /* Define this macro if the target machine has "register windows". This 1208: C expression returns the register number as seen by the calling function 1209: corresponding to register number IN as seen by the called function. 1210: Return IN if register number IN is not an inbound register. */ 1211: 1212: #define OUTGOING_REGNO(IN) \ 1213: ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1214: 1215: /* Define how to find the value returned by a function. 1216: VALTYPE is the data type of the value (as a tree). 1217: If the precise function being called is known, FUNC is its FUNCTION_DECL; 1218: otherwise, FUNC is 0. */ 1219: 1220: /* On SPARC the value is found in the first "output" register. */ 1221: 1222: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1223: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 1224: 1225: /* But the called function leaves it in the first "input" register. */ 1226: 1227: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1228: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) 1229: 1230: /* Define how to find the value returned by a library function 1231: assuming the value has mode MODE. */ 1232: 1233: #define LIBCALL_VALUE(MODE) \ 1234: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) 1235: 1236: /* 1 if N is a possible register number for a function value 1237: as seen by the caller. 1238: On SPARC, the first "output" reg is used for integer values, 1239: and the first floating point register is used for floating point values. */ 1240: 1241: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1242: 1.1.1.2 root 1243: /* Define the size of space to allocate for the return value of an 1244: untyped_call. */ 1245: 1246: #define APPLY_RESULT_SIZE 16 1247: 1.1 root 1248: /* 1 if N is a possible register number for function argument passing. 1.1.1.3 root 1249: On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */ 1.1 root 1250: 1.1.1.3 root 1251: #define FUNCTION_ARG_REGNO_P(N) \ 1252: (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \ 1253: : ((N) < 14 && (N) > 7)) 1.1 root 1254: 1255: /* Define a data type for recording info about an argument list 1256: during the scan of that argument list. This data type should 1257: hold all necessary information about the function itself 1258: and about the args processed so far, enough to enable macros 1259: such as FUNCTION_ARG to determine where the next arg should go. 1260: 1.1.1.3 root 1261: On SPARC (!v9), this is a single integer, which is a number of words 1.1 root 1262: of arguments scanned so far (including the invisible argument, 1263: if any, which holds the structure-value-address). 1.1.1.3 root 1264: Thus 7 or more means all following args should go on the stack. 1.1 root 1265: 1.1.1.3 root 1266: For v9, we record how many of each type has been passed. Different 1267: types get passed differently. 1268: 1269: - Float args are passed in %f0-15, after which they go to the stack 1270: where floats and doubles are passed 8 byte aligned and long doubles 1271: are passed 16 byte aligned. 1272: - All aggregates are passed by reference. The callee copies 1273: the structure if necessary, except if stdarg/varargs and the struct 1274: matches the ellipse in which case the caller makes a copy. 1275: - Any non-float argument might be split between memory and reg %o5. 1276: ??? I don't think this can ever happen now that structs are no 1277: longer passed in regs. 1278: 1279: For v9 return values: 1280: 1281: - For all aggregates, the caller allocates space for the return value, 1282: and passes the pointer as an implicit first argument, which is 1283: allocated like all other arguments. 1284: - The unimp instruction stuff for structure returns is gone. */ 1285: 1286: #ifdef SPARCV9 1287: enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 }; 1288: struct sparc_args { 1289: int arg_count[2]; /* must be int! (for __builtin_args_info) */ 1290: }; 1291: #define CUMULATIVE_ARGS struct sparc_args 1292: 1293: /* Return index into CUMULATIVE_ARGS. */ 1294: 1295: #define GET_SPARC_ARG_CLASS(MODE) \ 1296: (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT) 1297: 1298: /* Round a register number up to a proper boundary for an arg of mode MODE. 1299: This macro is only used in this file. 1300: 1301: The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */ 1302: 1303: #define ROUND_REG(CUM, MODE) \ 1304: (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 1305: ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ 1306: : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ 1307: + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \ 1308: & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4)) 1309: 1310: #define ROUND_ADVANCE(SIZE) \ 1311: (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1312: 1313: #else /* ! SPARCV9 */ 1.1 root 1314: #define CUMULATIVE_ARGS int 1315: 1.1.1.3 root 1316: #define ROUND_REG(CUM, MODE) (CUM) 1317: 1.1 root 1318: #define ROUND_ADVANCE(SIZE) \ 1319: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1.1.1.3 root 1320: #endif /* ! SPARCV9 */ 1.1 root 1321: 1322: /* Initialize a variable CUM of type CUMULATIVE_ARGS 1323: for a call to a function whose data type is FNTYPE. 1324: For a library call, FNTYPE is 0. 1325: 1326: On SPARC, the offset always starts at 0: the first parm reg is always 1327: the same reg. */ 1328: 1.1.1.3 root 1329: #ifdef SPARCV9 1330: extern int sparc_arg_count,sparc_n_named_args; 1331: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ 1332: do { \ 1333: (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \ 1334: (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \ 1335: sparc_arg_count = 0; \ 1336: sparc_n_named_args = \ 1337: ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \ 1338: ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \ 1339: + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \ 1340: || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \ 1341: /* Can't tell, treat 'em all as named. */ \ 1342: : 10000); \ 1343: } while (0) 1344: #else 1.1 root 1345: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) 1.1.1.3 root 1346: #endif 1.1 root 1347: 1348: /* Update the data in CUM to advance over an argument 1349: of mode MODE and data type TYPE. 1350: (TYPE is null for libcalls where that information may not be available.) */ 1351: 1.1.1.3 root 1352: #ifdef SPARCV9 1353: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1354: do { \ 1355: (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \ 1356: ROUND_REG ((CUM), (MODE)) \ 1357: + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1358: ? GET_MODE_SIZE (MODE) / 4 \ 1359: : ROUND_ADVANCE ((MODE) == BLKmode \ 1360: ? GET_MODE_SIZE (Pmode) \ 1361: : GET_MODE_SIZE (MODE))); \ 1362: sparc_arg_count++; \ 1363: } while (0) 1364: #else 1.1 root 1365: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1366: ((CUM) += ((MODE) != BLKmode \ 1367: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 1368: : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) 1.1.1.3 root 1369: #endif 1370: 1371: /* Return boolean indicating arg of mode MODE will be passed in a reg. 1372: This macro is only used in this file. */ 1373: 1374: #ifdef SPARCV9 1375: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1376: (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ 1377: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ 1378: && ((TYPE)==0 || (MODE) != BLKmode)) 1379: #else 1380: #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1381: ((CUM) < NPARM_REGS (SImode) \ 1382: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ 1383: && ((TYPE)==0 || (MODE) != BLKmode \ 1384: || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0))) 1385: #endif 1.1 root 1386: 1387: /* Determine where to put an argument to a function. 1388: Value is zero to push the argument on the stack, 1389: or a hard register in which to store the argument. 1390: 1391: MODE is the argument's machine mode. 1392: TYPE is the data type of the argument (as a tree). 1393: This is null for libcalls where that information may 1394: not be available. 1395: CUM is a variable of type CUMULATIVE_ARGS which gives info about 1396: the preceding args and about the function being called. 1397: NAMED is nonzero if this argument is a named parameter 1398: (otherwise it is an extra parameter matching an ellipsis). */ 1399: 1400: /* On SPARC the first six args are normally in registers 1401: and the rest are pushed. Any arg that starts within the first 6 words 1.1.1.3 root 1402: is at least partially passed in a register unless its data type forbids. 1403: For v9, the first 6 int args are passed in regs and the first N 1404: float args are passed in regs (where N is such that %f0-15 are filled). 1405: The rest are pushed. Any arg that starts within the first 6 words 1.1 root 1406: is at least partially passed in a register unless its data type forbids. */ 1407: 1408: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1409: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1410: ? gen_rtx (REG, (MODE), \ 1411: (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ 1412: : 0) 1.1 root 1413: 1414: /* Define where a function finds its arguments. 1415: This is different from FUNCTION_ARG because of register windows. */ 1416: 1417: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1418: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1419: ? gen_rtx (REG, (MODE), \ 1420: (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ 1421: : 0) 1.1 root 1422: 1423: /* For an arg passed partly in registers and partly in memory, 1424: this is the number of registers used. 1425: For args passed entirely in registers or entirely in memory, zero. 1426: Any arg that starts in the first 6 regs but won't entirely fit in them 1.1.1.3 root 1427: needs partial registers on the Sparc (!v9). On v9, there are no arguments 1428: that are passed partially in registers (??? complex values?). */ 1.1 root 1429: 1.1.1.3 root 1430: #ifndef SPARCV9 1.1 root 1431: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1.1.1.3 root 1432: (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1433: && ((CUM) + ((MODE) == BLKmode \ 1434: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 1435: : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\ 1436: ? (NPARM_REGS (SImode) - (CUM)) \ 1.1 root 1437: : 0) 1.1.1.3 root 1438: #endif 1.1 root 1439: 1440: /* The SPARC ABI stipulates passing struct arguments (of any size) and 1.1.1.3 root 1441: (!v9) quad-precision floats by invisible reference. 1442: For Pascal, also pass arrays by reference. */ 1.1 root 1443: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1444: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ 1.1.1.3 root 1445: || TREE_CODE (TYPE) == UNION_TYPE \ 1446: || TREE_CODE (TYPE) == ARRAY_TYPE)) \ 1447: || (!TARGET_V9 && MODE == TFmode)) 1448: 1449: /* A C expression that indicates when it is the called function's 1450: responsibility to make copies of arguments passed by reference. 1451: If the callee can determine that the argument won't be modified, it can 1452: avoid the copy. */ 1453: /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't 1454: include the last named argument so we keep track of the args ourselves. */ 1455: 1456: #ifdef SPARCV9 1457: #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ 1458: (sparc_arg_count < sparc_n_named_args) 1459: #endif 1460: 1461: /* Initialize data used by insn expanders. This is called from 1462: init_emit, once for each function, before code is generated. 1463: For v9, clear the temp slot used by float/int DImode conversions. 1464: ??? There is the 16 bytes at [%fp-16], however we'd like to delete this 1465: space at some point. 1466: ??? Use assign_stack_temp? */ 1467: 1468: extern void sparc64_init_expanders (); 1469: extern struct rtx_def *sparc64_fpconv_stack_temp (); 1470: #ifdef SPARCV9 1471: #define INIT_EXPANDERS sparc64_init_expanders () 1472: #endif 1.1 root 1473: 1474: /* Define the information needed to generate branch and scc insns. This is 1475: stored from the compare operation. Note that we can't use "rtx" here 1476: since it hasn't been defined! */ 1477: 1478: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; 1479: 1480: /* Define the function that build the compare insn for scc and bcc. */ 1481: 1482: extern struct rtx_def *gen_compare_reg (); 1.1.1.3 root 1483: 1484: /* This function handles all v9 scc insns */ 1485: 1486: extern int gen_v9_scc (); 1.1 root 1487: 1488: /* Generate the special assembly code needed to tell the assembler whatever 1489: it might need to know about the return value of a function. 1490: 1491: For Sparc assemblers, we need to output a .proc pseudo-op which conveys 1492: information to the assembler relating to peephole optimization (done in 1493: the assembler). */ 1494: 1495: #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1496: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) 1497: 1498: /* Output the label for a function definition. */ 1499: 1500: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1501: do { \ 1502: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1503: ASM_OUTPUT_LABEL (FILE, NAME); \ 1504: } while (0) 1505: 1506: /* This macro generates the assembly code for function entry. 1507: FILE is a stdio stream to output the code to. 1508: SIZE is an int: how many units of temporary storage to allocate. 1509: Refer to the array `regs_ever_live' to determine which registers 1510: to save; `regs_ever_live[I]' is nonzero if register number I 1511: is ever used in the function. This macro is responsible for 1512: knowing which registers should not be saved even if used. */ 1513: 1514: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block 1515: of memory. If any fpu reg is used in the function, we allocate 1516: such a block here, at the bottom of the frame, just in case it's needed. 1517: 1518: If this function is a leaf procedure, then we may choose not 1519: to do a "save" insn. The decision about whether or not 1520: to do this is made in regclass.c. */ 1521: 1.1.1.3 root 1522: extern int leaf_function; 1.1 root 1523: #define FUNCTION_PROLOGUE(FILE, SIZE) \ 1.1.1.3 root 1524: (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \ 1.1 root 1525: : output_function_prologue (FILE, SIZE, leaf_function)) 1526: 1527: /* Output assembler code to FILE to increment profiler label # LABELNO 1528: for profiling a function entry. */ 1529: 1530: #define FUNCTION_PROFILER(FILE, LABELNO) \ 1531: do { \ 1532: fputs ("\tsethi %hi(", (FILE)); \ 1533: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1.1.1.3 root 1534: fputs ("),%o0\n", (FILE)); \ 1535: if (TARGET_MEDANY) \ 1536: fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \ 1537: MEDANY_BASE_REG); \ 1538: fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \ 1.1 root 1539: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ 1540: fputs ("),%o0,%o0\n", (FILE)); \ 1541: } while (0) 1542: 1543: /* Output assembler code to FILE to initialize this source file's 1544: basic block profiling info, if that has not already been done. */ 1545: 1546: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ 1.1.1.3 root 1547: do { \ 1548: if (TARGET_MEDANY) \ 1549: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ 1550: MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \ 1551: else \ 1552: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ 1553: (LABELNO), (LABELNO)); \ 1554: } while (0) 1.1 root 1555: 1556: /* Output assembler code to FILE to increment the entry-count for 1557: the BLOCKNO'th basic block in this source file. */ 1558: 1559: #define BLOCK_PROFILER(FILE, BLOCKNO) \ 1.1.1.3 root 1560: { \ 1561: int blockn = (BLOCKNO); \ 1562: if (TARGET_MEDANY) \ 1563: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ 1564: 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ 1565: else \ 1566: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ 1567: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ 1568: 4 * blockn, 4 * blockn, 4 * blockn); \ 1.1 root 1569: } 1570: 1571: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1572: the stack pointer does not matter. The value is tested only in 1573: functions that have frame pointers. 1574: No definition is equivalent to always zero. */ 1575: 1576: extern int current_function_calls_alloca; 1577: extern int current_function_outgoing_args_size; 1578: 1579: #define EXIT_IGNORE_STACK \ 1580: (get_frame_size () != 0 \ 1581: || current_function_calls_alloca || current_function_outgoing_args_size) 1582: 1583: /* This macro generates the assembly code for function exit, 1584: on machines that need it. If FUNCTION_EPILOGUE is not defined 1585: then individual return instructions are generated for each 1586: return statement. Args are same as for FUNCTION_PROLOGUE. 1587: 1588: The function epilogue should not depend on the current stack pointer! 1589: It should use the frame pointer only. This is mandatory because 1590: of alloca; we also take advantage of it to omit stack adjustments 1591: before returning. */ 1592: 1593: /* This declaration is needed due to traditional/ANSI 1594: incompatibilities which cannot be #ifdefed away 1595: because they occur inside of macros. Sigh. */ 1596: extern union tree_node *current_function_decl; 1597: 1598: #define FUNCTION_EPILOGUE(FILE, SIZE) \ 1.1.1.3 root 1599: (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \ 1.1 root 1600: : output_function_epilogue (FILE, SIZE, leaf_function)) 1601: 1602: #define DELAY_SLOTS_FOR_EPILOGUE \ 1.1.1.3 root 1603: (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1) 1.1 root 1604: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ 1.1.1.3 root 1605: (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ 1.1 root 1606: : eligible_for_epilogue_delay (trial, slots_filled)) 1.1.1.2 root 1607: 1.1 root 1608: /* Output assembler code for a block containing the constant parts 1609: of a trampoline, leaving space for the variable parts. */ 1610: 1.1.1.4 root 1611: /* On 32 bit sparcs, the trampoline contains five instructions: 1.1.1.2 root 1612: sethi #TOP_OF_FUNCTION,%g1 1613: or #BOTTOM_OF_FUNCTION,%g1,%g1 1614: sethi #TOP_OF_STATIC,%g2 1615: jmp g1 1.1.1.4 root 1616: or #BOTTOM_OF_STATIC,%g2,%g2 1617: 1618: On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate 1619: constants (plus some padding): 1620: rd %pc,%g1 1621: ldx[%g1+20],%g5 1622: ldx[%g1+28],%g1 1623: jmp %g1 1624: nop 1625: nop 1626: .xword context 1627: .xword function */ 1628: 1629: #define TRAMPOLINE_TEMPLATE(FILE) \ 1630: do { \ 1631: if (TARGET_V9) \ 1632: { \ 1633: fprintf (FILE, "\trd %%pc,%%g1\n"); \ 1634: fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \ 1635: fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \ 1636: fprintf (FILE, "\tjmp %%g1\n"); \ 1637: fprintf (FILE, "\tnop\n"); \ 1638: fprintf (FILE, "\tnop\n"); \ 1639: /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \ 1640: fprintf (FILE, "\t.word 0,0,0,0\n"); \ 1641: } \ 1642: else \ 1643: { \ 1644: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1645: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1646: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1647: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \ 1648: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ 1649: } \ 1650: } while (0) 1.1 root 1651: 1652: /* Length in units of the trampoline for entering a nested function. */ 1653: 1.1.1.4 root 1654: #define TRAMPOLINE_SIZE (TARGET_V9 ? 40 : 20) 1.1 root 1655: 1656: /* Emit RTL insns to initialize the variable parts of a trampoline. 1657: FNADDR is an RTX for the address of the function's pure code. 1.1.1.3 root 1658: CXT is an RTX for the static chain value for the function. */ 1.1.1.2 root 1659: 1.1.1.3 root 1660: void sparc_initialize_trampoline (); 1661: void sparc64_initialize_trampoline (); 1662: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1663: do { \ 1664: if (TARGET_V9) \ 1665: sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1666: else \ 1667: sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1668: } while (0) 1.1.1.2 root 1669: 1.1 root 1670: /* Generate necessary RTL for __builtin_saveregs(). 1671: ARGLIST is the argument list; see expr.c. */ 1672: extern struct rtx_def *sparc_builtin_saveregs (); 1673: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) 1674: 1675: /* Generate RTL to flush the register windows so as to make arbitrary frames 1676: available. */ 1677: #define SETUP_FRAME_ADDRESSES() \ 1678: emit_insn (gen_flush_register_windows ()) 1679: 1680: /* Given an rtx for the address of a frame, 1681: return an rtx for the address of the word in the frame 1.1.1.3 root 1682: that holds the dynamic chain--the previous frame's address. 1683: ??? -mflat support? */ 1.1 root 1684: #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1.1.1.3 root 1685: gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD)) 1.1 root 1686: 1687: /* The return address isn't on the stack, it is in a register, so we can't 1688: access it from the current frame pointer. We can access it from the 1689: previous frame pointer though by reading a value from the register window 1690: save area. */ 1691: #define RETURN_ADDR_IN_PREVIOUS_FRAME 1692: 1.1.1.4 root 1693: /* This is the offset of the return address to the true next instruction to be 1694: executed for normal void functions. */ 1695: #define NORMAL_RETURN_ADDR_OFFSET (8) 1696: 1.1 root 1697: /* The current return address is in %i7. The return address of anything 1698: farther back is in the register window save area at [%fp+60]. */ 1699: /* ??? This ignores the fact that the actual return address is +8 for normal 1700: returns, and +12 for structure returns. */ 1701: #define RETURN_ADDR_RTX(count, frame) \ 1702: ((count == -1) \ 1703: ? gen_rtx (REG, Pmode, 31) \ 1.1.1.4 root 1704: : gen_rtx (MEM, Pmode, \ 1705: memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))) 1.1 root 1706: 1707: /* Addressing modes, and classification of registers for them. */ 1708: 1709: /* #define HAVE_POST_INCREMENT */ 1710: /* #define HAVE_POST_DECREMENT */ 1711: 1712: /* #define HAVE_PRE_DECREMENT */ 1713: /* #define HAVE_PRE_INCREMENT */ 1714: 1715: /* Macros to check register numbers against specific register classes. */ 1716: 1717: /* These assume that REGNO is a hard or pseudo reg number. 1718: They give nonzero only if REGNO is a hard reg of the suitable class 1719: or a pseudo reg currently allocated to a suitable hard reg. 1720: Since they use reg_renumber, they are safe only once reg_renumber 1721: has been allocated, which happens in local-alloc.c. */ 1722: 1723: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1724: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1725: #define REGNO_OK_FOR_BASE_P(REGNO) \ 1726: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) 1727: #define REGNO_OK_FOR_FP_P(REGNO) \ 1.1.1.3 root 1728: (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \ 1729: || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32))) 1730: #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1731: (TARGET_V9 \ 1732: && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4)) 1.1 root 1733: 1734: /* Now macros that check whether X is a register and also, 1735: strictly, whether it is in a specified class. 1736: 1737: These macros are specific to the SPARC, and may be used only 1738: in code for printing assembler insns and in conditions for 1739: define_optimization. */ 1740: 1741: /* 1 if X is an fp register. */ 1742: 1743: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1744: 1745: /* Maximum number of registers that can appear in a valid memory address. */ 1746: 1747: #define MAX_REGS_PER_ADDRESS 2 1748: 1.1.1.2 root 1749: /* Recognize any constant value that is a valid address. 1750: When PIC, we do not accept an address that would require a scratch reg 1751: to load into a register. */ 1.1 root 1752: 1753: #define CONSTANT_ADDRESS_P(X) \ 1754: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1.1.1.2 root 1755: || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 1756: || (GET_CODE (X) == CONST \ 1757: && ! (flag_pic && pic_address_needs_scratch (X)))) 1758: 1759: /* Define this, so that when PIC, reload won't try to reload invalid 1760: addresses which require two reload registers. */ 1761: 1762: #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) 1.1 root 1763: 1764: /* Nonzero if the constant value X is a legitimate general operand. 1765: Anything can be made to work except floating point constants. */ 1766: 1767: #define LEGITIMATE_CONSTANT_P(X) \ 1768: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) 1769: 1770: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1771: and check its validity for a certain class. 1772: We have two alternate definitions for each of them. 1773: The usual definition accepts all pseudo regs; the other rejects 1774: them unless they have been allocated suitable hard regs. 1775: The symbol REG_OK_STRICT causes the latter definition to be used. 1776: 1777: Most source files want to accept pseudo regs in the hope that 1778: they will get allocated to the class that the insn wants them to be in. 1779: Source files for reload pass need to be strict. 1780: After reload, it makes no difference, since pseudo regs have 1781: been eliminated by then. */ 1782: 1783: /* Optional extra constraints for this machine. Borrowed from romp.h. 1784: 1785: For the SPARC, `Q' means that this is a memory operand but not a 1786: symbolic memory operand. Note that an unassigned pseudo register 1787: is such a memory operand. Needed because reload will generate 1788: these things in insns and then not re-recognize the insns, causing 1789: constrain_operands to fail. 1790: 1.1.1.3 root 1791: `S' handles constraints for calls. ??? So where is it? */ 1.1 root 1792: 1793: #ifndef REG_OK_STRICT 1794: 1795: /* Nonzero if X is a hard reg that can be used as an index 1796: or if it is a pseudo reg. */ 1.1.1.3 root 1797: #define REG_OK_FOR_INDEX_P(X) \ 1798: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) 1.1 root 1799: /* Nonzero if X is a hard reg that can be used as a base reg 1800: or if it is a pseudo reg. */ 1.1.1.3 root 1801: #define REG_OK_FOR_BASE_P(X) \ 1802: (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) 1803: 1804: /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ 1.1 root 1805: 1806: #define EXTRA_CONSTRAINT(OP, C) \ 1807: ((C) == 'Q' \ 1808: ? ((GET_CODE (OP) == MEM \ 1.1.1.3 root 1809: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ 1.1 root 1810: && ! symbolic_memory_operand (OP, VOIDmode)) \ 1811: || (reload_in_progress && GET_CODE (OP) == REG \ 1812: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ 1.1.1.3 root 1813: : ! TARGET_V9 && (C) == 'T' \ 1.1 root 1814: ? (mem_aligned_8 (OP)) \ 1.1.1.3 root 1815: : ! TARGET_V9 && (C) == 'U' \ 1.1 root 1816: ? (register_ok_for_ldd (OP)) \ 1817: : 0) 1818: 1819: #else 1820: 1821: /* Nonzero if X is a hard reg that can be used as an index. */ 1822: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1823: /* Nonzero if X is a hard reg that can be used as a base reg. */ 1824: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1825: 1826: #define EXTRA_CONSTRAINT(OP, C) \ 1827: ((C) == 'Q' \ 1828: ? (GET_CODE (OP) == REG \ 1829: ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ 1830: && reg_renumber[REGNO (OP)] < 0) \ 1831: : GET_CODE (OP) == MEM) \ 1.1.1.3 root 1832: : ! TARGET_V9 && (C) == 'T' \ 1.1.1.2 root 1833: ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ 1.1.1.3 root 1834: : ! TARGET_V9 && (C) == 'U' \ 1.1.1.2 root 1835: ? (GET_CODE (OP) == REG \ 1836: && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ 1837: || reg_renumber[REGNO (OP)] > 0) \ 1838: && register_ok_for_ldd (OP)) : 0) 1.1 root 1839: #endif 1840: 1841: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1842: that is a valid memory address for an instruction. 1843: The MODE argument is the machine mode for the MEM expression 1844: that wants to use this address. 1845: 1846: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1847: ordinarily. This changes a bit when generating PIC. 1848: 1849: If you change this, execute "rm explow.o recog.o reload.o". */ 1850: 1851: #define RTX_OK_FOR_BASE_P(X) \ 1852: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1853: || (GET_CODE (X) == SUBREG \ 1854: && GET_CODE (SUBREG_REG (X)) == REG \ 1855: && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1856: 1857: #define RTX_OK_FOR_INDEX_P(X) \ 1858: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1859: || (GET_CODE (X) == SUBREG \ 1860: && GET_CODE (SUBREG_REG (X)) == REG \ 1861: && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1862: 1863: #define RTX_OK_FOR_OFFSET_P(X) \ 1864: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) 1865: 1866: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1867: { if (RTX_OK_FOR_BASE_P (X)) \ 1868: goto ADDR; \ 1869: else if (GET_CODE (X) == PLUS) \ 1870: { \ 1871: register rtx op0 = XEXP (X, 0); \ 1872: register rtx op1 = XEXP (X, 1); \ 1873: if (flag_pic && op0 == pic_offset_table_rtx) \ 1874: { \ 1875: if (RTX_OK_FOR_BASE_P (op1)) \ 1876: goto ADDR; \ 1877: else if (flag_pic == 1 \ 1878: && GET_CODE (op1) != REG \ 1879: && GET_CODE (op1) != LO_SUM \ 1.1.1.2 root 1880: && GET_CODE (op1) != MEM \ 1881: && (GET_CODE (op1) != CONST_INT \ 1882: || SMALL_INT (op1))) \ 1.1 root 1883: goto ADDR; \ 1884: } \ 1885: else if (RTX_OK_FOR_BASE_P (op0)) \ 1886: { \ 1887: if (RTX_OK_FOR_INDEX_P (op1) \ 1888: || RTX_OK_FOR_OFFSET_P (op1)) \ 1889: goto ADDR; \ 1890: } \ 1891: else if (RTX_OK_FOR_BASE_P (op1)) \ 1892: { \ 1893: if (RTX_OK_FOR_INDEX_P (op0) \ 1894: || RTX_OK_FOR_OFFSET_P (op0)) \ 1895: goto ADDR; \ 1896: } \ 1897: } \ 1898: else if (GET_CODE (X) == LO_SUM) \ 1899: { \ 1900: register rtx op0 = XEXP (X, 0); \ 1901: register rtx op1 = XEXP (X, 1); \ 1902: if (RTX_OK_FOR_BASE_P (op0) \ 1.1.1.3 root 1903: && CONSTANT_P (op1) \ 1904: /* We can't allow TFmode, because an offset \ 1905: greater than or equal to the alignment (8) \ 1906: may cause the LO_SUM to overflow. */ \ 1907: && MODE != TFmode) \ 1.1 root 1908: goto ADDR; \ 1909: } \ 1910: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ 1911: goto ADDR; \ 1912: } 1913: 1914: /* Try machine-dependent ways of modifying an illegitimate address 1915: to be legitimate. If we find one, return the new, valid address. 1916: This macro is used in only one place: `memory_address' in explow.c. 1917: 1918: OLDX is the address as it was before break_out_memory_refs was called. 1919: In some cases it is useful to look at this to decide what needs to be done. 1920: 1921: MODE and WIN are passed so that this macro can use 1922: GO_IF_LEGITIMATE_ADDRESS. 1923: 1924: It is always safe for this macro to do nothing. It exists to recognize 1925: opportunities to optimize the output. */ 1926: 1927: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 1928: extern struct rtx_def *legitimize_pic_address (); 1929: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1930: { rtx sparc_x = (X); \ 1931: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ 1932: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1933: force_operand (XEXP (X, 0), NULL_RTX)); \ 1934: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ 1935: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1936: force_operand (XEXP (X, 1), NULL_RTX)); \ 1937: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ 1938: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ 1939: XEXP (X, 1)); \ 1940: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ 1941: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1942: force_operand (XEXP (X, 1), NULL_RTX)); \ 1943: if (sparc_x != (X) && memory_address_p (MODE, X)) \ 1944: goto WIN; \ 1.1.1.2 root 1945: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ 1.1 root 1946: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ 1947: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 1948: copy_to_mode_reg (Pmode, XEXP (X, 1))); \ 1949: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ 1950: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ 1951: copy_to_mode_reg (Pmode, XEXP (X, 0))); \ 1952: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 1953: || GET_CODE (X) == LABEL_REF) \ 1954: (X) = gen_rtx (LO_SUM, Pmode, \ 1955: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ 1956: if (memory_address_p (MODE, X)) \ 1957: goto WIN; } 1958: 1959: /* Go to LABEL if ADDR (a legitimate address expression) 1960: has an effect that depends on the machine mode it is used for. 1961: On the SPARC this is never true. */ 1962: 1963: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) 1.1.1.3 root 1964: 1965: /* If we are referencing a function make the SYMBOL_REF special. 1966: In the Medium/Anywhere code model, %g4 points to the data segment so we 1967: must not add it to function addresses. */ 1968: 1969: #define ENCODE_SECTION_INFO(DECL) \ 1970: do { \ 1971: if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ 1972: SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ 1973: } while (0) 1.1 root 1974: 1975: /* Specify the machine mode that this machine uses 1976: for the index in the tablejump instruction. */ 1.1.1.3 root 1977: #define CASE_VECTOR_MODE Pmode 1.1 root 1978: 1979: /* Define this if the tablejump instruction expects the table 1980: to contain offsets from the address of the table. 1981: Do not define this if the table should contain absolute addresses. */ 1982: /* #define CASE_VECTOR_PC_RELATIVE */ 1983: 1984: /* Specify the tree operation to be used to convert reals to integers. */ 1985: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1986: 1987: /* This is the kind of divide that is easiest to do in the general case. */ 1988: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1989: 1990: /* Define this as 1 if `char' should by default be signed; else as 0. */ 1991: #define DEFAULT_SIGNED_CHAR 1 1992: 1993: /* Max number of bytes we can move from memory to memory 1994: in one reasonably fast instruction. */ 1995: #define MOVE_MAX 8 1996: 1997: #if 0 /* Sun 4 has matherr, so this is no good. */ 1998: /* This is the value of the error code EDOM for this machine, 1999: used by the sqrt instruction. */ 2000: #define TARGET_EDOM 33 2001: 2002: /* This is how to refer to the variable errno. */ 2003: #define GEN_ERRNO_RTX \ 2004: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) 2005: #endif /* 0 */ 2006: 1.1.1.2 root 2007: /* Define if operations between registers always perform the operation 2008: on the full register even if a narrower mode is specified. */ 2009: #define WORD_REGISTER_OPERATIONS 2010: 2011: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2012: will either zero-extend or sign-extend. The value of this macro should 2013: be the code that says which one of the two operations is implicitly 2014: done, NIL if none. */ 2015: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1.1 root 2016: 2017: /* Nonzero if access to memory by bytes is slow and undesirable. 2018: For RISC chips, it means that access to memory by bytes is no 2019: better than access by words when possible, so grab a whole word 2020: and maybe make use of that. */ 2021: #define SLOW_BYTE_ACCESS 1 2022: 2023: /* We assume that the store-condition-codes instructions store 0 for false 2024: and some other value for true. This is the value stored for true. */ 2025: 2026: #define STORE_FLAG_VALUE 1 2027: 2028: /* When a prototype says `char' or `short', really pass an `int'. */ 2029: #define PROMOTE_PROTOTYPES 2030: 1.1.1.2 root 2031: /* Define this to be nonzero if shift instructions ignore all but the low-order 2032: few bits. */ 2033: #define SHIFT_COUNT_TRUNCATED 1 1.1 root 2034: 2035: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2036: is done just by pretending it is already truncated. */ 2037: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2038: 2039: /* Specify the machine mode that pointers have. 2040: After generation of rtl, the compiler makes no further distinction 2041: between pointers and any other objects of this machine mode. */ 1.1.1.3 root 2042: #define Pmode (TARGET_PTR64 ? DImode : SImode) 1.1 root 2043: 2044: /* Generate calls to memcpy, memcmp and memset. */ 2045: #define TARGET_MEM_FUNCTIONS 2046: 2047: /* Add any extra modes needed to represent the condition code. 2048: 2049: On the Sparc, we have a "no-overflow" mode which is used when an add or 2050: subtract insn is used to set the condition code. Different branches are 2051: used in this case for some operations. 2052: 2053: We also have two modes to indicate that the relevant condition code is 2054: in the floating-point condition code register. One for comparisons which 2055: will generate an exception if the result is unordered (CCFPEmode) and 2056: one for comparisons which will never trap (CCFPmode). This really should 1.1.1.3 root 2057: be a separate register, but we don't want to go to 65 registers. 2058: 2059: CCXmode and CCX_NOOVmode are only used by v9. */ 2060: 2061: #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode 1.1 root 2062: 2063: /* Define the names for the modes specified above. */ 1.1.1.3 root 2064: 2065: #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" 1.1 root 2066: 2067: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2068: return the mode to be used for the comparison. For floating-point, 2069: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a 1.1.1.2 root 2070: PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2071: processing is needed. */ 1.1 root 2072: #define SELECT_CC_MODE(OP,X,Y) \ 2073: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1.1.1.2 root 2074: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ 2075: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 2076: || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ 1.1.1.3 root 2077: ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ 2078: : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode))) 2079: 2080: /* Return non-zero if SELECT_CC_MODE will never return MODE for a 2081: floating point inequality comparison. */ 2082: 2083: #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 1.1 root 2084: 2085: /* A function address in a call instruction 2086: is a byte address (for indexing purposes) 2087: so give the MEM rtx a byte's mode. */ 2088: #define FUNCTION_MODE SImode 2089: 2090: /* Define this if addresses of constant functions 2091: shouldn't be put through pseudo regs where they can be cse'd. 2092: Desirable on machines where ordinary constants are expensive 2093: but a CALL with constant address is cheap. */ 2094: #define NO_FUNCTION_CSE 2095: 2096: /* alloca should avoid clobbering the old register save area. */ 2097: #define SETJMP_VIA_SAVE_AREA 2098: 2099: /* Define subroutines to call to handle multiply and divide. 2100: Use the subroutines that Sun's library provides. 2101: The `*' prevents an underscore from being prepended by the compiler. */ 2102: 2103: #define DIVSI3_LIBCALL "*.div" 2104: #define UDIVSI3_LIBCALL "*.udiv" 2105: #define MODSI3_LIBCALL "*.rem" 2106: #define UMODSI3_LIBCALL "*.urem" 2107: /* .umul is a little faster than .mul. */ 2108: #define MULSI3_LIBCALL "*.umul" 2109: 1.1.1.3 root 2110: /* Define library calls for quad FP operations. These are all part of the 2111: SPARC ABI. */ 2112: #define ADDTF3_LIBCALL "_Q_add" 2113: #define SUBTF3_LIBCALL "_Q_sub" 1.1.1.4 root 2114: #define NEGTF2_LIBCALL "_Q_neg" 1.1.1.3 root 2115: #define MULTF3_LIBCALL "_Q_mul" 2116: #define DIVTF3_LIBCALL "_Q_div" 2117: #define FLOATSITF2_LIBCALL "_Q_itoq" 2118: #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" 2119: #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" 2120: #define EXTENDSFTF2_LIBCALL "_Q_stoq" 2121: #define TRUNCTFSF2_LIBCALL "_Q_qtos" 2122: #define EXTENDDFTF2_LIBCALL "_Q_dtoq" 2123: #define TRUNCTFDF2_LIBCALL "_Q_qtod" 2124: #define EQTF2_LIBCALL "_Q_feq" 2125: #define NETF2_LIBCALL "_Q_fne" 2126: #define GTTF2_LIBCALL "_Q_fgt" 2127: #define GETF2_LIBCALL "_Q_fge" 2128: #define LTTF2_LIBCALL "_Q_flt" 2129: #define LETF2_LIBCALL "_Q_fle" 2130: 2131: /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because 2132: with soft-float, the SFmode and DFmode sqrt instructions will be absent, 2133: and the compiler will notice and try to use the TFmode sqrt instruction 2134: for calls to the builtin function sqrt, but this fails. */ 1.1.1.4 root 2135: #define INIT_TARGET_OPTABS \ 2136: do { \ 2137: add_optab->handlers[(int) TFmode].libfunc \ 2138: = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \ 2139: sub_optab->handlers[(int) TFmode].libfunc \ 2140: = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \ 2141: neg_optab->handlers[(int) TFmode].libfunc \ 2142: = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \ 2143: smul_optab->handlers[(int) TFmode].libfunc \ 2144: = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \ 2145: flodiv_optab->handlers[(int) TFmode].libfunc \ 2146: = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \ 2147: eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \ 2148: netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \ 2149: gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \ 2150: getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \ 2151: lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \ 2152: letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \ 2153: trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \ 2154: trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \ 2155: extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \ 2156: extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \ 2157: floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \ 2158: fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \ 2159: fixunstfsi_libfunc \ 2160: = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \ 2161: if (TARGET_FPU) \ 2162: sqrt_optab->handlers[(int) TFmode].libfunc \ 2163: = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \ 2164: INIT_SUBTARGET_OPTABS; \ 1.1.1.3 root 2165: } while (0) 2166: 2167: /* This is meant to be redefined in the host dependent files */ 2168: #define INIT_SUBTARGET_OPTABS 2169: 1.1 root 2170: /* Compute the cost of computing a constant rtl expression RTX 2171: whose rtx-code is CODE. The body of this macro is a portion 2172: of a switch statement. If the code is computed here, 2173: return it with a return statement. Otherwise, break from the switch. */ 2174: 2175: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 2176: case CONST_INT: \ 2177: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ 2178: return 0; \ 2179: case HIGH: \ 2180: return 2; \ 2181: case CONST: \ 2182: case LABEL_REF: \ 2183: case SYMBOL_REF: \ 2184: return 4; \ 2185: case CONST_DOUBLE: \ 2186: if (GET_MODE (RTX) == DImode) \ 2187: if ((XINT (RTX, 3) == 0 \ 2188: && (unsigned) XINT (RTX, 2) < 0x1000) \ 2189: || (XINT (RTX, 3) == -1 \ 2190: && XINT (RTX, 2) < 0 \ 2191: && XINT (RTX, 2) >= -0x1000)) \ 2192: return 0; \ 2193: return 8; 2194: 1.1.1.3 root 2195: /* Compute the cost of an address. For the sparc, all valid addresses are 2196: the same cost. 2197: ??? Is this true for v9? */ 1.1 root 2198: 1.1.1.3 root 2199: #define ADDRESS_COST(RTX) 1 1.1 root 2200: 2201: /* Compute extra cost of moving data between one register class 1.1.1.3 root 2202: and another. 2203: ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */ 1.1 root 2204: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 1.1.1.3 root 2205: (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \ 2206: || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2) 1.1 root 2207: 2208: /* Provide the costs of a rtl expression. This is in the body of a 2209: switch on CODE. The purpose for the cost of MULT is to encourage 2210: `synth_mult' to find a synthetic multiply when reasonable. 2211: 2212: If we need more than 12 insns to do a multiply, then go out-of-line, 2213: since the call overhead will be < 10% of the cost of the multiply. */ 2214: 2215: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 2216: case MULT: \ 1.1.1.4 root 2217: return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ 1.1 root 2218: case DIV: \ 2219: case UDIV: \ 2220: case MOD: \ 2221: case UMOD: \ 2222: return COSTS_N_INSNS (25); \ 2223: /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ 2224: so that cse will favor the latter. */ \ 2225: case FLOAT: \ 2226: case FIX: \ 2227: return 19; 2228: 1.1.1.3 root 2229: /* Adjust the cost of dependencies. */ 2230: #define ADJUST_COST(INSN,LINK,DEP,COST) \ 2231: if (TARGET_SUPERSPARC) \ 2232: (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST) 2233: 1.1 root 2234: /* Conditional branches with empty delay slots have a length of two. */ 2235: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2236: if (GET_CODE (INSN) == CALL_INSN \ 2237: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ 2238: LENGTH += 1; 2239: 2240: /* Control the assembler format that we output. */ 2241: 2242: /* Output at beginning of assembler file. */ 2243: 2244: #define ASM_FILE_START(file) 2245: 2246: /* Output to assembler file text saying following lines 2247: may contain character constants, extra white space, comments, etc. */ 2248: 2249: #define ASM_APP_ON "" 2250: 2251: /* Output to assembler file text saying following lines 2252: no longer contain unusual constructs. */ 2253: 2254: #define ASM_APP_OFF "" 2255: 1.1.1.3 root 2256: /* ??? Try to make the style consistent here (_OP?). */ 2257: 2258: #define ASM_LONGLONG ".xword" 1.1 root 2259: #define ASM_LONG ".word" 2260: #define ASM_SHORT ".half" 2261: #define ASM_BYTE_OP ".byte" 1.1.1.3 root 2262: #define ASM_FLOAT ".single" 2263: #define ASM_DOUBLE ".double" 2264: #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ 1.1 root 2265: 2266: /* Output before read-only data. */ 2267: 2268: #define TEXT_SECTION_ASM_OP ".text" 2269: 2270: /* Output before writable data. */ 2271: 2272: #define DATA_SECTION_ASM_OP ".data" 2273: 2274: /* How to refer to registers in assembler output. 2275: This sequence is indexed by compiler's hard-register-number (see above). */ 2276: 1.1.1.3 root 2277: #ifdef SPARCV9 2278: #define REGISTER_NAMES \ 2279: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2280: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2281: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2282: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2283: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2284: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2285: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2286: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2287: "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2288: "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2289: "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2290: "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2291: "%fcc0", "%fcc1", "%fcc2", "%fcc3"} 2292: #else 1.1 root 2293: #define REGISTER_NAMES \ 2294: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2295: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2296: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2297: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2298: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2299: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2300: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2301: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} 1.1.1.3 root 2302: #endif 1.1 root 2303: 2304: /* Define additional names for use in asm clobbers and asm declarations. 2305: 2306: We define the fake Condition Code register as an alias for reg 0 (which 2307: is our `condition code' register), so that condition codes can easily 2308: be clobbered by an asm. No such register actually exists. Condition 2309: codes are partly stored in the PSR and partly in the FSR. */ 2310: 2311: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} 2312: 2313: /* How to renumber registers for dbx and gdb. */ 2314: 2315: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 2316: 2317: /* On Sun 4, this limit is 2048. We use 1500 to be safe, 2318: since the length can run past this up to a continuation point. */ 2319: #define DBX_CONTIN_LENGTH 1500 2320: 2321: /* This is how to output a note to DBX telling it the line number 2322: to which the following sequence of instructions corresponds. 2323: 2324: This is needed for SunOS 4.0, and should not hurt for 3.2 2325: versions either. */ 2326: #define ASM_OUTPUT_SOURCE_LINE(file, line) \ 2327: { static int sym_lineno = 1; \ 2328: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ 2329: line, sym_lineno, sym_lineno); \ 2330: sym_lineno += 1; } 2331: 2332: /* This is how to output the definition of a user-level label named NAME, 2333: such as the label on a static function or variable NAME. */ 2334: 2335: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 2336: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 2337: 2338: /* This is how to output a command to make the user-level label named NAME 2339: defined for reference from other files. */ 2340: 2341: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 2342: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) 2343: 2344: /* This is how to output a reference to a user-level label named NAME. 2345: `assemble_name' uses this. */ 2346: 2347: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2348: fprintf (FILE, "_%s", NAME) 2349: 2350: /* This is how to output a definition of an internal numbered label where 2351: PREFIX is the class of label and NUM is the number within the class. */ 2352: 2353: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 2354: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 2355: 2356: /* This is how to output a reference to an internal numbered label where 2357: PREFIX is the class of label and NUM is the number within the class. */ 2358: /* FIXME: This should be used throughout gcc, and documented in the texinfo 2359: files. There is no reason you should have to allocate a buffer and 2360: `sprintf' to reference an internal label (as opposed to defining it). */ 2361: 2362: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ 2363: fprintf (FILE, "%s%d", PREFIX, NUM) 2364: 2365: /* This is how to store into the string LABEL 2366: the symbol_ref name of an internal numbered label where 2367: PREFIX is the class of label and NUM is the number within the class. 2368: This is suitable for output with `assemble_name'. */ 2369: 2370: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2371: sprintf (LABEL, "*%s%d", PREFIX, NUM) 2372: 2373: /* This is how to output an assembler line defining a `double' constant. */ 2374: 2375: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 2376: { \ 1.1.1.2 root 2377: long t[2]; \ 2378: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ 2379: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2380: ASM_LONG, t[0], ASM_LONG, t[1]); \ 1.1 root 2381: } 2382: 2383: /* This is how to output an assembler line defining a `float' constant. */ 2384: 2385: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 2386: { \ 1.1.1.2 root 2387: long t; \ 2388: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ 2389: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ 2390: } \ 1.1 root 2391: 2392: /* This is how to output an assembler line defining a `long double' 2393: constant. */ 2394: 2395: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ 2396: { \ 2397: long t[4]; \ 2398: REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ 2399: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ 2400: ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ 2401: } 2402: 2403: /* This is how to output an assembler line defining an `int' constant. */ 2404: 2405: #define ASM_OUTPUT_INT(FILE,VALUE) \ 2406: ( fprintf (FILE, "\t%s\t", ASM_LONG), \ 2407: output_addr_const (FILE, (VALUE)), \ 2408: fprintf (FILE, "\n")) 2409: 2410: /* This is how to output an assembler line defining a DImode constant. */ 2411: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ 2412: output_double_int (FILE, VALUE) 2413: 2414: /* Likewise for `char' and `short' constants. */ 2415: 2416: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 2417: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ 2418: output_addr_const (FILE, (VALUE)), \ 2419: fprintf (FILE, "\n")) 2420: 2421: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 2422: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ 2423: output_addr_const (FILE, (VALUE)), \ 2424: fprintf (FILE, "\n")) 2425: 2426: /* This is how to output an assembler line for a numeric constant byte. */ 2427: 2428: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 2429: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) 2430: 2431: /* This is how to output an element of a case-vector that is absolute. */ 2432: 2433: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2434: do { \ 2435: char label[30]; \ 2436: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 root 2437: if (Pmode == SImode) \ 2438: fprintf (FILE, "\t.word\t"); \ 2439: else if (TARGET_ENV32) \ 2440: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ 2441: else \ 2442: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2443: assemble_name (FILE, label); \ 2444: fprintf (FILE, "\n"); \ 2445: } while (0) 2446: 2447: /* This is how to output an element of a case-vector that is relative. 2448: (SPARC uses such vectors only when generating PIC.) */ 2449: 2450: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 2451: do { \ 2452: char label[30]; \ 2453: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1.1.1.3 root 2454: if (Pmode == SImode) \ 2455: fprintf (FILE, "\t.word\t"); \ 2456: else if (TARGET_ENV32) \ 2457: fprintf (FILE, "\t.word\t0\n\t.word\t"); \ 2458: else \ 2459: fprintf (FILE, "\t.xword\t"); \ 1.1 root 2460: assemble_name (FILE, label); \ 2461: fprintf (FILE, "-1b\n"); \ 2462: } while (0) 2463: 2464: /* This is how to output an assembler line 2465: that says to advance the location counter 2466: to a multiple of 2**LOG bytes. */ 2467: 2468: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2469: if ((LOG) != 0) \ 2470: fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2471: 2472: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2473: fprintf (FILE, "\t.skip %u\n", (SIZE)) 2474: 2475: /* This says how to output an assembler line 2476: to define a global common symbol. */ 2477: 2478: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1.1.1.3 root 2479: ( fputs ("\t.common ", (FILE)), \ 1.1 root 2480: assemble_name ((FILE), (NAME)), \ 1.1.1.3 root 2481: fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) 1.1 root 2482: 1.1.1.3 root 2483: /* This says how to output an assembler line to define a local common 2484: symbol. */ 1.1 root 2485: 1.1.1.3 root 2486: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2487: ( fputs ("\t.reserve ", (FILE)), \ 2488: assemble_name ((FILE), (NAME)), \ 2489: fprintf ((FILE), ",%u,\"bss\",%u\n", \ 2490: (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1.1 root 2491: 2492: /* Store in OUTPUT a string (made with alloca) containing 2493: an assembler-name for a local static variable named NAME. 2494: LABELNO is an integer which is different for each call. */ 2495: 2496: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2497: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2498: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2499: 2500: #define IDENT_ASM_OP ".ident" 2501: 2502: /* Output #ident as a .ident. */ 2503: 2504: #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2505: fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); 2506: 2507: /* Define the parentheses used to group arithmetic operations 2508: in assembler code. */ 2509: 2510: #define ASM_OPEN_PAREN "(" 2511: #define ASM_CLOSE_PAREN ")" 2512: 2513: /* Define results of standard character escape sequences. */ 2514: #define TARGET_BELL 007 2515: #define TARGET_BS 010 2516: #define TARGET_TAB 011 2517: #define TARGET_NEWLINE 012 2518: #define TARGET_VT 013 2519: #define TARGET_FF 014 2520: #define TARGET_CR 015 2521: 2522: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2523: ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') 2524: 2525: /* Print operand X (an rtx) in assembler syntax to file FILE. 2526: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2527: For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2528: 2529: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2530: 2531: /* Print a memory address as an operand to reference that memory location. */ 2532: 2533: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2534: { register rtx base, index = 0; \ 2535: int offset = 0; \ 2536: register rtx addr = ADDR; \ 2537: if (GET_CODE (addr) == REG) \ 2538: fputs (reg_names[REGNO (addr)], FILE); \ 2539: else if (GET_CODE (addr) == PLUS) \ 2540: { \ 2541: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2542: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2543: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2544: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2545: else \ 2546: base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2547: fputs (reg_names[REGNO (base)], FILE); \ 2548: if (index == 0) \ 2549: fprintf (FILE, "%+d", offset); \ 2550: else if (GET_CODE (index) == REG) \ 2551: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 1.1.1.4 root 2552: else if (GET_CODE (index) == SYMBOL_REF \ 2553: || GET_CODE (index) == CONST) \ 1.1 root 2554: fputc ('+', FILE), output_addr_const (FILE, index); \ 2555: else abort (); \ 2556: } \ 2557: else if (GET_CODE (addr) == MINUS \ 2558: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2559: { \ 2560: output_addr_const (FILE, XEXP (addr, 0)); \ 2561: fputs ("-(", FILE); \ 2562: output_addr_const (FILE, XEXP (addr, 1)); \ 2563: fputs ("-.)", FILE); \ 2564: } \ 2565: else if (GET_CODE (addr) == LO_SUM) \ 2566: { \ 2567: output_operand (XEXP (addr, 0), 0); \ 2568: fputs ("+%lo(", FILE); \ 2569: output_address (XEXP (addr, 1)); \ 2570: fputc (')', FILE); \ 2571: } \ 2572: else if (flag_pic && GET_CODE (addr) == CONST \ 2573: && GET_CODE (XEXP (addr, 0)) == MINUS \ 2574: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2575: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2576: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2577: { \ 2578: addr = XEXP (addr, 0); \ 2579: output_addr_const (FILE, XEXP (addr, 0)); \ 2580: /* Group the args of the second CONST in parenthesis. */ \ 2581: fputs ("-(", FILE); \ 2582: /* Skip past the second CONST--it does nothing for us. */\ 2583: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2584: /* Close the parenthesis. */ \ 2585: fputc (')', FILE); \ 2586: } \ 2587: else \ 2588: { \ 2589: output_addr_const (FILE, addr); \ 2590: } \ 2591: } 2592: 2593: /* Declare functions defined in sparc.c and used in templates. */ 2594: 2595: extern char *singlemove_string (); 2596: extern char *output_move_double (); 2597: extern char *output_move_quad (); 2598: extern char *output_fp_move_double (); 2599: extern char *output_fp_move_quad (); 2600: extern char *output_block_move (); 2601: extern char *output_scc_insn (); 2602: extern char *output_cbranch (); 1.1.1.3 root 2603: extern char *output_v9branch (); 1.1 root 2604: extern char *output_return (); 2605: 2606: /* Defined in flags.h, but insn-emit.c does not include flags.h. */ 2607: 2608: extern int flag_pic;
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