--- gcc/config/sparc/sparc.md	2018/04/24 18:21:35	1.1.1.3
+++ gcc/config/sparc/sparc.md	2018/04/24 18:29:01	1.1.1.4
@@ -1,8 +1,8 @@
 ;;- Machine description for SPARC chip for GNU C compiler
-;;   Copyright (C) 1987, 88, 89, 92, 93, 1994 Free Software Foundation, Inc.
-;;   Contributed by Michael Tiemann (tiemann@cygnus.com)
-;;   64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
-;;   at Cygnus Support.
+;;  Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc.
+;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
+;;  64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
+;;  at Cygnus Support.
 
 ;; This file is part of GNU CC.
 
@@ -18,7 +18,8 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
@@ -688,7 +689,7 @@
 
 ;; Now the DEFINE_INSNs for the compare and scc cases.  First the compares.
 
-(define_insn ""
+(define_insn "*cmpsi_insn"
   [(set (reg:CC 0)
 	(compare:CC (match_operand:SI 0 "register_operand" "r")
 		    (match_operand:SI 1 "arith_operand" "rI")))]
@@ -696,7 +697,7 @@
   "cmp %r0,%1"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmpsf_fpe_sp32"
   [(set (reg:CCFPE 0)
 	(compare:CCFPE (match_operand:SF 0 "register_operand" "f")
 		       (match_operand:SF 1 "register_operand" "f")))]
@@ -704,7 +705,7 @@
   "fcmpes %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpdf_fpe_sp32"
   [(set (reg:CCFPE 0)
 	(compare:CCFPE (match_operand:DF 0 "register_operand" "e")
 		       (match_operand:DF 1 "register_operand" "e")))]
@@ -712,7 +713,7 @@
   "fcmped %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmptf_fpe_sp32"
   [(set (reg:CCFPE 0)
 	(compare:CCFPE (match_operand:TF 0 "register_operand" "e")
 		       (match_operand:TF 1 "register_operand" "e")))]
@@ -720,7 +721,7 @@
   "fcmpeq %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpsf_fp_sp32"
   [(set (reg:CCFP 0)
 	(compare:CCFP (match_operand:SF 0 "register_operand" "f")
 		      (match_operand:SF 1 "register_operand" "f")))]
@@ -728,7 +729,7 @@
   "fcmps %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpdf_fp_sp32"
   [(set (reg:CCFP 0)
 	(compare:CCFP (match_operand:DF 0 "register_operand" "e")
 		      (match_operand:DF 1 "register_operand" "e")))]
@@ -736,7 +737,7 @@
   "fcmpd %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmptf_fp_sp32"
   [(set (reg:CCFP 0)
 	(compare:CCFP (match_operand:TF 0 "register_operand" "e")
 		      (match_operand:TF 1 "register_operand" "e")))]
@@ -744,7 +745,7 @@
   "fcmpq %0,%1"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpdi_sp64"
   [(set (reg:CCX 0)
 	(compare:CCX (match_operand:DI 0 "register_operand" "r")
 		     (match_operand:DI 1 "arith_double_operand" "rHI")))]
@@ -752,7 +753,7 @@
   "cmp %r0,%1"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmpsf_fpe_sp64"
   [(set (match_operand:CCFPE 0 "ccfp_reg_operand" "=c")
 	(compare:CCFPE (match_operand:SF 1 "register_operand" "f")
 		       (match_operand:SF 2 "register_operand" "f")))]
@@ -760,7 +761,7 @@
   "fcmpes %0,%1,%2"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpdf_fpe_sp64"
   [(set (match_operand:CCFPE 0 "ccfp_reg_operand" "=c")
 	(compare:CCFPE (match_operand:DF 1 "register_operand" "e")
 		       (match_operand:DF 2 "register_operand" "e")))]
@@ -768,7 +769,7 @@
   "fcmped %0,%1,%2"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmptf_fpe_sp64"
   [(set (match_operand:CCFPE 0 "ccfp_reg_operand" "=c")
 	(compare:CCFPE (match_operand:TF 1 "register_operand" "e")
 		       (match_operand:TF 2 "register_operand" "e")))]
@@ -776,7 +777,7 @@
   "fcmpeq %0,%1,%2"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpsf_fp_sp64"
   [(set (match_operand:CCFP 0 "ccfp_reg_operand" "=c")
 	(compare:CCFP (match_operand:SF 1 "register_operand" "f")
 		      (match_operand:SF 2 "register_operand" "f")))]
@@ -784,7 +785,7 @@
   "fcmps %0,%1,%2"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmpdf_fp_sp64"
   [(set (match_operand:CCFP 0 "ccfp_reg_operand" "=c")
 	(compare:CCFP (match_operand:DF 1 "register_operand" "e")
 		      (match_operand:DF 2 "register_operand" "e")))]
@@ -792,7 +793,7 @@
   "fcmpd %0,%1,%2"
   [(set_attr "type" "fpcmp")])
 
-(define_insn ""
+(define_insn "*cmptf_fp_sp64"
   [(set (match_operand:CCFP 0 "ccfp_reg_operand" "=c")
 	(compare:CCFP (match_operand:TF 1 "register_operand" "e")
 		      (match_operand:TF 2 "register_operand" "e")))]
@@ -803,7 +804,7 @@
 ;; The SEQ and SNE patterns are special because they can be done
 ;; without any branching and do not involve a COMPARE.
 
-(define_insn ""
+(define_insn "*snesi_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ne:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
@@ -813,7 +814,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*neg_snesi_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
@@ -823,7 +824,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*snedi_zero"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ne:DI (match_operand:DI 1 "register_operand" "r")
 	       (const_int 0)))
@@ -833,7 +834,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*neg_snedi_zero"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
 		       (const_int 0))))
@@ -843,7 +844,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*seqsi_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(eq:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
@@ -853,7 +854,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*neg_seqsi_zero"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
@@ -863,7 +864,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*seqdi_zero"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(eq:DI (match_operand:DI 1 "register_operand" "r")
 	       (const_int 0)))
@@ -873,7 +874,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*neg_seqdi_zero"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
 		       (const_int 0))))
@@ -887,7 +888,7 @@
 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
 ;; versions for v9.
 
-(define_insn ""
+(define_insn "*x_plus_i_ne_0"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
 			(const_int 0))
@@ -897,7 +898,7 @@
   "subcc %%g0,%1,%%g0\;addx %2,0,%0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*x_minus_i_ne_0"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 2 "register_operand" "r")
 		  (ne:SI (match_operand:SI 1 "register_operand" "r")
@@ -907,7 +908,7 @@
   "subcc %%g0,%1,%%g0\;subx %2,0,%0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*x_plus_i_eq_0"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
 			(const_int 0))
@@ -917,7 +918,7 @@
   "subcc %%g0,%1,%%g0\;subx %2,-1,%0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*x_minus_i_eq_0"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 2 "register_operand" "r")
 		  (eq:SI (match_operand:SI 1 "register_operand" "r")
@@ -931,14 +932,14 @@
 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
 ;; versions for v9.
 
-(define_insn ""
+(define_insn "*sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ltu:SI (reg:CC 0) (const_int 0)))]
   ""
   "addx %%g0,0,%0"
   [(set_attr "type" "misc")])
 
-(define_insn ""
+(define_insn "*neg_sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (ltu:SI (reg:CC 0) (const_int 0))))]
   ""
@@ -946,7 +947,7 @@
   [(set_attr "type" "misc")])
 
 ;; ??? Combine should canonicalize these next two to the same pattern.
-(define_insn ""
+(define_insn "*neg_sltu_minus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (neg:SI (ltu:SI (reg:CC 0) (const_int 0)))
 		  (match_operand:SI 1 "arith_operand" "rI")))]
@@ -954,7 +955,7 @@
   "subx %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*neg_sltu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (plus:SI (ltu:SI (reg:CC 0) (const_int 0))
 			 (match_operand:SI 1 "arith_operand" "rI"))))]
@@ -962,14 +963,14 @@
   "subx %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(geu:SI (reg:CC 0) (const_int 0)))]
   ""
   "subx %%g0,-1,%0"
   [(set_attr "type" "misc")])
 
-(define_insn ""
+(define_insn "*neg_sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (geu:SI (reg:CC 0) (const_int 0))))]
   ""
@@ -980,7 +981,7 @@
 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
 ;; versions for v9.
 
-(define_insn ""
+(define_insn "*sltu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (ltu:SI (reg:CC 0) (const_int 0))
 		 (match_operand:SI 1 "arith_operand" "rI")))]
@@ -988,7 +989,7 @@
   "addx %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*sltu_plus_x_plus_y"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (ltu:SI (reg:CC 0) (const_int 0))
 		 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
@@ -996,7 +997,7 @@
   ""
   "addx %1,%2,%0")
 
-(define_insn ""
+(define_insn "*x_minus_sltu"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 1 "register_operand" "r")
 		  (ltu:SI (reg:CC 0) (const_int 0))))]
@@ -1005,7 +1006,7 @@
   [(set_attr "type" "unary")])
 
 ;; ??? Combine should canonicalize these next two to the same pattern.
-(define_insn ""
+(define_insn "*x_minus_y_minus_sltu"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
 			    (match_operand:SI 2 "arith_operand" "rI"))
@@ -1013,7 +1014,7 @@
   ""
   "subx %1,%2,%0")
 
-(define_insn ""
+(define_insn "*x_minus_sltu_plus_y"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 1 "register_operand" "r")
 		  (plus:SI (ltu:SI (reg:CC 0) (const_int 0))
@@ -1021,7 +1022,7 @@
   ""
   "subx %1,%2,%0")
 
-(define_insn ""
+(define_insn "*sgeu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (geu:SI (reg:CC 0) (const_int 0))
 		 (match_operand:SI 1 "register_operand" "r")))]
@@ -1029,7 +1030,7 @@
   "subx %1,-1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*x_minus_sgeu"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 1 "register_operand" "r")
 		  (geu:SI (reg:CC 0) (const_int 0))))]
@@ -1043,7 +1044,7 @@
 ;; We have to exclude the cases above, since we will not want combine to
 ;; turn something that does not require a jump into something that does.
 
-(define_insn ""
+(define_insn "*scc_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operator:SI 1 "noov_compare_op" [(reg 0) (const_int 0)]))]
   ""
@@ -1051,7 +1052,7 @@
   [(set_attr "type" "multi")
    (set_attr "length" "3")])
 
-(define_insn ""
+(define_insn "*scc_di"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operator:DI 1 "noov_compare_op" [(reg 0) (const_int 0)]))]
   "TARGET_V9"
@@ -1251,7 +1252,7 @@
 
 ;; Now match both normal and inverted jump.
 
-(define_insn ""
+(define_insn "*normal_branch"
   [(set (pc)
 	(if_then_else (match_operator 0 "noov_compare_op"
 				      [(reg 0) (const_int 0)])
@@ -1266,7 +1267,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*inverted_branch"
   [(set (pc)
 	(if_then_else (match_operator 0 "noov_compare_op"
 				      [(reg 0) (const_int 0)])
@@ -1281,7 +1282,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*normal_fp_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "comparison_operator"
 				      [(match_operand:CCFP 1 "ccfp_reg_operand" "c")
@@ -1297,7 +1298,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*inverted_fp_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "comparison_operator"
 				      [(match_operand:CCFP 1 "ccfp_reg_operand" "c")
@@ -1313,7 +1314,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*normal_fpe_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "comparison_operator"
 				      [(match_operand:CCFPE 1 "ccfp_reg_operand" "c")
@@ -1329,7 +1330,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*inverted_fpe_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "comparison_operator"
 				      [(match_operand:CCFPE 1 "ccfp_reg_operand" "c")
@@ -1350,7 +1351,7 @@
 
 ;; There are no 32 bit brreg insns.
 
-(define_insn ""
+(define_insn "*normal_int_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "v9_regcmp_op"
 				      [(match_operand:DI 1 "register_operand" "r")
@@ -1366,7 +1367,7 @@
 }"
   [(set_attr "type" "branch")])
 
-(define_insn ""
+(define_insn "*inverted_int_branch_sp64"
   [(set (pc)
 	(if_then_else (match_operator 0 "v9_regcmp_op"
 				      [(match_operand:DI 1 "register_operand" "r")
@@ -1384,7 +1385,7 @@
 
 ;; Esoteric move insns (lo_sum, high, pic).
 
-(define_insn ""
+(define_insn "*lo_sum_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "immediate_operand" "in")))]
@@ -1398,7 +1399,7 @@
 
 ;; For PIC, symbol_refs are put inside unspec so that the optimizer will not
 ;; confuse them with real addresses.
-(define_insn ""
+(define_insn "*pic_lo_sum_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
@@ -1412,7 +1413,7 @@
 
 ;; For PIC, symbol_refs are put inside unspec so that the optimizer will not
 ;; confuse them with real addresses.
-(define_insn ""
+(define_insn "*pic_sethi_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
   "check_pic (1)"
@@ -1420,7 +1421,7 @@
   [(set_attr "type" "move")
    (set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*sethi_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (match_operand 1 "" "")))]
   "check_pic (1)"
@@ -1428,7 +1429,7 @@
   [(set_attr "type" "move")
    (set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*sethi_hi"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(high:HI (match_operand 1 "" "")))]
   "check_pic (1)"
@@ -1440,7 +1441,7 @@
 ;; It clobbers o7 because the call puts the return address (i.e. pc value)
 ;; there.
 
-(define_insn ""
+(define_insn "*move_pic_label_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operand:SI 1 "move_pic_label" "i"))
    (set (reg:SI 15) (pc))]
@@ -1451,7 +1452,7 @@
 
 ;; v9 special pic pattern, for loading the address of a label into a register.
 
-(define_insn ""
+(define_insn "*move_pic_label_di"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operand:DI 1 "move_pic_label" "i"))
    (set (reg:DI 15) (pc))]
@@ -1460,7 +1461,7 @@
   [(set_attr "type" "multi")
    (set_attr "length" "4")])
 
-(define_insn ""
+(define_insn "*lo_sum_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lo_sum:DI (match_operand:DI 1 "register_operand" "0")
 		   (match_operand:DI 2 "immediate_operand" "in")))]
@@ -1481,7 +1482,7 @@
 ;; ??? The previous comment is obsolete.
 ;; ??? Optimizer does not handle "or %o1,%lo(0),%o1". How about add?
 
-(define_insn ""
+(define_insn "*lo_sum_di_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lo_sum:DI (match_operand:DI 1 "register_operand" "0")
 		   (match_operand:DI 2 "immediate_operand" "in")))]
@@ -1500,7 +1501,7 @@
   ;; is not an "arith_operand".
   [(set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*sethi_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "" "")))]
   "! TARGET_V9 && check_pic (1)"
@@ -1538,7 +1539,7 @@
    (set_attr "length" "2")])
 
 ;;; ??? This pattern originally clobbered a scratch register.  However, this
-;;; is illegal, the movdi pattern may not use a temp register because it
+;;; is invalid, the movdi pattern may not use a temp register because it
 ;;; may be called from reload to reload a DImode value.  In that case, we
 ;;; end up with a scratch register that never gets allocated.  To avoid this,
 ;;; we use global register 1 which is never otherwise used by gcc as a temp.
@@ -1551,7 +1552,7 @@
 ;;; %uhi and %ulo for them, but gas will handle these correctly.
 ;;; ??? This comment is obsolete, gas handles them now.
 
-(define_insn ""
+(define_insn "*sethi_di_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "const_double_operand" "")))
    (clobber (reg:DI 1))]
@@ -1577,6 +1578,8 @@
       if (low != const0_rtx)
 	output_asm_insn (\"sethi %%hi(%a1),%%g1; or %0,%%g1,%0\", operands);
     }
+
+  return \"\";
 }"
   [(set_attr "type" "move")
    (set_attr "length" "5")])
@@ -1593,7 +1596,7 @@
 ;; MEDANY_BASE_REG contains the start address, currently %g4.
 ;; When TARGET_FULLANY, symbolic addresses are 64 bits.
 
-(define_insn ""
+(define_insn "*sethi_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "" "")))
 ;; ??? Why the clobber?
@@ -1606,7 +1609,7 @@
 ;; WARNING: %0 gets %hi(%1)+%g4.
 ;;          You cannot OR in %lo(%1), it must be added in.
 
-(define_insn ""
+(define_insn "*sethi_di_medany_data"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "data_segment_operand" "")))
 ;; ??? Why the clobber?
@@ -1616,7 +1619,7 @@
   [(set_attr "type" "move")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*sethi_di_medany_text"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "text_segment_operand" "")))
 ;; ??? Why the clobber?
@@ -1626,7 +1629,7 @@
   [(set_attr "type" "move")
    (set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*sethi_di_fullany"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(high:DI (match_operand 1 "" "")))
    (clobber (reg:DI 1))]
@@ -1647,7 +1650,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movqi_insn"
   [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
 	(match_operand:QI 1 "move_operand" "rI,K,Q,rJ"))]
   "register_operand (operands[0], QImode)
@@ -1661,7 +1664,7 @@
   [(set_attr "type" "move,move,load,store")
    (set_attr "length" "*,1,*,1")])
 
-(define_insn ""
+(define_insn "*lo_sum_qi"
   [(set (match_operand:QI 0 "register_operand" "=r")
 	(subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
 			      (match_operand 2 "immediate_operand" "in")) 0))]
@@ -1669,7 +1672,7 @@
   "or %1,%%lo(%a2),%0"
   [(set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*store_qi"
   [(set (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
 	(match_operand:QI 1 "reg_or_0_operand" "rJ"))
    (clobber (match_scratch:SI 2 "=&r"))]
@@ -1688,7 +1691,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movhi_insn"
   [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
 	(match_operand:HI 1 "move_operand" "rI,K,Q,rJ"))]
   "register_operand (operands[0], HImode)
@@ -1702,7 +1705,7 @@
   [(set_attr "type" "move,move,load,store")
    (set_attr "length" "*,1,*,1")])
 
-(define_insn ""
+(define_insn "*lo_sum_hi"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(lo_sum:HI (match_operand:HI 1 "register_operand" "r")
 		   (match_operand 2 "immediate_operand" "in")))]
@@ -1710,7 +1713,7 @@
   "or %1,%%lo(%a2),%0"
   [(set_attr "length" "1")])
 
-(define_insn ""
+(define_insn "*store_hi"
   [(set (mem:HI (match_operand:SI 0 "symbolic_operand" ""))
 	(match_operand:HI 1 "reg_or_0_operand" "rJ"))
    (clobber (match_scratch:SI 2 "=&r"))]
@@ -1737,7 +1740,7 @@
 ;; problems with register allocation.  Reload might try to put an integer
 ;; in an fp register, or an fp number is an integer register.
 
-(define_insn ""
+(define_insn "*movsi_insn"
   [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,f,r,r,f,Q,Q")
 	(match_operand:SI 1 "move_operand" "rI,!f,K,Q,!Q,rJ,!f"))]
   "register_operand (operands[0], SImode)
@@ -1754,7 +1757,7 @@
   [(set_attr "type" "move,fp,move,load,load,store,store")
    (set_attr "length" "*,*,1,*,*,*,*")])
 
-(define_insn ""
+(define_insn "*store_si"
   [(set (mem:SI (match_operand:SI 0 "symbolic_operand" ""))
 	(match_operand:SI 1 "reg_or_0_operand" "rJ"))
    (clobber (match_scratch:SI 2 "=&r"))]
@@ -1773,7 +1776,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movdi_sp32_insn"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,T,U,Q,r,r,?f,?f,?Q")
 	(match_operand:DI 1 "general_operand" "r,U,T,r,Q,i,f,Q,f"))]
   "! TARGET_V9
@@ -1797,7 +1800,7 @@
 ;;; xor %o0, ((op1 & 0x3ff) | -0x400), %o0
 ;;; This needs the original value of operands[1], not the inverted value.
 
-(define_insn ""
+(define_insn "*movdi_sp64_insn"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q,?f,?f,?Q")
 	(match_operand:DI 1 "move_operand" "rI,K,Q,rJ,f,Q,f"))]
   "TARGET_V9
@@ -1880,7 +1883,7 @@
 ;  operands[2] = force_not_mem (operands[2]);
 ;}")
 
-;(define_insn ""
+;(define_insn "*block_move_insn"
 ;  [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r"))
 ;	(mem:BLK (match_operand:SI 1 "register_operand" "+r")))
 ;   (use (match_operand:SI 2 "nonmemory_operand" "rn"))
@@ -1900,9 +1903,9 @@
 ;; This pattern forces (set (reg:SF ...) (const_double ...))
 ;; to be reloaded by putting the constant into memory.
 ;; It must come before the more general movsf pattern.
-(define_insn ""
+(define_insn "*movsf_const_insn"
   [(set (match_operand:SF 0 "general_operand" "=?r,f,m")
-	(match_operand:SF 1 "" "?E,m,G"))]
+	(match_operand:SF 1 "" "?F,m,G"))]
   "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE"
   "*
 {
@@ -1929,7 +1932,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movsf_insn"
   [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=f,r,f,r,Q,Q")
 	(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "f,r,Q,Q,f,r"))]
   "TARGET_FPU
@@ -1948,7 +1951,7 @@
 ;; This is necessary to prevent reload from ever trying to use a `f' reg
 ;; when -mno-fpu.
 
-(define_insn ""
+(define_insn "*movsf_no_f_insn"
   [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
 	(match_operand:SF 1 "reg_or_nonsymb_mem_operand" "r,Q,r"))]
   "! TARGET_FPU
@@ -1960,7 +1963,7 @@
    st %r1,%0"
   [(set_attr "type" "move,load,store")])
 
-(define_insn ""
+(define_insn "*store_sf"
   [(set (mem:SF (match_operand:SI 0 "symbolic_operand" "i"))
 	(match_operand:SF 1 "reg_or_0_operand" "rfG"))
    (clobber (match_scratch:SI 2 "=&r"))]
@@ -1973,9 +1976,9 @@
 ;; to be reloaded by putting the constant into memory.
 ;; It must come before the more general movdf pattern.
 
-(define_insn ""
+(define_insn "*movdf_const_insn"
   [(set (match_operand:DF 0 "general_operand" "=?r,e,o")
-	(match_operand:DF 1 "" "?E,m,G"))]
+	(match_operand:DF 1 "" "?F,m,G"))]
   "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE"
   "*
 {
@@ -2010,7 +2013,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movdf_insn"
   [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,e,r,Q,Q,e,r")
 	(match_operand:DF 1 "reg_or_nonsymb_mem_operand" "U,T,e,r,e,r,Q,Q"))]
   "TARGET_FPU
@@ -2029,7 +2032,7 @@
 ;; This is necessary to prevent reload from ever trying to use a `e' reg
 ;; when -mno-fpu.
 
-(define_insn ""
+(define_insn "*movdf_no_e_insn"
   [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,r,Q,&r")
 	(match_operand:DF 1 "reg_or_nonsymb_mem_operand" "U,T,r,r,Q"))]
   "! TARGET_FPU
@@ -2069,7 +2072,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*store_df"
   [(set (mem:DF (match_operand:SI 0 "symbolic_operand" "i,i"))
 	(match_operand:DF 1 "reg_or_0_operand" "re,G"))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
@@ -2088,9 +2091,9 @@
 ;; This pattern forces (set (reg:TF ...) (const_double ...))
 ;; to be reloaded by putting the constant into memory.
 ;; It must come before the more general movtf pattern.
-(define_insn ""
+(define_insn "*movtf_const_insn"
   [(set (match_operand:TF 0 "general_operand" "=?r,e,o")
-	(match_operand:TF 1 "" "?E,m,G"))]
+	(match_operand:TF 1 "" "?F,m,G"))]
   "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE"
   "*
 {
@@ -2129,7 +2132,7 @@
     DONE;
 }")
 
-(define_insn ""
+(define_insn "*movtf_insn"
   [(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=e,r,Q,Q,e,&r")
 	(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "e,r,e,r,Q,Q"))]
   "TARGET_FPU
@@ -2148,7 +2151,7 @@
 ;; This is necessary to prevent reload from ever trying to use a `e' reg
 ;; when -mno-fpu.
 
-(define_insn ""
+(define_insn "*movtf_no_e_insn"
   [(set (match_operand:TF 0 "reg_or_nonsymb_mem_operand" "=r,Q,&r")
 	(match_operand:TF 1 "reg_or_nonsymb_mem_operand" "r,r,Q"))]
   "! TARGET_FPU
@@ -2166,7 +2169,7 @@
 ;; This is disabled because it does not work.  Long doubles have only 8
 ;; byte alignment.  Adding an offset of 8 or 12 to an 8 byte aligned %lo may 
 ;; cause it to overflow.  See also GO_IF_LEGITIMATE_ADDRESS.
-(define_insn ""
+(define_insn "*store_tf"
   [(set (mem:TF (match_operand:SI 0 "symbolic_operand" "i,i"))
 	(match_operand:TF 1 "reg_or_0_operand" "re,G"))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
@@ -2184,8 +2187,142 @@
 
 ;; Sparc V9 conditional move instructions.
 
-; ??? There is not actually a 32 bit version of this instruction.
-(define_insn ""
+;; We can handle larger constants here for some flavors, but for now we play
+;; it safe and only allow those constants supported by all flavours.
+
+(define_expand "movsicc"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:SI 2 "arith10_operand" "")
+		      (match_operand:SI 3 "register_operand" "")))]
+  "TARGET_V9"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+
+  if (sparc_compare_op1 == const0_rtx
+      && GET_CODE (sparc_compare_op0) == REG
+      && GET_MODE (sparc_compare_op0) == DImode
+      && v9_regcmp_p (code))
+    {
+      operands[1] = gen_rtx (code, DImode,
+			     sparc_compare_op0, sparc_compare_op1);
+    }
+  else
+    {
+      rtx cc_reg = gen_compare_reg (code,
+				    sparc_compare_op0, sparc_compare_op1);
+      operands[1] = gen_rtx (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+    }
+}")
+
+(define_expand "movdicc"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:DI 2 "arith10_operand" "")
+		      (match_operand:DI 3 "register_operand" "")))]
+  "TARGET_V9"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+
+  if (sparc_compare_op1 == const0_rtx
+      && GET_CODE (sparc_compare_op0) == REG
+      && GET_MODE (sparc_compare_op0) == DImode
+      && v9_regcmp_p (code))
+    {
+      operands[1] = gen_rtx (code, DImode,
+			     sparc_compare_op0, sparc_compare_op1);
+    }
+  else
+    {
+      rtx cc_reg = gen_compare_reg (code,
+				    sparc_compare_op0, sparc_compare_op1);
+      operands[1] = gen_rtx (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+    }
+}")
+
+(define_expand "movsfcc"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:SF 2 "register_operand" "")
+		      (match_operand:SF 3 "register_operand" "")))]
+  "TARGET_V9"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+
+  if (sparc_compare_op1 == const0_rtx
+      && GET_CODE (sparc_compare_op0) == REG
+      && GET_MODE (sparc_compare_op0) == DImode
+      && v9_regcmp_p (code))
+    {
+      operands[1] = gen_rtx (code, DImode,
+			     sparc_compare_op0, sparc_compare_op1);
+    }
+  else
+    {
+      rtx cc_reg = gen_compare_reg (code,
+				    sparc_compare_op0, sparc_compare_op1);
+      operands[1] = gen_rtx (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+    }
+}")
+
+(define_expand "movdfcc"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:DF 2 "register_operand" "")
+		      (match_operand:DF 3 "register_operand" "")))]
+  "TARGET_V9"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+
+  if (sparc_compare_op1 == const0_rtx
+      && GET_CODE (sparc_compare_op0) == REG
+      && GET_MODE (sparc_compare_op0) == DImode
+      && v9_regcmp_p (code))
+    {
+      operands[1] = gen_rtx (code, DImode,
+			     sparc_compare_op0, sparc_compare_op1);
+    }
+  else
+    {
+      rtx cc_reg = gen_compare_reg (code,
+				    sparc_compare_op0, sparc_compare_op1);
+      operands[1] = gen_rtx (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+    }
+}")
+
+(define_expand "movtfcc"
+  [(set (match_operand:TF 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:TF 2 "register_operand" "")
+		      (match_operand:TF 3 "register_operand" "")))]
+  "TARGET_V9"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+
+  if (sparc_compare_op1 == const0_rtx
+      && GET_CODE (sparc_compare_op0) == REG
+      && GET_MODE (sparc_compare_op0) == DImode
+      && v9_regcmp_p (code))
+    {
+      operands[1] = gen_rtx (code, DImode,
+			     sparc_compare_op0, sparc_compare_op1);
+    }
+  else
+    {
+      rtx cc_reg = gen_compare_reg (code,
+				    sparc_compare_op0, sparc_compare_op1);
+      operands[1] = gen_rtx (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+    }
+}")
+
+/* Conditional move define_insns.  */
+
+(define_insn "*movsi_cc_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CC 0) (const_int 0)])
@@ -2195,7 +2332,7 @@
   "mov%C1 %%icc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdi_cc_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CC 0) (const_int 0)])
@@ -2205,8 +2342,7 @@
   "mov%C1 %%icc,%2,%0"
   [(set_attr "type" "cmove")])
 
-;; ??? There is not actually a 32 bit version of this instruction.
-(define_insn ""
+(define_insn "*movsi_ccx_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CCX 0) (const_int 0)])
@@ -2216,7 +2352,7 @@
   "mov%C1 %%xcc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdi_ccx_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CCX 0) (const_int 0)])
@@ -2226,8 +2362,7 @@
   "mov%C1 %%xcc,%2,%0"
   [(set_attr "type" "cmove")])
 
-;; ??? There is not actually a 32 bit version of this instruction.
-(define_insn ""
+(define_insn "*movsi_ccfp_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFP 2 "ccfp_reg_operand" "c")
@@ -2238,8 +2373,7 @@
   "mov%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-;; ??? There is not actually a 32 bit version of this instruction.
-(define_insn ""
+(define_insn "*movsi_ccfpe_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFPE 2 "ccfp_reg_operand" "c")
@@ -2250,7 +2384,7 @@
   "mov%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdi_ccfp_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFP 2 "ccfp_reg_operand" "c")
@@ -2261,7 +2395,7 @@
   "mov%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdi_ccfpe_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFPE 2 "ccfp_reg_operand" "c")
@@ -2272,8 +2406,7 @@
   "mov%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-;; ??? There is not actually a 32 bit version of this instruction.
-(define_insn ""
+(define_insn "*movsi_cc_reg_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r")
@@ -2284,7 +2417,7 @@
   "movr%D1 %2,%r3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdi_cc_reg_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(if_then_else (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r")
@@ -2295,7 +2428,7 @@
   "movr%D1 %2,%r3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movsf_cc_reg_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(if_then_else (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r")
@@ -2306,7 +2439,7 @@
   "fmovrs%D1 %2,%r3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdf_cc_reg_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r")
@@ -2317,7 +2450,7 @@
   "fmovrd%D1 %2,%r3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movtf_cc_reg_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "v9_regcmp_op"
 				[(match_operand:DI 2 "register_operand" "r")
@@ -2328,7 +2461,7 @@
   "fmovrq%D1 %2,%r3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movsf_ccfp_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFP 2 "ccfp_reg_operand" "c")
@@ -2339,7 +2472,7 @@
   "fmovs%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movsf_ccfpe_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFPE 2 "ccfp_reg_operand" "c")
@@ -2350,7 +2483,7 @@
   "fmovs%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdf_ccfp_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFP 2 "ccfp_reg_operand" "c")
@@ -2361,7 +2494,7 @@
   "fmovd%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdf_ccfpe_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFPE 2 "ccfp_reg_operand" "c")
@@ -2372,7 +2505,7 @@
   "fmovd%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movtf_ccfp_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFP 2 "ccfp_reg_operand" "c")
@@ -2383,7 +2516,7 @@
   "fmovq%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movtf_ccfpe_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				[(match_operand:CCFPE 2 "ccfp_reg_operand" "c")
@@ -2394,7 +2527,7 @@
   "fmovq%C1 %2,%3,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movsf_cc_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CC 0) (const_int 0)])
@@ -2404,7 +2537,7 @@
   "fmovs%C1 %%icc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdf_cc_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CC 0) (const_int 0)])
@@ -2414,7 +2547,7 @@
   "fmovd%C1 %%icc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movtf_cc_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CC 0) (const_int 0)])
@@ -2424,7 +2557,7 @@
   "fmovq%C1 %%icc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movsf_ccx_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CCX 0) (const_int 0)])
@@ -2434,7 +2567,7 @@
   "fmovs%C1 %%xcc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movdf_ccx_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CCX 0) (const_int 0)])
@@ -2444,7 +2577,7 @@
   "fmovd%C1 %%xcc,%2,%0"
   [(set_attr "type" "cmove")])
 
-(define_insn ""
+(define_insn "*movtf_ccx_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(if_then_else (match_operator 1 "comparison_operator"
 				      [(reg:CCX 0) (const_int 0)])
@@ -2483,7 +2616,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*zero_extendhisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
   ""
@@ -2496,7 +2629,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*zero_extendqihi2_insn"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(zero_extend:HI (match_operand:QI 1 "sparc_operand" "r,Q")))]
   "GET_CODE (operands[1]) != CONST_INT"
@@ -2512,7 +2645,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*zero_extendqisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extend:SI (match_operand:QI 1 "sparc_operand" "r,Q")))]
   "GET_CODE (operands[1]) != CONST_INT"
@@ -2528,7 +2661,7 @@
   "TARGET_V9"
   "")
 
-(define_insn ""
+(define_insn "*zero_extendqidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (match_operand:QI 1 "sparc_operand" "r,Q")))]
   "TARGET_V9 && GET_CODE (operands[1]) != CONST_INT"
@@ -2561,7 +2694,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*zero_extendhidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_V9"
@@ -2576,7 +2709,7 @@
   "TARGET_V9"
   "")
 
-(define_insn ""
+(define_insn "*zero_extendsidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (match_operand:SI 1 "sparc_operand" "r,Q")))]
   "TARGET_V9 && GET_CODE (operands[1]) != CONST_INT"
@@ -2588,7 +2721,7 @@
 
 ;; Simplify comparisons of extended values.
 
-(define_insn ""
+(define_insn "*cmp_zero_extendqisi2"
   [(set (reg:CC 0)
 	(compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
 		    (const_int 0)))]
@@ -2596,7 +2729,7 @@
   "andcc %0,0xff,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_zero_extendqisi2_set"
   [(set (reg:CC 0)
 	(compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
 		    (const_int 0)))
@@ -2608,7 +2741,7 @@
 
 ;; Similarly, handle SI->QI mode truncation followed by a compare.
 
-(define_insn ""
+(define_insn "*cmp_siqi_trunc"
   [(set (reg:CC 0)
 	(compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0)
 		    (const_int 0)))]
@@ -2616,7 +2749,7 @@
   "andcc %0,0xff,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_siqi_trunc_set"
   [(set (reg:CC 0)
 	(compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0)
 		    (const_int 0)))
@@ -2655,7 +2788,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*sign_extendhisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
   ""
@@ -2692,7 +2825,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*sign_extendqihi2_insn"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
   ""
@@ -2722,7 +2855,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*sign_extendqisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
   ""
@@ -2752,7 +2885,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*sign_extendqidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
   "TARGET_V9"
@@ -2782,7 +2915,7 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*sign_extendhidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_V9"
@@ -2795,7 +2928,7 @@
   "TARGET_V9"
   "")
 
-(define_insn ""
+(define_insn "*sign_extendsidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(sign_extend:DI (match_operand:SI 1 "sparc_operand" "r,Q")))]
   "TARGET_V9"
@@ -2808,7 +2941,7 @@
 ;; Special pattern for optimizing bit-field compares.  This is needed
 ;; because combine uses this as a canonical form.
 
-(define_insn ""
+(define_insn "*cmp_zero_extract"
   [(set (reg:CC 0)
 	(compare:CC
 	 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
@@ -2826,7 +2959,7 @@
   return \"andcc %0,%1,%%g0\";
 }")
 
-(define_insn ""
+(define_insn "*cmp_zero_extract_sp64"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
@@ -2956,7 +3089,7 @@
   operands[3] = sparc64_fpconv_stack_temp ();
 }")
 
-(define_insn ""
+(define_insn "*floatdisf2_insn"
   [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
 		   (float:SF (match_operand:DI 1 "general_operand" "rm")))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -2973,7 +3106,7 @@
   [(set_attr "type" "fp")
    (set_attr "length" "3")])
 
-(define_insn ""
+(define_insn "*floatdidf2_insn"
   [(parallel [(set (match_operand:DF 0 "register_operand" "=e")
 		   (float:DF (match_operand:DI 1 "general_operand" "rm")))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -2990,7 +3123,7 @@
   [(set_attr "type" "fp")
    (set_attr "length" "3")])
 
-(define_insn ""
+(define_insn "*floatditf2_insn"
   [(parallel [(set (match_operand:TF 0 "register_operand" "=e")
 		   (float:TF (match_operand:DI 1 "general_operand" "rm")))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -3009,21 +3142,21 @@
 
 ;; ??? Ideally, these are what we would like to use.
 
-(define_insn "floatdisf2_v9"
+(define_insn "floatdisf2_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:DI 1 "register_operand" "e")))]
   "0 && TARGET_V9 && TARGET_FPU"
   "fxtos %1,%0"
   [(set_attr "type" "fp")])
 
-(define_insn "floatdidf2_v9"
+(define_insn "floatdidf2_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(float:DF (match_operand:DI 1 "register_operand" "e")))]
   "0 && TARGET_V9 && TARGET_FPU"
   "fxtod %1,%0"
   [(set_attr "type" "fp")])
 
-(define_insn "floatditf2_v9"
+(define_insn "floatditf2_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(float:TF (match_operand:DI 1 "register_operand" "e")))]
   "0 && TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
@@ -3098,7 +3231,7 @@
   operands[3] = sparc64_fpconv_stack_temp ();
 }")
 
-(define_insn ""
+(define_insn "*fix_truncsfdi2_insn"
   [(parallel [(set (match_operand:DI 0 "general_operand" "=rm")
 		   (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -3115,7 +3248,7 @@
   [(set_attr "type" "fp")
    (set_attr "length" "3")])
 
-(define_insn ""
+(define_insn "*fix_truncdfdi2_insn"
   [(parallel [(set (match_operand:DI 0 "general_operand" "=rm")
 		   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -3132,7 +3265,7 @@
   [(set_attr "type" "fp")
    (set_attr "length" "3")])
 
-(define_insn ""
+(define_insn "*fix_trunctfdi2_insn"
   [(parallel [(set (match_operand:DI 0 "general_operand" "=rm")
 		   (fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))
 	      (clobber (match_operand:DF 2 "register_operand" "=&e"))
@@ -3151,21 +3284,21 @@
 
 ;; ??? Ideally, these are what we would like to use.
 
-(define_insn "fix_truncsfdi2_v9"
+(define_insn "fix_truncsfdi2_sp64"
   [(set (match_operand:DI 0 "register_operand" "=e")
 	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
   "0 && TARGET_V9 && TARGET_FPU"
   "fstox %1,%0"
   [(set_attr "type" "fp")])
 
-(define_insn "fix_truncdfdi2_v9"
+(define_insn "fix_truncdfdi2_sp64"
   [(set (match_operand:DI 0 "register_operand" "=e")
 	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
   "0 && TARGET_V9 && TARGET_FPU"
   "fdtox %1,%0"
   [(set_attr "type" "fp")])
 
-(define_insn "fix_trunctfdi2_v9"
+(define_insn "fix_trunctfdi2_sp64"
   [(set (match_operand:DI 0 "register_operand" "=e")
 	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
   "0 && TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
@@ -3192,7 +3325,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*adddi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))
@@ -3228,7 +3361,7 @@
 }"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*adddi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3243,7 +3376,7 @@
   "add %1,%2,%0"
   [(set_attr "type" "ialu")])
 
-(define_insn ""
+(define_insn "*cmp_cc_plus"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
 				  (match_operand:SI 1 "arith_operand" "rI"))
@@ -3252,7 +3385,7 @@
   "addcc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_plus"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r")
 				   (match_operand:DI 1 "arith_double_operand" "rHI"))
@@ -3261,7 +3394,7 @@
   "addcc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_plus_set"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
 				  (match_operand:SI 2 "arith_operand" "rI"))
@@ -3271,7 +3404,7 @@
   ""
   "addcc %1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_ccx_plus_set"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 				   (match_operand:DI 2 "arith_double_operand" "rHI"))
@@ -3299,7 +3432,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*subdi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(minus:DI (match_operand:DI 1 "register_operand" "r")
 		  (match_operand:DI 2 "arith_double_operand" "rHI")))
@@ -3335,7 +3468,7 @@
 }"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*subdi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(minus:DI (match_operand:DI 1 "register_operand" "r")
 		  (match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3350,7 +3483,7 @@
   "sub %1,%2,%0"
   [(set_attr "type" "ialu")])
 
-(define_insn ""
+(define_insn "*cmp_minus_cc"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (minus:SI (match_operand:SI 0 "register_operand" "r")
 				   (match_operand:SI 1 "arith_operand" "rI"))
@@ -3359,7 +3492,7 @@
   "subcc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_minus_ccx"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
 				    (match_operand:DI 1 "arith_double_operand" "rHI"))
@@ -3368,7 +3501,7 @@
   "subcc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_minus_cc_set"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (minus:SI (match_operand:SI 1 "register_operand" "r")
 				   (match_operand:SI 2 "arith_operand" "rI"))
@@ -3378,7 +3511,7 @@
   ""
   "subcc %1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_minus_ccx_set"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
 				    (match_operand:DI 2 "arith_double_operand" "rHI"))
@@ -3408,7 +3541,7 @@
 
 ;; It is not known whether this will match.
 
-(define_insn ""
+(define_insn "*cmp_mul_set"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(mult:SI (match_operand:SI 1 "arith_operand" "%r")
 		 (match_operand:SI 2 "arith_operand" "rI")))
@@ -3433,7 +3566,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*mulsidi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
@@ -3441,7 +3574,7 @@
   "smul %1,%2,%R0\;rd %%y,%0"
   [(set_attr "length" "2")])
 
-;; Extra pattern, because sign_extend of a constant isn't legal.
+;; Extra pattern, because sign_extend of a constant isn't valid.
 
 (define_insn "const_mulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -3467,7 +3600,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*smulsidi3_highpart_sp32"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(truncate:SI
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
@@ -3501,7 +3634,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*umulsidi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
@@ -3509,7 +3642,7 @@
   "umul %1,%2,%R0\;rd %%y,%0"
   [(set_attr "length" "2")])
 
-;; Extra pattern, because sign_extend of a constant isn't legal.
+;; Extra pattern, because sign_extend of a constant isn't valid.
 
 (define_insn "const_umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -3535,7 +3668,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*umulsidi3_highpart_sp32"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(truncate:SI
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
@@ -3576,7 +3709,7 @@
 
 ;; It is not known whether this will match.
 
-(define_insn ""
+(define_insn "*cmp_sdiv_cc_set"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(div:SI (match_operand:SI 1 "register_operand" "r")
 		(match_operand:SI 2 "arith_operand" "rI")))
@@ -3605,7 +3738,7 @@
 
 ;; It is not known whether this will match.
 
-(define_insn ""
+(define_insn "*cmp_udiv_cc_set"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(udiv:SI (match_operand:SI 1 "register_operand" "r")
 		(match_operand:SI 2 "arith_operand" "rI")))
@@ -3627,7 +3760,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*anddi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3661,7 +3794,7 @@
 }"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*anddi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3691,7 +3824,7 @@
   operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
 }")
 
-(define_insn ""
+(define_insn "*and_not_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
 		(match_operand:DI 2 "register_operand" "r")))]
@@ -3699,14 +3832,14 @@
   "andn %2,%1,%0\;andn %R2,%R1,%R0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*and_not_di_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
 		(match_operand:DI 2 "register_operand" "r")))]
   "TARGET_V9"
   "andn %2,%1,%0")
 
-(define_insn ""
+(define_insn "*and_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
 		(match_operand:SI 2 "register_operand" "r")))]
@@ -3721,7 +3854,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*iordi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3755,7 +3888,7 @@
 }"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*iordi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3785,7 +3918,7 @@
   operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
 }")
 
-(define_insn ""
+(define_insn "*or_not_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
 		(match_operand:DI 2 "register_operand" "r")))]
@@ -3793,14 +3926,14 @@
   "orn %2,%1,%0\;orn %R2,%R1,%R0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*or_not_di_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
 		(match_operand:DI 2 "register_operand" "r")))]
   "TARGET_V9"
   "orn %2,%1,%0")
 
-(define_insn ""
+(define_insn "*or_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
 		(match_operand:SI 2 "register_operand" "r")))]
@@ -3815,7 +3948,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*xorsi3_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(xor:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3849,7 +3982,7 @@
 }"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*xordi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
@@ -3896,7 +4029,7 @@
 
 ;; xnor patterns.  Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
 ;; Combine now canonicalizes to the rightmost expression.
-(define_insn ""
+(define_insn "*xor_not_di_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(not:DI (xor:DI (match_operand:DI 1 "register_operand" "r")
 			(match_operand:DI 2 "register_operand" "r"))))]
@@ -3904,14 +4037,14 @@
   "xnor %1,%2,%0\;xnor %R1,%R2,%R0"
   [(set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*xor_not_di_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 			(match_operand:DI 2 "arith_double_operand" "rHI"))))]
   "TARGET_V9"
   "xnor %r1,%2,%0")
 
-(define_insn ""
+(define_insn "*xor_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
 			(match_operand:SI 2 "arith_operand" "rI"))))]
@@ -3922,7 +4055,7 @@
 ;; These correspond to the above in the case where we also (or only)
 ;; want to set the condition code.  
 
-(define_insn ""
+(define_insn "*cmp_cc_arith_op"
   [(set (reg:CC 0)
 	(compare:CC
 	 (match_operator:SI 2 "cc_arithop"
@@ -3933,7 +4066,7 @@
   "%A2cc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_arith_op"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (match_operator:DI 2 "cc_arithop"
@@ -3944,7 +4077,7 @@
   "%A2cc %0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_arith_op_set"
   [(set (reg:CC 0)
 	(compare:CC
 	 (match_operator:SI 3 "cc_arithop"
@@ -3956,7 +4089,7 @@
   ""
   "%A3cc %1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_ccx_arith_op_set"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (match_operator:DI 3 "cc_arithop"
@@ -3968,7 +4101,7 @@
   "TARGET_V9"
   "%A3cc %1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_cc_xor_not"
   [(set (reg:CC 0)
 	(compare:CC
 	 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
@@ -3978,7 +4111,7 @@
   "xnorcc %r0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_xor_not"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ")
@@ -3988,7 +4121,7 @@
   "xnorcc %r0,%1,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_xor_not_set"
   [(set (reg:CC 0)
 	(compare:CC
 	 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
@@ -3999,7 +4132,7 @@
   ""
   "xnorcc %r1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_ccx_xor_not_set"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
@@ -4010,7 +4143,7 @@
   "TARGET_V9"
   "xnorcc %r1,%2,%0")
 
-(define_insn ""
+(define_insn "*cmp_cc_arith_op_not"
   [(set (reg:CC 0)
 	(compare:CC
 	 (match_operator:SI 2 "cc_arithopn"
@@ -4021,7 +4154,7 @@
   "%B2cc %r1,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_arith_op_not"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (match_operator:DI 2 "cc_arithopn"
@@ -4032,7 +4165,7 @@
   "%B2cc %r1,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_arith_op_not_set"
   [(set (reg:CC 0)
 	(compare:CC
 	 (match_operator:SI 3 "cc_arithopn"
@@ -4044,7 +4177,7 @@
   ""
   "%B3cc %r2,%1,%0")
 
-(define_insn ""
+(define_insn "*cmp_ccx_arith_op_not_set"
   [(set (reg:CCX 0)
 	(compare:CCX
 	 (match_operator:DI 3 "cc_arithopn"
@@ -4075,7 +4208,7 @@
     }
 }")
 
-(define_insn ""
+(define_insn "*negdi2_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))
    (clobber (reg:SI 0))]
@@ -4084,7 +4217,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*negdi2_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
   "TARGET_V9"
@@ -4099,7 +4232,7 @@
   "sub %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*cmp_cc_neg"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
 			 (const_int 0)))]
@@ -4107,7 +4240,7 @@
   "subcc %%g0,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_neg"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
 			  (const_int 0)))]
@@ -4115,7 +4248,7 @@
   "subcc %%g0,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_set_neg"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
 			 (const_int 0)))
@@ -4125,7 +4258,7 @@
   "subcc %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_set_neg"
   [(set (reg:CCX_NOOV 0)
 	(compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
 			  (const_int 0)))
@@ -4143,7 +4276,7 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*one_cmpldi2_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(not:DI (match_operand:DI 1 "register_operand" "r")))]
   "! TARGET_V9"
@@ -4151,7 +4284,7 @@
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
 
-(define_insn ""
+(define_insn "*one_cmpldi2_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")))]
   "TARGET_V9"
@@ -4165,7 +4298,7 @@
   "xnor %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*cmp_cc_not"
   [(set (reg:CC 0)
 	(compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
 		    (const_int 0)))]
@@ -4173,7 +4306,7 @@
   "xnorcc %%g0,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_not"
   [(set (reg:CCX 0)
 	(compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
 		     (const_int 0)))]
@@ -4181,7 +4314,7 @@
   "xnorcc %%g0,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_set_not"
   [(set (reg:CC 0)
 	(compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
 		    (const_int 0)))
@@ -4191,7 +4324,7 @@
   "xnorcc %%g0,%1,%0"
   [(set_attr "type" "unary")])
 
-(define_insn ""
+(define_insn "*cmp_ccx_set_not"
   [(set (reg:CCX 0)
 	(compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
 		    (const_int 0)))
@@ -4275,7 +4408,7 @@
   "fmuls %1,%2,%0"
   [(set_attr "type" "fpmul")])
 
-(define_insn ""
+(define_insn "*muldf3_extend"
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
 		 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
@@ -4283,7 +4416,7 @@
   "fsmuld %1,%2,%0"
   [(set_attr "type" "fpmul")])
 
-(define_insn ""
+(define_insn "*multf3_extend"
   [(set (match_operand:TF 0 "register_operand" "=e")
 	(mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
 		 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
@@ -4454,7 +4587,7 @@
   return \"sllx %1,%2,%0\";
 }")
 
-(define_insn ""
+(define_insn "*cmp_cc_ashift_1"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
 				    (const_int 1))
@@ -4463,7 +4596,7 @@
   "addcc %0,%0,%%g0"
   [(set_attr "type" "compare")])
 
-(define_insn ""
+(define_insn "*cmp_cc_set_ashift_1"
   [(set (reg:CC_NOOV 0)
 	(compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
 				    (const_int 1))
@@ -4544,7 +4677,7 @@
 (define_expand "tablejump"
   [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
 	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
+  "! TARGET_MEDANY"
   "
 {
   if (GET_MODE (operands[0]) != Pmode)
@@ -4578,38 +4711,72 @@
   "jmp %%o7+%0%#"
   [(set_attr "type" "uncond_branch")])
 
-(define_insn ""
+(define_insn "*tablejump_sp32"
   [(set (pc) (match_operand:SI 0 "address_operand" "p"))
    (use (label_ref (match_operand 1 "" "")))]
   "! TARGET_PTR64"
   "jmp %a0%#"
   [(set_attr "type" "uncond_branch")])
 
-(define_insn ""
+(define_insn "*tablejump_sp64"
   [(set (pc) (match_operand:DI 0 "address_operand" "p"))
    (use (label_ref (match_operand 1 "" "")))]
   "TARGET_PTR64"
   "jmp %a0%#"
   [(set_attr "type" "uncond_branch")])
 
-(define_insn ""
+(define_insn "*get_pc_sp32"
   [(set (pc) (label_ref (match_operand 0 "" "")))
    (set (reg:SI 15) (label_ref (match_dup 0)))]
   "! TARGET_PTR64"
   "call %l0%#"
   [(set_attr "type" "uncond_branch")])
 
-(define_insn ""
+(define_insn "*get_pc_sp64"
   [(set (pc) (label_ref (match_operand 0 "" "")))
    (set (reg:DI 15) (label_ref (match_dup 0)))]
   "TARGET_PTR64"
   "call %l0%#"
   [(set_attr "type" "uncond_branch")])
 
+;; Implement a switch statement for the medium/anywhere code model.
+;; This wouldn't be necessary if we could distinguish label refs of the jump
+;; table from other label refs.  The problem is that jump tables live in the
+;; .rodata section and thus we need to add %g4 to get their address.
+
+(define_expand "casesi"
+  [(set (match_dup 5)
+	(minus:SI (match_operand:SI 0 "register_operand" "")
+		  (match_operand:SI 1 "nonmemory_operand" "")))
+   (set (reg:CC 0)
+	(compare:CC (match_dup 5)
+		    (match_operand:SI 2 "nonmemory_operand" "")))
+   (set (pc)
+	(if_then_else (gtu (reg:CC 0)
+			   (const_int 0))
+		      (label_ref (match_operand 4 "" ""))
+		      (pc)))
+   (parallel [(set (match_dup 6) (high:DI (label_ref (match_operand 3 "" ""))))
+	      (clobber (reg:DI 1))])
+   (set (match_dup 6)
+	(lo_sum:DI (match_dup 6) (label_ref (match_dup 3))))
+   (set (match_dup 6) (plus:DI (match_dup 6) (reg:DI 4)))
+   (set (match_dup 7) (zero_extend:DI (match_dup 5)))
+   (set (match_dup 7) (ashift:DI (match_dup 7) (const_int 3)))
+   (set (match_dup 7) (mem:DI (plus:DI (match_dup 6) (match_dup 7))))
+   (set (pc) (match_dup 7))]
+  "TARGET_MEDANY"
+  "
+{
+  operands[5] = gen_reg_rtx (SImode);
+  operands[6] = gen_reg_rtx (DImode);
+  operands[7] = gen_reg_rtx (DImode);
+}")
+
 ;; This pattern recognizes the "instruction" that appears in 
 ;; a function call that wants a structure value, 
 ;; to inform the called function if compiled with Sun CC.
-;(define_insn ""
+;(define_insn "*unimp_insn"
 ;  [(match_operand:SI 0 "immediate_operand" "")]
 ;  "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0"
 ;  "unimp %0"
@@ -4699,111 +4866,87 @@
 ;; We can't use the same pattern for these two insns, because then registers
 ;; in the address may not be properly reloaded.
 
-(define_insn ""
+(define_insn "*call_address_sp32"
   [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
 	 (match_operand 1 "" ""))
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_PTR64"
-  "*
-{
-  return \"call %a0,%1%#\";
-}"
+  "call %a0,%1%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_symbolic_sp32"
   [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
 	 (match_operand 1 "" ""))
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_PTR64"
-  "*
-{
-  return \"call %a0,%1%#\";
-}"
+  "call %a0,%1%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_address_sp64"
   [(call (mem:SI (match_operand:DI 0 "address_operand" "p"))
 	 (match_operand 1 "" ""))
    (clobber (reg:DI 15))]
   ;;- Do not use operand 1 for most machines.
   "TARGET_PTR64"
-  "*
-{
-  return \"call %a0,%1%#\";
-}"
+  "call %a0,%1%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_symbolic_sp64"
   [(call (mem:SI (match_operand:DI 0 "symbolic_operand" "s"))
 	 (match_operand 1 "" ""))
    (clobber (reg:DI 15))]
   ;;- Do not use operand 1 for most machines.
   "TARGET_PTR64"
-  "*
-{
-  return \"call %a0,%1%#\";
-}"
+  "call %a0,%1%#"
   [(set_attr "type" "call")])
 
 ;; This is a call that wants a structure value.
 ;; There is no such critter for v9 (??? we may need one anyway).
-(define_insn ""
+(define_insn "*call_address_struct_value_sp32"
   [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
 	 (match_operand 1 "" ""))
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_V9 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
-  "*
-{
-  return \"call %a0,%1\;nop\;unimp %2\";
-}"
+  "call %a0,%1\;nop\;unimp %2"
   [(set_attr "type" "call_no_delay_slot")])
 
 ;; This is a call that wants a structure value.
 ;; There is no such critter for v9 (??? we may need one anyway).
-(define_insn ""
+(define_insn "*call_symbolic_struct_value_sp32"
   [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
 	 (match_operand 1 "" ""))
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_V9 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
-  "*
-{
-  return \"call %a0,%1\;nop\;unimp %2\";
-}"
+  "call %a0,%1\;nop\;unimp %2"
   [(set_attr "type" "call_no_delay_slot")])
 
 ;; This is a call that may want a structure value.  This is used for
 ;; untyped_calls.
-(define_insn ""
+(define_insn "*call_address_untyped_struct_value_sp32"
   [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
 	 (match_operand 1 "" ""))
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_V9 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
-  "*
-{
-  return \"call %a0,%1\;nop\;nop\";
-}"
+  "call %a0,%1\;nop\;nop"
   [(set_attr "type" "call_no_delay_slot")])
 
 ;; This is a call that wants a structure value.
-(define_insn ""
+(define_insn "*call_symbolic_untyped_struct_value_sp32"
   [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
 	 (match_operand 1 "" ""))
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI 15))]
   ;;- Do not use operand 1 for most machines.
   "! TARGET_V9 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
-  "*
-{
-  return \"call %a0,%1\;nop\;nop\";
-}"
+  "call %a0,%1\;nop\;nop"
   [(set_attr "type" "call_no_delay_slot")])
 
 (define_expand "call_value"
@@ -4844,56 +4987,44 @@
   DONE;
 }")
 
-(define_insn ""
+(define_insn "*call_value_address_sp32"
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:SI 1 "address_operand" "p"))
 	      (match_operand 2 "" "")))
    (clobber (reg:SI 15))]
   ;;- Do not use operand 2 for most machines.
   "! TARGET_PTR64"
-  "*
-{
-  return \"call %a1,%2%#\";
-}"
+  "call %a1,%2%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_value_symbolic_sp32"
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
 	      (match_operand 2 "" "")))
    (clobber (reg:SI 15))]
   ;;- Do not use operand 2 for most machines.
   "! TARGET_PTR64"
-  "*
-{
-  return \"call %a1,%2%#\";
-}"
+  "call %a1,%2%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_value_address_sp64"
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:DI 1 "address_operand" "p"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 15))]
   ;;- Do not use operand 2 for most machines.
   "TARGET_PTR64"
-  "*
-{
-  return \"call %a1,%2%#\";
-}"
+  "call %a1,%2%#"
   [(set_attr "type" "call")])
 
-(define_insn ""
+(define_insn "*call_value_symbolic_sp64"
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:DI 1 "symbolic_operand" "s"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 15))]
   ;;- Do not use operand 2 for most machines.
   "TARGET_PTR64"
-  "*
-{
-  return \"call %a1,%2%#\";
-}"
+  "call %a1,%2%#"
   [(set_attr "type" "call")])
 
 (define_expand "untyped_call"
@@ -5001,19 +5132,19 @@
   ""
   "")
 
-(define_insn ""
+(define_insn "*branch_sp32"
   [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
   "! TARGET_PTR64"
  "jmp %a0%#"
  [(set_attr "type" "uncond_branch")])
  
-(define_insn ""
+(define_insn "*branch_sp64"
   [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
   "TARGET_PTR64"
   "jmp %a0%#"
   [(set_attr "type" "uncond_branch")])
 
-;; ??? This doesn't handle v9 yet.  It also doesn't work with -mflat.
+;; ??? Doesn't work with -mflat.
 (define_expand "nonlocal_goto"
   [(match_operand:SI 0 "general_operand" "")
    (match_operand:SI 1 "general_operand" "")
@@ -5030,11 +5161,11 @@
      register.  Thus we must copy operands[0] into a register if it isn't
      already one.  */
   if (GET_CODE (operands[0]) != REG)
-    operands[0] = force_reg (SImode, operands[0]);
+    operands[0] = force_reg (Pmode, operands[0]);
   emit_move_insn (virtual_stack_vars_rtx, operands[0]);
   /* Find the containing function's current nonlocal goto handler,
      which will do any cleanups and then jump to the label.  */
-  emit_move_insn (gen_rtx (REG, SImode, 8), operands[1]);
+  emit_move_insn (gen_rtx (REG, Pmode, 8), operands[1]);
   /* Restore %fp from stack pointer value for containing function.
      The restore insn that follows will move this to %sp,
      and reload the appropriate value into %fp.  */
@@ -5046,7 +5177,7 @@
   emit_insn (gen_rtx (USE, VOIDmode, frame_pointer_rtx));
   emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
   emit_insn (gen_rtx (USE, VOIDmode, static_chain_rtx));
-  emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, 8)));
+  emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 8)));
   /* Return, restoring reg window and jumping to goto handler.  */
   emit_insn (gen_goto_handler_and_restore ());
   DONE;
@@ -5069,9 +5200,9 @@
 ;; Special pattern for the FLUSH instruction.
 
 (define_insn "flush"
-  [(unspec_volatile [(match_operand 0 "" "")] 3)]
+  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 3)]
   ""
-  "* return TARGET_V9 ? \"flush %a0\" : \"iflush %a0\";"
+  "* return TARGET_V9 ? \"flush %f0\" : \"iflush %f0\";"
   [(set_attr "type" "misc")])
 
 ;; find first set.
@@ -5079,7 +5210,7 @@
 ;; The scan instruction searches from the most significant bit while ffs
 ;; searches from the least significant bit.  The bit index and treatment of
 ;; zero also differ.  It takes at least 7 instructions to get the proper
-;; result.  Here is an obvious 8 instruction seequence.
+;; result.  Here is an obvious 8 instruction sequence.
 
 (define_insn "ffssi2"
   [(set (match_operand:SI 0 "register_operand" "=&r")
@@ -5108,56 +5239,71 @@
 ;; either before or after register allocation.
 
 (define_split
-  [(set (match_operator 0 "memop" [(match_operand:SI 1 "symbolic_operand" "")])
-	(match_operand 2 "reg_or_0_operand" ""))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+  [(set (match_operand 0 "splittable_symbolic_memory_operand" "")
+	(match_operand 1 "reg_or_0_operand" ""))
+   (clobber (match_operand:SI 2 "register_operand" ""))]
   "! flag_pic"
-  [(set (match_dup 3) (high:SI (match_dup 1)))
-   (set (match_op_dup 0 [(lo_sum:SI (match_dup 3) (match_dup 1))])
-	(match_dup 2))]
-  "")
+  [(set (match_dup 2) (high:SI (match_dup 3)))
+   (set (match_dup 4) (match_dup 1))]
+  "
+{
+  operands[3] = XEXP (operands[0], 0);
+  operands[4] = gen_rtx (MEM, GET_MODE (operands[0]),
+			 gen_rtx (LO_SUM, SImode, operands[2], operands[3]));
+  MEM_IN_STRUCT_P (operands[4]) = MEM_IN_STRUCT_P (operands[0]);
+  MEM_VOLATILE_P (operands[4]) = MEM_VOLATILE_P (operands[0]);
+  RTX_UNCHANGING_P (operands[4]) = RTX_UNCHANGING_P (operands[0]);
+}")
 
 (define_split
-  [(set (match_operator 0 "memop"
-			[(match_operand:SI 1 "immediate_operand" "")])
-	(match_operand 2 "general_operand" ""))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+  [(set (match_operand 0 "splittable_immediate_memory_operand" "")
+	(match_operand 1 "general_operand" ""))
+   (clobber (match_operand:SI 2 "register_operand" ""))]
   "flag_pic"
-  [(set (match_op_dup 0 [(match_dup 1)])
-	(match_dup 2))]
+  [(set (match_dup 3) (match_dup 1))]
   "
 {
-  operands[1] = legitimize_pic_address (operands[1], GET_MODE (operands[0]),
-					operands[3]);
+  rtx addr = legitimize_pic_address (XEXP (operands[0], 0),
+				     GET_MODE (operands[0]),
+				     operands[2]);
+  operands[3] = gen_rtx (MEM, GET_MODE (operands[0]), addr);
+  MEM_IN_STRUCT_P (operands[3]) = MEM_IN_STRUCT_P (operands[0]);
+  MEM_VOLATILE_P (operands[3]) = MEM_VOLATILE_P (operands[0]);
+  RTX_UNCHANGING_P (operands[3]) = RTX_UNCHANGING_P (operands[0]);
 }")
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
-	(match_operator 1 "memop"
-			[(match_operand:SI 2 "immediate_operand" "")]))]
+	(match_operand 1 "splittable_immediate_memory_operand" ""))]
   "flag_pic"
-  [(set (match_dup 0)
-	(match_op_dup 1 [(match_dup 2)]))]
+  [(set (match_dup 0) (match_dup 2))]
   "
 {
-  operands[2] = legitimize_pic_address (operands[2], GET_MODE (operands[1]),
-					operands[0]);
+  rtx addr = legitimize_pic_address (XEXP (operands[1], 0),
+				     GET_MODE (operands[1]),
+				     operands[0]);
+  operands[2] = gen_rtx (MEM, GET_MODE (operands[1]), addr);
+  MEM_IN_STRUCT_P (operands[2]) = MEM_IN_STRUCT_P (operands[1]);
+  MEM_VOLATILE_P (operands[2]) = MEM_VOLATILE_P (operands[1]);
+  RTX_UNCHANGING_P (operands[2]) = RTX_UNCHANGING_P (operands[1]);
 }")
 
 ;; Sign- and Zero-extend operations can have symbolic memory operands.
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
-	(match_operator 1 "extend_op"
-			[(match_operator 2 "memop"
-					 [(match_operand:SI 3 "immediate_operand" "")])]))]
+	(match_operator 1 "extend_op" [(match_operand 2 "splittable_immediate_memory_operand" "")]))]
   "flag_pic"
-  [(set (match_dup 0)
-	(match_op_dup 1 [(match_op_dup 2 [(match_dup 3)])]))]
+  [(set (match_dup 0) (match_op_dup 1 [(match_dup 3)]))]
   "
 {
-  operands[3] = legitimize_pic_address (operands[3], GET_MODE (operands[2]),
-					operands[0]);
+  rtx addr = legitimize_pic_address (XEXP (operands[2], 0),
+				     GET_MODE (operands[2]),
+				     operands[0]);
+  operands[3] = gen_rtx (MEM, GET_MODE (operands[2]), addr);
+  MEM_IN_STRUCT_P (operands[3]) = MEM_IN_STRUCT_P (operands[2]);
+  MEM_VOLATILE_P (operands[3]) = MEM_VOLATILE_P (operands[2]);
+  RTX_UNCHANGING_P (operands[3]) = RTX_UNCHANGING_P (operands[2]);
 }")
 
 (define_split
@@ -5455,34 +5601,6 @@
   "TARGET_V9"
   "ldsb %1,%0\;orcc %0,%%g0,%2")
 
-(define_peephole
-  [(set (match_operand:HI 0 "register_operand" "")
-	(match_operand:HI 1 "memory_operand" ""))
-   (set (match_operand:SI 2 "register_operand" "")
-	(sign_extend:SI (match_dup 0)))]
-  "dead_or_set_p (insn, operands[0])"
-  "*
-{
-  warning (\"bad peephole\");
-  if (! MEM_VOLATILE_P (operands[1]))
-    abort ();
-  return \"ldsh %1,%2\";
-}")
-
-(define_peephole
-  [(set (match_operand:QI 0 "register_operand" "")
-	(match_operand:QI 1 "memory_operand" ""))
-   (set (match_operand:SI 2 "register_operand" "")
-	(sign_extend:SI (match_dup 0)))]
-  "dead_or_set_p (insn, operands[0])"
-  "*
-{
-  warning (\"bad peephole\");
-  if (! MEM_VOLATILE_P (operands[1]))
-    abort ();
-  return \"ldsb %1,%2\";
-}")
-
 ;; Floating-point move peepholes
 ;; ??? v9: Do we want similar ones?
 
@@ -5517,7 +5635,7 @@
 ;; ??? There are QImode, HImode, and SImode versions of this pattern.
 ;; It might be possible to write one more general pattern instead of three.
 
-(define_insn ""
+(define_insn "*return_qi"
   [(set (match_operand:QI 0 "restore_operand" "")
 	(match_operand:QI 1 "arith_operand" "rI"))
    (return)]
@@ -5531,7 +5649,7 @@
 }"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*return_hi"
   [(set (match_operand:HI 0 "restore_operand" "")
 	(match_operand:HI 1 "arith_operand" "rI"))
    (return)]
@@ -5545,7 +5663,7 @@
 }"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*return_si"
   [(set (match_operand:SI 0 "restore_operand" "")
 	(match_operand:SI 1 "arith_operand" "rI"))
    (return)]
@@ -5562,7 +5680,7 @@
 ;; The following pattern is only generated by delayed-branch scheduling,
 ;; when the insn winds up in the epilogue.  This can only happen when
 ;; ! TARGET_FPU because otherwise fp return values are in %f0.
-(define_insn ""
+(define_insn "*return_sf_no_fpu"
   [(set (match_operand:SF 0 "restore_operand" "r")
 	(match_operand:SF 1 "register_operand" "r"))
    (return)]
@@ -5576,7 +5694,7 @@
 }"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*return_addsi"
   [(set (match_operand:SI 0 "restore_operand" "")
 	(plus:SI (match_operand:SI 1 "arith_operand" "%r")
 		 (match_operand:SI 2 "arith_operand" "rI")))
@@ -5591,7 +5709,7 @@
 }"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*return_di"
   [(set (match_operand:DI 0 "restore_operand" "")
 	(match_operand:DI 1 "arith_double_operand" "rHI"))
    (return)]
@@ -5599,7 +5717,7 @@
   "ret\;restore %%g0,%1,%Y0"
   [(set_attr "type" "multi")])
 
-(define_insn ""
+(define_insn "*return_adddi"
   [(set (match_operand:DI 0 "restore_operand" "")
 	(plus:DI (match_operand:DI 1 "arith_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))
@@ -5611,7 +5729,7 @@
 ;; Turned off because it should never match (subtracting a constant
 ;; is turned into addition) and because it would do the wrong thing
 ;; when operand 2 is -4096 (--4096 == 4096 is not a valid immediate).
-;;(define_insn ""
+;;(define_insn "*minus_const"
 ;;  [(set (match_operand:SI 0 "restore_operand" "")
 ;;	(minus:SI (match_operand:SI 1 "register_operand" "r")
 ;;		  (match_operand:SI 2 "small_int" "I")))
@@ -5622,7 +5740,7 @@
 
 ;; The following pattern is only generated by delayed-branch scheduling,
 ;; when the insn winds up in the epilogue.
-(define_insn ""
+(define_insn "*return_sf"
   [(set (reg:SF 32)
 	(match_operand:SF 0 "register_operand" "f"))
    (return)]
@@ -5639,10 +5757,7 @@
 	      (clobber (reg:SI 15))])
    (set (pc) (label_ref (match_operand 3 "" "")))]
   "short_branch (INSN_UID (insn), INSN_UID (operands[3]))"
-  "*
-{
-  return \"call %a1,%2\;add %%o7,(%l3-.-4),%%o7\";
-}")
+  "call %a1,%2\;add %%o7,(%l3-.-4),%%o7")
 
 (define_peephole
   [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps"))
@@ -5662,10 +5777,7 @@
 	      (clobber (reg:DI 15))])
    (set (pc) (label_ref (match_operand 3 "" "")))]
   "TARGET_V9 && short_branch (INSN_UID (insn), INSN_UID (operands[3]))"
-  "*
-{
-  return \"call %a1,%2\;add %%o7,(%l3-.-4),%%o7\";
-}")
+  "call %a1,%2\;add %%o7,(%l3-.-4),%%o7")
 
 (define_peephole
   [(parallel [(call (mem:SI (match_operand:DI 0 "call_operand_address" "ps"))
@@ -5673,10 +5785,7 @@
 	      (clobber (reg:DI 15))])
    (set (pc) (label_ref (match_operand 2 "" "")))]
   "TARGET_V9 && short_branch (INSN_UID (insn), INSN_UID (operands[2]))"
-  "*
-{
-  return \"call %a0,%1\;add %%o7,(%l2-.-4),%%o7\";
-}")
+  "call %a0,%1\;add %%o7,(%l2-.-4),%%o7")
 
 ;; Other miscellaneous peepholes.