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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- Tahoe version ! 3: ;; Copyright (C) 1989 Free Software Foundation, Inc. ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 2, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ! 22: ; File: tahoe.md ! 23: ; ! 24: ; Original port made at the University of Buffalo by Devon Bowen, ! 25: ; Dale Wiles and Kevin Zachmann. ! 26: ; ! 27: ; Piet van Oostrum ([email protected]) made adaptions for HCX/UX, fixed ! 28: ; some bugs and made some improvements (hopefully). ! 29: ; ! 30: ; Mail bugs reports or fixes to: [email protected] ! 31: ! 32: ! 33: ; movdi must call the output_move_double routine to move it around since ! 34: ; the tahoe doesn't efficiently support 8 bit moves. ! 35: ! 36: (define_insn "movdi" ! 37: [(set (match_operand:DI 0 "general_operand" "=g") ! 38: (match_operand:DI 1 "general_operand" "g"))] ! 39: "" ! 40: "* ! 41: { ! 42: CC_STATUS_INIT; ! 43: return output_move_double (operands); ! 44: }") ! 45: ! 46: ! 47: ; the trick in the movsi is accessing the contents of the sp register. The ! 48: ; tahoe doesn't allow you to access it directly so you have to access the ! 49: ; address of the top of the stack instead. ! 50: ! 51: (define_insn "movsi" ! 52: [(set (match_operand:SI 0 "general_operand" "=g") ! 53: (match_operand:SI 1 "general_operand" "g"))] ! 54: "" ! 55: "* ! 56: { ! 57: rtx link; ! 58: if (operands[1] == const1_rtx ! 59: && (link = find_reg_note (insn, REG_WAS_0, 0)) ! 60: && ! XEXP (link, 0)->volatil ! 61: && GET_CODE (XEXP (link, 0)) != NOTE ! 62: && no_labels_between_p (XEXP (link, 0), insn)) ! 63: return \"incl %0\"; ! 64: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) ! 65: { ! 66: if (push_operand (operands[0], SImode)) ! 67: return \"pushab %a1\"; ! 68: return \"movab %a1,%0\"; ! 69: } ! 70: if (operands[1] == const0_rtx) ! 71: return \"clrl %0\"; ! 72: if (push_operand (operands[0], SImode)) ! 73: return \"pushl %1\"; ! 74: if (GET_CODE(operands[1]) == REG && REGNO(operands[1]) == 14) ! 75: return \"moval (sp),%0\"; ! 76: return \"movl %1,%0\"; ! 77: }") ! 78: ! 79: ! 80: (define_insn "movhi" ! 81: [(set (match_operand:HI 0 "general_operand" "=g") ! 82: (match_operand:HI 1 "general_operand" "g"))] ! 83: "" ! 84: "* ! 85: { ! 86: rtx link; ! 87: if (operands[1] == const1_rtx ! 88: && (link = find_reg_note (insn, REG_WAS_0, 0)) ! 89: && ! XEXP (link, 0)->volatil ! 90: && GET_CODE (XEXP (link, 0)) != NOTE ! 91: && no_labels_between_p (XEXP (link, 0), insn)) ! 92: return \"incw %0\"; ! 93: if (operands[1] == const0_rtx) ! 94: return \"clrw %0\"; ! 95: return \"movw %1,%0\"; ! 96: }") ! 97: ! 98: ! 99: (define_insn "movqi" ! 100: [(set (match_operand:QI 0 "general_operand" "=g") ! 101: (match_operand:QI 1 "general_operand" "g"))] ! 102: "" ! 103: "* ! 104: { ! 105: if (operands[1] == const0_rtx) ! 106: return \"clrb %0\"; ! 107: return \"movb %1,%0\"; ! 108: }") ! 109: ! 110: ! 111: ; movsf has three cases since they can move from one place to another ! 112: ; or to/from the fpp and since different instructions are needed for ! 113: ; each case. The fpp related instructions don't set the flags properly. ! 114: ! 115: (define_insn "movsf" ! 116: [(set (match_operand:SF 0 "general_operand" "=g,=a,=g") ! 117: (match_operand:SF 1 "general_operand" "g,g,a"))] ! 118: "" ! 119: "* ! 120: { ! 121: CC_STATUS_INIT; ! 122: switch (which_alternative) ! 123: { ! 124: case 0: return \"movl %1,%0\"; ! 125: case 1: return \"ldf %1\"; ! 126: case 2: return \"stf %0\"; ! 127: } ! 128: }") ! 129: ! 130: ! 131: ; movdf has a number of different cases. If it's going to or from ! 132: ; the fpp, use the special instructions to do it. If not, use the ! 133: ; output_move_double function. ! 134: ! 135: (define_insn "movdf" ! 136: [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g") ! 137: (match_operand:DF 1 "general_operand" "g,a,g"))] ! 138: "" ! 139: "* ! 140: { ! 141: CC_STATUS_INIT; ! 142: switch (which_alternative) ! 143: { ! 144: case 0: ! 145: return \"ldd %1\"; ! 146: case 1: ! 147: if (push_operand (operands[0], DFmode)) ! 148: return \"pushd\"; ! 149: else ! 150: return \"std %0\"; ! 151: case 2: ! 152: return output_move_double (operands); ! 153: } ! 154: }") ! 155: ! 156: ! 157: ;======================================================================== ! 158: ; The tahoe has the following semantics for byte (and similar for word) ! 159: ; operands: if the operand is a register or immediate, it takes the full 32 ! 160: ; bit operand, if the operand is memory, it sign-extends the byte. The ! 161: ; operation is performed on the 32 bit values. If the destination is a ! 162: ; register, the full 32 bit result is stored, if the destination is memory, ! 163: ; of course only the low part is stored. The condition code is based on the ! 164: ; 32 bit operation. Only on the movz instructions the byte from memory is ! 165: ; zero-extended rather than sign-extended. ! 166: ! 167: ; This means that for arithmetic instructions we can use addb etc. to ! 168: ; perform a long add from a signed byte from memory to a register. Of ! 169: ; course this would also work for logical operations, but that doesn't seem ! 170: ; very useful. ! 171: ! 172: (define_insn "" ! 173: [(set (match_operand:SI 0 "register_operand" "=r") ! 174: (plus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) ! 175: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] ! 176: "" ! 177: "addb3 %1,%2,%0") ! 178: ! 179: (define_insn "" ! 180: [(set (match_operand:SI 0 "register_operand" "=r") ! 181: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri") ! 182: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] ! 183: "" ! 184: "* ! 185: { ! 186: if (rtx_equal_p (operands[0], operands[1])) ! 187: return \"addb2 %2,%0\"; ! 188: return \"addb3 %1,%2,%0\"; ! 189: }") ! 190: ! 191: ; We can also consider the result to be a half integer ! 192: ! 193: (define_insn "" ! 194: [(set (match_operand:HI 0 "register_operand" "=r") ! 195: (plus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) ! 196: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] ! 197: "" ! 198: "addb3 %1,%2,%0") ! 199: ! 200: (define_insn "" ! 201: [(set (match_operand:HI 0 "register_operand" "=r") ! 202: (plus:HI (match_operand:HI 1 "nonmemory_operand" "%ri") ! 203: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] ! 204: "" ! 205: "* ! 206: { ! 207: if (rtx_equal_p (operands[0], operands[1])) ! 208: return \"addb2 %2,%0\"; ! 209: return \"addb3 %1,%2,%0\"; ! 210: }") ! 211: ! 212: ; The same applies to words (HI) ! 213: ! 214: (define_insn "" ! 215: [(set (match_operand:SI 0 "register_operand" "=r") ! 216: (plus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) ! 217: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] ! 218: "" ! 219: "addw3 %1,%2,%0") ! 220: ! 221: (define_insn "" ! 222: [(set (match_operand:SI 0 "register_operand" "=r") ! 223: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri") ! 224: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] ! 225: "" ! 226: "* ! 227: { ! 228: if (rtx_equal_p (operands[0], operands[1])) ! 229: return \"addw2 %2,%0\"; ! 230: return \"addw3 %1,%2,%0\"; ! 231: }") ! 232: ! 233: ; ======================= Now for subtract ============================== ! 234: ! 235: (define_insn "" ! 236: [(set (match_operand:SI 0 "register_operand" "=r") ! 237: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) ! 238: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] ! 239: "" ! 240: "subb3 %2,%1,%0") ! 241: ! 242: (define_insn "" ! 243: [(set (match_operand:SI 0 "register_operand" "=r") ! 244: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri") ! 245: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] ! 246: "" ! 247: "* ! 248: { ! 249: if (rtx_equal_p (operands[0], operands[1])) ! 250: return \"subb2 %2,%0\"; ! 251: return \"subb3 %2,%1,%0\"; ! 252: }") ! 253: ! 254: (define_insn "" ! 255: [(set (match_operand:SI 0 "register_operand" "=r") ! 256: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) ! 257: (match_operand:SI 2 "nonmemory_operand" "ri")))] ! 258: "" ! 259: "subb3 %2,%1,%0") ! 260: ! 261: ; We can also consider the result to be a half integer ! 262: ! 263: (define_insn "" ! 264: [(set (match_operand:HI 0 "register_operand" "=r") ! 265: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) ! 266: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] ! 267: "" ! 268: "subb3 %2,%1,%0") ! 269: ! 270: (define_insn "" ! 271: [(set (match_operand:HI 0 "register_operand" "=r") ! 272: (minus:HI (match_operand:HI 1 "nonmemory_operand" "%ri") ! 273: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] ! 274: "" ! 275: "* ! 276: { ! 277: if (rtx_equal_p (operands[0], operands[1])) ! 278: return \"subb2 %2,%0\"; ! 279: return \"subb3 %2,%1,%0\"; ! 280: }") ! 281: ! 282: (define_insn "" ! 283: [(set (match_operand:HI 0 "register_operand" "=r") ! 284: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) ! 285: (match_operand:HI 2 "nonmemory_operand" "ri")))] ! 286: "" ! 287: "subb3 %2,%1,%0") ! 288: ! 289: ; The same applies to words (HI) ! 290: ! 291: (define_insn "" ! 292: [(set (match_operand:SI 0 "register_operand" "=r") ! 293: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) ! 294: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] ! 295: "" ! 296: "subw3 %2,%1,%0") ! 297: ! 298: (define_insn "" ! 299: [(set (match_operand:SI 0 "register_operand" "=r") ! 300: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri") ! 301: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] ! 302: "" ! 303: "* ! 304: { ! 305: if (rtx_equal_p (operands[0], operands[1])) ! 306: return \"subw2 %2,%0\"; ! 307: return \"subw3 %2,%1,%0\"; ! 308: }") ! 309: ! 310: (define_insn "" ! 311: [(set (match_operand:SI 0 "register_operand" "=r") ! 312: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) ! 313: (match_operand:SI 2 "nonmemory_operand" "ri")))] ! 314: "" ! 315: "subw3 %2,%1,%0") ! 316: ! 317: ; ======================= Now for neg ============================== ! 318: ! 319: (define_insn "" ! 320: [(set (match_operand:SI 0 "register_operand" "=r") ! 321: (neg:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] ! 322: "" ! 323: "mnegb %1,%0") ! 324: ! 325: (define_insn "" ! 326: [(set (match_operand:HI 0 "register_operand" "=r") ! 327: (neg:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))))] ! 328: "" ! 329: "mnegb %1,%0") ! 330: ! 331: (define_insn "" ! 332: [(set (match_operand:SI 0 "register_operand" "=r") ! 333: (neg:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] ! 334: "" ! 335: "mnegw %1,%0") ! 336: ! 337: ;======================================================================== ! 338: ! 339: ! 340: (define_insn "addsi3" ! 341: [(set (match_operand:SI 0 "general_operand" "=g") ! 342: (plus:SI (match_operand:SI 1 "general_operand" "g") ! 343: (match_operand:SI 2 "general_operand" "g")))] ! 344: "" ! 345: "* ! 346: { ! 347: if (rtx_equal_p (operands[0], operands[1])) ! 348: { ! 349: if (operands[2] == const1_rtx) ! 350: return \"incl %0\"; ! 351: if (GET_CODE (operands[2]) == CONST_INT ! 352: && INTVAL (operands[2]) == -1) ! 353: return \"decl %0\"; ! 354: if (GET_CODE (operands[2]) == CONST_INT ! 355: && (unsigned) (- INTVAL (operands[2])) < 64) ! 356: return \"subl2 $%n2,%0\"; ! 357: return \"addl2 %2,%0\"; ! 358: } ! 359: if (rtx_equal_p (operands[0], operands[2])) ! 360: return \"addl2 %1,%0\"; ! 361: if (GET_CODE (operands[2]) == CONST_INT ! 362: && GET_CODE (operands[1]) == REG) ! 363: { ! 364: if (push_operand (operands[0], SImode)) ! 365: return \"pushab %c2(%1)\"; ! 366: return \"movab %c2(%1),%0\"; ! 367: } ! 368: if (GET_CODE (operands[2]) == CONST_INT ! 369: && (unsigned) (- INTVAL (operands[2])) < 64) ! 370: return \"subl3 $%n2,%1,%0\"; ! 371: return \"addl3 %1,%2,%0\"; ! 372: }") ! 373: ! 374: ! 375: (define_insn "addhi3" ! 376: [(set (match_operand:HI 0 "general_operand" "=g") ! 377: (plus:HI (match_operand:HI 1 "general_operand" "g") ! 378: (match_operand:HI 2 "general_operand" "g")))] ! 379: "" ! 380: "* ! 381: { ! 382: if (rtx_equal_p (operands[0], operands[1])) ! 383: { ! 384: if (operands[2] == const1_rtx) ! 385: return \"incw %0\"; ! 386: if (GET_CODE (operands[2]) == CONST_INT ! 387: && INTVAL (operands[2]) == -1) ! 388: return \"decw %0\"; ! 389: if (GET_CODE (operands[2]) == CONST_INT ! 390: && (unsigned) (- INTVAL (operands[2])) < 64) ! 391: return \"subw2 $%n2,%0\"; ! 392: return \"addw2 %2,%0\"; ! 393: } ! 394: if (rtx_equal_p (operands[0], operands[2])) ! 395: return \"addw2 %1,%0\"; ! 396: if (GET_CODE (operands[2]) == CONST_INT ! 397: && (unsigned) (- INTVAL (operands[2])) < 64) ! 398: return \"subw3 $%n2,%1,%0\"; ! 399: return \"addw3 %1,%2,%0\"; ! 400: }") ! 401: ! 402: ! 403: (define_insn "addqi3" ! 404: [(set (match_operand:QI 0 "general_operand" "=g") ! 405: (plus:QI (match_operand:QI 1 "general_operand" "g") ! 406: (match_operand:QI 2 "general_operand" "g")))] ! 407: "" ! 408: "* ! 409: { ! 410: if (rtx_equal_p (operands[0], operands[1])) ! 411: { ! 412: if (operands[2] == const1_rtx) ! 413: return \"incb %0\"; ! 414: if (GET_CODE (operands[2]) == CONST_INT ! 415: && INTVAL (operands[2]) == -1) ! 416: return \"decb %0\"; ! 417: if (GET_CODE (operands[2]) == CONST_INT ! 418: && (unsigned) (- INTVAL (operands[2])) < 64) ! 419: return \"subb2 $%n2,%0\"; ! 420: return \"addb2 %2,%0\"; ! 421: } ! 422: if (rtx_equal_p (operands[0], operands[2])) ! 423: return \"addb2 %1,%0\"; ! 424: if (GET_CODE (operands[2]) == CONST_INT ! 425: && (unsigned) (- INTVAL (operands[2])) < 64) ! 426: return \"subb3 $%n2,%1,%0\"; ! 427: return \"addb3 %1,%2,%0\"; ! 428: }") ! 429: ! 430: ; addsf3 can only add into the fpp register since the fpp is treated ! 431: ; as a separate unit in the machine. It also doesn't set the flags at ! 432: ; all. ! 433: ! 434: (define_insn "addsf3" ! 435: [(set (match_operand:SF 0 "register_operand" "=a") ! 436: (plus:SF (match_operand:SF 1 "register_operand" "%0") ! 437: (match_operand:SF 2 "general_operand" "g")))] ! 438: "" ! 439: "* ! 440: { ! 441: CC_STATUS_INIT; ! 442: return \"addf %2\"; ! 443: }") ! 444: ! 445: ! 446: ; adddf3 can only add into the fpp reg since the fpp is treated as a ! 447: ; separate entity. Doubles can only be read from a register or memory ! 448: ; since a double is not an immediate mode. Flags are not set by this ! 449: ; instruction. ! 450: ! 451: (define_insn "adddf3" ! 452: [(set (match_operand:DF 0 "register_operand" "=a") ! 453: (plus:DF (match_operand:DF 1 "register_operand" "%0") ! 454: (match_operand:DF 2 "general_operand" "rm")))] ! 455: "" ! 456: "* ! 457: { ! 458: CC_STATUS_INIT; ! 459: return \"addd %2\"; ! 460: }") ! 461: ! 462: ! 463: ; Subtraction from the sp (needed by the built in alloc funtion) needs ! 464: ; to be different since the sp cannot be directly read on the tahoe. ! 465: ; If it's a simple constant, you just use displacment. Otherwise, you ! 466: ; push the sp, and then do the subtraction off the stack. ! 467: ! 468: (define_insn "subsi3" ! 469: [(set (match_operand:SI 0 "general_operand" "=g") ! 470: (minus:SI (match_operand:SI 1 "general_operand" "g") ! 471: (match_operand:SI 2 "general_operand" "g")))] ! 472: "" ! 473: "* ! 474: { ! 475: if (rtx_equal_p (operands[0], operands[1])) ! 476: { ! 477: if (operands[2] == const1_rtx) ! 478: return \"decl %0\"; ! 479: if (GET_CODE(operands[0]) == REG && REGNO(operands[0]) == 14) ! 480: { ! 481: if (GET_CODE(operands[2]) == CONST_INT) ! 482: return \"movab %n2(sp),sp\"; ! 483: else ! 484: return \"pushab (sp)\;subl3 %2,(sp),sp\"; ! 485: } ! 486: return \"subl2 %2,%0\"; ! 487: } ! 488: if (rtx_equal_p (operands[1], operands[2])) ! 489: return \"clrl %0\"; ! 490: return \"subl3 %2,%1,%0\"; ! 491: }") ! 492: ! 493: ! 494: (define_insn "subhi3" ! 495: [(set (match_operand:HI 0 "general_operand" "=g") ! 496: (minus:HI (match_operand:HI 1 "general_operand" "g") ! 497: (match_operand:HI 2 "general_operand" "g")))] ! 498: "" ! 499: "* ! 500: { ! 501: if (rtx_equal_p (operands[0], operands[1])) ! 502: { ! 503: if (operands[2] == const1_rtx) ! 504: return \"decw %0\"; ! 505: return \"subw2 %2,%0\"; ! 506: } ! 507: if (rtx_equal_p (operands[1], operands[2])) ! 508: return \"clrw %0\"; ! 509: return \"subw3 %2,%1,%0\"; ! 510: }") ! 511: ! 512: ! 513: (define_insn "subqi3" ! 514: [(set (match_operand:QI 0 "general_operand" "=g") ! 515: (minus:QI (match_operand:QI 1 "general_operand" "g") ! 516: (match_operand:QI 2 "general_operand" "g")))] ! 517: "" ! 518: "* ! 519: { ! 520: if (rtx_equal_p (operands[0], operands[1])) ! 521: { ! 522: if (operands[2] == const1_rtx) ! 523: return \"decb %0\"; ! 524: return \"subb2 %2,%0\"; ! 525: } ! 526: if (rtx_equal_p (operands[1], operands[2])) ! 527: return \"clrb %0\"; ! 528: return \"subb3 %2,%1,%0\"; ! 529: }") ! 530: ! 531: ! 532: ; subsf3 can only subtract into the fpp accumulator due to the way ! 533: ; the fpp reg is limited by the instruction set. This also doesn't ! 534: ; bother setting up flags. ! 535: ! 536: (define_insn "subsf3" ! 537: [(set (match_operand:SF 0 "register_operand" "=a") ! 538: (minus:SF (match_operand:SF 1 "register_operand" "0") ! 539: (match_operand:SF 2 "general_operand" "g")))] ! 540: "" ! 541: "* ! 542: { ! 543: CC_STATUS_INIT; ! 544: return \"subf %2\"; ! 545: }") ! 546: ! 547: ! 548: ; subdf3 is set up to subtract into the fpp reg due to limitations ! 549: ; of the fpp instruction set. Doubles can not be immediate. This ! 550: ; instruction does not set the flags. ! 551: ! 552: (define_insn "subdf3" ! 553: [(set (match_operand:DF 0 "register_operand" "=a") ! 554: (minus:DF (match_operand:DF 1 "register_operand" "0") ! 555: (match_operand:DF 2 "general_operand" "rm")))] ! 556: "" ! 557: "* ! 558: { ! 559: CC_STATUS_INIT; ! 560: return \"subd %2\"; ! 561: }") ! 562: ! 563: ! 564: (define_insn "mulsi3" ! 565: [(set (match_operand:SI 0 "general_operand" "=g") ! 566: (mult:SI (match_operand:SI 1 "general_operand" "g") ! 567: (match_operand:SI 2 "general_operand" "g")))] ! 568: "" ! 569: "* ! 570: { ! 571: if (rtx_equal_p (operands[0], operands[1])) ! 572: return \"mull2 %2,%0\"; ! 573: if (rtx_equal_p (operands[0], operands[2])) ! 574: return \"mull2 %1,%0\"; ! 575: return \"mull3 %1,%2,%0\"; ! 576: }") ! 577: ! 578: ! 579: ; mulsf3 can only multiply into the fpp accumulator due to limitations ! 580: ; of the fpp. It also does not set the condition codes properly. ! 581: ! 582: (define_insn "mulsf3" ! 583: [(set (match_operand:SF 0 "register_operand" "=a") ! 584: (mult:SF (match_operand:SF 1 "register_operand" "%0") ! 585: (match_operand:SF 2 "general_operand" "g")))] ! 586: "" ! 587: "* ! 588: { ! 589: CC_STATUS_INIT; ! 590: return \"mulf %2\"; ! 591: }") ! 592: ! 593: ! 594: ; muldf3 can only multiply into the fpp reg since the fpp is limited ! 595: ; from the rest. Doubles may not be immediate mode. This does not set ! 596: ; the flags like gcc would expect. ! 597: ! 598: (define_insn "muldf3" ! 599: [(set (match_operand:DF 0 "register_operand" "=a") ! 600: (mult:DF (match_operand:DF 1 "register_operand" "%0") ! 601: (match_operand:DF 2 "general_operand" "rm")))] ! 602: "" ! 603: "* ! 604: { ! 605: CC_STATUS_INIT; ! 606: return \"muld %2\"; ! 607: }") ! 608: ! 609: ! 610: ! 611: (define_insn "divsi3" ! 612: [(set (match_operand:SI 0 "general_operand" "=g") ! 613: (div:SI (match_operand:SI 1 "general_operand" "g") ! 614: (match_operand:SI 2 "general_operand" "g")))] ! 615: "" ! 616: "* ! 617: { ! 618: if (rtx_equal_p (operands[1], operands[2])) ! 619: return \"movl $1,%0\"; ! 620: if (operands[1] == const0_rtx) ! 621: return \"clrl %0\"; ! 622: if (GET_CODE (operands[2]) == CONST_INT ! 623: && INTVAL (operands[2]) == -1) ! 624: return \"mnegl %1,%0\"; ! 625: if (rtx_equal_p (operands[0], operands[1])) ! 626: return \"divl2 %2,%0\"; ! 627: return \"divl3 %2,%1,%0\"; ! 628: }") ! 629: ! 630: ! 631: ; divsf3 must divide into the fpp accumulator. Flags are not set by ! 632: ; this instruction, so they are cleared. ! 633: ! 634: (define_insn "divsf3" ! 635: [(set (match_operand:SF 0 "register_operand" "=a") ! 636: (div:SF (match_operand:SF 1 "register_operand" "0") ! 637: (match_operand:SF 2 "general_operand" "g")))] ! 638: "" ! 639: "* ! 640: { ! 641: CC_STATUS_INIT; ! 642: return \"divf %2\"; ! 643: }") ! 644: ! 645: ! 646: ; divdf3 also must divide into the fpp reg so optimization isn't ! 647: ; possible. Note that doubles cannot be immediate. The flags here ! 648: ; are not set correctly so they must be ignored. ! 649: ! 650: (define_insn "divdf3" ! 651: [(set (match_operand:DF 0 "register_operand" "=a") ! 652: (div:DF (match_operand:DF 1 "register_operand" "0") ! 653: (match_operand:DF 2 "general_operand" "rm")))] ! 654: "" ! 655: "* ! 656: { ! 657: CC_STATUS_INIT; ! 658: return \"divd %2\"; ! 659: }") ! 660: ! 661: ! 662: ! 663: (define_insn "andsi3" ! 664: [(set (match_operand:SI 0 "general_operand" "=g") ! 665: (and:SI (match_operand:SI 1 "general_operand" "g") ! 666: (match_operand:SI 2 "general_operand" "g")))] ! 667: "" ! 668: "* ! 669: { ! 670: if (rtx_equal_p (operands[0], operands[1])) ! 671: return \"andl2 %2,%0\"; ! 672: if (rtx_equal_p (operands[0], operands[2])) ! 673: return \"andl2 %1,%0\"; ! 674: return \"andl3 %2,%1,%0\"; ! 675: }") ! 676: ! 677: ! 678: ! 679: (define_insn "andhi3" ! 680: [(set (match_operand:HI 0 "general_operand" "=g") ! 681: (and:HI (match_operand:HI 1 "general_operand" "g") ! 682: (match_operand:HI 2 "general_operand" "g")))] ! 683: "" ! 684: "* ! 685: { ! 686: if (rtx_equal_p (operands[0], operands[1])) ! 687: return \"andw2 %2,%0\"; ! 688: if (rtx_equal_p (operands[0], operands[2])) ! 689: return \"andw2 %1,%0\"; ! 690: return \"andw3 %2,%1,%0\"; ! 691: }") ! 692: ! 693: ! 694: (define_insn "andqi3" ! 695: [(set (match_operand:QI 0 "general_operand" "=g") ! 696: (and:QI (match_operand:QI 1 "general_operand" "g") ! 697: (match_operand:QI 2 "general_operand" "g")))] ! 698: "" ! 699: "* ! 700: { ! 701: if (rtx_equal_p (operands[0], operands[1])) ! 702: return \"andb2 %2,%0\"; ! 703: if (rtx_equal_p (operands[0], operands[2])) ! 704: return \"andb2 %1,%0\"; ! 705: return \"andb3 %2,%1,%0\"; ! 706: }") ! 707: ! 708: ! 709: (define_insn "iorsi3" ! 710: [(set (match_operand:SI 0 "general_operand" "=g") ! 711: (ior:SI (match_operand:SI 1 "general_operand" "g") ! 712: (match_operand:SI 2 "general_operand" "g")))] ! 713: "" ! 714: "* ! 715: { ! 716: if (rtx_equal_p (operands[0], operands[1])) ! 717: return \"orl2 %2,%0\"; ! 718: if (rtx_equal_p (operands[0], operands[2])) ! 719: return \"orl2 %1,%0\"; ! 720: return \"orl3 %2,%1,%0\"; ! 721: }") ! 722: ! 723: ! 724: ! 725: (define_insn "iorhi3" ! 726: [(set (match_operand:HI 0 "general_operand" "=g") ! 727: (ior:HI (match_operand:HI 1 "general_operand" "g") ! 728: (match_operand:HI 2 "general_operand" "g")))] ! 729: "" ! 730: "* ! 731: { ! 732: if (rtx_equal_p (operands[0], operands[1])) ! 733: return \"orw2 %2,%0\"; ! 734: if (rtx_equal_p (operands[0], operands[2])) ! 735: return \"orw2 %1,%0\"; ! 736: return \"orw3 %2,%1,%0\"; ! 737: }") ! 738: ! 739: ! 740: ! 741: (define_insn "iorqi3" ! 742: [(set (match_operand:QI 0 "general_operand" "=g") ! 743: (ior:QI (match_operand:QI 1 "general_operand" "g") ! 744: (match_operand:QI 2 "general_operand" "g")))] ! 745: "" ! 746: "* ! 747: { ! 748: if (rtx_equal_p (operands[0], operands[1])) ! 749: return \"orb2 %2,%0\"; ! 750: if (rtx_equal_p (operands[0], operands[2])) ! 751: return \"orb2 %1,%0\"; ! 752: return \"orb3 %2,%1,%0\"; ! 753: }") ! 754: ! 755: ! 756: (define_insn "xorsi3" ! 757: [(set (match_operand:SI 0 "general_operand" "=g") ! 758: (xor:SI (match_operand:SI 1 "general_operand" "g") ! 759: (match_operand:SI 2 "general_operand" "g")))] ! 760: "" ! 761: "* ! 762: { ! 763: if (rtx_equal_p (operands[0], operands[1])) ! 764: return \"xorl2 %2,%0\"; ! 765: if (rtx_equal_p (operands[0], operands[2])) ! 766: return \"xorl2 %1,%0\"; ! 767: return \"xorl3 %2,%1,%0\"; ! 768: }") ! 769: ! 770: ! 771: (define_insn "xorhi3" ! 772: [(set (match_operand:HI 0 "general_operand" "=g") ! 773: (xor:HI (match_operand:HI 1 "general_operand" "g") ! 774: (match_operand:HI 2 "general_operand" "g")))] ! 775: "" ! 776: "* ! 777: { ! 778: if (rtx_equal_p (operands[0], operands[1])) ! 779: return \"xorw2 %2,%0\"; ! 780: if (rtx_equal_p (operands[0], operands[2])) ! 781: return \"xorw2 %1,%0\"; ! 782: return \"xorw3 %2,%1,%0\"; ! 783: }") ! 784: ! 785: ! 786: (define_insn "xorqi3" ! 787: [(set (match_operand:QI 0 "general_operand" "=g") ! 788: (xor:QI (match_operand:QI 1 "general_operand" "g") ! 789: (match_operand:QI 2 "general_operand" "g")))] ! 790: "" ! 791: "* ! 792: { ! 793: if (rtx_equal_p (operands[0], operands[1])) ! 794: return \"xorb2 %2,%0\"; ! 795: if (rtx_equal_p (operands[0], operands[2])) ! 796: return \"xorb2 %1,%0\"; ! 797: return \"xorb3 %2,%1,%0\"; ! 798: }") ! 799: ! 800: ! 801: ; shifts on the tahoe are expensive, try some magic first... ! 802: ! 803: (define_insn "ashlsi3" ! 804: [(set (match_operand:SI 0 "general_operand" "=g") ! 805: (ashift:SI (match_operand:SI 1 "general_operand" "g") ! 806: (match_operand:QI 2 "general_operand" "g")))] ! 807: "" ! 808: "* ! 809: { ! 810: if (GET_CODE(operands[2]) == REG) ! 811: return \"mull3 ___shtab[%2],%1,%0\"; ! 812: /* if (GET_CODE(operands[2]) == REG) ! 813: if (rtx_equal_p (operands[0], operands[1])) ! 814: return \"mull2 ___shtab[%2],%1\"; ! 815: else ! 816: return \"mull3 ___shtab[%2],%1,%0\"; */ ! 817: if (GET_CODE(operands[1]) == REG) ! 818: { ! 819: if (operands[2] == const1_rtx) ! 820: { ! 821: CC_STATUS_INIT; ! 822: return \"movaw 0[%1],%0\"; ! 823: } ! 824: if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2) ! 825: { ! 826: CC_STATUS_INIT; ! 827: return \"moval 0[%1],%0\"; ! 828: } ! 829: } ! 830: if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1) ! 831: return \"shal %2,%1,%0\"; ! 832: if (rtx_equal_p (operands[0], operands[1])) ! 833: return \"mull2 %s2,%1\"; ! 834: else ! 835: return \"mull3 %s2,%1,%0\"; ! 836: }") ! 837: ! 838: ! 839: (define_insn "ashrsi3" ! 840: [(set (match_operand:SI 0 "general_operand" "=g") ! 841: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") ! 842: (match_operand:QI 2 "general_operand" "g")))] ! 843: "" ! 844: "shar %2,%1,%0") ! 845: ! 846: ! 847: ; shifts are very expensive, try some magic first... ! 848: ! 849: (define_insn "lshlsi3" ! 850: [(set (match_operand:SI 0 "general_operand" "=g") ! 851: (lshift:SI (match_operand:SI 1 "general_operand" "g") ! 852: (match_operand:QI 2 "general_operand" "g")))] ! 853: "" ! 854: "* ! 855: { ! 856: if (GET_CODE(operands[2]) == REG) ! 857: return \"mull3 ___shtab[%2],%1,%0\"; ! 858: /* if (GET_CODE(operands[2]) == REG) ! 859: if (rtx_equal_p (operands[0], operands[1])) ! 860: return \"mull2 ___shtab[%2],%1\"; ! 861: else ! 862: return \"mull3 ___shtab[%2],%1,%0\"; */ ! 863: if (GET_CODE(operands[1]) == REG) ! 864: { ! 865: if (operands[2] == const1_rtx) ! 866: { ! 867: CC_STATUS_INIT; ! 868: return \"movaw 0[%1],%0\"; ! 869: } ! 870: if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2) ! 871: { ! 872: CC_STATUS_INIT; ! 873: return \"moval 0[%1],%0\"; ! 874: } ! 875: } ! 876: if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1) ! 877: return \"shll %2,%1,%0\"; ! 878: if (rtx_equal_p (operands[0], operands[1])) ! 879: return \"mull2 %s2,%1\"; ! 880: else ! 881: return \"mull3 %s2,%1,%0\"; ! 882: }") ! 883: ! 884: ! 885: (define_insn "lshrsi3" ! 886: [(set (match_operand:SI 0 "general_operand" "=g") ! 887: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g") ! 888: (match_operand:QI 2 "general_operand" "g")))] ! 889: "" ! 890: "shrl %2,%1,%0") ! 891: ! 892: ! 893: (define_insn "negsi2" ! 894: [(set (match_operand:SI 0 "general_operand" "=g") ! 895: (neg:SI (match_operand:SI 1 "general_operand" "g")))] ! 896: "" ! 897: "mnegl %1,%0") ! 898: ! 899: ! 900: (define_insn "neghi2" ! 901: [(set (match_operand:HI 0 "general_operand" "=g") ! 902: (neg:HI (match_operand:HI 1 "general_operand" "g")))] ! 903: "" ! 904: "mnegw %1,%0") ! 905: ! 906: ! 907: (define_insn "negqi2" ! 908: [(set (match_operand:QI 0 "general_operand" "=g") ! 909: (neg:QI (match_operand:QI 1 "general_operand" "g")))] ! 910: "" ! 911: "mnegb %1,%0") ! 912: ! 913: ! 914: ; negsf2 can only negate the value already in the fpp accumulator. ! 915: ; The value remains in the fpp accumulator. No flags are set. ! 916: ! 917: (define_insn "negsf2" ! 918: [(set (match_operand:SF 0 "register_operand" "=a,=a") ! 919: (neg:SF (match_operand:SF 1 "register_operand" "a,g")))] ! 920: "" ! 921: "* ! 922: { ! 923: CC_STATUS_INIT; ! 924: switch (which_alternative) ! 925: { ! 926: case 0: return \"negf\"; ! 927: case 1: return \"lnf %1\"; ! 928: } ! 929: }") ! 930: ! 931: ! 932: ; negdf2 can only negate the value already in the fpp accumulator. ! 933: ; The value remains in the fpp accumulator. No flags are set. ! 934: ! 935: (define_insn "negdf2" ! 936: [(set (match_operand:DF 0 "register_operand" "=a,=a") ! 937: (neg:DF (match_operand:DF 1 "register_operand" "a,g")))] ! 938: "" ! 939: "* ! 940: { ! 941: CC_STATUS_INIT; ! 942: switch (which_alternative) ! 943: { ! 944: case 0: return \"negd\"; ! 945: case 1: return \"lnd %1\"; ! 946: } ! 947: }") ! 948: ! 949: ! 950: ; sqrtsf2 tahoe can calculate the square root of a float in the ! 951: ; fpp accumulator. The answer remains in the fpp accumulator. No ! 952: ; flags are set by this function. ! 953: ! 954: (define_insn "sqrtsf2" ! 955: [(set (match_operand:SF 0 "register_operand" "=a") ! 956: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] ! 957: "" ! 958: "* ! 959: { ! 960: CC_STATUS_INIT; ! 961: return \"sqrtf\"; ! 962: }") ! 963: ! 964: ! 965: ; ffssi2 tahoe instruction gives one less than gcc desired result for ! 966: ; any given input. So the increment is necessary here. ! 967: ! 968: (define_insn "ffssi2" ! 969: [(set (match_operand:SI 0 "general_operand" "=g") ! 970: (ffs:SI (match_operand:SI 1 "general_operand" "g")))] ! 971: "" ! 972: "* ! 973: { ! 974: if (push_operand(operands[0], SImode)) ! 975: return \"ffs %1,%0\;incl (sp)\"; ! 976: return \"ffs %1,%0\;incl %0\"; ! 977: }") ! 978: ! 979: ! 980: (define_insn "one_cmplsi2" ! 981: [(set (match_operand:SI 0 "general_operand" "=g") ! 982: (not:SI (match_operand:SI 1 "general_operand" "g")))] ! 983: "" ! 984: "mcoml %1,%0") ! 985: ! 986: ! 987: (define_insn "one_cmplhi2" ! 988: [(set (match_operand:HI 0 "general_operand" "=g") ! 989: (not:HI (match_operand:HI 1 "general_operand" "g")))] ! 990: "" ! 991: "mcomw %1,%0") ! 992: ! 993: ! 994: (define_insn "one_cmplqi2" ! 995: [(set (match_operand:QI 0 "general_operand" "=g") ! 996: (not:QI (match_operand:QI 1 "general_operand" "g")))] ! 997: "" ! 998: "mcomb %1,%0") ! 999: ! 1000: ! 1001: ; cmpsi works fine, but due to microcode problems, the tahoe doesn't ! 1002: ; properly compare hi's and qi's. Leaving them out seems to be acceptable ! 1003: ; to the compiler, so they were left out. Compares of the stack are ! 1004: ; possible, though. ! 1005: ! 1006: ; There are optimized cases possible, however. These follow first. ! 1007: ! 1008: (define_insn "" ! 1009: [(set (cc0) ! 1010: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")) ! 1011: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] ! 1012: "" ! 1013: "cmpw %0,%1") ! 1014: ! 1015: (define_insn "" ! 1016: [(set (cc0) ! 1017: (compare (match_operand:SI 0 "nonmemory_operand" "ri") ! 1018: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] ! 1019: "" ! 1020: "cmpw %0,%1") ! 1021: ! 1022: (define_insn "" ! 1023: [(set (cc0) ! 1024: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")) ! 1025: (match_operand:SI 1 "nonmemory_operand" "ri")))] ! 1026: "" ! 1027: "cmpw %0,%1") ! 1028: ! 1029: ; zero-extended compares give the same result as sign-extended compares, if ! 1030: ; the compare is unsigned. Just see: if both operands are <65536 they are the ! 1031: ; same in both cases. If both are >=65536 the you effectively compare x+D ! 1032: ; with y+D, where D=2**32-2**16, so the result is the same. if x<65536 and ! 1033: ; y>=65536 then you compare x with y+D, and in both cases the result is x<y. ! 1034: ! 1035: (define_insn "" ! 1036: [(set (cc0) ! 1037: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) ! 1038: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] ! 1039: "tahoe_cmp_check (insn, operands[0], 0)" ! 1040: "cmpw %0,%1") ! 1041: ! 1042: (define_insn "" ! 1043: [(set (cc0) ! 1044: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) ! 1045: (match_operand:SI 1 "immediate_operand" "i")))] ! 1046: "tahoe_cmp_check(insn, operands[1], 65535)" ! 1047: "* ! 1048: { ! 1049: if (INTVAL (operands[1]) > 32767) ! 1050: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffff0000); ! 1051: return \"cmpw %0,%1\"; ! 1052: }") ! 1053: ! 1054: ! 1055: (define_insn "" ! 1056: [(set (cc0) ! 1057: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")) ! 1058: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] ! 1059: "" ! 1060: "cmpb %0,%1") ! 1061: ! 1062: (define_insn "" ! 1063: [(set (cc0) ! 1064: (compare (match_operand:SI 0 "nonmemory_operand" "ri") ! 1065: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] ! 1066: "" ! 1067: "cmpb %0,%1") ! 1068: ! 1069: (define_insn "" ! 1070: [(set (cc0) ! 1071: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")) ! 1072: (match_operand:SI 1 "nonmemory_operand" "ri")))] ! 1073: "" ! 1074: "cmpb %0,%1") ! 1075: ! 1076: ; zero-extended compares give the same result as sign-extended compares, if ! 1077: ; the compare is unsigned. Just see: if both operands are <128 they are the ! 1078: ; same in both cases. If both are >=128 the you effectively compare x+D ! 1079: ; with y+D, where D=2**32-2**8, so the result is the same. if x<128 and ! 1080: ; y>=128 then you compare x with y+D, and in both cases the result is x<y. ! 1081: ! 1082: (define_insn "" ! 1083: [(set (cc0) ! 1084: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) ! 1085: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] ! 1086: "tahoe_cmp_check (insn, operands[0], 0)" ! 1087: "cmpb %0,%1") ! 1088: ! 1089: (define_insn "" ! 1090: [(set (cc0) ! 1091: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) ! 1092: (match_operand:SI 1 "immediate_operand" "i")))] ! 1093: "tahoe_cmp_check(insn, operands[1], 255)" ! 1094: "* ! 1095: { ! 1096: if (INTVAL (operands[1]) > 127) ! 1097: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffffff00); ! 1098: return \"cmpb %0,%1\"; ! 1099: }") ! 1100: ! 1101: ! 1102: (define_insn "cmpsi" ! 1103: [(set (cc0) ! 1104: (compare (match_operand:SI 0 "nonimmediate_operand" "g") ! 1105: (match_operand:SI 1 "general_operand" "g")))] ! 1106: "" ! 1107: "cmpl %0,%1") ! 1108: ! 1109: ! 1110: ; cmpsf similar to vax, but first operand is expected to be in the ! 1111: ; fpp accumulator. ! 1112: ! 1113: (define_insn "cmpsf" ! 1114: [(set (cc0) ! 1115: (compare (match_operand:SF 0 "general_operand" "a,g") ! 1116: (match_operand:SF 1 "general_operand" "g,g")))] ! 1117: "" ! 1118: "* ! 1119: { ! 1120: switch (which_alternative) ! 1121: { ! 1122: case 0: return \"cmpf %1\"; ! 1123: case 1: return \"cmpf2 %0,%1\"; ! 1124: } ! 1125: }") ! 1126: ! 1127: ! 1128: ; cmpdf similar to vax, but first operand is expected to be in the ! 1129: ; fpp accumulator. Immediate doubles not allowed. ! 1130: ! 1131: (define_insn "cmpdf" ! 1132: [(set (cc0) ! 1133: (compare (match_operand:DF 0 "general_operand" "a,rm") ! 1134: (match_operand:DF 1 "general_operand" "rm,rm")))] ! 1135: "" ! 1136: "* ! 1137: { ! 1138: switch (which_alternative) ! 1139: { ! 1140: case 0: return \"cmpd %1\"; ! 1141: case 1: return \"cmpd2 %0,%1\"; ! 1142: } ! 1143: }") ! 1144: ! 1145: ;; We don't want to allow a constant operand for test insns because ! 1146: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ! 1147: ;; be folded while optimizing anyway. ! 1148: ! 1149: (define_insn "tstsi" ! 1150: [(set (cc0) ! 1151: (match_operand:SI 0 "nonimmediate_operand" "g"))] ! 1152: "" ! 1153: "tstl %0") ! 1154: ! 1155: ! 1156: ; small tests from memory are normal, but testing from registers doesn't ! 1157: ; expand the data properly. So test in this case does a convert and tests ! 1158: ; the new register data from the stack. ! 1159: ! 1160: ; First some special cases that do work ! 1161: ! 1162: ! 1163: (define_insn "" ! 1164: [(set (cc0) ! 1165: (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")))] ! 1166: "" ! 1167: "tstw %0") ! 1168: ! 1169: (define_insn "" ! 1170: [(set (cc0) ! 1171: (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")))] ! 1172: "tahoe_cmp_check (insn, operands[0], 0)" ! 1173: "tstw %0") ! 1174: ! 1175: ! 1176: (define_insn "tsthi" ! 1177: [(set (cc0) ! 1178: (match_operand:HI 0 "extendable_operand" "m,!r"))] ! 1179: "GET_MODE (operands[0]) != VOIDmode" ! 1180: "* ! 1181: { ! 1182: rtx xoperands[2]; ! 1183: extern rtx tahoe_reg_conversion_loc; ! 1184: switch (which_alternative) ! 1185: { ! 1186: case 0: ! 1187: return \"tstw %0\"; ! 1188: case 1: ! 1189: xoperands[0] = operands[0]; ! 1190: xoperands[1] = tahoe_reg_conversion_loc; ! 1191: output_asm_insn (\"movl %0,%1\", xoperands); ! 1192: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 2); ! 1193: output_asm_insn (\"tstw %a1\", xoperands); ! 1194: return \"\"; ! 1195: } ! 1196: }") ! 1197: ! 1198: ! 1199: (define_insn "" ! 1200: [(set (cc0) ! 1201: (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")))] ! 1202: "" ! 1203: "tstb %0") ! 1204: ! 1205: (define_insn "" ! 1206: [(set (cc0) ! 1207: (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")))] ! 1208: "tahoe_cmp_check (insn, operands[0], 0)" ! 1209: "tstb %0") ! 1210: ! 1211: ! 1212: (define_insn "tstqi" ! 1213: [(set (cc0) ! 1214: (match_operand:QI 0 "extendable_operand" "m,!r"))] ! 1215: "GET_MODE (operands[0]) != VOIDmode" ! 1216: "* ! 1217: { ! 1218: rtx xoperands[2]; ! 1219: extern rtx tahoe_reg_conversion_loc; ! 1220: switch (which_alternative) ! 1221: { ! 1222: case 0: ! 1223: return \"tstb %0\"; ! 1224: case 1: ! 1225: xoperands[0] = operands[0]; ! 1226: xoperands[1] = tahoe_reg_conversion_loc; ! 1227: output_asm_insn (\"movl %0,%1\", xoperands); ! 1228: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 3); ! 1229: output_asm_insn (\"tstb %a1\", xoperands); ! 1230: return \"\"; ! 1231: } ! 1232: }") ! 1233: ! 1234: ; tstsf compares a given value to a value already in the fpp accumulator. ! 1235: ; No flags are set by this so ignore them. ! 1236: ! 1237: (define_insn "tstsf" ! 1238: [(set (cc0) ! 1239: (match_operand:SF 0 "register_operand" "a"))] ! 1240: "" ! 1241: "tstf") ! 1242: ! 1243: ! 1244: ; tstdf compares a given value to a value already in the fpp accumulator. ! 1245: ; immediate doubles not allowed. Flags are ignored after this. ! 1246: ! 1247: (define_insn "tstdf" ! 1248: [(set (cc0) ! 1249: (match_operand:DF 0 "register_operand" "a"))] ! 1250: "" ! 1251: "tstd") ! 1252: ! 1253: ! 1254: ! 1255: ; movstrhi tahoe instruction does not load registers by itself like ! 1256: ; the vax counterpart does. registers 0-2 must be primed by hand. ! 1257: ; we have loaded the registers in the order: dst, src, count. ! 1258: ! 1259: (define_insn "movstrhi" ! 1260: [(set (match_operand:BLK 0 "general_operand" "p") ! 1261: (match_operand:BLK 1 "general_operand" "p")) ! 1262: (use (match_operand:HI 2 "general_operand" "g")) ! 1263: (clobber (reg:SI 0)) ! 1264: (clobber (reg:SI 1)) ! 1265: (clobber (reg:SI 2))] ! 1266: "" ! 1267: "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk") ! 1268: ! 1269: ! 1270: ; floatsisf2 on tahoe converts the long from reg/mem into the fpp ! 1271: ; accumulator. There are no hi and qi counterparts. Flags are not ! 1272: ; set correctly here. ! 1273: ! 1274: (define_insn "floatsisf2" ! 1275: [(set (match_operand:SF 0 "register_operand" "=a") ! 1276: (float:SF (match_operand:SI 1 "general_operand" "g")))] ! 1277: "" ! 1278: "* ! 1279: { ! 1280: CC_STATUS_INIT; ! 1281: return \"cvlf %1\"; ! 1282: }") ! 1283: ! 1284: ! 1285: ; floatsidf2 on tahoe converts the long from reg/mem into the fpp ! 1286: ; accumulator. There are no hi and qi counterparts. Flags are not ! 1287: ; set correctly here. ! 1288: ! 1289: (define_insn "floatsidf2" ! 1290: [(set (match_operand:DF 0 "register_operand" "=a") ! 1291: (float:DF (match_operand:SI 1 "general_operand" "g")))] ! 1292: "" ! 1293: "* ! 1294: { ! 1295: CC_STATUS_INIT; ! 1296: return \"cvld %1\"; ! 1297: }") ! 1298: ! 1299: ! 1300: ; fix_truncsfsi2 to convert a float to long, tahoe must have the float ! 1301: ; in the fpp accumulator. Flags are not set here. ! 1302: ! 1303: (define_insn "fix_truncsfsi2" ! 1304: [(set (match_operand:SI 0 "general_operand" "=g") ! 1305: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))] ! 1306: "" ! 1307: "* ! 1308: { ! 1309: CC_STATUS_INIT; ! 1310: return \"cvfl %0\"; ! 1311: }") ! 1312: ! 1313: ! 1314: ; fix_truncsfsi2 to convert a double to long, tahoe must have the double ! 1315: ; in the fpp accumulator. Flags are not set here. ! 1316: ! 1317: (define_insn "fix_truncdfsi2" ! 1318: [(set (match_operand:SI 0 "general_operand" "=g") ! 1319: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))] ! 1320: "" ! 1321: "* ! 1322: { ! 1323: CC_STATUS_INIT; ! 1324: return \"cvdl %0\"; ! 1325: }") ! 1326: ! 1327: ! 1328: (define_insn "truncsihi2" ! 1329: [(set (match_operand:HI 0 "general_operand" "=g") ! 1330: (truncate:HI (match_operand:SI 1 "general_operand" "g")))] ! 1331: "" ! 1332: "cvtlw %1,%0") ! 1333: ! 1334: ! 1335: (define_insn "truncsiqi2" ! 1336: [(set (match_operand:QI 0 "general_operand" "=g") ! 1337: (truncate:QI (match_operand:SI 1 "general_operand" "g")))] ! 1338: "" ! 1339: "cvtlb %1,%0") ! 1340: ! 1341: ! 1342: (define_insn "trunchiqi2" ! 1343: [(set (match_operand:QI 0 "general_operand" "=g") ! 1344: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] ! 1345: "" ! 1346: "cvtwb %1,%0") ! 1347: ! 1348: ! 1349: ; The fpp related instructions don't set flags, so ignore them ! 1350: ; after this instruction. ! 1351: ! 1352: (define_insn "truncdfsf2" ! 1353: [(set (match_operand:SF 0 "register_operand" "=a") ! 1354: (float_truncate:SF (match_operand:DF 1 "register_operand" "0")))] ! 1355: "" ! 1356: "* ! 1357: { ! 1358: CC_STATUS_INIT; ! 1359: return \"cvdf\"; ! 1360: }") ! 1361: ! 1362: ! 1363: ; This monster is to cover for the Tahoe's nasty habit of not extending ! 1364: ; a number if the source is in a register. (It just moves it!) Case 0 is ! 1365: ; a normal extend from memory. Case 1 does the extension from the top of ! 1366: ; the stack. Extension from the stack doesn't set the flags right since ! 1367: ; the moval changes them. ! 1368: ! 1369: (define_insn "extendhisi2" ! 1370: [(set (match_operand:SI 0 "general_operand" "=g,?=g") ! 1371: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))] ! 1372: "" ! 1373: "* ! 1374: { ! 1375: switch (which_alternative) ! 1376: { ! 1377: case 0: ! 1378: return \"cvtwl %1,%0\"; ! 1379: case 1: ! 1380: if (push_operand (operands[0], SImode)) ! 1381: return \"pushl %1\;cvtwl 2(sp),(sp)\"; ! 1382: else ! 1383: { ! 1384: CC_STATUS_INIT; ! 1385: return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\"; ! 1386: } ! 1387: } ! 1388: }") ! 1389: ! 1390: ; This monster is to cover for the Tahoe's nasty habit of not extending ! 1391: ; a number if the source is in a register. (It just moves it!) Case 0 is ! 1392: ; a normal extend from memory. Case 1 does the extension from the top of ! 1393: ; the stack. Extension from the stack doesn't set the flags right since ! 1394: ; the moval changes them. ! 1395: ! 1396: (define_insn "extendqisi2" ! 1397: [(set (match_operand:SI 0 "general_operand" "=g,?=g") ! 1398: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] ! 1399: "" ! 1400: "* ! 1401: { ! 1402: switch (which_alternative) ! 1403: { ! 1404: case 0: ! 1405: return \"cvtbl %1,%0\"; ! 1406: case 1: ! 1407: if (push_operand (operands[0], SImode)) ! 1408: return \"pushl %1\;cvtbl 3(sp),(sp)\"; ! 1409: else ! 1410: { ! 1411: CC_STATUS_INIT; ! 1412: return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\"; ! 1413: } ! 1414: } ! 1415: }") ! 1416: ! 1417: ! 1418: ; This monster is to cover for the Tahoe's nasty habit of not extending ! 1419: ; a number if the source is in a register. (It just moves it!) Case 0 is ! 1420: ; a normal extend from memory. Case 1 does the extension from the top of ! 1421: ; the stack. Extension from the stack doesn't set the flags right since ! 1422: ; the moval changes them. ! 1423: ! 1424: (define_insn "extendqihi2" ! 1425: [(set (match_operand:HI 0 "general_operand" "=g,?=g") ! 1426: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] ! 1427: "" ! 1428: "* ! 1429: { ! 1430: switch (which_alternative) ! 1431: { ! 1432: case 0: ! 1433: return \"cvtbw %1,%0\"; ! 1434: case 1: ! 1435: if (push_operand (operands[0], SImode)) ! 1436: return \"pushl %1\;cvtbw 3(sp),(sp)\"; ! 1437: else ! 1438: { ! 1439: CC_STATUS_INIT; ! 1440: return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\"; ! 1441: } ! 1442: } ! 1443: }") ! 1444: ! 1445: ! 1446: ; extendsfdf2 tahoe uses the fpp accumulator to do the extension. ! 1447: ; It takes a float and loads it up directly as a double. ! 1448: ! 1449: (define_insn "extendsfdf2" ! 1450: [(set (match_operand:DF 0 "register_operand" "=a") ! 1451: (float_extend:DF (match_operand:SF 1 "general_operand" "g")))] ! 1452: "" ! 1453: "* ! 1454: { ! 1455: CC_STATUS_INIT; ! 1456: return \"ldfd %1\"; ! 1457: }") ! 1458: ! 1459: ! 1460: ; movz works fine from memory but not from register for the same reasons ! 1461: ; the cvt instructions don't work right. So we use the normal instruction ! 1462: ; from memory and we use an and to simulate it from register. This is faster ! 1463: ; than pulling it off the stack. ! 1464: ! 1465: ! 1466: (define_insn "zero_extendhisi2" ! 1467: [(set (match_operand:SI 0 "general_operand" "=g,?=g") ! 1468: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))] ! 1469: "" ! 1470: "* ! 1471: { ! 1472: switch (which_alternative) ! 1473: { ! 1474: case 0: return \"movzwl %1,%0\"; ! 1475: case 1: return \"andl3 $0xffff,%1,%0\"; ! 1476: } ! 1477: }") ! 1478: ! 1479: ; movz works fine from memory but not from register for the same reasons ! 1480: ; the cvt instructions don't work right. So we use the normal instruction ! 1481: ; from memory and we use an and to simulate it from register. This is faster ! 1482: ; than pulling it off the stack. ! 1483: ! 1484: (define_insn "zero_extendqihi2" ! 1485: [(set (match_operand:HI 0 "general_operand" "=g,?=g") ! 1486: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] ! 1487: "" ! 1488: "* ! 1489: { ! 1490: switch (which_alternative) ! 1491: { ! 1492: case 0: return \"movzbw %1,%0\"; ! 1493: case 1: return \"andw3 $0xff,%1,%0\"; ! 1494: } ! 1495: }") ! 1496: ! 1497: ! 1498: ; movz works fine from memory but not from register for the same reasons ! 1499: ; the cvt instructions don't work right. So we use the normal instruction ! 1500: ; from memory and we use an and to simulate it from register. This is faster ! 1501: ; than pulling it off the stack. ! 1502: ! 1503: (define_insn "zero_extendqisi2" ! 1504: [(set (match_operand:SI 0 "general_operand" "=g,?=g") ! 1505: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] ! 1506: "" ! 1507: "* ! 1508: { ! 1509: switch (which_alternative) ! 1510: { ! 1511: case 0: return \"movzbl %1,%0\"; ! 1512: case 1: return \"andl3 $0xff,%1,%0\"; ! 1513: } ! 1514: }") ! 1515: ! 1516: ! 1517: (define_insn "beq" ! 1518: [(set (pc) ! 1519: (if_then_else (eq (cc0) ! 1520: (const_int 0)) ! 1521: (label_ref (match_operand 0 "" "")) ! 1522: (pc)))] ! 1523: "" ! 1524: "jeql %l0") ! 1525: ! 1526: ! 1527: (define_insn "bne" ! 1528: [(set (pc) ! 1529: (if_then_else (ne (cc0) ! 1530: (const_int 0)) ! 1531: (label_ref (match_operand 0 "" "")) ! 1532: (pc)))] ! 1533: "" ! 1534: "jneq %l0") ! 1535: ! 1536: ! 1537: (define_insn "bgt" ! 1538: [(set (pc) ! 1539: (if_then_else (gt (cc0) ! 1540: (const_int 0)) ! 1541: (label_ref (match_operand 0 "" "")) ! 1542: (pc)))] ! 1543: "" ! 1544: "jgtr %l0") ! 1545: ! 1546: ! 1547: (define_insn "bgtu" ! 1548: [(set (pc) ! 1549: (if_then_else (gtu (cc0) ! 1550: (const_int 0)) ! 1551: (label_ref (match_operand 0 "" "")) ! 1552: (pc)))] ! 1553: "" ! 1554: "jgtru %l0") ! 1555: ! 1556: ! 1557: (define_insn "blt" ! 1558: [(set (pc) ! 1559: (if_then_else (lt (cc0) ! 1560: (const_int 0)) ! 1561: (label_ref (match_operand 0 "" "")) ! 1562: (pc)))] ! 1563: "" ! 1564: "jlss %l0") ! 1565: ! 1566: ! 1567: (define_insn "bltu" ! 1568: [(set (pc) ! 1569: (if_then_else (ltu (cc0) ! 1570: (const_int 0)) ! 1571: (label_ref (match_operand 0 "" "")) ! 1572: (pc)))] ! 1573: "" ! 1574: "jlssu %l0") ! 1575: ! 1576: ! 1577: (define_insn "bge" ! 1578: [(set (pc) ! 1579: (if_then_else (ge (cc0) ! 1580: (const_int 0)) ! 1581: (label_ref (match_operand 0 "" "")) ! 1582: (pc)))] ! 1583: "" ! 1584: "jgeq %l0") ! 1585: ! 1586: ! 1587: (define_insn "bgeu" ! 1588: [(set (pc) ! 1589: (if_then_else (geu (cc0) ! 1590: (const_int 0)) ! 1591: (label_ref (match_operand 0 "" "")) ! 1592: (pc)))] ! 1593: "" ! 1594: "jgequ %l0") ! 1595: ! 1596: ! 1597: (define_insn "ble" ! 1598: [(set (pc) ! 1599: (if_then_else (le (cc0) ! 1600: (const_int 0)) ! 1601: (label_ref (match_operand 0 "" "")) ! 1602: (pc)))] ! 1603: "" ! 1604: "jleq %l0") ! 1605: ! 1606: ! 1607: (define_insn "bleu" ! 1608: [(set (pc) ! 1609: (if_then_else (leu (cc0) ! 1610: (const_int 0)) ! 1611: (label_ref (match_operand 0 "" "")) ! 1612: (pc)))] ! 1613: "" ! 1614: "jlequ %l0") ! 1615: ! 1616: ! 1617: ; gcc does not account for register mask/argc longword. Thus the number ! 1618: ; for the call = number bytes for args + 4 ! 1619: ! 1620: (define_insn "call" ! 1621: [(call (match_operand:QI 0 "memory_operand" "m") ! 1622: (match_operand:QI 1 "general_operand" "g"))] ! 1623: "" ! 1624: "* ! 1625: { ! 1626: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 4)); ! 1627: if (GET_CODE(operands[0]) == MEM ! 1628: && CONSTANT_ADDRESS_P (XEXP(operands[0], 0)) ! 1629: && INTVAL (operands[1]) < 64) ! 1630: return \"callf %1,%0\"; /* this is much faster */ ! 1631: return \"calls %1,%0\"; ! 1632: }") ! 1633: ! 1634: ; gcc does not account for register mask/argc longword. Thus the number ! 1635: ; for the call = number bytes for args + 4 ! 1636: ! 1637: (define_insn "call_value" ! 1638: [(set (match_operand 0 "" "g") ! 1639: (call (match_operand:QI 1 "memory_operand" "m") ! 1640: (match_operand:QI 2 "general_operand" "g")))] ! 1641: "" ! 1642: "* ! 1643: { ! 1644: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 4)); ! 1645: if (GET_CODE(operands[1]) == MEM ! 1646: && CONSTANT_ADDRESS_P (XEXP(operands[1], 0)) ! 1647: && INTVAL (operands[2]) < 64) ! 1648: return \"callf %2,%1\"; /* this is much faster */ ! 1649: return \"calls %2,%1\"; ! 1650: }") ! 1651: ! 1652: ! 1653: (define_insn "return" ! 1654: [(return)] ! 1655: "" ! 1656: "ret") ! 1657: ! 1658: (define_insn "nop" ! 1659: [(const_int 0)] ! 1660: "" ! 1661: "nop") ! 1662: ! 1663: ; casesi this code extracted from the vax code. The instructions are ! 1664: ; very similar. Tahoe requires that the table be word aligned. GCC ! 1665: ; places the table immediately after, thus the alignment directive. ! 1666: ! 1667: (define_insn "casesi" ! 1668: [(set (pc) ! 1669: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g") ! 1670: (match_operand:SI 1 "general_operand" "g")) ! 1671: (match_operand:SI 2 "general_operand" "g")) ! 1672: (plus:SI (sign_extend:SI ! 1673: (mem:HI (plus:SI (pc) ! 1674: (minus:SI (match_dup 0) ! 1675: (match_dup 1))))) ! 1676: (label_ref:SI (match_operand 3 "" ""))) ! 1677: (pc)))] ! 1678: "" ! 1679: "casel %0,%1,%2\;.align %@") ! 1680: ! 1681: ! 1682: (define_insn "jump" ! 1683: [(set (pc) ! 1684: (label_ref (match_operand 0 "" "")))] ! 1685: "" ! 1686: "jbr %l0") ! 1687: ! 1688: ! 1689: ;; This is the list of all the non-standard insn patterns ! 1690: ! 1691: ! 1692: ; This is used to access the address of a byte. This is similar to ! 1693: ; movqi, but the second operand had to be "address_operand" type, so ! 1694: ; it had to be an unnamed one. ! 1695: ! 1696: (define_insn "" ! 1697: [(set (match_operand:SI 0 "general_operand" "=g") ! 1698: (match_operand:QI 1 "address_operand" "p"))] ! 1699: "" ! 1700: "* ! 1701: { ! 1702: if (push_operand (operands[0], SImode)) ! 1703: return \"pushab %a1\"; ! 1704: return \"movab %a1,%0\"; ! 1705: }") ! 1706: ! 1707: ; This is used to access the address of a word. This is similar to ! 1708: ; movhi, but the second operand had to be "address_operand" type, so ! 1709: ; it had to be an unnamed one. ! 1710: ! 1711: (define_insn "" ! 1712: [(set (match_operand:SI 0 "general_operand" "=g") ! 1713: (match_operand:HI 1 "address_operand" "p"))] ! 1714: "" ! 1715: "* ! 1716: { ! 1717: if (push_operand (operands[0], SImode)) ! 1718: return \"pushaw %a1\"; ! 1719: return \"movaw %a1,%0\"; ! 1720: }") ! 1721: ! 1722: ; This is used to access the address of a long. This is similar to ! 1723: ; movsi, but the second operand had to be "address_operand" type, so ! 1724: ; it had to be an unnamed one. ! 1725: ! 1726: (define_insn "" ! 1727: [(set (match_operand:SI 0 "general_operand" "=g") ! 1728: (match_operand:SI 1 "address_operand" "p"))] ! 1729: "" ! 1730: "* ! 1731: { ! 1732: if (push_operand (operands[0], SImode)) ! 1733: return \"pushal %a1\"; ! 1734: return \"moval %a1,%0\"; ! 1735: }") ! 1736: ! 1737: ! 1738: ; bit test longword instruction, same as vax ! 1739: ! 1740: (define_insn "" ! 1741: [(set (cc0) ! 1742: (and:SI (match_operand:SI 0 "general_operand" "g") ! 1743: (match_operand:SI 1 "general_operand" "g")))] ! 1744: "" ! 1745: "bitl %0,%1") ! 1746: ! 1747: ! 1748: ; bit test word instructions, same as vax ! 1749: ! 1750: (define_insn "" ! 1751: [(set (cc0) ! 1752: (and:HI (match_operand:HI 0 "general_operand" "g") ! 1753: (match_operand:HI 1 "general_operand" "g")))] ! 1754: "" ! 1755: "bitw %0,%1") ! 1756: ! 1757: ! 1758: ; bit test instructions, same as vax ! 1759: ! 1760: (define_insn "" ! 1761: [(set (cc0) ! 1762: (and:QI (match_operand:QI 0 "general_operand" "g") ! 1763: (match_operand:QI 1 "general_operand" "g")))] ! 1764: "" ! 1765: "bitb %0,%1") ! 1766: ! 1767: ! 1768: ; bne counterpart. in case gcc reverses the conditional. ! 1769: ! 1770: (define_insn "" ! 1771: [(set (pc) ! 1772: (if_then_else (eq (cc0) ! 1773: (const_int 0)) ! 1774: (pc) ! 1775: (label_ref (match_operand 0 "" ""))))] ! 1776: "" ! 1777: "jneq %l0") ! 1778: ! 1779: ! 1780: ; beq counterpart. in case gcc reverses the conditional. ! 1781: ! 1782: (define_insn "" ! 1783: [(set (pc) ! 1784: (if_then_else (ne (cc0) ! 1785: (const_int 0)) ! 1786: (pc) ! 1787: (label_ref (match_operand 0 "" ""))))] ! 1788: "" ! 1789: "jeql %l0") ! 1790: ! 1791: ! 1792: ; ble counterpart. in case gcc reverses the conditional. ! 1793: ! 1794: (define_insn "" ! 1795: [(set (pc) ! 1796: (if_then_else (gt (cc0) ! 1797: (const_int 0)) ! 1798: (pc) ! 1799: (label_ref (match_operand 0 "" ""))))] ! 1800: "" ! 1801: "jleq %l0") ! 1802: ! 1803: ! 1804: ; bleu counterpart. in case gcc reverses the conditional. ! 1805: ! 1806: (define_insn "" ! 1807: [(set (pc) ! 1808: (if_then_else (gtu (cc0) ! 1809: (const_int 0)) ! 1810: (pc) ! 1811: (label_ref (match_operand 0 "" ""))))] ! 1812: "" ! 1813: "jlequ %l0") ! 1814: ! 1815: ! 1816: ; bge counterpart. in case gcc reverses the conditional. ! 1817: ! 1818: (define_insn "" ! 1819: [(set (pc) ! 1820: (if_then_else (lt (cc0) ! 1821: (const_int 0)) ! 1822: (pc) ! 1823: (label_ref (match_operand 0 "" ""))))] ! 1824: "" ! 1825: "jgeq %l0") ! 1826: ! 1827: ! 1828: ; bgeu counterpart. in case gcc reverses the conditional. ! 1829: ! 1830: (define_insn "" ! 1831: [(set (pc) ! 1832: (if_then_else (ltu (cc0) ! 1833: (const_int 0)) ! 1834: (pc) ! 1835: (label_ref (match_operand 0 "" ""))))] ! 1836: "" ! 1837: "jgequ %l0") ! 1838: ! 1839: ! 1840: ; blt counterpart. in case gcc reverses the conditional. ! 1841: ! 1842: (define_insn "" ! 1843: [(set (pc) ! 1844: (if_then_else (ge (cc0) ! 1845: (const_int 0)) ! 1846: (pc) ! 1847: (label_ref (match_operand 0 "" ""))))] ! 1848: "" ! 1849: "jlss %l0") ! 1850: ! 1851: ! 1852: ; bltu counterpart. in case gcc reverses the conditional. ! 1853: ! 1854: (define_insn "" ! 1855: [(set (pc) ! 1856: (if_then_else (geu (cc0) ! 1857: (const_int 0)) ! 1858: (pc) ! 1859: (label_ref (match_operand 0 "" ""))))] ! 1860: "" ! 1861: "jlssu %l0") ! 1862: ! 1863: ! 1864: ; bgt counterpart. in case gcc reverses the conditional. ! 1865: ! 1866: (define_insn "" ! 1867: [(set (pc) ! 1868: (if_then_else (le (cc0) ! 1869: (const_int 0)) ! 1870: (pc) ! 1871: (label_ref (match_operand 0 "" ""))))] ! 1872: "" ! 1873: "jgtr %l0") ! 1874: ! 1875: ! 1876: ; bgtu counterpart. in case gcc reverses the conditional. ! 1877: ! 1878: (define_insn "" ! 1879: [(set (pc) ! 1880: (if_then_else (leu (cc0) ! 1881: (const_int 0)) ! 1882: (pc) ! 1883: (label_ref (match_operand 0 "" ""))))] ! 1884: "" ! 1885: "jgtru %l0") ! 1886: ! 1887: ! 1888: ; casesi alternate form as found in vax code. this form is to ! 1889: ; compensate for the table's offset being no distance (0 displacement) ! 1890: ! 1891: (define_insn "" ! 1892: [(set (pc) ! 1893: (if_then_else (le (match_operand:SI 0 "general_operand" "g") ! 1894: (match_operand:SI 1 "general_operand" "g")) ! 1895: (plus:SI (sign_extend:SI ! 1896: (mem:HI (plus:SI (pc) ! 1897: (minus:SI (match_dup 0) ! 1898: (const_int 0))))) ! 1899: (label_ref:SI (match_operand 3 "" ""))) ! 1900: (pc)))] ! 1901: "" ! 1902: "casel %0,$0,%1\;.align %@") ! 1903: ! 1904: ! 1905: ; casesi alternate form as found in vax code. another form to ! 1906: ; compensate for the table's offset being no distance (0 displacement) ! 1907: ! 1908: (define_insn "" ! 1909: [(set (pc) ! 1910: (if_then_else (le (match_operand:SI 0 "general_operand" "g") ! 1911: (match_operand:SI 1 "general_operand" "g")) ! 1912: (plus:SI (sign_extend:SI ! 1913: (mem:HI (plus:SI (pc) ! 1914: (match_dup 0)))) ! 1915: (label_ref:SI (match_operand 3 "" ""))) ! 1916: (pc)))] ! 1917: "" ! 1918: "casel %0,$0,%1 \;.align %@") ! 1919: ! 1920: (define_insn "" ! 1921: [(set (pc) ! 1922: (if_then_else ! 1923: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1924: (const_int 1)) ! 1925: (match_operand:SI 1 "general_operand" "g")) ! 1926: (label_ref (match_operand 2 "" "")) ! 1927: (pc))) ! 1928: (set (match_dup 0) ! 1929: (plus:SI (match_dup 0) ! 1930: (const_int 1)))] ! 1931: "" ! 1932: "aoblss %1,%0,%l2") ! 1933: ! 1934: (define_insn "" ! 1935: [(set (pc) ! 1936: (if_then_else ! 1937: (le (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1938: (const_int 1)) ! 1939: (match_operand:SI 1 "general_operand" "g")) ! 1940: (label_ref (match_operand 2 "" "")) ! 1941: (pc))) ! 1942: (set (match_dup 0) ! 1943: (plus:SI (match_dup 0) ! 1944: (const_int 1)))] ! 1945: "" ! 1946: "aobleq %1,%0,%l2") ! 1947: ! 1948: (define_insn "" ! 1949: [(set (pc) ! 1950: (if_then_else ! 1951: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1952: (const_int 1)) ! 1953: (match_operand:SI 1 "general_operand" "g")) ! 1954: (pc) ! 1955: (label_ref (match_operand 2 "" "")))) ! 1956: (set (match_dup 0) ! 1957: (plus:SI (match_dup 0) ! 1958: (const_int 1)))] ! 1959: "" ! 1960: "aoblss %1,%0,%l2") ! 1961: ! 1962: (define_insn "" ! 1963: [(set (pc) ! 1964: (if_then_else ! 1965: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1966: (const_int 1)) ! 1967: (match_operand:SI 1 "general_operand" "g")) ! 1968: (pc) ! 1969: (label_ref (match_operand 2 "" "")))) ! 1970: (set (match_dup 0) ! 1971: (plus:SI (match_dup 0) ! 1972: (const_int 1)))] ! 1973: "" ! 1974: "aobleq %1,%0,%l2") ! 1975: ! 1976: ; bbs/bbc ! 1977: ! 1978: (define_insn "" ! 1979: [(set (pc) ! 1980: (if_then_else ! 1981: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 1982: (const_int 1) ! 1983: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) ! 1984: (const_int 0)) ! 1985: (label_ref (match_operand 2 "" "")) ! 1986: (pc)))] ! 1987: "" ! 1988: "bbs %1,%0,%l2") ! 1989: ! 1990: (define_insn "" ! 1991: [(set (pc) ! 1992: (if_then_else ! 1993: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 1994: (const_int 1) ! 1995: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) ! 1996: (const_int 0)) ! 1997: (label_ref (match_operand 2 "" "")) ! 1998: (pc)))] ! 1999: "" ! 2000: "bbc %1,%0,%l2") ! 2001: ! 2002: (define_insn "" ! 2003: [(set (pc) ! 2004: (if_then_else ! 2005: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2006: (const_int 1) ! 2007: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) ! 2008: (const_int 0)) ! 2009: (pc) ! 2010: (label_ref (match_operand 2 "" ""))))] ! 2011: "" ! 2012: "bbc %1,%0,%l2") ! 2013: ! 2014: (define_insn "" ! 2015: [(set (pc) ! 2016: (if_then_else ! 2017: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2018: (const_int 1) ! 2019: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) ! 2020: (const_int 0)) ! 2021: (pc) ! 2022: (label_ref (match_operand 2 "" ""))))] ! 2023: "" ! 2024: "bbs %1,%0,%l2") ! 2025: ! 2026: ; if the shift count is a byte in a register we can use it as a long ! 2027: ! 2028: (define_insn "" ! 2029: [(set (pc) ! 2030: (if_then_else ! 2031: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2032: (const_int 1) ! 2033: (match_operand:QI 1 "register_operand" "r")) ! 2034: (const_int 0)) ! 2035: (label_ref (match_operand 2 "" "")) ! 2036: (pc)))] ! 2037: "" ! 2038: "bbs %1,%0,%l2") ! 2039: ! 2040: (define_insn "" ! 2041: [(set (pc) ! 2042: (if_then_else ! 2043: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2044: (const_int 1) ! 2045: (match_operand:QI 1 "register_operand" "r")) ! 2046: (const_int 0)) ! 2047: (label_ref (match_operand 2 "" "")) ! 2048: (pc)))] ! 2049: "" ! 2050: "bbc %1,%0,%l2") ! 2051: ! 2052: (define_insn "" ! 2053: [(set (pc) ! 2054: (if_then_else ! 2055: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2056: (const_int 1) ! 2057: (match_operand:QI 1 "register_operand" "r")) ! 2058: (const_int 0)) ! 2059: (pc) ! 2060: (label_ref (match_operand 2 "" ""))))] ! 2061: "" ! 2062: "bbc %1,%0,%l2") ! 2063: ! 2064: (define_insn "" ! 2065: [(set (pc) ! 2066: (if_then_else ! 2067: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") ! 2068: (const_int 1) ! 2069: (match_operand:QI 1 "register_operand" "r")) ! 2070: (const_int 0)) ! 2071: (pc) ! 2072: (label_ref (match_operand 2 "" ""))))] ! 2073: "" ! 2074: "bbs %1,%0,%l2") ! 2075: ! 2076: ; special case for 1 << constant. We don't do these because they are slower ! 2077: ; than the bitl instruction ! 2078: ! 2079: ;(define_insn "" ! 2080: ; [(set (pc) ! 2081: ; (if_then_else ! 2082: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") ! 2083: ; (match_operand:SI 1 "immediate_operand" "i")) ! 2084: ; (const_int 0)) ! 2085: ; (label_ref (match_operand 2 "" "")) ! 2086: ; (pc)))] ! 2087: ; "GET_CODE (operands[1]) == CONST_INT ! 2088: ; && exact_log2 (INTVAL (operands[1])) >= 0" ! 2089: ; "* ! 2090: ;{ ! 2091: ; operands[1] ! 2092: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 2093: ; return \"bbs %1,%0,%l2\"; ! 2094: ;}") ! 2095: ; ! 2096: ;(define_insn "" ! 2097: ; [(set (pc) ! 2098: ; (if_then_else ! 2099: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") ! 2100: ; (match_operand:SI 1 "immediate_operand" "i")) ! 2101: ; (const_int 0)) ! 2102: ; (label_ref (match_operand 2 "" "")) ! 2103: ; (pc)))] ! 2104: ; "GET_CODE (operands[1]) == CONST_INT ! 2105: ; && exact_log2 (INTVAL (operands[1])) >= 0" ! 2106: ; "* ! 2107: ;{ ! 2108: ; operands[1] ! 2109: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 2110: ; return \"bbc %1,%0,%l2\"; ! 2111: ;}") ! 2112: ; ! 2113: ;(define_insn "" ! 2114: ; [(set (pc) ! 2115: ; (if_then_else ! 2116: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") ! 2117: ; (match_operand:SI 1 "immediate_operand" "i")) ! 2118: ; (const_int 0)) ! 2119: ; (pc) ! 2120: ; (label_ref (match_operand 2 "" ""))))] ! 2121: ; "GET_CODE (operands[1]) == CONST_INT ! 2122: ; && exact_log2 (INTVAL (operands[1])) >= 0" ! 2123: ; "* ! 2124: ;{ ! 2125: ; operands[1] ! 2126: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 2127: ; return \"bbc %1,%0,%l2\"; ! 2128: ;}") ! 2129: ; ! 2130: ;(define_insn "" ! 2131: ; [(set (pc) ! 2132: ; (if_then_else ! 2133: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") ! 2134: ; (match_operand:SI 1 "immediate_operand" "i")) ! 2135: ; (const_int 0)) ! 2136: ; (pc) ! 2137: ; (label_ref (match_operand 2 "" ""))))] ! 2138: ; "GET_CODE (operands[1]) == CONST_INT ! 2139: ; && exact_log2 (INTVAL (operands[1])) >= 0" ! 2140: ; "* ! 2141: ;{ ! 2142: ; operands[1] ! 2143: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 2144: ; return \"bbs %1,%0,%l2\"; ! 2145: ;}") ! 2146: ! 2147: ! 2148: ;;- Local variables: ! 2149: ;;- mode:emacs-lisp ! 2150: ;;- comment-start: ";;- " ! 2151: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2152: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2153: ;;- eval: (modify-syntax-entry ?] ")[") ! 2154: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2155: ;;- eval: (modify-syntax-entry ?} "){") ! 2156: ;;- End:
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