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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Tahoe version
3: ;; Copyright (C) 1989 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ; File: tahoe.md
23: ;
24: ; This port made at the University of Buffalo by Devon Bowen,
25: ; Dale Wiles and Kevin Zachmann.
26: ;
27: ; Mail bugs reports or fixes to: [email protected]
28:
29:
30: ; movdi must call the output_move_double routine to move it around since
31: ; the tahoe doesn't efficiently support 8 bit moves.
32:
33: (define_insn "movdi"
34: [(set (match_operand:DI 0 "general_operand" "=g")
35: (match_operand:DI 1 "general_operand" "g"))]
36: ""
37: "*
38: {
39: CC_STATUS_INIT;
40: return output_move_double (operands);
41: }")
42:
43:
44: ; The trick in the movsi is accessing the contents of the sp register. The
45: ; tahoe doesn't allow you to access it directly so you have to access the
46: ; address of the top of the stack instead.
47:
48: (define_insn "movsi"
49: [(set (match_operand:SI 0 "general_operand" "=g")
50: (match_operand:SI 1 "general_operand" "g"))]
51: ""
52: "*
53: {
54: rtx link;
55: if (operands[1] == const1_rtx
56: && (link = find_reg_note (insn, REG_WAS_0, 0))
57: && ! XEXP (link, 0)->volatil
58: && GET_CODE (XEXP (link, 0)) != NOTE
59: && no_labels_between_p (XEXP (link, 0), insn))
60: return \"incl %0\";
61: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
62: {
63: if (push_operand (operands[0], SImode))
64: return \"pushab %a1\";
65: return \"movab %a1,%0\";
66: }
67: if (operands[1] == const0_rtx)
68: return \"clrl %0\";
69: if (push_operand (operands[0], SImode))
70: return \"pushl %1\";
71: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 14)
72: return \"moval (sp),%0\";
73: return \"movl %1,%0\";
74: }")
75:
76:
77: (define_insn "movhi"
78: [(set (match_operand:HI 0 "general_operand" "=g")
79: (match_operand:HI 1 "general_operand" "g"))]
80: ""
81: "*
82: {
83: rtx link;
84: if (operands[1] == const1_rtx
85: && (link = find_reg_note (insn, REG_WAS_0, 0))
86: && ! XEXP (link, 0)->volatil
87: && GET_CODE (XEXP (link, 0)) != NOTE
88: && no_labels_between_p (XEXP (link, 0), insn))
89: return \"incw %0\";
90: if (operands[1] == const0_rtx)
91: return \"clrw %0\";
92: return \"movw %1,%0\";
93: }")
94:
95:
96: (define_insn "movqi"
97: [(set (match_operand:QI 0 "general_operand" "=g")
98: (match_operand:QI 1 "general_operand" "g"))]
99: ""
100: "*
101: {
102: if (operands[1] == const0_rtx)
103: return \"clrb %0\";
104: return \"movb %1,%0\";
105: }")
106:
107:
108: ; movsf has three cases since they can move from one place to another
109: ; or to/from the fpp and since different instructions are needed for
110: ; each case. The fpp related instructions don't set the flags properly.
111:
112: (define_insn "movsf"
113: [(set (match_operand:SF 0 "general_operand" "=g,=a,=g")
114: (match_operand:SF 1 "general_operand" "g,g,a"))]
115: ""
116: "*
117: {
118: CC_STATUS_INIT;
119: switch (which_alternative)
120: {
121: case 0:
122: return \"movl %1,%0\";
123: case 1:
124: return \"ldf %1\";
125: case 2:
126: return \"stf %0\";
127: }
128: }")
129:
130:
131: ; movdf has a number of different cases. If it's going to or from
132: ; the fpp, use the special instructions to do it. If not, use the
133: ; output_move_double function.
134:
135: (define_insn "movdf"
136: [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g")
137: (match_operand:DF 1 "general_operand" "g,a,g"))]
138: ""
139: "*
140: {
141: CC_STATUS_INIT;
142: switch (which_alternative)
143: {
144: case 0:
145: return \"ldd %1\";
146: case 1:
147: if (push_operand (operands[0], DFmode))
148: return \"pushd\";
149: else
150: return \"std %0\";
151: case 2:
152: return output_move_double (operands);
153: }
154: }")
155:
156:
157: (define_insn "addsi3"
158: [(set (match_operand:SI 0 "general_operand" "=g")
159: (plus:SI (match_operand:SI 1 "general_operand" "g")
160: (match_operand:SI 2 "general_operand" "g")))]
161: ""
162: "*
163: {
164: if (rtx_equal_p (operands[0], operands[1]))
165: {
166: if (operands[2] == const1_rtx)
167: return \"incl %0\";
168: if (GET_CODE (operands[2]) == CONST_INT
169: && INTVAL (operands[2]) == -1)
170: return \"decl %0\";
171: if (GET_CODE (operands[2]) == CONST_INT
172: && (unsigned) (- INTVAL (operands[2])) < 64)
173: return \"subl2 $%n2,%0\";
174: return \"addl2 %2,%0\";
175: }
176: if (rtx_equal_p (operands[0], operands[2]))
177: return \"addl2 %1,%0\";
178: if (GET_CODE (operands[2]) == CONST_INT
179: && GET_CODE (operands[1]) == REG)
180: {
181: if (push_operand (operands[0], SImode))
182: return \"pushab %c2(%1)\";
183: return \"movab %c2(%1),%0\";
184: }
185: if (GET_CODE (operands[2]) == CONST_INT
186: && (unsigned) (- INTVAL (operands[2])) < 64)
187: return \"subl3 $%n2,%1,%0\";
188: return \"addl3 %1,%2,%0\";
189: }")
190:
191:
192: (define_insn "addhi3"
193: [(set (match_operand:HI 0 "general_operand" "=g")
194: (plus:HI (match_operand:HI 1 "general_operand" "g")
195: (match_operand:HI 2 "general_operand" "g")))]
196: ""
197: "*
198: {
199: if (rtx_equal_p (operands[0], operands[1]))
200: {
201: if (operands[2] == const1_rtx)
202: return \"incw %0\";
203: if (GET_CODE (operands[1]) == CONST_INT
204: && INTVAL (operands[1]) == -1)
205: return \"decw %0\";
206: if (GET_CODE (operands[2]) == CONST_INT
207: && (unsigned) (- INTVAL (operands[2])) < 64)
208: return \"subw2 $%n2,%0\";
209: return \"addw2 %2,%0\";
210: }
211: if (rtx_equal_p (operands[0], operands[2]))
212: return \"addw2 %1,%0\";
213: if (GET_CODE (operands[2]) == CONST_INT
214: && (unsigned) (- INTVAL (operands[2])) < 64)
215: return \"subw3 $%n2,%1,%0\";
216: return \"addw3 %1,%2,%0\";
217: }")
218:
219:
220: (define_insn "addqi3"
221: [(set (match_operand:QI 0 "general_operand" "=g")
222: (plus:QI (match_operand:QI 1 "general_operand" "g")
223: (match_operand:QI 2 "general_operand" "g")))]
224: ""
225: "*
226: {
227: if (rtx_equal_p (operands[0], operands[1]))
228: {
229: if (operands[2] == const1_rtx)
230: return \"incb %0\";
231: if (GET_CODE (operands[1]) == CONST_INT
232: && INTVAL (operands[1]) == -1)
233: return \"decb %0\";
234: if (GET_CODE (operands[2]) == CONST_INT
235: && (unsigned) (- INTVAL (operands[2])) < 64)
236: return \"subb2 $%n2,%0\";
237: return \"addb2 %2,%0\";
238: }
239: if (rtx_equal_p (operands[0], operands[2]))
240: return \"addb2 %1,%0\";
241: if (GET_CODE (operands[2]) == CONST_INT
242: && (unsigned) (- INTVAL (operands[2])) < 64)
243: return \"subb3 $%n2,%1,%0\";
244: return \"addb3 %1,%2,%0\";
245: }")
246:
247:
248: ; addsf3 can only add into the fpp register since the fpp is treated
249: ; as a separate unit in the machine. It also doesn't set the flags at
250: ; all.
251:
252: (define_insn "addsf3"
253: [(set (match_operand:SF 0 "register_operand" "=a")
254: (plus:SF (match_operand:SF 1 "register_operand" "%0")
255: (match_operand:SF 2 "general_operand" "g")))]
256: ""
257: "*
258: {
259: CC_STATUS_INIT;
260: return \"addf %2\";
261: }")
262:
263:
264: ; adddf3 can only add into the fpp reg since the fpp is treated as a
265: ; separate entity. Doubles can only be read from a register or memory
266: ; since a double is not an immediate mode. Flags are not set by this
267: ; instruction.
268:
269: (define_insn "adddf3"
270: [(set (match_operand:DF 0 "register_operand" "=a")
271: (plus:DF (match_operand:DF 1 "register_operand" "%0")
272: (match_operand:DF 2 "general_operand" "rm")))]
273: ""
274: "*
275: {
276: CC_STATUS_INIT;
277: return \"addd %2\";
278: }")
279:
280:
281: ; Subtraction from the sp (needed by the built in alloc funtion) needs
282: ; to be different since the sp cannot be directly read on the tahoe.
283: ; If it's a simple constant, you just use displacment. Otherwise, you
284: ; push the sp, and then do the subtraction off the stack.
285:
286: (define_insn "subsi3"
287: [(set (match_operand:SI 0 "general_operand" "=g")
288: (minus:SI (match_operand:SI 1 "general_operand" "g")
289: (match_operand:SI 2 "general_operand" "g")))]
290: ""
291: "*
292: {
293: if (rtx_equal_p (operands[0], operands[1]))
294: {
295: if (operands[2] == const1_rtx)
296: return \"decl %0\";
297: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 14)
298: if (GET_CODE (operands[2]) == CONST_INT)
299: return \"movab %n2(sp),sp\";
300: else
301: return \"pushab (sp)\;subl3 %2,(sp),sp\";
302: return \"subl2 %2,%0\";
303: }
304: if (rtx_equal_p (operands[1], operands[2]))
305: return \"clrl %0\";
306: return \"subl3 %2,%1,%0\";
307: }")
308:
309:
310: (define_insn "subhi3"
311: [(set (match_operand:HI 0 "general_operand" "=g")
312: (minus:HI (match_operand:HI 1 "general_operand" "g")
313: (match_operand:HI 2 "general_operand" "g")))]
314: ""
315: "*
316: {
317: if (rtx_equal_p (operands[0], operands[1]))
318: {
319: if (operands[2] == const1_rtx)
320: return \"decw %0\";
321: return \"subw2 %2,%0\";
322: }
323: if (rtx_equal_p (operands[1], operands[2]))
324: return \"clrw %0\";
325: return \"subw3 %2,%1,%0\";
326: }")
327:
328:
329: (define_insn "subqi3"
330: [(set (match_operand:QI 0 "general_operand" "=g")
331: (minus:QI (match_operand:QI 1 "general_operand" "g")
332: (match_operand:QI 2 "general_operand" "g")))]
333: ""
334: "*
335: {
336: if (rtx_equal_p (operands[0], operands[1]))
337: {
338: if (operands[2] == const1_rtx)
339: return \"decb %0\";
340: return \"subb2 %2,%0\";
341: }
342: if (rtx_equal_p (operands[1], operands[2]))
343: return \"clrb %0\";
344: return \"subb3 %2,%1,%0\";
345: }")
346:
347:
348: ; subsf3 can only subtract into the fpp accumulator due to the way
349: ; the fpp reg is limited by the instruction set. This also doesn't
350: ; bother setting up flags.
351:
352: (define_insn "subsf3"
353: [(set (match_operand:SF 0 "register_operand" "=a")
354: (minus:SF (match_operand:SF 1 "register_operand" "0")
355: (match_operand:SF 2 "general_operand" "g")))]
356: ""
357: "*
358: {
359: CC_STATUS_INIT;
360: return \"subf %2\";
361: }")
362:
363:
364: ; subdf3 is set up to subtract into the fpp reg due to limitations
365: ; of the fpp instruction set. Doubles can not be immediate. This
366: ; instruction does not set the flags.
367:
368: (define_insn "subdf3"
369: [(set (match_operand:DF 0 "register_operand" "=a")
370: (minus:DF (match_operand:DF 1 "register_operand" "0")
371: (match_operand:DF 2 "general_operand" "rm")))]
372: ""
373: "*
374: {
375: CC_STATUS_INIT;
376: return \"subd %2\";
377: }")
378:
379:
380: (define_insn "mulsi3"
381: [(set (match_operand:SI 0 "general_operand" "=g")
382: (mult:SI (match_operand:SI 1 "general_operand" "g")
383: (match_operand:SI 2 "general_operand" "g")))]
384: ""
385: "*
386: {
387: if (rtx_equal_p (operands[0], operands[1]))
388: return \"mull2 %2,%0\";
389: if (rtx_equal_p (operands[0], operands[2]))
390: return \"mull2 %1,%0\";
391: return \"mull3 %1,%2,%0\";
392: }")
393:
394:
395: ; mulsf3 can only multiply into the fpp accumulator due to limitations
396: ; of the fpp. It also does not set the condition codes properly.
397:
398: (define_insn "mulsf3"
399: [(set (match_operand:SF 0 "register_operand" "=a")
400: (mult:SF (match_operand:SF 1 "register_operand" "%0")
401: (match_operand:SF 2 "general_operand" "g")))]
402: ""
403: "*
404: {
405: CC_STATUS_INIT;
406: return \"mulf %2\";
407: }")
408:
409:
410: ; muldf3 can only multiply into the fpp reg since the fpp is limited
411: ; from the rest. Doubles may not be immediate mode. This does not set
412: ; the flags like GCC would expect.
413:
414: (define_insn "muldf3"
415: [(set (match_operand:DF 0 "register_operand" "=a")
416: (mult:DF (match_operand:DF 1 "register_operand" "%0")
417: (match_operand:DF 2 "general_operand" "rm")))]
418: ""
419: "*
420: {
421: CC_STATUS_INIT;
422: return \"muld %2\";
423: }")
424:
425:
426: (define_insn "divsi3"
427: [(set (match_operand:SI 0 "general_operand" "=g")
428: (div:SI (match_operand:SI 1 "general_operand" "g")
429: (match_operand:SI 2 "general_operand" "g")))]
430: ""
431: "*
432: {
433: if (rtx_equal_p (operands[1], operands[2]))
434: return \"movl $1,%0\";
435: if (operands[1] == const0_rtx)
436: return \"clrl %0\";
437: if (GET_CODE (operands[2]) == CONST_INT
438: && INTVAL (operands[2]) == -1)
439: return \"mnegl %1,%0\";
440: if (rtx_equal_p (operands[0], operands[1]))
441: return \"divl2 %2,%0\";
442: return \"divl3 %2,%1,%0\";
443: }")
444:
445:
446: ; divsf3 must divide into the fpp accumulator. Flags are not set by
447: ; this instruction, so they are cleared.
448:
449: (define_insn "divsf3"
450: [(set (match_operand:SF 0 "register_operand" "=a")
451: (div:SF (match_operand:SF 1 "register_operand" "0")
452: (match_operand:SF 2 "general_operand" "g")))]
453: ""
454: "*
455: {
456: CC_STATUS_INIT;
457: return \"divf %2\";
458: }")
459:
460:
461: ; divdf3 also must divide into the fpp reg so optimization isn't
462: ; possible. Note that doubles cannot be immediate. The flags here
463: ; are not set correctly so they must be ignored.
464:
465: (define_insn "divdf3"
466: [(set (match_operand:DF 0 "register_operand" "=a")
467: (div:DF (match_operand:DF 1 "register_operand" "0")
468: (match_operand:DF 2 "general_operand" "rm")))]
469: ""
470: "*
471: {
472: CC_STATUS_INIT;
473: return \"divd %2\";
474: }")
475:
476:
477: (define_insn "andsi3"
478: [(set (match_operand:SI 0 "general_operand" "=g")
479: (and:SI (match_operand:SI 1 "general_operand" "g")
480: (match_operand:SI 2 "general_operand" "g")))]
481: ""
482: "andl3 %2,%1,%0")
483:
484:
485: (define_insn "andhi3"
486: [(set (match_operand:HI 0 "general_operand" "=g")
487: (and:HI (match_operand:HI 1 "general_operand" "g")
488: (match_operand:HI 2 "general_operand" "g")))]
489: ""
490: "andw3 %1,%2,%0")
491:
492:
493: (define_insn "andqi3"
494: [(set (match_operand:QI 0 "general_operand" "=g")
495: (and:QI (match_operand:QI 1 "general_operand" "g")
496: (match_operand:QI 2 "general_operand" "g")))]
497: ""
498: "andb3 %1,%2,%0")
499:
500:
501: (define_insn "iorsi3"
502: [(set (match_operand:SI 0 "general_operand" "=g")
503: (ior:SI (match_operand:SI 1 "general_operand" "g")
504: (match_operand:SI 2 "general_operand" "g")))]
505: ""
506: "orl3 %2,%1,%0")
507:
508:
509: (define_insn "iorhi3"
510: [(set (match_operand:HI 0 "general_operand" "=g")
511: (ior:HI (match_operand:HI 1 "general_operand" "g")
512: (match_operand:HI 2 "general_operand" "g")))]
513: ""
514: "orw3 %2,%1,%0")
515:
516:
517: (define_insn "iorqi3"
518: [(set (match_operand:QI 0 "general_operand" "=g")
519: (ior:QI (match_operand:QI 1 "general_operand" "g")
520: (match_operand:QI 2 "general_operand" "g")))]
521: ""
522: "orb3 %2,%1,%0")
523:
524:
525: (define_insn "xorsi3"
526: [(set (match_operand:SI 0 "general_operand" "=g")
527: (xor:SI (match_operand:SI 1 "general_operand" "g")
528: (match_operand:SI 2 "general_operand" "g")))]
529: ""
530: "xorl3 %1,%2,%0")
531:
532:
533: (define_insn "xorhi3"
534: [(set (match_operand:HI 0 "general_operand" "=g")
535: (xor:HI (match_operand:HI 1 "general_operand" "g")
536: (match_operand:HI 2 "general_operand" "g")))]
537: ""
538: "xorw3 %1,%2,%0")
539:
540:
541: (define_insn "xorqi3"
542: [(set (match_operand:QI 0 "general_operand" "=g")
543: (xor:QI (match_operand:QI 1 "general_operand" "g")
544: (match_operand:QI 2 "general_operand" "g")))]
545: ""
546: "xorb3 %1,%2,%0")
547:
548:
549: ; Shifts on the tahoe are expensive, so try to do an add instead.
550:
551: (define_insn "ashlsi3"
552: [(set (match_operand:SI 0 "general_operand" "=g")
553: (ashift:SI (match_operand:SI 1 "general_operand" "g")
554: (match_operand:QI 2 "general_operand" "g")))]
555: ""
556: "*
557: {
558: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
559: {
560: CC_STATUS_INIT;
561: return \"addl2 %0,%0\";
562: }
563: return \"shal %2,%1,%0\";
564: }")
565:
566:
567: (define_insn "ashrsi3"
568: [(set (match_operand:SI 0 "general_operand" "=g")
569: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
570: (match_operand:QI 2 "general_operand" "g")))]
571: ""
572: "shar %2,%1,%0")
573:
574:
575: ; Shifts are very expensive, so try to do an add if possible.
576:
577: (define_insn "lshlsi3"
578: [(set (match_operand:SI 0 "general_operand" "=g")
579: (lshift:SI (match_operand:SI 1 "general_operand" "g")
580: (match_operand:QI 2 "general_operand" "g")))]
581: ""
582: "*
583: {
584: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
585: {
586: CC_STATUS_INIT;
587: return \"addl2 %0,%0\";
588: }
589: return \"shll %2,%1,%0\";
590: }")
591:
592:
593: (define_insn "lshrsi3"
594: [(set (match_operand:SI 0 "general_operand" "=g")
595: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
596: (match_operand:QI 2 "general_operand" "g")))]
597: ""
598: "shrl %2,%1,%0")
599:
600:
601: (define_insn "negsi2"
602: [(set (match_operand:SI 0 "general_operand" "=g")
603: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
604: ""
605: "mnegl %1,%0")
606:
607:
608: (define_insn "neghi2"
609: [(set (match_operand:HI 0 "general_operand" "=g")
610: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
611: ""
612: "mnegw %1,%0")
613:
614:
615: (define_insn "negqi2"
616: [(set (match_operand:QI 0 "general_operand" "=g")
617: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
618: ""
619: "mnegb %1,%0")
620:
621:
622: ; negsf2 can only negate the value already in the fpp accumulator.
623: ; The value remains in the fpp accumulator. No flags are set.
624:
625: (define_insn "negsf2"
626: [(set (match_operand:SF 0 "register_operand" "=a,=a")
627: (neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
628: ""
629: "*
630: {
631: CC_STATUS_INIT;
632: switch (which_alternative)
633: {
634: case 0:
635: return \"negf\";
636: case 1:
637: return \"lnf %1\";
638: }
639: }")
640:
641:
642: ; negdf2 can only negate the value already in the fpp accumulator.
643: ; The value remains in the fpp accumulator. No flags are set.
644:
645: (define_insn "negdf2"
646: [(set (match_operand:DF 0 "register_operand" "=a,=a")
647: (neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
648: ""
649: "*
650: {
651: CC_STATUS_INIT;
652: switch (which_alternative)
653: {
654: case 0:
655: return \"negd\";
656: case 1:
657: return \"lnd %1\";
658: }
659: }")
660:
661:
662: ; sqrtsf2 tahoe can calculate the square root of a float in the
663: ; fpp accumulator. The answer remains in the fpp accumulator. No
664: ; flags are set by this function.
665:
666: (define_insn "sqrtsf2"
667: [(set (match_operand:SF 0 "register_operand" "=a")
668: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
669: ""
670: "*
671: {
672: CC_STATUS_INIT;
673: return \"sqrtf\";
674: }")
675:
676:
677: ; ffssi2 tahoe instruction gives one less than GCC desired result for
678: ; any given input. So the increment is necessary here.
679:
680: (define_insn "ffssi2"
681: [(set (match_operand:SI 0 "general_operand" "=g")
682: (ffs:SI (match_operand:SI 1 "general_operand" "g")))]
683: ""
684: "ffs %1,%0\;incl %0")
685:
686:
687: (define_insn "one_cmplsi2"
688: [(set (match_operand:SI 0 "general_operand" "=g")
689: (not:SI (match_operand:SI 1 "general_operand" "g")))]
690: ""
691: "mcoml %1,%0")
692:
693:
694: (define_insn "one_cmplhi2"
695: [(set (match_operand:HI 0 "general_operand" "=g")
696: (not:HI (match_operand:HI 1 "general_operand" "g")))]
697: ""
698: "mcomw %1,%0")
699:
700:
701: (define_insn "one_cmplqi2"
702: [(set (match_operand:QI 0 "general_operand" "=g")
703: (not:QI (match_operand:QI 1 "general_operand" "g")))]
704: ""
705: "mcomb %1,%0")
706:
707:
708: ; cmpsi works fine, but due to microcode problems, the tahoe doesn't
709: ; properly compare hi's and qi's. Leaving them out seems to be acceptable
710: ; to the compiler, so they were left out. Compares of the stack are
711: ; possible, though.
712:
713: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
714:
715: (define_insn "cmpsi"
716: [(set (cc0)
717: (compare (match_operand:SI 0 "general_operand" "g")
718: (match_operand:SI 1 "general_operand" "g")))]
719: ""
720: "cmpl %0,%1")
721:
722:
723: ; cmpsf similar to vax, but first operand is expected to be in the
724: ; fpp accumulator.
725:
726: (define_insn "cmpsf"
727: [(set (cc0)
728: (compare (match_operand:SF 0 "register_operand" "a")
729: (match_operand:SF 1 "general_operand" "g")))]
730: ""
731: "cmpf %1")
732:
733:
734: ; cmpdf similar to vax, but first operand is expected to be in the
735: ; fpp accumulator. Immediate doubles not allowed.
736:
737: (define_insn "cmpdf"
738: [(set (cc0)
739: (compare (match_operand:DF 0 "register_operand" "a")
740: (match_operand:DF 1 "general_operand" "rm")))]
741: ""
742: "cmpd %1")
743:
744:
745: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
746:
747: (define_insn "tstsi"
748: [(set (cc0)
749: (match_operand:SI 0 "general_operand" "g"))]
750: ""
751: "tstl %0")
752:
753:
754: ; Small tests from memory are normal, but testing from registers don't
755: ; expand the data properly. So test in this case does a convert and tests
756: ; the new register data from the stack.
757:
758: (define_insn "tsthi"
759: [(set (cc0)
760: (match_operand:HI 0 "general_operand" "m,?r"))]
761: ""
762: "*
763: {
764: switch (which_alternative)
765: {
766: case 0:
767: return \"tstw %0\";
768: case 1:
769: return \"pushl %0\;cvtwl 2(sp),(sp)\;tstl (sp)+\";
770: }
771: }")
772:
773:
774: ; Small tests from memory are normal, but testing from registers don't
775: ; expand the data properly. So test in this case does a convert and tests
776: ; the new register data from the stack.
777:
778: (define_insn "tstqi"
779: [(set (cc0)
780: (match_operand:QI 0 "general_operand" "m,?r"))]
781: ""
782: "*
783: {
784: switch (which_alternative)
785: {
786: case 0:
787: return \"tstb %0\";
788: case 1:
789: return \"pushl %0\;cvtbl 3(sp),(sp)\;tstl (sp)+\";
790: }
791: }")
792:
793:
794: ; tstsf compares a given value to a value already in the fpp accumulator.
795: ; No flags are set by this so ignore them.
796:
797: (define_insn "tstsf"
798: [(set (cc0)
799: (match_operand:SF 0 "register_operand" "a"))]
800: ""
801: "tstf")
802:
803:
804: ; tstdf compares a given value to a value already in the fpp accumulator.
805: ; immediate doubles not allowed. Flags are ignored after this.
806:
807: (define_insn "tstdf"
808: [(set (cc0)
809: (match_operand:DF 0 "register_operand" "a"))]
810: ""
811: "tstd")
812:
813:
814: ; movstrhi tahoe instruction does not load registers by itself like
815: ; the vax counterpart does. registers 0-2 must be primed by hand.
816: ; we have loaded the registers in the order: dst, src, count.
817:
818: (define_insn "movstrhi"
819: [(set (match_operand:BLK 0 "general_operand" "p")
820: (match_operand:BLK 1 "general_operand" "p"))
821: (use (match_operand:HI 2 "general_operand" "g"))
822: (clobber (reg:SI 0))
823: (clobber (reg:SI 1))
824: (clobber (reg:SI 2))]
825: ""
826: "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk")
827:
828:
829: ; floatsisf2 on tahoe converts the long from reg/mem into the fpp
830: ; accumulator. There are no hi and qi counterparts. Flags are not
831: ; set correctly here.
832:
833: (define_insn "floatsisf2"
834: [(set (match_operand:SF 0 "register_operand" "=a")
835: (float:SF (match_operand:SI 1 "general_operand" "g")))]
836: ""
837: "*
838: {
839: CC_STATUS_INIT;
840: return \"cvlf %1\";
841: }")
842:
843:
844: ; floatsidf2 on tahoe converts the long from reg/mem into the fpp
845: ; accumulator. There are no hi and qi counterparts. Flags are not
846: ; set correctly here.
847:
848: (define_insn "floatsidf2"
849: [(set (match_operand:DF 0 "register_operand" "=a")
850: (float:DF (match_operand:SI 1 "general_operand" "g")))]
851: ""
852: "*
853: {
854: CC_STATUS_INIT;
855: return \"cvld %1\";
856: }")
857:
858:
859: ; fix_truncsfsi2 to convert a float to long, tahoe must have the float
860: ; in the fpp accumulator. Flags are not set here.
861:
862: (define_insn "fix_truncsfsi2"
863: [(set (match_operand:SI 0 "general_operand" "=g")
864: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))]
865: ""
866: "*
867: {
868: CC_STATUS_INIT;
869: return \"cvfl %0\";
870: }")
871:
872:
873: ; fix_truncsfsi2 to convert a double to long, tahoe must have the double
874: ; in the fpp accumulator. Flags are not set here.
875:
876: (define_insn "fix_truncdfsi2"
877: [(set (match_operand:SI 0 "general_operand" "=g")
878: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))]
879: ""
880: "*
881: {
882: CC_STATUS_INIT;
883: return \"cvdl %0\";
884: }")
885:
886:
887: (define_insn "truncsihi2"
888: [(set (match_operand:HI 0 "general_operand" "=g")
889: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
890: ""
891: "cvtlw %1,%0")
892:
893:
894: (define_insn "truncsiqi2"
895: [(set (match_operand:QI 0 "general_operand" "=g")
896: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
897: ""
898: "cvtlb %1,%0")
899:
900:
901: (define_insn "trunchiqi2"
902: [(set (match_operand:QI 0 "general_operand" "=g")
903: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
904: ""
905: "cvtwb %1,%0")
906:
907:
908: ; The fpp related instructions don't set flags, so ignore them
909: ; after this instruction.
910:
911: (define_insn "truncdfsf2"
912: [(set (match_operand:SF 0 "register_operand" "=a")
913: (float_truncate:SF (match_operand:DF 1 "register_operand" "0")))]
914: ""
915: "*
916: {
917: CC_STATUS_INIT;
918: return \"cvdf\";
919: }")
920:
921:
922: ; This monster is to cover for the Tahoe's nasty habit of not extending
923: ; a number if the source is in a register. (It just moves it!) Case 0 is
924: ; a normal extend from memory. Case 1 does the extension from the top of
925: ; the stack. Extension from the stack doesn't set the flags right since
926: ; the moval changes them.
927:
928: (define_insn "extendhisi2"
929: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
930: (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
931: ""
932: "*
933: {
934: switch (which_alternative)
935: {
936: case 0:
937: return \"cvtwl %1,%0\";
938: case 1:
939: if (push_operand(operands[0], SImode))
940: return \"pushl %1\;cvtwl 2(sp),(sp)\";
941: else
942: {
943: CC_STATUS_INIT;
944: return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\";
945: }
946: }
947: }")
948:
949:
950: ; This monster is to cover for the Tahoe's nasty habit of not extending
951: ; a number if the source is in a register. (It just moves it!) Case 0 is
952: ; a normal extend from memory. Case 1 does the extension from the top of
953: ; the stack. Extension from the stack doesn't set the flags right since
954: ; the moval changes them.
955:
956: (define_insn "extendqisi2"
957: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
958: (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
959: ""
960: "*
961: {
962: switch (which_alternative)
963: {
964: case 0:
965: return \"cvtbl %1,%0\";
966: case 1:
967: if (push_operand(operands[0], SImode))
968: return \"pushl %1\;cvtbl 3(sp),(sp)\";
969: else
970: {
971: CC_STATUS_INIT;
972: return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\";
973: }
974: }
975: }")
976:
977:
978: ; This monster is to cover for the Tahoe's nasty habit of not extending
979: ; a number if the source is in a register. (It just moves it!) Case 0 is
980: ; a normal extend from memory. Case 1 does the extension from the top of
981: ; the stack. Extension from the stack doesn't set the flags right since
982: ; the moval changes them.
983:
984: (define_insn "extendqihi2"
985: [(set (match_operand:HI 0 "general_operand" "=g,?=g")
986: (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
987: ""
988: "*
989: {
990: switch (which_alternative)
991: {
992: case 0:
993: return \"cvtbw %1,%0\";
994: case 1:
995: if (push_operand(operands[0], SImode))
996: return \"pushl %1\;cvtbw 3(sp),2(sp)\";
997: else {
998: CC_STATUS_INIT;
999: return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\";
1000: }
1001: }
1002: }")
1003:
1004:
1005: ; extendsfdf2 tahoe uses the fpp accumulator to do the extension.
1006: ; It takes a float and loads it up directly as a double.
1007:
1008: (define_insn "extendsfdf2"
1009: [(set (match_operand:DF 0 "register_operand" "=a")
1010: (float_extend:DF (match_operand:SF 1 "general_operand" "g")))]
1011: ""
1012: "*
1013: {
1014: CC_STATUS_INIT;
1015: return \"ldfd %1\";
1016: }")
1017:
1018:
1019: ; movz works fine from memory but not from register for the same reasons
1020: ; the cvt instructions don't work right. So we use the normal instruction
1021: ; from memory and we use an and to simulate it from register. This is faster
1022: ; than pulling it off the stack.
1023:
1024: (define_insn "zero_extendhisi2"
1025: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1026: (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
1027: ""
1028: "*
1029: {
1030: switch (which_alternative)
1031: {
1032: case 0:
1033: return \"movzwl %1,%0\";
1034: case 1:
1035: return \"andl3 $0xffff,%1,%0\";
1036: }
1037: }")
1038:
1039:
1040: ; movz works fine from memory but not from register for the same reasons
1041: ; the cvt instructions don't work right. So we use the normal instruction
1042: ; from memory and we use an and to simulate it from register. This is faster
1043: ; than pulling it off the stack.
1044:
1045: (define_insn "zero_extendqihi2"
1046: [(set (match_operand:HI 0 "general_operand" "=g,?=g")
1047: (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
1048: ""
1049: "*
1050: {
1051: switch (which_alternative)
1052: {
1053: case 0:
1054: return \"movzbw %1,%0\";
1055: case 1:
1056: return \"andw3 $0xff,%1,%0\";
1057: }
1058: }")
1059:
1060:
1061: ; movz works fine from memory but not from register for the same reasons
1062: ; the cvt instructions don't work right. So we use the normal instruction
1063: ; from memory and we use an and to simulate it from register. This is faster
1064: ; than pulling it off the stack.
1065:
1066: (define_insn "zero_extendqisi2"
1067: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1068: (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
1069: ""
1070: "*
1071: {
1072: switch (which_alternative)
1073: {
1074: case 0:
1075: return \"movzbl %1,%0\";
1076: case 1:
1077: return \"andl3 $0xff,%1,%0\";
1078: }
1079: }")
1080:
1081:
1082: (define_insn "beq"
1083: [(set (pc)
1084: (if_then_else (eq (cc0)
1085: (const_int 0))
1086: (label_ref (match_operand 0 "" ""))
1087: (pc)))]
1088: ""
1089: "jeql %l0")
1090:
1091:
1092: (define_insn "bne"
1093: [(set (pc)
1094: (if_then_else (ne (cc0)
1095: (const_int 0))
1096: (label_ref (match_operand 0 "" ""))
1097: (pc)))]
1098: ""
1099: "jneq %l0")
1100:
1101:
1102: (define_insn "bgt"
1103: [(set (pc)
1104: (if_then_else (gt (cc0)
1105: (const_int 0))
1106: (label_ref (match_operand 0 "" ""))
1107: (pc)))]
1108: ""
1109: "jgtr %l0")
1110:
1111:
1112: (define_insn "bgtu"
1113: [(set (pc)
1114: (if_then_else (gtu (cc0)
1115: (const_int 0))
1116: (label_ref (match_operand 0 "" ""))
1117: (pc)))]
1118: ""
1119: "jgtru %l0")
1120:
1121:
1122: (define_insn "blt"
1123: [(set (pc)
1124: (if_then_else (lt (cc0)
1125: (const_int 0))
1126: (label_ref (match_operand 0 "" ""))
1127: (pc)))]
1128: ""
1129: "jlss %l0")
1130:
1131:
1132: (define_insn "bltu"
1133: [(set (pc)
1134: (if_then_else (ltu (cc0)
1135: (const_int 0))
1136: (label_ref (match_operand 0 "" ""))
1137: (pc)))]
1138: ""
1139: "jlssu %l0")
1140:
1141:
1142: (define_insn "bge"
1143: [(set (pc)
1144: (if_then_else (ge (cc0)
1145: (const_int 0))
1146: (label_ref (match_operand 0 "" ""))
1147: (pc)))]
1148: ""
1149: "jgeq %l0")
1150:
1151:
1152: (define_insn "bgeu"
1153: [(set (pc)
1154: (if_then_else (geu (cc0)
1155: (const_int 0))
1156: (label_ref (match_operand 0 "" ""))
1157: (pc)))]
1158: ""
1159: "jgequ %l0")
1160:
1161:
1162: (define_insn "ble"
1163: [(set (pc)
1164: (if_then_else (le (cc0)
1165: (const_int 0))
1166: (label_ref (match_operand 0 "" ""))
1167: (pc)))]
1168: ""
1169: "jleq %l0")
1170:
1171:
1172: (define_insn "bleu"
1173: [(set (pc)
1174: (if_then_else (leu (cc0)
1175: (const_int 0))
1176: (label_ref (match_operand 0 "" ""))
1177: (pc)))]
1178: ""
1179: "jlequ %l0")
1180:
1181:
1182: ; GCC does not account for register mask/argc longword. Thus the number
1183: ; for the call = number bytes for args + 4
1184:
1185: (define_insn "call"
1186: [(call (match_operand:QI 0 "general_operand" "g")
1187: (match_operand:QI 1 "general_operand" "g"))]
1188: ""
1189: "*
1190: {
1191: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 4));
1192: return \"calls %1,%0\";
1193: }")
1194:
1195:
1196: ; GCC does not account for register mask/argc longword. Thus the number
1197: ; for the call = number bytes for args + 4
1198:
1199: (define_insn "call_value"
1200: [(set (match_operand 0 "" "=g")
1201: (call (match_operand:QI 1 "general_operand" "g")
1202: (match_operand:QI 2 "general_operand" "g")))]
1203: ""
1204: "*
1205: {
1206: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 4));
1207: return \"calls %2,%1\";
1208: }")
1209:
1210:
1211: (define_insn "nop"
1212: [(const_int 0)]
1213: ""
1214: "nop")
1215:
1216:
1217: (define_insn "return"
1218: [(return)]
1219: ""
1220: "ret")
1221:
1222:
1223: ; casesi, extracted from the vax code. The instructions are
1224: ; very similar. Tahoe requires that the table be word aligned. GCC
1225: ; places the table immediately after, thus the alignment directive.
1226:
1227: (define_insn "casesi"
1228: [(set (pc)
1229: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1230: (match_operand:SI 1 "general_operand" "g"))
1231: (match_operand:SI 2 "general_operand" "g"))
1232: (plus:SI (sign_extend:SI
1233: (mem:HI (plus:SI (pc)
1234: (minus:SI (match_dup 0)
1235: (match_dup 1)))))
1236: (label_ref:SI (match_operand 3 "" "")))
1237: (pc)))]
1238: ""
1239: "casel %0,%1,%2\;.align %@")
1240:
1241:
1242: (define_insn "jump"
1243: [(set (pc)
1244: (label_ref (match_operand 0 "" "")))]
1245: ""
1246: "jbr %l0")
1247:
1248:
1249: ;; This is the list of all the non-standard insn patterns
1250:
1251:
1252: ; This is used to access the address of a byte. This is similar to
1253: ; movqi, but the second operand had to be "address_operand" type, so
1254: ; it had to be an unnamed one.
1255:
1256: (define_insn ""
1257: [(set (match_operand:SI 0 "general_operand" "=g")
1258: (match_operand:QI 1 "address_operand" "p"))]
1259: ""
1260: "*
1261: {
1262: if (push_operand (operands[0], SImode))
1263: return \"pushab %a1\";
1264: return \"movab %a1,%0\";
1265: }")
1266:
1267: ; This is used to access the address of a word. This is similar to
1268: ; movhi, but the second operand had to be "address_operand" type, so
1269: ; it had to be an unnamed one.
1270:
1271: (define_insn ""
1272: [(set (match_operand:SI 0 "general_operand" "=g")
1273: (match_operand:HI 1 "address_operand" "p"))]
1274: ""
1275: "*
1276: {
1277: if (push_operand (operands[0], SImode))
1278: return \"pushaw %a1\";
1279: return \"movaw %a1,%0\";
1280: }")
1281:
1282: ; This is used to access the address of a long. This is similar to
1283: ; movsi, but the second operand had to be "address_operand" type, so
1284: ; it had to be an unnamed one.
1285:
1286: (define_insn ""
1287: [(set (match_operand:SI 0 "general_operand" "=g")
1288: (match_operand:SI 1 "address_operand" "p"))]
1289: ""
1290: "*
1291: {
1292: if (push_operand (operands[0], SImode))
1293: return \"pushal %a1\";
1294: return \"moval %a1,%0\";
1295: }")
1296:
1297: ; The tahoe doesn't have an 8 byte indexed move address command
1298: ; and GCC needs it. To work around it, double the index (%2) and
1299: ; then use the 4 byte indexed move address command.
1300: ;
1301: ;(define_insn ""
1302: ; [(set (match_operand:SI 0 "general_operand" "=g")
1303: ; (plus:SI (match_operand:SI 1 "general_operand" "g")
1304: ; (mult:SI (match_operand:SI 2 "register_operand" "r")
1305: ; (const_int 8))))]
1306: ; ""
1307: ; "*
1308: ;{
1309: ; if (GET_CODE (operands[0]) == REG &&
1310: ; REGNO (operands[0]) == REGNO (operands[2])) {
1311: ; return \"shll $3,%2,%2\;addl3 %1,%2,%0\";
1312: ; } else {
1313: ; return \"shll $3,%2,%2\;addl3 %1,%2,%0\;shrl $3,%2,%2\"; }
1314: ;}")
1315:
1316:
1317: ; Bit test longword instruction, same as vax.
1318:
1319: (define_insn ""
1320: [(set (cc0)
1321: (and:SI (match_operand:SI 0 "general_operand" "g")
1322: (match_operand:SI 1 "general_operand" "g")))]
1323: ""
1324: "bitl %0,%1")
1325:
1326:
1327: ; Bit test word instructions, same as vax.
1328:
1329: (define_insn ""
1330: [(set (cc0)
1331: (and:HI (match_operand:HI 0 "general_operand" "g")
1332: (match_operand:HI 1 "general_operand" "g")))]
1333: ""
1334: "bitw %0,%1")
1335:
1336:
1337: ; Bit test instructions, same as vax.
1338:
1339: (define_insn ""
1340: [(set (cc0)
1341: (and:QI (match_operand:QI 0 "general_operand" "g")
1342: (match_operand:QI 1 "general_operand" "g")))]
1343: ""
1344: "bitb %0,%1")
1345:
1346:
1347: ; bne counterpart. In case GCC reverses the conditional.
1348:
1349: (define_insn ""
1350: [(set (pc)
1351: (if_then_else (eq (cc0)
1352: (const_int 0))
1353: (pc)
1354: (label_ref (match_operand 0 "" ""))))]
1355: ""
1356: "jneq %l0")
1357:
1358:
1359: ; beq counterpart. In case GCC reverses the conditional.
1360:
1361: (define_insn ""
1362: [(set (pc)
1363: (if_then_else (ne (cc0)
1364: (const_int 0))
1365: (pc)
1366: (label_ref (match_operand 0 "" ""))))]
1367: ""
1368: "jeql %l0")
1369:
1370:
1371: ; ble counterpart. In case GCC reverses the conditional.
1372:
1373: (define_insn ""
1374: [(set (pc)
1375: (if_then_else (gt (cc0)
1376: (const_int 0))
1377: (pc)
1378: (label_ref (match_operand 0 "" ""))))]
1379: ""
1380: "jleq %l0")
1381:
1382:
1383: ; bleu counterpart. In case GCC reverses the conditional.
1384:
1385: (define_insn ""
1386: [(set (pc)
1387: (if_then_else (gtu (cc0)
1388: (const_int 0))
1389: (pc)
1390: (label_ref (match_operand 0 "" ""))))]
1391: ""
1392: "jlequ %l0")
1393:
1394:
1395: ; bge counterpart. In case GCC reverses the conditional.
1396:
1397: (define_insn ""
1398: [(set (pc)
1399: (if_then_else (lt (cc0)
1400: (const_int 0))
1401: (pc)
1402: (label_ref (match_operand 0 "" ""))))]
1403: ""
1404: "jgeq %l0")
1405:
1406:
1407: ; bgeu counterpart. In case GCC reverses the conditional.
1408:
1409: (define_insn ""
1410: [(set (pc)
1411: (if_then_else (ltu (cc0)
1412: (const_int 0))
1413: (pc)
1414: (label_ref (match_operand 0 "" ""))))]
1415: ""
1416: "jgequ %l0")
1417:
1418:
1419: ; blt counterpart. In case GCC reverses the conditional.
1420:
1421: (define_insn ""
1422: [(set (pc)
1423: (if_then_else (ge (cc0)
1424: (const_int 0))
1425: (pc)
1426: (label_ref (match_operand 0 "" ""))))]
1427: ""
1428: "jlss %l0")
1429:
1430:
1431: ; bltu counterpart. In case GCC reverses the conditional.
1432:
1433: (define_insn ""
1434: [(set (pc)
1435: (if_then_else (geu (cc0)
1436: (const_int 0))
1437: (pc)
1438: (label_ref (match_operand 0 "" ""))))]
1439: ""
1440: "jlssu %l0")
1441:
1442:
1443: ; bgt counterpart. In case GCC reverses the conditional.
1444:
1445: (define_insn ""
1446: [(set (pc)
1447: (if_then_else (le (cc0)
1448: (const_int 0))
1449: (pc)
1450: (label_ref (match_operand 0 "" ""))))]
1451: ""
1452: "jgtr %l0")
1453:
1454:
1455: ; bgtu counterpart. In case GCC reverses the conditional.
1456:
1457: (define_insn ""
1458: [(set (pc)
1459: (if_then_else (leu (cc0)
1460: (const_int 0))
1461: (pc)
1462: (label_ref (match_operand 0 "" ""))))]
1463: ""
1464: "jgtru %l0")
1465:
1466:
1467: ; casesi alternate form as found in vax code. This form is to
1468: ; compensate for the table's offset being no distance (0 displacement)
1469:
1470: (define_insn ""
1471: [(set (pc)
1472: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1473: (match_operand:SI 1 "general_operand" "g"))
1474: (plus:SI (sign_extend:SI
1475: (mem:HI (plus:SI (pc)
1476: (minus:SI (match_dup 0)
1477: (const_int 0)))))
1478: (label_ref:SI (match_operand 3 "" "")))
1479: (pc)))]
1480: ""
1481: "casel %0,$0,%1\;.align %@")
1482:
1483:
1484: ; casesi alternate form as found in vax code. Another form to
1485: ; compensate for the table's offset being no distance (0 displacement)
1486:
1487: (define_insn ""
1488: [(set (pc)
1489: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1490: (match_operand:SI 1 "general_operand" "g"))
1491: (plus:SI (sign_extend:SI
1492: (mem:HI (plus:SI (pc)
1493: (match_dup 0))))
1494: (label_ref:SI (match_operand 3 "" "")))
1495: (pc)))]
1496: ""
1497: "casel %0,$0,%1 \;.align %@")
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