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1.1.1.2 ! root 1: ;; Machine description for GNU compiler, Tahoe version ! 2: ;; Copyright (C) 1989, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: ;; This file is part of GNU CC. 5: 6: ;; GNU CC is free software; you can redistribute it and/or modify 7: ;; it under the terms of the GNU General Public License as published by 8: ;; the Free Software Foundation; either version 2, or (at your option) 9: ;; any later version. 10: 11: ;; GNU CC is distributed in the hope that it will be useful, 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: ;; GNU General Public License for more details. 15: 16: ;; You should have received a copy of the GNU General Public License 17: ;; along with GNU CC; see the file COPYING. If not, write to 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 19: 20: 21: ; File: tahoe.md 22: ; 23: ; Original port made at the University of Buffalo by Devon Bowen, 24: ; Dale Wiles and Kevin Zachmann. 25: ; 26: ; Piet van Oostrum ([email protected]) made changes for HCX/UX, fixed 27: ; some bugs and made some improvements (hopefully). 28: ; 29: ; Mail bugs reports or fixes to: [email protected] 30: 31: 32: ; movdi must call the output_move_double routine to move it around since 33: ; the tahoe doesn't efficiently support 8 bit moves. 34: 35: (define_insn "movdi" 36: [(set (match_operand:DI 0 "general_operand" "=g") 37: (match_operand:DI 1 "general_operand" "g"))] 38: "" 39: "* 40: { 41: CC_STATUS_INIT; 42: return output_move_double (operands); 43: }") 44: 45: 46: ; the trick in the movsi is accessing the contents of the sp register. The 47: ; tahoe doesn't allow you to access it directly so you have to access the 48: ; address of the top of the stack instead. 49: 50: (define_insn "movsi" 51: [(set (match_operand:SI 0 "general_operand" "=g") 52: (match_operand:SI 1 "general_operand" "g"))] 53: "" 54: "* 55: { 56: rtx link; 57: if (operands[1] == const1_rtx 58: && (link = find_reg_note (insn, REG_WAS_0, 0)) 59: && ! INSN_DELETED_P (XEXP (link, 0)) 60: && GET_CODE (XEXP (link, 0)) != NOTE 61: && no_labels_between_p (XEXP (link, 0), insn) 62: /* Make sure the reg hasn't been clobbered. */ 63: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 64: return \"incl %0\"; 65: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) 66: { 67: if (push_operand (operands[0], SImode)) 68: return \"pushab %a1\"; 69: return \"movab %a1,%0\"; 70: } 71: if (operands[1] == const0_rtx) 72: return \"clrl %0\"; 73: if (push_operand (operands[0], SImode)) 74: return \"pushl %1\"; 75: if (GET_CODE(operands[1]) == REG && REGNO(operands[1]) == 14) 76: return \"moval (sp),%0\"; 77: return \"movl %1,%0\"; 78: }") 79: 80: 81: (define_insn "movhi" 82: [(set (match_operand:HI 0 "general_operand" "=g") 83: (match_operand:HI 1 "general_operand" "g"))] 84: "" 85: "* 86: { 87: rtx link; 88: if (operands[1] == const1_rtx 89: && (link = find_reg_note (insn, REG_WAS_0, 0)) 90: && ! INSN_DELETED_P (XEXP (link, 0)) 91: && GET_CODE (XEXP (link, 0)) != NOTE 92: && no_labels_between_p (XEXP (link, 0), insn) 93: /* Make sure the reg hasn't been clobbered. */ 94: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 95: return \"incw %0\"; 96: if (operands[1] == const0_rtx) 97: return \"clrw %0\"; 98: return \"movw %1,%0\"; 99: }") 100: 101: 102: (define_insn "movqi" 103: [(set (match_operand:QI 0 "general_operand" "=g") 104: (match_operand:QI 1 "general_operand" "g"))] 105: "" 106: "* 107: { 108: if (operands[1] == const0_rtx) 109: return \"clrb %0\"; 110: return \"movb %1,%0\"; 111: }") 112: 113: 114: ; movsf has three cases since they can move from one place to another 115: ; or to/from the fpp and since different instructions are needed for 116: ; each case. The fpp related instructions don't set the flags properly. 117: 118: (define_insn "movsf" 119: [(set (match_operand:SF 0 "general_operand" "=g,=a,=g") 120: (match_operand:SF 1 "general_operand" "g,g,a"))] 121: "" 122: "* 123: { 124: CC_STATUS_INIT; 125: switch (which_alternative) 126: { 127: case 0: return \"movl %1,%0\"; 128: case 1: return \"ldf %1\"; 129: case 2: return \"stf %0\"; 130: } 131: }") 132: 133: 134: ; movdf has a number of different cases. If it's going to or from 135: ; the fpp, use the special instructions to do it. If not, use the 136: ; output_move_double function. 137: 138: (define_insn "movdf" 139: [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g") 140: (match_operand:DF 1 "general_operand" "g,a,g"))] 141: "" 142: "* 143: { 144: CC_STATUS_INIT; 145: switch (which_alternative) 146: { 147: case 0: 148: return \"ldd %1\"; 149: case 1: 150: if (push_operand (operands[0], DFmode)) 151: return \"pushd\"; 152: else 153: return \"std %0\"; 154: case 2: 155: return output_move_double (operands); 156: } 157: }") 158: 159: 160: ;======================================================================== 161: ; The tahoe has the following semantics for byte (and similar for word) 162: ; operands: if the operand is a register or immediate, it takes the full 32 163: ; bit operand, if the operand is memory, it sign-extends the byte. The 164: ; operation is performed on the 32 bit values. If the destination is a 165: ; register, the full 32 bit result is stored, if the destination is memory, 166: ; of course only the low part is stored. The condition code is based on the 167: ; 32 bit operation. Only on the movz instructions the byte from memory is 168: ; zero-extended rather than sign-extended. 169: 170: ; This means that for arithmetic instructions we can use addb etc. to 171: ; perform a long add from a signed byte from memory to a register. Of 172: ; course this would also work for logical operations, but that doesn't seem 173: ; very useful. 174: 175: (define_insn "" 176: [(set (match_operand:SI 0 "register_operand" "=r") 177: (plus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) 178: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] 179: "" 180: "addb3 %1,%2,%0") 181: 182: (define_insn "" 183: [(set (match_operand:SI 0 "register_operand" "=r") 184: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri") 185: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] 186: "" 187: "* 188: { 189: if (rtx_equal_p (operands[0], operands[1])) 190: return \"addb2 %2,%0\"; 191: return \"addb3 %1,%2,%0\"; 192: }") 193: 194: ; We can also consider the result to be a half integer 195: 196: (define_insn "" 197: [(set (match_operand:HI 0 "register_operand" "=r") 198: (plus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) 199: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] 200: "" 201: "addb3 %1,%2,%0") 202: 203: (define_insn "" 204: [(set (match_operand:HI 0 "register_operand" "=r") 205: (plus:HI (match_operand:HI 1 "nonmemory_operand" "%ri") 206: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] 207: "" 208: "* 209: { 210: if (rtx_equal_p (operands[0], operands[1])) 211: return \"addb2 %2,%0\"; 212: return \"addb3 %1,%2,%0\"; 213: }") 214: 215: ; The same applies to words (HI) 216: 217: (define_insn "" 218: [(set (match_operand:SI 0 "register_operand" "=r") 219: (plus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) 220: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] 221: "" 222: "addw3 %1,%2,%0") 223: 224: (define_insn "" 225: [(set (match_operand:SI 0 "register_operand" "=r") 226: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri") 227: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] 228: "" 229: "* 230: { 231: if (rtx_equal_p (operands[0], operands[1])) 232: return \"addw2 %2,%0\"; 233: return \"addw3 %1,%2,%0\"; 234: }") 235: 236: ; ======================= Now for subtract ============================== 237: 238: (define_insn "" 239: [(set (match_operand:SI 0 "register_operand" "=r") 240: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) 241: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] 242: "" 243: "subb3 %2,%1,%0") 244: 245: (define_insn "" 246: [(set (match_operand:SI 0 "register_operand" "=r") 247: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri") 248: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))] 249: "" 250: "* 251: { 252: if (rtx_equal_p (operands[0], operands[1])) 253: return \"subb2 %2,%0\"; 254: return \"subb3 %2,%1,%0\"; 255: }") 256: 257: (define_insn "" 258: [(set (match_operand:SI 0 "register_operand" "=r") 259: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")) 260: (match_operand:SI 2 "nonmemory_operand" "ri")))] 261: "" 262: "subb3 %2,%1,%0") 263: 264: ; We can also consider the result to be a half integer 265: 266: (define_insn "" 267: [(set (match_operand:HI 0 "register_operand" "=r") 268: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) 269: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] 270: "" 271: "subb3 %2,%1,%0") 272: 273: (define_insn "" 274: [(set (match_operand:HI 0 "register_operand" "=r") 275: (minus:HI (match_operand:HI 1 "nonmemory_operand" "%ri") 276: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))] 277: "" 278: "* 279: { 280: if (rtx_equal_p (operands[0], operands[1])) 281: return \"subb2 %2,%0\"; 282: return \"subb3 %2,%1,%0\"; 283: }") 284: 285: (define_insn "" 286: [(set (match_operand:HI 0 "register_operand" "=r") 287: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")) 288: (match_operand:HI 2 "nonmemory_operand" "ri")))] 289: "" 290: "subb3 %2,%1,%0") 291: 292: ; The same applies to words (HI) 293: 294: (define_insn "" 295: [(set (match_operand:SI 0 "register_operand" "=r") 296: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) 297: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] 298: "" 299: "subw3 %2,%1,%0") 300: 301: (define_insn "" 302: [(set (match_operand:SI 0 "register_operand" "=r") 303: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri") 304: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))] 305: "" 306: "* 307: { 308: if (rtx_equal_p (operands[0], operands[1])) 309: return \"subw2 %2,%0\"; 310: return \"subw3 %2,%1,%0\"; 311: }") 312: 313: (define_insn "" 314: [(set (match_operand:SI 0 "register_operand" "=r") 315: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) 316: (match_operand:SI 2 "nonmemory_operand" "ri")))] 317: "" 318: "subw3 %2,%1,%0") 319: 320: ; ======================= Now for neg ============================== 321: 322: (define_insn "" 323: [(set (match_operand:SI 0 "register_operand" "=r") 324: (neg:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] 325: "" 326: "mnegb %1,%0") 327: 328: (define_insn "" 329: [(set (match_operand:HI 0 "register_operand" "=r") 330: (neg:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))))] 331: "" 332: "mnegb %1,%0") 333: 334: (define_insn "" 335: [(set (match_operand:SI 0 "register_operand" "=r") 336: (neg:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] 337: "" 338: "mnegw %1,%0") 339: 340: ;======================================================================== 341: 342: 343: (define_insn "addsi3" 344: [(set (match_operand:SI 0 "general_operand" "=g") 345: (plus:SI (match_operand:SI 1 "general_operand" "g") 346: (match_operand:SI 2 "general_operand" "g")))] 347: "" 348: "* 349: { 350: if (rtx_equal_p (operands[0], operands[1])) 351: { 352: if (operands[2] == const1_rtx) 353: return \"incl %0\"; 354: if (GET_CODE (operands[2]) == CONST_INT 355: && INTVAL (operands[2]) == -1) 356: return \"decl %0\"; 357: if (GET_CODE (operands[2]) == CONST_INT 358: && (unsigned) (- INTVAL (operands[2])) < 64) 359: return \"subl2 $%n2,%0\"; 360: return \"addl2 %2,%0\"; 361: } 362: if (rtx_equal_p (operands[0], operands[2])) 363: return \"addl2 %1,%0\"; 364: if (GET_CODE (operands[2]) == CONST_INT 365: && GET_CODE (operands[1]) == REG) 366: { 367: if (push_operand (operands[0], SImode)) 368: return \"pushab %c2(%1)\"; 369: return \"movab %c2(%1),%0\"; 370: } 371: if (GET_CODE (operands[2]) == CONST_INT 372: && (unsigned) (- INTVAL (operands[2])) < 64) 373: return \"subl3 $%n2,%1,%0\"; 374: return \"addl3 %1,%2,%0\"; 375: }") 376: 377: 378: (define_insn "addhi3" 379: [(set (match_operand:HI 0 "general_operand" "=g") 380: (plus:HI (match_operand:HI 1 "general_operand" "g") 381: (match_operand:HI 2 "general_operand" "g")))] 382: "" 383: "* 384: { 385: if (rtx_equal_p (operands[0], operands[1])) 386: { 387: if (operands[2] == const1_rtx) 388: return \"incw %0\"; 389: if (GET_CODE (operands[2]) == CONST_INT 390: && INTVAL (operands[2]) == -1) 391: return \"decw %0\"; 392: if (GET_CODE (operands[2]) == CONST_INT 393: && (unsigned) (- INTVAL (operands[2])) < 64) 394: return \"subw2 $%n2,%0\"; 395: return \"addw2 %2,%0\"; 396: } 397: if (rtx_equal_p (operands[0], operands[2])) 398: return \"addw2 %1,%0\"; 399: if (GET_CODE (operands[2]) == CONST_INT 400: && (unsigned) (- INTVAL (operands[2])) < 64) 401: return \"subw3 $%n2,%1,%0\"; 402: return \"addw3 %1,%2,%0\"; 403: }") 404: 405: 406: (define_insn "addqi3" 407: [(set (match_operand:QI 0 "general_operand" "=g") 408: (plus:QI (match_operand:QI 1 "general_operand" "g") 409: (match_operand:QI 2 "general_operand" "g")))] 410: "" 411: "* 412: { 413: if (rtx_equal_p (operands[0], operands[1])) 414: { 415: if (operands[2] == const1_rtx) 416: return \"incb %0\"; 417: if (GET_CODE (operands[2]) == CONST_INT 418: && INTVAL (operands[2]) == -1) 419: return \"decb %0\"; 420: if (GET_CODE (operands[2]) == CONST_INT 421: && (unsigned) (- INTVAL (operands[2])) < 64) 422: return \"subb2 $%n2,%0\"; 423: return \"addb2 %2,%0\"; 424: } 425: if (rtx_equal_p (operands[0], operands[2])) 426: return \"addb2 %1,%0\"; 427: if (GET_CODE (operands[2]) == CONST_INT 428: && (unsigned) (- INTVAL (operands[2])) < 64) 429: return \"subb3 $%n2,%1,%0\"; 430: return \"addb3 %1,%2,%0\"; 431: }") 432: 433: ; addsf3 can only add into the fpp register since the fpp is treated 434: ; as a separate unit in the machine. It also doesn't set the flags at 435: ; all. 436: 437: (define_insn "addsf3" 438: [(set (match_operand:SF 0 "register_operand" "=a") 439: (plus:SF (match_operand:SF 1 "register_operand" "%0") 440: (match_operand:SF 2 "general_operand" "g")))] 441: "" 442: "* 443: { 444: CC_STATUS_INIT; 445: return \"addf %2\"; 446: }") 447: 448: 449: ; adddf3 can only add into the fpp reg since the fpp is treated as a 450: ; separate entity. Doubles can only be read from a register or memory 451: ; since a double is not an immediate mode. Flags are not set by this 452: ; instruction. 453: 454: (define_insn "adddf3" 455: [(set (match_operand:DF 0 "register_operand" "=a") 456: (plus:DF (match_operand:DF 1 "register_operand" "%0") 457: (match_operand:DF 2 "general_operand" "rm")))] 458: "" 459: "* 460: { 461: CC_STATUS_INIT; 462: return \"addd %2\"; 463: }") 464: 465: 466: ; Subtraction from the sp (needed by the built in alloc function) needs 467: ; to be different since the sp cannot be directly read on the tahoe. 468: ; If it's a simple constant, you just use displacement. Otherwise, you 469: ; push the sp, and then do the subtraction off the stack. 470: 471: (define_insn "subsi3" 472: [(set (match_operand:SI 0 "general_operand" "=g") 473: (minus:SI (match_operand:SI 1 "general_operand" "g") 474: (match_operand:SI 2 "general_operand" "g")))] 475: "" 476: "* 477: { 478: if (rtx_equal_p (operands[0], operands[1])) 479: { 480: if (operands[2] == const1_rtx) 481: return \"decl %0\"; 482: if (GET_CODE(operands[0]) == REG && REGNO(operands[0]) == 14) 483: { 484: if (GET_CODE(operands[2]) == CONST_INT) 485: return \"movab %n2(sp),sp\"; 486: else 487: return \"pushab (sp)\;subl3 %2,(sp),sp\"; 488: } 489: return \"subl2 %2,%0\"; 490: } 491: if (rtx_equal_p (operands[1], operands[2])) 492: return \"clrl %0\"; 493: return \"subl3 %2,%1,%0\"; 494: }") 495: 496: 497: (define_insn "subhi3" 498: [(set (match_operand:HI 0 "general_operand" "=g") 499: (minus:HI (match_operand:HI 1 "general_operand" "g") 500: (match_operand:HI 2 "general_operand" "g")))] 501: "" 502: "* 503: { 504: if (rtx_equal_p (operands[0], operands[1])) 505: { 506: if (operands[2] == const1_rtx) 507: return \"decw %0\"; 508: return \"subw2 %2,%0\"; 509: } 510: if (rtx_equal_p (operands[1], operands[2])) 511: return \"clrw %0\"; 512: return \"subw3 %2,%1,%0\"; 513: }") 514: 515: 516: (define_insn "subqi3" 517: [(set (match_operand:QI 0 "general_operand" "=g") 518: (minus:QI (match_operand:QI 1 "general_operand" "g") 519: (match_operand:QI 2 "general_operand" "g")))] 520: "" 521: "* 522: { 523: if (rtx_equal_p (operands[0], operands[1])) 524: { 525: if (operands[2] == const1_rtx) 526: return \"decb %0\"; 527: return \"subb2 %2,%0\"; 528: } 529: if (rtx_equal_p (operands[1], operands[2])) 530: return \"clrb %0\"; 531: return \"subb3 %2,%1,%0\"; 532: }") 533: 534: 535: ; subsf3 can only subtract into the fpp accumulator due to the way 536: ; the fpp reg is limited by the instruction set. This also doesn't 537: ; bother setting up flags. 538: 539: (define_insn "subsf3" 540: [(set (match_operand:SF 0 "register_operand" "=a") 541: (minus:SF (match_operand:SF 1 "register_operand" "0") 542: (match_operand:SF 2 "general_operand" "g")))] 543: "" 544: "* 545: { 546: CC_STATUS_INIT; 547: return \"subf %2\"; 548: }") 549: 550: 551: ; subdf3 is set up to subtract into the fpp reg due to limitations 552: ; of the fpp instruction set. Doubles can not be immediate. This 553: ; instruction does not set the flags. 554: 555: (define_insn "subdf3" 556: [(set (match_operand:DF 0 "register_operand" "=a") 557: (minus:DF (match_operand:DF 1 "register_operand" "0") 558: (match_operand:DF 2 "general_operand" "rm")))] 559: "" 560: "* 561: { 562: CC_STATUS_INIT; 563: return \"subd %2\"; 564: }") 565: 566: 567: (define_insn "mulsi3" 568: [(set (match_operand:SI 0 "general_operand" "=g") 569: (mult:SI (match_operand:SI 1 "general_operand" "g") 570: (match_operand:SI 2 "general_operand" "g")))] 571: "" 572: "* 573: { 574: if (rtx_equal_p (operands[0], operands[1])) 575: return \"mull2 %2,%0\"; 576: if (rtx_equal_p (operands[0], operands[2])) 577: return \"mull2 %1,%0\"; 578: return \"mull3 %1,%2,%0\"; 579: }") 580: 581: 582: ; mulsf3 can only multiply into the fpp accumulator due to limitations 583: ; of the fpp. It also does not set the condition codes properly. 584: 585: (define_insn "mulsf3" 586: [(set (match_operand:SF 0 "register_operand" "=a") 587: (mult:SF (match_operand:SF 1 "register_operand" "%0") 588: (match_operand:SF 2 "general_operand" "g")))] 589: "" 590: "* 591: { 592: CC_STATUS_INIT; 593: return \"mulf %2\"; 594: }") 595: 596: 597: ; muldf3 can only multiply into the fpp reg since the fpp is limited 598: ; from the rest. Doubles may not be immediate mode. This does not set 599: ; the flags like gcc would expect. 600: 601: (define_insn "muldf3" 602: [(set (match_operand:DF 0 "register_operand" "=a") 603: (mult:DF (match_operand:DF 1 "register_operand" "%0") 604: (match_operand:DF 2 "general_operand" "rm")))] 605: "" 606: "* 607: { 608: CC_STATUS_INIT; 609: return \"muld %2\"; 610: }") 611: 612: 613: 614: (define_insn "divsi3" 615: [(set (match_operand:SI 0 "general_operand" "=g") 616: (div:SI (match_operand:SI 1 "general_operand" "g") 617: (match_operand:SI 2 "general_operand" "g")))] 618: "" 619: "* 620: { 621: if (rtx_equal_p (operands[1], operands[2])) 622: return \"movl $1,%0\"; 623: if (operands[1] == const0_rtx) 624: return \"clrl %0\"; 625: if (GET_CODE (operands[2]) == CONST_INT 626: && INTVAL (operands[2]) == -1) 627: return \"mnegl %1,%0\"; 628: if (rtx_equal_p (operands[0], operands[1])) 629: return \"divl2 %2,%0\"; 630: return \"divl3 %2,%1,%0\"; 631: }") 632: 633: 634: ; divsf3 must divide into the fpp accumulator. Flags are not set by 635: ; this instruction, so they are cleared. 636: 637: (define_insn "divsf3" 638: [(set (match_operand:SF 0 "register_operand" "=a") 639: (div:SF (match_operand:SF 1 "register_operand" "0") 640: (match_operand:SF 2 "general_operand" "g")))] 641: "" 642: "* 643: { 644: CC_STATUS_INIT; 645: return \"divf %2\"; 646: }") 647: 648: 649: ; divdf3 also must divide into the fpp reg so optimization isn't 650: ; possible. Note that doubles cannot be immediate. The flags here 651: ; are not set correctly so they must be ignored. 652: 653: (define_insn "divdf3" 654: [(set (match_operand:DF 0 "register_operand" "=a") 655: (div:DF (match_operand:DF 1 "register_operand" "0") 656: (match_operand:DF 2 "general_operand" "rm")))] 657: "" 658: "* 659: { 660: CC_STATUS_INIT; 661: return \"divd %2\"; 662: }") 663: 664: 665: 666: (define_insn "andsi3" 667: [(set (match_operand:SI 0 "general_operand" "=g") 668: (and:SI (match_operand:SI 1 "general_operand" "g") 669: (match_operand:SI 2 "general_operand" "g")))] 670: "" 671: "* 672: { 673: if (rtx_equal_p (operands[0], operands[1])) 674: return \"andl2 %2,%0\"; 675: if (rtx_equal_p (operands[0], operands[2])) 676: return \"andl2 %1,%0\"; 677: return \"andl3 %2,%1,%0\"; 678: }") 679: 680: 681: 682: (define_insn "andhi3" 683: [(set (match_operand:HI 0 "general_operand" "=g") 684: (and:HI (match_operand:HI 1 "general_operand" "g") 685: (match_operand:HI 2 "general_operand" "g")))] 686: "" 687: "* 688: { 689: if (rtx_equal_p (operands[0], operands[1])) 690: return \"andw2 %2,%0\"; 691: if (rtx_equal_p (operands[0], operands[2])) 692: return \"andw2 %1,%0\"; 693: return \"andw3 %2,%1,%0\"; 694: }") 695: 696: 697: (define_insn "andqi3" 698: [(set (match_operand:QI 0 "general_operand" "=g") 699: (and:QI (match_operand:QI 1 "general_operand" "g") 700: (match_operand:QI 2 "general_operand" "g")))] 701: "" 702: "* 703: { 704: if (rtx_equal_p (operands[0], operands[1])) 705: return \"andb2 %2,%0\"; 706: if (rtx_equal_p (operands[0], operands[2])) 707: return \"andb2 %1,%0\"; 708: return \"andb3 %2,%1,%0\"; 709: }") 710: 711: 712: (define_insn "iorsi3" 713: [(set (match_operand:SI 0 "general_operand" "=g") 714: (ior:SI (match_operand:SI 1 "general_operand" "g") 715: (match_operand:SI 2 "general_operand" "g")))] 716: "" 717: "* 718: { 719: if (rtx_equal_p (operands[0], operands[1])) 720: return \"orl2 %2,%0\"; 721: if (rtx_equal_p (operands[0], operands[2])) 722: return \"orl2 %1,%0\"; 723: return \"orl3 %2,%1,%0\"; 724: }") 725: 726: 727: 728: (define_insn "iorhi3" 729: [(set (match_operand:HI 0 "general_operand" "=g") 730: (ior:HI (match_operand:HI 1 "general_operand" "g") 731: (match_operand:HI 2 "general_operand" "g")))] 732: "" 733: "* 734: { 735: if (rtx_equal_p (operands[0], operands[1])) 736: return \"orw2 %2,%0\"; 737: if (rtx_equal_p (operands[0], operands[2])) 738: return \"orw2 %1,%0\"; 739: return \"orw3 %2,%1,%0\"; 740: }") 741: 742: 743: 744: (define_insn "iorqi3" 745: [(set (match_operand:QI 0 "general_operand" "=g") 746: (ior:QI (match_operand:QI 1 "general_operand" "g") 747: (match_operand:QI 2 "general_operand" "g")))] 748: "" 749: "* 750: { 751: if (rtx_equal_p (operands[0], operands[1])) 752: return \"orb2 %2,%0\"; 753: if (rtx_equal_p (operands[0], operands[2])) 754: return \"orb2 %1,%0\"; 755: return \"orb3 %2,%1,%0\"; 756: }") 757: 758: 759: (define_insn "xorsi3" 760: [(set (match_operand:SI 0 "general_operand" "=g") 761: (xor:SI (match_operand:SI 1 "general_operand" "g") 762: (match_operand:SI 2 "general_operand" "g")))] 763: "" 764: "* 765: { 766: if (rtx_equal_p (operands[0], operands[1])) 767: return \"xorl2 %2,%0\"; 768: if (rtx_equal_p (operands[0], operands[2])) 769: return \"xorl2 %1,%0\"; 770: return \"xorl3 %2,%1,%0\"; 771: }") 772: 773: 774: (define_insn "xorhi3" 775: [(set (match_operand:HI 0 "general_operand" "=g") 776: (xor:HI (match_operand:HI 1 "general_operand" "g") 777: (match_operand:HI 2 "general_operand" "g")))] 778: "" 779: "* 780: { 781: if (rtx_equal_p (operands[0], operands[1])) 782: return \"xorw2 %2,%0\"; 783: if (rtx_equal_p (operands[0], operands[2])) 784: return \"xorw2 %1,%0\"; 785: return \"xorw3 %2,%1,%0\"; 786: }") 787: 788: 789: (define_insn "xorqi3" 790: [(set (match_operand:QI 0 "general_operand" "=g") 791: (xor:QI (match_operand:QI 1 "general_operand" "g") 792: (match_operand:QI 2 "general_operand" "g")))] 793: "" 794: "* 795: { 796: if (rtx_equal_p (operands[0], operands[1])) 797: return \"xorb2 %2,%0\"; 798: if (rtx_equal_p (operands[0], operands[2])) 799: return \"xorb2 %1,%0\"; 800: return \"xorb3 %2,%1,%0\"; 801: }") 802: 803: 804: ; shifts on the tahoe are expensive, try some magic first... 805: 806: (define_insn "ashlsi3" 807: [(set (match_operand:SI 0 "general_operand" "=g") 808: (ashift:SI (match_operand:SI 1 "general_operand" "g") 809: (match_operand:QI 2 "general_operand" "g")))] 810: "" 811: "* 812: { 813: if (GET_CODE(operands[2]) == REG) 814: return \"mull3 ___shtab[%2],%1,%0\"; 815: /* if (GET_CODE(operands[2]) == REG) 816: if (rtx_equal_p (operands[0], operands[1])) 817: return \"mull2 ___shtab[%2],%1\"; 818: else 819: return \"mull3 ___shtab[%2],%1,%0\"; */ 820: if (GET_CODE(operands[1]) == REG) 821: { 822: if (operands[2] == const1_rtx) 823: { 824: CC_STATUS_INIT; 825: return \"movaw 0[%1],%0\"; 826: } 827: if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2) 828: { 829: CC_STATUS_INIT; 830: return \"moval 0[%1],%0\"; 831: } 832: } 833: if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1) 834: return \"shal %2,%1,%0\"; 835: if (rtx_equal_p (operands[0], operands[1])) 836: return \"mull2 %s2,%1\"; 837: else 838: return \"mull3 %s2,%1,%0\"; 839: }") 840: 841: 842: (define_insn "ashrsi3" 843: [(set (match_operand:SI 0 "general_operand" "=g") 844: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 845: (match_operand:QI 2 "general_operand" "g")))] 846: "" 847: "shar %2,%1,%0") 848: 849: 850: ; shifts are very expensive, try some magic first... 851: 852: (define_insn "lshrsi3" 853: [(set (match_operand:SI 0 "general_operand" "=g") 854: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g") 855: (match_operand:QI 2 "general_operand" "g")))] 856: "" 857: "shrl %2,%1,%0") 858: 859: 860: (define_insn "negsi2" 861: [(set (match_operand:SI 0 "general_operand" "=g") 862: (neg:SI (match_operand:SI 1 "general_operand" "g")))] 863: "" 864: "mnegl %1,%0") 865: 866: 867: (define_insn "neghi2" 868: [(set (match_operand:HI 0 "general_operand" "=g") 869: (neg:HI (match_operand:HI 1 "general_operand" "g")))] 870: "" 871: "mnegw %1,%0") 872: 873: 874: (define_insn "negqi2" 875: [(set (match_operand:QI 0 "general_operand" "=g") 876: (neg:QI (match_operand:QI 1 "general_operand" "g")))] 877: "" 878: "mnegb %1,%0") 879: 880: 881: ; negsf2 can only negate the value already in the fpp accumulator. 882: ; The value remains in the fpp accumulator. No flags are set. 883: 884: (define_insn "negsf2" 885: [(set (match_operand:SF 0 "register_operand" "=a,=a") 886: (neg:SF (match_operand:SF 1 "register_operand" "a,g")))] 887: "" 888: "* 889: { 890: CC_STATUS_INIT; 891: switch (which_alternative) 892: { 893: case 0: return \"negf\"; 894: case 1: return \"lnf %1\"; 895: } 896: }") 897: 898: 899: ; negdf2 can only negate the value already in the fpp accumulator. 900: ; The value remains in the fpp accumulator. No flags are set. 901: 902: (define_insn "negdf2" 903: [(set (match_operand:DF 0 "register_operand" "=a,=a") 904: (neg:DF (match_operand:DF 1 "register_operand" "a,g")))] 905: "" 906: "* 907: { 908: CC_STATUS_INIT; 909: switch (which_alternative) 910: { 911: case 0: return \"negd\"; 912: case 1: return \"lnd %1\"; 913: } 914: }") 915: 916: 917: ; sqrtsf2 tahoe can calculate the square root of a float in the 918: ; fpp accumulator. The answer remains in the fpp accumulator. No 919: ; flags are set by this function. 920: 921: (define_insn "sqrtsf2" 922: [(set (match_operand:SF 0 "register_operand" "=a") 923: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] 924: "" 925: "* 926: { 927: CC_STATUS_INIT; 928: return \"sqrtf\"; 929: }") 930: 931: 932: ; ffssi2 tahoe instruction gives one less than gcc desired result for 933: ; any given input. So the increment is necessary here. 934: 935: (define_insn "ffssi2" 936: [(set (match_operand:SI 0 "general_operand" "=g") 937: (ffs:SI (match_operand:SI 1 "general_operand" "g")))] 938: "" 939: "* 940: { 941: if (push_operand(operands[0], SImode)) 942: return \"ffs %1,%0\;incl (sp)\"; 943: return \"ffs %1,%0\;incl %0\"; 944: }") 945: 946: 947: (define_insn "one_cmplsi2" 948: [(set (match_operand:SI 0 "general_operand" "=g") 949: (not:SI (match_operand:SI 1 "general_operand" "g")))] 950: "" 951: "mcoml %1,%0") 952: 953: 954: (define_insn "one_cmplhi2" 955: [(set (match_operand:HI 0 "general_operand" "=g") 956: (not:HI (match_operand:HI 1 "general_operand" "g")))] 957: "" 958: "mcomw %1,%0") 959: 960: 961: (define_insn "one_cmplqi2" 962: [(set (match_operand:QI 0 "general_operand" "=g") 963: (not:QI (match_operand:QI 1 "general_operand" "g")))] 964: "" 965: "mcomb %1,%0") 966: 967: 968: ; cmpsi works fine, but due to microcode problems, the tahoe doesn't 969: ; properly compare hi's and qi's. Leaving them out seems to be acceptable 970: ; to the compiler, so they were left out. Compares of the stack are 971: ; possible, though. 972: 973: ; There are optimized cases possible, however. These follow first. 974: 975: (define_insn "" 976: [(set (cc0) 977: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")) 978: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] 979: "" 980: "cmpw %0,%1") 981: 982: (define_insn "" 983: [(set (cc0) 984: (compare (match_operand:SI 0 "nonmemory_operand" "ri") 985: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] 986: "" 987: "cmpw %0,%1") 988: 989: (define_insn "" 990: [(set (cc0) 991: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")) 992: (match_operand:SI 1 "nonmemory_operand" "ri")))] 993: "" 994: "cmpw %0,%1") 995: 996: ; zero-extended compares give the same result as sign-extended compares, if 997: ; the compare is unsigned. Just see: if both operands are <65536 they are the 998: ; same in both cases. If both are >=65536 the you effectively compare x+D 999: ; with y+D, where D=2**32-2**16, so the result is the same. if x<65536 and 1000: ; y>=65536 then you compare x with y+D, and in both cases the result is x<y. 1001: 1002: (define_insn "" 1003: [(set (cc0) 1004: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) 1005: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] 1006: "tahoe_cmp_check (insn, operands[0], 0)" 1007: "cmpw %0,%1") 1008: 1009: (define_insn "" 1010: [(set (cc0) 1011: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) 1012: (match_operand:SI 1 "immediate_operand" "i")))] 1013: "tahoe_cmp_check(insn, operands[1], 65535)" 1014: "* 1015: { 1016: if (INTVAL (operands[1]) > 32767) 1017: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffff0000); 1018: return \"cmpw %0,%1\"; 1019: }") 1020: 1021: 1022: (define_insn "" 1023: [(set (cc0) 1024: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")) 1025: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] 1026: "" 1027: "cmpb %0,%1") 1028: 1029: (define_insn "" 1030: [(set (cc0) 1031: (compare (match_operand:SI 0 "nonmemory_operand" "ri") 1032: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] 1033: "" 1034: "cmpb %0,%1") 1035: 1036: (define_insn "" 1037: [(set (cc0) 1038: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")) 1039: (match_operand:SI 1 "nonmemory_operand" "ri")))] 1040: "" 1041: "cmpb %0,%1") 1042: 1043: ; zero-extended compares give the same result as sign-extended compares, if 1044: ; the compare is unsigned. Just see: if both operands are <128 they are the 1045: ; same in both cases. If both are >=128 the you effectively compare x+D 1046: ; with y+D, where D=2**32-2**8, so the result is the same. if x<128 and 1047: ; y>=128 then you compare x with y+D, and in both cases the result is x<y. 1048: 1049: (define_insn "" 1050: [(set (cc0) 1051: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) 1052: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))] 1053: "tahoe_cmp_check (insn, operands[0], 0)" 1054: "cmpb %0,%1") 1055: 1056: (define_insn "" 1057: [(set (cc0) 1058: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) 1059: (match_operand:SI 1 "immediate_operand" "i")))] 1060: "tahoe_cmp_check(insn, operands[1], 255)" 1061: "* 1062: { 1063: if (INTVAL (operands[1]) > 127) 1064: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffffff00); 1065: return \"cmpb %0,%1\"; 1066: }") 1067: 1068: 1069: (define_insn "cmpsi" 1070: [(set (cc0) 1071: (compare (match_operand:SI 0 "nonimmediate_operand" "g") 1072: (match_operand:SI 1 "general_operand" "g")))] 1073: "" 1074: "cmpl %0,%1") 1075: 1076: 1077: ; cmpsf similar to vax, but first operand is expected to be in the 1078: ; fpp accumulator. 1079: 1080: (define_insn "cmpsf" 1081: [(set (cc0) 1082: (compare (match_operand:SF 0 "general_operand" "a,g") 1083: (match_operand:SF 1 "general_operand" "g,g")))] 1084: "" 1085: "* 1086: { 1087: switch (which_alternative) 1088: { 1089: case 0: return \"cmpf %1\"; 1090: case 1: return \"cmpf2 %0,%1\"; 1091: } 1092: }") 1093: 1094: 1095: ; cmpdf similar to vax, but first operand is expected to be in the 1096: ; fpp accumulator. Immediate doubles not allowed. 1097: 1098: (define_insn "cmpdf" 1099: [(set (cc0) 1100: (compare (match_operand:DF 0 "general_operand" "a,rm") 1101: (match_operand:DF 1 "general_operand" "rm,rm")))] 1102: "" 1103: "* 1104: { 1105: switch (which_alternative) 1106: { 1107: case 0: return \"cmpd %1\"; 1108: case 1: return \"cmpd2 %0,%1\"; 1109: } 1110: }") 1111: 1112: ;; We don't want to allow a constant operand for test insns because 1113: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 1114: ;; be folded while optimizing anyway. 1115: 1116: (define_insn "tstsi" 1117: [(set (cc0) 1118: (match_operand:SI 0 "nonimmediate_operand" "g"))] 1119: "" 1120: "tstl %0") 1121: 1122: 1123: ; small tests from memory are normal, but testing from registers doesn't 1124: ; expand the data properly. So test in this case does a convert and tests 1125: ; the new register data from the stack. 1126: 1127: ; First some special cases that do work 1128: 1129: 1130: (define_insn "" 1131: [(set (cc0) 1132: (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")))] 1133: "" 1134: "tstw %0") 1135: 1136: (define_insn "" 1137: [(set (cc0) 1138: (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")))] 1139: "tahoe_cmp_check (insn, operands[0], 0)" 1140: "tstw %0") 1141: 1142: 1143: (define_insn "tsthi" 1144: [(set (cc0) 1145: (match_operand:HI 0 "extendable_operand" "m,!r"))] 1146: "GET_MODE (operands[0]) != VOIDmode" 1147: "* 1148: { 1149: rtx xoperands[2]; 1150: extern rtx tahoe_reg_conversion_loc; 1151: switch (which_alternative) 1152: { 1153: case 0: 1154: return \"tstw %0\"; 1155: case 1: 1156: xoperands[0] = operands[0]; 1157: xoperands[1] = tahoe_reg_conversion_loc; 1158: output_asm_insn (\"movl %0,%1\", xoperands); 1159: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 2); 1160: output_asm_insn (\"tstw %a1\", xoperands); 1161: return \"\"; 1162: } 1163: }") 1164: 1165: 1166: (define_insn "" 1167: [(set (cc0) 1168: (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")))] 1169: "" 1170: "tstb %0") 1171: 1172: (define_insn "" 1173: [(set (cc0) 1174: (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")))] 1175: "tahoe_cmp_check (insn, operands[0], 0)" 1176: "tstb %0") 1177: 1178: 1179: (define_insn "tstqi" 1180: [(set (cc0) 1181: (match_operand:QI 0 "extendable_operand" "m,!r"))] 1182: "GET_MODE (operands[0]) != VOIDmode" 1183: "* 1184: { 1185: rtx xoperands[2]; 1186: extern rtx tahoe_reg_conversion_loc; 1187: switch (which_alternative) 1188: { 1189: case 0: 1190: return \"tstb %0\"; 1191: case 1: 1192: xoperands[0] = operands[0]; 1193: xoperands[1] = tahoe_reg_conversion_loc; 1194: output_asm_insn (\"movl %0,%1\", xoperands); 1195: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 3); 1196: output_asm_insn (\"tstb %a1\", xoperands); 1197: return \"\"; 1198: } 1199: }") 1200: 1201: ; tstsf compares a given value to a value already in the fpp accumulator. 1202: ; No flags are set by this so ignore them. 1203: 1204: (define_insn "tstsf" 1205: [(set (cc0) 1206: (match_operand:SF 0 "register_operand" "a"))] 1207: "" 1208: "tstf") 1209: 1210: 1211: ; tstdf compares a given value to a value already in the fpp accumulator. 1212: ; immediate doubles not allowed. Flags are ignored after this. 1213: 1214: (define_insn "tstdf" 1215: [(set (cc0) 1216: (match_operand:DF 0 "register_operand" "a"))] 1217: "" 1218: "tstd") 1219: 1220: 1221: 1222: ; movstrhi tahoe instruction does not load registers by itself like 1223: ; the vax counterpart does. registers 0-2 must be primed by hand. 1224: ; we have loaded the registers in the order: dst, src, count. 1225: 1226: (define_insn "movstrhi" 1227: [(set (match_operand:BLK 0 "general_operand" "p") 1228: (match_operand:BLK 1 "general_operand" "p")) 1229: (use (match_operand:HI 2 "general_operand" "g")) 1230: (clobber (reg:SI 0)) 1231: (clobber (reg:SI 1)) 1232: (clobber (reg:SI 2))] 1233: "" 1234: "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk") 1235: 1236: 1237: ; floatsisf2 on tahoe converts the long from reg/mem into the fpp 1238: ; accumulator. There are no hi and qi counterparts. Flags are not 1239: ; set correctly here. 1240: 1241: (define_insn "floatsisf2" 1242: [(set (match_operand:SF 0 "register_operand" "=a") 1243: (float:SF (match_operand:SI 1 "general_operand" "g")))] 1244: "" 1245: "* 1246: { 1247: CC_STATUS_INIT; 1248: return \"cvlf %1\"; 1249: }") 1250: 1251: 1252: ; floatsidf2 on tahoe converts the long from reg/mem into the fpp 1253: ; accumulator. There are no hi and qi counterparts. Flags are not 1254: ; set correctly here. 1255: 1256: (define_insn "floatsidf2" 1257: [(set (match_operand:DF 0 "register_operand" "=a") 1258: (float:DF (match_operand:SI 1 "general_operand" "g")))] 1259: "" 1260: "* 1261: { 1262: CC_STATUS_INIT; 1263: return \"cvld %1\"; 1264: }") 1265: 1266: 1267: ; fix_truncsfsi2 to convert a float to long, tahoe must have the float 1268: ; in the fpp accumulator. Flags are not set here. 1269: 1270: (define_insn "fix_truncsfsi2" 1271: [(set (match_operand:SI 0 "general_operand" "=g") 1272: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))] 1273: "" 1274: "* 1275: { 1276: CC_STATUS_INIT; 1277: return \"cvfl %0\"; 1278: }") 1279: 1280: 1281: ; fix_truncsfsi2 to convert a double to long, tahoe must have the double 1282: ; in the fpp accumulator. Flags are not set here. 1283: 1284: (define_insn "fix_truncdfsi2" 1285: [(set (match_operand:SI 0 "general_operand" "=g") 1286: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))] 1287: "" 1288: "* 1289: { 1290: CC_STATUS_INIT; 1291: return \"cvdl %0\"; 1292: }") 1293: 1294: 1295: (define_insn "truncsihi2" 1296: [(set (match_operand:HI 0 "general_operand" "=g") 1297: (truncate:HI (match_operand:SI 1 "general_operand" "g")))] 1298: "" 1299: "cvtlw %1,%0") 1300: 1301: 1302: (define_insn "truncsiqi2" 1303: [(set (match_operand:QI 0 "general_operand" "=g") 1304: (truncate:QI (match_operand:SI 1 "general_operand" "g")))] 1305: "" 1306: "cvtlb %1,%0") 1307: 1308: 1309: (define_insn "trunchiqi2" 1310: [(set (match_operand:QI 0 "general_operand" "=g") 1311: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] 1312: "" 1313: "cvtwb %1,%0") 1314: 1315: 1316: ; The fpp related instructions don't set flags, so ignore them 1317: ; after this instruction. 1318: 1319: (define_insn "truncdfsf2" 1320: [(set (match_operand:SF 0 "register_operand" "=a") 1321: (float_truncate:SF (match_operand:DF 1 "register_operand" "0")))] 1322: "" 1323: "* 1324: { 1325: CC_STATUS_INIT; 1326: return \"cvdf\"; 1327: }") 1328: 1329: 1330: ; This monster is to cover for the Tahoe's nasty habit of not extending 1331: ; a number if the source is in a register. (It just moves it!) Case 0 is 1332: ; a normal extend from memory. Case 1 does the extension from the top of 1333: ; the stack. Extension from the stack doesn't set the flags right since 1334: ; the moval changes them. 1335: 1336: (define_insn "extendhisi2" 1337: [(set (match_operand:SI 0 "general_operand" "=g,?=g") 1338: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 1339: "" 1340: "* 1341: { 1342: switch (which_alternative) 1343: { 1344: case 0: 1345: return \"cvtwl %1,%0\"; 1346: case 1: 1347: if (push_operand (operands[0], SImode)) 1348: return \"pushl %1\;cvtwl 2(sp),(sp)\"; 1349: else 1350: { 1351: CC_STATUS_INIT; 1352: return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\"; 1353: } 1354: } 1355: }") 1356: 1357: ; This monster is to cover for the Tahoe's nasty habit of not extending 1358: ; a number if the source is in a register. (It just moves it!) Case 0 is 1359: ; a normal extend from memory. Case 1 does the extension from the top of 1360: ; the stack. Extension from the stack doesn't set the flags right since 1361: ; the moval changes them. 1362: 1363: (define_insn "extendqisi2" 1364: [(set (match_operand:SI 0 "general_operand" "=g,?=g") 1365: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] 1366: "" 1367: "* 1368: { 1369: switch (which_alternative) 1370: { 1371: case 0: 1372: return \"cvtbl %1,%0\"; 1373: case 1: 1374: if (push_operand (operands[0], SImode)) 1375: return \"pushl %1\;cvtbl 3(sp),(sp)\"; 1376: else 1377: { 1378: CC_STATUS_INIT; 1379: return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\"; 1380: } 1381: } 1382: }") 1383: 1384: 1385: ; This monster is to cover for the Tahoe's nasty habit of not extending 1386: ; a number if the source is in a register. (It just moves it!) Case 0 is 1387: ; a normal extend from memory. Case 1 does the extension from the top of 1388: ; the stack. Extension from the stack doesn't set the flags right since 1389: ; the moval changes them. 1390: 1391: (define_insn "extendqihi2" 1392: [(set (match_operand:HI 0 "general_operand" "=g,?=g") 1393: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] 1394: "" 1395: "* 1396: { 1397: switch (which_alternative) 1398: { 1399: case 0: 1400: return \"cvtbw %1,%0\"; 1401: case 1: 1402: if (push_operand (operands[0], SImode)) 1403: return \"pushl %1\;cvtbw 3(sp),(sp)\"; 1404: else 1405: { 1406: CC_STATUS_INIT; 1407: return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\"; 1408: } 1409: } 1410: }") 1411: 1412: 1413: ; extendsfdf2 tahoe uses the fpp accumulator to do the extension. 1414: ; It takes a float and loads it up directly as a double. 1415: 1416: (define_insn "extendsfdf2" 1417: [(set (match_operand:DF 0 "register_operand" "=a") 1418: (float_extend:DF (match_operand:SF 1 "general_operand" "g")))] 1419: "" 1420: "* 1421: { 1422: CC_STATUS_INIT; 1423: return \"ldfd %1\"; 1424: }") 1425: 1426: 1427: ; movz works fine from memory but not from register for the same reasons 1428: ; the cvt instructions don't work right. So we use the normal instruction 1429: ; from memory and we use an and to simulate it from register. This is faster 1430: ; than pulling it off the stack. 1431: 1432: 1433: (define_insn "zero_extendhisi2" 1434: [(set (match_operand:SI 0 "general_operand" "=g,?=g") 1435: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))] 1436: "" 1437: "* 1438: { 1439: switch (which_alternative) 1440: { 1441: case 0: return \"movzwl %1,%0\"; 1442: case 1: return \"andl3 $0xffff,%1,%0\"; 1443: } 1444: }") 1445: 1446: ; movz works fine from memory but not from register for the same reasons 1447: ; the cvt instructions don't work right. So we use the normal instruction 1448: ; from memory and we use an and to simulate it from register. This is faster 1449: ; than pulling it off the stack. 1450: 1451: (define_insn "zero_extendqihi2" 1452: [(set (match_operand:HI 0 "general_operand" "=g,?=g") 1453: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] 1454: "" 1455: "* 1456: { 1457: switch (which_alternative) 1458: { 1459: case 0: return \"movzbw %1,%0\"; 1460: case 1: return \"andw3 $0xff,%1,%0\"; 1461: } 1462: }") 1463: 1464: 1465: ; movz works fine from memory but not from register for the same reasons 1466: ; the cvt instructions don't work right. So we use the normal instruction 1467: ; from memory and we use an and to simulate it from register. This is faster 1468: ; than pulling it off the stack. 1469: 1470: (define_insn "zero_extendqisi2" 1471: [(set (match_operand:SI 0 "general_operand" "=g,?=g") 1472: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))] 1473: "" 1474: "* 1475: { 1476: switch (which_alternative) 1477: { 1478: case 0: return \"movzbl %1,%0\"; 1479: case 1: return \"andl3 $0xff,%1,%0\"; 1480: } 1481: }") 1482: 1483: 1484: (define_insn "beq" 1485: [(set (pc) 1486: (if_then_else (eq (cc0) 1487: (const_int 0)) 1488: (label_ref (match_operand 0 "" "")) 1489: (pc)))] 1490: "" 1491: "jeql %l0") 1492: 1493: 1494: (define_insn "bne" 1495: [(set (pc) 1496: (if_then_else (ne (cc0) 1497: (const_int 0)) 1498: (label_ref (match_operand 0 "" "")) 1499: (pc)))] 1500: "" 1501: "jneq %l0") 1502: 1503: 1504: (define_insn "bgt" 1505: [(set (pc) 1506: (if_then_else (gt (cc0) 1507: (const_int 0)) 1508: (label_ref (match_operand 0 "" "")) 1509: (pc)))] 1510: "" 1511: "jgtr %l0") 1512: 1513: 1514: (define_insn "bgtu" 1515: [(set (pc) 1516: (if_then_else (gtu (cc0) 1517: (const_int 0)) 1518: (label_ref (match_operand 0 "" "")) 1519: (pc)))] 1520: "" 1521: "jgtru %l0") 1522: 1523: 1524: (define_insn "blt" 1525: [(set (pc) 1526: (if_then_else (lt (cc0) 1527: (const_int 0)) 1528: (label_ref (match_operand 0 "" "")) 1529: (pc)))] 1530: "" 1531: "jlss %l0") 1532: 1533: 1534: (define_insn "bltu" 1535: [(set (pc) 1536: (if_then_else (ltu (cc0) 1537: (const_int 0)) 1538: (label_ref (match_operand 0 "" "")) 1539: (pc)))] 1540: "" 1541: "jlssu %l0") 1542: 1543: 1544: (define_insn "bge" 1545: [(set (pc) 1546: (if_then_else (ge (cc0) 1547: (const_int 0)) 1548: (label_ref (match_operand 0 "" "")) 1549: (pc)))] 1550: "" 1551: "jgeq %l0") 1552: 1553: 1554: (define_insn "bgeu" 1555: [(set (pc) 1556: (if_then_else (geu (cc0) 1557: (const_int 0)) 1558: (label_ref (match_operand 0 "" "")) 1559: (pc)))] 1560: "" 1561: "jgequ %l0") 1562: 1563: 1564: (define_insn "ble" 1565: [(set (pc) 1566: (if_then_else (le (cc0) 1567: (const_int 0)) 1568: (label_ref (match_operand 0 "" "")) 1569: (pc)))] 1570: "" 1571: "jleq %l0") 1572: 1573: 1574: (define_insn "bleu" 1575: [(set (pc) 1576: (if_then_else (leu (cc0) 1577: (const_int 0)) 1578: (label_ref (match_operand 0 "" "")) 1579: (pc)))] 1580: "" 1581: "jlequ %l0") 1582: 1583: 1584: ; gcc does not account for register mask/argc longword. Thus the number 1585: ; for the call = number bytes for args + 4 1586: 1587: (define_insn "call" 1588: [(call (match_operand:QI 0 "memory_operand" "m") 1589: (match_operand:QI 1 "general_operand" "g"))] 1590: "" 1591: "* 1592: { 1593: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 4)); 1594: if (GET_CODE(operands[0]) == MEM 1595: && CONSTANT_ADDRESS_P (XEXP(operands[0], 0)) 1596: && INTVAL (operands[1]) < 64) 1597: return \"callf %1,%0\"; /* this is much faster */ 1598: return \"calls %1,%0\"; 1599: }") 1600: 1601: ; gcc does not account for register mask/argc longword. Thus the number 1602: ; for the call = number bytes for args + 4 1603: 1604: (define_insn "call_value" 1605: [(set (match_operand 0 "" "=g") 1606: (call (match_operand:QI 1 "memory_operand" "m") 1607: (match_operand:QI 2 "general_operand" "g")))] 1608: "" 1609: "* 1610: { 1611: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 4)); 1612: if (GET_CODE(operands[1]) == MEM 1613: && CONSTANT_ADDRESS_P (XEXP(operands[1], 0)) 1614: && INTVAL (operands[2]) < 64) 1615: return \"callf %2,%1\"; /* this is much faster */ 1616: return \"calls %2,%1\"; 1617: }") 1618: 1619: 1620: (define_insn "return" 1621: [(return)] 1622: "" 1623: "ret") 1624: 1625: (define_insn "nop" 1626: [(const_int 0)] 1627: "" 1628: "nop") 1629: 1630: ; casesi this code extracted from the vax code. The instructions are 1631: ; very similar. Tahoe requires that the table be word aligned. GCC 1632: ; places the table immediately after, thus the alignment directive. 1633: 1634: (define_insn "casesi" 1635: [(set (pc) 1636: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g") 1637: (match_operand:SI 1 "general_operand" "g")) 1638: (match_operand:SI 2 "general_operand" "g")) 1639: (plus:SI (sign_extend:SI 1640: (mem:HI (plus:SI (pc) 1641: (minus:SI (match_dup 0) 1642: (match_dup 1))))) 1643: (label_ref:SI (match_operand 3 "" ""))) 1644: (pc)))] 1645: "" 1646: "casel %0,%1,%2\;.align %@") 1647: 1648: 1649: (define_insn "jump" 1650: [(set (pc) 1651: (label_ref (match_operand 0 "" "")))] 1652: "" 1653: "jbr %l0") 1654: 1655: 1656: ;; This is the list of all the non-standard insn patterns 1657: 1658: 1659: ; This is used to access the address of a byte. This is similar to 1660: ; movqi, but the second operand had to be "address_operand" type, so 1661: ; it had to be an unnamed one. 1662: 1663: (define_insn "" 1664: [(set (match_operand:SI 0 "general_operand" "=g") 1665: (match_operand:QI 1 "address_operand" "p"))] 1666: "" 1667: "* 1668: { 1669: if (push_operand (operands[0], SImode)) 1670: return \"pushab %a1\"; 1671: return \"movab %a1,%0\"; 1672: }") 1673: 1674: ; This is used to access the address of a word. This is similar to 1675: ; movhi, but the second operand had to be "address_operand" type, so 1676: ; it had to be an unnamed one. 1677: 1678: (define_insn "" 1679: [(set (match_operand:SI 0 "general_operand" "=g") 1680: (match_operand:HI 1 "address_operand" "p"))] 1681: "" 1682: "* 1683: { 1684: if (push_operand (operands[0], SImode)) 1685: return \"pushaw %a1\"; 1686: return \"movaw %a1,%0\"; 1687: }") 1688: 1689: ; This is used to access the address of a long. This is similar to 1690: ; movsi, but the second operand had to be "address_operand" type, so 1691: ; it had to be an unnamed one. 1692: 1693: (define_insn "" 1694: [(set (match_operand:SI 0 "general_operand" "=g") 1695: (match_operand:SI 1 "address_operand" "p"))] 1696: "" 1697: "* 1698: { 1699: if (push_operand (operands[0], SImode)) 1700: return \"pushal %a1\"; 1701: return \"moval %a1,%0\"; 1702: }") 1703: 1704: 1705: ; bit test longword instruction, same as vax 1706: 1707: (define_insn "" 1708: [(set (cc0) 1709: (and:SI (match_operand:SI 0 "general_operand" "g") 1710: (match_operand:SI 1 "general_operand" "g")))] 1711: "" 1712: "bitl %0,%1") 1713: 1714: 1715: ; bit test word instructions, same as vax 1716: 1717: (define_insn "" 1718: [(set (cc0) 1719: (and:HI (match_operand:HI 0 "general_operand" "g") 1720: (match_operand:HI 1 "general_operand" "g")))] 1721: "" 1722: "bitw %0,%1") 1723: 1724: 1725: ; bit test instructions, same as vax 1726: 1727: (define_insn "" 1728: [(set (cc0) 1729: (and:QI (match_operand:QI 0 "general_operand" "g") 1730: (match_operand:QI 1 "general_operand" "g")))] 1731: "" 1732: "bitb %0,%1") 1733: 1734: 1735: ; bne counterpart. in case gcc reverses the conditional. 1736: 1737: (define_insn "" 1738: [(set (pc) 1739: (if_then_else (eq (cc0) 1740: (const_int 0)) 1741: (pc) 1742: (label_ref (match_operand 0 "" ""))))] 1743: "" 1744: "jneq %l0") 1745: 1746: 1747: ; beq counterpart. in case gcc reverses the conditional. 1748: 1749: (define_insn "" 1750: [(set (pc) 1751: (if_then_else (ne (cc0) 1752: (const_int 0)) 1753: (pc) 1754: (label_ref (match_operand 0 "" ""))))] 1755: "" 1756: "jeql %l0") 1757: 1758: 1759: ; ble counterpart. in case gcc reverses the conditional. 1760: 1761: (define_insn "" 1762: [(set (pc) 1763: (if_then_else (gt (cc0) 1764: (const_int 0)) 1765: (pc) 1766: (label_ref (match_operand 0 "" ""))))] 1767: "" 1768: "jleq %l0") 1769: 1770: 1771: ; bleu counterpart. in case gcc reverses the conditional. 1772: 1773: (define_insn "" 1774: [(set (pc) 1775: (if_then_else (gtu (cc0) 1776: (const_int 0)) 1777: (pc) 1778: (label_ref (match_operand 0 "" ""))))] 1779: "" 1780: "jlequ %l0") 1781: 1782: 1783: ; bge counterpart. in case gcc reverses the conditional. 1784: 1785: (define_insn "" 1786: [(set (pc) 1787: (if_then_else (lt (cc0) 1788: (const_int 0)) 1789: (pc) 1790: (label_ref (match_operand 0 "" ""))))] 1791: "" 1792: "jgeq %l0") 1793: 1794: 1795: ; bgeu counterpart. in case gcc reverses the conditional. 1796: 1797: (define_insn "" 1798: [(set (pc) 1799: (if_then_else (ltu (cc0) 1800: (const_int 0)) 1801: (pc) 1802: (label_ref (match_operand 0 "" ""))))] 1803: "" 1804: "jgequ %l0") 1805: 1806: 1807: ; blt counterpart. in case gcc reverses the conditional. 1808: 1809: (define_insn "" 1810: [(set (pc) 1811: (if_then_else (ge (cc0) 1812: (const_int 0)) 1813: (pc) 1814: (label_ref (match_operand 0 "" ""))))] 1815: "" 1816: "jlss %l0") 1817: 1818: 1819: ; bltu counterpart. in case gcc reverses the conditional. 1820: 1821: (define_insn "" 1822: [(set (pc) 1823: (if_then_else (geu (cc0) 1824: (const_int 0)) 1825: (pc) 1826: (label_ref (match_operand 0 "" ""))))] 1827: "" 1828: "jlssu %l0") 1829: 1830: 1831: ; bgt counterpart. in case gcc reverses the conditional. 1832: 1833: (define_insn "" 1834: [(set (pc) 1835: (if_then_else (le (cc0) 1836: (const_int 0)) 1837: (pc) 1838: (label_ref (match_operand 0 "" ""))))] 1839: "" 1840: "jgtr %l0") 1841: 1842: 1843: ; bgtu counterpart. in case gcc reverses the conditional. 1844: 1845: (define_insn "" 1846: [(set (pc) 1847: (if_then_else (leu (cc0) 1848: (const_int 0)) 1849: (pc) 1850: (label_ref (match_operand 0 "" ""))))] 1851: "" 1852: "jgtru %l0") 1853: 1854: 1855: ; casesi alternate form as found in vax code. this form is to 1856: ; compensate for the table's offset being no distance (0 displacement) 1857: 1858: (define_insn "" 1859: [(set (pc) 1860: (if_then_else (le (match_operand:SI 0 "general_operand" "g") 1861: (match_operand:SI 1 "general_operand" "g")) 1862: (plus:SI (sign_extend:SI 1863: (mem:HI (plus:SI (pc) 1864: (minus:SI (match_dup 0) 1865: (const_int 0))))) 1866: (label_ref:SI (match_operand 3 "" ""))) 1867: (pc)))] 1868: "" 1869: "casel %0,$0,%1\;.align %@") 1870: 1871: 1872: ; casesi alternate form as found in vax code. another form to 1873: ; compensate for the table's offset being no distance (0 displacement) 1874: 1875: (define_insn "" 1876: [(set (pc) 1877: (if_then_else (le (match_operand:SI 0 "general_operand" "g") 1878: (match_operand:SI 1 "general_operand" "g")) 1879: (plus:SI (sign_extend:SI 1880: (mem:HI (plus:SI (pc) 1881: (match_dup 0)))) 1882: (label_ref:SI (match_operand 3 "" ""))) 1883: (pc)))] 1884: "" 1885: "casel %0,$0,%1 \;.align %@") 1886: 1887: (define_insn "" 1888: [(set (pc) 1889: (if_then_else 1890: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g") 1891: (const_int 1)) 1892: (match_operand:SI 1 "general_operand" "g")) 1893: (label_ref (match_operand 2 "" "")) 1894: (pc))) 1895: (set (match_dup 0) 1896: (plus:SI (match_dup 0) 1897: (const_int 1)))] 1898: "" 1899: "aoblss %1,%0,%l2") 1900: 1901: (define_insn "" 1902: [(set (pc) 1903: (if_then_else 1904: (le (plus:SI (match_operand:SI 0 "general_operand" "+g") 1905: (const_int 1)) 1906: (match_operand:SI 1 "general_operand" "g")) 1907: (label_ref (match_operand 2 "" "")) 1908: (pc))) 1909: (set (match_dup 0) 1910: (plus:SI (match_dup 0) 1911: (const_int 1)))] 1912: "" 1913: "aobleq %1,%0,%l2") 1914: 1915: (define_insn "" 1916: [(set (pc) 1917: (if_then_else 1918: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") 1919: (const_int 1)) 1920: (match_operand:SI 1 "general_operand" "g")) 1921: (pc) 1922: (label_ref (match_operand 2 "" "")))) 1923: (set (match_dup 0) 1924: (plus:SI (match_dup 0) 1925: (const_int 1)))] 1926: "" 1927: "aoblss %1,%0,%l2") 1928: 1929: (define_insn "" 1930: [(set (pc) 1931: (if_then_else 1932: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g") 1933: (const_int 1)) 1934: (match_operand:SI 1 "general_operand" "g")) 1935: (pc) 1936: (label_ref (match_operand 2 "" "")))) 1937: (set (match_dup 0) 1938: (plus:SI (match_dup 0) 1939: (const_int 1)))] 1940: "" 1941: "aobleq %1,%0,%l2") 1942: 1943: ; bbs/bbc 1944: 1945: (define_insn "" 1946: [(set (pc) 1947: (if_then_else 1948: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 1949: (const_int 1) 1950: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) 1951: (const_int 0)) 1952: (label_ref (match_operand 2 "" "")) 1953: (pc)))] 1954: "" 1955: "bbs %1,%0,%l2") 1956: 1957: (define_insn "" 1958: [(set (pc) 1959: (if_then_else 1960: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 1961: (const_int 1) 1962: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) 1963: (const_int 0)) 1964: (label_ref (match_operand 2 "" "")) 1965: (pc)))] 1966: "" 1967: "bbc %1,%0,%l2") 1968: 1969: (define_insn "" 1970: [(set (pc) 1971: (if_then_else 1972: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 1973: (const_int 1) 1974: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) 1975: (const_int 0)) 1976: (pc) 1977: (label_ref (match_operand 2 "" ""))))] 1978: "" 1979: "bbc %1,%0,%l2") 1980: 1981: (define_insn "" 1982: [(set (pc) 1983: (if_then_else 1984: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 1985: (const_int 1) 1986: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0)) 1987: (const_int 0)) 1988: (pc) 1989: (label_ref (match_operand 2 "" ""))))] 1990: "" 1991: "bbs %1,%0,%l2") 1992: 1993: ; if the shift count is a byte in a register we can use it as a long 1994: 1995: (define_insn "" 1996: [(set (pc) 1997: (if_then_else 1998: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 1999: (const_int 1) 2000: (match_operand:QI 1 "register_operand" "r")) 2001: (const_int 0)) 2002: (label_ref (match_operand 2 "" "")) 2003: (pc)))] 2004: "" 2005: "bbs %1,%0,%l2") 2006: 2007: (define_insn "" 2008: [(set (pc) 2009: (if_then_else 2010: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 2011: (const_int 1) 2012: (match_operand:QI 1 "register_operand" "r")) 2013: (const_int 0)) 2014: (label_ref (match_operand 2 "" "")) 2015: (pc)))] 2016: "" 2017: "bbc %1,%0,%l2") 2018: 2019: (define_insn "" 2020: [(set (pc) 2021: (if_then_else 2022: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 2023: (const_int 1) 2024: (match_operand:QI 1 "register_operand" "r")) 2025: (const_int 0)) 2026: (pc) 2027: (label_ref (match_operand 2 "" ""))))] 2028: "" 2029: "bbc %1,%0,%l2") 2030: 2031: (define_insn "" 2032: [(set (pc) 2033: (if_then_else 2034: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm") 2035: (const_int 1) 2036: (match_operand:QI 1 "register_operand" "r")) 2037: (const_int 0)) 2038: (pc) 2039: (label_ref (match_operand 2 "" ""))))] 2040: "" 2041: "bbs %1,%0,%l2") 2042: 2043: ; special case for 1 << constant. We don't do these because they are slower 2044: ; than the bitl instruction 2045: 2046: ;(define_insn "" 2047: ; [(set (pc) 2048: ; (if_then_else 2049: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") 2050: ; (match_operand:SI 1 "immediate_operand" "i")) 2051: ; (const_int 0)) 2052: ; (label_ref (match_operand 2 "" "")) 2053: ; (pc)))] 2054: ; "GET_CODE (operands[1]) == CONST_INT 2055: ; && exact_log2 (INTVAL (operands[1])) >= 0" 2056: ; "* 2057: ;{ 2058: ; operands[1] 2059: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 2060: ; return \"bbs %1,%0,%l2\"; 2061: ;}") 2062: ; 2063: ;(define_insn "" 2064: ; [(set (pc) 2065: ; (if_then_else 2066: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") 2067: ; (match_operand:SI 1 "immediate_operand" "i")) 2068: ; (const_int 0)) 2069: ; (label_ref (match_operand 2 "" "")) 2070: ; (pc)))] 2071: ; "GET_CODE (operands[1]) == CONST_INT 2072: ; && exact_log2 (INTVAL (operands[1])) >= 0" 2073: ; "* 2074: ;{ 2075: ; operands[1] 2076: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 2077: ; return \"bbc %1,%0,%l2\"; 2078: ;}") 2079: ; 2080: ;(define_insn "" 2081: ; [(set (pc) 2082: ; (if_then_else 2083: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") 2084: ; (match_operand:SI 1 "immediate_operand" "i")) 2085: ; (const_int 0)) 2086: ; (pc) 2087: ; (label_ref (match_operand 2 "" ""))))] 2088: ; "GET_CODE (operands[1]) == CONST_INT 2089: ; && exact_log2 (INTVAL (operands[1])) >= 0" 2090: ; "* 2091: ;{ 2092: ; operands[1] 2093: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 2094: ; return \"bbc %1,%0,%l2\"; 2095: ;}") 2096: ; 2097: ;(define_insn "" 2098: ; [(set (pc) 2099: ; (if_then_else 2100: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") 2101: ; (match_operand:SI 1 "immediate_operand" "i")) 2102: ; (const_int 0)) 2103: ; (pc) 2104: ; (label_ref (match_operand 2 "" ""))))] 2105: ; "GET_CODE (operands[1]) == CONST_INT 2106: ; && exact_log2 (INTVAL (operands[1])) >= 0" 2107: ; "* 2108: ;{ 2109: ; operands[1] 2110: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 2111: ; return \"bbs %1,%0,%l2\"; 2112: ;}")
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