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1.1 root 1: /* Definitions of target machine for GNU compiler. Alliant FX version.
2: Copyright (C) 1989 Free Software Foundation, Inc.
3: Adapted from tm-m68k.h by Paul Petersen ([email protected])
4: and Joe Weening ([email protected]).
5:
6: This file is part of GNU CC.
7:
8: GNU CC is free software; you can redistribute it and/or modify
9: it under the terms of the GNU General Public License as published by
10: the Free Software Foundation; either version 1, or (at your option)
11: any later version.
12:
13: GNU CC is distributed in the hope that it will be useful,
14: but WITHOUT ANY WARRANTY; without even the implied warranty of
15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: GNU General Public License for more details.
17:
18: You should have received a copy of the GNU General Public License
19: along with GNU CC; see the file COPYING. If not, write to
20: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21:
22:
23: /* This file is based on tm-m68k.h, simplified by removing support for
24: the Sun FPA and other things not applicable to the Alliant. Some
25: remnants of these features remain. */
26:
27: /* Names to predefine in the preprocessor for this target machine. */
28:
29: #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix"
30:
31: /* Print subsidiary information on the compiler version in use. */
32:
33: #define TARGET_VERSION fprintf (stderr, " (Alliant)");
34:
35: /* Run-time compilation parameters selecting different hardware
36: subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs
37: are no longer supported.) The Alliant CE is 68020-compatible, and
38: also has floating point, vector and concurrency instructions.
39:
40: Although the IP doesn't have floating point, it emulates it in the
41: operating system. Using this generally is faster than running code
42: compiled with -msoft-float, because the soft-float code still uses
43: (simulated) FP registers and ends up emulating several fmove{s,d}
44: instructions per call. So I don't recommend using soft-float for
45: any Alliant code. -- JSW
46: */
47:
48: extern int target_flags;
49:
50: /* Macros used in the machine description to test the flags. */
51:
52: /* Compile for a 68020 (not a 68000 or 68010). */
53: #define TARGET_68020 (target_flags & 1)
54: /* Compile CE insns for floating point (not library calls). */
55: #define TARGET_CE (target_flags & 2)
56: /* Compile using 68020 bitfield insns. */
57: #define TARGET_BITFIELD (target_flags & 4)
58: /* Compile with 16-bit `int'. */
59: #define TARGET_SHORT (target_flags & 040)
60:
61: /* Default 3 means compile 68020 and CE instructions. We don't use
62: bitfield instructions because there appears to be a bug in the
63: implementation of bfins on the CE. */
64:
65: #define TARGET_DEFAULT 3
66:
67: /* Define __HAVE_CE__ in preprocessor according to the -m flags.
68: This will control the use of inline FP insns in certain macros.
69: Also inform the program which CPU this is for. */
70:
71: #if TARGET_DEFAULT & 02
72:
73: /* -mce is the default */
74: #define CPP_SPEC \
75: "%{!msoft-float:-D__HAVE_CE__ }\
76: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
77:
78: #else
79:
80: /* -msoft-float is the default */
81: #define CPP_SPEC \
82: "%{mce:-D__HAVE_CE__ }\
83: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
84:
85: #endif
86:
87: /* Every structure or union's size must be a multiple of 2 bytes. */
88:
89: #define STRUCTURE_SIZE_BOUNDARY 16
90:
91: /* This is BSD, so it wants DBX format. */
92:
93: #define DBX_DEBUGGING_INFO
94:
95: /* Macro to define tables used to set the flags.
96: This is a list in braces of pairs in braces,
97: each pair being { "NAME", VALUE }
98: where VALUE is the bits to set or minus the bits to clear.
99: An empty string NAME is used to identify the default VALUE. */
100:
101: #define TARGET_SWITCHES \
102: { { "68020", 5}, \
103: { "c68020", 5}, \
104: { "bitfield", 4}, \
105: { "68000", -7}, \
106: { "c68000", -7}, \
107: { "soft-float", -2}, \
108: { "nobitfield", -4}, \
109: { "short", 040}, \
110: { "noshort", -040}, \
111: { "", TARGET_DEFAULT}}
112:
113: /* target machine storage layout */
114:
115: /* Define this if most significant bit is lowest numbered
116: in instructions that operate on numbered bit-fields.
117: This is true for 68020 insns such as bfins and bfexts.
118: We make it true always by avoiding using the single-bit insns
119: except in special cases with constant bit numbers. */
120: #define BITS_BIG_ENDIAN
121:
122: /* Define this if most significant byte of a word is the lowest numbered. */
123: /* That is true on the 68000. */
124: #define BYTES_BIG_ENDIAN
125:
126: /* Define this if most significant word of a multiword number is numbered. */
127: /* For 68000 we can decide arbitrarily
128: since there are no machine instructions for them. */
129: /* #define WORDS_BIG_ENDIAN */
130:
131: /* number of bits in an addressible storage unit */
132: #define BITS_PER_UNIT 8
133:
134: /* Width in bits of a "word", which is the contents of a machine register.
135: Note that this is not necessarily the width of data type `int';
136: if using 16-bit ints on a 68000, this would still be 32.
137: But on a machine with 16-bit registers, this would be 16. */
138: #define BITS_PER_WORD 32
139:
140: /* Width of a word, in units (bytes). */
141: #define UNITS_PER_WORD 4
142:
143: /* Width in bits of a pointer.
144: See also the macro `Pmode' defined below. */
145: #define POINTER_SIZE 32
146:
147: /* Allocation boundary (in *bits*) for storing pointers in memory. */
148: #define POINTER_BOUNDARY 16
149:
150: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
151: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
152:
153: /* Boundary (in *bits*) on which stack pointer should be aligned. */
154: #define STACK_BOUNDARY 16
155:
156: /* Allocation boundary (in *bits*) for the code of a function. */
157: #define FUNCTION_BOUNDARY 16
158:
159: /* Alignment of field after `int : 0' in a structure. */
160: #define EMPTY_FIELD_BOUNDARY 16
161:
162: /* No data type wants to be aligned rounder than this. */
163: #define BIGGEST_ALIGNMENT 16
164:
165: /* Define this if move instructions will actually fail to work
166: when given unaligned data. */
167: #define STRICT_ALIGNMENT
168:
169: /* Define number of bits in most basic integer type.
170: (If undefined, default is BITS_PER_WORD). */
171:
172: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
173:
174: /* Standard register usage. */
175:
176: /* Number of actual hardware registers.
177: The hardware registers are assigned numbers for the compiler
178: from 0 to just below FIRST_PSEUDO_REGISTER.
179: All registers that the compiler knows about must be given numbers,
180: even those that are not normally considered general registers.
181: For the Alliant, we give the data registers numbers 0-7,
182: the address registers numbers 010-017,
183: and the floating point registers numbers 020-027. */
184: #define FIRST_PSEUDO_REGISTER 24
185:
186: /* 1 for registers that have pervasive standard uses
187: and are not available for the register allocator.
188: On the Alliant, these are a0 (argument pointer),
189: a6 (frame pointer) and a7 (stack pointer). */
190: #define FIXED_REGISTERS \
191: {0, 0, 0, 0, 0, 0, 0, 0, \
192: 1, 0, 0, 0, 0, 0, 1, 1, \
193: 0, 0, 0, 0, 0, 0, 0, 0 }
194:
195: /* 1 for registers not available across function calls.
196: These must include the FIXED_REGISTERS and also any
197: registers that can be used without being saved.
198: The latter must include the registers where values are returned
199: and the register where structure-value addresses are passed.
200: Aside from that, you can include as many other registers as you like.
201: The Alliant calling sequence allows a function to use any register,
202: so we include them all here. */
203:
204: #define CALL_USED_REGISTERS \
205: {1, 1, 1, 1, 1, 1, 1, 1, \
206: 1, 1, 1, 1, 1, 1, 1, 1, \
207: 1, 1, 1, 1, 1, 1, 1, 1 }
208:
209: /* Return number of consecutive hard regs needed starting at reg REGNO
210: to hold something of mode MODE.
211: This is ordinarily the length in words of a value of mode MODE
212: but can be less for certain modes in special long registers.
213:
214: On the Alliant, ordinary registers hold 32 bits worth;
215: for the FP registers, a single register is always enough for
216: anything that can be stored in them at all. */
217: #define HARD_REGNO_NREGS(REGNO, MODE) \
218: ((REGNO) >= 16 ? 1 \
219: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
220:
221: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
222: On the Alliant, the cpu registers can hold any mode but the FP registers
223: can hold only SFmode or DFmode. */
224: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
225: ((REGNO) < 16 || (MODE) == SFmode || (MODE) == DFmode)
226:
227: /* Value is 1 if it is a good idea to tie two pseudo registers
228: when one has mode MODE1 and one has mode MODE2.
229: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
230: for any hard reg, then this must be 0 for correct output. */
231: #define MODES_TIEABLE_P(MODE1, MODE2) \
232: (((MODE1) == SFmode || (MODE1) == DFmode) \
233: == ((MODE2) == SFmode || (MODE2) == DFmode))
234:
235: /* Specify the registers used for certain standard purposes.
236: The values of these macros are register numbers. */
237:
238: /* m68000 pc isn't overloaded on a register. */
239: /* #define PC_REGNUM */
240:
241: /* Register to use for pushing function arguments. */
242: #define STACK_POINTER_REGNUM 15
243:
244: /* Base register for access to local variables of the function. */
245: #define FRAME_POINTER_REGNUM 14
246:
247: /* Value should be nonzero if functions must have frame pointers.
248: Zero means the frame pointer need not be set up (and parms
249: may be accessed via the stack pointer) in functions that seem suitable.
250: This is computed in `reload', in reload1.c. */
251: /* Set for now on Alliant until we find a way to make this work with
252: their calling sequence. */
253: #define FRAME_POINTER_REQUIRED 1
254:
255: /* Base register for access to arguments of the function. */
256: #define ARG_POINTER_REGNUM 8
257:
258: /* Register in which static-chain is passed to a function. */
259: #define STATIC_CHAIN_REGNUM 8
260:
261: /* Register in which address to store a structure value
262: is passed to a function. */
263: #define STRUCT_VALUE_REGNUM 9
264:
265: /* Define the classes of registers for register constraints in the
266: machine description. Also define ranges of constants.
267:
268: One of the classes must always be named ALL_REGS and include all hard regs.
269: If there is more than one class, another class must be named NO_REGS
270: and contain no registers.
271:
272: The name GENERAL_REGS must be the name of a class (or an alias for
273: another name such as ALL_REGS). This is the class of registers
274: that is allowed by "g" or "r" in a register constraint.
275: Also, registers outside this class are allocated only when
276: instructions express preferences for them.
277:
278: The classes must be numbered in nondecreasing order; that is,
279: a larger-numbered class must never be contained completely
280: in a smaller-numbered class.
281:
282: For any two classes, it is very desirable that there be another
283: class that represents their union. */
284:
285: /* The Alliant has three kinds of registers, so eight classes would be
286: a complete set. One of them is not needed. */
287:
288: enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS,
289: ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
290:
291: #define N_REG_CLASSES (int) LIM_REG_CLASSES
292:
293: /* Give names of register classes as strings for dump file. */
294:
295: #define REG_CLASS_NAMES \
296: { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS", \
297: "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }
298:
299: /* Define which registers fit in which classes.
300: This is an initializer for a vector of HARD_REG_SET
301: of length N_REG_CLASSES. */
302:
303: #define REG_CLASS_CONTENTS \
304: { \
305: 0, /* NO_REGS */ \
306: 0x00ff0000, /* FP_REGS */ \
307: 0x000000ff, /* DATA_REGS */ \
308: 0x00ff00ff, /* DATA_OR_FP_REGS */ \
309: 0x0000ff00, /* ADDR_REGS */ \
310: 0x0000ffff, /* GENERAL_REGS */ \
311: 0x00ffffff /* ALL_REGS */ \
312: }
313:
314: /* The same information, inverted:
315: Return the class number of the smallest class containing
316: reg number REGNO. This could be a conditional expression
317: or could index an array. */
318:
319: extern enum reg_class regno_reg_class[];
320: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
321:
322: /* The class value for index registers, and the one for base regs. */
323:
324: #define INDEX_REG_CLASS GENERAL_REGS
325: #define BASE_REG_CLASS ADDR_REGS
326:
327: /* Get reg_class from a letter such as appears in the machine description. */
328:
329: #define REG_CLASS_FROM_LETTER(C) \
330: ((C) == 'a' ? ADDR_REGS : \
331: ((C) == 'd' ? DATA_REGS : \
332: ((C) == 'f' ? FP_REGS : \
333: NO_REGS)))
334:
335: /* The letters I, J, K, L and M in a register constraint string
336: can be used to stand for particular ranges of immediate operands.
337: This macro defines what the ranges are.
338: C is the letter, and VALUE is a constant value.
339: Return 1 if VALUE is in the range specified by C.
340:
341: For the 68000, `I' is used for the range 1 to 8
342: allowed as immediate shift counts and in addq.
343: `J' is used for the range of signed numbers that fit in 16 bits.
344: `K' is for numbers that moveq can't handle.
345: `L' is for range -8 to -1, range of values that can be added with subq. */
346:
347: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
348: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
349: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
350: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
351: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
352:
353: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
354:
355: /* Given an rtx X being reloaded into a reg required to be
356: in class CLASS, return the class of reg to actually use.
357: In general this is just CLASS; but on some machines
358: in some cases it is preferable to use a more restrictive class.
359: On the 68000 series, use a data reg if possible when the
360: value is a constant in the range where moveq could be used
361: and we ensure that QImodes are reloaded into data regs. */
362:
363: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
364: ((GET_CODE (X) == CONST_INT \
365: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
366: && (CLASS) != ADDR_REGS) \
367: ? DATA_REGS \
368: : GET_MODE (X) == QImode \
369: ? DATA_REGS \
370: : (CLASS))
371:
372: /* Return the maximum number of consecutive registers
373: needed to represent mode MODE in a register of class CLASS. */
374: /* On the 68000, this is the size of MODE in words,
375: except in the FP regs, where a single reg is always enough. */
376: #define CLASS_MAX_NREGS(CLASS, MODE) \
377: ((CLASS) == FP_REGS ? 1 \
378: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
379:
380: /* Stack layout; function entry, exit and calling. */
381:
382: /* Define this if pushing a word on the stack
383: makes the stack pointer a smaller address. */
384: #define STACK_GROWS_DOWNWARD
385:
386: /* Define this if the nominal address of the stack frame
387: is at the high-address end of the local variables;
388: that is, each additional local variable allocated
389: goes at a more negative offset in the frame. */
390: #define FRAME_GROWS_DOWNWARD
391:
392: /* The Alliant uses -fcaller-saves by default. */
393: #define DEFAULT_CALLER_SAVES
394:
395: /* Offset within stack frame to start allocating local variables at.
396: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
397: first local allocated. Otherwise, it is the offset to the BEGINNING
398: of the first local allocated. */
399: #define STARTING_FRAME_OFFSET -4
400:
401: /* If we generate an insn to push BYTES bytes,
402: this says how many the stack pointer really advances by.
403: On the 68000, sp@- in a byte insn really pushes a word. */
404: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
405:
406: /* Offset of first parameter from the argument pointer register value. */
407: #define FIRST_PARM_OFFSET(FNDECL) 0
408:
409: /* Value is 1 if returning from a function call automatically
410: pops the arguments described by the number-of-args field in the call.
411: FUNTYPE is the data type of the function (as a tree),
412: or for a library call it is an identifier node for the subroutine name.
413:
414: On the Alliant we define this as 1 and make the calling sequence
415: (in alliant.md) pop the args. This wouldn't be necessary if we
416: could add to the pending stack adjustment the size of the argument
417: descriptors that are pushed after the arguments. */
418:
419: #define RETURN_POPS_ARGS(FUNTYPE) 1
420:
421: /* Define how to find the value returned by a function.
422: VALTYPE is the data type of the value (as a tree).
423: If the precise function being called is known, FUNC is its FUNCTION_DECL;
424: otherwise, FUNC is 0. */
425:
426: /* On the Alliant the return value is in FP0 if real, else D0. */
427:
428: #define FUNCTION_VALUE(VALTYPE, FUNC) \
429: (TREE_CODE (VALTYPE) == REAL_TYPE \
430: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
431: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
432:
433: /* Define how to find the value returned by a library function
434: assuming the value has mode MODE. */
435:
436: /* On the Alliant the return value is in FP0 if real, else D0. The
437: Alliant library functions for floating-point emulation return their
438: values both in FP0 and in D0/D1. But since not all gnulib functions
439: return the results of these directly, we cannot assume that D0/D1
440: contain the values we expect on return from a gnulib function. */
441:
442: #define LIBCALL_VALUE(MODE) \
443: (((MODE) == DFmode || (MODE) == SFmode) \
444: ? gen_rtx (REG, MODE, 16) \
445: : gen_rtx (REG, MODE, 0))
446:
447: /* 1 if N is a possible register number for a function value.
448: On the Alliant, D0 and FP0 are the only registers thus used.
449: (No need to mention D1 when used as a pair with D0.) */
450:
451: #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0)
452:
453: /* Define this if PCC uses the nonreentrant convention for returning
454: structure and union values. */
455:
456: #define PCC_STATIC_STRUCT_RETURN
457:
458: /* 1 if N is a possible register number for function argument passing.
459: On the Alliant, no registers are used in this way. */
460:
461: #define FUNCTION_ARG_REGNO_P(N) 0
462:
463: /* Define a data type for recording info about an argument list
464: during the scan of that argument list. This data type should
465: hold all necessary information about the function itself
466: and about the args processed so far, enough to enable macros
467: such as FUNCTION_ARG to determine where the next arg should go.
468:
469: On the Alliant, this is a single integer, which is a number of bytes
470: of arguments scanned so far. */
471:
472: #define CUMULATIVE_ARGS int
473:
474: /* Initialize a variable CUM of type CUMULATIVE_ARGS
475: for a call to a function whose data type is FNTYPE.
476: For a library call, FNTYPE is 0.
477:
478: On the Alliant, the offset starts at 0. */
479:
480: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE) \
481: ((CUM) = 0)
482:
483: /* Update the data in CUM to advance over an argument
484: of mode MODE and data type TYPE.
485: (TYPE is null for libcalls where that information may not be available.) */
486:
487: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
488: ((CUM) += ((MODE) != BLKmode \
489: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
490: : (int_size_in_bytes (TYPE) + 3) & ~3))
491:
492: /* Define where to put the arguments to a function.
493: Value is zero to push the argument on the stack,
494: or a hard register in which to store the argument.
495:
496: MODE is the argument's machine mode.
497: TYPE is the data type of the argument (as a tree).
498: This is null for libcalls where that information may
499: not be available.
500: CUM is a variable of type CUMULATIVE_ARGS which gives info about
501: the preceding args and about the function being called.
502: NAMED is nonzero if this argument is a named parameter
503: (otherwise it is an extra parameter matching an ellipsis). */
504:
505: /* On the Alliant all args are pushed. */
506:
507: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
508:
509: /* For an arg passed partly in registers and partly in memory,
510: this is the number of registers used.
511: For args passed entirely in registers or entirely in memory, zero. */
512:
513: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
514:
515: /* This macro generates the assembly code for function entry.
516: FILE is a stdio stream to output the code to.
517: SIZE is an int: how many units of temporary storage to allocate.
518: Refer to the array `regs_ever_live' to determine which registers
519: to save; `regs_ever_live[I]' is nonzero if register number I
520: is ever used in the function. This macro is responsible for
521: knowing which registers should not be saved even if used.
522: The Alliant uses caller-saves, so this macro is very simple. */
523:
524: #define FUNCTION_PROLOGUE(FILE, SIZE) \
525: { int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4; \
526: if (frame_pointer_needed) { \
527: if (TARGET_68020 || fsize < 0x8000) \
528: fprintf(FILE,"\tlink a6,#%d\n", -fsize); \
529: else \
530: fprintf(FILE,"\tlink a6,#0\n\tsubl #%d,sp\n", fsize); \
531: fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }}
532:
533: /* Output assembler code to FILE to increment profiler label # LABELNO
534: for profiling a function entry. */
535:
536: #define FUNCTION_PROFILER(FILE, LABELNO) \
537: fprintf (FILE, "\tjbsr __mcount_\n")
538:
539: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
540: the stack pointer does not matter. The value is tested only in
541: functions that have frame pointers.
542: No definition is equivalent to always zero. */
543:
544: #define EXIT_IGNORE_STACK 1
545:
546: /* This macro generates the assembly code for function exit,
547: on machines that need it. If FUNCTION_EPILOGUE is not defined
548: then individual return instructions are generated for each
549: return statement. Args are same as for FUNCTION_PROLOGUE.
550:
551: The function epilogue should not depend on the current stack pointer!
552: It should use the frame pointer only. This is mandatory because
553: of alloca; we also take advantage of it to omit stack adjustments
554: before returning. */
555:
556: #define FUNCTION_EPILOGUE(FILE, SIZE) \
557: { if (frame_pointer_needed) \
558: fprintf (FILE, "\tunlk a6\n"); \
559: fprintf (FILE, "\trts\n"); }
560:
561: /* If the memory address ADDR is relative to the frame pointer,
562: correct it to be relative to the stack pointer instead.
563: This is for when we don't use a frame pointer.
564: ADDR should be a variable name. */
565:
566: #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
567: { int offset = -1; \
568: rtx regs = stack_pointer_rtx; \
569: if (ADDR == frame_pointer_rtx) \
570: offset = 0; \
571: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
572: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
573: offset = INTVAL (XEXP (ADDR, 1)); \
574: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
575: { rtx other_reg = XEXP (ADDR, 1); \
576: offset = 0; \
577: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
578: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
579: { rtx other_reg = XEXP (ADDR, 0); \
580: offset = 0; \
581: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
582: else if (GET_CODE (ADDR) == PLUS \
583: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
584: && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
585: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
586: { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
587: offset = INTVAL (XEXP (ADDR, 1)); \
588: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
589: else if (GET_CODE (ADDR) == PLUS \
590: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
591: && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
592: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
593: { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
594: offset = INTVAL (XEXP (ADDR, 1)); \
595: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
596: if (offset >= 0) \
597: { int regno; \
598: extern char call_used_regs[]; \
599: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
600: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
601: offset += 12; \
602: for (regno = 0; regno < 16; regno++) \
603: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
604: offset += 4; \
605: offset -= 4; \
606: ADDR = plus_constant (regs, offset + (DEPTH)); } } \
607:
608: /* Addressing modes, and classification of registers for them. */
609:
610: #define HAVE_POST_INCREMENT
611: /* #define HAVE_POST_DECREMENT */
612:
613: #define HAVE_PRE_DECREMENT
614: /* #define HAVE_PRE_INCREMENT */
615:
616: /* Macros to check register numbers against specific register classes. */
617:
618: /* These assume that REGNO is a hard or pseudo reg number.
619: They give nonzero only if REGNO is a hard reg of the suitable class
620: or a pseudo reg currently allocated to a suitable hard reg.
621: Since they use reg_renumber, they are safe only once reg_renumber
622: has been allocated, which happens in local-alloc.c. */
623:
624: #define REGNO_OK_FOR_INDEX_P(REGNO) \
625: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
626: #define REGNO_OK_FOR_BASE_P(REGNO) \
627: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
628: #define REGNO_OK_FOR_DATA_P(REGNO) \
629: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
630: #define REGNO_OK_FOR_FP_P(REGNO) \
631: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
632:
633: /* Now macros that check whether X is a register and also,
634: strictly, whether it is in a specified class.
635:
636: These macros are specific to the 68000, and may be used only
637: in code for printing assembler insns and in conditions for
638: define_optimization. */
639:
640: /* 1 if X is a data register. */
641:
642: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
643:
644: /* 1 if X is an fp register. */
645:
646: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
647:
648: /* 1 if X is an address register */
649:
650: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
651:
652: /* Maximum number of registers that can appear in a valid memory address. */
653:
654: #define MAX_REGS_PER_ADDRESS 2
655:
656: /* Recognize any constant value that is a valid address. */
657:
658: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
659:
660: /* Nonzero if the constant value X is a legitimate general operand.
661: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
662:
663: /* Alliant FP instructions don't take immediate operands, so this
664: forces them into memory. */
665: #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
666:
667: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
668: and check its validity for a certain class.
669: We have two alternate definitions for each of them.
670: The usual definition accepts all pseudo regs; the other rejects
671: them unless they have been allocated suitable hard regs.
672: The symbol REG_OK_STRICT causes the latter definition to be used.
673:
674: Most source files want to accept pseudo regs in the hope that
675: they will get allocated to the class that the insn wants them to be in.
676: Source files for reload pass need to be strict.
677: After reload, it makes no difference, since pseudo regs have
678: been eliminated by then. */
679:
680: #ifndef REG_OK_STRICT
681:
682: /* Nonzero if X is a hard reg that can be used as an index
683: or if it is a pseudo reg. */
684: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
685: /* Nonzero if X is a hard reg that can be used as a base reg
686: or if it is a pseudo reg. */
687: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
688:
689: #else
690:
691: /* Nonzero if X is a hard reg that can be used as an index. */
692: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
693: /* Nonzero if X is a hard reg that can be used as a base reg. */
694: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
695:
696: #endif
697:
698: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
699: that is a valid memory address for an instruction.
700: The MODE argument is the machine mode for the MEM expression
701: that wants to use this address.
702:
703: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
704:
705: #define INDIRECTABLE_1_ADDRESS_P(X) \
706: (CONSTANT_ADDRESS_P (X) \
707: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
708: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
709: && REG_P (XEXP (X, 0)) \
710: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
711: || (GET_CODE (X) == PLUS \
712: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
713: && GET_CODE (XEXP (X, 1)) == CONST_INT \
714: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
715:
716: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
717: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
718:
719: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
720: { if (GET_CODE (X) == LABEL_REF) goto ADDR; \
721: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
722:
723: #define GO_IF_INDEXING(X, ADDR) \
724: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
725: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
726: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
727: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
728:
729: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
730: { GO_IF_INDEXING (X, ADDR); \
731: if (GET_CODE (X) == PLUS) \
732: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
733: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
734: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
735: if (GET_CODE (XEXP (X, 0)) == CONST_INT \
736: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
737: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
738:
739: #define LEGITIMATE_INDEX_REG_P(X) \
740: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
741: || (GET_CODE (X) == SIGN_EXTEND \
742: && GET_CODE (XEXP (X, 0)) == REG \
743: && GET_MODE (XEXP (X, 0)) == HImode \
744: && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
745:
746: #define LEGITIMATE_INDEX_P(X) \
747: (LEGITIMATE_INDEX_REG_P (X) \
748: || (TARGET_68020 && GET_CODE (X) == MULT \
749: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
750: && GET_CODE (XEXP (X, 1)) == CONST_INT \
751: && (INTVAL (XEXP (X, 1)) == 2 \
752: || INTVAL (XEXP (X, 1)) == 4 \
753: || INTVAL (XEXP (X, 1)) == 8)))
754:
755: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
756: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
757: GO_IF_INDEXED_ADDRESS (X, ADDR); }
758:
759: /* Try machine-dependent ways of modifying an illegitimate address
760: to be legitimate. If we find one, return the new, valid address.
761: This macro is used in only one place: `memory_address' in explow.c.
762:
763: OLDX is the address as it was before break_out_memory_refs was called.
764: In some cases it is useful to look at this to decide what needs to be done.
765:
766: MODE and WIN are passed so that this macro can use
767: GO_IF_LEGITIMATE_ADDRESS.
768:
769: It is always safe for this macro to do nothing. It exists to recognize
770: opportunities to optimize the output.
771:
772: For the 68000, we handle X+REG by loading X into a register R and
773: using R+REG. R will go in an address reg and indexing will be used.
774: However, if REG is a broken-out memory address or multiplication,
775: nothing needs to be done because REG can certainly go in an address reg. */
776:
777: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
778: { register int ch = (X) != (OLDX); \
779: if (GET_CODE (X) == PLUS) \
780: { if (GET_CODE (XEXP (X, 0)) == MULT) \
781: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
782: if (GET_CODE (XEXP (X, 1)) == MULT) \
783: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
784: if (ch && GET_CODE (XEXP (X, 1)) == REG \
785: && GET_CODE (XEXP (X, 0)) == REG) \
786: return X; \
787: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
788: if (GET_CODE (XEXP (X, 0)) == REG \
789: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
790: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
791: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
792: { register rtx temp = gen_reg_rtx (Pmode); \
793: register rtx val = force_operand (XEXP (X, 1), 0); \
794: emit_move_insn (temp, val); \
795: XEXP (X, 1) = temp; \
796: return X; } \
797: else if (GET_CODE (XEXP (X, 1)) == REG \
798: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
799: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
800: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
801: { register rtx temp = gen_reg_rtx (Pmode); \
802: register rtx val = force_operand (XEXP (X, 0), 0); \
803: emit_move_insn (temp, val); \
804: XEXP (X, 0) = temp; \
805: return X; }}}
806:
807: /* Go to LABEL if ADDR (a legitimate address expression)
808: has an effect that depends on the machine mode it is used for.
809: On the 68000, only predecrement and postincrement address depend thus
810: (the amount of decrement or increment being the length of the operand). */
811:
812: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
813: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
814:
815: /* Specify the machine mode that this machine uses
816: for the index in the tablejump instruction. */
817: #define CASE_VECTOR_MODE HImode
818:
819: /* Define this if the tablejump instruction expects the table
820: to contain offsets from the address of the table.
821: Do not define this if the table should contain absolute addresses. */
822: #define CASE_VECTOR_PC_RELATIVE
823:
824: /* Specify the tree operation to be used to convert reals to integers. */
825: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
826:
827: /* This is the kind of divide that is easiest to do in the general case. */
828: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
829:
830: /* Define this as 1 if `char' should by default be signed; else as 0. */
831: #define DEFAULT_SIGNED_CHAR 1
832:
833: /* Max number of bytes we can move from memory to memory
834: in one reasonably fast instruction. */
835: #define MOVE_MAX 4
836:
837: /* Define this if zero-extension is slow (more than one real instruction). */
838: #define SLOW_ZERO_EXTEND
839:
840: /* Nonzero if access to memory by bytes is slow and undesirable. */
841: #define SLOW_BYTE_ACCESS 0
842:
843: /* Define if shifts truncate the shift count
844: which implies one can omit a sign-extension or zero-extension
845: of a shift count. */
846: #define SHIFT_COUNT_TRUNCATED
847:
848: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
849: is done just by pretending it is already truncated. */
850: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
851:
852: /* We assume that the store-condition-codes instructions store 0 for false
853: and some other value for true. This is the value stored for true. */
854:
855: #define STORE_FLAG_VALUE -1
856:
857: /* When a prototype says `char' or `short', really pass an `int'. */
858: #define PROMOTE_PROTOTYPES
859:
860: /* Specify the machine mode that pointers have.
861: After generation of rtl, the compiler makes no further distinction
862: between pointers and any other objects of this machine mode. */
863: #define Pmode SImode
864:
865: /* A function address in a call instruction
866: is a byte address (for indexing purposes)
867: so give the MEM rtx a byte's mode. */
868: #define FUNCTION_MODE QImode
869:
870: /* Compute the cost of computing a constant rtl expression RTX
871: whose rtx-code is CODE. The body of this macro is a portion
872: of a switch statement. If the code is computed here,
873: return it with a return statement. Otherwise, break from the switch. */
874:
875: #define CONST_COSTS(RTX,CODE) \
876: case CONST_INT: \
877: /* Constant zero is super cheap due to clr instruction. */ \
878: if (RTX == const0_rtx) return 0; \
879: if ((unsigned) INTVAL (RTX) < 077) return 1; \
880: case CONST: \
881: case LABEL_REF: \
882: case SYMBOL_REF: \
883: return 3; \
884: case CONST_DOUBLE: \
885: return 5;
886:
887: /* Tell final.c how to eliminate redundant test instructions. */
888:
889: /* Here we define machine-dependent flags and fields in cc_status
890: (see `conditions.h'). */
891:
892: /* On the Alliant, floating-point instructions do not modify the
893: ordinary CC register. Only fcmp and ftest instructions modify the
894: floating-point CC register. We should actually keep track of what
895: both kinds of CC registers contain, but for now we only consider
896: the most recent instruction that has set either register. */
897:
898: /* Set if the cc value came from a floating point test, so a floating
899: point conditional branch must be output. */
900: #define CC_IN_FP 04000
901:
902: /* Store in cc_status the expressions
903: that the condition codes will describe
904: after execution of an instruction whose pattern is EXP.
905: Do not alter them if the instruction would not alter the cc's. */
906:
907: /* On the 68000, all the insns to store in an address register
908: fail to set the cc's. However, in some cases these instructions
909: can make it possibly invalid to use the saved cc's. In those
910: cases we clear out some or all of the saved cc's so they won't be used. */
911:
912: #define NOTICE_UPDATE_CC(EXP, INSN) \
913: { \
914: if (GET_CODE (EXP) == SET) \
915: { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP))) \
916: { if (cc_status.value1 \
917: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
918: cc_status.value1 = 0; \
919: if (cc_status.value2 \
920: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
921: cc_status.value2 = 0; } \
922: else if (SET_DEST (EXP) != cc0_rtx \
923: && (FP_REG_P (SET_SRC (EXP)) \
924: || GET_CODE (SET_SRC (EXP)) == FIX \
925: || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \
926: || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \
927: { CC_STATUS_INIT; } \
928: /* A pair of move insns doesn't produce a useful overall cc. */ \
929: else if (!FP_REG_P (SET_DEST (EXP)) \
930: && !FP_REG_P (SET_SRC (EXP)) \
931: && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4 \
932: && (GET_CODE (SET_SRC (EXP)) == REG \
933: || GET_CODE (SET_SRC (EXP)) == MEM \
934: || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\
935: { CC_STATUS_INIT; } \
936: else if (GET_CODE (SET_SRC (EXP)) == CALL) \
937: { CC_STATUS_INIT; } \
938: else if (XEXP (EXP, 0) != pc_rtx) \
939: { cc_status.flags = 0; \
940: cc_status.value1 = XEXP (EXP, 0); \
941: cc_status.value2 = XEXP (EXP, 1); } } \
942: else if (GET_CODE (EXP) == PARALLEL \
943: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
944: { \
945: if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \
946: CC_STATUS_INIT; \
947: else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \
948: { cc_status.flags = 0; \
949: cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \
950: cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \
951: else CC_STATUS_INIT; \
952: if (cc_status.value2 != 0 \
953: && ADDRESS_REG_P (cc_status.value2) \
954: && GET_MODE (cc_status.value2) == QImode) \
955: CC_STATUS_INIT; \
956: if (cc_status.value2 != 0) \
957: switch (GET_CODE (cc_status.value2)) \
958: { case PLUS: case MINUS: case MULT: case UMULT: \
959: case DIV: case UDIV: case MOD: case UMOD: case NEG: \
960: case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \
961: case ROTATE: case ROTATERT: \
962: if (GET_MODE (cc_status.value2) != VOIDmode) \
963: cc_status.flags |= CC_NO_OVERFLOW; \
964: break; \
965: case ZERO_EXTEND: \
966: /* (SET r1 (ZERO_EXTEND r2)) on this machine
967: ends with a move insn moving r2 in r2's mode.
968: Thus, the cc's are set for r2.
969: This can set N bit spuriously. */ \
970: cc_status.flags |= CC_NOT_NEGATIVE; } \
971: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
972: && cc_status.value2 \
973: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
974: cc_status.value2 = 0; \
975: if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \
976: || (cc_status.value2 && FP_REG_P (cc_status.value2))) \
977: cc_status.flags = CC_IN_FP; }
978:
979: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
980: { if (cc_prev_status.flags & CC_IN_FP) \
981: return FLOAT; \
982: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
983: return NO_OV; \
984: return NORMAL; }
985:
986: /* Control the assembler format that we output. */
987:
988: /* Output at beginning of assembler file. */
989:
990: #define ASM_FILE_START(FILE) \
991: fprintf (FILE, "#NO_APP\n");
992:
993: /* Output to assembler file text saying following lines
994: may contain character constants, extra white space, comments, etc. */
995:
996: #define ASM_APP_ON "#APP\n"
997:
998: /* Output to assembler file text saying following lines
999: no longer contain unusual constructs. */
1000:
1001: #define ASM_APP_OFF "#NO_APP\n"
1002:
1003: /* Output before read-only data. */
1004:
1005: #define TEXT_SECTION_ASM_OP "\t.text"
1006:
1007: /* Output before writable data. */
1008:
1009: #define DATA_SECTION_ASM_OP "\t.data"
1010:
1011: /* How to refer to registers in assembler output.
1012: This sequence is indexed by compiler's hard-register-number (see above). */
1013:
1014: #define REGISTER_NAMES \
1015: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1016: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1017: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1018:
1019: /* How to renumber registers for dbx and gdb.
1020: On the Sun-3, the floating point registers have numbers
1021: 18 to 25, not 16 to 23 as they do in the compiler. */
1022: /* (On the Alliant, dbx isn't working yet at all. */
1023:
1024: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1025:
1026: /* This is how to output the definition of a user-level label named NAME,
1027: such as the label on a static function or variable NAME. */
1028:
1029: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1030: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1031:
1032: /* This is how to output a command to make the user-level label named NAME
1033: defined for reference from other files. */
1034:
1035: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1036: do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1037:
1038: /* This is how to output a reference to a user-level label named NAME.
1039: `assemble_name' uses this. */
1040:
1041: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1042: fprintf (FILE, "_%s", NAME)
1043:
1044: /* This is how to output an internal numbered label where
1045: PREFIX is the class of label and NUM is the number within the class. */
1046:
1047: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1048: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1049:
1050: /* This is how to store into the string LABEL
1051: the symbol_ref name of an internal numbered label where
1052: PREFIX is the class of label and NUM is the number within the class.
1053: This is suitable for output with `assemble_name'. */
1054:
1055: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1056: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1057:
1058: /* This is how to output an assembler line defining a `double' constant. */
1059:
1060: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1061: do { union { double d; long v[2];} tem; \
1062: tem.d = (VALUE); \
1063: fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \
1064: } while (0)
1065:
1066: /* This is how to output an assembler line defining a `float' constant. */
1067:
1068: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1069: do { union { float f; long l;} tem; \
1070: tem.f = (VALUE); \
1071: fprintf (FILE, "\t.long 0x%x\n", tem.l); \
1072: } while (0)
1073:
1074: /* This is how to output an assembler line defining an `int' constant. */
1075:
1076: #define ASM_OUTPUT_INT(FILE,VALUE) \
1077: ( fprintf (FILE, "\t.long "), \
1078: output_addr_const (FILE, (VALUE)), \
1079: fprintf (FILE, "\n"))
1080:
1081: /* Likewise for `char' and `short' constants. */
1082:
1083: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1084: ( fprintf (FILE, "\t.word "), \
1085: output_addr_const (FILE, (VALUE)), \
1086: fprintf (FILE, "\n"))
1087:
1088: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1089: ( fprintf (FILE, "\t.byte "), \
1090: output_addr_const (FILE, (VALUE)), \
1091: fprintf (FILE, "\n"))
1092:
1093: #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \
1094: { int i; unsigned char *pp = (unsigned char *) PTR; \
1095: fprintf(FILE, "\t.byte %d", (unsigned int)*pp++); \
1096: for (i = 1; i < SIZE; ++i, ++pp) { \
1097: if ((i % 8) == 0) \
1098: fprintf(FILE, "\n\t.byte %d", (unsigned int) *pp); \
1099: else \
1100: fprintf(FILE, ",%d", (unsigned int) *pp); } \
1101: fprintf (FILE, "\n"); }
1102:
1103: /* This is how to output an assembler line for a numeric constant byte. */
1104:
1105: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1106: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1107:
1108: /* This is how to output an insn to push a register on the stack.
1109: It need not be very fast code. */
1110:
1111: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1112: fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
1113:
1114: /* This is how to output an insn to pop a register from the stack.
1115: It need not be very fast code. */
1116:
1117: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1118: fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
1119:
1120: /* This is how to output an element of a case-vector that is absolute.
1121: (The 68000 does not use such vectors,
1122: but we must define this macro anyway.) */
1123:
1124: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1125: fprintf (FILE, "\t.long L%d\n", VALUE)
1126:
1127: /* This is how to output an element of a case-vector that is relative. */
1128:
1129: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1130: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1131:
1132: /* This is how to output an assembler line
1133: that says to advance the location counter
1134: to a multiple of 2**LOG bytes. */
1135:
1136: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1137: if ((LOG) == 1) \
1138: fprintf (FILE, "\t.even\n"); \
1139: else if ((LOG) != 0) \
1140: fprintf (FILE, "\t.align %dn", (LOG));
1141:
1142: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1143: fprintf (FILE, "\t. = . + %d\n", (SIZE))
1144:
1145: /* This says how to output an assembler line
1146: to define a global common symbol. */
1147:
1148: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1149: ( fputs ("\t.comm ", (FILE)), \
1150: assemble_name ((FILE), (NAME)), \
1151: fprintf ((FILE), ",%d\n", (ROUNDED)))
1152:
1153: /* This says how to output an assembler line
1154: to define a local common symbol. */
1155:
1156: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1157: ( fputs ("\t.lcomm ", (FILE)), \
1158: assemble_name ((FILE), (NAME)), \
1159: fprintf ((FILE), ",%d\n", (ROUNDED)))
1160:
1161: /* Store in OUTPUT a string (made with alloca) containing
1162: an assembler-name for a local static variable named NAME.
1163: LABELNO is an integer which is different for each call. */
1164:
1165: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1166: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1167: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1168:
1169: /* Define the parentheses used to group arithmetic operations
1170: in assembler code. */
1171:
1172: #define ASM_OPEN_PAREN "("
1173: #define ASM_CLOSE_PAREN ")"
1174:
1175: /* Define results of standard character escape sequences. */
1176: #define TARGET_BELL 007
1177: #define TARGET_BS 010
1178: #define TARGET_TAB 011
1179: #define TARGET_NEWLINE 012
1180: #define TARGET_VT 013
1181: #define TARGET_FF 014
1182: #define TARGET_CR 015
1183:
1184: /* Print operand X (an rtx) in assembler syntax to file FILE.
1185: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1186: For `%' followed by punctuation, CODE is the punctuation and X is null.
1187:
1188: On the Alliant, we use several CODE characters:
1189: '.' for dot needed in Motorola-style opcode names.
1190: '-' for an operand pushing on the stack:
1191: sp@-, -(sp) or -(%sp) depending on the style of syntax.
1192: '+' for an operand pushing on the stack:
1193: sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1194: '@' for a reference to the top word on the stack:
1195: sp@, (sp) or (%sp) depending on the style of syntax.
1196: '#' for an immediate operand prefix (# in MIT and Motorola syntax
1197: but & in SGS syntax).
1198: '!' for the cc register (used in an `and to cc' insn).
1199:
1200: 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1201: 'd' to force memory addressing to be absolute, not relative.
1202: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1203: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1204: or print pair of registers as rx:ry. */
1205:
1206: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1207: ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1208: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1209:
1210: #define PRINT_OPERAND(FILE, X, CODE) \
1211: { int i; \
1212: if (CODE == '.') ; \
1213: else if (CODE == '#') fprintf (FILE, "#"); \
1214: else if (CODE == '-') fprintf (FILE, "sp@-"); \
1215: else if (CODE == '+') fprintf (FILE, "sp@+"); \
1216: else if (CODE == '@') fprintf (FILE, "sp@"); \
1217: else if (CODE == '!') fprintf (FILE, "cc"); \
1218: else if ((X) == 0 ) ; \
1219: else if (GET_CODE (X) == REG) \
1220: { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \
1221: fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
1222: else \
1223: fprintf (FILE, "%s", reg_names[REGNO (X)]); \
1224: } \
1225: else if (GET_CODE (X) == MEM) \
1226: { \
1227: output_address (XEXP (X, 0)); \
1228: if (CODE == 'd' && ! TARGET_68020 \
1229: && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1230: fprintf (FILE, ":l"); \
1231: } \
1232: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1233: { union { double d; int i[2]; } u; \
1234: union { float f; int i; } u1; \
1235: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1236: u1.f = u.d; \
1237: if (CODE == 'f') \
1238: fprintf (FILE, "#0r%.9g", u1.f); \
1239: else \
1240: fprintf (FILE, "#0x%x", u1.i); } \
1241: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \
1242: { union { double d; int i[2]; } u; \
1243: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1244: fprintf (FILE, "#0r%.20g", u.d); } \
1245: else { putc ('#', FILE); output_addr_const (FILE, X); }}
1246:
1247: /* Note that this contains a kludge that knows that the only reason
1248: we have an address (plus (label_ref...) (reg...))
1249: is in the insn before a tablejump, and we know that m68k.md
1250: generates a label LInnn: on such an insn. */
1251: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1252: { register rtx reg1, reg2, breg, ireg; \
1253: register rtx addr = ADDR; \
1254: static char *sz = ".BW.L...D"; \
1255: rtx offset; \
1256: switch (GET_CODE (addr)) \
1257: { \
1258: case REG: \
1259: fprintf (FILE, "%s@", reg_names[REGNO (addr)]); \
1260: break; \
1261: case PRE_DEC: \
1262: fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); \
1263: break; \
1264: case POST_INC: \
1265: fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); \
1266: break; \
1267: case PLUS: \
1268: reg1 = 0; reg2 = 0; \
1269: ireg = 0; breg = 0; \
1270: offset = 0; \
1271: if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
1272: { \
1273: offset = XEXP (addr, 0); \
1274: addr = XEXP (addr, 1); \
1275: } \
1276: else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
1277: { \
1278: offset = XEXP (addr, 1); \
1279: addr = XEXP (addr, 0); \
1280: } \
1281: if (GET_CODE (addr) != PLUS) ; \
1282: else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
1283: { \
1284: reg1 = XEXP (addr, 0); \
1285: addr = XEXP (addr, 1); \
1286: } \
1287: else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
1288: { \
1289: reg1 = XEXP (addr, 1); \
1290: addr = XEXP (addr, 0); \
1291: } \
1292: else if (GET_CODE (XEXP (addr, 0)) == MULT) \
1293: { \
1294: reg1 = XEXP (addr, 0); \
1295: addr = XEXP (addr, 1); \
1296: } \
1297: else if (GET_CODE (XEXP (addr, 1)) == MULT) \
1298: { \
1299: reg1 = XEXP (addr, 1); \
1300: addr = XEXP (addr, 0); \
1301: } \
1302: else if (GET_CODE (XEXP (addr, 0)) == REG) \
1303: { \
1304: reg1 = XEXP (addr, 0); \
1305: addr = XEXP (addr, 1); \
1306: } \
1307: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1308: { \
1309: reg1 = XEXP (addr, 1); \
1310: addr = XEXP (addr, 0); \
1311: } \
1312: if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
1313: || GET_CODE (addr) == SIGN_EXTEND) \
1314: { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
1315: /* for OLD_INDEXING \
1316: else if (GET_CODE (addr) == PLUS) \
1317: { \
1318: if (GET_CODE (XEXP (addr, 0)) == REG) \
1319: { \
1320: reg2 = XEXP (addr, 0); \
1321: addr = XEXP (addr, 1); \
1322: } \
1323: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1324: { \
1325: reg2 = XEXP (addr, 1); \
1326: addr = XEXP (addr, 0); \
1327: } \
1328: } \
1329: */ \
1330: if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
1331: if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
1332: || GET_CODE (reg1) == MULT)) \
1333: || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
1334: { breg = reg2; ireg = reg1; } \
1335: else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
1336: { breg = reg1; ireg = reg2; } \
1337: if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
1338: { int scale = 1; \
1339: if (GET_CODE (ireg) == MULT) \
1340: { scale = INTVAL (XEXP (ireg, 1)); \
1341: ireg = XEXP (ireg, 0); } \
1342: if (GET_CODE (ireg) == SIGN_EXTEND) \
1343: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \
1344: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1345: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1346: reg_names[REGNO (XEXP (ireg, 0))]); \
1347: else \
1348: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \
1349: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1350: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1351: reg_names[REGNO (ireg)]); \
1352: fprintf (FILE, ":%c", sz[scale]); \
1353: putc (']', FILE); \
1354: break; } \
1355: if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \
1356: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1357: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1358: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1359: reg_names[REGNO (breg)]); \
1360: break; } \
1361: if (ireg != 0 || breg != 0) \
1362: { int scale = 1; \
1363: if (breg == 0) \
1364: abort (); \
1365: if (addr && GET_CODE (addr) == LABEL_REF) abort (); \
1366: fprintf (FILE, "%s@", reg_names[REGNO (breg)]); \
1367: if (addr != 0) { \
1368: putc( '(', FILE ); \
1369: output_addr_const (FILE, addr); \
1370: if (ireg != 0) { \
1371: if (GET_CODE(addr) == CONST_INT) { \
1372: int size_of = 1, val = INTVAL(addr); \
1373: if (val < -0x8000 || val >= 0x8000) \
1374: size_of = 4; \
1375: else if (val < -0x80 || val >= 0x80) \
1376: size_of = 2; \
1377: fprintf(FILE, ":%c", sz[size_of]); \
1378: } \
1379: else \
1380: fprintf(FILE, ":L"); } \
1381: putc( ')', FILE ); } \
1382: if (ireg != 0) { \
1383: putc ('[', FILE); \
1384: if (ireg != 0 && GET_CODE (ireg) == MULT) \
1385: { scale = INTVAL (XEXP (ireg, 1)); \
1386: ireg = XEXP (ireg, 0); } \
1387: if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
1388: fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]); \
1389: else if (ireg != 0) \
1390: fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]); \
1391: fprintf (FILE, ":%c", sz[scale]); \
1392: putc (']', FILE); \
1393: } \
1394: break; \
1395: } \
1396: else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
1397: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1398: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1399: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1400: reg_names[REGNO (reg1)]); \
1401: break; } \
1402: default: \
1403: if (GET_CODE (addr) == CONST_INT \
1404: && INTVAL (addr) < 0x8000 \
1405: && INTVAL (addr) >= -0x8000) \
1406: fprintf (FILE, "%d:W", INTVAL (addr)); \
1407: else \
1408: output_addr_const (FILE, addr); \
1409: }}
1410:
1411: /*
1412: Local variables:
1413: version-control: t
1414: End:
1415: */
1416:
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