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1.1 root 1: /* Definitions of target machine for GNU compiler. Alliant FX version.
2: Copyright (C) 1989 Free Software Foundation, Inc.
3: Adapted from tm-m68k.h by Paul Petersen ([email protected])
4: and Joe Weening ([email protected]).
5:
6: This file is part of GNU CC.
7:
8: GNU CC is free software; you can redistribute it and/or modify
9: it under the terms of the GNU General Public License as published by
10: the Free Software Foundation; either version 1, or (at your option)
11: any later version.
12:
13: GNU CC is distributed in the hope that it will be useful,
14: but WITHOUT ANY WARRANTY; without even the implied warranty of
15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: GNU General Public License for more details.
17:
18: You should have received a copy of the GNU General Public License
19: along with GNU CC; see the file COPYING. If not, write to
20: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21:
22:
23: /* This file is based on tm-m68k.h, simplified by removing support for
24: the Sun FPA and other things not applicable to the Alliant. Some
25: remnants of these features remain. */
26:
27: /* Names to predefine in the preprocessor for this target machine. */
28:
29: #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix"
30:
31: /* Print subsidiary information on the compiler version in use. */
32:
33: #define TARGET_VERSION fprintf (stderr, " (Alliant)");
34:
35: /* Run-time compilation parameters selecting different hardware
36: subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs
37: are no longer supported.) The Alliant CE is 68020-compatible, and
38: also has floating point, vector and concurrency instructions.
39:
40: Although the IP doesn't have floating point, it emulates it in the
41: operating system. Using this generally is faster than running code
42: compiled with -msoft-float, because the soft-float code still uses
43: (simulated) FP registers and ends up emulating several fmove{s,d}
44: instructions per call. So I don't recommend using soft-float for
45: any Alliant code. -- JSW
46: */
47:
48: extern int target_flags;
49:
50: /* Macros used in the machine description to test the flags. */
51:
52: /* Compile for a 68020 (not a 68000 or 68010). */
53: #define TARGET_68020 (target_flags & 1)
54: /* Compile CE insns for floating point (not library calls). */
55: #define TARGET_CE (target_flags & 2)
56: /* Compile using 68020 bitfield insns. */
57: #define TARGET_BITFIELD (target_flags & 4)
58: /* Compile with 16-bit `int'. */
59: #define TARGET_SHORT (target_flags & 040)
60:
61: /* Default 3 means compile 68020 and CE instructions. We don't use
62: bitfield instructions because there appears to be a bug in the
63: implementation of bfins on the CE. */
64:
65: #define TARGET_DEFAULT 3
66:
67: /* Define __HAVE_CE__ in preprocessor according to the -m flags.
68: This will control the use of inline FP insns in certain macros.
69: Also inform the program which CPU this is for. */
70:
71: #if TARGET_DEFAULT & 02
72:
73: /* -mce is the default */
74: #define CPP_SPEC \
75: "%{!msoft-float:-D__HAVE_CE__ }\
76: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
77:
78: #else
79:
80: /* -msoft-float is the default */
81: #define CPP_SPEC \
82: "%{mce:-D__HAVE_CE__ }\
83: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
84:
85: #endif
86:
87: /* Every structure or union's size must be a multiple of 2 bytes. */
88:
89: #define STRUCTURE_SIZE_BOUNDARY 16
90:
91: /* This is BSD, so it wants DBX format. */
92:
93: #define DBX_DEBUGGING_INFO
94:
95: /* Macro to define tables used to set the flags.
96: This is a list in braces of pairs in braces,
97: each pair being { "NAME", VALUE }
98: where VALUE is the bits to set or minus the bits to clear.
99: An empty string NAME is used to identify the default VALUE. */
100:
101: #define TARGET_SWITCHES \
102: { { "68020", 5}, \
103: { "c68020", 5}, \
104: { "bitfield", 4}, \
105: { "68000", -7}, \
106: { "c68000", -7}, \
107: { "soft-float", -2}, \
108: { "nobitfield", -4}, \
109: { "short", 040}, \
110: { "noshort", -040}, \
111: { "", TARGET_DEFAULT}}
112:
113: /* target machine storage layout */
114:
115: /* Define this if most significant bit is lowest numbered
116: in instructions that operate on numbered bit-fields.
117: This is true for 68020 insns such as bfins and bfexts.
118: We make it true always by avoiding using the single-bit insns
119: except in special cases with constant bit numbers. */
120: #define BITS_BIG_ENDIAN
121:
122: /* Define this if most significant byte of a word is the lowest numbered. */
123: /* That is true on the 68000. */
124: #define BYTES_BIG_ENDIAN
125:
126: /* Define this if most significant word of a multiword number is numbered. */
127: /* For 68000 we can decide arbitrarily
128: since there are no machine instructions for them. */
129: /* #define WORDS_BIG_ENDIAN */
130:
131: /* number of bits in an addressible storage unit */
132: #define BITS_PER_UNIT 8
133:
134: /* Width in bits of a "word", which is the contents of a machine register.
135: Note that this is not necessarily the width of data type `int';
136: if using 16-bit ints on a 68000, this would still be 32.
137: But on a machine with 16-bit registers, this would be 16. */
138: #define BITS_PER_WORD 32
139:
140: /* Width of a word, in units (bytes). */
141: #define UNITS_PER_WORD 4
142:
143: /* Width in bits of a pointer.
144: See also the macro `Pmode' defined below. */
145: #define POINTER_SIZE 32
146:
147: /* Allocation boundary (in *bits*) for storing pointers in memory. */
148: #define POINTER_BOUNDARY 16
149:
150: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
151: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
152:
153: /* Boundary (in *bits*) on which stack pointer should be aligned. */
154: #define STACK_BOUNDARY 16
155:
156: /* Allocation boundary (in *bits*) for the code of a function. */
157: #define FUNCTION_BOUNDARY 16
158:
159: /* Alignment of field after `int : 0' in a structure. */
160: #define EMPTY_FIELD_BOUNDARY 16
161:
162: /* No data type wants to be aligned rounder than this. */
163: #define BIGGEST_ALIGNMENT 16
164:
165: /* Define this if move instructions will actually fail to work
166: when given unaligned data. */
167: #define STRICT_ALIGNMENT
168:
169: /* Define number of bits in most basic integer type.
170: (If undefined, default is BITS_PER_WORD). */
171:
172: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
173:
174: /* Standard register usage. */
175:
176: /* Number of actual hardware registers.
177: The hardware registers are assigned numbers for the compiler
178: from 0 to just below FIRST_PSEUDO_REGISTER.
179: All registers that the compiler knows about must be given numbers,
180: even those that are not normally considered general registers.
181: For the Alliant, we give the data registers numbers 0-7,
182: the address registers numbers 010-017,
183: and the floating point registers numbers 020-027. */
184: #define FIRST_PSEUDO_REGISTER 24
185:
186: /* 1 for registers that have pervasive standard uses
187: and are not available for the register allocator.
188: On the Alliant, these are a0 (argument pointer),
189: a6 (frame pointer) and a7 (stack pointer). */
190: #define FIXED_REGISTERS \
191: {0, 0, 0, 0, 0, 0, 0, 0, \
192: 1, 0, 0, 0, 0, 0, 1, 1, \
193: 0, 0, 0, 0, 0, 0, 0, 0 }
194:
195: /* 1 for registers not available across function calls.
196: These must include the FIXED_REGISTERS and also any
197: registers that can be used without being saved.
198: The latter must include the registers where values are returned
199: and the register where structure-value addresses are passed.
200: Aside from that, you can include as many other registers as you like.
201: The Alliant calling sequence allows a function to use any register,
202: so we include them all here. */
203:
204: #define CALL_USED_REGISTERS \
205: {1, 1, 1, 1, 1, 1, 1, 1, \
206: 1, 1, 1, 1, 1, 1, 1, 1, \
207: 1, 1, 1, 1, 1, 1, 1, 1 }
208:
209: /* Return number of consecutive hard regs needed starting at reg REGNO
210: to hold something of mode MODE.
211: This is ordinarily the length in words of a value of mode MODE
212: but can be less for certain modes in special long registers.
213:
214: On the Alliant, ordinary registers hold 32 bits worth;
215: for the FP registers, a single register is always enough for
216: anything that can be stored in them at all. */
217: #define HARD_REGNO_NREGS(REGNO, MODE) \
218: ((REGNO) >= 16 ? 1 \
219: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
220:
221: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
222: On the Alliant, the cpu registers can hold any mode but the FP registers
223: can hold only SFmode or DFmode. */
224: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
225: ((REGNO) < 16 || (MODE) == SFmode || (MODE) == DFmode)
226:
227: /* Value is 1 if it is a good idea to tie two pseudo registers
228: when one has mode MODE1 and one has mode MODE2.
229: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
230: for any hard reg, then this must be 0 for correct output. */
231: #define MODES_TIEABLE_P(MODE1, MODE2) \
232: (((MODE1) == SFmode || (MODE1) == DFmode) \
233: == ((MODE2) == SFmode || (MODE2) == DFmode))
234:
235: /* Specify the registers used for certain standard purposes.
236: The values of these macros are register numbers. */
237:
238: /* m68000 pc isn't overloaded on a register. */
239: /* #define PC_REGNUM */
240:
241: /* Register to use for pushing function arguments. */
242: #define STACK_POINTER_REGNUM 15
243:
244: /* Base register for access to local variables of the function. */
245: #define FRAME_POINTER_REGNUM 14
246:
247: /* Value should be nonzero if functions must have frame pointers.
248: Zero means the frame pointer need not be set up (and parms
249: may be accessed via the stack pointer) in functions that seem suitable.
250: This is computed in `reload', in reload1.c. */
251: /* Set for now on Alliant until we find a way to make this work with
252: their calling sequence. */
253: #define FRAME_POINTER_REQUIRED 1
254:
255: /* Base register for access to arguments of the function. */
256: #define ARG_POINTER_REGNUM 8
257:
258: /* Register in which static-chain is passed to a function. */
259: #define STATIC_CHAIN_REGNUM 8
260:
261: /* Register in which address to store a structure value
262: is passed to a function. */
263: #define STRUCT_VALUE_REGNUM 9
264:
265: /* Define the classes of registers for register constraints in the
266: machine description. Also define ranges of constants.
267:
268: One of the classes must always be named ALL_REGS and include all hard regs.
269: If there is more than one class, another class must be named NO_REGS
270: and contain no registers.
271:
272: The name GENERAL_REGS must be the name of a class (or an alias for
273: another name such as ALL_REGS). This is the class of registers
274: that is allowed by "g" or "r" in a register constraint.
275: Also, registers outside this class are allocated only when
276: instructions express preferences for them.
277:
278: The classes must be numbered in nondecreasing order; that is,
279: a larger-numbered class must never be contained completely
280: in a smaller-numbered class.
281:
282: For any two classes, it is very desirable that there be another
283: class that represents their union. */
284:
285: /* The Alliant has three kinds of registers, so eight classes would be
286: a complete set. One of them is not needed. */
287:
288: enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS,
289: ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
290:
291: #define N_REG_CLASSES (int) LIM_REG_CLASSES
292:
293: /* Give names of register classes as strings for dump file. */
294:
295: #define REG_CLASS_NAMES \
296: { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS", \
297: "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }
298:
299: /* Define which registers fit in which classes.
300: This is an initializer for a vector of HARD_REG_SET
301: of length N_REG_CLASSES. */
302:
303: #define REG_CLASS_CONTENTS \
304: { \
305: 0, /* NO_REGS */ \
306: 0x00ff0000, /* FP_REGS */ \
307: 0x000000ff, /* DATA_REGS */ \
308: 0x00ff00ff, /* DATA_OR_FP_REGS */ \
309: 0x0000ff00, /* ADDR_REGS */ \
310: 0x0000ffff, /* GENERAL_REGS */ \
311: 0x00ffffff /* ALL_REGS */ \
312: }
313:
314: /* The same information, inverted:
315: Return the class number of the smallest class containing
316: reg number REGNO. This could be a conditional expression
317: or could index an array. */
318:
319: extern enum reg_class regno_reg_class[];
320: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
321:
322: /* The class value for index registers, and the one for base regs. */
323:
324: #define INDEX_REG_CLASS GENERAL_REGS
325: #define BASE_REG_CLASS ADDR_REGS
326:
327: /* Get reg_class from a letter such as appears in the machine description. */
328:
329: #define REG_CLASS_FROM_LETTER(C) \
330: ((C) == 'a' ? ADDR_REGS : \
331: ((C) == 'd' ? DATA_REGS : \
332: ((C) == 'f' ? FP_REGS : \
333: NO_REGS)))
334:
335: /* The letters I, J, K, L and M in a register constraint string
336: can be used to stand for particular ranges of immediate operands.
337: This macro defines what the ranges are.
338: C is the letter, and VALUE is a constant value.
339: Return 1 if VALUE is in the range specified by C.
340:
341: For the 68000, `I' is used for the range 1 to 8
342: allowed as immediate shift counts and in addq.
343: `J' is used for the range of signed numbers that fit in 16 bits.
344: `K' is for numbers that moveq can't handle.
345: `L' is for range -8 to -1, range of values that can be added with subq. */
346:
347: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
348: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
349: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
350: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
351: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
352:
353: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
354:
355: /* Given an rtx X being reloaded into a reg required to be
356: in class CLASS, return the class of reg to actually use.
357: In general this is just CLASS; but on some machines
358: in some cases it is preferable to use a more restrictive class.
359: On the 68000 series, use a data reg if possible when the
360: value is a constant in the range where moveq could be used
361: and we ensure that QImodes are reloaded into data regs. */
362:
363: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
364: ((GET_CODE (X) == CONST_INT \
365: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
366: && (CLASS) != ADDR_REGS) \
367: ? DATA_REGS \
368: : GET_MODE (X) == QImode \
369: ? DATA_REGS \
370: : (CLASS))
371:
372: /* Return the maximum number of consecutive registers
373: needed to represent mode MODE in a register of class CLASS. */
374: /* On the 68000, this is the size of MODE in words,
375: except in the FP regs, where a single reg is always enough. */
376: #define CLASS_MAX_NREGS(CLASS, MODE) \
377: ((CLASS) == FP_REGS ? 1 \
378: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
379:
380: /* Stack layout; function entry, exit and calling. */
381:
382: /* Define this if pushing a word on the stack
383: makes the stack pointer a smaller address. */
384: #define STACK_GROWS_DOWNWARD
385:
386: /* Define this if the nominal address of the stack frame
387: is at the high-address end of the local variables;
388: that is, each additional local variable allocated
389: goes at a more negative offset in the frame. */
390: #define FRAME_GROWS_DOWNWARD
391:
392: /* The Alliant uses -fcaller-saves by default. */
393: #define DEFAULT_CALLER_SAVES
394:
395: /* Offset within stack frame to start allocating local variables at.
396: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
397: first local allocated. Otherwise, it is the offset to the BEGINNING
398: of the first local allocated. */
399: #define STARTING_FRAME_OFFSET -4
400:
401: /* If we generate an insn to push BYTES bytes,
402: this says how many the stack pointer really advances by.
403: On the 68000, sp@- in a byte insn really pushes a word. */
404: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
405:
406: /* Offset of first parameter from the argument pointer register value. */
407: #define FIRST_PARM_OFFSET(FNDECL) 0
408:
409: /* Value is 1 if returning from a function call automatically
410: pops the arguments described by the number-of-args field in the call.
411: FUNTYPE is the data type of the function (as a tree),
412: or for a library call it is an identifier node for the subroutine name.
413:
414: On the Alliant we define this as 1 and make the calling sequence
415: (in alliant.md) pop the args. This wouldn't be necessary if we
416: could add to the pending stack adjustment the size of the argument
417: descriptors that are pushed after the arguments. */
418:
419: #define RETURN_POPS_ARGS(FUNTYPE) 1
420:
421: /* Define how to find the value returned by a function.
422: VALTYPE is the data type of the value (as a tree).
423: If the precise function being called is known, FUNC is its FUNCTION_DECL;
424: otherwise, FUNC is 0. */
425:
426: /* On the Alliant the return value is in FP0 if real, else D0. */
427:
428: #define FUNCTION_VALUE(VALTYPE, FUNC) \
429: (TREE_CODE (VALTYPE) == REAL_TYPE \
430: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
431: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
432:
433: /* Define how to find the value returned by a library function
434: assuming the value has mode MODE. */
435:
436: /* On the Alliant the return value is in FP0 if real, else D0. The
437: Alliant library functions for floating-point emulation return their
438: values both in FP0 and in D0/D1. But since not all gnulib functions
439: return the results of these directly, we cannot assume that D0/D1
440: contain the values we expect on return from a gnulib function. */
441:
442: #define LIBCALL_VALUE(MODE) \
443: (((MODE) == DFmode || (MODE) == SFmode) \
444: ? gen_rtx (REG, MODE, 16) \
445: : gen_rtx (REG, MODE, 0))
446:
447: /* 1 if N is a possible register number for a function value.
448: On the Alliant, D0 and FP0 are the only registers thus used.
449: (No need to mention D1 when used as a pair with D0.) */
450:
451: #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0)
452:
453: /* Define this if PCC uses the nonreentrant convention for returning
454: structure and union values. */
455:
456: #define PCC_STATIC_STRUCT_RETURN
457:
458: /* 1 if N is a possible register number for function argument passing.
459: On the Alliant, no registers are used in this way. */
460:
461: #define FUNCTION_ARG_REGNO_P(N) 0
462:
463: /* Define a data type for recording info about an argument list
464: during the scan of that argument list. This data type should
465: hold all necessary information about the function itself
466: and about the args processed so far, enough to enable macros
467: such as FUNCTION_ARG to determine where the next arg should go.
468:
469: On the Alliant, this is a single integer, which is a number of bytes
470: of arguments scanned so far. */
471:
472: #define CUMULATIVE_ARGS int
473:
474: /* Initialize a variable CUM of type CUMULATIVE_ARGS
475: for a call to a function whose data type is FNTYPE.
476: For a library call, FNTYPE is 0.
477:
478: On the Alliant, the offset starts at 0. */
479:
480: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE) \
481: ((CUM) = 0)
482:
483: /* Update the data in CUM to advance over an argument
484: of mode MODE and data type TYPE.
485: (TYPE is null for libcalls where that information may not be available.) */
486:
487: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
488: ((CUM) += ((MODE) != BLKmode \
489: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
490: : (int_size_in_bytes (TYPE) + 3) & ~3))
491:
492: /* Define where to put the arguments to a function.
493: Value is zero to push the argument on the stack,
494: or a hard register in which to store the argument.
495:
496: MODE is the argument's machine mode.
497: TYPE is the data type of the argument (as a tree).
498: This is null for libcalls where that information may
499: not be available.
500: CUM is a variable of type CUMULATIVE_ARGS which gives info about
501: the preceding args and about the function being called.
502: NAMED is nonzero if this argument is a named parameter
503: (otherwise it is an extra parameter matching an ellipsis). */
504:
505: /* On the Alliant all args are pushed. */
506:
507: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
508:
509: /* For an arg passed partly in registers and partly in memory,
510: this is the number of registers used.
511: For args passed entirely in registers or entirely in memory, zero. */
512:
513: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
514:
515: /* This macro generates the assembly code for function entry.
516: FILE is a stdio stream to output the code to.
517: SIZE is an int: how many units of temporary storage to allocate.
518: Refer to the array `regs_ever_live' to determine which registers
519: to save; `regs_ever_live[I]' is nonzero if register number I
520: is ever used in the function. This macro is responsible for
521: knowing which registers should not be saved even if used.
522: The Alliant uses caller-saves, so this macro is very simple. */
523:
524: #define FUNCTION_PROLOGUE(FILE, SIZE) \
525: { int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4; \
1.1.1.3 ! root 526: if (frame_pointer_needed) \
! 527: { \
! 528: if (fsize < 0x8000) \
! 529: fprintf(FILE,"\tlinkw a6,#%d\n", -fsize); \
! 530: else if (TARGET_68020) \
! 531: fprintf(FILE,"\tlinkl a6,#%d\n", -fsize); \
! 532: else \
! 533: fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize); \
! 534: fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }}
1.1 root 535:
536: /* Output assembler code to FILE to increment profiler label # LABELNO
537: for profiling a function entry. */
538:
539: #define FUNCTION_PROFILER(FILE, LABELNO) \
540: fprintf (FILE, "\tjbsr __mcount_\n")
541:
542: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
543: the stack pointer does not matter. The value is tested only in
544: functions that have frame pointers.
545: No definition is equivalent to always zero. */
546:
547: #define EXIT_IGNORE_STACK 1
548:
549: /* This macro generates the assembly code for function exit,
550: on machines that need it. If FUNCTION_EPILOGUE is not defined
551: then individual return instructions are generated for each
552: return statement. Args are same as for FUNCTION_PROLOGUE.
553:
554: The function epilogue should not depend on the current stack pointer!
555: It should use the frame pointer only. This is mandatory because
556: of alloca; we also take advantage of it to omit stack adjustments
557: before returning. */
558:
559: #define FUNCTION_EPILOGUE(FILE, SIZE) \
560: { if (frame_pointer_needed) \
561: fprintf (FILE, "\tunlk a6\n"); \
562: fprintf (FILE, "\trts\n"); }
563:
564: /* If the memory address ADDR is relative to the frame pointer,
565: correct it to be relative to the stack pointer instead.
566: This is for when we don't use a frame pointer.
567: ADDR should be a variable name. */
568:
569: #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
570: { int offset = -1; \
571: rtx regs = stack_pointer_rtx; \
572: if (ADDR == frame_pointer_rtx) \
573: offset = 0; \
574: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
575: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
576: offset = INTVAL (XEXP (ADDR, 1)); \
577: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
578: { rtx other_reg = XEXP (ADDR, 1); \
579: offset = 0; \
580: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
581: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
582: { rtx other_reg = XEXP (ADDR, 0); \
583: offset = 0; \
584: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
585: else if (GET_CODE (ADDR) == PLUS \
586: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
587: && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
588: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
589: { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
590: offset = INTVAL (XEXP (ADDR, 1)); \
591: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
592: else if (GET_CODE (ADDR) == PLUS \
593: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
594: && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
595: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
596: { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
597: offset = INTVAL (XEXP (ADDR, 1)); \
598: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
599: if (offset >= 0) \
600: { int regno; \
601: extern char call_used_regs[]; \
602: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
603: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
604: offset += 12; \
605: for (regno = 0; regno < 16; regno++) \
606: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
607: offset += 4; \
608: offset -= 4; \
609: ADDR = plus_constant (regs, offset + (DEPTH)); } } \
610:
611: /* Addressing modes, and classification of registers for them. */
612:
613: #define HAVE_POST_INCREMENT
614: /* #define HAVE_POST_DECREMENT */
615:
616: #define HAVE_PRE_DECREMENT
617: /* #define HAVE_PRE_INCREMENT */
618:
619: /* Macros to check register numbers against specific register classes. */
620:
621: /* These assume that REGNO is a hard or pseudo reg number.
622: They give nonzero only if REGNO is a hard reg of the suitable class
623: or a pseudo reg currently allocated to a suitable hard reg.
624: Since they use reg_renumber, they are safe only once reg_renumber
625: has been allocated, which happens in local-alloc.c. */
626:
627: #define REGNO_OK_FOR_INDEX_P(REGNO) \
628: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
629: #define REGNO_OK_FOR_BASE_P(REGNO) \
630: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
631: #define REGNO_OK_FOR_DATA_P(REGNO) \
632: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
633: #define REGNO_OK_FOR_FP_P(REGNO) \
634: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
635:
636: /* Now macros that check whether X is a register and also,
637: strictly, whether it is in a specified class.
638:
639: These macros are specific to the 68000, and may be used only
640: in code for printing assembler insns and in conditions for
641: define_optimization. */
642:
643: /* 1 if X is a data register. */
644:
645: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
646:
647: /* 1 if X is an fp register. */
648:
649: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
650:
651: /* 1 if X is an address register */
652:
653: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
654:
655: /* Maximum number of registers that can appear in a valid memory address. */
656:
657: #define MAX_REGS_PER_ADDRESS 2
658:
659: /* Recognize any constant value that is a valid address. */
660:
661: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
662:
663: /* Nonzero if the constant value X is a legitimate general operand.
664: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
665:
666: /* Alliant FP instructions don't take immediate operands, so this
667: forces them into memory. */
668: #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
669:
670: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
671: and check its validity for a certain class.
672: We have two alternate definitions for each of them.
673: The usual definition accepts all pseudo regs; the other rejects
674: them unless they have been allocated suitable hard regs.
675: The symbol REG_OK_STRICT causes the latter definition to be used.
676:
677: Most source files want to accept pseudo regs in the hope that
678: they will get allocated to the class that the insn wants them to be in.
679: Source files for reload pass need to be strict.
680: After reload, it makes no difference, since pseudo regs have
681: been eliminated by then. */
682:
683: #ifndef REG_OK_STRICT
684:
685: /* Nonzero if X is a hard reg that can be used as an index
686: or if it is a pseudo reg. */
687: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
688: /* Nonzero if X is a hard reg that can be used as a base reg
689: or if it is a pseudo reg. */
690: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
691:
692: #else
693:
694: /* Nonzero if X is a hard reg that can be used as an index. */
695: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
696: /* Nonzero if X is a hard reg that can be used as a base reg. */
697: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
698:
699: #endif
700:
701: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
702: that is a valid memory address for an instruction.
703: The MODE argument is the machine mode for the MEM expression
704: that wants to use this address.
705:
706: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
707:
708: #define INDIRECTABLE_1_ADDRESS_P(X) \
709: (CONSTANT_ADDRESS_P (X) \
710: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
711: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
712: && REG_P (XEXP (X, 0)) \
713: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
714: || (GET_CODE (X) == PLUS \
715: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
716: && GET_CODE (XEXP (X, 1)) == CONST_INT \
717: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
718:
719: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
720: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
721:
722: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
723: { if (GET_CODE (X) == LABEL_REF) goto ADDR; \
724: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
725:
726: #define GO_IF_INDEXING(X, ADDR) \
727: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
728: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
729: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
730: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
731:
732: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
733: { GO_IF_INDEXING (X, ADDR); \
734: if (GET_CODE (X) == PLUS) \
735: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
736: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
737: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
738: if (GET_CODE (XEXP (X, 0)) == CONST_INT \
739: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
740: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
741:
742: #define LEGITIMATE_INDEX_REG_P(X) \
743: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
744: || (GET_CODE (X) == SIGN_EXTEND \
745: && GET_CODE (XEXP (X, 0)) == REG \
746: && GET_MODE (XEXP (X, 0)) == HImode \
747: && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
748:
749: #define LEGITIMATE_INDEX_P(X) \
750: (LEGITIMATE_INDEX_REG_P (X) \
751: || (TARGET_68020 && GET_CODE (X) == MULT \
752: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
753: && GET_CODE (XEXP (X, 1)) == CONST_INT \
754: && (INTVAL (XEXP (X, 1)) == 2 \
755: || INTVAL (XEXP (X, 1)) == 4 \
756: || INTVAL (XEXP (X, 1)) == 8)))
757:
758: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
759: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
760: GO_IF_INDEXED_ADDRESS (X, ADDR); }
761:
762: /* Try machine-dependent ways of modifying an illegitimate address
763: to be legitimate. If we find one, return the new, valid address.
764: This macro is used in only one place: `memory_address' in explow.c.
765:
766: OLDX is the address as it was before break_out_memory_refs was called.
767: In some cases it is useful to look at this to decide what needs to be done.
768:
769: MODE and WIN are passed so that this macro can use
770: GO_IF_LEGITIMATE_ADDRESS.
771:
772: It is always safe for this macro to do nothing. It exists to recognize
773: opportunities to optimize the output.
774:
775: For the 68000, we handle X+REG by loading X into a register R and
776: using R+REG. R will go in an address reg and indexing will be used.
777: However, if REG is a broken-out memory address or multiplication,
778: nothing needs to be done because REG can certainly go in an address reg. */
779:
780: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
781: { register int ch = (X) != (OLDX); \
782: if (GET_CODE (X) == PLUS) \
783: { if (GET_CODE (XEXP (X, 0)) == MULT) \
784: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
785: if (GET_CODE (XEXP (X, 1)) == MULT) \
786: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
787: if (ch && GET_CODE (XEXP (X, 1)) == REG \
788: && GET_CODE (XEXP (X, 0)) == REG) \
789: return X; \
790: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
791: if (GET_CODE (XEXP (X, 0)) == REG \
792: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
793: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
794: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
795: { register rtx temp = gen_reg_rtx (Pmode); \
796: register rtx val = force_operand (XEXP (X, 1), 0); \
797: emit_move_insn (temp, val); \
798: XEXP (X, 1) = temp; \
799: return X; } \
800: else if (GET_CODE (XEXP (X, 1)) == REG \
801: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
802: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
803: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
804: { register rtx temp = gen_reg_rtx (Pmode); \
805: register rtx val = force_operand (XEXP (X, 0), 0); \
806: emit_move_insn (temp, val); \
807: XEXP (X, 0) = temp; \
808: return X; }}}
809:
810: /* Go to LABEL if ADDR (a legitimate address expression)
811: has an effect that depends on the machine mode it is used for.
812: On the 68000, only predecrement and postincrement address depend thus
813: (the amount of decrement or increment being the length of the operand). */
814:
815: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
816: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
817:
818: /* Specify the machine mode that this machine uses
819: for the index in the tablejump instruction. */
820: #define CASE_VECTOR_MODE HImode
821:
822: /* Define this if the tablejump instruction expects the table
823: to contain offsets from the address of the table.
824: Do not define this if the table should contain absolute addresses. */
825: #define CASE_VECTOR_PC_RELATIVE
826:
827: /* Specify the tree operation to be used to convert reals to integers. */
828: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
829:
830: /* This is the kind of divide that is easiest to do in the general case. */
831: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
832:
833: /* Define this as 1 if `char' should by default be signed; else as 0. */
834: #define DEFAULT_SIGNED_CHAR 1
835:
836: /* Max number of bytes we can move from memory to memory
837: in one reasonably fast instruction. */
838: #define MOVE_MAX 4
839:
840: /* Define this if zero-extension is slow (more than one real instruction). */
841: #define SLOW_ZERO_EXTEND
842:
843: /* Nonzero if access to memory by bytes is slow and undesirable. */
844: #define SLOW_BYTE_ACCESS 0
845:
846: /* Define if shifts truncate the shift count
847: which implies one can omit a sign-extension or zero-extension
848: of a shift count. */
849: #define SHIFT_COUNT_TRUNCATED
850:
851: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
852: is done just by pretending it is already truncated. */
853: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
854:
855: /* We assume that the store-condition-codes instructions store 0 for false
856: and some other value for true. This is the value stored for true. */
857:
858: #define STORE_FLAG_VALUE -1
859:
860: /* When a prototype says `char' or `short', really pass an `int'. */
861: #define PROMOTE_PROTOTYPES
862:
863: /* Specify the machine mode that pointers have.
864: After generation of rtl, the compiler makes no further distinction
865: between pointers and any other objects of this machine mode. */
866: #define Pmode SImode
867:
868: /* A function address in a call instruction
869: is a byte address (for indexing purposes)
870: so give the MEM rtx a byte's mode. */
871: #define FUNCTION_MODE QImode
872:
873: /* Compute the cost of computing a constant rtl expression RTX
874: whose rtx-code is CODE. The body of this macro is a portion
875: of a switch statement. If the code is computed here,
876: return it with a return statement. Otherwise, break from the switch. */
877:
878: #define CONST_COSTS(RTX,CODE) \
879: case CONST_INT: \
880: /* Constant zero is super cheap due to clr instruction. */ \
881: if (RTX == const0_rtx) return 0; \
882: if ((unsigned) INTVAL (RTX) < 077) return 1; \
883: case CONST: \
884: case LABEL_REF: \
885: case SYMBOL_REF: \
886: return 3; \
887: case CONST_DOUBLE: \
888: return 5;
1.1.1.2 root 889:
890: /* Check a `double' value for validity for a particular machine mode.
891: This is defined to avoid crashes outputting certain constants. */
892:
893: #define CHECK_FLOAT_VALUE(mode, d) \
894: if ((mode) == SFmode) \
895: { \
896: if ((d) > 3.4028234663852890e+38) \
897: { warning ("magnitude of value too large for `float'"); \
898: (d) = 3.4028234663852890e+38; } \
899: else if ((d) < -3.4028234663852890e+38) \
900: { warning ("magnitude of value too large for `float'"); \
901: (d) = -3.4028234663852890e+38; } \
902: else if (((d) > 0) && ((d) < 1.1754943508222873e-38)) \
903: (d) = 0.0; \
904: else if (((d) < 0) && ((d) > -1.1754943508222873e-38)) \
905: (d) = 0.0; \
906: }
1.1 root 907:
908: /* Tell final.c how to eliminate redundant test instructions. */
909:
910: /* Here we define machine-dependent flags and fields in cc_status
911: (see `conditions.h'). */
912:
913: /* On the Alliant, floating-point instructions do not modify the
914: ordinary CC register. Only fcmp and ftest instructions modify the
915: floating-point CC register. We should actually keep track of what
916: both kinds of CC registers contain, but for now we only consider
917: the most recent instruction that has set either register. */
918:
919: /* Set if the cc value came from a floating point test, so a floating
920: point conditional branch must be output. */
921: #define CC_IN_FP 04000
922:
923: /* Store in cc_status the expressions
924: that the condition codes will describe
925: after execution of an instruction whose pattern is EXP.
926: Do not alter them if the instruction would not alter the cc's. */
927:
928: /* On the 68000, all the insns to store in an address register
929: fail to set the cc's. However, in some cases these instructions
930: can make it possibly invalid to use the saved cc's. In those
931: cases we clear out some or all of the saved cc's so they won't be used. */
932:
933: #define NOTICE_UPDATE_CC(EXP, INSN) \
934: { \
935: if (GET_CODE (EXP) == SET) \
936: { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP))) \
937: { if (cc_status.value1 \
938: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
939: cc_status.value1 = 0; \
940: if (cc_status.value2 \
941: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
942: cc_status.value2 = 0; } \
943: else if (SET_DEST (EXP) != cc0_rtx \
944: && (FP_REG_P (SET_SRC (EXP)) \
945: || GET_CODE (SET_SRC (EXP)) == FIX \
946: || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \
947: || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \
948: { CC_STATUS_INIT; } \
949: /* A pair of move insns doesn't produce a useful overall cc. */ \
950: else if (!FP_REG_P (SET_DEST (EXP)) \
951: && !FP_REG_P (SET_SRC (EXP)) \
952: && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4 \
953: && (GET_CODE (SET_SRC (EXP)) == REG \
954: || GET_CODE (SET_SRC (EXP)) == MEM \
955: || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\
956: { CC_STATUS_INIT; } \
957: else if (GET_CODE (SET_SRC (EXP)) == CALL) \
958: { CC_STATUS_INIT; } \
959: else if (XEXP (EXP, 0) != pc_rtx) \
960: { cc_status.flags = 0; \
961: cc_status.value1 = XEXP (EXP, 0); \
962: cc_status.value2 = XEXP (EXP, 1); } } \
963: else if (GET_CODE (EXP) == PARALLEL \
964: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
965: { \
966: if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \
967: CC_STATUS_INIT; \
968: else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \
969: { cc_status.flags = 0; \
970: cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \
971: cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \
972: else CC_STATUS_INIT; \
973: if (cc_status.value2 != 0 \
974: && ADDRESS_REG_P (cc_status.value2) \
975: && GET_MODE (cc_status.value2) == QImode) \
976: CC_STATUS_INIT; \
977: if (cc_status.value2 != 0) \
978: switch (GET_CODE (cc_status.value2)) \
979: { case PLUS: case MINUS: case MULT: case UMULT: \
980: case DIV: case UDIV: case MOD: case UMOD: case NEG: \
981: case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \
982: case ROTATE: case ROTATERT: \
983: if (GET_MODE (cc_status.value2) != VOIDmode) \
984: cc_status.flags |= CC_NO_OVERFLOW; \
985: break; \
986: case ZERO_EXTEND: \
987: /* (SET r1 (ZERO_EXTEND r2)) on this machine
988: ends with a move insn moving r2 in r2's mode.
989: Thus, the cc's are set for r2.
990: This can set N bit spuriously. */ \
991: cc_status.flags |= CC_NOT_NEGATIVE; } \
992: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
993: && cc_status.value2 \
994: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
995: cc_status.value2 = 0; \
996: if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \
997: || (cc_status.value2 && FP_REG_P (cc_status.value2))) \
998: cc_status.flags = CC_IN_FP; }
999:
1000: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1001: { if (cc_prev_status.flags & CC_IN_FP) \
1002: return FLOAT; \
1003: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1004: return NO_OV; \
1005: return NORMAL; }
1006:
1007: /* Control the assembler format that we output. */
1008:
1009: /* Output at beginning of assembler file. */
1010:
1011: #define ASM_FILE_START(FILE) \
1012: fprintf (FILE, "#NO_APP\n");
1013:
1014: /* Output to assembler file text saying following lines
1015: may contain character constants, extra white space, comments, etc. */
1016:
1017: #define ASM_APP_ON "#APP\n"
1018:
1019: /* Output to assembler file text saying following lines
1020: no longer contain unusual constructs. */
1021:
1022: #define ASM_APP_OFF "#NO_APP\n"
1023:
1024: /* Output before read-only data. */
1025:
1026: #define TEXT_SECTION_ASM_OP "\t.text"
1027:
1028: /* Output before writable data. */
1029:
1030: #define DATA_SECTION_ASM_OP "\t.data"
1031:
1032: /* How to refer to registers in assembler output.
1033: This sequence is indexed by compiler's hard-register-number (see above). */
1034:
1035: #define REGISTER_NAMES \
1036: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1037: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1038: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1039:
1040: /* How to renumber registers for dbx and gdb.
1041: On the Sun-3, the floating point registers have numbers
1042: 18 to 25, not 16 to 23 as they do in the compiler. */
1043: /* (On the Alliant, dbx isn't working yet at all. */
1044:
1045: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1046:
1047: /* This is how to output the definition of a user-level label named NAME,
1048: such as the label on a static function or variable NAME. */
1049:
1050: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1051: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1052:
1053: /* This is how to output a command to make the user-level label named NAME
1054: defined for reference from other files. */
1055:
1056: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1057: do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1058:
1059: /* This is how to output a reference to a user-level label named NAME.
1060: `assemble_name' uses this. */
1061:
1062: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1063: fprintf (FILE, "_%s", NAME)
1064:
1065: /* This is how to output an internal numbered label where
1066: PREFIX is the class of label and NUM is the number within the class. */
1067:
1068: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1069: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1070:
1071: /* This is how to store into the string LABEL
1072: the symbol_ref name of an internal numbered label where
1073: PREFIX is the class of label and NUM is the number within the class.
1074: This is suitable for output with `assemble_name'. */
1075:
1076: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1077: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1078:
1079: /* This is how to output an assembler line defining a `double' constant. */
1080:
1081: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1082: do { union { double d; long v[2];} tem; \
1083: tem.d = (VALUE); \
1084: fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \
1085: } while (0)
1086:
1087: /* This is how to output an assembler line defining a `float' constant. */
1088:
1089: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1090: do { union { float f; long l;} tem; \
1091: tem.f = (VALUE); \
1092: fprintf (FILE, "\t.long 0x%x\n", tem.l); \
1093: } while (0)
1094:
1095: /* This is how to output an assembler line defining an `int' constant. */
1096:
1097: #define ASM_OUTPUT_INT(FILE,VALUE) \
1098: ( fprintf (FILE, "\t.long "), \
1099: output_addr_const (FILE, (VALUE)), \
1100: fprintf (FILE, "\n"))
1101:
1102: /* Likewise for `char' and `short' constants. */
1103:
1104: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1105: ( fprintf (FILE, "\t.word "), \
1106: output_addr_const (FILE, (VALUE)), \
1107: fprintf (FILE, "\n"))
1108:
1109: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1110: ( fprintf (FILE, "\t.byte "), \
1111: output_addr_const (FILE, (VALUE)), \
1112: fprintf (FILE, "\n"))
1113:
1114: #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \
1115: { int i; unsigned char *pp = (unsigned char *) PTR; \
1116: fprintf(FILE, "\t.byte %d", (unsigned int)*pp++); \
1117: for (i = 1; i < SIZE; ++i, ++pp) { \
1118: if ((i % 8) == 0) \
1119: fprintf(FILE, "\n\t.byte %d", (unsigned int) *pp); \
1120: else \
1121: fprintf(FILE, ",%d", (unsigned int) *pp); } \
1122: fprintf (FILE, "\n"); }
1123:
1124: /* This is how to output an assembler line for a numeric constant byte. */
1125:
1126: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1127: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1128:
1129: /* This is how to output an insn to push a register on the stack.
1130: It need not be very fast code. */
1131:
1132: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1133: fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
1134:
1135: /* This is how to output an insn to pop a register from the stack.
1136: It need not be very fast code. */
1137:
1138: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1139: fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
1140:
1141: /* This is how to output an element of a case-vector that is absolute.
1142: (The 68000 does not use such vectors,
1143: but we must define this macro anyway.) */
1144:
1145: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1146: fprintf (FILE, "\t.long L%d\n", VALUE)
1147:
1148: /* This is how to output an element of a case-vector that is relative. */
1149:
1150: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1151: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1152:
1153: /* This is how to output an assembler line
1154: that says to advance the location counter
1155: to a multiple of 2**LOG bytes. */
1156:
1157: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1158: if ((LOG) == 1) \
1159: fprintf (FILE, "\t.even\n"); \
1160: else if ((LOG) != 0) \
1161: fprintf (FILE, "\t.align %dn", (LOG));
1162:
1163: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1.1.1.3 ! root 1164: fprintf (FILE, "\t. = . + %u\n", (SIZE))
1.1 root 1165:
1166: /* This says how to output an assembler line
1167: to define a global common symbol. */
1168:
1169: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1170: ( fputs ("\t.comm ", (FILE)), \
1171: assemble_name ((FILE), (NAME)), \
1.1.1.3 ! root 1172: fprintf ((FILE), ",%u\n", (ROUNDED)))
1.1 root 1173:
1174: /* This says how to output an assembler line
1175: to define a local common symbol. */
1176:
1177: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1178: ( fputs ("\t.lcomm ", (FILE)), \
1179: assemble_name ((FILE), (NAME)), \
1.1.1.3 ! root 1180: fprintf ((FILE), ",%u\n", (ROUNDED)))
1.1 root 1181:
1182: /* Store in OUTPUT a string (made with alloca) containing
1183: an assembler-name for a local static variable named NAME.
1184: LABELNO is an integer which is different for each call. */
1185:
1186: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1187: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1188: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1189:
1190: /* Define the parentheses used to group arithmetic operations
1191: in assembler code. */
1192:
1193: #define ASM_OPEN_PAREN "("
1194: #define ASM_CLOSE_PAREN ")"
1195:
1196: /* Define results of standard character escape sequences. */
1197: #define TARGET_BELL 007
1198: #define TARGET_BS 010
1199: #define TARGET_TAB 011
1200: #define TARGET_NEWLINE 012
1201: #define TARGET_VT 013
1202: #define TARGET_FF 014
1203: #define TARGET_CR 015
1204:
1205: /* Print operand X (an rtx) in assembler syntax to file FILE.
1206: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1207: For `%' followed by punctuation, CODE is the punctuation and X is null.
1208:
1209: On the Alliant, we use several CODE characters:
1210: '.' for dot needed in Motorola-style opcode names.
1211: '-' for an operand pushing on the stack:
1212: sp@-, -(sp) or -(%sp) depending on the style of syntax.
1213: '+' for an operand pushing on the stack:
1214: sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1215: '@' for a reference to the top word on the stack:
1216: sp@, (sp) or (%sp) depending on the style of syntax.
1217: '#' for an immediate operand prefix (# in MIT and Motorola syntax
1218: but & in SGS syntax).
1219: '!' for the cc register (used in an `and to cc' insn).
1220:
1221: 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1222: 'd' to force memory addressing to be absolute, not relative.
1223: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1224: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1225: or print pair of registers as rx:ry. */
1226:
1227: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1228: ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1229: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1230:
1231: #define PRINT_OPERAND(FILE, X, CODE) \
1232: { int i; \
1233: if (CODE == '.') ; \
1234: else if (CODE == '#') fprintf (FILE, "#"); \
1235: else if (CODE == '-') fprintf (FILE, "sp@-"); \
1236: else if (CODE == '+') fprintf (FILE, "sp@+"); \
1237: else if (CODE == '@') fprintf (FILE, "sp@"); \
1238: else if (CODE == '!') fprintf (FILE, "cc"); \
1239: else if ((X) == 0 ) ; \
1240: else if (GET_CODE (X) == REG) \
1241: { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \
1242: fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
1243: else \
1244: fprintf (FILE, "%s", reg_names[REGNO (X)]); \
1245: } \
1246: else if (GET_CODE (X) == MEM) \
1247: { \
1248: output_address (XEXP (X, 0)); \
1249: if (CODE == 'd' && ! TARGET_68020 \
1.1.1.2 root 1250: && CONSTANT_ADDRESS_P (XEXP (X, 0)) \
1251: && !(GET_CODE (XEXP (X, 0)) == CONST_INT \
1252: && INTVAL (XEXP (X, 0)) < 0x8000 \
1253: && INTVAL (XEXP (X, 0)) >= -0x8000)) \
1.1 root 1254: fprintf (FILE, ":l"); \
1255: } \
1256: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1257: { union { double d; int i[2]; } u; \
1258: union { float f; int i; } u1; \
1259: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1260: u1.f = u.d; \
1261: if (CODE == 'f') \
1262: fprintf (FILE, "#0r%.9g", u1.f); \
1263: else \
1264: fprintf (FILE, "#0x%x", u1.i); } \
1265: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \
1266: { union { double d; int i[2]; } u; \
1267: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1268: fprintf (FILE, "#0r%.20g", u.d); } \
1269: else { putc ('#', FILE); output_addr_const (FILE, X); }}
1270:
1271: /* Note that this contains a kludge that knows that the only reason
1272: we have an address (plus (label_ref...) (reg...))
1273: is in the insn before a tablejump, and we know that m68k.md
1274: generates a label LInnn: on such an insn. */
1275: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1276: { register rtx reg1, reg2, breg, ireg; \
1277: register rtx addr = ADDR; \
1278: static char *sz = ".BW.L...D"; \
1279: rtx offset; \
1280: switch (GET_CODE (addr)) \
1281: { \
1282: case REG: \
1283: fprintf (FILE, "%s@", reg_names[REGNO (addr)]); \
1284: break; \
1285: case PRE_DEC: \
1286: fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); \
1287: break; \
1288: case POST_INC: \
1289: fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); \
1290: break; \
1291: case PLUS: \
1292: reg1 = 0; reg2 = 0; \
1293: ireg = 0; breg = 0; \
1294: offset = 0; \
1295: if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
1296: { \
1297: offset = XEXP (addr, 0); \
1298: addr = XEXP (addr, 1); \
1299: } \
1300: else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
1301: { \
1302: offset = XEXP (addr, 1); \
1303: addr = XEXP (addr, 0); \
1304: } \
1305: if (GET_CODE (addr) != PLUS) ; \
1306: else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
1307: { \
1308: reg1 = XEXP (addr, 0); \
1309: addr = XEXP (addr, 1); \
1310: } \
1311: else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
1312: { \
1313: reg1 = XEXP (addr, 1); \
1314: addr = XEXP (addr, 0); \
1315: } \
1316: else if (GET_CODE (XEXP (addr, 0)) == MULT) \
1317: { \
1318: reg1 = XEXP (addr, 0); \
1319: addr = XEXP (addr, 1); \
1320: } \
1321: else if (GET_CODE (XEXP (addr, 1)) == MULT) \
1322: { \
1323: reg1 = XEXP (addr, 1); \
1324: addr = XEXP (addr, 0); \
1325: } \
1326: else if (GET_CODE (XEXP (addr, 0)) == REG) \
1327: { \
1328: reg1 = XEXP (addr, 0); \
1329: addr = XEXP (addr, 1); \
1330: } \
1331: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1332: { \
1333: reg1 = XEXP (addr, 1); \
1334: addr = XEXP (addr, 0); \
1335: } \
1336: if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
1337: || GET_CODE (addr) == SIGN_EXTEND) \
1338: { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
1339: /* for OLD_INDEXING \
1340: else if (GET_CODE (addr) == PLUS) \
1341: { \
1342: if (GET_CODE (XEXP (addr, 0)) == REG) \
1343: { \
1344: reg2 = XEXP (addr, 0); \
1345: addr = XEXP (addr, 1); \
1346: } \
1347: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1348: { \
1349: reg2 = XEXP (addr, 1); \
1350: addr = XEXP (addr, 0); \
1351: } \
1352: } \
1353: */ \
1354: if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
1355: if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
1356: || GET_CODE (reg1) == MULT)) \
1357: || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
1358: { breg = reg2; ireg = reg1; } \
1359: else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
1360: { breg = reg1; ireg = reg2; } \
1361: if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
1362: { int scale = 1; \
1363: if (GET_CODE (ireg) == MULT) \
1364: { scale = INTVAL (XEXP (ireg, 1)); \
1365: ireg = XEXP (ireg, 0); } \
1366: if (GET_CODE (ireg) == SIGN_EXTEND) \
1367: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \
1368: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1369: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1370: reg_names[REGNO (XEXP (ireg, 0))]); \
1371: else \
1372: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \
1373: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1374: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1375: reg_names[REGNO (ireg)]); \
1376: fprintf (FILE, ":%c", sz[scale]); \
1377: putc (']', FILE); \
1378: break; } \
1379: if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \
1380: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1381: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1382: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1383: reg_names[REGNO (breg)]); \
1384: break; } \
1385: if (ireg != 0 || breg != 0) \
1386: { int scale = 1; \
1387: if (breg == 0) \
1388: abort (); \
1389: if (addr && GET_CODE (addr) == LABEL_REF) abort (); \
1390: fprintf (FILE, "%s@", reg_names[REGNO (breg)]); \
1391: if (addr != 0) { \
1392: putc( '(', FILE ); \
1393: output_addr_const (FILE, addr); \
1394: if (ireg != 0) { \
1395: if (GET_CODE(addr) == CONST_INT) { \
1396: int size_of = 1, val = INTVAL(addr); \
1397: if (val < -0x8000 || val >= 0x8000) \
1398: size_of = 4; \
1399: else if (val < -0x80 || val >= 0x80) \
1400: size_of = 2; \
1401: fprintf(FILE, ":%c", sz[size_of]); \
1402: } \
1403: else \
1404: fprintf(FILE, ":L"); } \
1405: putc( ')', FILE ); } \
1406: if (ireg != 0) { \
1407: putc ('[', FILE); \
1408: if (ireg != 0 && GET_CODE (ireg) == MULT) \
1409: { scale = INTVAL (XEXP (ireg, 1)); \
1410: ireg = XEXP (ireg, 0); } \
1411: if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
1412: fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]); \
1413: else if (ireg != 0) \
1414: fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]); \
1415: fprintf (FILE, ":%c", sz[scale]); \
1416: putc (']', FILE); \
1417: } \
1418: break; \
1419: } \
1420: else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
1421: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1422: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1423: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1424: reg_names[REGNO (reg1)]); \
1425: break; } \
1426: default: \
1427: if (GET_CODE (addr) == CONST_INT \
1428: && INTVAL (addr) < 0x8000 \
1429: && INTVAL (addr) >= -0x8000) \
1430: fprintf (FILE, "%d:W", INTVAL (addr)); \
1431: else \
1432: output_addr_const (FILE, addr); \
1433: }}
1434:
1435: /*
1436: Local variables:
1437: version-control: t
1438: End:
1439: */
1440:
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