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1.1 ! root 1: ! 2: ;;- Machine description for GNU compiler ! 3: ;;- Vax Version ! 4: ;; Copyright (C) 1987, 1988 Free Software Foundation, Inc. ! 5: ! 6: ;; This file is part of GNU CC. ! 7: ! 8: ;; GNU CC is free software; you can redistribute it and/or modify ! 9: ;; it under the terms of the GNU General Public License as published by ! 10: ;; the Free Software Foundation; either version 1, or (at your option) ! 11: ;; any later version. ! 12: ! 13: ;; GNU CC is distributed in the hope that it will be useful, ! 14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 16: ;; GNU General Public License for more details. ! 17: ! 18: ;; You should have received a copy of the GNU General Public License ! 19: ;; along with GNU CC; see the file COPYING. If not, write to ! 20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 21: ! 22: ! 23: ;;- Instruction patterns. When multiple patterns apply, ! 24: ;;- the first one in the file is chosen. ! 25: ;;- ! 26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 27: ;;- ! 28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 29: ;;- updates for most instructions. ! 30: ! 31: ; tstsi is first test insn so that it is the one to match ! 32: ; a constant argument. ! 33: ! 34: (define_insn "tstsi" ! 35: [(set (cc0) ! 36: (match_operand:SI 0 "general_operand" "g"))] ! 37: "" ! 38: "tstl %0") ! 39: ! 40: (define_insn "tsthi" ! 41: [(set (cc0) ! 42: (match_operand:HI 0 "general_operand" "g"))] ! 43: "" ! 44: "tstw %0") ! 45: ! 46: (define_insn "tstqi" ! 47: [(set (cc0) ! 48: (match_operand:QI 0 "general_operand" "g"))] ! 49: "" ! 50: "tstb %0") ! 51: ! 52: (define_insn "tstdf" ! 53: [(set (cc0) ! 54: (match_operand:DF 0 "general_operand" "gF"))] ! 55: "" ! 56: "tst%# %0") ! 57: ! 58: (define_insn "tstsf" ! 59: [(set (cc0) ! 60: (match_operand:SF 0 "general_operand" "gF"))] ! 61: "" ! 62: "tstf %0") ! 63: ! 64: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands. ! 65: ! 66: (define_insn "cmpsi" ! 67: [(set (cc0) ! 68: (compare (match_operand:SI 0 "general_operand" "g") ! 69: (match_operand:SI 1 "general_operand" "g")))] ! 70: "" ! 71: "cmpl %0,%1") ! 72: ! 73: (define_insn "cmphi" ! 74: [(set (cc0) ! 75: (compare (match_operand:HI 0 "general_operand" "g") ! 76: (match_operand:HI 1 "general_operand" "g")))] ! 77: "" ! 78: "cmpw %0,%1") ! 79: ! 80: (define_insn "cmpqi" ! 81: [(set (cc0) ! 82: (compare (match_operand:QI 0 "general_operand" "g") ! 83: (match_operand:QI 1 "general_operand" "g")))] ! 84: "" ! 85: "cmpb %0,%1") ! 86: ! 87: (define_insn "cmpdf" ! 88: [(set (cc0) ! 89: (compare (match_operand:DF 0 "general_operand" "gF") ! 90: (match_operand:DF 1 "general_operand" "gF")))] ! 91: "" ! 92: "cmp%# %0,%1") ! 93: ! 94: (define_insn "cmpsf" ! 95: [(set (cc0) ! 96: (compare (match_operand:SF 0 "general_operand" "gF") ! 97: (match_operand:SF 1 "general_operand" "gF")))] ! 98: "" ! 99: "cmpf %0,%1") ! 100: ! 101: (define_insn "" ! 102: [(set (cc0) ! 103: (and:SI (match_operand:SI 0 "general_operand" "g") ! 104: (match_operand:SI 1 "general_operand" "g")))] ! 105: "" ! 106: "bitl %0,%1") ! 107: ! 108: (define_insn "" ! 109: [(set (cc0) ! 110: (and:HI (match_operand:HI 0 "general_operand" "g") ! 111: (match_operand:HI 1 "general_operand" "g")))] ! 112: "" ! 113: "bitw %0,%1") ! 114: ! 115: (define_insn "" ! 116: [(set (cc0) ! 117: (and:QI (match_operand:QI 0 "general_operand" "g") ! 118: (match_operand:QI 1 "general_operand" "g")))] ! 119: "" ! 120: "bitb %0,%1") ! 121: ! 122: (define_insn "movdf" ! 123: [(set (match_operand:DF 0 "general_operand" "=g") ! 124: (match_operand:DF 1 "general_operand" "gF"))] ! 125: "" ! 126: "* ! 127: { ! 128: if (operands[1] == dconst0_rtx) ! 129: return \"clr%# %0\"; ! 130: return \"mov%# %1,%0\"; ! 131: }") ! 132: ! 133: (define_insn "movsf" ! 134: [(set (match_operand:SF 0 "general_operand" "=g") ! 135: (match_operand:SF 1 "general_operand" "gF"))] ! 136: "" ! 137: "* ! 138: { ! 139: if (operands[1] == fconst0_rtx) ! 140: return \"clrf %0\"; ! 141: return \"movf %1,%0\"; ! 142: }") ! 143: ! 144: ;; Some vaxes don't support this instruction. ! 145: ;;(define_insn "movti" ! 146: ;; [(set (match_operand:TI 0 "general_operand" "=g") ! 147: ;; (match_operand:TI 1 "general_operand" "g"))] ! 148: ;; "" ! 149: ;; "movh %1,%0") ! 150: ! 151: (define_insn "movdi" ! 152: [(set (match_operand:DI 0 "general_operand" "=g") ! 153: (match_operand:DI 1 "general_operand" "g"))] ! 154: "" ! 155: "movq %1,%0") ! 156: ! 157: (define_insn "movsi" ! 158: [(set (match_operand:SI 0 "general_operand" "=g") ! 159: (match_operand:SI 1 "general_operand" "g"))] ! 160: "" ! 161: "* ! 162: { ! 163: rtx link; ! 164: if (operands[1] == const1_rtx ! 165: && (link = find_reg_note (insn, REG_WAS_0, 0)) ! 166: /* Make sure the insn that stored the 0 is still present. */ ! 167: && ! XEXP (link, 0)->volatil ! 168: && GET_CODE (XEXP (link, 0)) != NOTE ! 169: /* Make sure cross jumping didn't happen here. */ ! 170: && no_labels_between_p (XEXP (link, 0), insn)) ! 171: /* Fastest way to change a 0 to a 1. */ ! 172: return \"incl %0\"; ! 173: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) ! 174: { ! 175: if (push_operand (operands[0], SImode)) ! 176: return \"pushab %a1\"; ! 177: return \"movab %a1,%0\"; ! 178: } ! 179: /* this is slower than a movl, except when pushing an operand */ ! 180: if (operands[1] == const0_rtx) ! 181: return \"clrl %0\"; ! 182: if (GET_CODE (operands[1]) == CONST_INT ! 183: && (unsigned) INTVAL (operands[1]) >= 64) ! 184: { ! 185: int i = INTVAL (operands[1]); ! 186: if ((unsigned)(~i) < 64) ! 187: { ! 188: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i); ! 189: return \"mcoml %1,%0\"; ! 190: } ! 191: if ((unsigned)i < 127) ! 192: { ! 193: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63); ! 194: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63); ! 195: return \"addl3 %2,%1,%0\"; ! 196: } ! 197: /* trading speed for space */ ! 198: if ((unsigned)i < 0x100) ! 199: return \"movzbl %1,%0\"; ! 200: if (i >= -0x80 && i < 0) ! 201: return \"cvtbl %1,%0\"; ! 202: if ((unsigned)i < 0x10000) ! 203: return \"movzwl %1,%0\"; ! 204: if (i >= -0x8000 && i < 0) ! 205: return \"cvtwl %1,%0\"; ! 206: } ! 207: if (push_operand (operands[0], SImode)) ! 208: return \"pushl %1\"; ! 209: return \"movl %1,%0\"; ! 210: }") ! 211: ! 212: (define_insn "movhi" ! 213: [(set (match_operand:HI 0 "general_operand" "=g") ! 214: (match_operand:HI 1 "general_operand" "g"))] ! 215: "" ! 216: "* ! 217: { ! 218: rtx link; ! 219: if (operands[1] == const1_rtx ! 220: && (link = find_reg_note (insn, REG_WAS_0, 0)) ! 221: /* Make sure the insn that stored the 0 is still present. */ ! 222: && ! XEXP (link, 0)->volatil ! 223: && GET_CODE (XEXP (link, 0)) != NOTE ! 224: /* Make sure cross jumping didn't happen here. */ ! 225: && no_labels_between_p (XEXP (link, 0), insn)) ! 226: /* Fastest way to change a 0 to a 1. */ ! 227: return \"incw %0\"; ! 228: if (operands[1] == const0_rtx) ! 229: return \"clrw %0\"; ! 230: if (GET_CODE (operands[1]) == CONST_INT ! 231: && (unsigned) INTVAL (operands[1]) >= 64) ! 232: { ! 233: int i = INTVAL (operands[1]); ! 234: if ((unsigned)((~i) & 0xffff) < 64) ! 235: { ! 236: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff); ! 237: return \"mcomw %1,%0\"; ! 238: } ! 239: if ((unsigned)(i & 0xffff) < 127) ! 240: { ! 241: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63); ! 242: operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff); ! 243: return \"addw3 %2,%1,%0\"; ! 244: } ! 245: /* this is a lot slower, and only saves 1 measly byte! */ ! 246: /* if ((unsigned)i < 0x100) ! 247: return \"movzbw %1,%0\"; */ ! 248: /* if (i >= -0x80 && i < 0) ! 249: return \"cvtbw %1,%0\"; */ ! 250: } ! 251: return \"movw %1,%0\"; ! 252: }") ! 253: ! 254: (define_insn "movqi" ! 255: [(set (match_operand:QI 0 "general_operand" "=g") ! 256: (match_operand:QI 1 "general_operand" "g"))] ! 257: "" ! 258: "* ! 259: { ! 260: if (operands[1] == const0_rtx) ! 261: return \"clrb %0\"; ! 262: if (GET_CODE (operands[1]) == CONST_INT ! 263: && (unsigned) INTVAL (operands[1]) >= 64) ! 264: { ! 265: int i = INTVAL (operands[1]); ! 266: if ((unsigned)((~i) & 0xff) < 64) ! 267: { ! 268: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff); ! 269: return \"mcomb %1,%0\"; ! 270: } ! 271: #if 0 ! 272: /* ASCII alphabetics */ ! 273: if (((unsigned) INTVAL (operands[1]) &0xff) < 127) ! 274: { ! 275: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63); ! 276: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63); ! 277: return \"addb3 %2,%1,%0\"; ! 278: } ! 279: #endif ! 280: } ! 281: return \"movb %1,%0\"; ! 282: }") ! 283: ! 284: ;; The definition of this insn does not really explain what it does, ! 285: ;; but it should suffice ! 286: ;; that anything generated as this insn will be recognized as one ! 287: ;; and that it won't successfully combine with anything. ! 288: (define_insn "movstrhi" ! 289: [(set (match_operand:BLK 0 "general_operand" "=g") ! 290: (match_operand:BLK 1 "general_operand" "g")) ! 291: (use (match_operand:HI 2 "general_operand" "g")) ! 292: (clobber (reg:SI 0)) ! 293: (clobber (reg:SI 1)) ! 294: (clobber (reg:SI 2)) ! 295: (clobber (reg:SI 3)) ! 296: (clobber (reg:SI 4)) ! 297: (clobber (reg:SI 5))] ! 298: "" ! 299: "movc3 %2,%1,%0") ! 300: ! 301: ;; Extension and truncation insns. ! 302: ;; Those for integer source operand ! 303: ;; are ordered widest source type first. ! 304: ! 305: (define_insn "truncsiqi2" ! 306: [(set (match_operand:QI 0 "general_operand" "=g") ! 307: (truncate:QI (match_operand:SI 1 "general_operand" "g")))] ! 308: "" ! 309: "cvtlb %1,%0") ! 310: ! 311: (define_insn "truncsihi2" ! 312: [(set (match_operand:HI 0 "general_operand" "=g") ! 313: (truncate:HI (match_operand:SI 1 "general_operand" "g")))] ! 314: "" ! 315: "cvtlw %1,%0") ! 316: ! 317: (define_insn "trunchiqi2" ! 318: [(set (match_operand:QI 0 "general_operand" "=g") ! 319: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] ! 320: "" ! 321: "cvtwb %1,%0") ! 322: ! 323: (define_insn "extendhisi2" ! 324: [(set (match_operand:SI 0 "general_operand" "=g") ! 325: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 326: "" ! 327: "cvtwl %1,%0") ! 328: ! 329: (define_insn "extendqihi2" ! 330: [(set (match_operand:HI 0 "general_operand" "=g") ! 331: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 332: "" ! 333: "cvtbw %1,%0") ! 334: ! 335: (define_insn "extendqisi2" ! 336: [(set (match_operand:SI 0 "general_operand" "=g") ! 337: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 338: "" ! 339: "cvtbl %1,%0") ! 340: ! 341: (define_insn "extendsfdf2" ! 342: [(set (match_operand:DF 0 "general_operand" "=g") ! 343: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] ! 344: "" ! 345: "cvtf%# %1,%0") ! 346: ! 347: (define_insn "truncdfsf2" ! 348: [(set (match_operand:SF 0 "general_operand" "=g") ! 349: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] ! 350: "" ! 351: "cvt%#f %1,%0") ! 352: ! 353: (define_insn "zero_extendhisi2" ! 354: [(set (match_operand:SI 0 "general_operand" "=g") ! 355: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 356: "" ! 357: "movzwl %1,%0") ! 358: ! 359: (define_insn "zero_extendqihi2" ! 360: [(set (match_operand:HI 0 "general_operand" "=g") ! 361: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 362: "" ! 363: "movzbw %1,%0") ! 364: ! 365: (define_insn "zero_extendqisi2" ! 366: [(set (match_operand:SI 0 "general_operand" "=g") ! 367: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 368: "" ! 369: "movzbl %1,%0") ! 370: ! 371: ;; Fix-to-float conversion insns. ! 372: ;; Note that the ones that start with SImode come first. ! 373: ;; That is so that an operand that is a CONST_INT ! 374: ;; (and therefore lacks a specific machine mode). ! 375: ;; will be recognized as SImode (which is always valid) ! 376: ;; rather than as QImode or HImode. ! 377: ! 378: (define_insn "floatsisf2" ! 379: [(set (match_operand:SF 0 "general_operand" "=g") ! 380: (float:SF (match_operand:SI 1 "general_operand" "g")))] ! 381: "" ! 382: "cvtlf %1,%0") ! 383: ! 384: (define_insn "floatsidf2" ! 385: [(set (match_operand:DF 0 "general_operand" "=g") ! 386: (float:DF (match_operand:SI 1 "general_operand" "g")))] ! 387: "" ! 388: "cvtl%# %1,%0") ! 389: ! 390: (define_insn "floathisf2" ! 391: [(set (match_operand:SF 0 "general_operand" "=g") ! 392: (float:SF (match_operand:HI 1 "general_operand" "g")))] ! 393: "" ! 394: "cvtwf %1,%0") ! 395: ! 396: (define_insn "floathidf2" ! 397: [(set (match_operand:DF 0 "general_operand" "=g") ! 398: (float:DF (match_operand:HI 1 "general_operand" "g")))] ! 399: "" ! 400: "cvtw%# %1,%0") ! 401: ! 402: (define_insn "floatqisf2" ! 403: [(set (match_operand:SF 0 "general_operand" "=g") ! 404: (float:SF (match_operand:QI 1 "general_operand" "g")))] ! 405: "" ! 406: "cvtbf %1,%0") ! 407: ! 408: (define_insn "floatqidf2" ! 409: [(set (match_operand:DF 0 "general_operand" "=g") ! 410: (float:DF (match_operand:QI 1 "general_operand" "g")))] ! 411: "" ! 412: "cvtb%# %1,%0") ! 413: ! 414: ;; Float-to-fix conversion insns. ! 415: ! 416: (define_insn "fix_truncsfqi2" ! 417: [(set (match_operand:QI 0 "general_operand" "=g") ! 418: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] ! 419: "" ! 420: "cvtfb %1,%0") ! 421: ! 422: (define_insn "fix_truncsfhi2" ! 423: [(set (match_operand:HI 0 "general_operand" "=g") ! 424: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] ! 425: "" ! 426: "cvtfw %1,%0") ! 427: ! 428: (define_insn "fix_truncsfsi2" ! 429: [(set (match_operand:SI 0 "general_operand" "=g") ! 430: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] ! 431: "" ! 432: "cvtfl %1,%0") ! 433: ! 434: (define_insn "fix_truncdfqi2" ! 435: [(set (match_operand:QI 0 "general_operand" "=g") ! 436: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] ! 437: "" ! 438: "cvt%#b %1,%0") ! 439: ! 440: (define_insn "fix_truncdfhi2" ! 441: [(set (match_operand:HI 0 "general_operand" "=g") ! 442: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] ! 443: "" ! 444: "cvt%#w %1,%0") ! 445: ! 446: (define_insn "fix_truncdfsi2" ! 447: [(set (match_operand:SI 0 "general_operand" "=g") ! 448: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] ! 449: "" ! 450: "cvt%#l %1,%0") ! 451: ! 452: ;;- All kinds of add instructions. ! 453: ! 454: (define_insn "adddf3" ! 455: [(set (match_operand:DF 0 "general_operand" "=g") ! 456: (plus:DF (match_operand:DF 1 "general_operand" "gF") ! 457: (match_operand:DF 2 "general_operand" "gF")))] ! 458: "" ! 459: "* ! 460: { ! 461: if (rtx_equal_p (operands[0], operands[1])) ! 462: return \"add%#2 %2,%0\"; ! 463: if (rtx_equal_p (operands[0], operands[2])) ! 464: return \"add%#2 %1,%0\"; ! 465: return \"add%#3 %1,%2,%0\"; ! 466: }") ! 467: ! 468: (define_insn "addsf3" ! 469: [(set (match_operand:SF 0 "general_operand" "=g") ! 470: (plus:SF (match_operand:SF 1 "general_operand" "gF") ! 471: (match_operand:SF 2 "general_operand" "gF")))] ! 472: "" ! 473: "* ! 474: { ! 475: if (rtx_equal_p (operands[0], operands[1])) ! 476: return \"addf2 %2,%0\"; ! 477: if (rtx_equal_p (operands[0], operands[2])) ! 478: return \"addf2 %1,%0\"; ! 479: return \"addf3 %1,%2,%0\"; ! 480: }") ! 481: ! 482: (define_insn "addsi3" ! 483: [(set (match_operand:SI 0 "general_operand" "=g") ! 484: (plus:SI (match_operand:SI 1 "general_operand" "g") ! 485: (match_operand:SI 2 "general_operand" "g")))] ! 486: "" ! 487: "* ! 488: { ! 489: if (rtx_equal_p (operands[0], operands[1])) ! 490: { ! 491: if (operands[2] == const1_rtx) ! 492: return \"incl %0\"; ! 493: if (GET_CODE (operands[2]) == CONST_INT ! 494: && INTVAL (operands[2]) == -1) ! 495: return \"decl %0\"; ! 496: if (GET_CODE (operands[2]) == CONST_INT ! 497: && (unsigned) (- INTVAL (operands[2])) < 64) ! 498: return \"subl2 $%n2,%0\"; ! 499: if (GET_CODE (operands[2]) == CONST_INT ! 500: && (unsigned) INTVAL (operands[2]) >= 64 ! 501: && GET_CODE (operands[1]) == REG) ! 502: return \"movab %c2(%1),%0\"; ! 503: return \"addl2 %2,%0\"; ! 504: } ! 505: if (rtx_equal_p (operands[0], operands[2])) ! 506: return \"addl2 %1,%0\"; ! 507: if (GET_CODE (operands[2]) == CONST_INT ! 508: && (unsigned) (- INTVAL (operands[2])) < 64) ! 509: return \"subl3 $%n2,%1,%0\"; ! 510: if (GET_CODE (operands[2]) == CONST_INT ! 511: && (unsigned) INTVAL (operands[2]) >= 64 ! 512: && GET_CODE (operands[1]) == REG) ! 513: { ! 514: if (push_operand (operands[0], SImode)) ! 515: return \"pushab %c2(%1)\"; ! 516: return \"movab %c2(%1),%0\"; ! 517: } ! 518: return \"addl3 %1,%2,%0\"; ! 519: }") ! 520: ! 521: (define_insn "addhi3" ! 522: [(set (match_operand:HI 0 "general_operand" "=g") ! 523: (plus:HI (match_operand:HI 1 "general_operand" "g") ! 524: (match_operand:HI 2 "general_operand" "g")))] ! 525: "" ! 526: "* ! 527: { ! 528: if (rtx_equal_p (operands[0], operands[1])) ! 529: { ! 530: if (operands[2] == const1_rtx) ! 531: return \"incw %0\"; ! 532: if (GET_CODE (operands[1]) == CONST_INT ! 533: && INTVAL (operands[1]) == -1) ! 534: return \"decw %0\"; ! 535: if (GET_CODE (operands[2]) == CONST_INT ! 536: && (unsigned) (- INTVAL (operands[2])) < 64) ! 537: return \"subw2 $%n2,%0\"; ! 538: return \"addw2 %2,%0\"; ! 539: } ! 540: if (rtx_equal_p (operands[0], operands[2])) ! 541: return \"addw2 %1,%0\"; ! 542: if (GET_CODE (operands[2]) == CONST_INT ! 543: && (unsigned) (- INTVAL (operands[2])) < 64) ! 544: return \"subw3 $%n2,%1,%0\"; ! 545: return \"addw3 %1,%2,%0\"; ! 546: }") ! 547: ! 548: (define_insn "addqi3" ! 549: [(set (match_operand:QI 0 "general_operand" "=g") ! 550: (plus:QI (match_operand:QI 1 "general_operand" "g") ! 551: (match_operand:QI 2 "general_operand" "g")))] ! 552: "" ! 553: "* ! 554: { ! 555: if (rtx_equal_p (operands[0], operands[1])) ! 556: { ! 557: if (operands[2] == const1_rtx) ! 558: return \"incb %0\"; ! 559: if (GET_CODE (operands[1]) == CONST_INT ! 560: && INTVAL (operands[1]) == -1) ! 561: return \"decb %0\"; ! 562: if (GET_CODE (operands[2]) == CONST_INT ! 563: && (unsigned) (- INTVAL (operands[2])) < 64) ! 564: return \"subb2 $%n2,%0\"; ! 565: return \"addb2 %2,%0\"; ! 566: } ! 567: if (rtx_equal_p (operands[0], operands[2])) ! 568: return \"addb2 %1,%0\"; ! 569: if (GET_CODE (operands[2]) == CONST_INT ! 570: && (unsigned) (- INTVAL (operands[2])) < 64) ! 571: return \"subb3 $%n2,%1,%0\"; ! 572: return \"addb3 %1,%2,%0\"; ! 573: }") ! 574: ! 575: ;;- All kinds of subtract instructions. ! 576: ! 577: (define_insn "subdf3" ! 578: [(set (match_operand:DF 0 "general_operand" "=g") ! 579: (minus:DF (match_operand:DF 1 "general_operand" "gF") ! 580: (match_operand:DF 2 "general_operand" "gF")))] ! 581: "" ! 582: "* ! 583: { ! 584: if (rtx_equal_p (operands[0], operands[1])) ! 585: return \"sub%#2 %2,%0\"; ! 586: return \"sub%#3 %2,%1,%0\"; ! 587: }") ! 588: ! 589: (define_insn "subsf3" ! 590: [(set (match_operand:SF 0 "general_operand" "=g") ! 591: (minus:SF (match_operand:SF 1 "general_operand" "gF") ! 592: (match_operand:SF 2 "general_operand" "gF")))] ! 593: "" ! 594: "* ! 595: { ! 596: if (rtx_equal_p (operands[0], operands[1])) ! 597: return \"subf2 %2,%0\"; ! 598: return \"subf3 %2,%1,%0\"; ! 599: }") ! 600: ! 601: (define_insn "subsi3" ! 602: [(set (match_operand:SI 0 "general_operand" "=g") ! 603: (minus:SI (match_operand:SI 1 "general_operand" "g") ! 604: (match_operand:SI 2 "general_operand" "g")))] ! 605: "" ! 606: "* ! 607: { ! 608: if (rtx_equal_p (operands[0], operands[1])) ! 609: { ! 610: if (operands[2] == const1_rtx) ! 611: return \"decl %0\"; ! 612: return \"subl2 %2,%0\"; ! 613: } ! 614: return \"subl3 %2,%1,%0\"; ! 615: }") ! 616: ! 617: (define_insn "subhi3" ! 618: [(set (match_operand:HI 0 "general_operand" "=g") ! 619: (minus:HI (match_operand:HI 1 "general_operand" "g") ! 620: (match_operand:HI 2 "general_operand" "g")))] ! 621: "" ! 622: "* ! 623: { ! 624: if (rtx_equal_p (operands[0], operands[1])) ! 625: { ! 626: if (operands[2] == const1_rtx) ! 627: return \"decw %0\"; ! 628: return \"subw2 %2,%0\"; ! 629: } ! 630: return \"subw3 %2,%1,%0\"; ! 631: }") ! 632: ! 633: (define_insn "subqi3" ! 634: [(set (match_operand:QI 0 "general_operand" "=g") ! 635: (minus:QI (match_operand:QI 1 "general_operand" "g") ! 636: (match_operand:QI 2 "general_operand" "g")))] ! 637: "" ! 638: "* ! 639: { ! 640: if (rtx_equal_p (operands[0], operands[1])) ! 641: { ! 642: if (operands[2] == const1_rtx) ! 643: return \"decb %0\"; ! 644: return \"subb2 %2,%0\"; ! 645: } ! 646: return \"subb3 %2,%1,%0\"; ! 647: }") ! 648: ! 649: ;;- Multiply instructions. ! 650: ! 651: (define_insn "muldf3" ! 652: [(set (match_operand:DF 0 "general_operand" "=g") ! 653: (mult:DF (match_operand:DF 1 "general_operand" "gF") ! 654: (match_operand:DF 2 "general_operand" "gF")))] ! 655: "" ! 656: "* ! 657: { ! 658: if (rtx_equal_p (operands[0], operands[1])) ! 659: return \"mul%#2 %2,%0\"; ! 660: if (rtx_equal_p (operands[0], operands[2])) ! 661: return \"mul%#2 %1,%0\"; ! 662: return \"mul%#3 %1,%2,%0\"; ! 663: }") ! 664: ! 665: (define_insn "mulsf3" ! 666: [(set (match_operand:SF 0 "general_operand" "=g") ! 667: (mult:SF (match_operand:SF 1 "general_operand" "gF") ! 668: (match_operand:SF 2 "general_operand" "gF")))] ! 669: "" ! 670: "* ! 671: { ! 672: if (rtx_equal_p (operands[0], operands[1])) ! 673: return \"mulf2 %2,%0\"; ! 674: if (rtx_equal_p (operands[0], operands[2])) ! 675: return \"mulf2 %1,%0\"; ! 676: return \"mulf3 %1,%2,%0\"; ! 677: }") ! 678: ! 679: (define_insn "mulsi3" ! 680: [(set (match_operand:SI 0 "general_operand" "=g") ! 681: (mult:SI (match_operand:SI 1 "general_operand" "g") ! 682: (match_operand:SI 2 "general_operand" "g")))] ! 683: "" ! 684: "* ! 685: { ! 686: if (rtx_equal_p (operands[0], operands[1])) ! 687: return \"mull2 %2,%0\"; ! 688: if (rtx_equal_p (operands[0], operands[2])) ! 689: return \"mull2 %1,%0\"; ! 690: return \"mull3 %1,%2,%0\"; ! 691: }") ! 692: ! 693: (define_insn "mulhi3" ! 694: [(set (match_operand:HI 0 "general_operand" "=g") ! 695: (mult:HI (match_operand:HI 1 "general_operand" "g") ! 696: (match_operand:HI 2 "general_operand" "g")))] ! 697: "" ! 698: "* ! 699: { ! 700: if (rtx_equal_p (operands[0], operands[1])) ! 701: return \"mulw2 %2,%0\"; ! 702: if (rtx_equal_p (operands[0], operands[2])) ! 703: return \"mulw2 %1,%0\"; ! 704: return \"mulw3 %1,%2,%0\"; ! 705: }") ! 706: ! 707: (define_insn "mulqi3" ! 708: [(set (match_operand:QI 0 "general_operand" "=g") ! 709: (mult:QI (match_operand:QI 1 "general_operand" "g") ! 710: (match_operand:QI 2 "general_operand" "g")))] ! 711: "" ! 712: "* ! 713: { ! 714: if (rtx_equal_p (operands[0], operands[1])) ! 715: return \"mulb2 %2,%0\"; ! 716: if (rtx_equal_p (operands[0], operands[2])) ! 717: return \"mulb2 %1,%0\"; ! 718: return \"mulb3 %1,%2,%0\"; ! 719: }") ! 720: ! 721: ;;- Divide instructions. ! 722: ! 723: (define_insn "divdf3" ! 724: [(set (match_operand:DF 0 "general_operand" "=g") ! 725: (div:DF (match_operand:DF 1 "general_operand" "gF") ! 726: (match_operand:DF 2 "general_operand" "gF")))] ! 727: "" ! 728: "* ! 729: { ! 730: if (rtx_equal_p (operands[0], operands[1])) ! 731: return \"div%#2 %2,%0\"; ! 732: return \"div%#3 %2,%1,%0\"; ! 733: }") ! 734: ! 735: (define_insn "divsf3" ! 736: [(set (match_operand:SF 0 "general_operand" "=g") ! 737: (div:SF (match_operand:SF 1 "general_operand" "gF") ! 738: (match_operand:SF 2 "general_operand" "gF")))] ! 739: "" ! 740: "* ! 741: { ! 742: if (rtx_equal_p (operands[0], operands[1])) ! 743: return \"divf2 %2,%0\"; ! 744: return \"divf3 %2,%1,%0\"; ! 745: }") ! 746: ! 747: (define_insn "divsi3" ! 748: [(set (match_operand:SI 0 "general_operand" "=g") ! 749: (div:SI (match_operand:SI 1 "general_operand" "g") ! 750: (match_operand:SI 2 "general_operand" "g")))] ! 751: "" ! 752: "* ! 753: { ! 754: if (rtx_equal_p (operands[0], operands[1])) ! 755: return \"divl2 %2,%0\"; ! 756: return \"divl3 %2,%1,%0\"; ! 757: }") ! 758: ! 759: (define_insn "divhi3" ! 760: [(set (match_operand:HI 0 "general_operand" "=g") ! 761: (div:HI (match_operand:HI 1 "general_operand" "g") ! 762: (match_operand:HI 2 "general_operand" "g")))] ! 763: "" ! 764: "* ! 765: { ! 766: if (rtx_equal_p (operands[0], operands[1])) ! 767: return \"divw2 %2,%0\"; ! 768: return \"divw3 %2,%1,%0\"; ! 769: }") ! 770: ! 771: (define_insn "divqi3" ! 772: [(set (match_operand:QI 0 "general_operand" "=g") ! 773: (div:QI (match_operand:QI 1 "general_operand" "g") ! 774: (match_operand:QI 2 "general_operand" "g")))] ! 775: "" ! 776: "* ! 777: { ! 778: if (rtx_equal_p (operands[0], operands[1])) ! 779: return \"divb2 %2,%0\"; ! 780: return \"divb3 %2,%1,%0\"; ! 781: }") ! 782: ! 783: ;This is left out because it is very slow; ! 784: ;we are better off programming around the "lack" of this insn. ! 785: ;(define_insn "divmoddisi4" ! 786: ; [(set (match_operand:SI 0 "general_operand" "=g") ! 787: ; (div:SI (match_operand:DI 1 "general_operand" "g") ! 788: ; (match_operand:SI 2 "general_operand" "g"))) ! 789: ; (set (match_operand:SI 3 "general_operand" "=g") ! 790: ; (mod:SI (match_operand:DI 1 "general_operand" "g") ! 791: ; (match_operand:SI 2 "general_operand" "g")))] ! 792: ; "" ! 793: ; "ediv %2,%1,%0,%3") ! 794: ! 795: ;; Bit-and on the vax is done with a clear-bits insn. ! 796: (define_expand "andsi3" ! 797: [(set (match_operand:SI 0 "general_operand" "=g") ! 798: (and:SI (match_operand:SI 1 "general_operand" "g") ! 799: (not:SI (match_operand:SI 2 "general_operand" "g"))))] ! 800: "" ! 801: " ! 802: { ! 803: extern rtx expand_unop (); ! 804: if (GET_CODE (operands[2]) == CONST_INT) ! 805: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); ! 806: else ! 807: operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1); ! 808: }") ! 809: ! 810: (define_expand "andhi3" ! 811: [(set (match_operand:HI 0 "general_operand" "=g") ! 812: (and:HI (match_operand:HI 1 "general_operand" "g") ! 813: (not:HI (match_operand:HI 2 "general_operand" "g"))))] ! 814: "" ! 815: " ! 816: { ! 817: extern rtx expand_unop (); ! 818: rtx op = operands[2]; ! 819: if (GET_CODE (op) == CONST_INT) ! 820: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 821: ((1 << 16) - 1) & ~INTVAL (op)); ! 822: else ! 823: operands[2] = expand_unop (HImode, one_cmpl_optab, op, 0, 1); ! 824: }") ! 825: ! 826: (define_expand "andqi3" ! 827: [(set (match_operand:QI 0 "general_operand" "=g") ! 828: (and:QI (match_operand:QI 1 "general_operand" "g") ! 829: (not:QI (match_operand:QI 2 "general_operand" "g"))))] ! 830: "" ! 831: " ! 832: { ! 833: extern rtx expand_unop (); ! 834: rtx op = operands[2]; ! 835: if (GET_CODE (op) == CONST_INT) ! 836: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 837: ((1 << 8) - 1) & ~INTVAL (op)); ! 838: else ! 839: operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1); ! 840: }") ! 841: ! 842: (define_insn "andcbsi3" ! 843: [(set (match_operand:SI 0 "general_operand" "=g") ! 844: (and:SI (match_operand:SI 1 "general_operand" "g") ! 845: (not:SI (match_operand:SI 2 "general_operand" "g"))))] ! 846: "" ! 847: "* ! 848: { ! 849: if (rtx_equal_p (operands[0], operands[1])) ! 850: return \"bicl2 %2,%0\"; ! 851: return \"bicl3 %2,%1,%0\"; ! 852: }") ! 853: ! 854: (define_insn "andcbhi3" ! 855: [(set (match_operand:HI 0 "general_operand" "=g") ! 856: (and:HI (match_operand:HI 1 "general_operand" "g") ! 857: (not:HI (match_operand:HI 2 "general_operand" "g"))))] ! 858: "" ! 859: "* ! 860: { ! 861: if (rtx_equal_p (operands[0], operands[1])) ! 862: return \"bicw2 %2,%0\"; ! 863: return \"bicw3 %2,%1,%0\"; ! 864: }") ! 865: ! 866: (define_insn "andcbqi3" ! 867: [(set (match_operand:QI 0 "general_operand" "=g") ! 868: (and:QI (match_operand:QI 1 "general_operand" "g") ! 869: (not:QI (match_operand:QI 2 "general_operand" "g"))))] ! 870: "" ! 871: "* ! 872: { ! 873: if (rtx_equal_p (operands[0], operands[1])) ! 874: return \"bicb2 %2,%0\"; ! 875: return \"bicb3 %2,%1,%0\"; ! 876: }") ! 877: ! 878: ;; The following are needed because constant propagation can ! 879: ;; create them starting from the bic insn patterns above. ! 880: ! 881: (define_insn "" ! 882: [(set (match_operand:SI 0 "general_operand" "=g") ! 883: (and:SI (match_operand:SI 1 "general_operand" "g") ! 884: (match_operand:SI 2 "general_operand" "g")))] ! 885: "GET_CODE (operands[2]) == CONST_INT" ! 886: "* ! 887: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); ! 888: if (rtx_equal_p (operands[1], operands[0])) ! 889: return \"bicl2 %2,%0\"; ! 890: return \"bicl3 %2,%1,%0\"; ! 891: }") ! 892: ! 893: (define_insn "" ! 894: [(set (match_operand:HI 0 "general_operand" "=g") ! 895: (and:HI (match_operand:HI 1 "general_operand" "g") ! 896: (match_operand:HI 2 "general_operand" "g")))] ! 897: "GET_CODE (operands[2]) == CONST_INT" ! 898: "* ! 899: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2])); ! 900: if (rtx_equal_p (operands[1], operands[0])) ! 901: return \"bicw2 %2,%0\"; ! 902: return \"bicw3 %2,%1,%0\"; ! 903: }") ! 904: ! 905: (define_insn "" ! 906: [(set (match_operand:QI 0 "general_operand" "=g") ! 907: (and:QI (match_operand:QI 1 "general_operand" "g") ! 908: (match_operand:QI 2 "general_operand" "g")))] ! 909: "GET_CODE (operands[2]) == CONST_INT" ! 910: "* ! 911: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2])); ! 912: if (rtx_equal_p (operands[1], operands[0])) ! 913: return \"bicb2 %2,%0\"; ! 914: return \"bicb3 %2,%1,%0\"; ! 915: }") ! 916: ! 917: ;;- Bit set instructions. ! 918: ! 919: (define_insn "iorsi3" ! 920: [(set (match_operand:SI 0 "general_operand" "=g") ! 921: (ior:SI (match_operand:SI 1 "general_operand" "g") ! 922: (match_operand:SI 2 "general_operand" "g")))] ! 923: "" ! 924: "* ! 925: { ! 926: if (rtx_equal_p (operands[0], operands[1])) ! 927: return \"bisl2 %2,%0\"; ! 928: if (rtx_equal_p (operands[0], operands[2])) ! 929: return \"bisl2 %1,%0\"; ! 930: return \"bisl3 %2,%1,%0\"; ! 931: }") ! 932: ! 933: (define_insn "iorhi3" ! 934: [(set (match_operand:HI 0 "general_operand" "=g") ! 935: (ior:HI (match_operand:HI 1 "general_operand" "g") ! 936: (match_operand:HI 2 "general_operand" "g")))] ! 937: "" ! 938: "* ! 939: { ! 940: if (rtx_equal_p (operands[0], operands[1])) ! 941: return \"bisw2 %2,%0\"; ! 942: if (rtx_equal_p (operands[0], operands[2])) ! 943: return \"bisw2 %1,%0\"; ! 944: return \"bisw3 %2,%1,%0\"; ! 945: }") ! 946: ! 947: (define_insn "iorqi3" ! 948: [(set (match_operand:QI 0 "general_operand" "=g") ! 949: (ior:QI (match_operand:QI 1 "general_operand" "g") ! 950: (match_operand:QI 2 "general_operand" "g")))] ! 951: "" ! 952: "* ! 953: { ! 954: if (rtx_equal_p (operands[0], operands[1])) ! 955: return \"bisb2 %2,%0\"; ! 956: if (rtx_equal_p (operands[0], operands[2])) ! 957: return \"bisb2 %1,%0\"; ! 958: return \"bisb3 %2,%1,%0\"; ! 959: }") ! 960: ! 961: ;;- xor instructions. ! 962: ! 963: (define_insn "xorsi3" ! 964: [(set (match_operand:SI 0 "general_operand" "=g") ! 965: (xor:SI (match_operand:SI 1 "general_operand" "g") ! 966: (match_operand:SI 2 "general_operand" "g")))] ! 967: "" ! 968: "* ! 969: { ! 970: if (rtx_equal_p (operands[0], operands[1])) ! 971: return \"xorl2 %2,%0\"; ! 972: if (rtx_equal_p (operands[0], operands[2])) ! 973: return \"xorl2 %1,%0\"; ! 974: return \"xorl3 %2,%1,%0\"; ! 975: }") ! 976: ! 977: (define_insn "xorhi3" ! 978: [(set (match_operand:HI 0 "general_operand" "=g") ! 979: (xor:HI (match_operand:HI 1 "general_operand" "g") ! 980: (match_operand:HI 2 "general_operand" "g")))] ! 981: "" ! 982: "* ! 983: { ! 984: if (rtx_equal_p (operands[0], operands[1])) ! 985: return \"xorw2 %2,%0\"; ! 986: if (rtx_equal_p (operands[0], operands[2])) ! 987: return \"xorw2 %1,%0\"; ! 988: return \"xorw3 %2,%1,%0\"; ! 989: }") ! 990: ! 991: (define_insn "xorqi3" ! 992: [(set (match_operand:QI 0 "general_operand" "=g") ! 993: (xor:QI (match_operand:QI 1 "general_operand" "g") ! 994: (match_operand:QI 2 "general_operand" "g")))] ! 995: "" ! 996: "* ! 997: { ! 998: if (rtx_equal_p (operands[0], operands[1])) ! 999: return \"xorb2 %2,%0\"; ! 1000: if (rtx_equal_p (operands[0], operands[2])) ! 1001: return \"xorb2 %1,%0\"; ! 1002: return \"xorb3 %2,%1,%0\"; ! 1003: }") ! 1004: ! 1005: (define_insn "negdf2" ! 1006: [(set (match_operand:DF 0 "general_operand" "=g") ! 1007: (neg:DF (match_operand:DF 1 "general_operand" "gF")))] ! 1008: "" ! 1009: "mneg%# %1,%0") ! 1010: ! 1011: (define_insn "negsf2" ! 1012: [(set (match_operand:SF 0 "general_operand" "=g") ! 1013: (neg:SF (match_operand:SF 1 "general_operand" "gF")))] ! 1014: "" ! 1015: "mnegf %1,%0") ! 1016: ! 1017: (define_insn "negsi2" ! 1018: [(set (match_operand:SI 0 "general_operand" "=g") ! 1019: (neg:SI (match_operand:SI 1 "general_operand" "g")))] ! 1020: "" ! 1021: "mnegl %1,%0") ! 1022: ! 1023: (define_insn "neghi2" ! 1024: [(set (match_operand:HI 0 "general_operand" "=g") ! 1025: (neg:HI (match_operand:HI 1 "general_operand" "g")))] ! 1026: "" ! 1027: "mnegw %1,%0") ! 1028: ! 1029: (define_insn "negqi2" ! 1030: [(set (match_operand:QI 0 "general_operand" "=g") ! 1031: (neg:QI (match_operand:QI 1 "general_operand" "g")))] ! 1032: "" ! 1033: "mnegb %1,%0") ! 1034: ! 1035: (define_insn "one_cmplsi2" ! 1036: [(set (match_operand:SI 0 "general_operand" "=g") ! 1037: (not:SI (match_operand:SI 1 "general_operand" "g")))] ! 1038: "" ! 1039: "mcoml %1,%0") ! 1040: ! 1041: (define_insn "one_cmplhi2" ! 1042: [(set (match_operand:HI 0 "general_operand" "=g") ! 1043: (not:HI (match_operand:HI 1 "general_operand" "g")))] ! 1044: "" ! 1045: "mcomw %1,%0") ! 1046: ! 1047: (define_insn "one_cmplqi2" ! 1048: [(set (match_operand:QI 0 "general_operand" "=g") ! 1049: (not:QI (match_operand:QI 1 "general_operand" "g")))] ! 1050: "" ! 1051: "mcomb %1,%0") ! 1052: ! 1053: ;; Arithmetic right shift on the vax works by negating the shift count. ! 1054: (define_expand "ashrsi3" ! 1055: [(set (match_operand:SI 0 "general_operand" "=g") ! 1056: (ashift:SI (match_operand:SI 1 "general_operand" "g") ! 1057: (match_operand:QI 2 "general_operand" "g")))] ! 1058: "" ! 1059: " ! 1060: { ! 1061: operands[2] = negate_rtx (QImode, operands[2]); ! 1062: }") ! 1063: ! 1064: (define_insn "ashlsi3" ! 1065: [(set (match_operand:SI 0 "general_operand" "=g") ! 1066: (ashift:SI (match_operand:SI 1 "general_operand" "g") ! 1067: (match_operand:QI 2 "general_operand" "g")))] ! 1068: "" ! 1069: "* ! 1070: { ! 1071: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) ! 1072: return \"addl2 %0,%0\"; ! 1073: if (GET_CODE (operands[1]) == REG ! 1074: && GET_CODE (operands[2]) == CONST_INT) ! 1075: { ! 1076: int i = INTVAL (operands[2]); ! 1077: if (i == 1) ! 1078: return \"addl3 %1,%1,%0\"; ! 1079: if (i == 2) ! 1080: return \"moval 0[%1],%0\"; ! 1081: if (i == 3) ! 1082: return \"movad 0[%1],%0\"; ! 1083: } ! 1084: return \"ashl %2,%1,%0\"; ! 1085: }") ! 1086: ! 1087: ;; Arithmetic right shift on the vax works by negating the shift count. ! 1088: (define_expand "ashrdi3" ! 1089: [(set (match_operand:DI 0 "general_operand" "=g") ! 1090: (ashift:DI (match_operand:DI 1 "general_operand" "g") ! 1091: (match_operand:QI 2 "general_operand" "g")))] ! 1092: "" ! 1093: " ! 1094: { ! 1095: operands[2] = negate_rtx (QImode, operands[2]); ! 1096: }") ! 1097: ! 1098: (define_insn "ashldi3" ! 1099: [(set (match_operand:DI 0 "general_operand" "=g") ! 1100: (ashift:DI (match_operand:DI 1 "general_operand" "g") ! 1101: (match_operand:QI 2 "general_operand" "g")))] ! 1102: "" ! 1103: "ashq %2,%1,%0") ! 1104: ! 1105: ;; Rotate right on the vax works by negating the shift count. ! 1106: (define_expand "rotrsi3" ! 1107: [(set (match_operand:SI 0 "general_operand" "=g") ! 1108: (rotate:SI (match_operand:SI 1 "general_operand" "g") ! 1109: (match_operand:QI 2 "general_operand" "g")))] ! 1110: "" ! 1111: " ! 1112: { ! 1113: operands[2] = negate_rtx (QImode, operands[2]); ! 1114: }") ! 1115: ! 1116: (define_insn "rotlsi3" ! 1117: [(set (match_operand:SI 0 "general_operand" "=g") ! 1118: (rotate:SI (match_operand:SI 1 "general_operand" "g") ! 1119: (match_operand:QI 2 "general_operand" "g")))] ! 1120: "" ! 1121: "rotl %2,%1,%0") ! 1122: ! 1123: ;This insn is probably slower than a multiply and an add. ! 1124: ;(define_insn "" ! 1125: ; [(set (match_operand:SI 0 "general_operand" "=g") ! 1126: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") ! 1127: ; (match_operand:SI 2 "general_operand" "g")) ! 1128: ; (match_operand:SI 3 "general_operand" "g")))] ! 1129: ; "" ! 1130: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") ! 1131: ! 1132: ;; Special cases of bit-field insns which we should ! 1133: ;; recognize in preference to the general case. ! 1134: ;; These handle aligned 8-bit and 16-bit fields, ! 1135: ;; which can usually be done with move instructions. ! 1136: ! 1137: (define_insn "" ! 1138: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro") ! 1139: (match_operand:SI 1 "immediate_operand" "i") ! 1140: (match_operand:SI 2 "immediate_operand" "i")) ! 1141: (match_operand:SI 3 "general_operand" "g"))] ! 1142: "GET_CODE (operands[1]) == CONST_INT ! 1143: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) ! 1144: && GET_CODE (operands[2]) == CONST_INT ! 1145: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 ! 1146: && (GET_CODE (operands[0]) == REG ! 1147: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1148: "* ! 1149: { ! 1150: if (REG_P (operands[0])) ! 1151: { ! 1152: if (INTVAL (operands[2]) != 0) ! 1153: return \"insv %3,%2,%1,%0\"; ! 1154: } ! 1155: else ! 1156: operands[0] ! 1157: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); ! 1158: ! 1159: if (INTVAL (operands[1]) == 8) ! 1160: return \"movb %3,%0\"; ! 1161: return \"movw %3,%0\"; ! 1162: }") ! 1163: ! 1164: (define_insn "" ! 1165: [(set (match_operand:SI 0 "general_operand" "=&g") ! 1166: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro") ! 1167: (match_operand:SI 2 "immediate_operand" "i") ! 1168: (match_operand:SI 3 "immediate_operand" "i")))] ! 1169: "GET_CODE (operands[2]) == CONST_INT ! 1170: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1171: && GET_CODE (operands[3]) == CONST_INT ! 1172: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 1173: && (GET_CODE (operands[1]) == REG ! 1174: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 1175: "* ! 1176: { ! 1177: if (REG_P (operands[1])) ! 1178: { ! 1179: if (INTVAL (operands[3]) != 0) ! 1180: return \"extzv %3,%2,%1,%0\"; ! 1181: } ! 1182: else ! 1183: operands[1] ! 1184: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); ! 1185: ! 1186: if (INTVAL (operands[2]) == 8) ! 1187: return \"movzbl %1,%0\"; ! 1188: return \"movzwl %1,%0\"; ! 1189: }") ! 1190: ! 1191: (define_insn "" ! 1192: [(set (match_operand:SI 0 "general_operand" "=g") ! 1193: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro") ! 1194: (match_operand:SI 2 "immediate_operand" "i") ! 1195: (match_operand:SI 3 "immediate_operand" "i")))] ! 1196: "GET_CODE (operands[2]) == CONST_INT ! 1197: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1198: && GET_CODE (operands[3]) == CONST_INT ! 1199: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 1200: && (GET_CODE (operands[1]) == REG ! 1201: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 1202: "* ! 1203: { ! 1204: if (REG_P (operands[1])) ! 1205: { ! 1206: if (INTVAL (operands[3]) != 0) ! 1207: return \"extv %3,%2,%1,%0\"; ! 1208: } ! 1209: else ! 1210: operands[1] ! 1211: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); ! 1212: ! 1213: if (INTVAL (operands[2]) == 8) ! 1214: return \"cvtbl %1,%0\"; ! 1215: return \"cvtwl %1,%0\"; ! 1216: }") ! 1217: ! 1218: ;; Register-only SImode cases of bit-field insns. ! 1219: ! 1220: (define_insn "" ! 1221: [(set (cc0) ! 1222: (compare ! 1223: (sign_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1224: (match_operand:SI 1 "general_operand" "g") ! 1225: (match_operand:SI 2 "general_operand" "g")) ! 1226: (match_operand:SI 3 "general_operand" "g")))] ! 1227: "" ! 1228: "cmpv %2,%1,%0,%3") ! 1229: ! 1230: (define_insn "" ! 1231: [(set (cc0) ! 1232: (compare ! 1233: (zero_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1234: (match_operand:SI 1 "general_operand" "g") ! 1235: (match_operand:SI 2 "general_operand" "g")) ! 1236: (match_operand:SI 3 "general_operand" "g")))] ! 1237: "" ! 1238: "cmpzv %2,%1,%0,%3") ! 1239: ! 1240: (define_insn "" ! 1241: [(set (match_operand:SI 0 "general_operand" "=g") ! 1242: (sign_extract:SI (match_operand:SI 1 "general_operand" "r") ! 1243: (match_operand:SI 2 "general_operand" "g") ! 1244: (match_operand:SI 3 "general_operand" "g")))] ! 1245: "" ! 1246: "extv %3,%2,%1,%0") ! 1247: ! 1248: (define_insn "" ! 1249: [(set (match_operand:SI 0 "general_operand" "=g") ! 1250: (zero_extract:SI (match_operand:SI 1 "general_operand" "r") ! 1251: (match_operand:SI 2 "general_operand" "g") ! 1252: (match_operand:SI 3 "general_operand" "g")))] ! 1253: "" ! 1254: "extzv %3,%2,%1,%0") ! 1255: ! 1256: ;; Non-register cases. ! 1257: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases ! 1258: ;; don't match these (and therefore match the cases above instead). ! 1259: ! 1260: (define_insn "" ! 1261: [(set (cc0) ! 1262: (compare ! 1263: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") ! 1264: (match_operand:SI 1 "general_operand" "g") ! 1265: (match_operand:SI 2 "general_operand" "g")) ! 1266: (match_operand:SI 3 "general_operand" "g")))] ! 1267: "" ! 1268: "cmpv %2,%1,%0,%3") ! 1269: ! 1270: (define_insn "" ! 1271: [(set (cc0) ! 1272: (compare ! 1273: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") ! 1274: (match_operand:SI 1 "general_operand" "g") ! 1275: (match_operand:SI 2 "general_operand" "g")) ! 1276: (match_operand:SI 3 "general_operand" "g")))] ! 1277: "" ! 1278: "cmpzv %2,%1,%0,%3") ! 1279: ! 1280: (define_insn "extv" ! 1281: [(set (match_operand:SI 0 "general_operand" "=g") ! 1282: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") ! 1283: (match_operand:SI 2 "general_operand" "g") ! 1284: (match_operand:SI 3 "general_operand" "g")))] ! 1285: "" ! 1286: "extv %3,%2,%1,%0") ! 1287: ! 1288: (define_insn "extzv" ! 1289: [(set (match_operand:SI 0 "general_operand" "=g") ! 1290: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") ! 1291: (match_operand:SI 2 "general_operand" "g") ! 1292: (match_operand:SI 3 "general_operand" "g")))] ! 1293: "" ! 1294: "extzv %3,%2,%1,%0") ! 1295: ! 1296: (define_insn "insv" ! 1297: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g") ! 1298: (match_operand:SI 1 "general_operand" "g") ! 1299: (match_operand:SI 2 "general_operand" "g")) ! 1300: (match_operand:SI 3 "general_operand" "g"))] ! 1301: "" ! 1302: "insv %3,%2,%1,%0") ! 1303: ! 1304: (define_insn "" ! 1305: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ! 1306: (match_operand:SI 1 "general_operand" "g") ! 1307: (match_operand:SI 2 "general_operand" "g")) ! 1308: (match_operand:SI 3 "general_operand" "g"))] ! 1309: "" ! 1310: "insv %3,%2,%1,%0") ! 1311: ! 1312: (define_insn "jump" ! 1313: [(set (pc) ! 1314: (label_ref (match_operand 0 "" "")))] ! 1315: "" ! 1316: "jbr %l0") ! 1317: ! 1318: (define_insn "beq" ! 1319: [(set (pc) ! 1320: (if_then_else (eq (cc0) ! 1321: (const_int 0)) ! 1322: (label_ref (match_operand 0 "" "")) ! 1323: (pc)))] ! 1324: "" ! 1325: "jeql %l0") ! 1326: ! 1327: (define_insn "bne" ! 1328: [(set (pc) ! 1329: (if_then_else (ne (cc0) ! 1330: (const_int 0)) ! 1331: (label_ref (match_operand 0 "" "")) ! 1332: (pc)))] ! 1333: "" ! 1334: "jneq %l0") ! 1335: ! 1336: (define_insn "bgt" ! 1337: [(set (pc) ! 1338: (if_then_else (gt (cc0) ! 1339: (const_int 0)) ! 1340: (label_ref (match_operand 0 "" "")) ! 1341: (pc)))] ! 1342: "" ! 1343: "jgtr %l0") ! 1344: ! 1345: (define_insn "bgtu" ! 1346: [(set (pc) ! 1347: (if_then_else (gtu (cc0) ! 1348: (const_int 0)) ! 1349: (label_ref (match_operand 0 "" "")) ! 1350: (pc)))] ! 1351: "" ! 1352: "jgtru %l0") ! 1353: ! 1354: (define_insn "blt" ! 1355: [(set (pc) ! 1356: (if_then_else (lt (cc0) ! 1357: (const_int 0)) ! 1358: (label_ref (match_operand 0 "" "")) ! 1359: (pc)))] ! 1360: "" ! 1361: "jlss %l0") ! 1362: ! 1363: (define_insn "bltu" ! 1364: [(set (pc) ! 1365: (if_then_else (ltu (cc0) ! 1366: (const_int 0)) ! 1367: (label_ref (match_operand 0 "" "")) ! 1368: (pc)))] ! 1369: "" ! 1370: "jlssu %l0") ! 1371: ! 1372: (define_insn "bge" ! 1373: [(set (pc) ! 1374: (if_then_else (ge (cc0) ! 1375: (const_int 0)) ! 1376: (label_ref (match_operand 0 "" "")) ! 1377: (pc)))] ! 1378: "" ! 1379: "jgeq %l0") ! 1380: ! 1381: (define_insn "bgeu" ! 1382: [(set (pc) ! 1383: (if_then_else (geu (cc0) ! 1384: (const_int 0)) ! 1385: (label_ref (match_operand 0 "" "")) ! 1386: (pc)))] ! 1387: "" ! 1388: "jgequ %l0") ! 1389: ! 1390: (define_insn "ble" ! 1391: [(set (pc) ! 1392: (if_then_else (le (cc0) ! 1393: (const_int 0)) ! 1394: (label_ref (match_operand 0 "" "")) ! 1395: (pc)))] ! 1396: "" ! 1397: "jleq %l0") ! 1398: ! 1399: (define_insn "bleu" ! 1400: [(set (pc) ! 1401: (if_then_else (leu (cc0) ! 1402: (const_int 0)) ! 1403: (label_ref (match_operand 0 "" "")) ! 1404: (pc)))] ! 1405: "" ! 1406: "jlequ %l0") ! 1407: ! 1408: (define_insn "" ! 1409: [(set (pc) ! 1410: (if_then_else (eq (cc0) ! 1411: (const_int 0)) ! 1412: (pc) ! 1413: (label_ref (match_operand 0 "" ""))))] ! 1414: "" ! 1415: "jneq %l0") ! 1416: ! 1417: (define_insn "" ! 1418: [(set (pc) ! 1419: (if_then_else (ne (cc0) ! 1420: (const_int 0)) ! 1421: (pc) ! 1422: (label_ref (match_operand 0 "" ""))))] ! 1423: "" ! 1424: "jeql %l0") ! 1425: ! 1426: (define_insn "" ! 1427: [(set (pc) ! 1428: (if_then_else (gt (cc0) ! 1429: (const_int 0)) ! 1430: (pc) ! 1431: (label_ref (match_operand 0 "" ""))))] ! 1432: "" ! 1433: "jleq %l0") ! 1434: ! 1435: (define_insn "" ! 1436: [(set (pc) ! 1437: (if_then_else (gtu (cc0) ! 1438: (const_int 0)) ! 1439: (pc) ! 1440: (label_ref (match_operand 0 "" ""))))] ! 1441: "" ! 1442: "jlequ %l0") ! 1443: ! 1444: (define_insn "" ! 1445: [(set (pc) ! 1446: (if_then_else (lt (cc0) ! 1447: (const_int 0)) ! 1448: (pc) ! 1449: (label_ref (match_operand 0 "" ""))))] ! 1450: "" ! 1451: "jgeq %l0") ! 1452: ! 1453: (define_insn "" ! 1454: [(set (pc) ! 1455: (if_then_else (ltu (cc0) ! 1456: (const_int 0)) ! 1457: (pc) ! 1458: (label_ref (match_operand 0 "" ""))))] ! 1459: "" ! 1460: "jgequ %l0") ! 1461: ! 1462: (define_insn "" ! 1463: [(set (pc) ! 1464: (if_then_else (ge (cc0) ! 1465: (const_int 0)) ! 1466: (pc) ! 1467: (label_ref (match_operand 0 "" ""))))] ! 1468: "" ! 1469: "jlss %l0") ! 1470: ! 1471: (define_insn "" ! 1472: [(set (pc) ! 1473: (if_then_else (geu (cc0) ! 1474: (const_int 0)) ! 1475: (pc) ! 1476: (label_ref (match_operand 0 "" ""))))] ! 1477: "" ! 1478: "jlssu %l0") ! 1479: ! 1480: (define_insn "" ! 1481: [(set (pc) ! 1482: (if_then_else (le (cc0) ! 1483: (const_int 0)) ! 1484: (pc) ! 1485: (label_ref (match_operand 0 "" ""))))] ! 1486: "" ! 1487: "jgtr %l0") ! 1488: ! 1489: (define_insn "" ! 1490: [(set (pc) ! 1491: (if_then_else (leu (cc0) ! 1492: (const_int 0)) ! 1493: (pc) ! 1494: (label_ref (match_operand 0 "" ""))))] ! 1495: "" ! 1496: "jgtru %l0") ! 1497: ! 1498: ;; Recognize jlbs and jlbc insns. ! 1499: ;; These come before the jbc and jbs recognizers so these will be preferred. ! 1500: ! 1501: (define_insn "" ! 1502: [(set (pc) ! 1503: (if_then_else ! 1504: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1505: (const_int 1)) ! 1506: (const_int 0)) ! 1507: (label_ref (match_operand 1 "" "")) ! 1508: (pc)))] ! 1509: "GET_CODE (operands[0]) != MEM ! 1510: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1511: "jlbs %0,%l1") ! 1512: ! 1513: (define_insn "" ! 1514: [(set (pc) ! 1515: (if_then_else ! 1516: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1517: (const_int 1)) ! 1518: (const_int 0)) ! 1519: (label_ref (match_operand 1 "" "")) ! 1520: (pc)))] ! 1521: "GET_CODE (operands[0]) != MEM ! 1522: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1523: "jlbc %0,%l1") ! 1524: ! 1525: (define_insn "" ! 1526: [(set (pc) ! 1527: (if_then_else ! 1528: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1529: (const_int 1)) ! 1530: (const_int 0)) ! 1531: (pc) ! 1532: (label_ref (match_operand 1 "" ""))))] ! 1533: "GET_CODE (operands[0]) != MEM ! 1534: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1535: "jlbc %0,%l1") ! 1536: ! 1537: (define_insn "" ! 1538: [(set (pc) ! 1539: (if_then_else ! 1540: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1541: (const_int 1)) ! 1542: (const_int 0)) ! 1543: (pc) ! 1544: (label_ref (match_operand 1 "" ""))))] ! 1545: "GET_CODE (operands[0]) != MEM ! 1546: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1547: "jlbs %0,%l1") ! 1548: ! 1549: ;; These four entries allow a jlbc or jlbs to be made ! 1550: ;; by combination with a bic. ! 1551: (define_insn "" ! 1552: [(set (pc) ! 1553: (if_then_else ! 1554: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1555: (not:SI (const_int -2))) ! 1556: (const_int 0)) ! 1557: (label_ref (match_operand 1 "" "")) ! 1558: (pc)))] ! 1559: "GET_CODE (operands[0]) != MEM ! 1560: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1561: "jlbs %0,%l1") ! 1562: ! 1563: (define_insn "" ! 1564: [(set (pc) ! 1565: (if_then_else ! 1566: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1567: (not:SI (const_int -2))) ! 1568: (const_int 0)) ! 1569: (label_ref (match_operand 1 "" "")) ! 1570: (pc)))] ! 1571: "GET_CODE (operands[0]) != MEM ! 1572: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1573: "jlbc %0,%l1") ! 1574: ! 1575: (define_insn "" ! 1576: [(set (pc) ! 1577: (if_then_else ! 1578: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1579: (not:SI (const_int -2))) ! 1580: (const_int 0)) ! 1581: (pc) ! 1582: (label_ref (match_operand 1 "" ""))))] ! 1583: "GET_CODE (operands[0]) != MEM ! 1584: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1585: "jlbc %0,%l1") ! 1586: ! 1587: (define_insn "" ! 1588: [(set (pc) ! 1589: (if_then_else ! 1590: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1591: (not:SI (const_int -2))) ! 1592: (const_int 0)) ! 1593: (pc) ! 1594: (label_ref (match_operand 1 "" ""))))] ! 1595: "GET_CODE (operands[0]) != MEM ! 1596: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1597: "jlbs %0,%l1") ! 1598: ! 1599: ;; Recognize jbs and jbc instructions. ! 1600: ! 1601: (define_insn "" ! 1602: [(set (pc) ! 1603: (if_then_else ! 1604: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1605: (const_int 1) ! 1606: (match_operand:SI 1 "general_operand" "g")) ! 1607: (const_int 0)) ! 1608: (label_ref (match_operand 2 "" "")) ! 1609: (pc)))] ! 1610: "" ! 1611: "jbs %1,%0,%l2") ! 1612: ! 1613: (define_insn "" ! 1614: [(set (pc) ! 1615: (if_then_else ! 1616: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1617: (const_int 1) ! 1618: (match_operand:SI 1 "general_operand" "g")) ! 1619: (const_int 0)) ! 1620: (label_ref (match_operand 2 "" "")) ! 1621: (pc)))] ! 1622: "" ! 1623: "jbc %1,%0,%l2") ! 1624: ! 1625: (define_insn "" ! 1626: [(set (pc) ! 1627: (if_then_else ! 1628: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1629: (const_int 1) ! 1630: (match_operand:SI 1 "general_operand" "g")) ! 1631: (const_int 0)) ! 1632: (pc) ! 1633: (label_ref (match_operand 2 "" ""))))] ! 1634: "" ! 1635: "jbc %1,%0,%l2") ! 1636: ! 1637: (define_insn "" ! 1638: [(set (pc) ! 1639: (if_then_else ! 1640: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1641: (const_int 1) ! 1642: (match_operand:SI 1 "general_operand" "g")) ! 1643: (const_int 0)) ! 1644: (pc) ! 1645: (label_ref (match_operand 2 "" ""))))] ! 1646: "" ! 1647: "jbs %1,%0,%l2") ! 1648: ! 1649: (define_insn "" ! 1650: [(set (pc) ! 1651: (if_then_else ! 1652: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1653: (const_int 1) ! 1654: (match_operand:SI 1 "general_operand" "g")) ! 1655: (const_int 0)) ! 1656: (label_ref (match_operand 2 "" "")) ! 1657: (pc)))] ! 1658: "GET_CODE (operands[0]) != MEM ! 1659: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1660: "jbs %1,%0,%l2") ! 1661: ! 1662: (define_insn "" ! 1663: [(set (pc) ! 1664: (if_then_else ! 1665: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1666: (const_int 1) ! 1667: (match_operand:SI 1 "general_operand" "g")) ! 1668: (const_int 0)) ! 1669: (label_ref (match_operand 2 "" "")) ! 1670: (pc)))] ! 1671: "GET_CODE (operands[0]) != MEM ! 1672: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1673: "jbc %1,%0,%l2") ! 1674: ! 1675: (define_insn "" ! 1676: [(set (pc) ! 1677: (if_then_else ! 1678: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1679: (match_operand:SI 1 "general_operand" "g")) ! 1680: (const_int 0)) ! 1681: (pc) ! 1682: (label_ref (match_operand 2 "" ""))))] ! 1683: "GET_CODE (operands[1]) == CONST_INT ! 1684: && exact_log2 (INTVAL (operands[1])) >= 0 ! 1685: && (GET_CODE (operands[0]) != MEM ! 1686: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1687: "* ! 1688: { ! 1689: operands[1] ! 1690: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1691: return \"jbs %1,%0,%l2\"; ! 1692: }") ! 1693: ! 1694: (define_insn "" ! 1695: [(set (pc) ! 1696: (if_then_else ! 1697: (eq (and:SI (match_operand:SI 0 "general_operand" "g") ! 1698: (match_operand:SI 1 "general_operand" "g")) ! 1699: (const_int 0)) ! 1700: (label_ref (match_operand 2 "" "")) ! 1701: (pc)))] ! 1702: "GET_CODE (operands[1]) == CONST_INT ! 1703: && exact_log2 (INTVAL (operands[1])) >= 0 ! 1704: && (GET_CODE (operands[0]) != MEM ! 1705: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1706: "* ! 1707: { ! 1708: operands[1] ! 1709: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1710: return \"jbc %1,%0,%l2\"; ! 1711: }") ! 1712: ! 1713: (define_insn "" ! 1714: [(set (pc) ! 1715: (if_then_else ! 1716: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1717: (match_operand:SI 1 "general_operand" "g")) ! 1718: (const_int 0)) ! 1719: (pc) ! 1720: (label_ref (match_operand 2 "" ""))))] ! 1721: "GET_CODE (operands[1]) == CONST_INT ! 1722: && exact_log2 (INTVAL (operands[1])) >= 0 ! 1723: && (GET_CODE (operands[0]) != MEM ! 1724: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1725: "* ! 1726: { ! 1727: operands[1] ! 1728: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1729: return \"jbc %1,%0,%l2\"; ! 1730: }") ! 1731: ! 1732: (define_insn "" ! 1733: [(set (pc) ! 1734: (if_then_else ! 1735: (ne (and:SI (match_operand:SI 0 "general_operand" "g") ! 1736: (match_operand:SI 1 "general_operand" "g")) ! 1737: (const_int 0)) ! 1738: (label_ref (match_operand 2 "" "")) ! 1739: (pc)))] ! 1740: "GET_CODE (operands[1]) == CONST_INT ! 1741: && exact_log2 (INTVAL (operands[1])) >= 0 ! 1742: && (GET_CODE (operands[0]) != MEM ! 1743: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1744: "* ! 1745: { ! 1746: operands[1] ! 1747: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1748: return \"jbs %1,%0,%l2\"; ! 1749: }") ! 1750: ! 1751: (define_insn "" ! 1752: [(set (pc) ! 1753: (if_then_else ! 1754: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1755: (const_int 1) ! 1756: (match_operand:SI 1 "general_operand" "g")) ! 1757: (const_int 0)) ! 1758: (pc) ! 1759: (label_ref (match_operand 2 "" ""))))] ! 1760: "GET_CODE (operands[0]) != MEM ! 1761: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1762: "jbc %1,%0,%l2") ! 1763: ! 1764: (define_insn "" ! 1765: [(set (pc) ! 1766: (if_then_else ! 1767: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r") ! 1768: (const_int 1) ! 1769: (match_operand:SI 1 "general_operand" "g")) ! 1770: (const_int 0)) ! 1771: (pc) ! 1772: (label_ref (match_operand 2 "" ""))))] ! 1773: "GET_CODE (operands[0]) != MEM ! 1774: || ! mode_dependent_address_p (XEXP (operands[0], 0))" ! 1775: "jbs %1,%0,%l2") ! 1776: ! 1777: ;; Subtract-and-jump and Add-and-jump insns. ! 1778: ;; These are not used when output is for the Unix assembler ! 1779: ;; because it does not know how to modify them to reach far. ! 1780: ! 1781: ;; Normal sob insns. ! 1782: ! 1783: (define_insn "" ! 1784: [(set (pc) ! 1785: (if_then_else ! 1786: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1787: (const_int -1)) ! 1788: (const_int 0)) ! 1789: (label_ref (match_operand 1 "" "")) ! 1790: (pc))) ! 1791: (set (match_dup 0) ! 1792: (plus:SI (match_dup 0) ! 1793: (const_int -1)))] ! 1794: "!TARGET_UNIX_ASM" ! 1795: "jsobgtr %0,%l1") ! 1796: ! 1797: (define_insn "" ! 1798: [(set (pc) ! 1799: (if_then_else ! 1800: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1801: (const_int -1)) ! 1802: (const_int 0)) ! 1803: (label_ref (match_operand 1 "" "")) ! 1804: (pc))) ! 1805: (set (match_dup 0) ! 1806: (plus:SI (match_dup 0) ! 1807: (const_int -1)))] ! 1808: "!TARGET_UNIX_ASM" ! 1809: "jsobgeq %0,%l1") ! 1810: ! 1811: ;; Reversed sob insns. ! 1812: ! 1813: (define_insn "" ! 1814: [(set (pc) ! 1815: (if_then_else ! 1816: (le (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1817: (const_int -1)) ! 1818: (const_int 0)) ! 1819: (pc) ! 1820: (label_ref (match_operand 1 "" "")))) ! 1821: (set (match_dup 0) ! 1822: (plus:SI (match_dup 0) ! 1823: (const_int -1)))] ! 1824: "!TARGET_UNIX_ASM" ! 1825: "jsobgtr %0,%l1") ! 1826: ! 1827: (define_insn "" ! 1828: [(set (pc) ! 1829: (if_then_else ! 1830: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1831: (const_int -1)) ! 1832: (const_int 0)) ! 1833: (pc) ! 1834: (label_ref (match_operand 1 "" "")))) ! 1835: (set (match_dup 0) ! 1836: (plus:SI (match_dup 0) ! 1837: (const_int -1)))] ! 1838: "!TARGET_UNIX_ASM" ! 1839: "jsobgeq %0,%l1") ! 1840: ! 1841: ;; Normal aob insns. ! 1842: (define_insn "" ! 1843: [(set (pc) ! 1844: (if_then_else ! 1845: (lt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1846: (const_int 1)) ! 1847: (match_operand:SI 1 "general_operand" "g")) ! 1848: (const_int 0)) ! 1849: (label_ref (match_operand 2 "" "")) ! 1850: (pc))) ! 1851: (set (match_dup 0) ! 1852: (plus:SI (match_dup 0) ! 1853: (const_int 1)))] ! 1854: "!TARGET_UNIX_ASM" ! 1855: "jaoblss %1,%0,%l2") ! 1856: ! 1857: (define_insn "" ! 1858: [(set (pc) ! 1859: (if_then_else ! 1860: (le (compare (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1861: (const_int 1)) ! 1862: (match_operand:SI 1 "general_operand" "g")) ! 1863: (const_int 0)) ! 1864: (label_ref (match_operand 2 "" "")) ! 1865: (pc))) ! 1866: (set (match_dup 0) ! 1867: (plus:SI (match_dup 0) ! 1868: (const_int 1)))] ! 1869: "!TARGET_UNIX_ASM" ! 1870: "jaobleq %1,%0,%l2") ! 1871: ! 1872: ;; Reverse aob insns. ! 1873: (define_insn "" ! 1874: [(set (pc) ! 1875: (if_then_else ! 1876: (ge (compare (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1877: (const_int 1)) ! 1878: (match_operand:SI 1 "general_operand" "g")) ! 1879: (const_int 0)) ! 1880: (pc) ! 1881: (label_ref (match_operand 2 "" "")))) ! 1882: (set (match_dup 0) ! 1883: (plus:SI (match_dup 0) ! 1884: (const_int 1)))] ! 1885: "!TARGET_UNIX_ASM" ! 1886: "jaoblss %1,%0,%l2") ! 1887: ! 1888: (define_insn "" ! 1889: [(set (pc) ! 1890: (if_then_else ! 1891: (gt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 1892: (const_int 1)) ! 1893: (match_operand:SI 1 "general_operand" "g")) ! 1894: (const_int 0)) ! 1895: (pc) ! 1896: (label_ref (match_operand 2 "" "")))) ! 1897: (set (match_dup 0) ! 1898: (plus:SI (match_dup 0) ! 1899: (const_int 1)))] ! 1900: "!TARGET_UNIX_ASM" ! 1901: "jaobleq %1,%0,%l2") ! 1902: ! 1903: ;; Something like a sob insn, but compares against -1. ! 1904: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'. ! 1905: ! 1906: (define_insn "" ! 1907: [(set (pc) ! 1908: (if_then_else ! 1909: (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "g") ! 1910: (const_int -1)) ! 1911: (const_int -1)) ! 1912: (const_int 0)) ! 1913: (label_ref (match_operand 1 "" "")) ! 1914: (pc))) ! 1915: (set (match_dup 0) ! 1916: (plus:SI (match_dup 0) ! 1917: (const_int -1)))] ! 1918: "" ! 1919: "decl %0\;jgequ %l1") ! 1920: ! 1921: ;; Note that operand 1 is total size of args, in bytes, ! 1922: ;; and what the call insn wants is the number of words. ! 1923: (define_insn "call" ! 1924: [(call (match_operand:QI 0 "general_operand" "g") ! 1925: (match_operand:QI 1 "general_operand" "g"))] ! 1926: "" ! 1927: "* ! 1928: if (INTVAL (operands[1]) > 255 * 4) ! 1929: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ ! 1930: return \"calls $0,%0\;addl2 %1,sp\"; ! 1931: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4); ! 1932: return \"calls %1,%0\"; ! 1933: ") ! 1934: ! 1935: (define_insn "call_value" ! 1936: [(set (match_operand 0 "" "=g") ! 1937: (call (match_operand:QI 1 "general_operand" "g") ! 1938: (match_operand:QI 2 "general_operand" "g")))] ! 1939: "" ! 1940: "* ! 1941: if (INTVAL (operands[2]) > 255 * 4) ! 1942: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ ! 1943: return \"calls $0,%1\;addl2 %2,sp\"; ! 1944: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4); ! 1945: return \"calls %2,%1\"; ! 1946: ") ! 1947: ! 1948: (define_insn "return" ! 1949: [(return)] ! 1950: "" ! 1951: "ret") ! 1952: ! 1953: (define_insn "nop" ! 1954: [(const_int 0)] ! 1955: "" ! 1956: "nop") ! 1957: ! 1958: (define_insn "casesi" ! 1959: [(set (pc) ! 1960: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g") ! 1961: (match_operand:SI 1 "general_operand" "g")) ! 1962: (match_operand:SI 2 "general_operand" "g")) ! 1963: (plus:SI (sign_extend:SI ! 1964: (mem:HI (plus:SI (pc) ! 1965: (minus:SI (match_dup 0) ! 1966: (match_dup 1))))) ! 1967: (label_ref:SI (match_operand 3 "" ""))) ! 1968: (pc)))] ! 1969: "" ! 1970: "casel %0,%1,%2") ! 1971: ! 1972: ;; This used to arise from the preceding by simplification ! 1973: ;; if operand 1 is zero. Perhaps it is no longer necessary. ! 1974: (define_insn "" ! 1975: [(set (pc) ! 1976: (if_then_else (le (match_operand:SI 0 "general_operand" "g") ! 1977: (match_operand:SI 1 "general_operand" "g")) ! 1978: (plus:SI (sign_extend:SI ! 1979: (mem:HI (plus:SI (pc) ! 1980: (minus:SI (match_dup 0) ! 1981: (const_int 0))))) ! 1982: (label_ref:SI (match_operand 3 "" ""))) ! 1983: (pc)))] ! 1984: "" ! 1985: "casel %0,$0,%1") ! 1986: ! 1987: ;; This arises from the preceding by simplification if operand 1 is zero. ! 1988: (define_insn "" ! 1989: [(set (pc) ! 1990: (if_then_else (le (match_operand:SI 0 "general_operand" "g") ! 1991: (match_operand:SI 1 "general_operand" "g")) ! 1992: (plus:SI (sign_extend:SI ! 1993: (mem:HI (plus:SI (pc) ! 1994: (match_dup 0)))) ! 1995: (label_ref:SI (match_operand 3 "" ""))) ! 1996: (pc)))] ! 1997: "" ! 1998: "casel %0,$0,%1") ! 1999: ! 2000: ;; This arises from casesi if operand 0 is a constant, in range. ! 2001: (define_insn "" ! 2002: [(set (pc) ! 2003: (plus:SI (sign_extend:SI ! 2004: (mem:HI (plus:SI (pc) ! 2005: (match_operand:SI 0 "general_operand" "g")))) ! 2006: (label_ref:SI (match_operand 3 "" ""))))] ! 2007: "" ! 2008: "casel %0,$0,%0") ! 2009: ! 2010: ;;- load or push effective address ! 2011: ;; These come after the move and add/sub patterns ! 2012: ;; because we don't want pushl $1 turned into pushad 1. ! 2013: ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. ! 2014: ! 2015: (define_insn "" ! 2016: [(set (match_operand:SI 0 "general_operand" "=g") ! 2017: (match_operand:QI 1 "address_operand" "p"))] ! 2018: "" ! 2019: "* ! 2020: { ! 2021: if (push_operand (operands[0], SImode)) ! 2022: return \"pushab %a1\"; ! 2023: return \"movab %a1,%0\"; ! 2024: }") ! 2025: ! 2026: (define_insn "" ! 2027: [(set (match_operand:SI 0 "general_operand" "=g") ! 2028: (match_operand:HI 1 "address_operand" "p"))] ! 2029: "" ! 2030: "* ! 2031: { ! 2032: if (push_operand (operands[0], SImode)) ! 2033: return \"pushaw %a1\"; ! 2034: return \"movaw %a1,%0\"; ! 2035: }") ! 2036: ! 2037: (define_insn "" ! 2038: [(set (match_operand:SI 0 "general_operand" "=g") ! 2039: (match_operand:SI 1 "address_operand" "p"))] ! 2040: "" ! 2041: "* ! 2042: { ! 2043: if (push_operand (operands[0], SImode)) ! 2044: return \"pushal %a1\"; ! 2045: return \"moval %a1,%0\"; ! 2046: }") ! 2047: ! 2048: (define_insn "" ! 2049: [(set (match_operand:SI 0 "general_operand" "=g") ! 2050: (match_operand:SF 1 "address_operand" "p"))] ! 2051: "" ! 2052: "* ! 2053: { ! 2054: if (push_operand (operands[0], SImode)) ! 2055: return \"pushaf %a1\"; ! 2056: return \"movaf %a1,%0\"; ! 2057: }") ! 2058: ! 2059: (define_insn "" ! 2060: [(set (match_operand:SI 0 "general_operand" "=g") ! 2061: (match_operand:DF 1 "address_operand" "p"))] ! 2062: "" ! 2063: "* ! 2064: { ! 2065: if (push_operand (operands[0], SImode)) ! 2066: return \"pushad %a1\"; ! 2067: return \"movad %a1,%0\"; ! 2068: }") ! 2069: ! 2070: ;; Optimize extzv ...,z; andl2 ...,z ! 2071: ;; with other operands constant. ! 2072: (define_peephole ! 2073: [(set (match_operand:SI 0 "general_operand" "g") ! 2074: (zero_extract:SI (match_operand:SI 1 "general_operand" "g") ! 2075: (match_operand:SI 2 "general_operand" "g") ! 2076: (match_operand:SI 3 "general_operand" "g"))) ! 2077: (set (match_operand:SI 4 "general_operand" "g") ! 2078: (and:SI (match_dup 0) ! 2079: (match_operand:SI 5 "general_operand" "g")))] ! 2080: "GET_CODE (operands[2]) == CONST_INT ! 2081: && GET_CODE (operands[3]) == CONST_INT ! 2082: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32 ! 2083: && GET_CODE (operands[5]) == CONST_INT ! 2084: && dead_or_set_p (insn, operands[0])" ! 2085: "* ! 2086: { ! 2087: unsigned long mask = INTVAL (operands[5]); ! 2088: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3])); ! 2089: ! 2090: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2])) ! 2091: mask &= ((1 << INTVAL (operands[2])) - 1); ! 2092: ! 2093: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask); ! 2094: if (push_operand (operands[4], SImode)) ! 2095: { ! 2096: output_asm_insn (\"rotl %3,%1,%0\", operands); ! 2097: return \"bicl3 %5,%0,%4\"; ! 2098: } ! 2099: else ! 2100: { ! 2101: output_asm_insn (\"rotl %3,%1,%4\", operands); ! 2102: return \"bicl2 %5,%4\"; ! 2103: } ! 2104: }") ! 2105: ! 2106: ;; Optimize andl3 x,y,z; extzv z,....,z ! 2107: ! 2108: (define_peephole ! 2109: [(set (match_operand:SI 0 "general_operand" "g") ! 2110: (and:SI (match_operand:SI 1 "general_operand" "g") ! 2111: (match_operand:SI 2 "general_operand" "g"))) ! 2112: (set (match_operand 3 "general_operand" "g") ! 2113: (zero_extract:SI (match_dup 0) ! 2114: (match_operand:SI 4 "general_operand" "g") ! 2115: (match_operand:SI 5 "general_operand" "g")))] ! 2116: "GET_CODE (operands[2]) == CONST_INT ! 2117: && GET_CODE (operands[4]) == CONST_INT ! 2118: && GET_CODE (operands[5]) == CONST_INT ! 2119: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32 ! 2120: && dead_or_set_p (insn, operands[0])" ! 2121: "* ! 2122: { ! 2123: unsigned long mask = INTVAL (operands[2]); ! 2124: ! 2125: mask &= ~((1 << INTVAL (operands[5])) - 1); ! 2126: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask); ! 2127: ! 2128: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5])); ! 2129: ! 2130: if (rtx_equal_p (operands[0], operands[1])) ! 2131: output_asm_insn (\"bicl2 %2,%0\", operands); ! 2132: else ! 2133: output_asm_insn (\"bicl3 %2,%1,%0\", operands); ! 2134: return \"rotl %5,%0,%3\"; ! 2135: }") ! 2136: ! 2137: ;;- Local variables: ! 2138: ;;- mode:emacs-lisp ! 2139: ;;- comment-start: ";;- " ! 2140: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2141: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2142: ;;- eval: (modify-syntax-entry ?] ")[") ! 2143: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2144: ;;- eval: (modify-syntax-entry ?} "){") ! 2145: ;;- End:
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