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1.1 root 1: ;;- Machine description for GNU compiler, Vax Version
2: ;; Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
3:
4: ;; This file is part of GNU CC.
5:
6: ;; GNU CC is free software; you can redistribute it and/or modify
7: ;; it under the terms of the GNU General Public License as published by
8: ;; the Free Software Foundation; either version 2, or (at your option)
9: ;; any later version.
10:
11: ;; GNU CC is distributed in the hope that it will be useful,
12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: ;; GNU General Public License for more details.
15:
16: ;; You should have received a copy of the GNU General Public License
17: ;; along with GNU CC; see the file COPYING. If not, write to
18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19:
20:
21: ;;- Instruction patterns. When multiple patterns apply,
22: ;;- the first one in the file is chosen.
23: ;;-
24: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25: ;;-
26: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
27: ;;- updates for most instructions.
28:
29: ;; We don't want to allow a constant operand for test insns because
30: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
31: ;; be folded while optimizing anyway.
32:
33: (define_insn "tstsi"
34: [(set (cc0)
35: (match_operand:SI 0 "nonimmediate_operand" "g"))]
36: ""
37: "tstl %0")
38:
39: (define_insn "tsthi"
40: [(set (cc0)
41: (match_operand:HI 0 "nonimmediate_operand" "g"))]
42: ""
43: "tstw %0")
44:
45: (define_insn "tstqi"
46: [(set (cc0)
47: (match_operand:QI 0 "nonimmediate_operand" "g"))]
48: ""
49: "tstb %0")
50:
51: (define_insn "tstdf"
52: [(set (cc0)
53: (match_operand:DF 0 "general_operand" "gF"))]
54: ""
55: "tst%# %0")
56:
57: (define_insn "tstsf"
58: [(set (cc0)
59: (match_operand:SF 0 "general_operand" "gF"))]
60: ""
61: "tstf %0")
62:
63: (define_insn "cmpsi"
64: [(set (cc0)
65: (compare (match_operand:SI 0 "nonimmediate_operand" "g")
66: (match_operand:SI 1 "general_operand" "g")))]
67: ""
68: "cmpl %0,%1")
69:
70: (define_insn "cmphi"
71: [(set (cc0)
72: (compare (match_operand:HI 0 "nonimmediate_operand" "g")
73: (match_operand:HI 1 "general_operand" "g")))]
74: ""
75: "cmpw %0,%1")
76:
77: (define_insn "cmpqi"
78: [(set (cc0)
79: (compare (match_operand:QI 0 "nonimmediate_operand" "g")
80: (match_operand:QI 1 "general_operand" "g")))]
81: ""
82: "cmpb %0,%1")
83:
84: (define_insn "cmpdf"
85: [(set (cc0)
86: (compare (match_operand:DF 0 "general_operand" "gF")
87: (match_operand:DF 1 "general_operand" "gF")))]
88: ""
89: "cmp%# %0,%1")
90:
91: (define_insn "cmpsf"
92: [(set (cc0)
93: (compare (match_operand:SF 0 "general_operand" "gF")
94: (match_operand:SF 1 "general_operand" "gF")))]
95: ""
96: "cmpf %0,%1")
97:
98: (define_insn ""
99: [(set (cc0)
100: (and:SI (match_operand:SI 0 "general_operand" "g")
101: (match_operand:SI 1 "general_operand" "g")))]
102: ""
103: "bitl %0,%1")
104:
105: (define_insn ""
106: [(set (cc0)
107: (and:HI (match_operand:HI 0 "general_operand" "g")
108: (match_operand:HI 1 "general_operand" "g")))]
109: ""
110: "bitw %0,%1")
111:
112: (define_insn ""
113: [(set (cc0)
114: (and:QI (match_operand:QI 0 "general_operand" "g")
115: (match_operand:QI 1 "general_operand" "g")))]
116: ""
117: "bitb %0,%1")
118:
119: ;; The vax has no sltu or sgeu patterns, but does have two-operand
120: ;; add/subtract with carry. This is still better than the alternative.
121: ;; Since the cc0-using insn cannot be separated from the cc0-setting insn,
122: ;; and the two are created independently, we can't just use a define_expand
123: ;; to try to optimize this. (The "movl" and "clrl" insns alter the cc0
124: ;; flags, but leave the carry flag alone, but that can't easily be expressed.)
125: ;;
126: ;; Several two-operator combinations could be added to make slightly more
127: ;; optimal code, but they'd have to cover all combinations of plus and minus
128: ;; using match_dup. If you want to do this, I'd suggest changing the "sgeu"
129: ;; pattern to something like (minus (const_int 1) (ltu ...)), so fewer
130: ;; patterns need to be recognized.
131: ;; -- Ken Raeburn ([email protected]) 24 August 1991.
132:
133: (define_insn "sltu"
134: [(set (match_operand:SI 0 "general_operand" "=ro")
135: (ltu (cc0) (const_int 0)))]
136: ""
137: "clrl %0\;adwc $0,%0")
138:
139: (define_insn "sgeu"
140: [(set (match_operand:SI 0 "general_operand" "=ro")
141: (geu (cc0) (const_int 0)))]
142: ""
143: "movl $1,%0\;sbwc $0,%0")
144:
145: (define_insn "movdf"
146: [(set (match_operand:DF 0 "general_operand" "=g,g")
147: (match_operand:DF 1 "general_operand" "G,gF"))]
148: ""
149: "@
150: clr%# %0
151: mov%# %1,%0")
152:
153: (define_insn "movsf"
154: [(set (match_operand:SF 0 "general_operand" "=g,g")
155: (match_operand:SF 1 "general_operand" "G,gF"))]
156: ""
157: "@
158: clrf %0
159: movf %1,%0")
160:
161: ;; Some vaxes don't support this instruction.
162: ;;(define_insn "movti"
163: ;; [(set (match_operand:TI 0 "general_operand" "=g")
164: ;; (match_operand:TI 1 "general_operand" "g"))]
165: ;; ""
166: ;; "movh %1,%0")
167:
168: (define_insn "movdi"
169: [(set (match_operand:DI 0 "general_operand" "=g,g")
170: (match_operand:DI 1 "general_operand" "I,g"))]
171: ""
172: "@
173: clrq %0
174: movq %1,%0")
175:
176: (define_insn "movsi"
177: [(set (match_operand:SI 0 "general_operand" "=g")
178: (match_operand:SI 1 "general_operand" "g"))]
179: ""
180: "*
181: {
182: rtx link;
183: if (operands[1] == const1_rtx
184: && (link = find_reg_note (insn, REG_WAS_0, 0))
185: /* Make sure the insn that stored the 0 is still present. */
186: && ! INSN_DELETED_P (XEXP (link, 0))
187: && GET_CODE (XEXP (link, 0)) != NOTE
188: /* Make sure cross jumping didn't happen here. */
189: && no_labels_between_p (XEXP (link, 0), insn))
190: /* Fastest way to change a 0 to a 1. */
191: return \"incl %0\";
192: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
193: {
194: if (push_operand (operands[0], SImode))
195: return \"pushab %a1\";
196: return \"movab %a1,%0\";
197: }
198: /* this is slower than a movl, except when pushing an operand */
199: if (operands[1] == const0_rtx)
200: return \"clrl %0\";
201: if (GET_CODE (operands[1]) == CONST_INT
202: && (unsigned) INTVAL (operands[1]) >= 64)
203: {
204: int i = INTVAL (operands[1]);
205: if ((unsigned)(~i) < 64)
206: {
207: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
208: return \"mcoml %1,%0\";
209: }
210: if ((unsigned)i < 127)
211: {
212: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
213: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
214: return \"addl3 %2,%1,%0\";
215: }
216: /* trading speed for space */
217: if ((unsigned)i < 0x100)
218: return \"movzbl %1,%0\";
219: if (i >= -0x80 && i < 0)
220: return \"cvtbl %1,%0\";
221: if ((unsigned)i < 0x10000)
222: return \"movzwl %1,%0\";
223: if (i >= -0x8000 && i < 0)
224: return \"cvtwl %1,%0\";
225: }
226: if (push_operand (operands[0], SImode))
227: return \"pushl %1\";
228: return \"movl %1,%0\";
229: }")
230:
231: (define_insn "movhi"
232: [(set (match_operand:HI 0 "general_operand" "=g")
233: (match_operand:HI 1 "general_operand" "g"))]
234: ""
235: "*
236: {
237: rtx link;
238: if (operands[1] == const1_rtx
239: && (link = find_reg_note (insn, REG_WAS_0, 0))
240: /* Make sure the insn that stored the 0 is still present. */
241: && ! INSN_DELETED_P (XEXP (link, 0))
242: && GET_CODE (XEXP (link, 0)) != NOTE
243: /* Make sure cross jumping didn't happen here. */
244: && no_labels_between_p (XEXP (link, 0), insn))
245: /* Fastest way to change a 0 to a 1. */
246: return \"incw %0\";
247: if (operands[1] == const0_rtx)
248: return \"clrw %0\";
249: if (GET_CODE (operands[1]) == CONST_INT
250: && (unsigned) INTVAL (operands[1]) >= 64)
251: {
252: int i = INTVAL (operands[1]);
253: if ((unsigned)((~i) & 0xffff) < 64)
254: {
255: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff);
256: return \"mcomw %1,%0\";
257: }
258: if ((unsigned)(i & 0xffff) < 127)
259: {
260: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
261: operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff);
262: return \"addw3 %2,%1,%0\";
263: }
264: /* this is a lot slower, and only saves 1 measly byte! */
265: /* if ((unsigned)i < 0x100)
266: return \"movzbw %1,%0\"; */
267: /* if (i >= -0x80 && i < 0)
268: return \"cvtbw %1,%0\"; */
269: }
270: return \"movw %1,%0\";
271: }")
272:
273: (define_insn "movqi"
274: [(set (match_operand:QI 0 "general_operand" "=g")
275: (match_operand:QI 1 "general_operand" "g"))]
276: ""
277: "*
278: {
279: if (operands[1] == const0_rtx)
280: return \"clrb %0\";
281: if (GET_CODE (operands[1]) == CONST_INT
282: && (unsigned) INTVAL (operands[1]) >= 64)
283: {
284: int i = INTVAL (operands[1]);
285: if ((unsigned)((~i) & 0xff) < 64)
286: {
287: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff);
288: return \"mcomb %1,%0\";
289: }
290: }
291: return \"movb %1,%0\";
292: }")
293:
294: ;; The definition of this insn does not really explain what it does,
295: ;; but it should suffice
296: ;; that anything generated as this insn will be recognized as one
297: ;; and that it won't successfully combine with anything.
298: (define_insn "movstrhi"
299: [(set (match_operand:BLK 0 "general_operand" "=g")
300: (match_operand:BLK 1 "general_operand" "g"))
301: (use (match_operand:HI 2 "general_operand" "g"))
302: (clobber (reg:SI 0))
303: (clobber (reg:SI 1))
304: (clobber (reg:SI 2))
305: (clobber (reg:SI 3))
306: (clobber (reg:SI 4))
307: (clobber (reg:SI 5))]
308: ""
309: "movc3 %2,%1,%0")
310:
311: ;; Extension and truncation insns.
312:
313: (define_insn "truncsiqi2"
314: [(set (match_operand:QI 0 "general_operand" "=g")
315: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
316: ""
317: "cvtlb %1,%0")
318:
319: (define_insn "truncsihi2"
320: [(set (match_operand:HI 0 "general_operand" "=g")
321: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
322: ""
323: "cvtlw %1,%0")
324:
325: (define_insn "trunchiqi2"
326: [(set (match_operand:QI 0 "general_operand" "=g")
327: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
328: ""
329: "cvtwb %1,%0")
330:
331: (define_insn "extendhisi2"
332: [(set (match_operand:SI 0 "general_operand" "=g")
333: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
334: ""
335: "cvtwl %1,%0")
336:
337: (define_insn "extendqihi2"
338: [(set (match_operand:HI 0 "general_operand" "=g")
339: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
340: ""
341: "cvtbw %1,%0")
342:
343: (define_insn "extendqisi2"
344: [(set (match_operand:SI 0 "general_operand" "=g")
345: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
346: ""
347: "cvtbl %1,%0")
348:
349: (define_insn "extendsfdf2"
350: [(set (match_operand:DF 0 "general_operand" "=g")
351: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
352: ""
353: "cvtf%# %1,%0")
354:
355: (define_insn "truncdfsf2"
356: [(set (match_operand:SF 0 "general_operand" "=g")
357: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
358: ""
359: "cvt%#f %1,%0")
360:
361: (define_insn "zero_extendhisi2"
362: [(set (match_operand:SI 0 "general_operand" "=g")
363: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
364: ""
365: "movzwl %1,%0")
366:
367: (define_insn "zero_extendqihi2"
368: [(set (match_operand:HI 0 "general_operand" "=g")
369: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
370: ""
371: "movzbw %1,%0")
372:
373: (define_insn "zero_extendqisi2"
374: [(set (match_operand:SI 0 "general_operand" "=g")
375: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
376: ""
377: "movzbl %1,%0")
378:
379: ;; Fix-to-float conversion insns.
380:
381: (define_insn "floatsisf2"
382: [(set (match_operand:SF 0 "general_operand" "=g")
383: (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
384: ""
385: "cvtlf %1,%0")
386:
387: (define_insn "floatsidf2"
388: [(set (match_operand:DF 0 "general_operand" "=g")
389: (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
390: ""
391: "cvtl%# %1,%0")
392:
393: (define_insn "floathisf2"
394: [(set (match_operand:SF 0 "general_operand" "=g")
395: (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
396: ""
397: "cvtwf %1,%0")
398:
399: (define_insn "floathidf2"
400: [(set (match_operand:DF 0 "general_operand" "=g")
401: (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
402: ""
403: "cvtw%# %1,%0")
404:
405: (define_insn "floatqisf2"
406: [(set (match_operand:SF 0 "general_operand" "=g")
407: (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
408: ""
409: "cvtbf %1,%0")
410:
411: (define_insn "floatqidf2"
412: [(set (match_operand:DF 0 "general_operand" "=g")
413: (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
414: ""
415: "cvtb%# %1,%0")
416:
417: ;; Float-to-fix conversion insns.
418:
419: (define_insn "fix_truncsfqi2"
420: [(set (match_operand:QI 0 "general_operand" "=g")
421: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
422: ""
423: "cvtfb %1,%0")
424:
425: (define_insn "fix_truncsfhi2"
426: [(set (match_operand:HI 0 "general_operand" "=g")
427: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
428: ""
429: "cvtfw %1,%0")
430:
431: (define_insn "fix_truncsfsi2"
432: [(set (match_operand:SI 0 "general_operand" "=g")
433: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
434: ""
435: "cvtfl %1,%0")
436:
437: (define_insn "fix_truncdfqi2"
438: [(set (match_operand:QI 0 "general_operand" "=g")
439: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
440: ""
441: "cvt%#b %1,%0")
442:
443: (define_insn "fix_truncdfhi2"
444: [(set (match_operand:HI 0 "general_operand" "=g")
445: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
446: ""
447: "cvt%#w %1,%0")
448:
449: (define_insn "fix_truncdfsi2"
450: [(set (match_operand:SI 0 "general_operand" "=g")
451: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
452: ""
453: "cvt%#l %1,%0")
454:
455: ;;- All kinds of add instructions.
456:
457: (define_insn "adddf3"
458: [(set (match_operand:DF 0 "general_operand" "=g,g,g")
459: (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
460: (match_operand:DF 2 "general_operand" "gF,0,gF")))]
461: ""
462: "@
463: add%#2 %2,%0
464: add%#2 %1,%0
465: add%#3 %1,%2,%0")
466:
467: (define_insn "addsf3"
468: [(set (match_operand:SF 0 "general_operand" "=g,g,g")
469: (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
470: (match_operand:SF 2 "general_operand" "gF,0,gF")))]
471: ""
472: "@
473: addf2 %2,%0
474: addf2 %1,%0
475: addf3 %1,%2,%0")
476:
477: (define_insn "addsi3"
478: [(set (match_operand:SI 0 "general_operand" "=g")
479: (plus:SI (match_operand:SI 1 "general_operand" "g")
480: (match_operand:SI 2 "general_operand" "g")))]
481: ""
482: "*
483: {
484: if (rtx_equal_p (operands[0], operands[1]))
485: {
486: if (operands[2] == const1_rtx)
487: return \"incl %0\";
488: if (operands[2] == constm1_rtx)
489: return \"decl %0\";
490: if (GET_CODE (operands[2]) == CONST_INT
491: && (unsigned) (- INTVAL (operands[2])) < 64)
492: return \"subl2 $%n2,%0\";
493: if (GET_CODE (operands[2]) == CONST_INT
494: && (unsigned) INTVAL (operands[2]) >= 64
495: && GET_CODE (operands[1]) == REG)
496: return \"movab %c2(%1),%0\";
497: return \"addl2 %2,%0\";
498: }
499: if (rtx_equal_p (operands[0], operands[2]))
500: return \"addl2 %1,%0\";
501: if (GET_CODE (operands[2]) == CONST_INT
502: && (unsigned) (- INTVAL (operands[2])) < 64)
503: return \"subl3 $%n2,%1,%0\";
504: if (GET_CODE (operands[2]) == CONST_INT
505: && (unsigned) INTVAL (operands[2]) >= 64
506: && GET_CODE (operands[1]) == REG)
507: {
508: if (push_operand (operands[0], SImode))
509: return \"pushab %c2(%1)\";
510: return \"movab %c2(%1),%0\";
511: }
512: return \"addl3 %1,%2,%0\";
513: }")
514:
515: (define_insn "addhi3"
516: [(set (match_operand:HI 0 "general_operand" "=g")
517: (plus:HI (match_operand:HI 1 "general_operand" "g")
518: (match_operand:HI 2 "general_operand" "g")))]
519: ""
520: "*
521: {
522: if (rtx_equal_p (operands[0], operands[1]))
523: {
524: if (operands[2] == const1_rtx)
525: return \"incw %0\";
526: if (operands[2] == constm1_rtx)
527: return \"decw %0\";
528: if (GET_CODE (operands[2]) == CONST_INT
529: && (unsigned) (- INTVAL (operands[2])) < 64)
530: return \"subw2 $%n2,%0\";
531: return \"addw2 %2,%0\";
532: }
533: if (rtx_equal_p (operands[0], operands[2]))
534: return \"addw2 %1,%0\";
535: if (GET_CODE (operands[2]) == CONST_INT
536: && (unsigned) (- INTVAL (operands[2])) < 64)
537: return \"subw3 $%n2,%1,%0\";
538: return \"addw3 %1,%2,%0\";
539: }")
540:
541: (define_insn "addqi3"
542: [(set (match_operand:QI 0 "general_operand" "=g")
543: (plus:QI (match_operand:QI 1 "general_operand" "g")
544: (match_operand:QI 2 "general_operand" "g")))]
545: ""
546: "*
547: {
548: if (rtx_equal_p (operands[0], operands[1]))
549: {
550: if (operands[2] == const1_rtx)
551: return \"incb %0\";
552: if (operands[2] == constm1_rtx)
553: return \"decb %0\";
554: if (GET_CODE (operands[2]) == CONST_INT
555: && (unsigned) (- INTVAL (operands[2])) < 64)
556: return \"subb2 $%n2,%0\";
557: return \"addb2 %2,%0\";
558: }
559: if (rtx_equal_p (operands[0], operands[2]))
560: return \"addb2 %1,%0\";
561: if (GET_CODE (operands[2]) == CONST_INT
562: && (unsigned) (- INTVAL (operands[2])) < 64)
563: return \"subb3 $%n2,%1,%0\";
564: return \"addb3 %1,%2,%0\";
565: }")
566:
567: ;; The add-with-carry (adwc) instruction only accepts two operands.
568: (define_insn "adddi3"
569: [(set (match_operand:DI 0 "general_operand" "=ro>,ro>")
570: (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
571: (match_operand:DI 2 "general_operand" "Fro,F")))]
572: ""
573: "*
574: {
575: rtx low[3];
576: char *pattern;
577: int carry = 1;
578:
579: split_quadword_operands (operands, low, 3);
580: /* Add low parts. */
581: if (rtx_equal_p (operands[0], operands[1]))
582: {
583: if (low[2] == const0_rtx)
584: /* Should examine operand, punt if not POST_INC. */
585: pattern = \"tstl %0\", carry = 0;
586: else if (low[2] == const1_rtx)
587: pattern = \"incl %0\";
588: else
589: pattern = \"addl2 %2,%0\";
590: }
591: else
592: {
593: if (low[2] == const0_rtx)
594: pattern = \"movl %1,%0\", carry = 0;
595: else
596: pattern = \"addl3 %2,%1,%0\";
597: }
598: if (pattern)
599: output_asm_insn (pattern, low);
600: if (!carry)
601: /* If CARRY is 0, we don't have any carry value to worry about. */
602: return OUT_FCN (CODE_FOR_addsi3) (operands, insn);
603: /* %0 = C + %1 + %2 */
604: if (!rtx_equal_p (operands[0], operands[1]))
605: output_asm_insn ((operands[1] == const0_rtx
606: ? \"clrl %0\"
607: : \"movl %1,%0\"), operands);
608: return \"adwc %2,%0\";
609: }")
610:
611: ;;- All kinds of subtract instructions.
612:
613: (define_insn "subdf3"
614: [(set (match_operand:DF 0 "general_operand" "=g,g")
615: (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
616: (match_operand:DF 2 "general_operand" "gF,gF")))]
617: ""
618: "@
619: sub%#2 %2,%0
620: sub%#3 %2,%1,%0")
621:
622: (define_insn "subsf3"
623: [(set (match_operand:SF 0 "general_operand" "=g,g")
624: (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
625: (match_operand:SF 2 "general_operand" "gF,gF")))]
626: ""
627: "@
628: subf2 %2,%0
629: subf3 %2,%1,%0")
630:
631: (define_insn "subsi3"
632: [(set (match_operand:SI 0 "general_operand" "=g,g")
633: (minus:SI (match_operand:SI 1 "general_operand" "0,g")
634: (match_operand:SI 2 "general_operand" "g,g")))]
635: ""
636: "@
637: subl2 %2,%0
638: subl3 %2,%1,%0")
639:
640: (define_insn "subhi3"
641: [(set (match_operand:HI 0 "general_operand" "=g,g")
642: (minus:HI (match_operand:HI 1 "general_operand" "0,g")
643: (match_operand:HI 2 "general_operand" "g,g")))]
644: ""
645: "@
646: subw2 %2,%0
647: subw3 %2,%1,%0")
648:
649: (define_insn "subqi3"
650: [(set (match_operand:QI 0 "general_operand" "=g,g")
651: (minus:QI (match_operand:QI 1 "general_operand" "0,g")
652: (match_operand:QI 2 "general_operand" "g,g")))]
653: ""
654: "@
655: subb2 %2,%0
656: subb3 %2,%1,%0")
657:
658: ;; The subtract-with-carry (sbwc) instruction only takes two operands.
659: (define_insn "subdi3"
660: [(set (match_operand:DI 0 "general_operand" "=or>,or>")
661: (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
662: (match_operand:DI 2 "general_operand" "For,F")))]
663: ""
664: "*
665: {
666: rtx low[3];
667: char *pattern;
668: int carry = 1;
669:
670: split_quadword_operands (operands, low, 3);
671: /* Subtract low parts. */
672: if (rtx_equal_p (operands[0], operands[1]))
673: {
674: if (low[2] == const0_rtx)
675: pattern = 0, carry = 0;
676: else if (low[2] == constm1_rtx)
677: pattern = \"decl %0\";
678: else
679: pattern = \"subl2 %2,%0\";
680: }
681: else
682: {
683: if (low[2] == constm1_rtx)
684: pattern = \"decl %0\";
685: else if (low[2] == const0_rtx)
686: pattern = OUT_FCN (CODE_FOR_movsi) (low, insn), carry = 0;
687: else
688: pattern = \"subl3 %2,%1,%0\";
689: }
690: if (pattern)
691: output_asm_insn (pattern, low);
692: if (carry)
693: {
694: if (!rtx_equal_p (operands[0], operands[1]))
695: return \"movl %1,%0\;sbwc %2,%0\";
696: return \"sbwc %2,%0\";
697: /* %0 = %2 - %1 - C */
698: }
699: return OUT_FCN (CODE_FOR_subsi3) (operands, insn);
700: }")
701:
702: ;;- Multiply instructions.
703:
704: (define_insn "muldf3"
705: [(set (match_operand:DF 0 "general_operand" "=g,g,g")
706: (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
707: (match_operand:DF 2 "general_operand" "gF,0,gF")))]
708: ""
709: "@
710: mul%#2 %2,%0
711: mul%#2 %1,%0
712: mul%#3 %1,%2,%0")
713:
714: (define_insn "mulsf3"
715: [(set (match_operand:SF 0 "general_operand" "=g,g,g")
716: (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
717: (match_operand:SF 2 "general_operand" "gF,0,gF")))]
718: ""
719: "@
720: mulf2 %2,%0
721: mulf2 %1,%0
722: mulf3 %1,%2,%0")
723:
724: (define_insn "mulsi3"
725: [(set (match_operand:SI 0 "general_operand" "=g,g,g")
726: (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
727: (match_operand:SI 2 "general_operand" "g,0,g")))]
728: ""
729: "@
730: mull2 %2,%0
731: mull2 %1,%0
732: mull3 %1,%2,%0")
733:
734: (define_insn "mulhi3"
735: [(set (match_operand:HI 0 "general_operand" "=g,g,")
736: (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
737: (match_operand:HI 2 "general_operand" "g,0,g")))]
738: ""
739: "@
740: mulw2 %2,%0
741: mulw2 %1,%0
742: mulw3 %1,%2,%0")
743:
744: (define_insn "mulqi3"
745: [(set (match_operand:QI 0 "general_operand" "=g,g,g")
746: (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
747: (match_operand:QI 2 "general_operand" "g,0,g")))]
748: ""
749: "@
750: mulb2 %2,%0
751: mulb2 %1,%0
752: mulb3 %1,%2,%0")
753:
754: (define_insn "mulsidi3"
755: [(set (match_operand:DI 0 "general_operand" "=g")
756: (mult:DI (sign_extend:DI
757: (match_operand:SI 1 "nonimmediate_operand" "g"))
758: (sign_extend:DI
759: (match_operand:SI 2 "nonimmediate_operand" "g"))))]
760: ""
761: "emul %1,%2,$0,%0")
762:
763: (define_insn ""
764: [(set (match_operand:DI 0 "general_operand" "=g")
765: (plus:DI
766: (mult:DI (sign_extend:DI
767: (match_operand:SI 1 "nonimmediate_operand" "g"))
768: (sign_extend:DI
769: (match_operand:SI 2 "nonimmediate_operand" "g")))
770: (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
771: ""
772: "emul %1,%2,%3,%0")
773:
774: ;; 'F' constraint means type CONST_DOUBLE
775: (define_insn ""
776: [(set (match_operand:DI 0 "general_operand" "=g")
777: (plus:DI
778: (mult:DI (sign_extend:DI
779: (match_operand:SI 1 "nonimmediate_operand" "g"))
780: (sign_extend:DI
781: (match_operand:SI 2 "nonimmediate_operand" "g")))
782: (match_operand:DI 3 "immediate_operand" "F")))]
783: "GET_CODE (operands[3]) == CONST_DOUBLE
784: && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
785: "*
786: {
787: if (CONST_DOUBLE_HIGH (operands[3]))
788: operands[3] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[3]));
789: return \"emul %1,%2,%3,%0\";
790: }")
791:
792: ;;- Divide instructions.
793:
794: (define_insn "divdf3"
795: [(set (match_operand:DF 0 "general_operand" "=g,g")
796: (div:DF (match_operand:DF 1 "general_operand" "0,gF")
797: (match_operand:DF 2 "general_operand" "gF,gF")))]
798: ""
799: "@
800: div%#2 %2,%0
801: div%#3 %2,%1,%0")
802:
803: (define_insn "divsf3"
804: [(set (match_operand:SF 0 "general_operand" "=g,g")
805: (div:SF (match_operand:SF 1 "general_operand" "0,gF")
806: (match_operand:SF 2 "general_operand" "gF,gF")))]
807: ""
808: "@
809: divf2 %2,%0
810: divf3 %2,%1,%0")
811:
812: (define_insn "divsi3"
813: [(set (match_operand:SI 0 "general_operand" "=g,g")
814: (div:SI (match_operand:SI 1 "general_operand" "0,g")
815: (match_operand:SI 2 "general_operand" "g,g")))]
816: ""
817: "@
818: divl2 %2,%0
819: divl3 %2,%1,%0")
820:
821: (define_insn "divhi3"
822: [(set (match_operand:HI 0 "general_operand" "=g,g")
823: (div:HI (match_operand:HI 1 "general_operand" "0,g")
824: (match_operand:HI 2 "general_operand" "g,g")))]
825: ""
826: "@
827: divw2 %2,%0
828: divw3 %2,%1,%0")
829:
830: (define_insn "divqi3"
831: [(set (match_operand:QI 0 "general_operand" "=g,g")
832: (div:QI (match_operand:QI 1 "general_operand" "0,g")
833: (match_operand:QI 2 "general_operand" "g,g")))]
834: ""
835: "@
836: divb2 %2,%0
837: divb3 %2,%1,%0")
838:
839: ;This is left out because it is very slow;
840: ;we are better off programming around the "lack" of this insn.
841: ;(define_insn "divmoddisi4"
842: ; [(set (match_operand:SI 0 "general_operand" "=g")
843: ; (div:SI (match_operand:DI 1 "general_operand" "g")
844: ; (match_operand:SI 2 "general_operand" "g")))
845: ; (set (match_operand:SI 3 "general_operand" "=g")
846: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
847: ; (match_operand:SI 2 "general_operand" "g")))]
848: ; ""
849: ; "ediv %2,%1,%0,%3")
850:
851: ;; Bit-and on the vax is done with a clear-bits insn.
852: (define_expand "andsi3"
853: [(set (match_operand:SI 0 "general_operand" "=g")
854: (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
855: (match_operand:SI 2 "general_operand" "g")))]
856: ""
857: "
858: {
859: if (GET_CODE (operands[1]) == CONST_INT)
860: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[1]));
861: else
862: operands[1] = expand_unop (SImode, one_cmpl_optab, operands[1], 0, 1);
863: }")
864:
865: (define_expand "andhi3"
866: [(set (match_operand:HI 0 "general_operand" "=g")
867: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
868: (match_operand:HI 2 "general_operand" "g")))]
869: ""
870: "
871: {
872: rtx op = operands[1];
873: if (GET_CODE (op) == CONST_INT)
874: operands[1] = gen_rtx (CONST_INT, VOIDmode,
875: ((1 << 16) - 1) & ~INTVAL (op));
876: else
877: operands[1] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
878: }")
879:
880: (define_expand "andqi3"
881: [(set (match_operand:QI 0 "general_operand" "=g")
882: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
883: (match_operand:QI 2 "general_operand" "g")))]
884: ""
885: "
886: {
887: rtx op = operands[1];
888: if (GET_CODE (op) == CONST_INT)
889: operands[1] = gen_rtx (CONST_INT, VOIDmode,
890: ((1 << 8) - 1) & ~INTVAL (op));
891: else
892: operands[1] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
893: }")
894:
895: (define_insn ""
896: [(set (match_operand:SI 0 "general_operand" "=g,g")
897: (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
898: (match_operand:SI 2 "general_operand" "0,g")))]
899: ""
900: "@
901: bicl2 %1,%0
902: bicl3 %1,%2,%0")
903:
904: (define_insn ""
905: [(set (match_operand:HI 0 "general_operand" "=g,g")
906: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
907: (match_operand:HI 2 "general_operand" "0,g")))]
908: ""
909: "@
910: bicw2 %1,%0
911: bicw3 %1,%2,%0")
912:
913: (define_insn ""
914: [(set (match_operand:QI 0 "general_operand" "=g,g")
915: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
916: (match_operand:QI 2 "general_operand" "0,g")))]
917: ""
918: "@
919: bicb2 %1,%0
920: bicb3 %1,%2,%0")
921:
922: ;; The following used to be needed because constant propagation can
923: ;; create them starting from the bic insn patterns above. This is no
924: ;; longer a problem. However, having these patterns allows optimization
925: ;; opportunities in combine.c.
926:
927: (define_insn ""
928: [(set (match_operand:SI 0 "general_operand" "=g,g")
929: (and:SI (match_operand:SI 1 "general_operand" "0,g")
930: (match_operand:SI 2 "const_int_operand" "n,n")))]
931: ""
932: "@
933: bicl2 %N2,%0
934: bicl3 %N2,%1,%0")
935:
936: (define_insn ""
937: [(set (match_operand:HI 0 "general_operand" "=g,g")
938: (and:HI (match_operand:HI 1 "general_operand" "0,g")
939: (match_operand:HI 2 "const_int_operand" "n,n")))]
940: ""
941: "@
942: bicw2 %H2,%0
943: bicw3 %H2,%1,%0")
944:
945: (define_insn ""
946: [(set (match_operand:QI 0 "general_operand" "=g,g")
947: (and:QI (match_operand:QI 1 "general_operand" "0,g")
948: (match_operand:QI 2 "const_int_operand" "n,n")))]
949: ""
950: "@
951: bicb2 %B2,%0
952: bicb3 %B2,%1,%0")
953:
954: ;;- Bit set instructions.
955:
956: (define_insn "iorsi3"
957: [(set (match_operand:SI 0 "general_operand" "=g,g,g")
958: (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
959: (match_operand:SI 2 "general_operand" "g,0,g")))]
960: ""
961: "@
962: bisl2 %2,%0
963: bisl2 %1,%0
964: bisl3 %2,%1,%0")
965:
966: (define_insn "iorhi3"
967: [(set (match_operand:HI 0 "general_operand" "=g,g,g")
968: (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
969: (match_operand:HI 2 "general_operand" "g,0,g")))]
970: ""
971: "@
972: bisw2 %2,%0
973: bisw2 %1,%0
974: bisw3 %2,%1,%0")
975:
976: (define_insn "iorqi3"
977: [(set (match_operand:QI 0 "general_operand" "=g,g,g")
978: (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
979: (match_operand:QI 2 "general_operand" "g,0,g")))]
980: ""
981: "@
982: bisb2 %2,%0
983: bisb2 %1,%0
984: bisb3 %2,%1,%0")
985:
986: ;;- xor instructions.
987:
988: (define_insn "xorsi3"
989: [(set (match_operand:SI 0 "general_operand" "=g,g,g")
990: (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
991: (match_operand:SI 2 "general_operand" "g,0,g")))]
992: ""
993: "@
994: xorl2 %2,%0
995: xorl2 %1,%0
996: xorl3 %2,%1,%0")
997:
998: (define_insn "xorhi3"
999: [(set (match_operand:HI 0 "general_operand" "=g,g,g")
1000: (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1001: (match_operand:HI 2 "general_operand" "g,0,g")))]
1002: ""
1003: "@
1004: xorw2 %2,%0
1005: xorw2 %1,%0
1006: xorw3 %2,%1,%0")
1007:
1008: (define_insn "xorqi3"
1009: [(set (match_operand:QI 0 "general_operand" "=g,g,g")
1010: (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1011: (match_operand:QI 2 "general_operand" "g,0,g")))]
1012: ""
1013: "@
1014: xorb2 %2,%0
1015: xorb2 %1,%0
1016: xorb3 %2,%1,%0")
1017:
1018: (define_insn "negdf2"
1019: [(set (match_operand:DF 0 "general_operand" "=g")
1020: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1021: ""
1022: "mneg%# %1,%0")
1023:
1024: (define_insn "negsf2"
1025: [(set (match_operand:SF 0 "general_operand" "=g")
1026: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1027: ""
1028: "mnegf %1,%0")
1029:
1030: (define_insn "negsi2"
1031: [(set (match_operand:SI 0 "general_operand" "=g")
1032: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1033: ""
1034: "mnegl %1,%0")
1035:
1036: (define_insn "neghi2"
1037: [(set (match_operand:HI 0 "general_operand" "=g")
1038: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1039: ""
1040: "mnegw %1,%0")
1041:
1042: (define_insn "negqi2"
1043: [(set (match_operand:QI 0 "general_operand" "=g")
1044: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1045: ""
1046: "mnegb %1,%0")
1047:
1048: (define_insn "one_cmplsi2"
1049: [(set (match_operand:SI 0 "general_operand" "=g")
1050: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1051: ""
1052: "mcoml %1,%0")
1053:
1054: (define_insn "one_cmplhi2"
1055: [(set (match_operand:HI 0 "general_operand" "=g")
1056: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1057: ""
1058: "mcomw %1,%0")
1059:
1060: (define_insn "one_cmplqi2"
1061: [(set (match_operand:QI 0 "general_operand" "=g")
1062: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1063: ""
1064: "mcomb %1,%0")
1065:
1066: ;; Arithmetic right shift on the vax works by negating the shift count,
1067: ;; then emitting a right shift with the shift count negated. This means
1068: ;; that all actual shift counts in the RTL will be positive. This
1069: ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1070: ;; which isn't valid.
1071: (define_expand "ashrsi3"
1072: [(set (match_operand:SI 0 "general_operand" "=g")
1073: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1074: (match_operand:QI 2 "general_operand" "g")))]
1075: ""
1076: "
1077: {
1078: if (GET_CODE (operands[2]) != CONST_INT)
1079: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1080: }")
1081:
1082: (define_insn ""
1083: [(set (match_operand:SI 0 "general_operand" "=g")
1084: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1085: (match_operand:QI 2 "const_int_operand" "n")))]
1086: ""
1087: "ashl $%n2,%1,%0")
1088:
1089: (define_insn ""
1090: [(set (match_operand:SI 0 "general_operand" "=g")
1091: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1092: (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1093: ""
1094: "ashl %2,%1,%0")
1095:
1096: (define_insn "ashlsi3"
1097: [(set (match_operand:SI 0 "general_operand" "=g")
1098: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1099: (match_operand:QI 2 "general_operand" "g")))]
1100: ""
1101: "*
1102: {
1103: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1104: return \"addl2 %0,%0\";
1105: if (GET_CODE (operands[1]) == REG
1106: && GET_CODE (operands[2]) == CONST_INT)
1107: {
1108: int i = INTVAL (operands[2]);
1109: if (i == 1)
1110: return \"addl3 %1,%1,%0\";
1111: if (i == 2)
1112: return \"moval 0[%1],%0\";
1113: if (i == 3)
1114: return \"movad 0[%1],%0\";
1115: }
1116: return \"ashl %2,%1,%0\";
1117: }")
1118:
1119: ;; Arithmetic right shift on the vax works by negating the shift count.
1120: (define_expand "ashrdi3"
1121: [(set (match_operand:DI 0 "general_operand" "=g")
1122: (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1123: (match_operand:QI 2 "general_operand" "g")))]
1124: ""
1125: "
1126: {
1127: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1128: }")
1129:
1130: (define_insn "ashldi3"
1131: [(set (match_operand:DI 0 "general_operand" "=g")
1132: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1133: (match_operand:QI 2 "general_operand" "g")))]
1134: ""
1135: "ashq %2,%1,%0")
1136:
1137: (define_insn ""
1138: [(set (match_operand:DI 0 "general_operand" "=g")
1139: (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1140: (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1141: ""
1142: "ashq %2,%1,%0")
1143:
1144: ;; Rotate right on the vax works by negating the shift count.
1145: (define_expand "rotrsi3"
1146: [(set (match_operand:SI 0 "general_operand" "=g")
1147: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1148: (match_operand:QI 2 "general_operand" "g")))]
1149: ""
1150: "
1151: {
1152: if (GET_CODE (operands[2]) != CONST_INT)
1153: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1154: }")
1155:
1156: (define_insn "rotlsi3"
1157: [(set (match_operand:SI 0 "general_operand" "=g")
1158: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1159: (match_operand:QI 2 "general_operand" "g")))]
1160: ""
1161: "rotl %2,%1,%0")
1162:
1163: (define_insn ""
1164: [(set (match_operand:SI 0 "general_operand" "=g")
1165: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1166: (match_operand:QI 2 "const_int_operand" "n")))]
1167: ""
1168: "rotl $%R2,%1,%0")
1169:
1170: (define_insn ""
1171: [(set (match_operand:SI 0 "general_operand" "=g")
1172: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1173: (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1174: ""
1175: "rotl %2,%1,%0")
1176:
1177: ;This insn is probably slower than a multiply and an add.
1178: ;(define_insn ""
1179: ; [(set (match_operand:SI 0 "general_operand" "=g")
1180: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1181: ; (match_operand:SI 2 "general_operand" "g"))
1182: ; (match_operand:SI 3 "general_operand" "g")))]
1183: ; ""
1184: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1185:
1186: ;; Special cases of bit-field insns which we should
1187: ;; recognize in preference to the general case.
1188: ;; These handle aligned 8-bit and 16-bit fields,
1189: ;; which can usually be done with move instructions.
1190:
1191: (define_insn ""
1192: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1193: (match_operand:QI 1 "const_int_operand" "n")
1194: (match_operand:SI 2 "const_int_operand" "n"))
1195: (match_operand:SI 3 "general_operand" "g"))]
1196: "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1197: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1198: && (GET_CODE (operands[0]) == REG
1199: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1200: "*
1201: {
1202: if (REG_P (operands[0]))
1203: {
1204: if (INTVAL (operands[2]) != 0)
1205: return \"insv %3,%2,%1,%0\";
1206: }
1207: else
1208: operands[0]
1209: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1210:
1211: if (INTVAL (operands[1]) == 8)
1212: return \"movb %3,%0\";
1213: return \"movw %3,%0\";
1214: }")
1215:
1216: (define_insn ""
1217: [(set (match_operand:SI 0 "general_operand" "=&g")
1218: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1219: (match_operand:QI 2 "const_int_operand" "n")
1220: (match_operand:SI 3 "const_int_operand" "n")))]
1221: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1222: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1223: && (GET_CODE (operands[1]) == REG
1224: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1225: "*
1226: {
1227: if (REG_P (operands[1]))
1228: {
1229: if (INTVAL (operands[3]) != 0)
1230: return \"extzv %3,%2,%1,%0\";
1231: }
1232: else
1233: operands[1]
1234: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1235:
1236: if (INTVAL (operands[2]) == 8)
1237: return \"movzbl %1,%0\";
1238: return \"movzwl %1,%0\";
1239: }")
1240:
1241: (define_insn ""
1242: [(set (match_operand:SI 0 "general_operand" "=g")
1243: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1244: (match_operand:QI 2 "const_int_operand" "n")
1245: (match_operand:SI 3 "const_int_operand" "n")))]
1246: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1247: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1248: && (GET_CODE (operands[1]) == REG
1249: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1250: "*
1251: {
1252: if (REG_P (operands[1]))
1253: {
1254: if (INTVAL (operands[3]) != 0)
1255: return \"extv %3,%2,%1,%0\";
1256: }
1257: else
1258: operands[1]
1259: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1260:
1261: if (INTVAL (operands[2]) == 8)
1262: return \"cvtbl %1,%0\";
1263: return \"cvtwl %1,%0\";
1264: }")
1265:
1266: ;; Register-only SImode cases of bit-field insns.
1267:
1268: (define_insn ""
1269: [(set (cc0)
1270: (compare
1271: (sign_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
1272: (match_operand:QI 1 "general_operand" "g")
1273: (match_operand:SI 2 "general_operand" "g"))
1274: (match_operand:SI 3 "general_operand" "g")))]
1275: ""
1276: "cmpv %2,%1,%0,%3")
1277:
1278: (define_insn ""
1279: [(set (cc0)
1280: (compare
1281: (zero_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
1282: (match_operand:QI 1 "general_operand" "g")
1283: (match_operand:SI 2 "general_operand" "g"))
1284: (match_operand:SI 3 "general_operand" "g")))]
1285: ""
1286: "cmpzv %2,%1,%0,%3")
1287:
1288: (define_insn ""
1289: [(set (match_operand:SI 0 "general_operand" "=g")
1290: (sign_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
1291: (match_operand:QI 2 "general_operand" "g")
1292: (match_operand:SI 3 "general_operand" "g")))]
1293: ""
1294: "extv %3,%2,%1,%0")
1295:
1296: (define_insn ""
1297: [(set (match_operand:SI 0 "general_operand" "=g")
1298: (zero_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
1299: (match_operand:QI 2 "general_operand" "g")
1300: (match_operand:SI 3 "general_operand" "g")))]
1301: ""
1302: "extzv %3,%2,%1,%0")
1303:
1304: ;; Non-register cases.
1305: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1306: ;; don't match these (and therefore match the cases above instead).
1307:
1308: (define_insn ""
1309: [(set (cc0)
1310: (compare
1311: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1312: (match_operand:QI 1 "general_operand" "g")
1313: (match_operand:SI 2 "general_operand" "g"))
1314: (match_operand:SI 3 "general_operand" "g")))]
1315: ""
1316: "cmpv %2,%1,%0,%3")
1317:
1318: (define_insn ""
1319: [(set (cc0)
1320: (compare
1321: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1322: (match_operand:QI 1 "general_operand" "g")
1323: (match_operand:SI 2 "general_operand" "g"))
1324: (match_operand:SI 3 "general_operand" "g")))]
1325: ""
1326: "cmpzv %2,%1,%0,%3")
1327:
1328: (define_insn "extv"
1329: [(set (match_operand:SI 0 "general_operand" "=g")
1330: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1331: (match_operand:QI 2 "general_operand" "g")
1332: (match_operand:SI 3 "general_operand" "g")))]
1333: ""
1334: "extv %3,%2,%1,%0")
1335:
1336: (define_insn "extzv"
1337: [(set (match_operand:SI 0 "general_operand" "=g")
1338: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1339: (match_operand:QI 2 "general_operand" "g")
1340: (match_operand:SI 3 "general_operand" "g")))]
1341: ""
1342: "extzv %3,%2,%1,%0")
1343:
1344: (define_insn "insv"
1345: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1346: (match_operand:QI 1 "general_operand" "g")
1347: (match_operand:SI 2 "general_operand" "g"))
1348: (match_operand:SI 3 "general_operand" "g"))]
1349: ""
1350: "insv %3,%2,%1,%0")
1351:
1352: (define_insn ""
1353: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1354: (match_operand:QI 1 "general_operand" "g")
1355: (match_operand:SI 2 "general_operand" "g"))
1356: (match_operand:SI 3 "general_operand" "g"))]
1357: ""
1358: "insv %3,%2,%1,%0")
1359:
1360: (define_insn "jump"
1361: [(set (pc)
1362: (label_ref (match_operand 0 "" "")))]
1363: ""
1364: "jbr %l0")
1365:
1366: (define_insn "beq"
1367: [(set (pc)
1368: (if_then_else (eq (cc0)
1369: (const_int 0))
1370: (label_ref (match_operand 0 "" ""))
1371: (pc)))]
1372: ""
1373: "jeql %l0")
1374:
1375: (define_insn "bne"
1376: [(set (pc)
1377: (if_then_else (ne (cc0)
1378: (const_int 0))
1379: (label_ref (match_operand 0 "" ""))
1380: (pc)))]
1381: ""
1382: "jneq %l0")
1383:
1384: (define_insn "bgt"
1385: [(set (pc)
1386: (if_then_else (gt (cc0)
1387: (const_int 0))
1388: (label_ref (match_operand 0 "" ""))
1389: (pc)))]
1390: ""
1391: "jgtr %l0")
1392:
1393: (define_insn "bgtu"
1394: [(set (pc)
1395: (if_then_else (gtu (cc0)
1396: (const_int 0))
1397: (label_ref (match_operand 0 "" ""))
1398: (pc)))]
1399: ""
1400: "jgtru %l0")
1401:
1402: (define_insn "blt"
1403: [(set (pc)
1404: (if_then_else (lt (cc0)
1405: (const_int 0))
1406: (label_ref (match_operand 0 "" ""))
1407: (pc)))]
1408: ""
1409: "jlss %l0")
1410:
1411: (define_insn "bltu"
1412: [(set (pc)
1413: (if_then_else (ltu (cc0)
1414: (const_int 0))
1415: (label_ref (match_operand 0 "" ""))
1416: (pc)))]
1417: ""
1418: "jlssu %l0")
1419:
1420: (define_insn "bge"
1421: [(set (pc)
1422: (if_then_else (ge (cc0)
1423: (const_int 0))
1424: (label_ref (match_operand 0 "" ""))
1425: (pc)))]
1426: ""
1427: "jgeq %l0")
1428:
1429: (define_insn "bgeu"
1430: [(set (pc)
1431: (if_then_else (geu (cc0)
1432: (const_int 0))
1433: (label_ref (match_operand 0 "" ""))
1434: (pc)))]
1435: ""
1436: "jgequ %l0")
1437:
1438: (define_insn "ble"
1439: [(set (pc)
1440: (if_then_else (le (cc0)
1441: (const_int 0))
1442: (label_ref (match_operand 0 "" ""))
1443: (pc)))]
1444: ""
1445: "jleq %l0")
1446:
1447: (define_insn "bleu"
1448: [(set (pc)
1449: (if_then_else (leu (cc0)
1450: (const_int 0))
1451: (label_ref (match_operand 0 "" ""))
1452: (pc)))]
1453: ""
1454: "jlequ %l0")
1455:
1456: ;; Recognize reversed jumps.
1457: (define_insn ""
1458: [(set (pc)
1459: (if_then_else (match_operator 0 "comparison_operator"
1460: [(cc0)
1461: (const_int 0)])
1462: (pc)
1463: (label_ref (match_operand 1 "" ""))))]
1464: ""
1465: "j%C0 %l1") ; %C0 negates condition
1466:
1467: ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1.1.1.2 ! root 1468: ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
! 1469: ;; memory, we use QImode in the insn. So we can't use those instructions
! 1470: ;; for mode-dependent addresses.
1.1 root 1471:
1472: (define_insn ""
1473: [(set (pc)
1474: (if_then_else
1.1.1.2 ! root 1475: (ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
1.1 root 1476: (const_int 1)
1477: (match_operand:SI 1 "general_operand" "I,g"))
1478: (const_int 0))
1479: (label_ref (match_operand 2 "" ""))
1480: (pc)))]
1481: ""
1482: "@
1483: jlbs %0,%l2
1484: jbs %1,%0,%l2")
1485:
1486: (define_insn ""
1487: [(set (pc)
1488: (if_then_else
1.1.1.2 ! root 1489: (eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
1.1 root 1490: (const_int 1)
1491: (match_operand:SI 1 "general_operand" "I,g"))
1492: (const_int 0))
1493: (label_ref (match_operand 2 "" ""))
1494: (pc)))]
1495: ""
1496: "@
1497: jlbc %0,%l2
1498: jbc %1,%0,%l2")
1499:
1500: (define_insn ""
1501: [(set (pc)
1502: (if_then_else
1503: (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1504: (const_int 1)
1505: (match_operand:SI 1 "general_operand" "I,g"))
1506: (const_int 0))
1507: (label_ref (match_operand 2 "" ""))
1508: (pc)))]
1509: ""
1510: "@
1511: jlbs %0,%l2
1512: jbs %1,%0,%l2")
1513:
1514: (define_insn ""
1515: [(set (pc)
1516: (if_then_else
1517: (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1518: (const_int 1)
1519: (match_operand:SI 1 "general_operand" "I,g"))
1520: (const_int 0))
1521: (label_ref (match_operand 2 "" ""))
1522: (pc)))]
1523: ""
1524: "@
1525: jlbc %0,%l2
1526: jbc %1,%0,%l2")
1527:
1528: ;; Subtract-and-jump and Add-and-jump insns.
1529: ;; These are not used when output is for the Unix assembler
1530: ;; because it does not know how to modify them to reach far.
1531:
1532: ;; Normal sob insns.
1533:
1534: (define_insn ""
1535: [(set (pc)
1536: (if_then_else
1.1.1.2 ! root 1537: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1538: (const_int -1))
! 1539: (const_int 0))
1.1 root 1540: (label_ref (match_operand 1 "" ""))
1541: (pc)))
1542: (set (match_dup 0)
1543: (plus:SI (match_dup 0)
1544: (const_int -1)))]
1545: "!TARGET_UNIX_ASM"
1546: "jsobgtr %0,%l1")
1547:
1548: (define_insn ""
1549: [(set (pc)
1550: (if_then_else
1.1.1.2 ! root 1551: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1552: (const_int -1))
! 1553: (const_int 0))
1.1 root 1554: (label_ref (match_operand 1 "" ""))
1555: (pc)))
1556: (set (match_dup 0)
1557: (plus:SI (match_dup 0)
1558: (const_int -1)))]
1559: "!TARGET_UNIX_ASM"
1560: "jsobgeq %0,%l1")
1561:
1562: ;; Normal aob insns. Define a version for when operands[1] is a constant.
1563: (define_insn ""
1564: [(set (pc)
1565: (if_then_else
1566: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1567: (const_int 1))
1568: (match_operand:SI 1 "general_operand" "g"))
1569: (label_ref (match_operand 2 "" ""))
1570: (pc)))
1571: (set (match_dup 0)
1572: (plus:SI (match_dup 0)
1573: (const_int 1)))]
1574: "!TARGET_UNIX_ASM"
1575: "jaoblss %1,%0,%l2")
1576:
1577: (define_insn ""
1578: [(set (pc)
1579: (if_then_else
1580: (lt (match_operand:SI 0 "general_operand" "+g")
1581: (match_operand:SI 1 "general_operand" "g"))
1582: (label_ref (match_operand 2 "" ""))
1583: (pc)))
1584: (set (match_dup 0)
1585: (plus:SI (match_dup 0)
1586: (const_int 1)))]
1587: "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1588: "jaoblss %P1,%0,%l2")
1589:
1590: (define_insn ""
1591: [(set (pc)
1592: (if_then_else
1593: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1594: (const_int 1))
1595: (match_operand:SI 1 "general_operand" "g"))
1596: (label_ref (match_operand 2 "" ""))
1597: (pc)))
1598: (set (match_dup 0)
1599: (plus:SI (match_dup 0)
1600: (const_int 1)))]
1601: "!TARGET_UNIX_ASM"
1602: "jaobleq %1,%0,%l2")
1603:
1604: (define_insn ""
1605: [(set (pc)
1606: (if_then_else
1607: (le (match_operand:SI 0 "general_operand" "+g")
1608: (match_operand:SI 1 "general_operand" "g"))
1609: (label_ref (match_operand 2 "" ""))
1610: (pc)))
1611: (set (match_dup 0)
1612: (plus:SI (match_dup 0)
1613: (const_int 1)))]
1614: "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1615: "jaobleq %P1,%0,%l2")
1616:
1617: ;; Something like a sob insn, but compares against -1.
1618: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1619:
1620: (define_insn ""
1621: [(set (pc)
1622: (if_then_else
1623: (ne (match_operand:SI 0 "general_operand" "g")
1624: (const_int 0))
1625: (label_ref (match_operand 1 "" ""))
1626: (pc)))
1627: (set (match_dup 0)
1628: (plus:SI (match_dup 0)
1629: (const_int -1)))]
1630: ""
1631: "decl %0\;jgequ %l1")
1632:
1633: ;; Note that operand 1 is total size of args, in bytes,
1634: ;; and what the call insn wants is the number of words.
1635: (define_insn "call_pop"
1636: [(call (match_operand:QI 0 "memory_operand" "m")
1637: (match_operand:QI 1 "general_operand" "g"))
1638: (set (reg:SI 14) (plus:SI (reg:SI 14)
1639: (match_operand:SI 3 "immediate_operand" "i")))]
1640: ""
1641: "*
1642: if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4)
1643: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1644: return \"calls $0,%0\;addl2 %1,sp\";
1645: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1646: return \"calls %1,%0\";
1647: ")
1648:
1649: (define_insn "call_value_pop"
1650: [(set (match_operand 0 "" "=g")
1651: (call (match_operand:QI 1 "memory_operand" "m")
1652: (match_operand:QI 2 "general_operand" "g")))
1653: (set (reg:SI 14) (plus:SI (reg:SI 14)
1654: (match_operand:SI 4 "immediate_operand" "i")))]
1655: ""
1656: "*
1657: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4)
1658: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1659: return \"calls $0,%1\;addl2 %2,sp\";
1660: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1661: return \"calls %2,%1\";
1662: ")
1663:
1664: ;; Define another set of these for the case of functions with no
1665: ;; operands. In that case, combine may simplify the adjustment of sp.
1666: (define_insn ""
1667: [(call (match_operand:QI 0 "memory_operand" "m")
1668: (match_operand:QI 1 "general_operand" "g"))
1669: (set (reg:SI 14) (reg:SI 14))]
1670: ""
1671: "*
1672: if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4)
1673: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1674: return \"calls $0,%0\;addl2 %1,sp\";
1675: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1676: return \"calls %1,%0\";
1677: ")
1678:
1679: (define_insn ""
1680: [(set (match_operand 0 "" "=g")
1681: (call (match_operand:QI 1 "memory_operand" "m")
1682: (match_operand:QI 2 "general_operand" "g")))
1683: (set (reg:SI 14) (reg:SI 14))]
1684: ""
1685: "*
1686: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4)
1687: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1688: return \"calls $0,%1\;addl2 %2,sp\";
1689: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1690: return \"calls %2,%1\";
1691: ")
1692:
1693: (define_insn "return"
1694: [(return)]
1695: ""
1696: "ret")
1697:
1698: (define_insn "nop"
1699: [(const_int 0)]
1700: ""
1701: "nop")
1702:
1703: (define_insn "indirect_jump"
1704: [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
1705: "(GET_CODE (operands[0]) != MEM || offsettable_memref_p (operands[0]))"
1706: "jmp (%0)")
1707:
1708: (define_insn "casesi"
1709: [(set (pc)
1710: (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1711: (match_operand:SI 1 "general_operand" "g"))
1712: (match_operand:SI 2 "general_operand" "g"))
1713: (plus:SI (sign_extend:SI
1714: (mem:HI
1715: (plus:SI (pc)
1716: (mult:SI (minus:SI (match_dup 0)
1717: (match_dup 1))
1718: (const_int 2)))))
1719: (label_ref:SI (match_operand 3 "" "")))
1720: (pc)))]
1721: ""
1722: "casel %0,%1,%2")
1723:
1724: ;; This used to arise from the preceding by simplification
1725: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1726: (define_insn ""
1727: [(set (pc)
1728: (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
1729: (match_operand:SI 1 "general_operand" "g"))
1730: (plus:SI (sign_extend:SI
1731: (mem:HI
1732: (plus:SI (pc)
1733: (mult:SI (minus:SI (match_dup 0)
1734: (const_int 0))
1735: (const_int 2)))))
1736: (label_ref:SI (match_operand 3 "" "")))
1737: (pc)))]
1738: ""
1739: "casel %0,$0,%1")
1740:
1741: ;;- load or push effective address
1742: ;; These come after the move and add/sub patterns
1743: ;; because we don't want pushl $1 turned into pushad 1.
1744: ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1745:
1746: (define_insn ""
1747: [(set (match_operand:SI 0 "general_operand" "=<,g")
1748: (match_operand:QI 1 "address_operand" "p,p"))]
1749: ""
1750: "@
1751: pushab %a1
1752: movab %a1,%0")
1753:
1754: (define_insn ""
1755: [(set (match_operand:SI 0 "general_operand" "=<,g")
1756: (match_operand:HI 1 "address_operand" "p,p"))]
1757: ""
1758: "@
1759: pushaw %a1
1760: movaw %a1,%0")
1761:
1762: (define_insn ""
1763: [(set (match_operand:SI 0 "general_operand" "=<,g")
1764: (match_operand:SI 1 "address_operand" "p,p"))]
1765: ""
1766: "@
1767: pushal %a1
1768: moval %a1,%0")
1769:
1770: (define_insn ""
1771: [(set (match_operand:SI 0 "general_operand" "=<,g")
1772: (match_operand:DI 1 "address_operand" "p,p"))]
1773: ""
1774: "@
1775: pushaq %a1
1776: movaq %a1,%0")
1777:
1778: (define_insn ""
1779: [(set (match_operand:SI 0 "general_operand" "=<,g")
1780: (match_operand:SF 1 "address_operand" "p,p"))]
1781: ""
1782: "@
1783: pushaf %a1
1784: movaf %a1,%0")
1785:
1786: (define_insn ""
1787: [(set (match_operand:SI 0 "general_operand" "=<,g")
1788: (match_operand:DF 1 "address_operand" "p,p"))]
1789: ""
1790: "@
1791: pushad %a1
1792: movad %a1,%0")
1793:
1794: ;; These used to be peepholes, but it is more straightforward to do them
1795: ;; as single insns. However, we must force the output to be a register
1796: ;; if it is not an offsettable address so that we know that we can assign
1797: ;; to it twice.
1798:
1799: ;; If we had a good way of evaluating the relative costs, these could be
1800: ;; machine-independent.
1801:
1802: ;; Optimize extzv ...,z; andl2 ...,z
1803: ;; or ashl ...,z; andl2 ...,z
1804: ;; with other operands constant. This is what the combiner converts the
1805: ;; above sequences to before attempting to recognize the new insn.
1806:
1807: (define_insn ""
1808: [(set (match_operand:SI 0 "general_operand" "=ro")
1809: (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1810: (match_operand:QI 2 "const_int_operand" "n"))
1811: (match_operand:SI 3 "const_int_operand" "n")))]
1812: "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1813: "*
1814: {
1815: unsigned long mask1 = INTVAL (operands[3]);
1816: unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1817:
1818: if ((mask1 & mask2) != mask1)
1819: operands[3] = gen_rtx (CONST_INT, VOIDmode, mask1 & mask2);
1820:
1821: return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1822: }")
1823:
1824: ;; left-shift and mask
1825: ;; The only case where `ashl' is better is if the mask only turns off
1826: ;; bits that the ashl would anyways, in which case it should have been
1827: ;; optimized away.
1828:
1829: (define_insn ""
1830: [(set (match_operand:SI 0 "general_operand" "=ro")
1831: (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
1832: (match_operand:QI 2 "const_int_operand" "n"))
1833: (match_operand:SI 3 "const_int_operand" "n")))]
1834: ""
1835: "*
1836: {
1837: operands[3] = gen_rtx (CONST_INT, VOIDmode,
1838: INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1839: return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1840: }")
1841:
1842: ;;- Local variables:
1843: ;;- mode:emacs-lisp
1844: ;;- comment-start: ";;- "
1845: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1846: ;;- eval: (modify-syntax-entry ?[ "(]")
1847: ;;- eval: (modify-syntax-entry ?] ")[")
1848: ;;- eval: (modify-syntax-entry ?{ "(}")
1849: ;;- eval: (modify-syntax-entry ?} "){")
1850: ;;- End:
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