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Up to [GCC 1.x] / gcc / config|
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1.1 root 1:
2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987, 1988 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 1, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22:
23: ;;- Instruction patterns. When multiple patterns apply,
24: ;;- the first one in the file is chosen.
25: ;;-
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27: ;;-
28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29: ;;- updates for most instructions.
30:
31: ; tstsi is first test insn so that it is the one to match
32: ; a constant argument.
33:
34: (define_insn "tstsi"
35: [(set (cc0)
36: (match_operand:SI 0 "general_operand" "g"))]
37: ""
38: "tstl %0")
39:
40: (define_insn "tsthi"
41: [(set (cc0)
42: (match_operand:HI 0 "general_operand" "g"))]
43: ""
44: "tstw %0")
45:
46: (define_insn "tstqi"
47: [(set (cc0)
48: (match_operand:QI 0 "general_operand" "g"))]
49: ""
50: "tstb %0")
51:
52: (define_insn "tstdf"
53: [(set (cc0)
54: (match_operand:DF 0 "general_operand" "gF"))]
55: ""
56: "tst%# %0")
57:
58: (define_insn "tstsf"
59: [(set (cc0)
60: (match_operand:SF 0 "general_operand" "gF"))]
61: ""
62: "tstf %0")
63:
64: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
65:
66: (define_insn "cmpsi"
67: [(set (cc0)
68: (compare (match_operand:SI 0 "general_operand" "g")
69: (match_operand:SI 1 "general_operand" "g")))]
70: ""
71: "cmpl %0,%1")
72:
73: (define_insn "cmphi"
74: [(set (cc0)
75: (compare (match_operand:HI 0 "general_operand" "g")
76: (match_operand:HI 1 "general_operand" "g")))]
77: ""
78: "cmpw %0,%1")
79:
80: (define_insn "cmpqi"
81: [(set (cc0)
82: (compare (match_operand:QI 0 "general_operand" "g")
83: (match_operand:QI 1 "general_operand" "g")))]
84: ""
85: "cmpb %0,%1")
86:
87: (define_insn "cmpdf"
88: [(set (cc0)
89: (compare (match_operand:DF 0 "general_operand" "gF")
90: (match_operand:DF 1 "general_operand" "gF")))]
91: ""
92: "cmp%# %0,%1")
93:
94: (define_insn "cmpsf"
95: [(set (cc0)
96: (compare (match_operand:SF 0 "general_operand" "gF")
97: (match_operand:SF 1 "general_operand" "gF")))]
98: ""
99: "cmpf %0,%1")
100:
101: (define_insn ""
102: [(set (cc0)
103: (and:SI (match_operand:SI 0 "general_operand" "g")
104: (match_operand:SI 1 "general_operand" "g")))]
105: ""
106: "bitl %0,%1")
107:
108: (define_insn ""
109: [(set (cc0)
110: (and:HI (match_operand:HI 0 "general_operand" "g")
111: (match_operand:HI 1 "general_operand" "g")))]
112: ""
113: "bitw %0,%1")
114:
115: (define_insn ""
116: [(set (cc0)
117: (and:QI (match_operand:QI 0 "general_operand" "g")
118: (match_operand:QI 1 "general_operand" "g")))]
119: ""
120: "bitb %0,%1")
121:
122: (define_insn "movdf"
123: [(set (match_operand:DF 0 "general_operand" "=g")
124: (match_operand:DF 1 "general_operand" "gF"))]
125: ""
126: "*
127: {
128: if (operands[1] == dconst0_rtx)
129: return \"clr%# %0\";
130: return \"mov%# %1,%0\";
131: }")
132:
133: (define_insn "movsf"
134: [(set (match_operand:SF 0 "general_operand" "=g")
135: (match_operand:SF 1 "general_operand" "gF"))]
136: ""
137: "*
138: {
139: if (operands[1] == fconst0_rtx)
140: return \"clrf %0\";
141: return \"movf %1,%0\";
142: }")
143:
144: ;; Some vaxes don't support this instruction.
145: ;;(define_insn "movti"
146: ;; [(set (match_operand:TI 0 "general_operand" "=g")
147: ;; (match_operand:TI 1 "general_operand" "g"))]
148: ;; ""
149: ;; "movh %1,%0")
150:
151: (define_insn "movdi"
152: [(set (match_operand:DI 0 "general_operand" "=g")
153: (match_operand:DI 1 "general_operand" "g"))]
154: ""
155: "movq %1,%0")
156:
1.1.1.3 ! root 157: ;; This handles constants which are not legitimate
! 158: ;; for the sake of shared libraries on VMS.
! 159: (define_insn ""
! 160: [(set (match_operand:SI 0 "general_operand" "=g")
! 161: (match_operand:SI 1 "" "i"))]
! 162: "CONSTANT_P (operands[1]) && ! LEGITIMATE_CONSTANT_P (operands[1])"
! 163: "*
! 164: {
! 165: operands[2] = XEXP (XEXP (operands[1], 0), 0);
! 166: operands[1] = XEXP (XEXP (operands[1], 0), 1);
! 167: return \"movl %2,%0\;addl2 %1,%0\";
! 168: }")
! 169:
1.1 root 170: (define_insn "movsi"
171: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.3 ! root 172: (match_operand:SI 1 "supergeneral_operand" "g"))]
1.1 root 173: ""
174: "*
175: {
176: rtx link;
177: if (operands[1] == const1_rtx
178: && (link = find_reg_note (insn, REG_WAS_0, 0))
179: /* Make sure the insn that stored the 0 is still present. */
180: && ! XEXP (link, 0)->volatil
181: && GET_CODE (XEXP (link, 0)) != NOTE
182: /* Make sure cross jumping didn't happen here. */
183: && no_labels_between_p (XEXP (link, 0), insn))
184: /* Fastest way to change a 0 to a 1. */
185: return \"incl %0\";
186: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
187: {
188: if (push_operand (operands[0], SImode))
189: return \"pushab %a1\";
190: return \"movab %a1,%0\";
191: }
192: /* this is slower than a movl, except when pushing an operand */
193: if (operands[1] == const0_rtx)
194: return \"clrl %0\";
195: if (GET_CODE (operands[1]) == CONST_INT
196: && (unsigned) INTVAL (operands[1]) >= 64)
197: {
198: int i = INTVAL (operands[1]);
199: if ((unsigned)(~i) < 64)
200: {
201: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
202: return \"mcoml %1,%0\";
203: }
204: if ((unsigned)i < 127)
205: {
206: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
207: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
208: return \"addl3 %2,%1,%0\";
209: }
210: /* trading speed for space */
211: if ((unsigned)i < 0x100)
212: return \"movzbl %1,%0\";
213: if (i >= -0x80 && i < 0)
214: return \"cvtbl %1,%0\";
215: if ((unsigned)i < 0x10000)
216: return \"movzwl %1,%0\";
217: if (i >= -0x8000 && i < 0)
218: return \"cvtwl %1,%0\";
219: }
220: if (push_operand (operands[0], SImode))
221: return \"pushl %1\";
222: return \"movl %1,%0\";
223: }")
224:
225: (define_insn "movhi"
226: [(set (match_operand:HI 0 "general_operand" "=g")
227: (match_operand:HI 1 "general_operand" "g"))]
228: ""
229: "*
230: {
231: rtx link;
232: if (operands[1] == const1_rtx
233: && (link = find_reg_note (insn, REG_WAS_0, 0))
234: /* Make sure the insn that stored the 0 is still present. */
235: && ! XEXP (link, 0)->volatil
236: && GET_CODE (XEXP (link, 0)) != NOTE
237: /* Make sure cross jumping didn't happen here. */
238: && no_labels_between_p (XEXP (link, 0), insn))
239: /* Fastest way to change a 0 to a 1. */
240: return \"incw %0\";
241: if (operands[1] == const0_rtx)
242: return \"clrw %0\";
243: if (GET_CODE (operands[1]) == CONST_INT
244: && (unsigned) INTVAL (operands[1]) >= 64)
245: {
246: int i = INTVAL (operands[1]);
247: if ((unsigned)((~i) & 0xffff) < 64)
248: {
249: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff);
250: return \"mcomw %1,%0\";
251: }
252: if ((unsigned)(i & 0xffff) < 127)
253: {
254: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
255: operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff);
256: return \"addw3 %2,%1,%0\";
257: }
258: /* this is a lot slower, and only saves 1 measly byte! */
259: /* if ((unsigned)i < 0x100)
260: return \"movzbw %1,%0\"; */
261: /* if (i >= -0x80 && i < 0)
262: return \"cvtbw %1,%0\"; */
263: }
264: return \"movw %1,%0\";
265: }")
266:
267: (define_insn "movqi"
268: [(set (match_operand:QI 0 "general_operand" "=g")
269: (match_operand:QI 1 "general_operand" "g"))]
270: ""
271: "*
272: {
273: if (operands[1] == const0_rtx)
274: return \"clrb %0\";
275: if (GET_CODE (operands[1]) == CONST_INT
276: && (unsigned) INTVAL (operands[1]) >= 64)
277: {
278: int i = INTVAL (operands[1]);
279: if ((unsigned)((~i) & 0xff) < 64)
280: {
281: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff);
282: return \"mcomb %1,%0\";
283: }
284: #if 0
285: /* ASCII alphabetics */
286: if (((unsigned) INTVAL (operands[1]) &0xff) < 127)
287: {
288: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
289: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
290: return \"addb3 %2,%1,%0\";
291: }
292: #endif
293: }
294: return \"movb %1,%0\";
295: }")
296:
297: ;; The definition of this insn does not really explain what it does,
298: ;; but it should suffice
299: ;; that anything generated as this insn will be recognized as one
300: ;; and that it won't successfully combine with anything.
301: (define_insn "movstrhi"
302: [(set (match_operand:BLK 0 "general_operand" "=g")
303: (match_operand:BLK 1 "general_operand" "g"))
304: (use (match_operand:HI 2 "general_operand" "g"))
305: (clobber (reg:SI 0))
306: (clobber (reg:SI 1))
307: (clobber (reg:SI 2))
308: (clobber (reg:SI 3))
309: (clobber (reg:SI 4))
310: (clobber (reg:SI 5))]
311: ""
312: "movc3 %2,%1,%0")
313:
314: ;; Extension and truncation insns.
315: ;; Those for integer source operand
316: ;; are ordered widest source type first.
317:
318: (define_insn "truncsiqi2"
319: [(set (match_operand:QI 0 "general_operand" "=g")
320: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
321: ""
322: "cvtlb %1,%0")
323:
324: (define_insn "truncsihi2"
325: [(set (match_operand:HI 0 "general_operand" "=g")
326: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
327: ""
328: "cvtlw %1,%0")
329:
330: (define_insn "trunchiqi2"
331: [(set (match_operand:QI 0 "general_operand" "=g")
332: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
333: ""
334: "cvtwb %1,%0")
335:
336: (define_insn "extendhisi2"
337: [(set (match_operand:SI 0 "general_operand" "=g")
338: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
339: ""
340: "cvtwl %1,%0")
341:
342: (define_insn "extendqihi2"
343: [(set (match_operand:HI 0 "general_operand" "=g")
344: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
345: ""
346: "cvtbw %1,%0")
347:
348: (define_insn "extendqisi2"
349: [(set (match_operand:SI 0 "general_operand" "=g")
350: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
351: ""
352: "cvtbl %1,%0")
353:
354: (define_insn "extendsfdf2"
355: [(set (match_operand:DF 0 "general_operand" "=g")
356: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
357: ""
358: "cvtf%# %1,%0")
359:
360: (define_insn "truncdfsf2"
361: [(set (match_operand:SF 0 "general_operand" "=g")
362: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
363: ""
364: "cvt%#f %1,%0")
365:
366: (define_insn "zero_extendhisi2"
367: [(set (match_operand:SI 0 "general_operand" "=g")
368: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
369: ""
370: "movzwl %1,%0")
371:
372: (define_insn "zero_extendqihi2"
373: [(set (match_operand:HI 0 "general_operand" "=g")
374: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
375: ""
376: "movzbw %1,%0")
377:
378: (define_insn "zero_extendqisi2"
379: [(set (match_operand:SI 0 "general_operand" "=g")
380: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
381: ""
382: "movzbl %1,%0")
383:
384: ;; Fix-to-float conversion insns.
385: ;; Note that the ones that start with SImode come first.
386: ;; That is so that an operand that is a CONST_INT
387: ;; (and therefore lacks a specific machine mode).
388: ;; will be recognized as SImode (which is always valid)
389: ;; rather than as QImode or HImode.
390:
391: (define_insn "floatsisf2"
392: [(set (match_operand:SF 0 "general_operand" "=g")
393: (float:SF (match_operand:SI 1 "general_operand" "g")))]
394: ""
395: "cvtlf %1,%0")
396:
397: (define_insn "floatsidf2"
398: [(set (match_operand:DF 0 "general_operand" "=g")
399: (float:DF (match_operand:SI 1 "general_operand" "g")))]
400: ""
401: "cvtl%# %1,%0")
402:
403: (define_insn "floathisf2"
404: [(set (match_operand:SF 0 "general_operand" "=g")
405: (float:SF (match_operand:HI 1 "general_operand" "g")))]
406: ""
407: "cvtwf %1,%0")
408:
409: (define_insn "floathidf2"
410: [(set (match_operand:DF 0 "general_operand" "=g")
411: (float:DF (match_operand:HI 1 "general_operand" "g")))]
412: ""
413: "cvtw%# %1,%0")
414:
415: (define_insn "floatqisf2"
416: [(set (match_operand:SF 0 "general_operand" "=g")
417: (float:SF (match_operand:QI 1 "general_operand" "g")))]
418: ""
419: "cvtbf %1,%0")
420:
421: (define_insn "floatqidf2"
422: [(set (match_operand:DF 0 "general_operand" "=g")
423: (float:DF (match_operand:QI 1 "general_operand" "g")))]
424: ""
425: "cvtb%# %1,%0")
426:
427: ;; Float-to-fix conversion insns.
428:
429: (define_insn "fix_truncsfqi2"
430: [(set (match_operand:QI 0 "general_operand" "=g")
431: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
432: ""
433: "cvtfb %1,%0")
434:
435: (define_insn "fix_truncsfhi2"
436: [(set (match_operand:HI 0 "general_operand" "=g")
437: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
438: ""
439: "cvtfw %1,%0")
440:
441: (define_insn "fix_truncsfsi2"
442: [(set (match_operand:SI 0 "general_operand" "=g")
443: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
444: ""
445: "cvtfl %1,%0")
446:
447: (define_insn "fix_truncdfqi2"
448: [(set (match_operand:QI 0 "general_operand" "=g")
449: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
450: ""
451: "cvt%#b %1,%0")
452:
453: (define_insn "fix_truncdfhi2"
454: [(set (match_operand:HI 0 "general_operand" "=g")
455: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
456: ""
457: "cvt%#w %1,%0")
458:
459: (define_insn "fix_truncdfsi2"
460: [(set (match_operand:SI 0 "general_operand" "=g")
461: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
462: ""
463: "cvt%#l %1,%0")
464:
465: ;;- All kinds of add instructions.
466:
467: (define_insn "adddf3"
468: [(set (match_operand:DF 0 "general_operand" "=g")
469: (plus:DF (match_operand:DF 1 "general_operand" "gF")
470: (match_operand:DF 2 "general_operand" "gF")))]
471: ""
472: "*
473: {
474: if (rtx_equal_p (operands[0], operands[1]))
475: return \"add%#2 %2,%0\";
476: if (rtx_equal_p (operands[0], operands[2]))
477: return \"add%#2 %1,%0\";
478: return \"add%#3 %1,%2,%0\";
479: }")
480:
481: (define_insn "addsf3"
482: [(set (match_operand:SF 0 "general_operand" "=g")
483: (plus:SF (match_operand:SF 1 "general_operand" "gF")
484: (match_operand:SF 2 "general_operand" "gF")))]
485: ""
486: "*
487: {
488: if (rtx_equal_p (operands[0], operands[1]))
489: return \"addf2 %2,%0\";
490: if (rtx_equal_p (operands[0], operands[2]))
491: return \"addf2 %1,%0\";
492: return \"addf3 %1,%2,%0\";
493: }")
494:
495: (define_insn "addsi3"
496: [(set (match_operand:SI 0 "general_operand" "=g")
497: (plus:SI (match_operand:SI 1 "general_operand" "g")
498: (match_operand:SI 2 "general_operand" "g")))]
499: ""
500: "*
501: {
502: if (rtx_equal_p (operands[0], operands[1]))
503: {
504: if (operands[2] == const1_rtx)
505: return \"incl %0\";
506: if (GET_CODE (operands[2]) == CONST_INT
507: && INTVAL (operands[2]) == -1)
508: return \"decl %0\";
509: if (GET_CODE (operands[2]) == CONST_INT
510: && (unsigned) (- INTVAL (operands[2])) < 64)
511: return \"subl2 $%n2,%0\";
512: if (GET_CODE (operands[2]) == CONST_INT
513: && (unsigned) INTVAL (operands[2]) >= 64
514: && GET_CODE (operands[1]) == REG)
515: return \"movab %c2(%1),%0\";
516: return \"addl2 %2,%0\";
517: }
518: if (rtx_equal_p (operands[0], operands[2]))
519: return \"addl2 %1,%0\";
520: if (GET_CODE (operands[2]) == CONST_INT
521: && (unsigned) (- INTVAL (operands[2])) < 64)
522: return \"subl3 $%n2,%1,%0\";
523: if (GET_CODE (operands[2]) == CONST_INT
524: && (unsigned) INTVAL (operands[2]) >= 64
525: && GET_CODE (operands[1]) == REG)
526: {
527: if (push_operand (operands[0], SImode))
528: return \"pushab %c2(%1)\";
529: return \"movab %c2(%1),%0\";
530: }
531: return \"addl3 %1,%2,%0\";
532: }")
533:
534: (define_insn "addhi3"
535: [(set (match_operand:HI 0 "general_operand" "=g")
536: (plus:HI (match_operand:HI 1 "general_operand" "g")
537: (match_operand:HI 2 "general_operand" "g")))]
538: ""
539: "*
540: {
541: if (rtx_equal_p (operands[0], operands[1]))
542: {
543: if (operands[2] == const1_rtx)
544: return \"incw %0\";
545: if (GET_CODE (operands[1]) == CONST_INT
546: && INTVAL (operands[1]) == -1)
547: return \"decw %0\";
548: if (GET_CODE (operands[2]) == CONST_INT
549: && (unsigned) (- INTVAL (operands[2])) < 64)
550: return \"subw2 $%n2,%0\";
551: return \"addw2 %2,%0\";
552: }
553: if (rtx_equal_p (operands[0], operands[2]))
554: return \"addw2 %1,%0\";
555: if (GET_CODE (operands[2]) == CONST_INT
556: && (unsigned) (- INTVAL (operands[2])) < 64)
557: return \"subw3 $%n2,%1,%0\";
558: return \"addw3 %1,%2,%0\";
559: }")
560:
561: (define_insn "addqi3"
562: [(set (match_operand:QI 0 "general_operand" "=g")
563: (plus:QI (match_operand:QI 1 "general_operand" "g")
564: (match_operand:QI 2 "general_operand" "g")))]
565: ""
566: "*
567: {
568: if (rtx_equal_p (operands[0], operands[1]))
569: {
570: if (operands[2] == const1_rtx)
571: return \"incb %0\";
572: if (GET_CODE (operands[1]) == CONST_INT
573: && INTVAL (operands[1]) == -1)
574: return \"decb %0\";
575: if (GET_CODE (operands[2]) == CONST_INT
576: && (unsigned) (- INTVAL (operands[2])) < 64)
577: return \"subb2 $%n2,%0\";
578: return \"addb2 %2,%0\";
579: }
580: if (rtx_equal_p (operands[0], operands[2]))
581: return \"addb2 %1,%0\";
582: if (GET_CODE (operands[2]) == CONST_INT
583: && (unsigned) (- INTVAL (operands[2])) < 64)
584: return \"subb3 $%n2,%1,%0\";
585: return \"addb3 %1,%2,%0\";
586: }")
587:
588: ;;- All kinds of subtract instructions.
589:
590: (define_insn "subdf3"
591: [(set (match_operand:DF 0 "general_operand" "=g")
592: (minus:DF (match_operand:DF 1 "general_operand" "gF")
593: (match_operand:DF 2 "general_operand" "gF")))]
594: ""
595: "*
596: {
597: if (rtx_equal_p (operands[0], operands[1]))
598: return \"sub%#2 %2,%0\";
599: return \"sub%#3 %2,%1,%0\";
600: }")
601:
602: (define_insn "subsf3"
603: [(set (match_operand:SF 0 "general_operand" "=g")
604: (minus:SF (match_operand:SF 1 "general_operand" "gF")
605: (match_operand:SF 2 "general_operand" "gF")))]
606: ""
607: "*
608: {
609: if (rtx_equal_p (operands[0], operands[1]))
610: return \"subf2 %2,%0\";
611: return \"subf3 %2,%1,%0\";
612: }")
613:
614: (define_insn "subsi3"
615: [(set (match_operand:SI 0 "general_operand" "=g")
616: (minus:SI (match_operand:SI 1 "general_operand" "g")
617: (match_operand:SI 2 "general_operand" "g")))]
618: ""
619: "*
620: {
621: if (rtx_equal_p (operands[0], operands[1]))
622: {
623: if (operands[2] == const1_rtx)
624: return \"decl %0\";
625: return \"subl2 %2,%0\";
626: }
627: return \"subl3 %2,%1,%0\";
628: }")
629:
630: (define_insn "subhi3"
631: [(set (match_operand:HI 0 "general_operand" "=g")
632: (minus:HI (match_operand:HI 1 "general_operand" "g")
633: (match_operand:HI 2 "general_operand" "g")))]
634: ""
635: "*
636: {
637: if (rtx_equal_p (operands[0], operands[1]))
638: {
639: if (operands[2] == const1_rtx)
640: return \"decw %0\";
641: return \"subw2 %2,%0\";
642: }
643: return \"subw3 %2,%1,%0\";
644: }")
645:
646: (define_insn "subqi3"
647: [(set (match_operand:QI 0 "general_operand" "=g")
648: (minus:QI (match_operand:QI 1 "general_operand" "g")
649: (match_operand:QI 2 "general_operand" "g")))]
650: ""
651: "*
652: {
653: if (rtx_equal_p (operands[0], operands[1]))
654: {
655: if (operands[2] == const1_rtx)
656: return \"decb %0\";
657: return \"subb2 %2,%0\";
658: }
659: return \"subb3 %2,%1,%0\";
660: }")
661:
662: ;;- Multiply instructions.
663:
664: (define_insn "muldf3"
665: [(set (match_operand:DF 0 "general_operand" "=g")
666: (mult:DF (match_operand:DF 1 "general_operand" "gF")
667: (match_operand:DF 2 "general_operand" "gF")))]
668: ""
669: "*
670: {
671: if (rtx_equal_p (operands[0], operands[1]))
672: return \"mul%#2 %2,%0\";
673: if (rtx_equal_p (operands[0], operands[2]))
674: return \"mul%#2 %1,%0\";
675: return \"mul%#3 %1,%2,%0\";
676: }")
677:
678: (define_insn "mulsf3"
679: [(set (match_operand:SF 0 "general_operand" "=g")
680: (mult:SF (match_operand:SF 1 "general_operand" "gF")
681: (match_operand:SF 2 "general_operand" "gF")))]
682: ""
683: "*
684: {
685: if (rtx_equal_p (operands[0], operands[1]))
686: return \"mulf2 %2,%0\";
687: if (rtx_equal_p (operands[0], operands[2]))
688: return \"mulf2 %1,%0\";
689: return \"mulf3 %1,%2,%0\";
690: }")
691:
692: (define_insn "mulsi3"
693: [(set (match_operand:SI 0 "general_operand" "=g")
694: (mult:SI (match_operand:SI 1 "general_operand" "g")
695: (match_operand:SI 2 "general_operand" "g")))]
696: ""
697: "*
698: {
699: if (rtx_equal_p (operands[0], operands[1]))
700: return \"mull2 %2,%0\";
701: if (rtx_equal_p (operands[0], operands[2]))
702: return \"mull2 %1,%0\";
703: return \"mull3 %1,%2,%0\";
704: }")
705:
706: (define_insn "mulhi3"
707: [(set (match_operand:HI 0 "general_operand" "=g")
708: (mult:HI (match_operand:HI 1 "general_operand" "g")
709: (match_operand:HI 2 "general_operand" "g")))]
710: ""
711: "*
712: {
713: if (rtx_equal_p (operands[0], operands[1]))
714: return \"mulw2 %2,%0\";
715: if (rtx_equal_p (operands[0], operands[2]))
716: return \"mulw2 %1,%0\";
717: return \"mulw3 %1,%2,%0\";
718: }")
719:
720: (define_insn "mulqi3"
721: [(set (match_operand:QI 0 "general_operand" "=g")
722: (mult:QI (match_operand:QI 1 "general_operand" "g")
723: (match_operand:QI 2 "general_operand" "g")))]
724: ""
725: "*
726: {
727: if (rtx_equal_p (operands[0], operands[1]))
728: return \"mulb2 %2,%0\";
729: if (rtx_equal_p (operands[0], operands[2]))
730: return \"mulb2 %1,%0\";
731: return \"mulb3 %1,%2,%0\";
732: }")
733:
734: ;;- Divide instructions.
735:
736: (define_insn "divdf3"
737: [(set (match_operand:DF 0 "general_operand" "=g")
738: (div:DF (match_operand:DF 1 "general_operand" "gF")
739: (match_operand:DF 2 "general_operand" "gF")))]
740: ""
741: "*
742: {
743: if (rtx_equal_p (operands[0], operands[1]))
744: return \"div%#2 %2,%0\";
745: return \"div%#3 %2,%1,%0\";
746: }")
747:
748: (define_insn "divsf3"
749: [(set (match_operand:SF 0 "general_operand" "=g")
750: (div:SF (match_operand:SF 1 "general_operand" "gF")
751: (match_operand:SF 2 "general_operand" "gF")))]
752: ""
753: "*
754: {
755: if (rtx_equal_p (operands[0], operands[1]))
756: return \"divf2 %2,%0\";
757: return \"divf3 %2,%1,%0\";
758: }")
759:
760: (define_insn "divsi3"
761: [(set (match_operand:SI 0 "general_operand" "=g")
762: (div:SI (match_operand:SI 1 "general_operand" "g")
763: (match_operand:SI 2 "general_operand" "g")))]
764: ""
765: "*
766: {
767: if (rtx_equal_p (operands[0], operands[1]))
768: return \"divl2 %2,%0\";
769: return \"divl3 %2,%1,%0\";
770: }")
771:
772: (define_insn "divhi3"
773: [(set (match_operand:HI 0 "general_operand" "=g")
774: (div:HI (match_operand:HI 1 "general_operand" "g")
775: (match_operand:HI 2 "general_operand" "g")))]
776: ""
777: "*
778: {
779: if (rtx_equal_p (operands[0], operands[1]))
780: return \"divw2 %2,%0\";
781: return \"divw3 %2,%1,%0\";
782: }")
783:
784: (define_insn "divqi3"
785: [(set (match_operand:QI 0 "general_operand" "=g")
786: (div:QI (match_operand:QI 1 "general_operand" "g")
787: (match_operand:QI 2 "general_operand" "g")))]
788: ""
789: "*
790: {
791: if (rtx_equal_p (operands[0], operands[1]))
792: return \"divb2 %2,%0\";
793: return \"divb3 %2,%1,%0\";
794: }")
795:
796: ;This is left out because it is very slow;
797: ;we are better off programming around the "lack" of this insn.
798: ;(define_insn "divmoddisi4"
799: ; [(set (match_operand:SI 0 "general_operand" "=g")
800: ; (div:SI (match_operand:DI 1 "general_operand" "g")
801: ; (match_operand:SI 2 "general_operand" "g")))
802: ; (set (match_operand:SI 3 "general_operand" "=g")
803: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
804: ; (match_operand:SI 2 "general_operand" "g")))]
805: ; ""
806: ; "ediv %2,%1,%0,%3")
807:
808: ;; Bit-and on the vax is done with a clear-bits insn.
809: (define_expand "andsi3"
810: [(set (match_operand:SI 0 "general_operand" "=g")
811: (and:SI (match_operand:SI 1 "general_operand" "g")
812: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
813: ""
814: "
815: {
816: extern rtx expand_unop ();
817: if (GET_CODE (operands[2]) == CONST_INT)
818: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
819: else
820: operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
821: }")
822:
823: (define_expand "andhi3"
824: [(set (match_operand:HI 0 "general_operand" "=g")
825: (and:HI (match_operand:HI 1 "general_operand" "g")
826: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
827: ""
828: "
829: {
830: extern rtx expand_unop ();
831: rtx op = operands[2];
832: if (GET_CODE (op) == CONST_INT)
833: operands[2] = gen_rtx (CONST_INT, VOIDmode,
834: ((1 << 16) - 1) & ~INTVAL (op));
835: else
836: operands[2] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
837: }")
838:
839: (define_expand "andqi3"
840: [(set (match_operand:QI 0 "general_operand" "=g")
841: (and:QI (match_operand:QI 1 "general_operand" "g")
842: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
843: ""
844: "
845: {
846: extern rtx expand_unop ();
847: rtx op = operands[2];
848: if (GET_CODE (op) == CONST_INT)
849: operands[2] = gen_rtx (CONST_INT, VOIDmode,
850: ((1 << 8) - 1) & ~INTVAL (op));
851: else
852: operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
853: }")
854:
855: (define_insn "andcbsi3"
856: [(set (match_operand:SI 0 "general_operand" "=g")
857: (and:SI (match_operand:SI 1 "general_operand" "g")
858: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
859: ""
860: "*
861: {
862: if (rtx_equal_p (operands[0], operands[1]))
863: return \"bicl2 %2,%0\";
864: return \"bicl3 %2,%1,%0\";
865: }")
866:
867: (define_insn "andcbhi3"
868: [(set (match_operand:HI 0 "general_operand" "=g")
869: (and:HI (match_operand:HI 1 "general_operand" "g")
870: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
871: ""
872: "*
873: {
874: if (rtx_equal_p (operands[0], operands[1]))
875: return \"bicw2 %2,%0\";
876: return \"bicw3 %2,%1,%0\";
877: }")
878:
879: (define_insn "andcbqi3"
880: [(set (match_operand:QI 0 "general_operand" "=g")
881: (and:QI (match_operand:QI 1 "general_operand" "g")
882: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
883: ""
884: "*
885: {
886: if (rtx_equal_p (operands[0], operands[1]))
887: return \"bicb2 %2,%0\";
888: return \"bicb3 %2,%1,%0\";
889: }")
890:
891: ;; The following are needed because constant propagation can
892: ;; create them starting from the bic insn patterns above.
893:
894: (define_insn ""
895: [(set (match_operand:SI 0 "general_operand" "=g")
896: (and:SI (match_operand:SI 1 "general_operand" "g")
897: (match_operand:SI 2 "general_operand" "g")))]
898: "GET_CODE (operands[2]) == CONST_INT"
899: "*
900: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
901: if (rtx_equal_p (operands[1], operands[0]))
902: return \"bicl2 %2,%0\";
903: return \"bicl3 %2,%1,%0\";
904: }")
905:
906: (define_insn ""
907: [(set (match_operand:HI 0 "general_operand" "=g")
908: (and:HI (match_operand:HI 1 "general_operand" "g")
909: (match_operand:HI 2 "general_operand" "g")))]
910: "GET_CODE (operands[2]) == CONST_INT"
911: "*
912: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
913: if (rtx_equal_p (operands[1], operands[0]))
914: return \"bicw2 %2,%0\";
915: return \"bicw3 %2,%1,%0\";
916: }")
917:
918: (define_insn ""
919: [(set (match_operand:QI 0 "general_operand" "=g")
920: (and:QI (match_operand:QI 1 "general_operand" "g")
921: (match_operand:QI 2 "general_operand" "g")))]
922: "GET_CODE (operands[2]) == CONST_INT"
923: "*
924: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
925: if (rtx_equal_p (operands[1], operands[0]))
926: return \"bicb2 %2,%0\";
927: return \"bicb3 %2,%1,%0\";
928: }")
929:
930: ;;- Bit set instructions.
931:
932: (define_insn "iorsi3"
933: [(set (match_operand:SI 0 "general_operand" "=g")
934: (ior:SI (match_operand:SI 1 "general_operand" "g")
935: (match_operand:SI 2 "general_operand" "g")))]
936: ""
937: "*
938: {
939: if (rtx_equal_p (operands[0], operands[1]))
940: return \"bisl2 %2,%0\";
941: if (rtx_equal_p (operands[0], operands[2]))
942: return \"bisl2 %1,%0\";
943: return \"bisl3 %2,%1,%0\";
944: }")
945:
946: (define_insn "iorhi3"
947: [(set (match_operand:HI 0 "general_operand" "=g")
948: (ior:HI (match_operand:HI 1 "general_operand" "g")
949: (match_operand:HI 2 "general_operand" "g")))]
950: ""
951: "*
952: {
953: if (rtx_equal_p (operands[0], operands[1]))
954: return \"bisw2 %2,%0\";
955: if (rtx_equal_p (operands[0], operands[2]))
956: return \"bisw2 %1,%0\";
957: return \"bisw3 %2,%1,%0\";
958: }")
959:
960: (define_insn "iorqi3"
961: [(set (match_operand:QI 0 "general_operand" "=g")
962: (ior:QI (match_operand:QI 1 "general_operand" "g")
963: (match_operand:QI 2 "general_operand" "g")))]
964: ""
965: "*
966: {
967: if (rtx_equal_p (operands[0], operands[1]))
968: return \"bisb2 %2,%0\";
969: if (rtx_equal_p (operands[0], operands[2]))
970: return \"bisb2 %1,%0\";
971: return \"bisb3 %2,%1,%0\";
972: }")
973:
974: ;;- xor instructions.
975:
976: (define_insn "xorsi3"
977: [(set (match_operand:SI 0 "general_operand" "=g")
978: (xor:SI (match_operand:SI 1 "general_operand" "g")
979: (match_operand:SI 2 "general_operand" "g")))]
980: ""
981: "*
982: {
983: if (rtx_equal_p (operands[0], operands[1]))
984: return \"xorl2 %2,%0\";
985: if (rtx_equal_p (operands[0], operands[2]))
986: return \"xorl2 %1,%0\";
987: return \"xorl3 %2,%1,%0\";
988: }")
989:
990: (define_insn "xorhi3"
991: [(set (match_operand:HI 0 "general_operand" "=g")
992: (xor:HI (match_operand:HI 1 "general_operand" "g")
993: (match_operand:HI 2 "general_operand" "g")))]
994: ""
995: "*
996: {
997: if (rtx_equal_p (operands[0], operands[1]))
998: return \"xorw2 %2,%0\";
999: if (rtx_equal_p (operands[0], operands[2]))
1000: return \"xorw2 %1,%0\";
1001: return \"xorw3 %2,%1,%0\";
1002: }")
1003:
1004: (define_insn "xorqi3"
1005: [(set (match_operand:QI 0 "general_operand" "=g")
1006: (xor:QI (match_operand:QI 1 "general_operand" "g")
1007: (match_operand:QI 2 "general_operand" "g")))]
1008: ""
1009: "*
1010: {
1011: if (rtx_equal_p (operands[0], operands[1]))
1012: return \"xorb2 %2,%0\";
1013: if (rtx_equal_p (operands[0], operands[2]))
1014: return \"xorb2 %1,%0\";
1015: return \"xorb3 %2,%1,%0\";
1016: }")
1017:
1018: (define_insn "negdf2"
1019: [(set (match_operand:DF 0 "general_operand" "=g")
1020: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1021: ""
1022: "mneg%# %1,%0")
1023:
1024: (define_insn "negsf2"
1025: [(set (match_operand:SF 0 "general_operand" "=g")
1026: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1027: ""
1028: "mnegf %1,%0")
1029:
1030: (define_insn "negsi2"
1031: [(set (match_operand:SI 0 "general_operand" "=g")
1032: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1033: ""
1034: "mnegl %1,%0")
1035:
1036: (define_insn "neghi2"
1037: [(set (match_operand:HI 0 "general_operand" "=g")
1038: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1039: ""
1040: "mnegw %1,%0")
1041:
1042: (define_insn "negqi2"
1043: [(set (match_operand:QI 0 "general_operand" "=g")
1044: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1045: ""
1046: "mnegb %1,%0")
1047:
1048: (define_insn "one_cmplsi2"
1049: [(set (match_operand:SI 0 "general_operand" "=g")
1050: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1051: ""
1052: "mcoml %1,%0")
1053:
1054: (define_insn "one_cmplhi2"
1055: [(set (match_operand:HI 0 "general_operand" "=g")
1056: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1057: ""
1058: "mcomw %1,%0")
1059:
1060: (define_insn "one_cmplqi2"
1061: [(set (match_operand:QI 0 "general_operand" "=g")
1062: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1063: ""
1064: "mcomb %1,%0")
1065:
1066: ;; Arithmetic right shift on the vax works by negating the shift count.
1067: (define_expand "ashrsi3"
1068: [(set (match_operand:SI 0 "general_operand" "=g")
1069: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1070: (match_operand:QI 2 "general_operand" "g")))]
1071: ""
1072: "
1073: {
1074: operands[2] = negate_rtx (QImode, operands[2]);
1075: }")
1076:
1077: (define_insn "ashlsi3"
1078: [(set (match_operand:SI 0 "general_operand" "=g")
1079: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1080: (match_operand:QI 2 "general_operand" "g")))]
1081: ""
1082: "*
1083: {
1084: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1085: return \"addl2 %0,%0\";
1086: if (GET_CODE (operands[1]) == REG
1087: && GET_CODE (operands[2]) == CONST_INT)
1088: {
1089: int i = INTVAL (operands[2]);
1090: if (i == 1)
1091: return \"addl3 %1,%1,%0\";
1092: if (i == 2)
1093: return \"moval 0[%1],%0\";
1094: if (i == 3)
1095: return \"movad 0[%1],%0\";
1096: }
1097: return \"ashl %2,%1,%0\";
1098: }")
1099:
1100: ;; Arithmetic right shift on the vax works by negating the shift count.
1101: (define_expand "ashrdi3"
1102: [(set (match_operand:DI 0 "general_operand" "=g")
1103: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1104: (match_operand:QI 2 "general_operand" "g")))]
1105: ""
1106: "
1107: {
1108: operands[2] = negate_rtx (QImode, operands[2]);
1109: }")
1110:
1111: (define_insn "ashldi3"
1112: [(set (match_operand:DI 0 "general_operand" "=g")
1113: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1114: (match_operand:QI 2 "general_operand" "g")))]
1115: ""
1116: "ashq %2,%1,%0")
1117:
1118: ;; Rotate right on the vax works by negating the shift count.
1119: (define_expand "rotrsi3"
1120: [(set (match_operand:SI 0 "general_operand" "=g")
1121: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1122: (match_operand:QI 2 "general_operand" "g")))]
1123: ""
1124: "
1125: {
1126: operands[2] = negate_rtx (QImode, operands[2]);
1127: }")
1128:
1129: (define_insn "rotlsi3"
1130: [(set (match_operand:SI 0 "general_operand" "=g")
1131: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1132: (match_operand:QI 2 "general_operand" "g")))]
1133: ""
1134: "rotl %2,%1,%0")
1135:
1136: ;This insn is probably slower than a multiply and an add.
1137: ;(define_insn ""
1138: ; [(set (match_operand:SI 0 "general_operand" "=g")
1139: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1140: ; (match_operand:SI 2 "general_operand" "g"))
1141: ; (match_operand:SI 3 "general_operand" "g")))]
1142: ; ""
1143: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1144:
1145: ;; Special cases of bit-field insns which we should
1146: ;; recognize in preference to the general case.
1147: ;; These handle aligned 8-bit and 16-bit fields,
1148: ;; which can usually be done with move instructions.
1149:
1150: (define_insn ""
1151: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1152: (match_operand:SI 1 "immediate_operand" "i")
1153: (match_operand:SI 2 "immediate_operand" "i"))
1154: (match_operand:SI 3 "general_operand" "g"))]
1155: "GET_CODE (operands[1]) == CONST_INT
1156: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1157: && GET_CODE (operands[2]) == CONST_INT
1158: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1159: && (GET_CODE (operands[0]) == REG
1160: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1161: "*
1162: {
1163: if (REG_P (operands[0]))
1164: {
1165: if (INTVAL (operands[2]) != 0)
1166: return \"insv %3,%2,%1,%0\";
1167: }
1168: else
1169: operands[0]
1170: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1171:
1172: if (INTVAL (operands[1]) == 8)
1173: return \"movb %3,%0\";
1174: return \"movw %3,%0\";
1175: }")
1176:
1177: (define_insn ""
1178: [(set (match_operand:SI 0 "general_operand" "=&g")
1179: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1180: (match_operand:SI 2 "immediate_operand" "i")
1181: (match_operand:SI 3 "immediate_operand" "i")))]
1182: "GET_CODE (operands[2]) == CONST_INT
1183: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1184: && GET_CODE (operands[3]) == CONST_INT
1185: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1186: && (GET_CODE (operands[1]) == REG
1187: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1188: "*
1189: {
1190: if (REG_P (operands[1]))
1191: {
1192: if (INTVAL (operands[3]) != 0)
1193: return \"extzv %3,%2,%1,%0\";
1194: }
1195: else
1196: operands[1]
1197: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1198:
1199: if (INTVAL (operands[2]) == 8)
1200: return \"movzbl %1,%0\";
1201: return \"movzwl %1,%0\";
1202: }")
1203:
1204: (define_insn ""
1205: [(set (match_operand:SI 0 "general_operand" "=g")
1206: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1207: (match_operand:SI 2 "immediate_operand" "i")
1208: (match_operand:SI 3 "immediate_operand" "i")))]
1209: "GET_CODE (operands[2]) == CONST_INT
1210: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1211: && GET_CODE (operands[3]) == CONST_INT
1212: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1213: && (GET_CODE (operands[1]) == REG
1214: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1215: "*
1216: {
1217: if (REG_P (operands[1]))
1218: {
1219: if (INTVAL (operands[3]) != 0)
1220: return \"extv %3,%2,%1,%0\";
1221: }
1222: else
1223: operands[1]
1224: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1225:
1226: if (INTVAL (operands[2]) == 8)
1227: return \"cvtbl %1,%0\";
1228: return \"cvtwl %1,%0\";
1229: }")
1230:
1231: ;; Register-only SImode cases of bit-field insns.
1232:
1233: (define_insn ""
1234: [(set (cc0)
1235: (compare
1236: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1237: (match_operand:SI 1 "general_operand" "g")
1238: (match_operand:SI 2 "general_operand" "g"))
1239: (match_operand:SI 3 "general_operand" "g")))]
1240: ""
1241: "cmpv %2,%1,%0,%3")
1242:
1243: (define_insn ""
1244: [(set (cc0)
1245: (compare
1246: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1247: (match_operand:SI 1 "general_operand" "g")
1248: (match_operand:SI 2 "general_operand" "g"))
1249: (match_operand:SI 3 "general_operand" "g")))]
1250: ""
1251: "cmpzv %2,%1,%0,%3")
1252:
1253: (define_insn ""
1254: [(set (match_operand:SI 0 "general_operand" "=g")
1255: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1256: (match_operand:SI 2 "general_operand" "g")
1257: (match_operand:SI 3 "general_operand" "g")))]
1258: ""
1259: "extv %3,%2,%1,%0")
1260:
1261: (define_insn ""
1262: [(set (match_operand:SI 0 "general_operand" "=g")
1263: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1264: (match_operand:SI 2 "general_operand" "g")
1265: (match_operand:SI 3 "general_operand" "g")))]
1266: ""
1267: "extzv %3,%2,%1,%0")
1268:
1269: ;; Non-register cases.
1270: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1271: ;; don't match these (and therefore match the cases above instead).
1272:
1273: (define_insn ""
1274: [(set (cc0)
1275: (compare
1276: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1277: (match_operand:SI 1 "general_operand" "g")
1278: (match_operand:SI 2 "general_operand" "g"))
1279: (match_operand:SI 3 "general_operand" "g")))]
1280: ""
1281: "cmpv %2,%1,%0,%3")
1282:
1283: (define_insn ""
1284: [(set (cc0)
1285: (compare
1286: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1287: (match_operand:SI 1 "general_operand" "g")
1288: (match_operand:SI 2 "general_operand" "g"))
1289: (match_operand:SI 3 "general_operand" "g")))]
1290: ""
1291: "cmpzv %2,%1,%0,%3")
1292:
1293: (define_insn "extv"
1294: [(set (match_operand:SI 0 "general_operand" "=g")
1295: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1296: (match_operand:SI 2 "general_operand" "g")
1297: (match_operand:SI 3 "general_operand" "g")))]
1298: ""
1299: "extv %3,%2,%1,%0")
1300:
1301: (define_insn "extzv"
1302: [(set (match_operand:SI 0 "general_operand" "=g")
1303: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1304: (match_operand:SI 2 "general_operand" "g")
1305: (match_operand:SI 3 "general_operand" "g")))]
1306: ""
1307: "extzv %3,%2,%1,%0")
1308:
1309: (define_insn "insv"
1310: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1311: (match_operand:SI 1 "general_operand" "g")
1312: (match_operand:SI 2 "general_operand" "g"))
1313: (match_operand:SI 3 "general_operand" "g"))]
1314: ""
1315: "insv %3,%2,%1,%0")
1316:
1317: (define_insn ""
1318: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1319: (match_operand:SI 1 "general_operand" "g")
1320: (match_operand:SI 2 "general_operand" "g"))
1321: (match_operand:SI 3 "general_operand" "g"))]
1322: ""
1323: "insv %3,%2,%1,%0")
1324:
1325: (define_insn "jump"
1326: [(set (pc)
1327: (label_ref (match_operand 0 "" "")))]
1328: ""
1329: "jbr %l0")
1330:
1331: (define_insn "beq"
1332: [(set (pc)
1333: (if_then_else (eq (cc0)
1334: (const_int 0))
1335: (label_ref (match_operand 0 "" ""))
1336: (pc)))]
1337: ""
1338: "jeql %l0")
1339:
1340: (define_insn "bne"
1341: [(set (pc)
1342: (if_then_else (ne (cc0)
1343: (const_int 0))
1344: (label_ref (match_operand 0 "" ""))
1345: (pc)))]
1346: ""
1347: "jneq %l0")
1348:
1349: (define_insn "bgt"
1350: [(set (pc)
1351: (if_then_else (gt (cc0)
1352: (const_int 0))
1353: (label_ref (match_operand 0 "" ""))
1354: (pc)))]
1355: ""
1356: "jgtr %l0")
1357:
1358: (define_insn "bgtu"
1359: [(set (pc)
1360: (if_then_else (gtu (cc0)
1361: (const_int 0))
1362: (label_ref (match_operand 0 "" ""))
1363: (pc)))]
1364: ""
1365: "jgtru %l0")
1366:
1367: (define_insn "blt"
1368: [(set (pc)
1369: (if_then_else (lt (cc0)
1370: (const_int 0))
1371: (label_ref (match_operand 0 "" ""))
1372: (pc)))]
1373: ""
1374: "jlss %l0")
1375:
1376: (define_insn "bltu"
1377: [(set (pc)
1378: (if_then_else (ltu (cc0)
1379: (const_int 0))
1380: (label_ref (match_operand 0 "" ""))
1381: (pc)))]
1382: ""
1383: "jlssu %l0")
1384:
1385: (define_insn "bge"
1386: [(set (pc)
1387: (if_then_else (ge (cc0)
1388: (const_int 0))
1389: (label_ref (match_operand 0 "" ""))
1390: (pc)))]
1391: ""
1392: "jgeq %l0")
1393:
1394: (define_insn "bgeu"
1395: [(set (pc)
1396: (if_then_else (geu (cc0)
1397: (const_int 0))
1398: (label_ref (match_operand 0 "" ""))
1399: (pc)))]
1400: ""
1401: "jgequ %l0")
1402:
1403: (define_insn "ble"
1404: [(set (pc)
1405: (if_then_else (le (cc0)
1406: (const_int 0))
1407: (label_ref (match_operand 0 "" ""))
1408: (pc)))]
1409: ""
1410: "jleq %l0")
1411:
1412: (define_insn "bleu"
1413: [(set (pc)
1414: (if_then_else (leu (cc0)
1415: (const_int 0))
1416: (label_ref (match_operand 0 "" ""))
1417: (pc)))]
1418: ""
1419: "jlequ %l0")
1420:
1421: (define_insn ""
1422: [(set (pc)
1423: (if_then_else (eq (cc0)
1424: (const_int 0))
1425: (pc)
1426: (label_ref (match_operand 0 "" ""))))]
1427: ""
1428: "jneq %l0")
1429:
1430: (define_insn ""
1431: [(set (pc)
1432: (if_then_else (ne (cc0)
1433: (const_int 0))
1434: (pc)
1435: (label_ref (match_operand 0 "" ""))))]
1436: ""
1437: "jeql %l0")
1438:
1439: (define_insn ""
1440: [(set (pc)
1441: (if_then_else (gt (cc0)
1442: (const_int 0))
1443: (pc)
1444: (label_ref (match_operand 0 "" ""))))]
1445: ""
1446: "jleq %l0")
1447:
1448: (define_insn ""
1449: [(set (pc)
1450: (if_then_else (gtu (cc0)
1451: (const_int 0))
1452: (pc)
1453: (label_ref (match_operand 0 "" ""))))]
1454: ""
1455: "jlequ %l0")
1456:
1457: (define_insn ""
1458: [(set (pc)
1459: (if_then_else (lt (cc0)
1460: (const_int 0))
1461: (pc)
1462: (label_ref (match_operand 0 "" ""))))]
1463: ""
1464: "jgeq %l0")
1465:
1466: (define_insn ""
1467: [(set (pc)
1468: (if_then_else (ltu (cc0)
1469: (const_int 0))
1470: (pc)
1471: (label_ref (match_operand 0 "" ""))))]
1472: ""
1473: "jgequ %l0")
1474:
1475: (define_insn ""
1476: [(set (pc)
1477: (if_then_else (ge (cc0)
1478: (const_int 0))
1479: (pc)
1480: (label_ref (match_operand 0 "" ""))))]
1481: ""
1482: "jlss %l0")
1483:
1484: (define_insn ""
1485: [(set (pc)
1486: (if_then_else (geu (cc0)
1487: (const_int 0))
1488: (pc)
1489: (label_ref (match_operand 0 "" ""))))]
1490: ""
1491: "jlssu %l0")
1492:
1493: (define_insn ""
1494: [(set (pc)
1495: (if_then_else (le (cc0)
1496: (const_int 0))
1497: (pc)
1498: (label_ref (match_operand 0 "" ""))))]
1499: ""
1500: "jgtr %l0")
1501:
1502: (define_insn ""
1503: [(set (pc)
1504: (if_then_else (leu (cc0)
1505: (const_int 0))
1506: (pc)
1507: (label_ref (match_operand 0 "" ""))))]
1508: ""
1509: "jgtru %l0")
1510:
1511: ;; Recognize jlbs and jlbc insns.
1512: ;; These come before the jbc and jbs recognizers so these will be preferred.
1513:
1514: (define_insn ""
1515: [(set (pc)
1516: (if_then_else
1517: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1518: (const_int 1))
1519: (const_int 0))
1520: (label_ref (match_operand 1 "" ""))
1521: (pc)))]
1522: "GET_CODE (operands[0]) != MEM
1523: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1524: "jlbs %0,%l1")
1525:
1526: (define_insn ""
1527: [(set (pc)
1528: (if_then_else
1529: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1530: (const_int 1))
1531: (const_int 0))
1532: (label_ref (match_operand 1 "" ""))
1533: (pc)))]
1534: "GET_CODE (operands[0]) != MEM
1535: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1536: "jlbc %0,%l1")
1537:
1538: (define_insn ""
1539: [(set (pc)
1540: (if_then_else
1541: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1542: (const_int 1))
1543: (const_int 0))
1544: (pc)
1545: (label_ref (match_operand 1 "" ""))))]
1546: "GET_CODE (operands[0]) != MEM
1547: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1548: "jlbc %0,%l1")
1549:
1550: (define_insn ""
1551: [(set (pc)
1552: (if_then_else
1553: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1554: (const_int 1))
1555: (const_int 0))
1556: (pc)
1557: (label_ref (match_operand 1 "" ""))))]
1558: "GET_CODE (operands[0]) != MEM
1559: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1560: "jlbs %0,%l1")
1561:
1562: ;; These four entries allow a jlbc or jlbs to be made
1563: ;; by combination with a bic.
1564: (define_insn ""
1565: [(set (pc)
1566: (if_then_else
1567: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1568: (not:SI (const_int -2)))
1569: (const_int 0))
1570: (label_ref (match_operand 1 "" ""))
1571: (pc)))]
1572: "GET_CODE (operands[0]) != MEM
1573: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1574: "jlbs %0,%l1")
1575:
1576: (define_insn ""
1577: [(set (pc)
1578: (if_then_else
1579: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1580: (not:SI (const_int -2)))
1581: (const_int 0))
1582: (label_ref (match_operand 1 "" ""))
1583: (pc)))]
1584: "GET_CODE (operands[0]) != MEM
1585: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1586: "jlbc %0,%l1")
1587:
1588: (define_insn ""
1589: [(set (pc)
1590: (if_then_else
1591: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1592: (not:SI (const_int -2)))
1593: (const_int 0))
1594: (pc)
1595: (label_ref (match_operand 1 "" ""))))]
1596: "GET_CODE (operands[0]) != MEM
1597: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1598: "jlbc %0,%l1")
1599:
1600: (define_insn ""
1601: [(set (pc)
1602: (if_then_else
1603: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1604: (not:SI (const_int -2)))
1605: (const_int 0))
1606: (pc)
1607: (label_ref (match_operand 1 "" ""))))]
1608: "GET_CODE (operands[0]) != MEM
1609: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1610: "jlbs %0,%l1")
1611:
1612: ;; Recognize jbs and jbc instructions.
1613:
1614: (define_insn ""
1615: [(set (pc)
1616: (if_then_else
1617: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1618: (const_int 1)
1619: (match_operand:SI 1 "general_operand" "g"))
1620: (const_int 0))
1621: (label_ref (match_operand 2 "" ""))
1622: (pc)))]
1623: ""
1624: "jbs %1,%0,%l2")
1625:
1626: (define_insn ""
1627: [(set (pc)
1628: (if_then_else
1629: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1630: (const_int 1)
1631: (match_operand:SI 1 "general_operand" "g"))
1632: (const_int 0))
1633: (label_ref (match_operand 2 "" ""))
1634: (pc)))]
1635: ""
1636: "jbc %1,%0,%l2")
1637:
1638: (define_insn ""
1639: [(set (pc)
1640: (if_then_else
1641: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1642: (const_int 1)
1643: (match_operand:SI 1 "general_operand" "g"))
1644: (const_int 0))
1645: (pc)
1646: (label_ref (match_operand 2 "" ""))))]
1647: ""
1648: "jbc %1,%0,%l2")
1649:
1650: (define_insn ""
1651: [(set (pc)
1652: (if_then_else
1653: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1654: (const_int 1)
1655: (match_operand:SI 1 "general_operand" "g"))
1656: (const_int 0))
1657: (pc)
1658: (label_ref (match_operand 2 "" ""))))]
1659: ""
1660: "jbs %1,%0,%l2")
1661:
1662: (define_insn ""
1663: [(set (pc)
1664: (if_then_else
1665: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1666: (const_int 1)
1667: (match_operand:SI 1 "general_operand" "g"))
1668: (const_int 0))
1669: (label_ref (match_operand 2 "" ""))
1670: (pc)))]
1671: "GET_CODE (operands[0]) != MEM
1672: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1673: "jbs %1,%0,%l2")
1674:
1675: (define_insn ""
1676: [(set (pc)
1677: (if_then_else
1678: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1679: (const_int 1)
1680: (match_operand:SI 1 "general_operand" "g"))
1681: (const_int 0))
1682: (label_ref (match_operand 2 "" ""))
1683: (pc)))]
1684: "GET_CODE (operands[0]) != MEM
1685: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1686: "jbc %1,%0,%l2")
1687:
1688: (define_insn ""
1689: [(set (pc)
1690: (if_then_else
1691: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1692: (match_operand:SI 1 "general_operand" "g"))
1693: (const_int 0))
1694: (pc)
1695: (label_ref (match_operand 2 "" ""))))]
1696: "GET_CODE (operands[1]) == CONST_INT
1697: && exact_log2 (INTVAL (operands[1])) >= 0
1698: && (GET_CODE (operands[0]) != MEM
1699: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1700: "*
1701: {
1702: operands[1]
1703: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1704: return \"jbs %1,%0,%l2\";
1705: }")
1706:
1707: (define_insn ""
1708: [(set (pc)
1709: (if_then_else
1710: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1711: (match_operand:SI 1 "general_operand" "g"))
1712: (const_int 0))
1713: (label_ref (match_operand 2 "" ""))
1714: (pc)))]
1715: "GET_CODE (operands[1]) == CONST_INT
1716: && exact_log2 (INTVAL (operands[1])) >= 0
1717: && (GET_CODE (operands[0]) != MEM
1718: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1719: "*
1720: {
1721: operands[1]
1722: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1723: return \"jbc %1,%0,%l2\";
1724: }")
1725:
1726: (define_insn ""
1727: [(set (pc)
1728: (if_then_else
1729: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1730: (match_operand:SI 1 "general_operand" "g"))
1731: (const_int 0))
1732: (pc)
1733: (label_ref (match_operand 2 "" ""))))]
1734: "GET_CODE (operands[1]) == CONST_INT
1735: && exact_log2 (INTVAL (operands[1])) >= 0
1736: && (GET_CODE (operands[0]) != MEM
1737: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1738: "*
1739: {
1740: operands[1]
1741: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1742: return \"jbc %1,%0,%l2\";
1743: }")
1744:
1745: (define_insn ""
1746: [(set (pc)
1747: (if_then_else
1748: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1749: (match_operand:SI 1 "general_operand" "g"))
1750: (const_int 0))
1751: (label_ref (match_operand 2 "" ""))
1752: (pc)))]
1753: "GET_CODE (operands[1]) == CONST_INT
1754: && exact_log2 (INTVAL (operands[1])) >= 0
1755: && (GET_CODE (operands[0]) != MEM
1756: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1757: "*
1758: {
1759: operands[1]
1760: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1761: return \"jbs %1,%0,%l2\";
1762: }")
1763:
1764: (define_insn ""
1765: [(set (pc)
1766: (if_then_else
1767: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1768: (const_int 1)
1769: (match_operand:SI 1 "general_operand" "g"))
1770: (const_int 0))
1771: (pc)
1772: (label_ref (match_operand 2 "" ""))))]
1773: "GET_CODE (operands[0]) != MEM
1774: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1775: "jbc %1,%0,%l2")
1776:
1777: (define_insn ""
1778: [(set (pc)
1779: (if_then_else
1780: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1781: (const_int 1)
1782: (match_operand:SI 1 "general_operand" "g"))
1783: (const_int 0))
1784: (pc)
1785: (label_ref (match_operand 2 "" ""))))]
1786: "GET_CODE (operands[0]) != MEM
1787: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1788: "jbs %1,%0,%l2")
1789:
1790: ;; Subtract-and-jump and Add-and-jump insns.
1791: ;; These are not used when output is for the Unix assembler
1792: ;; because it does not know how to modify them to reach far.
1793:
1794: ;; Normal sob insns.
1795:
1796: (define_insn ""
1797: [(set (pc)
1798: (if_then_else
1799: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1800: (const_int -1))
1801: (const_int 0))
1802: (label_ref (match_operand 1 "" ""))
1803: (pc)))
1804: (set (match_dup 0)
1805: (plus:SI (match_dup 0)
1806: (const_int -1)))]
1807: "!TARGET_UNIX_ASM"
1808: "jsobgtr %0,%l1")
1809:
1810: (define_insn ""
1811: [(set (pc)
1812: (if_then_else
1813: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1814: (const_int -1))
1815: (const_int 0))
1816: (label_ref (match_operand 1 "" ""))
1817: (pc)))
1818: (set (match_dup 0)
1819: (plus:SI (match_dup 0)
1820: (const_int -1)))]
1821: "!TARGET_UNIX_ASM"
1822: "jsobgeq %0,%l1")
1823:
1824: ;; Reversed sob insns.
1825:
1826: (define_insn ""
1827: [(set (pc)
1828: (if_then_else
1829: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1830: (const_int -1))
1831: (const_int 0))
1832: (pc)
1833: (label_ref (match_operand 1 "" ""))))
1834: (set (match_dup 0)
1835: (plus:SI (match_dup 0)
1836: (const_int -1)))]
1837: "!TARGET_UNIX_ASM"
1838: "jsobgtr %0,%l1")
1839:
1840: (define_insn ""
1841: [(set (pc)
1842: (if_then_else
1843: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1844: (const_int -1))
1845: (const_int 0))
1846: (pc)
1847: (label_ref (match_operand 1 "" ""))))
1848: (set (match_dup 0)
1849: (plus:SI (match_dup 0)
1850: (const_int -1)))]
1851: "!TARGET_UNIX_ASM"
1852: "jsobgeq %0,%l1")
1853:
1854: ;; Normal aob insns.
1855: (define_insn ""
1856: [(set (pc)
1857: (if_then_else
1858: (lt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")
1859: (const_int 1))
1860: (match_operand:SI 1 "general_operand" "g"))
1861: (const_int 0))
1862: (label_ref (match_operand 2 "" ""))
1863: (pc)))
1864: (set (match_dup 0)
1865: (plus:SI (match_dup 0)
1866: (const_int 1)))]
1867: "!TARGET_UNIX_ASM"
1868: "jaoblss %1,%0,%l2")
1869:
1870: (define_insn ""
1871: [(set (pc)
1872: (if_then_else
1873: (le (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")
1874: (const_int 1))
1875: (match_operand:SI 1 "general_operand" "g"))
1876: (const_int 0))
1877: (label_ref (match_operand 2 "" ""))
1878: (pc)))
1879: (set (match_dup 0)
1880: (plus:SI (match_dup 0)
1881: (const_int 1)))]
1882: "!TARGET_UNIX_ASM"
1883: "jaobleq %1,%0,%l2")
1884:
1885: ;; Reverse aob insns.
1886: (define_insn ""
1887: [(set (pc)
1888: (if_then_else
1889: (ge (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")
1890: (const_int 1))
1891: (match_operand:SI 1 "general_operand" "g"))
1892: (const_int 0))
1893: (pc)
1894: (label_ref (match_operand 2 "" ""))))
1895: (set (match_dup 0)
1896: (plus:SI (match_dup 0)
1897: (const_int 1)))]
1898: "!TARGET_UNIX_ASM"
1899: "jaoblss %1,%0,%l2")
1900:
1901: (define_insn ""
1902: [(set (pc)
1903: (if_then_else
1904: (gt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")
1905: (const_int 1))
1906: (match_operand:SI 1 "general_operand" "g"))
1907: (const_int 0))
1908: (pc)
1909: (label_ref (match_operand 2 "" ""))))
1910: (set (match_dup 0)
1911: (plus:SI (match_dup 0)
1912: (const_int 1)))]
1913: "!TARGET_UNIX_ASM"
1914: "jaobleq %1,%0,%l2")
1915:
1916: ;; Something like a sob insn, but compares against -1.
1917: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1918:
1919: (define_insn ""
1920: [(set (pc)
1921: (if_then_else
1922: (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "g")
1923: (const_int -1))
1924: (const_int -1))
1925: (const_int 0))
1926: (label_ref (match_operand 1 "" ""))
1927: (pc)))
1928: (set (match_dup 0)
1929: (plus:SI (match_dup 0)
1930: (const_int -1)))]
1931: ""
1932: "decl %0\;jgequ %l1")
1933:
1934: ;; Note that operand 1 is total size of args, in bytes,
1935: ;; and what the call insn wants is the number of words.
1936: (define_insn "call"
1937: [(call (match_operand:QI 0 "general_operand" "g")
1938: (match_operand:QI 1 "general_operand" "g"))]
1939: ""
1940: "*
1941: if (INTVAL (operands[1]) > 255 * 4)
1942: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1943: return \"calls $0,%0\;addl2 %1,sp\";
1944: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1945: return \"calls %1,%0\";
1946: ")
1947:
1948: (define_insn "call_value"
1949: [(set (match_operand 0 "" "=g")
1950: (call (match_operand:QI 1 "general_operand" "g")
1951: (match_operand:QI 2 "general_operand" "g")))]
1952: ""
1953: "*
1954: if (INTVAL (operands[2]) > 255 * 4)
1955: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1956: return \"calls $0,%1\;addl2 %2,sp\";
1957: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1958: return \"calls %2,%1\";
1959: ")
1960:
1961: (define_insn "return"
1962: [(return)]
1963: ""
1964: "ret")
1965:
1966: (define_insn "nop"
1967: [(const_int 0)]
1968: ""
1969: "nop")
1970:
1971: (define_insn "casesi"
1972: [(set (pc)
1973: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1974: (match_operand:SI 1 "general_operand" "g"))
1975: (match_operand:SI 2 "general_operand" "g"))
1976: (plus:SI (sign_extend:SI
1977: (mem:HI (plus:SI (pc)
1978: (minus:SI (match_dup 0)
1979: (match_dup 1)))))
1980: (label_ref:SI (match_operand 3 "" "")))
1981: (pc)))]
1982: ""
1983: "casel %0,%1,%2")
1984:
1985: ;; This used to arise from the preceding by simplification
1986: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1987: (define_insn ""
1988: [(set (pc)
1989: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1990: (match_operand:SI 1 "general_operand" "g"))
1991: (plus:SI (sign_extend:SI
1992: (mem:HI (plus:SI (pc)
1993: (minus:SI (match_dup 0)
1994: (const_int 0)))))
1995: (label_ref:SI (match_operand 3 "" "")))
1996: (pc)))]
1997: ""
1998: "casel %0,$0,%1")
1999:
2000: ;; This arises from the preceding by simplification if operand 1 is zero.
2001: (define_insn ""
2002: [(set (pc)
2003: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
2004: (match_operand:SI 1 "general_operand" "g"))
2005: (plus:SI (sign_extend:SI
2006: (mem:HI (plus:SI (pc)
2007: (match_dup 0))))
2008: (label_ref:SI (match_operand 3 "" "")))
2009: (pc)))]
2010: ""
2011: "casel %0,$0,%1")
2012:
2013: ;; This arises from casesi if operand 0 is a constant, in range.
2014: (define_insn ""
2015: [(set (pc)
2016: (plus:SI (sign_extend:SI
2017: (mem:HI (plus:SI (pc)
2018: (match_operand:SI 0 "general_operand" "g"))))
2019: (label_ref:SI (match_operand 3 "" ""))))]
2020: ""
2021: "casel %0,$0,%0")
1.1.1.2 root 2022:
2023: ;; This arises from the above if both operands are the same.
2024: (define_insn ""
2025: [(set (pc)
2026: (plus:SI (sign_extend:SI (mem:HI (pc)))
2027: (label_ref:SI (match_operand 3 "" ""))))]
2028: ""
2029: "casel $0,$0,$0")
1.1 root 2030:
2031: ;;- load or push effective address
2032: ;; These come after the move and add/sub patterns
2033: ;; because we don't want pushl $1 turned into pushad 1.
2034: ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2035:
2036: (define_insn ""
2037: [(set (match_operand:SI 0 "general_operand" "=g")
2038: (match_operand:QI 1 "address_operand" "p"))]
2039: ""
2040: "*
2041: {
2042: if (push_operand (operands[0], SImode))
2043: return \"pushab %a1\";
2044: return \"movab %a1,%0\";
2045: }")
2046:
2047: (define_insn ""
2048: [(set (match_operand:SI 0 "general_operand" "=g")
2049: (match_operand:HI 1 "address_operand" "p"))]
2050: ""
2051: "*
2052: {
2053: if (push_operand (operands[0], SImode))
2054: return \"pushaw %a1\";
2055: return \"movaw %a1,%0\";
2056: }")
2057:
2058: (define_insn ""
2059: [(set (match_operand:SI 0 "general_operand" "=g")
2060: (match_operand:SI 1 "address_operand" "p"))]
2061: ""
2062: "*
2063: {
2064: if (push_operand (operands[0], SImode))
2065: return \"pushal %a1\";
2066: return \"moval %a1,%0\";
2067: }")
2068:
2069: (define_insn ""
2070: [(set (match_operand:SI 0 "general_operand" "=g")
2071: (match_operand:SF 1 "address_operand" "p"))]
2072: ""
2073: "*
2074: {
2075: if (push_operand (operands[0], SImode))
2076: return \"pushaf %a1\";
2077: return \"movaf %a1,%0\";
2078: }")
2079:
2080: (define_insn ""
2081: [(set (match_operand:SI 0 "general_operand" "=g")
2082: (match_operand:DF 1 "address_operand" "p"))]
2083: ""
2084: "*
2085: {
2086: if (push_operand (operands[0], SImode))
2087: return \"pushad %a1\";
2088: return \"movad %a1,%0\";
2089: }")
2090:
2091: ;; Optimize extzv ...,z; andl2 ...,z
2092: ;; with other operands constant.
2093: (define_peephole
2094: [(set (match_operand:SI 0 "general_operand" "g")
2095: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
2096: (match_operand:SI 2 "general_operand" "g")
2097: (match_operand:SI 3 "general_operand" "g")))
2098: (set (match_operand:SI 4 "general_operand" "g")
2099: (and:SI (match_dup 0)
2100: (match_operand:SI 5 "general_operand" "g")))]
2101: "GET_CODE (operands[2]) == CONST_INT
2102: && GET_CODE (operands[3]) == CONST_INT
2103: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
2104: && GET_CODE (operands[5]) == CONST_INT
2105: && dead_or_set_p (insn, operands[0])"
2106: "*
2107: {
2108: unsigned long mask = INTVAL (operands[5]);
2109: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
2110:
2111: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
2112: mask &= ((1 << INTVAL (operands[2])) - 1);
2113:
2114: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2115: if (push_operand (operands[4], SImode))
2116: {
2117: output_asm_insn (\"rotl %3,%1,%0\", operands);
2118: return \"bicl3 %5,%0,%4\";
2119: }
2120: else
2121: {
2122: output_asm_insn (\"rotl %3,%1,%4\", operands);
2123: return \"bicl2 %5,%4\";
2124: }
2125: }")
2126:
2127: ;; Optimize andl3 x,y,z; extzv z,....,z
2128:
2129: (define_peephole
2130: [(set (match_operand:SI 0 "general_operand" "g")
2131: (and:SI (match_operand:SI 1 "general_operand" "g")
2132: (match_operand:SI 2 "general_operand" "g")))
2133: (set (match_operand 3 "general_operand" "g")
2134: (zero_extract:SI (match_dup 0)
2135: (match_operand:SI 4 "general_operand" "g")
2136: (match_operand:SI 5 "general_operand" "g")))]
2137: "GET_CODE (operands[2]) == CONST_INT
2138: && GET_CODE (operands[4]) == CONST_INT
2139: && GET_CODE (operands[5]) == CONST_INT
2140: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
2141: && dead_or_set_p (insn, operands[0])"
2142: "*
2143: {
2144: unsigned long mask = INTVAL (operands[2]);
2145:
2146: mask &= ~((1 << INTVAL (operands[5])) - 1);
2147: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2148:
2149: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
2150:
2151: if (rtx_equal_p (operands[0], operands[1]))
2152: output_asm_insn (\"bicl2 %2,%0\", operands);
2153: else
2154: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
2155: return \"rotl %5,%0,%3\";
2156: }")
2157:
2158: ;;- Local variables:
2159: ;;- mode:emacs-lisp
2160: ;;- comment-start: ";;- "
2161: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2162: ;;- eval: (modify-syntax-entry ?[ "(]")
2163: ;;- eval: (modify-syntax-entry ?] ")[")
2164: ;;- eval: (modify-syntax-entry ?{ "(}")
2165: ;;- eval: (modify-syntax-entry ?} "){")
2166: ;;- End:
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