--- gcc/config/vax/vax.md	2018/04/24 18:10:25	1.1.1.1
+++ gcc/config/vax/vax.md	2018/04/24 18:29:59	1.1.1.3
@@ -1,5 +1,5 @@
 ;;- Machine description for GNU compiler, Vax Version
-;;   Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
+;;   Copyright (C) 1987, 1988, 1991, 1994, 1995 Free Software Foundation, Inc.
 
 ;; This file is part of GNU CC.
 
@@ -15,7 +15,8 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 
 ;;- Instruction patterns.  When multiple patterns apply,
@@ -1253,6 +1254,26 @@
   ""
   "ashq %2,%1,%0")
 
+;; We used to have expand_shift handle logical right shifts by using extzv,
+;; but this make it very difficult to do lshrdi3.  Since the VAX is the
+;; only machine with this kludge, it's better to just do this with a
+;; define_expand and remove that case from expand_shift.
+
+(define_expand "lshrsi3"
+  [(set (match_dup 3)
+	(minus:QI (const_int 32)
+		  (match_dup 4)))
+   (set (match_operand:SI 0 "general_operand" "=g")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_dup 3)
+			 (match_operand:SI 2 "register_operand" "g")))]
+  ""
+  "
+{
+  operands[3] = gen_reg_rtx (QImode);
+  operands[4] = gen_lowpart (QImode, operands[2]);
+}")
+
 ;; Rotate right on the vax works by negating the shift count.
 (define_expand "rotrsi3"
   [(set (match_operand:SI 0 "general_operand" "=g")
@@ -1301,7 +1322,7 @@
 ;; which can usually be done with move instructions.
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
 			 (match_operand:QI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "general_operand" "g"))]
@@ -1327,7 +1348,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=&g")
-	(zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
+	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
 			 (match_operand:QI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
@@ -1352,7 +1373,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
+	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
 			 (match_operand:QI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
@@ -1390,7 +1411,7 @@
 (define_insn ""
   [(set (cc0)
 	(compare
-	 (zero_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
+	 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 			  (match_operand:QI 1 "general_operand" "g")
 			  (match_operand:SI 2 "general_operand" "g"))
 	 (match_operand:SI 3 "general_operand" "g")))]
@@ -1399,11 +1420,12 @@
 
 ;; When the field position and size are constant and the destination
 ;; is a register, extv and extzv are much slower than a rotate followed
-;; by a bicl or sign extension.
+;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
+;; anyway, we can't allow immediate values for the primary source operand.
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
+	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "g")))]
   ""
@@ -1420,7 +1442,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
+	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "g")))]
   ""
@@ -1475,6 +1497,7 @@
   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
       || GET_CODE (operands[3]) != CONST_INT
       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
+      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
       || side_effects_p (operands[1])
       || (GET_CODE (operands[1]) == MEM
 	  && mode_dependent_address_p (XEXP (operands[1], 0))))
@@ -1494,6 +1517,7 @@
 {
   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
       || GET_CODE (operands[3]) != CONST_INT
+      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
       || side_effects_p (operands[1])
       || (GET_CODE (operands[1]) == MEM
 	  && mode_dependent_address_p (XEXP (operands[1], 0))))
@@ -1506,7 +1530,7 @@
 }")
 
 (define_insn "insv"
-  [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
+  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+g")
 			 (match_operand:QI 1 "general_operand" "g")
 			 (match_operand:SI 2 "general_operand" "g"))
 	(match_operand:SI 3 "general_operand" "g"))]
@@ -1514,7 +1538,7 @@
   "insv %3,%2,%1,%0")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+r")
 			 (match_operand:QI 1 "general_operand" "g")
 			 (match_operand:SI 2 "general_operand" "g"))
 	(match_operand:SI 3 "general_operand" "g"))]