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1.1 root 1: ;;- Machine description for GNU compiler, Vax Version 1.1.1.2 ! root 2: ;; Copyright (C) 1987, 1988, 1991, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: ;; This file is part of GNU CC. 5: 6: ;; GNU CC is free software; you can redistribute it and/or modify 7: ;; it under the terms of the GNU General Public License as published by 8: ;; the Free Software Foundation; either version 2, or (at your option) 9: ;; any later version. 10: 11: ;; GNU CC is distributed in the hope that it will be useful, 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: ;; GNU General Public License for more details. 15: 16: ;; You should have received a copy of the GNU General Public License 17: ;; along with GNU CC; see the file COPYING. If not, write to 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 19: 20: 21: ;;- Instruction patterns. When multiple patterns apply, 22: ;;- the first one in the file is chosen. 23: ;;- 24: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 25: ;;- 26: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 27: ;;- updates for most instructions. 28: 29: ;; We don't want to allow a constant operand for test insns because 30: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 31: ;; be folded while optimizing anyway. 32: 33: (define_insn "tstsi" 34: [(set (cc0) 35: (match_operand:SI 0 "nonimmediate_operand" "g"))] 36: "" 37: "tstl %0") 38: 39: (define_insn "tsthi" 40: [(set (cc0) 41: (match_operand:HI 0 "nonimmediate_operand" "g"))] 42: "" 43: "tstw %0") 44: 45: (define_insn "tstqi" 46: [(set (cc0) 47: (match_operand:QI 0 "nonimmediate_operand" "g"))] 48: "" 49: "tstb %0") 50: 51: (define_insn "tstdf" 52: [(set (cc0) 53: (match_operand:DF 0 "general_operand" "gF"))] 54: "" 55: "tst%# %0") 56: 57: (define_insn "tstsf" 58: [(set (cc0) 59: (match_operand:SF 0 "general_operand" "gF"))] 60: "" 61: "tstf %0") 62: 63: (define_insn "cmpsi" 64: [(set (cc0) 65: (compare (match_operand:SI 0 "nonimmediate_operand" "g") 66: (match_operand:SI 1 "general_operand" "g")))] 67: "" 68: "cmpl %0,%1") 69: 70: (define_insn "cmphi" 71: [(set (cc0) 72: (compare (match_operand:HI 0 "nonimmediate_operand" "g") 73: (match_operand:HI 1 "general_operand" "g")))] 74: "" 75: "cmpw %0,%1") 76: 77: (define_insn "cmpqi" 78: [(set (cc0) 79: (compare (match_operand:QI 0 "nonimmediate_operand" "g") 80: (match_operand:QI 1 "general_operand" "g")))] 81: "" 82: "cmpb %0,%1") 83: 84: (define_insn "cmpdf" 85: [(set (cc0) 86: (compare (match_operand:DF 0 "general_operand" "gF,gF") 87: (match_operand:DF 1 "general_operand" "G,gF")))] 88: "" 89: "@ 90: tst%# %0 91: cmp%# %0,%1") 92: 93: (define_insn "cmpsf" 94: [(set (cc0) 95: (compare (match_operand:SF 0 "general_operand" "gF,gF") 96: (match_operand:SF 1 "general_operand" "G,gF")))] 97: "" 98: "@ 99: tstf %0 100: cmpf %0,%1") 101: 102: (define_insn "" 103: [(set (cc0) 104: (and:SI (match_operand:SI 0 "general_operand" "g") 105: (match_operand:SI 1 "general_operand" "g")))] 106: "" 107: "bitl %0,%1") 108: 109: (define_insn "" 110: [(set (cc0) 111: (and:HI (match_operand:HI 0 "general_operand" "g") 112: (match_operand:HI 1 "general_operand" "g")))] 113: "" 114: "bitw %0,%1") 115: 116: (define_insn "" 117: [(set (cc0) 118: (and:QI (match_operand:QI 0 "general_operand" "g") 119: (match_operand:QI 1 "general_operand" "g")))] 120: "" 121: "bitb %0,%1") 122: 123: ;; The vax has no sltu or sgeu patterns, but does have two-operand 124: ;; add/subtract with carry. This is still better than the alternative. 125: ;; Since the cc0-using insn cannot be separated from the cc0-setting insn, 126: ;; and the two are created independently, we can't just use a define_expand 127: ;; to try to optimize this. (The "movl" and "clrl" insns alter the cc0 128: ;; flags, but leave the carry flag alone, but that can't easily be expressed.) 129: ;; 130: ;; Several two-operator combinations could be added to make slightly more 131: ;; optimal code, but they'd have to cover all combinations of plus and minus 132: ;; using match_dup. If you want to do this, I'd suggest changing the "sgeu" 133: ;; pattern to something like (minus (const_int 1) (ltu ...)), so fewer 134: ;; patterns need to be recognized. 135: ;; -- Ken Raeburn ([email protected]) 24 August 1991. 136: 137: (define_insn "sltu" 138: [(set (match_operand:SI 0 "general_operand" "=ro") 139: (ltu (cc0) (const_int 0)))] 140: "" 141: "clrl %0\;adwc $0,%0") 142: 143: (define_insn "sgeu" 144: [(set (match_operand:SI 0 "general_operand" "=ro") 145: (geu (cc0) (const_int 0)))] 146: "" 147: "movl $1,%0\;sbwc $0,%0") 148: 149: (define_insn "movdf" 150: [(set (match_operand:DF 0 "general_operand" "=g,g") 151: (match_operand:DF 1 "general_operand" "G,gF"))] 152: "" 153: "@ 154: clr%# %0 155: mov%# %1,%0") 156: 157: (define_insn "movsf" 158: [(set (match_operand:SF 0 "general_operand" "=g,g") 159: (match_operand:SF 1 "general_operand" "G,gF"))] 160: "" 161: "@ 162: clrf %0 163: movf %1,%0") 164: 165: ;; Some vaxes don't support this instruction. 166: ;;(define_insn "movti" 167: ;; [(set (match_operand:TI 0 "general_operand" "=g") 168: ;; (match_operand:TI 1 "general_operand" "g"))] 169: ;; "" 170: ;; "movh %1,%0") 171: 172: (define_insn "movdi" 173: [(set (match_operand:DI 0 "general_operand" "=g,g") 174: (match_operand:DI 1 "general_operand" "I,g"))] 175: "" 176: "@ 177: clrq %0 178: movq %D1,%0") 179: 180: ;; The VAX move instructions have space-time tradeoffs. On a microVAX 181: ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl 182: ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles 183: ;; if the constant is smaller than 4 bytes, 3 cycles for a longword 184: ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster 185: ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt 186: ;; instructions take 4 cycles. inc takes 3 cycles. The machine description 187: ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl 188: ;; instead of movl). 189: 190: ;; Cycle counts for other models may vary (on a VAX 750 they are similar, 191: ;; but on a VAX 9000 most move and add instructions with one constant 192: ;; operand take 1 cycle). 193: 194: ;; Loads of constants between 64 and 128 used to be done with 195: ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space. 196: 197: (define_insn "movsi" 198: [(set (match_operand:SI 0 "general_operand" "=g") 199: (match_operand:SI 1 "general_operand" "g"))] 200: "" 201: "* 202: { 203: rtx link; 204: if (operands[1] == const1_rtx 205: && (link = find_reg_note (insn, REG_WAS_0, 0)) 206: /* Make sure the insn that stored the 0 is still present. */ 207: && ! INSN_DELETED_P (XEXP (link, 0)) 208: && GET_CODE (XEXP (link, 0)) != NOTE 209: /* Make sure cross jumping didn't happen here. */ 210: && no_labels_between_p (XEXP (link, 0), insn) 211: /* Make sure the reg hasn't been clobbered. */ 212: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 213: return \"incl %0\"; 214: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) 215: { 216: if (push_operand (operands[0], SImode)) 217: return \"pushab %a1\"; 218: return \"movab %a1,%0\"; 219: } 220: if (operands[1] == const0_rtx) 221: return \"clrl %0\"; 222: if (GET_CODE (operands[1]) == CONST_INT 223: && (unsigned) INTVAL (operands[1]) >= 64) 224: { 225: int i = INTVAL (operands[1]); 226: if ((unsigned)(~i) < 64) 227: return \"mcoml %N1,%0\"; 228: if ((unsigned)i < 0x100) 229: return \"movzbl %1,%0\"; 230: if (i >= -0x80 && i < 0) 231: return \"cvtbl %1,%0\"; 232: if ((unsigned)i < 0x10000) 233: return \"movzwl %1,%0\"; 234: if (i >= -0x8000 && i < 0) 235: return \"cvtwl %1,%0\"; 236: } 237: if (push_operand (operands[0], SImode)) 238: return \"pushl %1\"; 239: return \"movl %1,%0\"; 240: }") 241: 242: (define_insn "movhi" 243: [(set (match_operand:HI 0 "general_operand" "=g") 244: (match_operand:HI 1 "general_operand" "g"))] 245: "" 246: "* 247: { 248: rtx link; 249: if (operands[1] == const1_rtx 250: && (link = find_reg_note (insn, REG_WAS_0, 0)) 251: /* Make sure the insn that stored the 0 is still present. */ 252: && ! INSN_DELETED_P (XEXP (link, 0)) 253: && GET_CODE (XEXP (link, 0)) != NOTE 254: /* Make sure cross jumping didn't happen here. */ 255: && no_labels_between_p (XEXP (link, 0), insn) 256: /* Make sure the reg hasn't been clobbered. */ 257: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 258: return \"incw %0\"; 259: 260: if (GET_CODE (operands[1]) == CONST_INT) 261: { 262: int i = INTVAL (operands[1]); 263: if (i == 0) 264: return \"clrw %0\"; 265: else if ((unsigned int)i < 64) 266: return \"movw %1,%0\"; 267: else if ((unsigned int)~i < 64) 268: return \"mcomw %H1,%0\"; 269: else if ((unsigned int)i < 256) 270: return \"movzbw %1,%0\"; 271: } 272: return \"movw %1,%0\"; 273: }") 274: 275: (define_insn "movstricthi" 276: [(set (strict_low_part (match_operand:HI 0 "register_operand" "=g")) 277: (match_operand:HI 1 "general_operand" "g"))] 278: "" 279: "* 280: { 281: if (GET_CODE (operands[1]) == CONST_INT) 282: { 283: int i = INTVAL (operands[1]); 284: if (i == 0) 285: return \"clrw %0\"; 286: else if ((unsigned int)i < 64) 287: return \"movw %1,%0\"; 288: else if ((unsigned int)~i < 64) 289: return \"mcomw %H1,%0\"; 290: else if ((unsigned int)i < 256) 291: return \"movzbw %1,%0\"; 292: } 293: return \"movw %1,%0\"; 294: }") 295: 296: (define_insn "movqi" 297: [(set (match_operand:QI 0 "general_operand" "=g") 298: (match_operand:QI 1 "general_operand" "g"))] 299: "" 300: "* 301: { 302: rtx link; 303: if (operands[1] == const1_rtx 304: && (link = find_reg_note (insn, REG_WAS_0, 0)) 305: /* Make sure the insn that stored the 0 is still present. */ 306: && ! INSN_DELETED_P (XEXP (link, 0)) 307: && GET_CODE (XEXP (link, 0)) != NOTE 308: /* Make sure cross jumping didn't happen here. */ 309: && no_labels_between_p (XEXP (link, 0), insn) 310: /* Make sure the reg hasn't been clobbered. */ 311: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) 312: return \"incb %0\"; 313: 314: if (GET_CODE (operands[1]) == CONST_INT) 315: { 316: int i = INTVAL (operands[1]); 317: if (i == 0) 318: return \"clrb %0\"; 319: else if ((unsigned int)~i < 64) 320: return \"mcomb %B1,%0\"; 321: } 322: return \"movb %1,%0\"; 323: }") 324: 325: (define_insn "movstrictqi" 326: [(set (strict_low_part (match_operand:QI 0 "register_operand" "=g")) 327: (match_operand:QI 1 "general_operand" "g"))] 328: "" 329: "* 330: { 331: if (GET_CODE (operands[1]) == CONST_INT) 332: { 333: int i = INTVAL (operands[1]); 334: if (i == 0) 335: return \"clrb %0\"; 336: else if ((unsigned int)~i < 64) 337: return \"mcomb %B1,%0\"; 338: } 339: return \"movb %1,%0\"; 340: }") 341: 342: ;; This is here to accept 4 arguments and pass the first 3 along 343: ;; to the movstrhi1 pattern that really does the work. 344: (define_expand "movstrhi" 345: [(set (match_operand:BLK 0 "general_operand" "=g") 346: (match_operand:BLK 1 "general_operand" "g")) 347: (use (match_operand:HI 2 "general_operand" "g")) 348: (match_operand 3 "" "")] 349: "" 350: " 351: emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2])); 352: DONE; 353: ") 354: 355: ;; The definition of this insn does not really explain what it does, 356: ;; but it should suffice 357: ;; that anything generated as this insn will be recognized as one 358: ;; and that it won't successfully combine with anything. 359: (define_insn "movstrhi1" 360: [(set (match_operand:BLK 0 "general_operand" "=g") 361: (match_operand:BLK 1 "general_operand" "g")) 362: (use (match_operand:HI 2 "general_operand" "g")) 363: (clobber (reg:SI 0)) 364: (clobber (reg:SI 1)) 365: (clobber (reg:SI 2)) 366: (clobber (reg:SI 3)) 367: (clobber (reg:SI 4)) 368: (clobber (reg:SI 5))] 369: "" 370: "movc3 %2,%1,%0") 371: 372: ;; Extension and truncation insns. 373: 374: (define_insn "truncsiqi2" 375: [(set (match_operand:QI 0 "general_operand" "=g") 376: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))] 377: "" 378: "cvtlb %1,%0") 379: 380: (define_insn "truncsihi2" 381: [(set (match_operand:HI 0 "general_operand" "=g") 382: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))] 383: "" 384: "cvtlw %1,%0") 385: 386: (define_insn "trunchiqi2" 387: [(set (match_operand:QI 0 "general_operand" "=g") 388: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] 389: "" 390: "cvtwb %1,%0") 391: 392: (define_insn "extendhisi2" 393: [(set (match_operand:SI 0 "general_operand" "=g") 394: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 395: "" 396: "cvtwl %1,%0") 397: 398: (define_insn "extendqihi2" 399: [(set (match_operand:HI 0 "general_operand" "=g") 400: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 401: "" 402: "cvtbw %1,%0") 403: 404: (define_insn "extendqisi2" 405: [(set (match_operand:SI 0 "general_operand" "=g") 406: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 407: "" 408: "cvtbl %1,%0") 409: 410: (define_insn "extendsfdf2" 411: [(set (match_operand:DF 0 "general_operand" "=g") 412: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] 413: "" 414: "cvtf%# %1,%0") 415: 416: (define_insn "truncdfsf2" 417: [(set (match_operand:SF 0 "general_operand" "=g") 418: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] 419: "" 420: "cvt%#f %1,%0") 421: 422: (define_insn "zero_extendhisi2" 423: [(set (match_operand:SI 0 "general_operand" "=g") 424: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 425: "" 426: "movzwl %1,%0") 427: 428: (define_insn "zero_extendqihi2" 429: [(set (match_operand:HI 0 "general_operand" "=g") 430: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 431: "" 432: "movzbw %1,%0") 433: 434: (define_insn "zero_extendqisi2" 435: [(set (match_operand:SI 0 "general_operand" "=g") 436: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 437: "" 438: "movzbl %1,%0") 439: 440: ;; Fix-to-float conversion insns. 441: 442: (define_insn "floatsisf2" 443: [(set (match_operand:SF 0 "general_operand" "=g") 444: (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))] 445: "" 446: "cvtlf %1,%0") 447: 448: (define_insn "floatsidf2" 449: [(set (match_operand:DF 0 "general_operand" "=g") 450: (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))] 451: "" 452: "cvtl%# %1,%0") 453: 454: (define_insn "floathisf2" 455: [(set (match_operand:SF 0 "general_operand" "=g") 456: (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))] 457: "" 458: "cvtwf %1,%0") 459: 460: (define_insn "floathidf2" 461: [(set (match_operand:DF 0 "general_operand" "=g") 462: (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))] 463: "" 464: "cvtw%# %1,%0") 465: 466: (define_insn "floatqisf2" 467: [(set (match_operand:SF 0 "general_operand" "=g") 468: (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))] 469: "" 470: "cvtbf %1,%0") 471: 472: (define_insn "floatqidf2" 473: [(set (match_operand:DF 0 "general_operand" "=g") 474: (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))] 475: "" 476: "cvtb%# %1,%0") 477: 478: ;; Float-to-fix conversion insns. 479: 480: (define_insn "fix_truncsfqi2" 481: [(set (match_operand:QI 0 "general_operand" "=g") 482: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 483: "" 484: "cvtfb %1,%0") 485: 486: (define_insn "fix_truncsfhi2" 487: [(set (match_operand:HI 0 "general_operand" "=g") 488: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 489: "" 490: "cvtfw %1,%0") 491: 492: (define_insn "fix_truncsfsi2" 493: [(set (match_operand:SI 0 "general_operand" "=g") 494: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 495: "" 496: "cvtfl %1,%0") 497: 498: (define_insn "fix_truncdfqi2" 499: [(set (match_operand:QI 0 "general_operand" "=g") 500: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 501: "" 502: "cvt%#b %1,%0") 503: 504: (define_insn "fix_truncdfhi2" 505: [(set (match_operand:HI 0 "general_operand" "=g") 506: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 507: "" 508: "cvt%#w %1,%0") 509: 510: (define_insn "fix_truncdfsi2" 511: [(set (match_operand:SI 0 "general_operand" "=g") 512: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 513: "" 514: "cvt%#l %1,%0") 515: 516: ;;- All kinds of add instructions. 517: 518: (define_insn "adddf3" 519: [(set (match_operand:DF 0 "general_operand" "=g,g,g") 520: (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF") 521: (match_operand:DF 2 "general_operand" "gF,0,gF")))] 522: "" 523: "@ 524: add%#2 %2,%0 525: add%#2 %1,%0 526: add%#3 %1,%2,%0") 527: 528: (define_insn "addsf3" 529: [(set (match_operand:SF 0 "general_operand" "=g,g,g") 530: (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF") 531: (match_operand:SF 2 "general_operand" "gF,0,gF")))] 532: "" 533: "@ 534: addf2 %2,%0 535: addf2 %1,%0 536: addf3 %1,%2,%0") 537: 538: /* The space-time-opcode tradeoffs for addition vary by model of VAX. 539: 540: On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3", 541: but it not faster on other models. 542: 543: "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is 544: faster on a VAX 3, but some VAXes (e.g. VAX 9000) will stall if 545: a register is used in an address too soon after it is set. 546: Compromise by using movab only when it is shorter than the add 547: or the base register in the address is one of sp, ap, and fp, 548: which are not modified very often. */ 549: 550: 551: (define_insn "addsi3" 552: [(set (match_operand:SI 0 "general_operand" "=g") 553: (plus:SI (match_operand:SI 1 "general_operand" "g") 554: (match_operand:SI 2 "general_operand" "g")))] 555: "" 556: "* 557: { 558: if (rtx_equal_p (operands[0], operands[1])) 559: { 560: if (operands[2] == const1_rtx) 561: return \"incl %0\"; 562: if (operands[2] == constm1_rtx) 563: return \"decl %0\"; 564: if (GET_CODE (operands[2]) == CONST_INT 565: && (unsigned) (- INTVAL (operands[2])) < 64) 566: return \"subl2 $%n2,%0\"; 567: if (GET_CODE (operands[2]) == CONST_INT 568: && (unsigned) INTVAL (operands[2]) >= 64 569: && GET_CODE (operands[1]) == REG 570: && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) 571: || REGNO (operands[1]) > 11)) 572: return \"movab %c2(%1),%0\"; 573: return \"addl2 %2,%0\"; 574: } 575: if (rtx_equal_p (operands[0], operands[2])) 576: return \"addl2 %1,%0\"; 577: 578: if (GET_CODE (operands[2]) == CONST_INT 579: && INTVAL (operands[2]) < 32767 580: && INTVAL (operands[2]) > -32768 581: && GET_CODE (operands[1]) == REG 582: && push_operand (operands[0], SImode)) 583: return \"pushab %c2(%1)\"; 584: 585: if (GET_CODE (operands[2]) == CONST_INT 586: && (unsigned) (- INTVAL (operands[2])) < 64) 587: return \"subl3 $%n2,%1,%0\"; 588: 589: if (GET_CODE (operands[2]) == CONST_INT 590: && (unsigned) INTVAL (operands[2]) >= 64 591: && GET_CODE (operands[1]) == REG 592: && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) 593: || REGNO (operands[1]) > 11)) 594: return \"movab %c2(%1),%0\"; 595: 596: /* Add this if using gcc on a VAX 3xxx: 597: if (REG_P (operands[1]) && REG_P (operands[2])) 598: return \"movab (%1)[%2],%0\"; 599: */ 600: return \"addl3 %1,%2,%0\"; 601: }") 602: 603: (define_insn "addhi3" 604: [(set (match_operand:HI 0 "general_operand" "=g") 605: (plus:HI (match_operand:HI 1 "general_operand" "g") 606: (match_operand:HI 2 "general_operand" "g")))] 607: "" 608: "* 609: { 610: if (rtx_equal_p (operands[0], operands[1])) 611: { 612: if (operands[2] == const1_rtx) 613: return \"incw %0\"; 614: if (operands[2] == constm1_rtx) 615: return \"decw %0\"; 616: if (GET_CODE (operands[2]) == CONST_INT 617: && (unsigned) (- INTVAL (operands[2])) < 64) 618: return \"subw2 $%n2,%0\"; 619: return \"addw2 %2,%0\"; 620: } 621: if (rtx_equal_p (operands[0], operands[2])) 622: return \"addw2 %1,%0\"; 623: if (GET_CODE (operands[2]) == CONST_INT 624: && (unsigned) (- INTVAL (operands[2])) < 64) 625: return \"subw3 $%n2,%1,%0\"; 626: return \"addw3 %1,%2,%0\"; 627: }") 628: 629: (define_insn "addqi3" 630: [(set (match_operand:QI 0 "general_operand" "=g") 631: (plus:QI (match_operand:QI 1 "general_operand" "g") 632: (match_operand:QI 2 "general_operand" "g")))] 633: "" 634: "* 635: { 636: if (rtx_equal_p (operands[0], operands[1])) 637: { 638: if (operands[2] == const1_rtx) 639: return \"incb %0\"; 640: if (operands[2] == constm1_rtx) 641: return \"decb %0\"; 642: if (GET_CODE (operands[2]) == CONST_INT 643: && (unsigned) (- INTVAL (operands[2])) < 64) 644: return \"subb2 $%n2,%0\"; 645: return \"addb2 %2,%0\"; 646: } 647: if (rtx_equal_p (operands[0], operands[2])) 648: return \"addb2 %1,%0\"; 649: if (GET_CODE (operands[2]) == CONST_INT 650: && (unsigned) (- INTVAL (operands[2])) < 64) 651: return \"subb3 $%n2,%1,%0\"; 652: return \"addb3 %1,%2,%0\"; 653: }") 654: 655: ;; The add-with-carry (adwc) instruction only accepts two operands. 656: (define_insn "adddi3" 657: [(set (match_operand:DI 0 "general_operand" "=ro>,ro>") 658: (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 659: (match_operand:DI 2 "general_operand" "Fro,F")))] 660: "" 661: "* 662: { 663: rtx low[3]; 664: char *pattern; 665: int carry = 1; 666: 667: split_quadword_operands (operands, low, 3); 668: /* Add low parts. */ 669: if (rtx_equal_p (operands[0], operands[1])) 670: { 671: if (low[2] == const0_rtx) 672: /* Should examine operand, punt if not POST_INC. */ 673: pattern = \"tstl %0\", carry = 0; 674: else if (low[2] == const1_rtx) 675: pattern = \"incl %0\"; 676: else 677: pattern = \"addl2 %2,%0\"; 678: } 679: else 680: { 681: if (low[2] == const0_rtx) 682: pattern = \"movl %1,%0\", carry = 0; 683: else 684: pattern = \"addl3 %2,%1,%0\"; 685: } 686: if (pattern) 687: output_asm_insn (pattern, low); 688: if (!carry) 689: /* If CARRY is 0, we don't have any carry value to worry about. */ 690: return OUT_FCN (CODE_FOR_addsi3) (operands, insn); 691: /* %0 = C + %1 + %2 */ 692: if (!rtx_equal_p (operands[0], operands[1])) 693: output_asm_insn ((operands[1] == const0_rtx 694: ? \"clrl %0\" 695: : \"movl %1,%0\"), operands); 696: return \"adwc %2,%0\"; 697: }") 698: 699: ;;- All kinds of subtract instructions. 700: 701: (define_insn "subdf3" 702: [(set (match_operand:DF 0 "general_operand" "=g,g") 703: (minus:DF (match_operand:DF 1 "general_operand" "0,gF") 704: (match_operand:DF 2 "general_operand" "gF,gF")))] 705: "" 706: "@ 707: sub%#2 %2,%0 708: sub%#3 %2,%1,%0") 709: 710: (define_insn "subsf3" 711: [(set (match_operand:SF 0 "general_operand" "=g,g") 712: (minus:SF (match_operand:SF 1 "general_operand" "0,gF") 713: (match_operand:SF 2 "general_operand" "gF,gF")))] 714: "" 715: "@ 716: subf2 %2,%0 717: subf3 %2,%1,%0") 718: 719: (define_insn "subsi3" 720: [(set (match_operand:SI 0 "general_operand" "=g,g") 721: (minus:SI (match_operand:SI 1 "general_operand" "0,g") 722: (match_operand:SI 2 "general_operand" "g,g")))] 723: "" 724: "@ 725: subl2 %2,%0 726: subl3 %2,%1,%0") 727: 728: (define_insn "subhi3" 729: [(set (match_operand:HI 0 "general_operand" "=g,g") 730: (minus:HI (match_operand:HI 1 "general_operand" "0,g") 731: (match_operand:HI 2 "general_operand" "g,g")))] 732: "" 733: "@ 734: subw2 %2,%0 735: subw3 %2,%1,%0") 736: 737: (define_insn "subqi3" 738: [(set (match_operand:QI 0 "general_operand" "=g,g") 739: (minus:QI (match_operand:QI 1 "general_operand" "0,g") 740: (match_operand:QI 2 "general_operand" "g,g")))] 741: "" 742: "@ 743: subb2 %2,%0 744: subb3 %2,%1,%0") 745: 746: ;; The subtract-with-carry (sbwc) instruction only takes two operands. 747: (define_insn "subdi3" 748: [(set (match_operand:DI 0 "general_operand" "=or>,or>") 749: (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 750: (match_operand:DI 2 "general_operand" "For,F")))] 751: "" 752: "* 753: { 754: rtx low[3]; 755: char *pattern; 756: int carry = 1; 757: 758: split_quadword_operands (operands, low, 3); 759: /* Subtract low parts. */ 760: if (rtx_equal_p (operands[0], operands[1])) 761: { 762: if (low[2] == const0_rtx) 763: pattern = 0, carry = 0; 764: else if (low[2] == constm1_rtx) 765: pattern = \"decl %0\"; 766: else 767: pattern = \"subl2 %2,%0\"; 768: } 769: else 770: { 771: if (low[2] == constm1_rtx) 772: pattern = \"decl %0\"; 773: else if (low[2] == const0_rtx) 774: pattern = OUT_FCN (CODE_FOR_movsi) (low, insn), carry = 0; 775: else 776: pattern = \"subl3 %2,%1,%0\"; 777: } 778: if (pattern) 779: output_asm_insn (pattern, low); 780: if (carry) 781: { 782: if (!rtx_equal_p (operands[0], operands[1])) 783: return \"movl %1,%0\;sbwc %2,%0\"; 784: return \"sbwc %2,%0\"; 785: /* %0 = %2 - %1 - C */ 786: } 787: return OUT_FCN (CODE_FOR_subsi3) (operands, insn); 788: }") 789: 790: ;;- Multiply instructions. 791: 792: (define_insn "muldf3" 793: [(set (match_operand:DF 0 "general_operand" "=g,g,g") 794: (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF") 795: (match_operand:DF 2 "general_operand" "gF,0,gF")))] 796: "" 797: "@ 798: mul%#2 %2,%0 799: mul%#2 %1,%0 800: mul%#3 %1,%2,%0") 801: 802: (define_insn "mulsf3" 803: [(set (match_operand:SF 0 "general_operand" "=g,g,g") 804: (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF") 805: (match_operand:SF 2 "general_operand" "gF,0,gF")))] 806: "" 807: "@ 808: mulf2 %2,%0 809: mulf2 %1,%0 810: mulf3 %1,%2,%0") 811: 812: (define_insn "mulsi3" 813: [(set (match_operand:SI 0 "general_operand" "=g,g,g") 814: (mult:SI (match_operand:SI 1 "general_operand" "0,g,g") 815: (match_operand:SI 2 "general_operand" "g,0,g")))] 816: "" 817: "@ 818: mull2 %2,%0 819: mull2 %1,%0 820: mull3 %1,%2,%0") 821: 822: (define_insn "mulhi3" 823: [(set (match_operand:HI 0 "general_operand" "=g,g,") 824: (mult:HI (match_operand:HI 1 "general_operand" "0,g,g") 825: (match_operand:HI 2 "general_operand" "g,0,g")))] 826: "" 827: "@ 828: mulw2 %2,%0 829: mulw2 %1,%0 830: mulw3 %1,%2,%0") 831: 832: (define_insn "mulqi3" 833: [(set (match_operand:QI 0 "general_operand" "=g,g,g") 834: (mult:QI (match_operand:QI 1 "general_operand" "0,g,g") 835: (match_operand:QI 2 "general_operand" "g,0,g")))] 836: "" 837: "@ 838: mulb2 %2,%0 839: mulb2 %1,%0 840: mulb3 %1,%2,%0") 841: 842: (define_insn "mulsidi3" 843: [(set (match_operand:DI 0 "general_operand" "=g") 844: (mult:DI (sign_extend:DI 845: (match_operand:SI 1 "nonimmediate_operand" "g")) 846: (sign_extend:DI 847: (match_operand:SI 2 "nonimmediate_operand" "g"))))] 848: "" 849: "emul %1,%2,$0,%0") 850: 851: (define_insn "" 852: [(set (match_operand:DI 0 "general_operand" "=g") 853: (plus:DI 854: (mult:DI (sign_extend:DI 855: (match_operand:SI 1 "nonimmediate_operand" "g")) 856: (sign_extend:DI 857: (match_operand:SI 2 "nonimmediate_operand" "g"))) 858: (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))] 859: "" 860: "emul %1,%2,%3,%0") 861: 862: ;; 'F' constraint means type CONST_DOUBLE 863: (define_insn "" 864: [(set (match_operand:DI 0 "general_operand" "=g") 865: (plus:DI 866: (mult:DI (sign_extend:DI 867: (match_operand:SI 1 "nonimmediate_operand" "g")) 868: (sign_extend:DI 869: (match_operand:SI 2 "nonimmediate_operand" "g"))) 870: (match_operand:DI 3 "immediate_operand" "F")))] 871: "GET_CODE (operands[3]) == CONST_DOUBLE 872: && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)" 873: "* 874: { 875: if (CONST_DOUBLE_HIGH (operands[3])) 876: operands[3] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[3])); 877: return \"emul %1,%2,%3,%0\"; 878: }") 879: 880: ;;- Divide instructions. 881: 882: (define_insn "divdf3" 883: [(set (match_operand:DF 0 "general_operand" "=g,g") 884: (div:DF (match_operand:DF 1 "general_operand" "0,gF") 885: (match_operand:DF 2 "general_operand" "gF,gF")))] 886: "" 887: "@ 888: div%#2 %2,%0 889: div%#3 %2,%1,%0") 890: 891: (define_insn "divsf3" 892: [(set (match_operand:SF 0 "general_operand" "=g,g") 893: (div:SF (match_operand:SF 1 "general_operand" "0,gF") 894: (match_operand:SF 2 "general_operand" "gF,gF")))] 895: "" 896: "@ 897: divf2 %2,%0 898: divf3 %2,%1,%0") 899: 900: (define_insn "divsi3" 901: [(set (match_operand:SI 0 "general_operand" "=g,g") 902: (div:SI (match_operand:SI 1 "general_operand" "0,g") 903: (match_operand:SI 2 "general_operand" "g,g")))] 904: "" 905: "@ 906: divl2 %2,%0 907: divl3 %2,%1,%0") 908: 909: (define_insn "divhi3" 910: [(set (match_operand:HI 0 "general_operand" "=g,g") 911: (div:HI (match_operand:HI 1 "general_operand" "0,g") 912: (match_operand:HI 2 "general_operand" "g,g")))] 913: "" 914: "@ 915: divw2 %2,%0 916: divw3 %2,%1,%0") 917: 918: (define_insn "divqi3" 919: [(set (match_operand:QI 0 "general_operand" "=g,g") 920: (div:QI (match_operand:QI 1 "general_operand" "0,g") 921: (match_operand:QI 2 "general_operand" "g,g")))] 922: "" 923: "@ 924: divb2 %2,%0 925: divb3 %2,%1,%0") 926: 927: ;This is left out because it is very slow; 928: ;we are better off programming around the "lack" of this insn. 929: ;(define_insn "divmoddisi4" 930: ; [(set (match_operand:SI 0 "general_operand" "=g") 931: ; (div:SI (match_operand:DI 1 "general_operand" "g") 932: ; (match_operand:SI 2 "general_operand" "g"))) 933: ; (set (match_operand:SI 3 "general_operand" "=g") 934: ; (mod:SI (match_operand:DI 1 "general_operand" "g") 935: ; (match_operand:SI 2 "general_operand" "g")))] 936: ; "" 937: ; "ediv %2,%1,%0,%3") 938: 939: ;; Bit-and on the vax is done with a clear-bits insn. 940: (define_expand "andsi3" 941: [(set (match_operand:SI 0 "general_operand" "=g") 942: (and:SI (not:SI (match_operand:SI 1 "general_operand" "g")) 943: (match_operand:SI 2 "general_operand" "g")))] 944: "" 945: " 946: { 947: rtx op1 = operands[1]; 948: 949: /* If there is a constant argument, complement that one. */ 950: if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT) 951: { 952: operands[1] = operands[2]; 953: operands[2] = op1; 954: op1 = operands[1]; 955: } 956: 957: if (GET_CODE (op1) == CONST_INT) 958: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (op1)); 959: else 960: operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1); 961: }") 962: 963: (define_expand "andhi3" 964: [(set (match_operand:HI 0 "general_operand" "=g") 965: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g")) 966: (match_operand:HI 2 "general_operand" "g")))] 967: "" 968: " 969: { 970: rtx op1 = operands[1]; 971: 972: if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT) 973: { 974: operands[1] = operands[2]; 975: operands[2] = op1; 976: op1 = operands[1]; 977: } 978: 979: if (GET_CODE (op1) == CONST_INT) 980: operands[1] = gen_rtx (CONST_INT, VOIDmode, 65535 & ~INTVAL (op1)); 981: else 982: operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1); 983: }") 984: 985: (define_expand "andqi3" 986: [(set (match_operand:QI 0 "general_operand" "=g") 987: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g")) 988: (match_operand:QI 2 "general_operand" "g")))] 989: "" 990: " 991: { 992: rtx op1 = operands[1]; 993: 994: if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT) 995: { 996: operands[1] = operands[2]; 997: operands[2] = op1; 998: op1 = operands[1]; 999: } 1000: 1001: if (GET_CODE (op1) == CONST_INT) 1002: operands[1] = gen_rtx (CONST_INT, VOIDmode, 255 & ~INTVAL (op1)); 1003: else 1004: operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1); 1005: }") 1006: 1007: (define_insn "" 1008: [(set (match_operand:SI 0 "general_operand" "=g,g") 1009: (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g")) 1010: (match_operand:SI 2 "general_operand" "0,g")))] 1011: "" 1012: "@ 1013: bicl2 %1,%0 1014: bicl3 %1,%2,%0") 1015: 1016: (define_insn "" 1017: [(set (match_operand:HI 0 "general_operand" "=g,g") 1018: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g")) 1019: (match_operand:HI 2 "general_operand" "0,g")))] 1020: "" 1021: "@ 1022: bicw2 %1,%0 1023: bicw3 %1,%2,%0") 1024: 1025: (define_insn "" 1026: [(set (match_operand:QI 0 "general_operand" "=g,g") 1027: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g")) 1028: (match_operand:QI 2 "general_operand" "0,g")))] 1029: "" 1030: "@ 1031: bicb2 %1,%0 1032: bicb3 %1,%2,%0") 1033: 1034: ;; The following used to be needed because constant propagation can 1035: ;; create them starting from the bic insn patterns above. This is no 1036: ;; longer a problem. However, having these patterns allows optimization 1037: ;; opportunities in combine.c. 1038: 1039: (define_insn "" 1040: [(set (match_operand:SI 0 "general_operand" "=g,g") 1041: (and:SI (match_operand:SI 1 "general_operand" "0,g") 1042: (match_operand:SI 2 "const_int_operand" "n,n")))] 1043: "" 1044: "@ 1045: bicl2 %N2,%0 1046: bicl3 %N2,%1,%0") 1047: 1048: (define_insn "" 1049: [(set (match_operand:HI 0 "general_operand" "=g,g") 1050: (and:HI (match_operand:HI 1 "general_operand" "0,g") 1051: (match_operand:HI 2 "const_int_operand" "n,n")))] 1052: "" 1053: "@ 1054: bicw2 %H2,%0 1055: bicw3 %H2,%1,%0") 1056: 1057: (define_insn "" 1058: [(set (match_operand:QI 0 "general_operand" "=g,g") 1059: (and:QI (match_operand:QI 1 "general_operand" "0,g") 1060: (match_operand:QI 2 "const_int_operand" "n,n")))] 1061: "" 1062: "@ 1063: bicb2 %B2,%0 1064: bicb3 %B2,%1,%0") 1065: 1066: ;;- Bit set instructions. 1067: 1068: (define_insn "iorsi3" 1069: [(set (match_operand:SI 0 "general_operand" "=g,g,g") 1070: (ior:SI (match_operand:SI 1 "general_operand" "0,g,g") 1071: (match_operand:SI 2 "general_operand" "g,0,g")))] 1072: "" 1073: "@ 1074: bisl2 %2,%0 1075: bisl2 %1,%0 1076: bisl3 %2,%1,%0") 1077: 1078: (define_insn "iorhi3" 1079: [(set (match_operand:HI 0 "general_operand" "=g,g,g") 1080: (ior:HI (match_operand:HI 1 "general_operand" "0,g,g") 1081: (match_operand:HI 2 "general_operand" "g,0,g")))] 1082: "" 1083: "@ 1084: bisw2 %2,%0 1085: bisw2 %1,%0 1086: bisw3 %2,%1,%0") 1087: 1088: (define_insn "iorqi3" 1089: [(set (match_operand:QI 0 "general_operand" "=g,g,g") 1090: (ior:QI (match_operand:QI 1 "general_operand" "0,g,g") 1091: (match_operand:QI 2 "general_operand" "g,0,g")))] 1092: "" 1093: "@ 1094: bisb2 %2,%0 1095: bisb2 %1,%0 1096: bisb3 %2,%1,%0") 1097: 1098: ;;- xor instructions. 1099: 1100: (define_insn "xorsi3" 1101: [(set (match_operand:SI 0 "general_operand" "=g,g,g") 1102: (xor:SI (match_operand:SI 1 "general_operand" "0,g,g") 1103: (match_operand:SI 2 "general_operand" "g,0,g")))] 1104: "" 1105: "@ 1106: xorl2 %2,%0 1107: xorl2 %1,%0 1108: xorl3 %2,%1,%0") 1109: 1110: (define_insn "xorhi3" 1111: [(set (match_operand:HI 0 "general_operand" "=g,g,g") 1112: (xor:HI (match_operand:HI 1 "general_operand" "0,g,g") 1113: (match_operand:HI 2 "general_operand" "g,0,g")))] 1114: "" 1115: "@ 1116: xorw2 %2,%0 1117: xorw2 %1,%0 1118: xorw3 %2,%1,%0") 1119: 1120: (define_insn "xorqi3" 1121: [(set (match_operand:QI 0 "general_operand" "=g,g,g") 1122: (xor:QI (match_operand:QI 1 "general_operand" "0,g,g") 1123: (match_operand:QI 2 "general_operand" "g,0,g")))] 1124: "" 1125: "@ 1126: xorb2 %2,%0 1127: xorb2 %1,%0 1128: xorb3 %2,%1,%0") 1129: 1130: (define_insn "negdf2" 1131: [(set (match_operand:DF 0 "general_operand" "=g") 1132: (neg:DF (match_operand:DF 1 "general_operand" "gF")))] 1133: "" 1134: "mneg%# %1,%0") 1135: 1136: (define_insn "negsf2" 1137: [(set (match_operand:SF 0 "general_operand" "=g") 1138: (neg:SF (match_operand:SF 1 "general_operand" "gF")))] 1139: "" 1140: "mnegf %1,%0") 1141: 1142: (define_insn "negsi2" 1143: [(set (match_operand:SI 0 "general_operand" "=g") 1144: (neg:SI (match_operand:SI 1 "general_operand" "g")))] 1145: "" 1146: "mnegl %1,%0") 1147: 1148: (define_insn "neghi2" 1149: [(set (match_operand:HI 0 "general_operand" "=g") 1150: (neg:HI (match_operand:HI 1 "general_operand" "g")))] 1151: "" 1152: "mnegw %1,%0") 1153: 1154: (define_insn "negqi2" 1155: [(set (match_operand:QI 0 "general_operand" "=g") 1156: (neg:QI (match_operand:QI 1 "general_operand" "g")))] 1157: "" 1158: "mnegb %1,%0") 1159: 1160: (define_insn "one_cmplsi2" 1161: [(set (match_operand:SI 0 "general_operand" "=g") 1162: (not:SI (match_operand:SI 1 "general_operand" "g")))] 1163: "" 1164: "mcoml %1,%0") 1165: 1166: (define_insn "one_cmplhi2" 1167: [(set (match_operand:HI 0 "general_operand" "=g") 1168: (not:HI (match_operand:HI 1 "general_operand" "g")))] 1169: "" 1170: "mcomw %1,%0") 1171: 1172: (define_insn "one_cmplqi2" 1173: [(set (match_operand:QI 0 "general_operand" "=g") 1174: (not:QI (match_operand:QI 1 "general_operand" "g")))] 1175: "" 1176: "mcomb %1,%0") 1177: 1178: ;; Arithmetic right shift on the vax works by negating the shift count, 1179: ;; then emitting a right shift with the shift count negated. This means 1180: ;; that all actual shift counts in the RTL will be positive. This 1181: ;; prevents converting shifts to ZERO_EXTRACTs with negative positions, 1182: ;; which isn't valid. 1183: (define_expand "ashrsi3" 1184: [(set (match_operand:SI 0 "general_operand" "=g") 1185: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1186: (match_operand:QI 2 "general_operand" "g")))] 1187: "" 1188: " 1189: { 1190: if (GET_CODE (operands[2]) != CONST_INT) 1191: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); 1192: }") 1193: 1194: (define_insn "" 1195: [(set (match_operand:SI 0 "general_operand" "=g") 1196: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1197: (match_operand:QI 2 "const_int_operand" "n")))] 1198: "" 1199: "ashl $%n2,%1,%0") 1200: 1201: (define_insn "" 1202: [(set (match_operand:SI 0 "general_operand" "=g") 1203: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1204: (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1205: "" 1206: "ashl %2,%1,%0") 1207: 1208: (define_insn "ashlsi3" 1209: [(set (match_operand:SI 0 "general_operand" "=g") 1210: (ashift:SI (match_operand:SI 1 "general_operand" "g") 1211: (match_operand:QI 2 "general_operand" "g")))] 1212: "" 1213: "* 1214: { 1215: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 1216: return \"addl2 %0,%0\"; 1217: if (GET_CODE (operands[1]) == REG 1218: && GET_CODE (operands[2]) == CONST_INT) 1219: { 1220: int i = INTVAL (operands[2]); 1221: if (i == 1) 1222: return \"addl3 %1,%1,%0\"; 1223: if (i == 2) 1224: return \"moval 0[%1],%0\"; 1225: if (i == 3) 1226: return \"movad 0[%1],%0\"; 1227: } 1228: return \"ashl %2,%1,%0\"; 1229: }") 1230: 1231: ;; Arithmetic right shift on the vax works by negating the shift count. 1232: (define_expand "ashrdi3" 1233: [(set (match_operand:DI 0 "general_operand" "=g") 1234: (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1235: (match_operand:QI 2 "general_operand" "g")))] 1236: "" 1237: " 1238: { 1239: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); 1240: }") 1241: 1242: (define_insn "ashldi3" 1243: [(set (match_operand:DI 0 "general_operand" "=g") 1244: (ashift:DI (match_operand:DI 1 "general_operand" "g") 1245: (match_operand:QI 2 "general_operand" "g")))] 1246: "" 1247: "ashq %2,%1,%0") 1248: 1249: (define_insn "" 1250: [(set (match_operand:DI 0 "general_operand" "=g") 1251: (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1252: (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1253: "" 1254: "ashq %2,%1,%0") 1255: 1.1.1.2 ! root 1256: ;; We used to have expand_shift handle logical right shifts by using extzv, ! 1257: ;; but this make it very difficult to do lshrdi3. Since the VAX is the ! 1258: ;; only machine with this kludge, it's better to just do this with a ! 1259: ;; define_expand and remove that case from expand_shift. ! 1260: ! 1261: (define_expand "lshrsi3" ! 1262: [(set (match_dup 3) ! 1263: (minus:QI (const_int 32) ! 1264: (match_dup 4))) ! 1265: (set (match_operand:SI 0 "general_operand" "=g") ! 1266: (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ! 1267: (match_dup 3) ! 1268: (match_operand:SI 2 "register_operand" "g")))] ! 1269: "" ! 1270: " ! 1271: { ! 1272: operands[3] = gen_reg_rtx (QImode); ! 1273: operands[4] = gen_lowpart (QImode, operands[2]); ! 1274: }") ! 1275: 1.1 root 1276: ;; Rotate right on the vax works by negating the shift count. 1277: (define_expand "rotrsi3" 1278: [(set (match_operand:SI 0 "general_operand" "=g") 1279: (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1280: (match_operand:QI 2 "general_operand" "g")))] 1281: "" 1282: " 1283: { 1284: if (GET_CODE (operands[2]) != CONST_INT) 1285: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); 1286: }") 1287: 1288: (define_insn "rotlsi3" 1289: [(set (match_operand:SI 0 "general_operand" "=g") 1290: (rotate:SI (match_operand:SI 1 "general_operand" "g") 1291: (match_operand:QI 2 "general_operand" "g")))] 1292: "" 1293: "rotl %2,%1,%0") 1294: 1295: (define_insn "" 1296: [(set (match_operand:SI 0 "general_operand" "=g") 1297: (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1298: (match_operand:QI 2 "const_int_operand" "n")))] 1299: "" 1300: "rotl $%R2,%1,%0") 1301: 1302: (define_insn "" 1303: [(set (match_operand:SI 0 "general_operand" "=g") 1304: (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1305: (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1306: "" 1307: "rotl %2,%1,%0") 1308: 1309: ;This insn is probably slower than a multiply and an add. 1310: ;(define_insn "" 1311: ; [(set (match_operand:SI 0 "general_operand" "=g") 1312: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1313: ; (match_operand:SI 2 "general_operand" "g")) 1314: ; (match_operand:SI 3 "general_operand" "g")))] 1315: ; "" 1316: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") 1317: 1318: ;; Special cases of bit-field insns which we should 1319: ;; recognize in preference to the general case. 1320: ;; These handle aligned 8-bit and 16-bit fields, 1321: ;; which can usually be done with move instructions. 1322: 1323: (define_insn "" 1.1.1.2 ! root 1324: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 1.1 root 1325: (match_operand:QI 1 "const_int_operand" "n") 1326: (match_operand:SI 2 "const_int_operand" "n")) 1327: (match_operand:SI 3 "general_operand" "g"))] 1328: "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1329: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 1330: && (GET_CODE (operands[0]) == REG 1331: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 1332: "* 1333: { 1334: if (REG_P (operands[0])) 1335: { 1336: if (INTVAL (operands[2]) != 0) 1337: return \"insv %3,%2,%1,%0\"; 1338: } 1339: else 1340: operands[0] 1341: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 1342: 1343: if (INTVAL (operands[1]) == 8) 1344: return \"movb %3,%0\"; 1345: return \"movw %3,%0\"; 1346: }") 1347: 1348: (define_insn "" 1349: [(set (match_operand:SI 0 "general_operand" "=&g") 1.1.1.2 ! root 1350: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1.1 root 1351: (match_operand:QI 2 "const_int_operand" "n") 1352: (match_operand:SI 3 "const_int_operand" "n")))] 1353: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1354: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1355: && (GET_CODE (operands[1]) == REG 1356: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 1357: "* 1358: { 1359: if (REG_P (operands[1])) 1360: { 1361: if (INTVAL (operands[3]) != 0) 1362: return \"extzv %3,%2,%1,%0\"; 1363: } 1364: else 1365: operands[1] 1366: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 1367: 1368: if (INTVAL (operands[2]) == 8) 1369: return \"movzbl %1,%0\"; 1370: return \"movzwl %1,%0\"; 1371: }") 1372: 1373: (define_insn "" 1374: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.2 ! root 1375: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1.1 root 1376: (match_operand:QI 2 "const_int_operand" "n") 1377: (match_operand:SI 3 "const_int_operand" "n")))] 1378: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1379: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1380: && (GET_CODE (operands[1]) == REG 1381: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 1382: "* 1383: { 1384: if (REG_P (operands[1])) 1385: { 1386: if (INTVAL (operands[3]) != 0) 1387: return \"extv %3,%2,%1,%0\"; 1388: } 1389: else 1390: operands[1] 1391: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 1392: 1393: if (INTVAL (operands[2]) == 8) 1394: return \"cvtbl %1,%0\"; 1395: return \"cvtwl %1,%0\"; 1396: }") 1397: 1398: ;; Register-only SImode cases of bit-field insns. 1399: 1400: (define_insn "" 1401: [(set (cc0) 1402: (compare 1403: (sign_extract:SI (match_operand:SI 0 "nonmemory_operand" "r") 1404: (match_operand:QI 1 "general_operand" "g") 1405: (match_operand:SI 2 "general_operand" "g")) 1406: (match_operand:SI 3 "general_operand" "g")))] 1407: "" 1408: "cmpv %2,%1,%0,%3") 1409: 1410: (define_insn "" 1411: [(set (cc0) 1412: (compare 1.1.1.2 ! root 1413: (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 1.1 root 1414: (match_operand:QI 1 "general_operand" "g") 1415: (match_operand:SI 2 "general_operand" "g")) 1416: (match_operand:SI 3 "general_operand" "g")))] 1417: "" 1418: "cmpzv %2,%1,%0,%3") 1419: 1420: ;; When the field position and size are constant and the destination 1421: ;; is a register, extv and extzv are much slower than a rotate followed 1422: ;; by a bicl or sign extension. 1423: 1424: (define_insn "" 1425: [(set (match_operand:SI 0 "general_operand" "=g") 1426: (sign_extract:SI (match_operand:SI 1 "nonmemory_operand" "r") 1427: (match_operand:QI 2 "general_operand" "g") 1428: (match_operand:SI 3 "general_operand" "g")))] 1429: "" 1430: "* 1431: { 1432: if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT 1433: || GET_CODE (operands[0]) != REG 1434: || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)) 1435: return \"extv %3,%2,%1,%0\"; 1436: if (INTVAL (operands[2]) == 8) 1437: return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 1438: return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 1439: }") 1440: 1441: (define_insn "" 1442: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.2 ! root 1443: (zero_extract:SI (match_operand:SI 1 "register_operand" "ri") 1.1 root 1444: (match_operand:QI 2 "general_operand" "g") 1445: (match_operand:SI 3 "general_operand" "g")))] 1446: "" 1447: "* 1448: { 1449: if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT 1450: || GET_CODE (operands[0]) != REG) 1451: return \"extzv %3,%2,%1,%0\"; 1452: if (INTVAL (operands[2]) == 8) 1453: return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 1454: if (INTVAL (operands[2]) == 16) 1455: return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 1456: if (INTVAL (operands[3]) & 31) 1457: return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 1458: if (rtx_equal_p (operands[0], operands[1])) 1459: return \"bicl2 %M2,%0\"; 1460: return \"bicl3 %M2,%1,%0\"; 1461: }") 1462: 1463: ;; Non-register cases. 1464: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases 1465: ;; don't match these (and therefore match the cases above instead). 1466: 1467: (define_insn "" 1468: [(set (cc0) 1469: (compare 1470: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") 1471: (match_operand:QI 1 "general_operand" "g") 1472: (match_operand:SI 2 "general_operand" "g")) 1473: (match_operand:SI 3 "general_operand" "g")))] 1474: "" 1475: "cmpv %2,%1,%0,%3") 1476: 1477: (define_insn "" 1478: [(set (cc0) 1479: (compare 1480: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") 1481: (match_operand:QI 1 "general_operand" "g") 1482: (match_operand:SI 2 "general_operand" "g")) 1483: (match_operand:SI 3 "general_operand" "g")))] 1484: "" 1485: "cmpzv %2,%1,%0,%3") 1486: 1487: (define_insn "extv" 1488: [(set (match_operand:SI 0 "general_operand" "=g") 1489: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") 1490: (match_operand:QI 2 "general_operand" "g") 1491: (match_operand:SI 3 "general_operand" "g")))] 1492: "" 1493: "* 1494: { 1495: if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT 1496: || GET_CODE (operands[3]) != CONST_INT 1497: || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16) 1.1.1.2 ! root 1498: || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 1.1 root 1499: || side_effects_p (operands[1]) 1500: || (GET_CODE (operands[1]) == MEM 1501: && mode_dependent_address_p (XEXP (operands[1], 0)))) 1502: return \"extv %3,%2,%1,%0\"; 1503: if (INTVAL (operands[2]) == 8) 1504: return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 1505: return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 1506: }") 1507: 1508: (define_insn "extzv" 1509: [(set (match_operand:SI 0 "general_operand" "=g") 1510: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") 1511: (match_operand:QI 2 "general_operand" "g") 1512: (match_operand:SI 3 "general_operand" "g")))] 1513: "" 1514: "* 1515: { 1516: if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT 1517: || GET_CODE (operands[3]) != CONST_INT 1.1.1.2 ! root 1518: || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 1.1 root 1519: || side_effects_p (operands[1]) 1520: || (GET_CODE (operands[1]) == MEM 1521: && mode_dependent_address_p (XEXP (operands[1], 0)))) 1522: return \"extzv %3,%2,%1,%0\"; 1523: if (INTVAL (operands[2]) == 8) 1524: return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 1525: if (INTVAL (operands[2]) == 16) 1526: return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 1527: return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 1528: }") 1529: 1530: (define_insn "insv" 1.1.1.2 ! root 1531: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+g") 1.1 root 1532: (match_operand:QI 1 "general_operand" "g") 1533: (match_operand:SI 2 "general_operand" "g")) 1534: (match_operand:SI 3 "general_operand" "g"))] 1535: "" 1536: "insv %3,%2,%1,%0") 1537: 1538: (define_insn "" 1.1.1.2 ! root 1539: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+r") 1.1 root 1540: (match_operand:QI 1 "general_operand" "g") 1541: (match_operand:SI 2 "general_operand" "g")) 1542: (match_operand:SI 3 "general_operand" "g"))] 1543: "" 1544: "insv %3,%2,%1,%0") 1545: 1546: (define_insn "jump" 1547: [(set (pc) 1548: (label_ref (match_operand 0 "" "")))] 1549: "" 1550: "jbr %l0") 1551: 1552: (define_insn "beq" 1553: [(set (pc) 1554: (if_then_else (eq (cc0) 1555: (const_int 0)) 1556: (label_ref (match_operand 0 "" "")) 1557: (pc)))] 1558: "" 1559: "jeql %l0") 1560: 1561: (define_insn "bne" 1562: [(set (pc) 1563: (if_then_else (ne (cc0) 1564: (const_int 0)) 1565: (label_ref (match_operand 0 "" "")) 1566: (pc)))] 1567: "" 1568: "jneq %l0") 1569: 1570: (define_insn "bgt" 1571: [(set (pc) 1572: (if_then_else (gt (cc0) 1573: (const_int 0)) 1574: (label_ref (match_operand 0 "" "")) 1575: (pc)))] 1576: "" 1577: "jgtr %l0") 1578: 1579: (define_insn "bgtu" 1580: [(set (pc) 1581: (if_then_else (gtu (cc0) 1582: (const_int 0)) 1583: (label_ref (match_operand 0 "" "")) 1584: (pc)))] 1585: "" 1586: "jgtru %l0") 1587: 1588: (define_insn "blt" 1589: [(set (pc) 1590: (if_then_else (lt (cc0) 1591: (const_int 0)) 1592: (label_ref (match_operand 0 "" "")) 1593: (pc)))] 1594: "" 1595: "jlss %l0") 1596: 1597: (define_insn "bltu" 1598: [(set (pc) 1599: (if_then_else (ltu (cc0) 1600: (const_int 0)) 1601: (label_ref (match_operand 0 "" "")) 1602: (pc)))] 1603: "" 1604: "jlssu %l0") 1605: 1606: (define_insn "bge" 1607: [(set (pc) 1608: (if_then_else (ge (cc0) 1609: (const_int 0)) 1610: (label_ref (match_operand 0 "" "")) 1611: (pc)))] 1612: "" 1613: "jgeq %l0") 1614: 1615: (define_insn "bgeu" 1616: [(set (pc) 1617: (if_then_else (geu (cc0) 1618: (const_int 0)) 1619: (label_ref (match_operand 0 "" "")) 1620: (pc)))] 1621: "" 1622: "jgequ %l0") 1623: 1624: (define_insn "ble" 1625: [(set (pc) 1626: (if_then_else (le (cc0) 1627: (const_int 0)) 1628: (label_ref (match_operand 0 "" "")) 1629: (pc)))] 1630: "" 1631: "jleq %l0") 1632: 1633: (define_insn "bleu" 1634: [(set (pc) 1635: (if_then_else (leu (cc0) 1636: (const_int 0)) 1637: (label_ref (match_operand 0 "" "")) 1638: (pc)))] 1639: "" 1640: "jlequ %l0") 1641: 1642: ;; Recognize reversed jumps. 1643: (define_insn "" 1644: [(set (pc) 1645: (if_then_else (match_operator 0 "comparison_operator" 1646: [(cc0) 1647: (const_int 0)]) 1648: (pc) 1649: (label_ref (match_operand 1 "" ""))))] 1650: "" 1651: "j%C0 %l1") ; %C0 negates condition 1652: 1653: ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand 1654: ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is 1655: ;; memory, we use QImode in the insn. So we can't use those instructions 1656: ;; for mode-dependent addresses. 1657: 1658: (define_insn "" 1659: [(set (pc) 1660: (if_then_else 1661: (ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g") 1662: (const_int 1) 1663: (match_operand:SI 1 "general_operand" "I,g")) 1664: (const_int 0)) 1665: (label_ref (match_operand 2 "" "")) 1666: (pc)))] 1667: "" 1668: "@ 1669: jlbs %0,%l2 1670: jbs %1,%0,%l2") 1671: 1672: (define_insn "" 1673: [(set (pc) 1674: (if_then_else 1675: (eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g") 1676: (const_int 1) 1677: (match_operand:SI 1 "general_operand" "I,g")) 1678: (const_int 0)) 1679: (label_ref (match_operand 2 "" "")) 1680: (pc)))] 1681: "" 1682: "@ 1683: jlbc %0,%l2 1684: jbc %1,%0,%l2") 1685: 1686: (define_insn "" 1687: [(set (pc) 1688: (if_then_else 1689: (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1690: (const_int 1) 1691: (match_operand:SI 1 "general_operand" "I,g")) 1692: (const_int 0)) 1693: (label_ref (match_operand 2 "" "")) 1694: (pc)))] 1695: "" 1696: "@ 1697: jlbs %0,%l2 1698: jbs %1,%0,%l2") 1699: 1700: (define_insn "" 1701: [(set (pc) 1702: (if_then_else 1703: (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1704: (const_int 1) 1705: (match_operand:SI 1 "general_operand" "I,g")) 1706: (const_int 0)) 1707: (label_ref (match_operand 2 "" "")) 1708: (pc)))] 1709: "" 1710: "@ 1711: jlbc %0,%l2 1712: jbc %1,%0,%l2") 1713: 1714: ;; Subtract-and-jump and Add-and-jump insns. 1715: ;; These are not used when output is for the Unix assembler 1716: ;; because it does not know how to modify them to reach far. 1717: 1718: ;; Normal sob insns. 1719: 1720: (define_insn "" 1721: [(set (pc) 1722: (if_then_else 1723: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g") 1724: (const_int -1)) 1725: (const_int 0)) 1726: (label_ref (match_operand 1 "" "")) 1727: (pc))) 1728: (set (match_dup 0) 1729: (plus:SI (match_dup 0) 1730: (const_int -1)))] 1731: "!TARGET_UNIX_ASM" 1732: "jsobgtr %0,%l1") 1733: 1734: (define_insn "" 1735: [(set (pc) 1736: (if_then_else 1737: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") 1738: (const_int -1)) 1739: (const_int 0)) 1740: (label_ref (match_operand 1 "" "")) 1741: (pc))) 1742: (set (match_dup 0) 1743: (plus:SI (match_dup 0) 1744: (const_int -1)))] 1745: "!TARGET_UNIX_ASM" 1746: "jsobgeq %0,%l1") 1747: 1748: ;; Normal aob insns. Define a version for when operands[1] is a constant. 1749: (define_insn "" 1750: [(set (pc) 1751: (if_then_else 1752: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g") 1753: (const_int 1)) 1754: (match_operand:SI 1 "general_operand" "g")) 1755: (label_ref (match_operand 2 "" "")) 1756: (pc))) 1757: (set (match_dup 0) 1758: (plus:SI (match_dup 0) 1759: (const_int 1)))] 1760: "!TARGET_UNIX_ASM" 1761: "jaoblss %1,%0,%l2") 1762: 1763: (define_insn "" 1764: [(set (pc) 1765: (if_then_else 1766: (lt (match_operand:SI 0 "general_operand" "+g") 1767: (match_operand:SI 1 "general_operand" "g")) 1768: (label_ref (match_operand 2 "" "")) 1769: (pc))) 1770: (set (match_dup 0) 1771: (plus:SI (match_dup 0) 1772: (const_int 1)))] 1773: "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT" 1774: "jaoblss %P1,%0,%l2") 1775: 1776: (define_insn "" 1777: [(set (pc) 1778: (if_then_else 1779: (le (plus:SI (match_operand:SI 0 "general_operand" "+g") 1780: (const_int 1)) 1781: (match_operand:SI 1 "general_operand" "g")) 1782: (label_ref (match_operand 2 "" "")) 1783: (pc))) 1784: (set (match_dup 0) 1785: (plus:SI (match_dup 0) 1786: (const_int 1)))] 1787: "!TARGET_UNIX_ASM" 1788: "jaobleq %1,%0,%l2") 1789: 1790: (define_insn "" 1791: [(set (pc) 1792: (if_then_else 1793: (le (match_operand:SI 0 "general_operand" "+g") 1794: (match_operand:SI 1 "general_operand" "g")) 1795: (label_ref (match_operand 2 "" "")) 1796: (pc))) 1797: (set (match_dup 0) 1798: (plus:SI (match_dup 0) 1799: (const_int 1)))] 1800: "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT" 1801: "jaobleq %P1,%0,%l2") 1802: 1803: ;; Something like a sob insn, but compares against -1. 1804: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'. 1805: 1806: (define_insn "" 1807: [(set (pc) 1808: (if_then_else 1809: (ne (match_operand:SI 0 "general_operand" "g") 1810: (const_int 0)) 1811: (label_ref (match_operand 1 "" "")) 1812: (pc))) 1813: (set (match_dup 0) 1814: (plus:SI (match_dup 0) 1815: (const_int -1)))] 1816: "" 1817: "decl %0\;jgequ %l1") 1818: 1819: ;; Note that operand 1 is total size of args, in bytes, 1820: ;; and what the call insn wants is the number of words. 1821: (define_insn "call_pop" 1822: [(call (match_operand:QI 0 "memory_operand" "m") 1823: (match_operand:QI 1 "general_operand" "g")) 1824: (set (reg:SI 14) (plus:SI (reg:SI 14) 1825: (match_operand:SI 3 "immediate_operand" "i")))] 1826: "" 1827: "* 1828: if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4) 1829: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ 1830: return \"calls $0,%0\;addl2 %1,sp\"; 1831: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4); 1832: return \"calls %1,%0\"; 1833: ") 1834: 1835: (define_insn "call_value_pop" 1836: [(set (match_operand 0 "" "=g") 1837: (call (match_operand:QI 1 "memory_operand" "m") 1838: (match_operand:QI 2 "general_operand" "g"))) 1839: (set (reg:SI 14) (plus:SI (reg:SI 14) 1840: (match_operand:SI 4 "immediate_operand" "i")))] 1841: "" 1842: "* 1843: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4) 1844: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ 1845: return \"calls $0,%1\;addl2 %2,sp\"; 1846: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4); 1847: return \"calls %2,%1\"; 1848: ") 1849: 1850: ;; Define another set of these for the case of functions with no 1851: ;; operands. In that case, combine may simplify the adjustment of sp. 1852: (define_insn "" 1853: [(call (match_operand:QI 0 "memory_operand" "m") 1854: (match_operand:QI 1 "general_operand" "g")) 1855: (set (reg:SI 14) (reg:SI 14))] 1856: "" 1857: "* 1858: if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4) 1859: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ 1860: return \"calls $0,%0\;addl2 %1,sp\"; 1861: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4); 1862: return \"calls %1,%0\"; 1863: ") 1864: 1865: (define_insn "" 1866: [(set (match_operand 0 "" "=g") 1867: (call (match_operand:QI 1 "memory_operand" "m") 1868: (match_operand:QI 2 "general_operand" "g"))) 1869: (set (reg:SI 14) (reg:SI 14))] 1870: "" 1871: "* 1872: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4) 1873: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */ 1874: return \"calls $0,%1\;addl2 %2,sp\"; 1875: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4); 1876: return \"calls %2,%1\"; 1877: ") 1878: 1879: ;; Call subroutine returning any type. 1880: 1881: (define_expand "untyped_call" 1882: [(parallel [(call (match_operand 0 "" "") 1883: (const_int 0)) 1884: (match_operand 1 "" "") 1885: (match_operand 2 "" "")])] 1886: "" 1887: " 1888: { 1889: int i; 1890: 1891: emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx)); 1892: 1893: for (i = 0; i < XVECLEN (operands[2], 0); i++) 1894: { 1895: rtx set = XVECEXP (operands[2], 0, i); 1896: emit_move_insn (SET_DEST (set), SET_SRC (set)); 1897: } 1898: 1899: /* The optimizer does not know that the call sets the function value 1900: registers we stored in the result block. We avoid problems by 1901: claiming that all hard registers are used and clobbered at this 1902: point. */ 1903: emit_insn (gen_blockage ()); 1904: 1905: DONE; 1906: }") 1907: 1908: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 1909: ;; all of memory. This blocks insns from being moved across this point. 1910: 1911: (define_insn "blockage" 1912: [(unspec_volatile [(const_int 0)] 0)] 1913: "" 1914: "") 1915: 1916: (define_insn "return" 1917: [(return)] 1918: "" 1919: "ret") 1920: 1921: (define_insn "nop" 1922: [(const_int 0)] 1923: "" 1924: "nop") 1925: 1926: ;; This had a wider constraint once, and it had trouble. 1927: ;; If you are tempted to try `g', please don't--it's not worth 1928: ;; the risk we will reopen the same bug. 1929: (define_insn "indirect_jump" 1930: [(set (pc) (match_operand:SI 0 "general_operand" "r"))] 1931: "" 1932: "jmp (%0)") 1933: 1934: ;; This is here to accept 5 arguments (as passed by expand_end_case) 1935: ;; and pass the first 4 along to the casesi1 pattern that really does the work. 1936: (define_expand "casesi" 1937: [(set (pc) 1938: (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g") 1939: (match_operand:SI 1 "general_operand" "g")) 1940: (match_operand:SI 2 "general_operand" "g")) 1941: (plus:SI (sign_extend:SI 1942: (mem:HI 1943: (plus:SI (pc) 1944: (mult:SI (minus:SI (match_dup 0) 1945: (match_dup 1)) 1946: (const_int 2))))) 1947: (label_ref:SI (match_operand 3 "" ""))) 1948: (pc))) 1949: (match_operand 4 "" "")] 1950: "" 1951: " 1952: emit_insn (gen_casesi1 (operands[0], operands[1], operands[2], operands[3])); 1953: DONE; 1954: ") 1955: 1956: (define_insn "casesi1" 1957: [(set (pc) 1958: (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g") 1959: (match_operand:SI 1 "general_operand" "g")) 1960: (match_operand:SI 2 "general_operand" "g")) 1961: (plus:SI (sign_extend:SI 1962: (mem:HI 1963: (plus:SI (pc) 1964: (mult:SI (minus:SI (match_dup 0) 1965: (match_dup 1)) 1966: (const_int 2))))) 1967: (label_ref:SI (match_operand 3 "" ""))) 1968: (pc)))] 1969: "" 1970: "casel %0,%1,%2") 1971: 1972: ;; This used to arise from the preceding by simplification 1973: ;; if operand 1 is zero. Perhaps it is no longer necessary. 1974: (define_insn "" 1975: [(set (pc) 1976: (if_then_else (leu (match_operand:SI 0 "general_operand" "g") 1977: (match_operand:SI 1 "general_operand" "g")) 1978: (plus:SI (sign_extend:SI 1979: (mem:HI 1980: (plus:SI (pc) 1981: (mult:SI (minus:SI (match_dup 0) 1982: (const_int 0)) 1983: (const_int 2))))) 1984: (label_ref:SI (match_operand 3 "" ""))) 1985: (pc)))] 1986: "" 1987: "casel %0,$0,%1") 1988: 1989: ;;- load or push effective address 1990: ;; These come after the move and add/sub patterns 1991: ;; because we don't want pushl $1 turned into pushad 1. 1992: ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. 1993: 1994: ;; It does not work to use constraints to distinguish pushes from moves, 1995: ;; because < matches any autodecrement, not just a push. 1996: 1997: (define_insn "" 1998: [(set (match_operand:SI 0 "general_operand" "=g") 1999: (match_operand:QI 1 "address_operand" "p"))] 2000: "" 2001: "* 2002: { 2003: if (push_operand (operands[0], SImode)) 2004: return \"pushab %a1\"; 2005: else 2006: return \"movab %a1,%0\"; 2007: }") 2008: 2009: (define_insn "" 2010: [(set (match_operand:SI 0 "general_operand" "=g") 2011: (match_operand:HI 1 "address_operand" "p"))] 2012: "" 2013: "* 2014: { 2015: if (push_operand (operands[0], SImode)) 2016: return \"pushaw %a1\"; 2017: else 2018: return \"movaw %a1,%0\"; 2019: }") 2020: 2021: (define_insn "" 2022: [(set (match_operand:SI 0 "general_operand" "=g") 2023: (match_operand:SI 1 "address_operand" "p"))] 2024: "" 2025: "* 2026: { 2027: if (push_operand (operands[0], SImode)) 2028: return \"pushal %a1\"; 2029: else 2030: return \"moval %a1,%0\"; 2031: }") 2032: 2033: (define_insn "" 2034: [(set (match_operand:SI 0 "general_operand" "=g") 2035: (match_operand:DI 1 "address_operand" "p"))] 2036: "" 2037: "* 2038: { 2039: if (push_operand (operands[0], SImode)) 2040: return \"pushaq %a1\"; 2041: else 2042: return \"movaq %a1,%0\"; 2043: }") 2044: 2045: (define_insn "" 2046: [(set (match_operand:SI 0 "general_operand" "=g") 2047: (match_operand:SF 1 "address_operand" "p"))] 2048: "" 2049: "* 2050: { 2051: if (push_operand (operands[0], SImode)) 2052: return \"pushaf %a1\"; 2053: else 2054: return \"movaf %a1,%0\"; 2055: }") 2056: 2057: (define_insn "" 2058: [(set (match_operand:SI 0 "general_operand" "=g") 2059: (match_operand:DF 1 "address_operand" "p"))] 2060: "" 2061: "* 2062: { 2063: if (push_operand (operands[0], SImode)) 2064: return \"pushad %a1\"; 2065: else 2066: return \"movad %a1,%0\"; 2067: }") 2068: 2069: ;; These used to be peepholes, but it is more straightforward to do them 2070: ;; as single insns. However, we must force the output to be a register 2071: ;; if it is not an offsettable address so that we know that we can assign 2072: ;; to it twice. 2073: 2074: ;; If we had a good way of evaluating the relative costs, these could be 2075: ;; machine-independent. 2076: 2077: ;; Optimize extzv ...,z; andl2 ...,z 2078: ;; or ashl ...,z; andl2 ...,z 2079: ;; with other operands constant. This is what the combiner converts the 2080: ;; above sequences to before attempting to recognize the new insn. 2081: 2082: (define_insn "" 2083: [(set (match_operand:SI 0 "general_operand" "=ro") 2084: (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 2085: (match_operand:QI 2 "const_int_operand" "n")) 2086: (match_operand:SI 3 "const_int_operand" "n")))] 2087: "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0" 2088: "* 2089: { 2090: unsigned long mask1 = INTVAL (operands[3]); 2091: unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1; 2092: 2093: if ((mask1 & mask2) != mask1) 2094: operands[3] = gen_rtx (CONST_INT, VOIDmode, mask1 & mask2); 2095: 2096: return \"rotl %R2,%1,%0\;bicl2 %N3,%0\"; 2097: }") 2098: 2099: ;; left-shift and mask 2100: ;; The only case where `ashl' is better is if the mask only turns off 2101: ;; bits that the ashl would anyways, in which case it should have been 2102: ;; optimized away. 2103: 2104: (define_insn "" 2105: [(set (match_operand:SI 0 "general_operand" "=ro") 2106: (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g") 2107: (match_operand:QI 2 "const_int_operand" "n")) 2108: (match_operand:SI 3 "const_int_operand" "n")))] 2109: "" 2110: "* 2111: { 2112: operands[3] = gen_rtx (CONST_INT, VOIDmode, 2113: INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1)); 2114: return \"rotl %2,%1,%0\;bicl2 %N3,%0\"; 2115: }")
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