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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- AT&T we32000 Version ! 3: ;; Contributed by John Wehle ([email protected]) ! 4: ;; Copyright (C) 1991-1992 Free Software Foundation, Inc. ! 5: ! 6: ;; This file is part of GNU CC. ! 7: ! 8: ;; GNU CC is free software; you can redistribute it and/or modify ! 9: ;; it under the terms of the GNU General Public License as published by ! 10: ;; the Free Software Foundation; either version 1, or (at your option) ! 11: ;; any later version. ! 12: ! 13: ;; GNU CC is distributed in the hope that it will be useful, ! 14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 16: ;; GNU General Public License for more details. ! 17: ! 18: ;; You should have received a copy of the GNU General Public License ! 19: ;; along with GNU CC; see the file COPYING. If not, write to ! 20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 21: ! 22: ! 23: ;;- instruction definitions ! 24: ! 25: ;;- @@The original PO technology requires these to be ordered by speed, ! 26: ;;- @@ so that assigner will pick the fastest. ! 27: ! 28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 29: ! 30: ;;- When naming insn's (operand 0 of define_insn) be careful about using ! 31: ;;- names from other targets machine descriptions. ! 32: ! 33: ;; move instructions ! 34: ! 35: (define_insn "" ! 36: [(set (match_operand:DF 0 "push_operand" "=m") ! 37: (match_operand:DF 1 "general_operand" "mrF"))] ! 38: "" ! 39: "* ! 40: { ! 41: output_push_double(&operands[1]); ! 42: ! 43: return \"\"; ! 44: }") ! 45: ! 46: (define_insn "movdf" ! 47: [(set (match_operand:DF 0 "nonimmediate_operand" "=mr") ! 48: (match_operand:DF 1 "general_operand" "mrF"))] ! 49: "" ! 50: "* ! 51: { ! 52: output_move_double(operands); ! 53: ! 54: return \"\"; ! 55: }") ! 56: ! 57: (define_insn "" ! 58: [(set (match_operand:SF 0 "push_operand" "=m") ! 59: (match_operand:SF 1 "general_operand" "mrF"))] ! 60: "" ! 61: "pushw %1") ! 62: ! 63: (define_insn "movsf" ! 64: [(set (match_operand:SF 0 "nonimmediate_operand" "=mr") ! 65: (match_operand:SF 1 "general_operand" "mrF"))] ! 66: "" ! 67: "movw %1, %0") ! 68: ! 69: (define_insn "" ! 70: [(set (match_operand:DI 0 "push_operand" "=m") ! 71: (match_operand:DI 1 "general_operand" "mriF"))] ! 72: "" ! 73: "* ! 74: { ! 75: output_push_double(&operands[1]); ! 76: ! 77: return \"\"; ! 78: }") ! 79: ! 80: (define_insn "movdi" ! 81: [(set (match_operand:DI 0 "nonimmediate_operand" "=mr") ! 82: (match_operand:DI 1 "general_operand" "mriF"))] ! 83: "" ! 84: "* ! 85: { ! 86: output_move_double(operands); ! 87: ! 88: return \"\"; ! 89: }") ! 90: ! 91: (define_insn "" ! 92: [(set (match_operand:SI 0 "push_operand" "=m") ! 93: (match_operand:SI 1 "general_operand" "mri"))] ! 94: "" ! 95: "pushw %1") ! 96: ! 97: (define_insn "movsi" ! 98: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 99: (match_operand:SI 1 "general_operand" "mri"))] ! 100: "" ! 101: "movw %1, %0") ! 102: ! 103: (define_insn "movhi" ! 104: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 105: (match_operand:HI 1 "general_operand" "mri"))] ! 106: "" ! 107: "movh %1, %0") ! 108: ! 109: (define_insn "movqi" ! 110: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 111: (match_operand:QI 1 "general_operand" "mri"))] ! 112: "" ! 113: "movb %1, %0") ! 114: ! 115: ;; add instructions ! 116: ! 117: (define_insn "" ! 118: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") ! 119: (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") ! 120: (match_operand:DI 2 "general_operand" "oriF")))] ! 121: "" ! 122: "* ! 123: { ! 124: rtx label[1]; ! 125: rtx lsw_operands[3]; ! 126: ! 127: if (GET_CODE (operands[0]) == REG) ! 128: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); ! 129: else ! 130: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) ! 131: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); ! 132: else ! 133: abort(); ! 134: ! 135: if (GET_CODE (operands[2]) == REG) ! 136: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); ! 137: else ! 138: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) ! 139: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); ! 140: else ! 141: if (GET_CODE (operands[2]) == CONST_DOUBLE) ! 142: { ! 143: lsw_operands[2] = gen_rtx(CONST_INT, SImode, ! 144: CONST_DOUBLE_HIGH(operands[2])); ! 145: operands[2] = gen_rtx(CONST_INT, SImode, ! 146: CONST_DOUBLE_LOW(operands[2])); ! 147: } ! 148: else ! 149: if (GET_CODE (operands[2]) == CONST_INT) ! 150: { ! 151: lsw_operands[2] = operands[2]; ! 152: operands[2] = const0_rtx; ! 153: } ! 154: else ! 155: abort(); ! 156: ! 157: label[0] = gen_label_rtx(); ! 158: LABEL_NUSES(label[0]) = 1; ! 159: ! 160: output_asm_insn(\"addw2 %2, %0\", operands); ! 161: output_asm_insn(\"addw2 %2, %0\", lsw_operands); ! 162: output_asm_insn(\"BCCB %l0\", label); ! 163: output_asm_insn(\"INCW %0\", operands); ! 164: output_asm_insn(\"%l0:\", label); ! 165: ! 166: return \"\"; ! 167: }") ! 168: ! 169: (define_insn "adddi3" ! 170: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") ! 171: (plus:DI (match_operand:DI 1 "general_operand" "oriF") ! 172: (match_operand:DI 2 "general_operand" "oriF")))] ! 173: "" ! 174: "* ! 175: { ! 176: rtx label[1]; ! 177: rtx lsw_operands[3]; ! 178: ! 179: if (GET_CODE (operands[0]) == REG) ! 180: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); ! 181: else ! 182: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) ! 183: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); ! 184: else ! 185: abort(); ! 186: ! 187: if (GET_CODE (operands[1]) == REG) ! 188: lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1); ! 189: else ! 190: if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) ! 191: lsw_operands[1] = adj_offsettable_operand(operands[1], 4); ! 192: else ! 193: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 194: { ! 195: lsw_operands[1] = gen_rtx(CONST_INT, SImode, ! 196: CONST_DOUBLE_HIGH(operands[1])); ! 197: operands[1] = gen_rtx(CONST_INT, SImode, ! 198: CONST_DOUBLE_LOW(operands[1])); ! 199: } ! 200: else ! 201: if (GET_CODE (operands[1]) == CONST_INT) ! 202: { ! 203: lsw_operands[1] = operands[1]; ! 204: operands[1] = const0_rtx; ! 205: } ! 206: else ! 207: abort(); ! 208: ! 209: if (GET_CODE (operands[2]) == REG) ! 210: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); ! 211: else ! 212: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) ! 213: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); ! 214: else ! 215: if (GET_CODE (operands[2]) == CONST_DOUBLE) ! 216: { ! 217: lsw_operands[2] = gen_rtx(CONST_INT, SImode, ! 218: CONST_DOUBLE_HIGH(operands[2])); ! 219: operands[2] = gen_rtx(CONST_INT, SImode, ! 220: CONST_DOUBLE_LOW(operands[2])); ! 221: } ! 222: else ! 223: if (GET_CODE (operands[2]) == CONST_INT) ! 224: { ! 225: lsw_operands[2] = operands[2]; ! 226: operands[2] = const0_rtx; ! 227: } ! 228: else ! 229: abort(); ! 230: ! 231: label[0] = gen_label_rtx(); ! 232: LABEL_NUSES(label[0]) = 1; ! 233: ! 234: output_asm_insn(\"addw3 %2, %1, %0\", operands); ! 235: output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands); ! 236: output_asm_insn(\"BCCB %l0\", label); ! 237: output_asm_insn(\"INCW %0\", operands); ! 238: output_asm_insn(\"%l0:\", label); ! 239: ! 240: return \"\"; ! 241: }") ! 242: ! 243: (define_insn "" ! 244: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 245: (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 246: (match_operand:SI 2 "general_operand" "mri")))] ! 247: "" ! 248: "addw2 %2, %0") ! 249: ! 250: (define_insn "addsi3" ! 251: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 252: (plus:SI (match_operand:SI 1 "general_operand" "mri") ! 253: (match_operand:SI 2 "general_operand" "mri")))] ! 254: "" ! 255: "addw3 %2, %1, %0") ! 256: ! 257: (define_insn "" ! 258: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 259: (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0") ! 260: (match_operand:HI 2 "general_operand" "mri")))] ! 261: "" ! 262: "addh2 %2, %0") ! 263: ! 264: (define_insn "addhi3" ! 265: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 266: (plus:HI (match_operand:HI 1 "general_operand" "mri") ! 267: (match_operand:HI 2 "general_operand" "mri")))] ! 268: "" ! 269: "addh3 %2, %1, %0") ! 270: ! 271: (define_insn "" ! 272: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 273: (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0") ! 274: (match_operand:QI 2 "general_operand" "mri")))] ! 275: "" ! 276: "addb2 %2, %0") ! 277: ! 278: (define_insn "addqi3" ! 279: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 280: (plus:QI (match_operand:QI 1 "general_operand" "mri") ! 281: (match_operand:QI 2 "general_operand" "mri")))] ! 282: "" ! 283: "addb3 %2, %1, %0") ! 284: ! 285: ;; subtract instructions ! 286: ! 287: (define_insn "" ! 288: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") ! 289: (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0") ! 290: (match_operand:DI 2 "general_operand" "oriF")))] ! 291: "" ! 292: "* ! 293: { ! 294: rtx label[1]; ! 295: rtx lsw_operands[3]; ! 296: ! 297: if (GET_CODE (operands[0]) == REG) ! 298: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); ! 299: else ! 300: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) ! 301: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); ! 302: else ! 303: abort(); ! 304: ! 305: if (GET_CODE (operands[2]) == REG) ! 306: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); ! 307: else ! 308: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) ! 309: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); ! 310: else ! 311: if (GET_CODE (operands[2]) == CONST_DOUBLE) ! 312: { ! 313: lsw_operands[2] = gen_rtx(CONST_INT, SImode, ! 314: CONST_DOUBLE_HIGH(operands[2])); ! 315: operands[2] = gen_rtx(CONST_INT, SImode, ! 316: CONST_DOUBLE_LOW(operands[2])); ! 317: } ! 318: else ! 319: if (GET_CODE (operands[2]) == CONST_INT) ! 320: { ! 321: lsw_operands[2] = operands[2]; ! 322: operands[2] = const0_rtx; ! 323: } ! 324: else ! 325: abort(); ! 326: ! 327: label[0] = gen_label_rtx(); ! 328: LABEL_NUSES(label[0]) = 1; ! 329: ! 330: output_asm_insn(\"subw2 %2, %0\", operands); ! 331: output_asm_insn(\"subw2 %2, %0\", lsw_operands); ! 332: output_asm_insn(\"BCCB %l0\", label); ! 333: output_asm_insn(\"DECW %0\", operands); ! 334: output_asm_insn(\"%l0:\", label); ! 335: ! 336: return \"\"; ! 337: }") ! 338: ! 339: (define_insn "subdi3" ! 340: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") ! 341: (minus:DI (match_operand:DI 1 "general_operand" "oriF") ! 342: (match_operand:DI 2 "general_operand" "oriF")))] ! 343: "" ! 344: "* ! 345: { ! 346: rtx label[1]; ! 347: rtx lsw_operands[3]; ! 348: ! 349: if (GET_CODE (operands[0]) == REG) ! 350: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); ! 351: else ! 352: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) ! 353: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); ! 354: else ! 355: abort(); ! 356: ! 357: if (GET_CODE (operands[1]) == REG) ! 358: lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1); ! 359: else ! 360: if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) ! 361: lsw_operands[1] = adj_offsettable_operand(operands[1], 4); ! 362: else ! 363: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 364: { ! 365: lsw_operands[1] = gen_rtx(CONST_INT, SImode, ! 366: CONST_DOUBLE_HIGH(operands[1])); ! 367: operands[1] = gen_rtx(CONST_INT, SImode, ! 368: CONST_DOUBLE_LOW(operands[1])); ! 369: } ! 370: else ! 371: if (GET_CODE (operands[1]) == CONST_INT) ! 372: { ! 373: lsw_operands[1] = operands[1]; ! 374: operands[1] = const0_rtx; ! 375: } ! 376: else ! 377: abort(); ! 378: ! 379: if (GET_CODE (operands[2]) == REG) ! 380: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); ! 381: else ! 382: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) ! 383: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); ! 384: else ! 385: if (GET_CODE (operands[2]) == CONST_DOUBLE) ! 386: { ! 387: lsw_operands[2] = gen_rtx(CONST_INT, SImode, ! 388: CONST_DOUBLE_HIGH(operands[2])); ! 389: operands[2] = gen_rtx(CONST_INT, SImode, ! 390: CONST_DOUBLE_LOW(operands[2])); ! 391: } ! 392: else ! 393: if (GET_CODE (operands[2]) == CONST_INT) ! 394: { ! 395: lsw_operands[2] = operands[2]; ! 396: operands[2] = const0_rtx; ! 397: } ! 398: else ! 399: abort(); ! 400: ! 401: label[0] = gen_label_rtx(); ! 402: LABEL_NUSES(label[0]) = 1; ! 403: ! 404: output_asm_insn(\"subw3 %2, %1, %0\", operands); ! 405: output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands); ! 406: output_asm_insn(\"BCCB %l0\", label); ! 407: output_asm_insn(\"DECW %0\", operands); ! 408: output_asm_insn(\"%l0:\", label); ! 409: ! 410: return \"\"; ! 411: }") ! 412: ! 413: (define_insn "" ! 414: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 415: (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 416: (match_operand:SI 2 "general_operand" "mri")))] ! 417: "" ! 418: "subw2 %2, %0") ! 419: ! 420: (define_insn "subsi3" ! 421: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 422: (minus:SI (match_operand:SI 1 "general_operand" "mri") ! 423: (match_operand:SI 2 "general_operand" "mri")))] ! 424: "" ! 425: "subw3 %2, %1, %0") ! 426: ! 427: (define_insn "" ! 428: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 429: (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0") ! 430: (match_operand:HI 2 "general_operand" "mri")))] ! 431: "" ! 432: "subh2 %2, %0") ! 433: ! 434: (define_insn "subhi3" ! 435: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 436: (minus:HI (match_operand:HI 1 "general_operand" "mri") ! 437: (match_operand:HI 2 "general_operand" "mri")))] ! 438: "" ! 439: "subh3 %2, %1, %0") ! 440: ! 441: (define_insn "" ! 442: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 443: (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0") ! 444: (match_operand:QI 2 "general_operand" "mri")))] ! 445: "" ! 446: "subb2 %2, %0") ! 447: ! 448: (define_insn "subqi3" ! 449: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 450: (minus:QI (match_operand:QI 1 "general_operand" "mri") ! 451: (match_operand:QI 2 "general_operand" "mri")))] ! 452: "" ! 453: "subb3 %2, %1, %0") ! 454: ! 455: ;; signed multiply instructions ! 456: ! 457: (define_insn "" ! 458: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 459: (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 460: (match_operand:SI 2 "general_operand" "mri")))] ! 461: "" ! 462: "mulw2 %2, %0") ! 463: ! 464: (define_insn "mulsi3" ! 465: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 466: (mult:SI (match_operand:SI 1 "general_operand" "mri") ! 467: (match_operand:SI 2 "general_operand" "mri")))] ! 468: "" ! 469: "mulw3 %2, %1, %0") ! 470: ! 471: ;; signed divide instructions ! 472: ! 473: (define_insn "" ! 474: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 475: (div:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 476: (match_operand:SI 2 "general_operand" "mri")))] ! 477: "" ! 478: "divw2 %2, %0") ! 479: ! 480: (define_insn "divsi3" ! 481: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 482: (div:SI (match_operand:SI 1 "general_operand" "mri") ! 483: (match_operand:SI 2 "general_operand" "mri")))] ! 484: "" ! 485: "divw3 %2, %1, %0") ! 486: ! 487: ;; signed modulus instruction ! 488: ! 489: (define_insn "" ! 490: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 491: (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 492: (match_operand:SI 2 "general_operand" "mri")))] ! 493: "" ! 494: "modw2 %2, %0") ! 495: ! 496: (define_insn "modsi3" ! 497: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 498: (mod:SI (match_operand:SI 1 "general_operand" "mri") ! 499: (match_operand:SI 2 "general_operand" "mri")))] ! 500: "" ! 501: "modw3 %2, %1, %0") ! 502: ! 503: ;; unsigned divide instruction ! 504: ! 505: (define_insn "" ! 506: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 507: (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 508: (match_operand:SI 2 "general_operand" "mri")))] ! 509: "" ! 510: "udivw2 %2, %0") ! 511: ! 512: (define_insn "udivsi3" ! 513: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 514: (udiv:SI (match_operand:SI 1 "general_operand" "mri") ! 515: (match_operand:SI 2 "general_operand" "mri")))] ! 516: "" ! 517: "udivw3 %2, %1, %0") ! 518: ! 519: ;; unsigned modulus instruction ! 520: ! 521: (define_insn "" ! 522: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 523: (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 524: (match_operand:SI 2 "general_operand" "mri")))] ! 525: "" ! 526: "umodw2 %2, %0") ! 527: ! 528: (define_insn "umodsi3" ! 529: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 530: (umod:SI (match_operand:SI 1 "general_operand" "mri") ! 531: (match_operand:SI 2 "general_operand" "mri")))] ! 532: "" ! 533: "umodw3 %2, %1, %0") ! 534: ! 535: ;; logical-and instructions ! 536: ! 537: (define_insn "" ! 538: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 539: (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 540: (match_operand:SI 2 "general_operand" "mri")))] ! 541: "" ! 542: "andw2 %2, %0") ! 543: ! 544: (define_insn "andsi3" ! 545: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 546: (and:SI (match_operand:SI 1 "general_operand" "mri") ! 547: (match_operand:SI 2 "general_operand" "mri")))] ! 548: "" ! 549: "andw3 %2, %1, %0") ! 550: ! 551: (define_insn "" ! 552: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 553: (and:HI (match_operand:HI 1 "nonimmediate_operand" "0") ! 554: (match_operand:HI 2 "general_operand" "mri")))] ! 555: "" ! 556: "andh2 %2, %0") ! 557: ! 558: (define_insn "andhi3" ! 559: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 560: (and:HI (match_operand:HI 1 "general_operand" "mri") ! 561: (match_operand:HI 2 "general_operand" "mri")))] ! 562: "" ! 563: "andh3 %2, %1, %0") ! 564: ! 565: (define_insn "" ! 566: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 567: (and:QI (match_operand:QI 1 "nonimmediate_operand" "0") ! 568: (match_operand:QI 2 "general_operand" "mri")))] ! 569: "" ! 570: "andb2 %2, %0") ! 571: ! 572: (define_insn "andqi3" ! 573: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 574: (and:QI (match_operand:QI 1 "general_operand" "mri") ! 575: (match_operand:QI 2 "general_operand" "mri")))] ! 576: "" ! 577: "andb3 %2, %1, %0") ! 578: ! 579: ;; inclusive-or instructions ! 580: ! 581: (define_insn "" ! 582: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 583: (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 584: (match_operand:SI 2 "general_operand" "mri")))] ! 585: "" ! 586: "orw2 %2, %0") ! 587: ! 588: (define_insn "iorsi3" ! 589: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 590: (ior:SI (match_operand:SI 1 "general_operand" "mri") ! 591: (match_operand:SI 2 "general_operand" "mri")))] ! 592: "" ! 593: "orw3 %2, %1, %0") ! 594: ! 595: (define_insn "" ! 596: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 597: (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0") ! 598: (match_operand:HI 2 "general_operand" "mri")))] ! 599: "" ! 600: "orh2 %2, %0") ! 601: ! 602: (define_insn "iorhi3" ! 603: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 604: (ior:HI (match_operand:HI 1 "general_operand" "mri") ! 605: (match_operand:HI 2 "general_operand" "mri")))] ! 606: "" ! 607: "orh3 %2, %1, %0") ! 608: ! 609: (define_insn "" ! 610: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 611: (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0") ! 612: (match_operand:QI 2 "general_operand" "mri")))] ! 613: "" ! 614: "orb2 %2, %0") ! 615: ! 616: (define_insn "iorqi3" ! 617: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 618: (ior:QI (match_operand:QI 1 "general_operand" "mri") ! 619: (match_operand:QI 2 "general_operand" "mri")))] ! 620: "" ! 621: "orb3 %2, %1, %0") ! 622: ! 623: ;; exclusive-or instructions ! 624: ! 625: (define_insn "" ! 626: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 627: (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0") ! 628: (match_operand:SI 2 "general_operand" "mri")))] ! 629: "" ! 630: "xorw2 %2, %0") ! 631: ! 632: (define_insn "xorsi3" ! 633: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 634: (xor:SI (match_operand:SI 1 "general_operand" "mri") ! 635: (match_operand:SI 2 "general_operand" "mri")))] ! 636: "" ! 637: "xorw3 %2, %1, %0") ! 638: ! 639: (define_insn "" ! 640: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 641: (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0") ! 642: (match_operand:HI 2 "general_operand" "mri")))] ! 643: "" ! 644: "xorh2 %2, %0") ! 645: ! 646: (define_insn "xorhi3" ! 647: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 648: (xor:HI (match_operand:HI 1 "general_operand" "mri") ! 649: (match_operand:HI 2 "general_operand" "mri")))] ! 650: "" ! 651: "xorh3 %2, %1, %0") ! 652: ! 653: (define_insn "" ! 654: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 655: (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0") ! 656: (match_operand:QI 2 "general_operand" "mri")))] ! 657: "" ! 658: "xorb2 %2, %0") ! 659: ! 660: (define_insn "xorqi3" ! 661: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 662: (xor:QI (match_operand:QI 1 "general_operand" "mri") ! 663: (match_operand:QI 2 "general_operand" "mri")))] ! 664: "" ! 665: "xorb3 %2, %1, %0") ! 666: ! 667: ;; arithmetic shift instructions ! 668: ! 669: (define_insn "ashlsi3" ! 670: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 671: (ashift:SI (match_operand:SI 1 "general_operand" "mri") ! 672: (match_operand:SI 2 "general_operand" "mri")))] ! 673: "" ! 674: "LLSW3 %2, %1, %0") ! 675: ! 676: (define_insn "ashrsi3" ! 677: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 678: (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri") ! 679: (match_operand:SI 2 "general_operand" "mri")))] ! 680: "" ! 681: "ARSW3 %2, %1, %0") ! 682: ! 683: ;; logical shift instructions ! 684: ! 685: ;; (define_insn "lshlsi3" ! 686: ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 687: ;; (lshift:SI (match_operand:SI 1 "general_operand" "mri") ! 688: ;; (match_operand:SI 2 "general_operand" "mri")))] ! 689: ;; "" ! 690: ;; "LLSW3 %2, %1, %0") ! 691: ! 692: (define_insn "lshrsi3" ! 693: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 694: (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri") ! 695: (match_operand:SI 2 "general_operand" "mri")))] ! 696: "" ! 697: "LRSW3 %2, %1, %0") ! 698: ! 699: ;; rotate instruction ! 700: ! 701: (define_insn "rotrsi3" ! 702: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 703: (rotatert: SI (match_operand:SI 1 "general_operand" "mri") ! 704: (match_operand:SI 2 "general_operand" "mri")))] ! 705: "" ! 706: "ROTW %2, %1, %0") ! 707: ! 708: ;; negate instructions ! 709: ! 710: (define_insn "negsi2" ! 711: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 712: (neg:SI (match_operand:SI 1 "general_operand" "mri")))] ! 713: "" ! 714: "mnegw %1, %0") ! 715: ! 716: (define_insn "neghi2" ! 717: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 718: (neg:HI (match_operand:HI 1 "general_operand" "mri")))] ! 719: "" ! 720: "mnegh %1, %0") ! 721: ! 722: ;; complement instructions ! 723: ! 724: (define_insn "one_cmplsi2" ! 725: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 726: (not:SI (match_operand:SI 1 "general_operand" "mri")))] ! 727: "" ! 728: "mcomw %1, %0") ! 729: ! 730: (define_insn "one_cmplhi2" ! 731: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 732: (not:HI (match_operand:HI 1 "general_operand" "mri")))] ! 733: "" ! 734: "mcomh %1, %0") ! 735: ! 736: (define_insn "one_cmplqi2" ! 737: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 738: (not:QI (match_operand:QI 1 "general_operand" "mri")))] ! 739: "" ! 740: "mcomb %1, %0") ! 741: ! 742: ;; test instruction ! 743: ! 744: ;; We don't want to allow a constant operand for test insns because ! 745: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ! 746: ;; be folded while optimizing anyway. ! 747: ! 748: (define_insn "tstsi" ! 749: [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))] ! 750: "" ! 751: "TSTW %0") ! 752: ! 753: (define_insn "tsthi" ! 754: [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))] ! 755: "" ! 756: "TSTH %0") ! 757: ! 758: (define_insn "tstqi" ! 759: [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))] ! 760: "" ! 761: "TSTB {sbyte}%0") ! 762: ! 763: ;; compare instruction ! 764: ! 765: (define_insn "cmpsi" ! 766: [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr") ! 767: (match_operand:SI 1 "general_operand" "mri")))] ! 768: "" ! 769: "CMPW %1, %0") ! 770: ! 771: (define_insn "cmphi" ! 772: [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr") ! 773: (match_operand:HI 1 "general_operand" "mri")))] ! 774: "" ! 775: "* ! 776: { ! 777: ! 778: if (GET_CODE (operands[1]) == CONST_INT && ! 779: ((unsigned long)INTVAL (operands[1]) & 0x8000L)) ! 780: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffff0000L); ! 781: ! 782: output_asm_insn(\"CMPH %1, %0\",operands); ! 783: ! 784: return \"\"; ! 785: }") ! 786: ! 787: (define_insn "cmpqi" ! 788: [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr") ! 789: (match_operand:QI 1 "general_operand" "mri")))] ! 790: "" ! 791: "* ! 792: { ! 793: ! 794: if (GET_CODE (operands[1]) == CONST_INT && ! 795: ((unsigned long)INTVAL (operands[1]) & 0x80L)) ! 796: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffffff00L); ! 797: ! 798: output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands); ! 799: ! 800: return \"\"; ! 801: }") ! 802: ! 803: ;; truncate instructions ! 804: ! 805: (define_insn "truncdfsf2" ! 806: [(clobber (reg:SI 0)) ! 807: (clobber (reg:SI 1)) ! 808: (clobber (reg:SI 2)) ! 809: (set (match_operand:SF 0 "nonimmediate_operand" "=mr") ! 810: (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))] ! 811: "" ! 812: "* ! 813: { ! 814: output_push_double(&operands[1]); ! 815: output_asm_insn(\"call &2, _fdtos\"); ! 816: ! 817: if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 0) ! 818: output_asm_insn(\"movw %%r0, %0\", operands); ! 819: ! 820: return \"\"; ! 821: }") ! 822: ! 823: ! 824: (define_insn "truncsihi2" ! 825: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 826: (truncate:HI (match_operand:SI 1 "general_operand" "mri")))] ! 827: "" ! 828: "movtwh %1, %0") ! 829: ! 830: (define_insn "truncsiqi2" ! 831: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 832: (truncate:QI (match_operand:SI 1 "general_operand" "mri")))] ! 833: "" ! 834: "movtwb %1, %0") ! 835: ! 836: (define_insn "trunchiqi2" ! 837: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") ! 838: (truncate:QI (match_operand:HI 1 "general_operand" "mri")))] ! 839: "" ! 840: "movthb %1, %0") ! 841: ! 842: ;; sign-extend move instructions ! 843: ! 844: (define_insn "extendsfdf2" ! 845: [(clobber (reg:SI 0)) ! 846: (clobber (reg:SI 1)) ! 847: (clobber (reg:SI 2)) ! 848: (set (match_operand:DF 0 "nonimmediate_operand" "=or") ! 849: (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))] ! 850: "" ! 851: "* ! 852: { ! 853: rtx xoperands[2]; ! 854: ! 855: output_asm_insn(\"pushw %1\", operands); ! 856: output_asm_insn(\"call &1, _fstod\"); ! 857: ! 858: if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 0) { ! 859: xoperands[0] = operands[0]; ! 860: xoperands[1] = gen_rtx(REG, DFmode, 0); ! 861: output_move_double(xoperands); ! 862: } ! 863: ! 864: return \"\"; ! 865: }") ! 866: ! 867: (define_insn "extendhisi2" ! 868: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 869: (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))] ! 870: "" ! 871: "movbhw %1, %0") ! 872: ! 873: (define_insn "extendqisi2" ! 874: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 875: (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))] ! 876: "" ! 877: "movbbw %1, %0") ! 878: ! 879: (define_insn "extendqihi2" ! 880: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 881: (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))] ! 882: "" ! 883: "movbbh %1, %0") ! 884: ! 885: ;; zero-extend move instructions ! 886: ! 887: (define_insn "zero_extendhisi2" ! 888: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 889: (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))] ! 890: "" ! 891: "movzhw %1, %0") ! 892: ! 893: (define_insn "zero_extendqisi2" ! 894: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 895: (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))] ! 896: "" ! 897: "movzbw %1, %0") ! 898: ! 899: (define_insn "zero_extendqihi2" ! 900: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") ! 901: (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))] ! 902: "" ! 903: "movzbh %1, %0") ! 904: ! 905: ;; bit field instructions ! 906: ! 907: (define_insn "extzv" ! 908: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 909: (zero_extract:SI (match_operand:SI 1 "general_operand" "mri") ! 910: (match_operand:SI 2 "immediate_operand" "i") ! 911: (match_operand:SI 3 "general_operand" "mri")))] ! 912: "" ! 913: "* ! 914: { ! 915: ! 916: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); ! 917: output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands); ! 918: ! 919: return \"\"; ! 920: }") ! 921: ! 922: (define_insn "" ! 923: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 924: (zero_extract:SI (match_operand:HI 1 "general_operand" "mri") ! 925: (match_operand:SI 2 "immediate_operand" "i") ! 926: (match_operand:SI 3 "general_operand" "mri")))] ! 927: "" ! 928: "* ! 929: { ! 930: ! 931: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); ! 932: output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands); ! 933: ! 934: return \"\"; ! 935: }") ! 936: ! 937: (define_insn "" ! 938: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") ! 939: (zero_extract:SI (match_operand:QI 1 "general_operand" "mri") ! 940: (match_operand:SI 2 "immediate_operand" "i") ! 941: (match_operand:SI 3 "general_operand" "mri")))] ! 942: "" ! 943: "* ! 944: { ! 945: ! 946: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); ! 947: output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands); ! 948: ! 949: return \"\"; ! 950: }") ! 951: ! 952: (define_insn "insv" ! 953: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr") ! 954: (match_operand:SI 1 "immediate_operand" "i") ! 955: (match_operand:SI 2 "general_operand" "mri")) ! 956: (match_operand:SI 3 "general_operand" "mri"))] ! 957: "" ! 958: "* ! 959: { ! 960: ! 961: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); ! 962: output_asm_insn(\"INSFW %1, %2, %3, %0\",operands); ! 963: ! 964: return \"\"; ! 965: }") ! 966: ! 967: (define_insn "" ! 968: [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr") ! 969: (match_operand:SI 1 "immediate_operand" "i") ! 970: (match_operand:SI 2 "general_operand" "mri")) ! 971: (match_operand:SI 3 "general_operand" "mri"))] ! 972: "" ! 973: "* ! 974: { ! 975: ! 976: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); ! 977: output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands); ! 978: ! 979: return \"\"; ! 980: }") ! 981: ! 982: (define_insn "" ! 983: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr") ! 984: (match_operand:SI 1 "immediate_operand" "i") ! 985: (match_operand:SI 2 "general_operand" "mri")) ! 986: (match_operand:SI 3 "general_operand" "mri"))] ! 987: "" ! 988: "* ! 989: { ! 990: ! 991: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); ! 992: output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands); ! 993: ! 994: return \"\"; ! 995: }") ! 996: ! 997: ;; conditional branch instructions ! 998: ! 999: (define_insn "beq" ! 1000: [(set (pc) (if_then_else (eq (cc0) (const_int 0)) ! 1001: (label_ref (match_operand 0 "" "")) ! 1002: (pc)))] ! 1003: "" ! 1004: "je %l0") ! 1005: ! 1006: (define_insn "bne" ! 1007: [(set (pc) (if_then_else (ne (cc0) (const_int 0)) ! 1008: (label_ref (match_operand 0 "" "")) ! 1009: (pc)))] ! 1010: "" ! 1011: "jne %l0") ! 1012: ! 1013: (define_insn "bgt" ! 1014: [(set (pc) (if_then_else (gt (cc0) (const_int 0)) ! 1015: (label_ref (match_operand 0 "" "")) ! 1016: (pc)))] ! 1017: "" ! 1018: "jg %l0") ! 1019: ! 1020: (define_insn "bgtu" ! 1021: [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) ! 1022: (label_ref (match_operand 0 "" "")) ! 1023: (pc)))] ! 1024: "" ! 1025: "jgu %l0") ! 1026: ! 1027: (define_insn "blt" ! 1028: [(set (pc) (if_then_else (lt (cc0) (const_int 0)) ! 1029: (label_ref (match_operand 0 "" "")) ! 1030: (pc)))] ! 1031: "" ! 1032: "jl %l0") ! 1033: ! 1034: (define_insn "bltu" ! 1035: [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) ! 1036: (label_ref (match_operand 0 "" "")) ! 1037: (pc)))] ! 1038: "" ! 1039: "jlu %l0") ! 1040: ! 1041: (define_insn "bge" ! 1042: [(set (pc) (if_then_else (ge (cc0) (const_int 0)) ! 1043: (label_ref (match_operand 0 "" "")) ! 1044: (pc)))] ! 1045: "" ! 1046: "jge %l0") ! 1047: ! 1048: (define_insn "bgeu" ! 1049: [(set (pc) (if_then_else (geu (cc0) (const_int 0)) ! 1050: (label_ref (match_operand 0 "" "")) ! 1051: (pc)))] ! 1052: "" ! 1053: "jgeu %l0") ! 1054: ! 1055: (define_insn "ble" ! 1056: [(set (pc) (if_then_else (le (cc0) (const_int 0)) ! 1057: (label_ref (match_operand 0 "" "")) ! 1058: (pc)))] ! 1059: "" ! 1060: "jle %l0") ! 1061: ! 1062: (define_insn "bleu" ! 1063: [(set (pc) (if_then_else (leu (cc0) (const_int 0)) ! 1064: (label_ref (match_operand 0 "" "")) ! 1065: (pc)))] ! 1066: "" ! 1067: "jleu %l0") ! 1068: ! 1069: ;; reverse-conditional branch instructions ! 1070: ! 1071: (define_insn "" ! 1072: [(set (pc) (if_then_else (eq (cc0) (const_int 0)) ! 1073: (pc) ! 1074: (label_ref (match_operand 0 "" ""))))] ! 1075: "" ! 1076: "jne %l0") ! 1077: ! 1078: (define_insn "" ! 1079: [(set (pc) (if_then_else (ne (cc0) (const_int 0)) ! 1080: (pc) ! 1081: (label_ref (match_operand 0 "" ""))))] ! 1082: "" ! 1083: "je %l0") ! 1084: ! 1085: (define_insn "" ! 1086: [(set (pc) (if_then_else (gt (cc0) (const_int 0)) ! 1087: (pc) ! 1088: (label_ref (match_operand 0 "" ""))))] ! 1089: "" ! 1090: "jle %l0") ! 1091: ! 1092: (define_insn "" ! 1093: [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) ! 1094: (pc) ! 1095: (label_ref (match_operand 0 "" ""))))] ! 1096: "" ! 1097: "jleu %l0") ! 1098: ! 1099: (define_insn "" ! 1100: [(set (pc) (if_then_else (lt (cc0) (const_int 0)) ! 1101: (pc) ! 1102: (label_ref (match_operand 0 "" ""))))] ! 1103: "" ! 1104: "jge %l0") ! 1105: ! 1106: (define_insn "" ! 1107: [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) ! 1108: (pc) ! 1109: (label_ref (match_operand 0 "" ""))))] ! 1110: "" ! 1111: "jgeu %l0") ! 1112: ! 1113: (define_insn "" ! 1114: [(set (pc) (if_then_else (ge (cc0) (const_int 0)) ! 1115: (pc) ! 1116: (label_ref (match_operand 0 "" ""))))] ! 1117: "" ! 1118: "jl %l0") ! 1119: ! 1120: (define_insn "" ! 1121: [(set (pc) (if_then_else (geu (cc0) (const_int 0)) ! 1122: (pc) ! 1123: (label_ref (match_operand 0 "" ""))))] ! 1124: "" ! 1125: "jlu %l0") ! 1126: ! 1127: (define_insn "" ! 1128: [(set (pc) (if_then_else (le (cc0) (const_int 0)) ! 1129: (pc) ! 1130: (label_ref (match_operand 0 "" ""))))] ! 1131: "" ! 1132: "jg %l0") ! 1133: ! 1134: (define_insn "" ! 1135: [(set (pc) (if_then_else (leu (cc0) (const_int 0)) ! 1136: (pc) ! 1137: (label_ref (match_operand 0 "" ""))))] ! 1138: "" ! 1139: "jgu %l0") ! 1140: ! 1141: ;; call instructions ! 1142: ! 1143: (define_insn "call" ! 1144: [(call (match_operand:QI 0 "memory_operand" "m") ! 1145: (match_operand:SI 1 "immediate_operand" "i"))] ! 1146: "" ! 1147: "call %1/4, %0") ! 1148: ! 1149: (define_insn "call_value" ! 1150: [(set (match_operand 0 "register_operand" "=r") ! 1151: (call (match_operand:QI 1 "memory_operand" "m") ! 1152: (match_operand:SI 2 "immediate_operand" "i")))] ! 1153: "" ! 1154: "call %2/4, %1") ! 1155: ! 1156: ;; No-op instruction ! 1157: ! 1158: (define_insn "nop" ! 1159: [(const_int 0)] ! 1160: "" ! 1161: "NOP") ! 1162: ! 1163: ;; jump through a dispatch table instruction ! 1164: ! 1165: (define_expand "casesi" ! 1166: [(use (match_operand:SI 0 "general_operand" "mri")) ! 1167: (set (cc0) (compare (match_dup 5) ! 1168: (match_operand:SI 1 "general_operand" "mri"))) ! 1169: (set (pc) (if_then_else (lt (cc0) (const_int 0)) ! 1170: (label_ref (match_operand 4 "" "")) ! 1171: (pc))) ! 1172: (set (match_dup 5) (minus:SI (match_dup 5) ! 1173: (match_dup 1))) ! 1174: (set (cc0) (compare (match_dup 5) ! 1175: (match_operand:SI 2 "general_operand" "mri"))) ! 1176: (set (pc) (if_then_else (gtu (cc0) (const_int 0)) ! 1177: (label_ref (match_operand 4 "" "")) ! 1178: (pc))) ! 1179: (set (match_dup 5) (ashift:SI (match_dup 5) ! 1180: (const_int 2))) ! 1181: (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" "")) ! 1182: (match_dup 5))))] ! 1183: "" ! 1184: " ! 1185: { ! 1186: operands[5] = gen_reg_rtx(GET_MODE (operands[0])); ! 1187: emit_move_insn(operands[5], operands[0]); ! 1188: }") ! 1189: ! 1190: ;; jump instructions ! 1191: ! 1192: (define_insn "" ! 1193: [(set (pc) (mem:SI (match_operand:SI 0 "address_operand" "p")))] ! 1194: "GET_CODE (operands[0]) != MEM" ! 1195: "jmp *%a0") ! 1196: ! 1197: (define_insn "indirect_jump" ! 1198: [(set (pc) (match_operand:SI 0 "address_operand" "p"))] ! 1199: "" ! 1200: "jmp %a0") ! 1201: ! 1202: (define_insn "jump" ! 1203: [(set (pc) (label_ref (match_operand 0 "" "")))] ! 1204: "" ! 1205: "jmp %l0") ! 1206: ! 1207: ;; peephole optimizations ! 1208: ! 1209: (define_peephole ! 1210: [(set (match_operand:SI 0 "register_operand" "=r") ! 1211: (match_operand:SI 1 "nonimmediate_operand" "or")) ! 1212: (set (match_operand:SI 2 "register_operand" "=r") ! 1213: (mem:SI (match_dup 0)))] ! 1214: "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))" ! 1215: "movw %a1, %0") ! 1216: ! 1217: (define_peephole ! 1218: [(set (match_operand:SI 0 "register_operand" "=r") ! 1219: (match_operand:SI 1 "nonimmediate_operand" "or")) ! 1220: (set (match_operand:HI 2 "register_operand" "=r") ! 1221: (mem:HI (match_dup 0)))] ! 1222: "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))" ! 1223: "movh %a1, %0") ! 1224: ! 1225: (define_peephole ! 1226: [(set (match_operand:SI 0 "register_operand" "=r") ! 1227: (match_operand:SI 1 "nonimmediate_operand" "or")) ! 1228: (set (match_operand:QI 2 "register_operand" "=r") ! 1229: (mem:QI (match_dup 0)))] ! 1230: "REGNO (operands[0]) == REGNO (operands[2]) && (REG_P (operands[1]) || offsettable_memref_p (operands[1]))" ! 1231: "movb %a1, %0")
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