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1.1.1.2 ! root 1: ;; Machine description for GNU compiler, AT&T we32000 Version ! 2: ;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by John Wehle ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 1, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: 22: ;;- instruction definitions 23: 24: ;;- @@The original PO technology requires these to be ordered by speed, 25: ;;- @@ so that assigner will pick the fastest. 26: 27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28: 29: ;;- When naming insn's (operand 0 of define_insn) be careful about using 30: ;;- names from other targets machine descriptions. 31: 32: ;; move instructions 33: 34: (define_insn "" 35: [(set (match_operand:DF 0 "push_operand" "=m") 36: (match_operand:DF 1 "general_operand" "mrF"))] 37: "" 38: "* 39: { 40: output_push_double(&operands[1]); 41: 42: return \"\"; 43: }") 44: 45: (define_insn "movdf" 46: [(set (match_operand:DF 0 "nonimmediate_operand" "=mr") 47: (match_operand:DF 1 "general_operand" "mrF"))] 48: "" 49: "* 50: { 51: output_move_double(operands); 52: 53: return \"\"; 54: }") 55: 56: (define_insn "" 57: [(set (match_operand:SF 0 "push_operand" "=m") 58: (match_operand:SF 1 "general_operand" "mrF"))] 59: "" 60: "pushw %1") 61: 62: (define_insn "movsf" 63: [(set (match_operand:SF 0 "nonimmediate_operand" "=mr") 64: (match_operand:SF 1 "general_operand" "mrF"))] 65: "" 66: "movw %1, %0") 67: 68: (define_insn "" 69: [(set (match_operand:DI 0 "push_operand" "=m") 70: (match_operand:DI 1 "general_operand" "mriF"))] 71: "" 72: "* 73: { 74: output_push_double(&operands[1]); 75: 76: return \"\"; 77: }") 78: 79: (define_insn "movdi" 80: [(set (match_operand:DI 0 "nonimmediate_operand" "=mr") 81: (match_operand:DI 1 "general_operand" "mriF"))] 82: "" 83: "* 84: { 85: output_move_double(operands); 86: 87: return \"\"; 88: }") 89: 90: (define_insn "" 91: [(set (match_operand:SI 0 "push_operand" "=m") 92: (match_operand:SI 1 "general_operand" "mri"))] 93: "" 94: "pushw %1") 95: 96: (define_insn "movsi" 97: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 98: (match_operand:SI 1 "general_operand" "mri"))] 99: "" 100: "movw %1, %0") 101: 102: (define_insn "movhi" 103: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 104: (match_operand:HI 1 "general_operand" "mri"))] 105: "" 106: "movh %1, %0") 107: 108: (define_insn "movqi" 109: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 110: (match_operand:QI 1 "general_operand" "mri"))] 111: "" 112: "movb %1, %0") 113: 114: ;; add instructions 115: 116: (define_insn "" 117: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") 118: (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") 119: (match_operand:DI 2 "general_operand" "oriF")))] 120: "" 121: "* 122: { 123: rtx label[1]; 124: rtx lsw_operands[3]; 125: 126: if (GET_CODE (operands[0]) == REG) 127: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); 128: else 129: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) 130: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); 131: else 132: abort(); 133: 134: if (GET_CODE (operands[2]) == REG) 135: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); 136: else 137: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) 138: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); 139: else 140: if (GET_CODE (operands[2]) == CONST_DOUBLE) 141: { 142: lsw_operands[2] = gen_rtx(CONST_INT, SImode, 143: CONST_DOUBLE_HIGH(operands[2])); 144: operands[2] = gen_rtx(CONST_INT, SImode, 145: CONST_DOUBLE_LOW(operands[2])); 146: } 147: else 148: if (GET_CODE (operands[2]) == CONST_INT) 149: { 150: lsw_operands[2] = operands[2]; 151: operands[2] = const0_rtx; 152: } 153: else 154: abort(); 155: 156: label[0] = gen_label_rtx(); 157: LABEL_NUSES(label[0]) = 1; 158: 159: output_asm_insn(\"addw2 %2, %0\", operands); 160: output_asm_insn(\"addw2 %2, %0\", lsw_operands); 161: output_asm_insn(\"BCCB %l0\", label); 162: output_asm_insn(\"INCW %0\", operands); 163: output_asm_insn(\"%l0:\", label); 164: 165: return \"\"; 166: }") 167: 168: (define_insn "adddi3" 169: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") 170: (plus:DI (match_operand:DI 1 "general_operand" "oriF") 171: (match_operand:DI 2 "general_operand" "oriF")))] 172: "" 173: "* 174: { 175: rtx label[1]; 176: rtx lsw_operands[3]; 177: 178: if (GET_CODE (operands[0]) == REG) 179: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); 180: else 181: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) 182: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); 183: else 184: abort(); 185: 186: if (GET_CODE (operands[1]) == REG) 187: lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1); 188: else 189: if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) 190: lsw_operands[1] = adj_offsettable_operand(operands[1], 4); 191: else 192: if (GET_CODE (operands[1]) == CONST_DOUBLE) 193: { 194: lsw_operands[1] = gen_rtx(CONST_INT, SImode, 195: CONST_DOUBLE_HIGH(operands[1])); 196: operands[1] = gen_rtx(CONST_INT, SImode, 197: CONST_DOUBLE_LOW(operands[1])); 198: } 199: else 200: if (GET_CODE (operands[1]) == CONST_INT) 201: { 202: lsw_operands[1] = operands[1]; 203: operands[1] = const0_rtx; 204: } 205: else 206: abort(); 207: 208: if (GET_CODE (operands[2]) == REG) 209: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); 210: else 211: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) 212: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); 213: else 214: if (GET_CODE (operands[2]) == CONST_DOUBLE) 215: { 216: lsw_operands[2] = gen_rtx(CONST_INT, SImode, 217: CONST_DOUBLE_HIGH(operands[2])); 218: operands[2] = gen_rtx(CONST_INT, SImode, 219: CONST_DOUBLE_LOW(operands[2])); 220: } 221: else 222: if (GET_CODE (operands[2]) == CONST_INT) 223: { 224: lsw_operands[2] = operands[2]; 225: operands[2] = const0_rtx; 226: } 227: else 228: abort(); 229: 230: label[0] = gen_label_rtx(); 231: LABEL_NUSES(label[0]) = 1; 232: 233: output_asm_insn(\"addw3 %2, %1, %0\", operands); 234: output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands); 235: output_asm_insn(\"BCCB %l0\", label); 236: output_asm_insn(\"INCW %0\", operands); 237: output_asm_insn(\"%l0:\", label); 238: 239: return \"\"; 240: }") 241: 242: (define_insn "" 243: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 244: (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") 245: (match_operand:SI 2 "general_operand" "mri")))] 246: "" 247: "addw2 %2, %0") 248: 249: (define_insn "addsi3" 250: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 251: (plus:SI (match_operand:SI 1 "general_operand" "mri") 252: (match_operand:SI 2 "general_operand" "mri")))] 253: "" 254: "addw3 %2, %1, %0") 255: 256: (define_insn "" 257: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 258: (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0") 259: (match_operand:HI 2 "general_operand" "mri")))] 260: "" 261: "addh2 %2, %0") 262: 263: (define_insn "addhi3" 264: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 265: (plus:HI (match_operand:HI 1 "general_operand" "mri") 266: (match_operand:HI 2 "general_operand" "mri")))] 267: "" 268: "addh3 %2, %1, %0") 269: 270: (define_insn "" 271: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 272: (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0") 273: (match_operand:QI 2 "general_operand" "mri")))] 274: "" 275: "addb2 %2, %0") 276: 277: (define_insn "addqi3" 278: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 279: (plus:QI (match_operand:QI 1 "general_operand" "mri") 280: (match_operand:QI 2 "general_operand" "mri")))] 281: "" 282: "addb3 %2, %1, %0") 283: 284: ;; subtract instructions 285: 286: (define_insn "" 287: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") 288: (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0") 289: (match_operand:DI 2 "general_operand" "oriF")))] 290: "" 291: "* 292: { 293: rtx label[1]; 294: rtx lsw_operands[3]; 295: 296: if (GET_CODE (operands[0]) == REG) 297: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); 298: else 299: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) 300: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); 301: else 302: abort(); 303: 304: if (GET_CODE (operands[2]) == REG) 305: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); 306: else 307: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) 308: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); 309: else 310: if (GET_CODE (operands[2]) == CONST_DOUBLE) 311: { 312: lsw_operands[2] = gen_rtx(CONST_INT, SImode, 313: CONST_DOUBLE_HIGH(operands[2])); 314: operands[2] = gen_rtx(CONST_INT, SImode, 315: CONST_DOUBLE_LOW(operands[2])); 316: } 317: else 318: if (GET_CODE (operands[2]) == CONST_INT) 319: { 320: lsw_operands[2] = operands[2]; 321: operands[2] = const0_rtx; 322: } 323: else 324: abort(); 325: 326: label[0] = gen_label_rtx(); 327: LABEL_NUSES(label[0]) = 1; 328: 329: output_asm_insn(\"subw2 %2, %0\", operands); 330: output_asm_insn(\"subw2 %2, %0\", lsw_operands); 331: output_asm_insn(\"BCCB %l0\", label); 332: output_asm_insn(\"DECW %0\", operands); 333: output_asm_insn(\"%l0:\", label); 334: 335: return \"\"; 336: }") 337: 338: (define_insn "subdi3" 339: [(set (match_operand:DI 0 "nonimmediate_operand" "=&or") 340: (minus:DI (match_operand:DI 1 "general_operand" "oriF") 341: (match_operand:DI 2 "general_operand" "oriF")))] 342: "" 343: "* 344: { 345: rtx label[1]; 346: rtx lsw_operands[3]; 347: 348: if (GET_CODE (operands[0]) == REG) 349: lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1); 350: else 351: if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0])) 352: lsw_operands[0] = adj_offsettable_operand(operands[0], 4); 353: else 354: abort(); 355: 356: if (GET_CODE (operands[1]) == REG) 357: lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1); 358: else 359: if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) 360: lsw_operands[1] = adj_offsettable_operand(operands[1], 4); 361: else 362: if (GET_CODE (operands[1]) == CONST_DOUBLE) 363: { 364: lsw_operands[1] = gen_rtx(CONST_INT, SImode, 365: CONST_DOUBLE_HIGH(operands[1])); 366: operands[1] = gen_rtx(CONST_INT, SImode, 367: CONST_DOUBLE_LOW(operands[1])); 368: } 369: else 370: if (GET_CODE (operands[1]) == CONST_INT) 371: { 372: lsw_operands[1] = operands[1]; 373: operands[1] = const0_rtx; 374: } 375: else 376: abort(); 377: 378: if (GET_CODE (operands[2]) == REG) 379: lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1); 380: else 381: if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2])) 382: lsw_operands[2] = adj_offsettable_operand(operands[2], 4); 383: else 384: if (GET_CODE (operands[2]) == CONST_DOUBLE) 385: { 386: lsw_operands[2] = gen_rtx(CONST_INT, SImode, 387: CONST_DOUBLE_HIGH(operands[2])); 388: operands[2] = gen_rtx(CONST_INT, SImode, 389: CONST_DOUBLE_LOW(operands[2])); 390: } 391: else 392: if (GET_CODE (operands[2]) == CONST_INT) 393: { 394: lsw_operands[2] = operands[2]; 395: operands[2] = const0_rtx; 396: } 397: else 398: abort(); 399: 400: label[0] = gen_label_rtx(); 401: LABEL_NUSES(label[0]) = 1; 402: 403: output_asm_insn(\"subw3 %2, %1, %0\", operands); 404: output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands); 405: output_asm_insn(\"BCCB %l0\", label); 406: output_asm_insn(\"DECW %0\", operands); 407: output_asm_insn(\"%l0:\", label); 408: 409: return \"\"; 410: }") 411: 412: (define_insn "" 413: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 414: (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0") 415: (match_operand:SI 2 "general_operand" "mri")))] 416: "" 417: "subw2 %2, %0") 418: 419: (define_insn "subsi3" 420: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 421: (minus:SI (match_operand:SI 1 "general_operand" "mri") 422: (match_operand:SI 2 "general_operand" "mri")))] 423: "" 424: "subw3 %2, %1, %0") 425: 426: (define_insn "" 427: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 428: (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0") 429: (match_operand:HI 2 "general_operand" "mri")))] 430: "" 431: "subh2 %2, %0") 432: 433: (define_insn "subhi3" 434: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 435: (minus:HI (match_operand:HI 1 "general_operand" "mri") 436: (match_operand:HI 2 "general_operand" "mri")))] 437: "" 438: "subh3 %2, %1, %0") 439: 440: (define_insn "" 441: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 442: (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0") 443: (match_operand:QI 2 "general_operand" "mri")))] 444: "" 445: "subb2 %2, %0") 446: 447: (define_insn "subqi3" 448: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 449: (minus:QI (match_operand:QI 1 "general_operand" "mri") 450: (match_operand:QI 2 "general_operand" "mri")))] 451: "" 452: "subb3 %2, %1, %0") 453: 454: ;; signed multiply instructions 455: 456: (define_insn "" 457: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 458: (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0") 459: (match_operand:SI 2 "general_operand" "mri")))] 460: "" 461: "mulw2 %2, %0") 462: 463: (define_insn "mulsi3" 464: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 465: (mult:SI (match_operand:SI 1 "general_operand" "mri") 466: (match_operand:SI 2 "general_operand" "mri")))] 467: "" 468: "mulw3 %2, %1, %0") 469: 470: ;; signed divide instructions 471: 472: (define_insn "" 473: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 474: (div:SI (match_operand:SI 1 "nonimmediate_operand" "0") 475: (match_operand:SI 2 "general_operand" "mri")))] 476: "" 477: "divw2 %2, %0") 478: 479: (define_insn "divsi3" 480: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 481: (div:SI (match_operand:SI 1 "general_operand" "mri") 482: (match_operand:SI 2 "general_operand" "mri")))] 483: "" 484: "divw3 %2, %1, %0") 485: 486: ;; signed modulus instruction 487: 488: (define_insn "" 489: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 490: (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0") 491: (match_operand:SI 2 "general_operand" "mri")))] 492: "" 493: "modw2 %2, %0") 494: 495: (define_insn "modsi3" 496: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 497: (mod:SI (match_operand:SI 1 "general_operand" "mri") 498: (match_operand:SI 2 "general_operand" "mri")))] 499: "" 500: "modw3 %2, %1, %0") 501: 502: ;; unsigned divide instruction 503: 504: (define_insn "" 505: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 506: (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0") 507: (match_operand:SI 2 "general_operand" "mri")))] 508: "" 509: "udivw2 %2, %0") 510: 511: (define_insn "udivsi3" 512: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 513: (udiv:SI (match_operand:SI 1 "general_operand" "mri") 514: (match_operand:SI 2 "general_operand" "mri")))] 515: "" 516: "udivw3 %2, %1, %0") 517: 518: ;; unsigned modulus instruction 519: 520: (define_insn "" 521: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 522: (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0") 523: (match_operand:SI 2 "general_operand" "mri")))] 524: "" 525: "umodw2 %2, %0") 526: 527: (define_insn "umodsi3" 528: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 529: (umod:SI (match_operand:SI 1 "general_operand" "mri") 530: (match_operand:SI 2 "general_operand" "mri")))] 531: "" 532: "umodw3 %2, %1, %0") 533: 534: ;; logical-and instructions 535: 536: (define_insn "" 537: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 538: (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") 539: (match_operand:SI 2 "general_operand" "mri")))] 540: "" 541: "andw2 %2, %0") 542: 543: (define_insn "andsi3" 544: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 545: (and:SI (match_operand:SI 1 "general_operand" "mri") 546: (match_operand:SI 2 "general_operand" "mri")))] 547: "" 548: "andw3 %2, %1, %0") 549: 550: (define_insn "" 551: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 552: (and:HI (match_operand:HI 1 "nonimmediate_operand" "0") 553: (match_operand:HI 2 "general_operand" "mri")))] 554: "" 555: "andh2 %2, %0") 556: 557: (define_insn "andhi3" 558: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 559: (and:HI (match_operand:HI 1 "general_operand" "mri") 560: (match_operand:HI 2 "general_operand" "mri")))] 561: "" 562: "andh3 %2, %1, %0") 563: 564: (define_insn "" 565: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 566: (and:QI (match_operand:QI 1 "nonimmediate_operand" "0") 567: (match_operand:QI 2 "general_operand" "mri")))] 568: "" 569: "andb2 %2, %0") 570: 571: (define_insn "andqi3" 572: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 573: (and:QI (match_operand:QI 1 "general_operand" "mri") 574: (match_operand:QI 2 "general_operand" "mri")))] 575: "" 576: "andb3 %2, %1, %0") 577: 578: ;; inclusive-or instructions 579: 580: (define_insn "" 581: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 582: (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") 583: (match_operand:SI 2 "general_operand" "mri")))] 584: "" 585: "orw2 %2, %0") 586: 587: (define_insn "iorsi3" 588: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 589: (ior:SI (match_operand:SI 1 "general_operand" "mri") 590: (match_operand:SI 2 "general_operand" "mri")))] 591: "" 592: "orw3 %2, %1, %0") 593: 594: (define_insn "" 595: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 596: (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0") 597: (match_operand:HI 2 "general_operand" "mri")))] 598: "" 599: "orh2 %2, %0") 600: 601: (define_insn "iorhi3" 602: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 603: (ior:HI (match_operand:HI 1 "general_operand" "mri") 604: (match_operand:HI 2 "general_operand" "mri")))] 605: "" 606: "orh3 %2, %1, %0") 607: 608: (define_insn "" 609: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 610: (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0") 611: (match_operand:QI 2 "general_operand" "mri")))] 612: "" 613: "orb2 %2, %0") 614: 615: (define_insn "iorqi3" 616: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 617: (ior:QI (match_operand:QI 1 "general_operand" "mri") 618: (match_operand:QI 2 "general_operand" "mri")))] 619: "" 620: "orb3 %2, %1, %0") 621: 622: ;; exclusive-or instructions 623: 624: (define_insn "" 625: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 626: (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0") 627: (match_operand:SI 2 "general_operand" "mri")))] 628: "" 629: "xorw2 %2, %0") 630: 631: (define_insn "xorsi3" 632: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 633: (xor:SI (match_operand:SI 1 "general_operand" "mri") 634: (match_operand:SI 2 "general_operand" "mri")))] 635: "" 636: "xorw3 %2, %1, %0") 637: 638: (define_insn "" 639: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 640: (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0") 641: (match_operand:HI 2 "general_operand" "mri")))] 642: "" 643: "xorh2 %2, %0") 644: 645: (define_insn "xorhi3" 646: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 647: (xor:HI (match_operand:HI 1 "general_operand" "mri") 648: (match_operand:HI 2 "general_operand" "mri")))] 649: "" 650: "xorh3 %2, %1, %0") 651: 652: (define_insn "" 653: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 654: (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0") 655: (match_operand:QI 2 "general_operand" "mri")))] 656: "" 657: "xorb2 %2, %0") 658: 659: (define_insn "xorqi3" 660: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 661: (xor:QI (match_operand:QI 1 "general_operand" "mri") 662: (match_operand:QI 2 "general_operand" "mri")))] 663: "" 664: "xorb3 %2, %1, %0") 665: 666: ;; arithmetic shift instructions 667: 668: (define_insn "ashlsi3" 669: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 670: (ashift:SI (match_operand:SI 1 "general_operand" "mri") 671: (match_operand:SI 2 "general_operand" "mri")))] 672: "" 673: "LLSW3 %2, %1, %0") 674: 675: (define_insn "ashrsi3" 676: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 677: (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri") 678: (match_operand:SI 2 "general_operand" "mri")))] 679: "" 680: "ARSW3 %2, %1, %0") 681: 682: ;; logical shift instructions 683: 684: (define_insn "lshrsi3" 685: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 686: (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri") 687: (match_operand:SI 2 "general_operand" "mri")))] 688: "" 689: "LRSW3 %2, %1, %0") 690: 691: ;; rotate instruction 692: 693: (define_insn "rotrsi3" 694: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 695: (rotatert: SI (match_operand:SI 1 "general_operand" "mri") 696: (match_operand:SI 2 "general_operand" "mri")))] 697: "" 698: "ROTW %2, %1, %0") 699: 700: ;; negate instructions 701: 702: (define_insn "negsi2" 703: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 704: (neg:SI (match_operand:SI 1 "general_operand" "mri")))] 705: "" 706: "mnegw %1, %0") 707: 708: (define_insn "neghi2" 709: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 710: (neg:HI (match_operand:HI 1 "general_operand" "mri")))] 711: "" 712: "mnegh %1, %0") 713: 714: ;; complement instructions 715: 716: (define_insn "one_cmplsi2" 717: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 718: (not:SI (match_operand:SI 1 "general_operand" "mri")))] 719: "" 720: "mcomw %1, %0") 721: 722: (define_insn "one_cmplhi2" 723: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 724: (not:HI (match_operand:HI 1 "general_operand" "mri")))] 725: "" 726: "mcomh %1, %0") 727: 728: (define_insn "one_cmplqi2" 729: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 730: (not:QI (match_operand:QI 1 "general_operand" "mri")))] 731: "" 732: "mcomb %1, %0") 733: 734: ;; test instruction 735: 736: ;; We don't want to allow a constant operand for test insns because 737: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 738: ;; be folded while optimizing anyway. 739: 740: (define_insn "tstsi" 741: [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))] 742: "" 743: "TSTW %0") 744: 745: (define_insn "tsthi" 746: [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))] 747: "" 748: "TSTH %0") 749: 750: (define_insn "tstqi" 751: [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))] 752: "" 753: "TSTB {sbyte}%0") 754: 755: ;; compare instruction 756: 757: (define_insn "cmpsi" 758: [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr") 759: (match_operand:SI 1 "general_operand" "mri")))] 760: "" 761: "CMPW %1, %0") 762: 763: (define_insn "cmphi" 764: [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr") 765: (match_operand:HI 1 "general_operand" "mri")))] 766: "" 767: "* 768: { 769: 770: if (GET_CODE (operands[1]) == CONST_INT && 771: ((unsigned long)INTVAL (operands[1]) & 0x8000L)) 772: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffff0000L); 773: 774: output_asm_insn(\"CMPH %1, %0\",operands); 775: 776: return \"\"; 777: }") 778: 779: (define_insn "cmpqi" 780: [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr") 781: (match_operand:QI 1 "general_operand" "mri")))] 782: "" 783: "* 784: { 785: 786: if (GET_CODE (operands[1]) == CONST_INT && 787: ((unsigned long)INTVAL (operands[1]) & 0x80L)) 788: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) | 0xffffff00L); 789: 790: output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands); 791: 792: return \"\"; 793: }") 794: 795: ;; truncate instructions 796: 797: (define_insn "" 798: [(set (match_operand:SF 0 "register_operand" "=r") 799: (float_truncate:SF (match_operand:DF 1 "general_operand" "orF"))) 800: (clobber (reg:SI 1)) 801: (clobber (reg:SI 2))] 802: "REGNO (operands[0]) == 0" 803: "* 804: { 805: output_push_double(&operands[1]); 806: output_asm_insn(\"call &2, _fdtos\", operands); 807: 808: return \"\"; 809: }") 810: 811: (define_expand "truncdfsf2" 812: [(parallel [(set (reg:SF 0) 813: (float_truncate:SF (match_operand:DF 1 "general_operand" "orF"))) 814: (clobber (reg:SI 1)) 815: (clobber (reg:SI 2))]) 816: (set (match_operand:SF 0 "nonimmediate_operand" "=mr") 817: (reg:SF 0))] 818: "" 819: "") 820: 821: (define_insn "truncsihi2" 822: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 823: (truncate:HI (match_operand:SI 1 "general_operand" "mri")))] 824: "" 825: "movtwh %1, %0") 826: 827: (define_insn "truncsiqi2" 828: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 829: (truncate:QI (match_operand:SI 1 "general_operand" "mri")))] 830: "" 831: "movtwb %1, %0") 832: 833: (define_insn "trunchiqi2" 834: [(set (match_operand:QI 0 "nonimmediate_operand" "=mr") 835: (truncate:QI (match_operand:HI 1 "general_operand" "mri")))] 836: "" 837: "movthb %1, %0") 838: 839: ;; sign-extend move instructions 840: 841: (define_insn "" 842: [(set (match_operand:DF 0 "register_operand" "=r") 843: (float_extend:DF (match_operand:SF 1 "general_operand" "mrF"))) 844: (clobber (reg:SI 2))] 845: "REGNO (operands[0]) == 0" 846: "* 847: { 848: output_asm_insn(\"pushw %1\", operands); 849: output_asm_insn(\"call &1, _fstod\", operands); 850: 851: return \"\"; 852: }") 853: 854: (define_expand "extendsfdf2" 855: [(parallel [(set (reg:DF 0) 856: (float_extend:DF (match_operand:SF 1 "general_operand" "mrF"))) 857: (clobber (reg:SI 2))]) 858: (set (match_operand:DF 0 "nonimmediate_operand" "=or") 859: (reg:DF 0))] 860: "" 861: "") 862: 863: (define_insn "extendhisi2" 864: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 865: (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))] 866: "" 867: "movbhw %1, %0") 868: 869: (define_insn "extendqisi2" 870: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 871: (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))] 872: "" 873: "movbbw %1, %0") 874: 875: (define_insn "extendqihi2" 876: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 877: (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))] 878: "" 879: "movbbh %1, %0") 880: 881: ;; zero-extend move instructions 882: 883: (define_insn "zero_extendhisi2" 884: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 885: (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))] 886: "" 887: "movzhw %1, %0") 888: 889: (define_insn "zero_extendqisi2" 890: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 891: (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))] 892: "" 893: "movzbw %1, %0") 894: 895: (define_insn "zero_extendqihi2" 896: [(set (match_operand:HI 0 "nonimmediate_operand" "=mr") 897: (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))] 898: "" 899: "movzbh %1, %0") 900: 901: ;; bit field instructions 902: 903: (define_insn "extzv" 904: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 905: (zero_extract:SI (match_operand:SI 1 "general_operand" "mri") 906: (match_operand:SI 2 "immediate_operand" "i") 907: (match_operand:SI 3 "general_operand" "mri")))] 908: "" 909: "* 910: { 911: 912: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); 913: output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands); 914: 915: return \"\"; 916: }") 917: 918: (define_insn "" 919: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 920: (zero_extract:SI (match_operand:HI 1 "general_operand" "mri") 921: (match_operand:SI 2 "immediate_operand" "i") 922: (match_operand:SI 3 "general_operand" "mri")))] 923: "" 924: "* 925: { 926: 927: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); 928: output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands); 929: 930: return \"\"; 931: }") 932: 933: (define_insn "" 934: [(set (match_operand:SI 0 "nonimmediate_operand" "=mr") 935: (zero_extract:SI (match_operand:QI 1 "general_operand" "mri") 936: (match_operand:SI 2 "immediate_operand" "i") 937: (match_operand:SI 3 "general_operand" "mri")))] 938: "" 939: "* 940: { 941: 942: operands[2] = gen_rtx(CONST_INT, SImode, INTVAL(operands[2]) - 1); 943: output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands); 944: 945: return \"\"; 946: }") 947: 948: (define_insn "insv" 949: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr") 950: (match_operand:SI 1 "immediate_operand" "i") 951: (match_operand:SI 2 "general_operand" "mri")) 952: (match_operand:SI 3 "general_operand" "mri"))] 953: "" 954: "* 955: { 956: 957: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); 958: output_asm_insn(\"INSFW %1, %2, %3, %0\",operands); 959: 960: return \"\"; 961: }") 962: 963: (define_insn "" 964: [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr") 965: (match_operand:SI 1 "immediate_operand" "i") 966: (match_operand:SI 2 "general_operand" "mri")) 967: (match_operand:SI 3 "general_operand" "mri"))] 968: "" 969: "* 970: { 971: 972: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); 973: output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands); 974: 975: return \"\"; 976: }") 977: 978: (define_insn "" 979: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr") 980: (match_operand:SI 1 "immediate_operand" "i") 981: (match_operand:SI 2 "general_operand" "mri")) 982: (match_operand:SI 3 "general_operand" "mri"))] 983: "" 984: "* 985: { 986: 987: operands[1] = gen_rtx(CONST_INT, SImode, INTVAL(operands[1]) - 1); 988: output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands); 989: 990: return \"\"; 991: }") 992: 993: ;; conditional branch instructions 994: 995: (define_insn "beq" 996: [(set (pc) (if_then_else (eq (cc0) (const_int 0)) 997: (label_ref (match_operand 0 "" "")) 998: (pc)))] 999: "" 1000: "je %l0") 1001: 1002: (define_insn "bne" 1003: [(set (pc) (if_then_else (ne (cc0) (const_int 0)) 1004: (label_ref (match_operand 0 "" "")) 1005: (pc)))] 1006: "" 1007: "jne %l0") 1008: 1009: (define_insn "bgt" 1010: [(set (pc) (if_then_else (gt (cc0) (const_int 0)) 1011: (label_ref (match_operand 0 "" "")) 1012: (pc)))] 1013: "" 1014: "jg %l0") 1015: 1016: (define_insn "bgtu" 1017: [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) 1018: (label_ref (match_operand 0 "" "")) 1019: (pc)))] 1020: "" 1021: "jgu %l0") 1022: 1023: (define_insn "blt" 1024: [(set (pc) (if_then_else (lt (cc0) (const_int 0)) 1025: (label_ref (match_operand 0 "" "")) 1026: (pc)))] 1027: "" 1028: "jl %l0") 1029: 1030: (define_insn "bltu" 1031: [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) 1032: (label_ref (match_operand 0 "" "")) 1033: (pc)))] 1034: "" 1035: "jlu %l0") 1036: 1037: (define_insn "bge" 1038: [(set (pc) (if_then_else (ge (cc0) (const_int 0)) 1039: (label_ref (match_operand 0 "" "")) 1040: (pc)))] 1041: "" 1042: "jge %l0") 1043: 1044: (define_insn "bgeu" 1045: [(set (pc) (if_then_else (geu (cc0) (const_int 0)) 1046: (label_ref (match_operand 0 "" "")) 1047: (pc)))] 1048: "" 1049: "jgeu %l0") 1050: 1051: (define_insn "ble" 1052: [(set (pc) (if_then_else (le (cc0) (const_int 0)) 1053: (label_ref (match_operand 0 "" "")) 1054: (pc)))] 1055: "" 1056: "jle %l0") 1057: 1058: (define_insn "bleu" 1059: [(set (pc) (if_then_else (leu (cc0) (const_int 0)) 1060: (label_ref (match_operand 0 "" "")) 1061: (pc)))] 1062: "" 1063: "jleu %l0") 1064: 1065: ;; reverse-conditional branch instructions 1066: 1067: (define_insn "" 1068: [(set (pc) (if_then_else (eq (cc0) (const_int 0)) 1069: (pc) 1070: (label_ref (match_operand 0 "" ""))))] 1071: "" 1072: "jne %l0") 1073: 1074: (define_insn "" 1075: [(set (pc) (if_then_else (ne (cc0) (const_int 0)) 1076: (pc) 1077: (label_ref (match_operand 0 "" ""))))] 1078: "" 1079: "je %l0") 1080: 1081: (define_insn "" 1082: [(set (pc) (if_then_else (gt (cc0) (const_int 0)) 1083: (pc) 1084: (label_ref (match_operand 0 "" ""))))] 1085: "" 1086: "jle %l0") 1087: 1088: (define_insn "" 1089: [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) 1090: (pc) 1091: (label_ref (match_operand 0 "" ""))))] 1092: "" 1093: "jleu %l0") 1094: 1095: (define_insn "" 1096: [(set (pc) (if_then_else (lt (cc0) (const_int 0)) 1097: (pc) 1098: (label_ref (match_operand 0 "" ""))))] 1099: "" 1100: "jge %l0") 1101: 1102: (define_insn "" 1103: [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) 1104: (pc) 1105: (label_ref (match_operand 0 "" ""))))] 1106: "" 1107: "jgeu %l0") 1108: 1109: (define_insn "" 1110: [(set (pc) (if_then_else (ge (cc0) (const_int 0)) 1111: (pc) 1112: (label_ref (match_operand 0 "" ""))))] 1113: "" 1114: "jl %l0") 1115: 1116: (define_insn "" 1117: [(set (pc) (if_then_else (geu (cc0) (const_int 0)) 1118: (pc) 1119: (label_ref (match_operand 0 "" ""))))] 1120: "" 1121: "jlu %l0") 1122: 1123: (define_insn "" 1124: [(set (pc) (if_then_else (le (cc0) (const_int 0)) 1125: (pc) 1126: (label_ref (match_operand 0 "" ""))))] 1127: "" 1128: "jg %l0") 1129: 1130: (define_insn "" 1131: [(set (pc) (if_then_else (leu (cc0) (const_int 0)) 1132: (pc) 1133: (label_ref (match_operand 0 "" ""))))] 1134: "" 1135: "jgu %l0") 1136: 1137: ;; call instructions 1138: 1139: (define_insn "call" 1140: [(call (match_operand:QI 0 "memory_operand" "m") 1141: (match_operand:SI 1 "immediate_operand" "i"))] 1142: "" 1143: "call %1/4, %0") 1144: 1145: (define_insn "call_value" 1146: [(set (match_operand 0 "register_operand" "=r") 1147: (call (match_operand:QI 1 "memory_operand" "m") 1148: (match_operand:SI 2 "immediate_operand" "i")))] 1149: "" 1150: "call %2/4, %1") 1151: 1152: ;; No-op instruction 1153: 1154: (define_insn "nop" 1155: [(const_int 0)] 1156: "" 1157: "NOP") 1158: 1159: ;; jump through a dispatch table instruction 1160: 1161: (define_expand "casesi" 1162: [(use (match_operand:SI 0 "general_operand" "mri")) 1163: (set (cc0) (compare (match_dup 5) 1164: (match_operand:SI 1 "general_operand" "mri"))) 1165: (set (pc) (if_then_else (lt (cc0) (const_int 0)) 1166: (label_ref (match_operand 4 "" "")) 1167: (pc))) 1168: (set (match_dup 5) (minus:SI (match_dup 5) 1169: (match_dup 1))) 1170: (set (cc0) (compare (match_dup 5) 1171: (match_operand:SI 2 "general_operand" "mri"))) 1172: (set (pc) (if_then_else (gtu (cc0) (const_int 0)) 1173: (label_ref (match_dup 4)) 1174: (pc))) 1175: (set (match_dup 5) (ashift:SI (match_dup 5) 1176: (const_int 2))) 1177: (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" "")) 1178: (match_dup 5))))] 1179: "" 1180: " 1181: { 1182: operands[5] = gen_reg_rtx(GET_MODE (operands[0])); 1183: emit_move_insn(operands[5], operands[0]); 1184: }") 1185: 1186: ;; jump instructions 1187: 1188: (define_insn "indirect_jump" 1189: [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 1190: "" 1191: "jmp %a0") 1192: 1193: (define_insn "jump" 1194: [(set (pc) (label_ref (match_operand 0 "" "")))] 1195: "" 1196: "jmp %l0")
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