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1.1 root 1: /* Medium-level subroutines: convert bit-field store and extract
2: and shifts, multiplies and divides to rtl instructions.
1.1.1.5 ! root 3: Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
1.1 root 4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21:
22: #include "config.h"
23: #include "rtl.h"
24: #include "tree.h"
25: #include "flags.h"
26: #include "insn-flags.h"
27: #include "insn-codes.h"
28: #include "insn-config.h"
29: #include "expr.h"
30: #include "real.h"
31: #include "recog.h"
32:
33: static rtx extract_split_bit_field ();
34: static rtx extract_fixed_bit_field ();
35: static void store_split_bit_field ();
36: static void store_fixed_bit_field ();
37: static rtx mask_rtx ();
38: static rtx lshift_value ();
39:
40: #define CEIL(x,y) (((x) + (y) - 1) / (y))
41:
42: /* Non-zero means multiply instructions are cheaper than shifts. */
43: int mult_is_very_cheap;
44:
45: /* Non-zero means divides or modulus operations are relatively cheap for
46: powers of two, so don't use branches; emit the operation instead.
47: Usually, this will mean that the MD file will emit non-branch
48: sequences. */
49:
50: static int sdiv_pow2_cheap, smod_pow2_cheap;
51:
1.1.1.5 ! root 52: /* For compilers that support multiple targets with different word sizes,
! 53: MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
! 54: is the H8/300(H) compiler. */
! 55:
! 56: #ifndef MAX_BITS_PER_WORD
! 57: #define MAX_BITS_PER_WORD BITS_PER_WORD
! 58: #endif
1.1 root 59:
1.1.1.5 ! root 60: /* Cost of various pieces of RTL. */
! 61: static int add_cost, mult_cost, negate_cost, zero_cost;
! 62: static int shift_cost[MAX_BITS_PER_WORD];
! 63: static int shiftadd_cost[MAX_BITS_PER_WORD];
! 64: static int shiftsub_cost[MAX_BITS_PER_WORD];
1.1 root 65:
66: void
67: init_expmed ()
68: {
1.1.1.5 ! root 69: char *free_point;
1.1 root 70: /* This is "some random pseudo register" for purposes of calling recog
71: to see what insns exist. */
72: rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER);
1.1.1.5 ! root 73: rtx shift_insn, shiftadd_insn, shiftsub_insn;
1.1.1.4 root 74: int dummy;
1.1.1.5 ! root 75: int m;
1.1 root 76:
1.1.1.5 ! root 77: start_sequence ();
! 78:
! 79: /* Since we are on the permanent obstack, we must be sure we save this
! 80: spot AFTER we call start_sequence, since it will reuse the rtl it
! 81: makes. */
! 82:
! 83: free_point = (char *) oballoc (0);
! 84:
! 85: zero_cost = rtx_cost (const0_rtx, 0);
1.1.1.3 root 86: add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
1.1.1.5 ! root 87:
! 88: shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
! 89: gen_rtx (ASHIFT, word_mode, reg,
! 90: const0_rtx)));
! 91:
! 92: shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
! 93: gen_rtx (PLUS, word_mode,
! 94: gen_rtx (MULT, word_mode,
! 95: reg, const0_rtx),
! 96: reg)));
! 97:
! 98: shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
! 99: gen_rtx (MINUS, word_mode,
! 100: gen_rtx (MULT, word_mode,
! 101: reg, const0_rtx),
! 102: reg)));
! 103:
! 104: init_recog ();
! 105:
! 106: shift_cost[0] = 0;
! 107: shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
! 108:
! 109: for (m = 1; m < BITS_PER_WORD; m++)
! 110: {
! 111: shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
! 112:
! 113: XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
! 114: if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
! 115: shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
! 116:
! 117: XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
! 118: = GEN_INT ((HOST_WIDE_INT) 1 << m);
! 119: if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
! 120: shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
! 121:
! 122: XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
! 123: = GEN_INT ((HOST_WIDE_INT) 1 << m);
! 124: if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
! 125: shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
! 126: }
! 127:
1.1.1.3 root 128: mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET);
1.1.1.5 ! root 129: /* For gcc 2.4 keep MULT_COST small to avoid really slow searches
! 130: in synth_mult. */
! 131: mult_cost = MIN (12 * add_cost, mult_cost);
1.1.1.3 root 132: negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
1.1 root 133:
1.1.1.2 root 134: /* 999999 is chosen to avoid any plausible faster special case. */
1.1 root 135: mult_is_very_cheap
1.1.1.4 root 136: = (rtx_cost (gen_rtx (MULT, word_mode, reg, GEN_INT (999999)), SET)
1.1.1.5 ! root 137: < rtx_cost (gen_rtx (ASHIFT, word_mode, reg, GEN_INT (7)), SET));
1.1 root 138:
139: sdiv_pow2_cheap
1.1.1.5 ! root 140: = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET)
! 141: <= 2 * add_cost);
1.1 root 142: smod_pow2_cheap
1.1.1.5 ! root 143: = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET)
! 144: <= 2 * add_cost);
1.1 root 145:
146: /* Free the objects we just allocated. */
1.1.1.5 ! root 147: end_sequence ();
1.1 root 148: obfree (free_point);
149: }
150:
151: /* Return an rtx representing minus the value of X.
152: MODE is the intended mode of the result,
153: useful if X is a CONST_INT. */
154:
155: rtx
156: negate_rtx (mode, x)
157: enum machine_mode mode;
158: rtx x;
159: {
160: if (GET_CODE (x) == CONST_INT)
161: {
1.1.1.4 root 162: HOST_WIDE_INT val = - INTVAL (x);
163: if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
1.1 root 164: {
165: /* Sign extend the value from the bits that are significant. */
1.1.1.4 root 166: if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
167: val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode);
1.1 root 168: else
1.1.1.4 root 169: val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
1.1 root 170: }
1.1.1.4 root 171: return GEN_INT (val);
1.1 root 172: }
173: else
1.1.1.4 root 174: return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0);
1.1 root 175: }
176:
177: /* Generate code to store value from rtx VALUE
178: into a bit-field within structure STR_RTX
179: containing BITSIZE bits starting at bit BITNUM.
180: FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
181: ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
182: TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
183:
184: /* ??? Note that there are two different ideas here for how
185: to determine the size to count bits within, for a register.
186: One is BITS_PER_WORD, and the other is the size of operand 3
187: of the insv pattern. (The latter assumes that an n-bit machine
188: will be able to insert bit fields up to n bits wide.)
189: It isn't certain that either of these is right.
190: extract_bit_field has the same quandary. */
191:
192: rtx
193: store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
194: rtx str_rtx;
195: register int bitsize;
196: int bitnum;
197: enum machine_mode fieldmode;
198: rtx value;
199: int align;
200: int total_size;
201: {
202: int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
203: register int offset = bitnum / unit;
204: register int bitpos = bitnum % unit;
205: register rtx op0 = str_rtx;
206:
207: if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
208: abort ();
209:
210: /* Discount the part of the structure before the desired byte.
211: We need to know how many bytes are safe to reference after it. */
212: if (total_size >= 0)
213: total_size -= (bitpos / BIGGEST_ALIGNMENT
214: * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
215:
216: while (GET_CODE (op0) == SUBREG)
217: {
218: /* The following line once was done only if WORDS_BIG_ENDIAN,
219: but I think that is a mistake. WORDS_BIG_ENDIAN is
220: meaningful at a much higher level; when structures are copied
221: between memory and regs, the higher-numbered regs
222: always get higher addresses. */
223: offset += SUBREG_WORD (op0);
224: /* We used to adjust BITPOS here, but now we do the whole adjustment
225: right after the loop. */
226: op0 = SUBREG_REG (op0);
227: }
228:
229: #if BYTES_BIG_ENDIAN
230: /* If OP0 is a register, BITPOS must count within a word.
231: But as we have it, it counts within whatever size OP0 now has.
232: On a bigendian machine, these are not the same, so convert. */
233: if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
234: bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
235: #endif
236:
237: value = protect_from_queue (value, 0);
238:
239: if (flag_force_mem)
240: value = force_not_mem (value);
241:
242: /* Note that the adjustment of BITPOS above has no effect on whether
243: BITPOS is 0 in a REG bigger than a word. */
1.1.1.3 root 244: if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
245: && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM)
1.1 root 246: && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
247: {
248: /* Storing in a full-word or multi-word field in a register
249: can be done with just SUBREG. */
250: if (GET_MODE (op0) != fieldmode)
1.1.1.3 root 251: if (GET_CODE (op0) == REG)
252: op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
253: else
254: op0 = change_address (op0, fieldmode,
255: plus_constant (XEXP (op0, 0), offset));
1.1 root 256: emit_move_insn (op0, value);
257: return value;
258: }
259:
260: /* Storing an lsb-aligned field in a register
261: can be done with a movestrict instruction. */
262:
263: if (GET_CODE (op0) != MEM
264: #if BYTES_BIG_ENDIAN
265: && bitpos + bitsize == unit
266: #else
267: && bitpos == 0
268: #endif
269: && bitsize == GET_MODE_BITSIZE (fieldmode)
270: && (GET_MODE (op0) == fieldmode
271: || (movstrict_optab->handlers[(int) fieldmode].insn_code
272: != CODE_FOR_nothing)))
273: {
274: /* Get appropriate low part of the value being stored. */
275: if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
276: value = gen_lowpart (fieldmode, value);
277: else if (!(GET_CODE (value) == SYMBOL_REF
278: || GET_CODE (value) == LABEL_REF
279: || GET_CODE (value) == CONST))
280: value = convert_to_mode (fieldmode, value, 0);
281:
282: if (GET_MODE (op0) == fieldmode)
283: emit_move_insn (op0, value);
284: else
285: {
286: int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
287: if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
288: value = copy_to_mode_reg (fieldmode, value);
289: emit_insn (GEN_FCN (icode)
290: (gen_rtx (SUBREG, fieldmode, op0, offset), value));
291: }
292: return value;
293: }
294:
295: /* Handle fields bigger than a word. */
296:
297: if (bitsize > BITS_PER_WORD)
298: {
299: /* Here we transfer the words of the field
300: in the order least significant first.
301: This is because the most significant word is the one which may
302: be less than full. */
303:
304: int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
305: int i;
306:
307: /* This is the mode we must force value to, so that there will be enough
308: subwords to extract. Note that fieldmode will often (always?) be
309: VOIDmode, because that is what store_field uses to indicate that this
310: is a bit field, but passing VOIDmode to operand_subword_force will
311: result in an abort. */
312: fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
313:
314: for (i = 0; i < nwords; i++)
315: {
316: /* If I is 0, use the low-order word in both field and target;
317: if I is 1, use the next to lowest word; and so on. */
318: int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
319: int bit_offset = (WORDS_BIG_ENDIAN
320: ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
321: : i * BITS_PER_WORD);
322: store_bit_field (op0, MIN (BITS_PER_WORD,
323: bitsize - i * BITS_PER_WORD),
324: bitnum + bit_offset, word_mode,
325: operand_subword_force (value, wordnum, fieldmode),
326: align, total_size);
327: }
328: return value;
329: }
330:
331: /* From here on we can assume that the field to be stored in is
332: a full-word (whatever type that is), since it is shorter than a word. */
333:
334: /* OFFSET is the number of words or bytes (UNIT says which)
335: from STR_RTX to the first word or byte containing part of the field. */
336:
337: if (GET_CODE (op0) == REG)
338: {
339: if (offset != 0
340: || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
341: op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
342: op0, offset);
343: offset = 0;
344: }
345: else
346: {
347: op0 = protect_from_queue (op0, 1);
348: }
349:
350: /* Now OFFSET is nonzero only if OP0 is memory
351: and is therefore always measured in bytes. */
352:
353: #ifdef HAVE_insv
354: if (HAVE_insv
355: && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
356: /* Ensure insv's size is wide enough for this field. */
357: && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
358: >= bitsize))
359: {
360: int xbitpos = bitpos;
361: rtx value1;
362: rtx xop0 = op0;
363: rtx last = get_last_insn ();
364: rtx pat;
365: enum machine_mode maxmode
366: = insn_operand_mode[(int) CODE_FOR_insv][3];
367:
368: int save_volatile_ok = volatile_ok;
369: volatile_ok = 1;
370:
371: /* If this machine's insv can only insert into a register, or if we
372: are to force MEMs into a register, copy OP0 into a register and
373: save it back later. */
374: if (GET_CODE (op0) == MEM
375: && (flag_force_mem
376: || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
377: (op0, VOIDmode))))
378: {
379: rtx tempreg;
380: enum machine_mode bestmode;
381:
382: /* Get the mode to use for inserting into this field. If OP0 is
383: BLKmode, get the smallest mode consistent with the alignment. If
384: OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
385: mode. Otherwise, use the smallest mode containing the field. */
386:
387: if (GET_MODE (op0) == BLKmode
388: || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
389: bestmode
1.1.1.3 root 390: = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
391: MEM_VOLATILE_P (op0));
1.1 root 392: else
393: bestmode = GET_MODE (op0);
394:
395: if (bestmode == VOIDmode)
396: goto insv_loses;
397:
398: /* Adjust address to point to the containing unit of that mode. */
399: unit = GET_MODE_BITSIZE (bestmode);
400: /* Compute offset as multiple of this unit, counting in bytes. */
401: offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
402: bitpos = bitnum % unit;
403: op0 = change_address (op0, bestmode,
404: plus_constant (XEXP (op0, 0), offset));
405:
406: /* Fetch that unit, store the bitfield in it, then store the unit. */
407: tempreg = copy_to_reg (op0);
408: store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
409: align, total_size);
410: emit_move_insn (op0, tempreg);
411: return value;
412: }
413: volatile_ok = save_volatile_ok;
414:
415: /* Add OFFSET into OP0's address. */
416: if (GET_CODE (xop0) == MEM)
417: xop0 = change_address (xop0, byte_mode,
418: plus_constant (XEXP (xop0, 0), offset));
419:
420: /* If xop0 is a register, we need it in MAXMODE
421: to make it acceptable to the format of insv. */
422: if (GET_CODE (xop0) == SUBREG)
423: PUT_MODE (xop0, maxmode);
424: if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
425: xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
426:
427: /* On big-endian machines, we count bits from the most significant.
428: If the bit field insn does not, we must invert. */
429:
430: #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
431: xbitpos = unit - bitsize - xbitpos;
432: #endif
433: /* We have been counting XBITPOS within UNIT.
434: Count instead within the size of the register. */
435: #if BITS_BIG_ENDIAN
436: if (GET_CODE (xop0) != MEM)
437: xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
438: #endif
439: unit = GET_MODE_BITSIZE (maxmode);
440:
441: /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
442: value1 = value;
443: if (GET_MODE (value) != maxmode)
444: {
445: if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
446: {
447: /* Optimization: Don't bother really extending VALUE
1.1.1.4 root 448: if it has all the bits we will actually use. However,
449: if we must narrow it, be sure we do it correctly. */
1.1 root 450:
1.1.1.4 root 451: if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
452: {
453: /* Avoid making subreg of a subreg, or of a mem. */
454: if (GET_CODE (value1) != REG)
1.1 root 455: value1 = copy_to_reg (value1);
1.1.1.4 root 456: value1 = gen_rtx (SUBREG, maxmode, value1, 0);
457: }
458: else
459: value1 = gen_lowpart (maxmode, value1);
1.1 root 460: }
461: else if (!CONSTANT_P (value))
462: /* Parse phase is supposed to make VALUE's data type
463: match that of the component reference, which is a type
464: at least as wide as the field; so VALUE should have
465: a mode that corresponds to that type. */
466: abort ();
467: }
468:
469: /* If this machine's insv insists on a register,
470: get VALUE1 into a register. */
471: if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
472: (value1, maxmode)))
473: value1 = force_reg (maxmode, value1);
474:
1.1.1.4 root 475: pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
1.1 root 476: if (pat)
477: emit_insn (pat);
478: else
479: {
480: delete_insns_since (last);
481: store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
482: }
483: }
484: else
485: insv_loses:
486: #endif
487: /* Insv is not available; store using shifts and boolean ops. */
488: store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
489: return value;
490: }
491:
492: /* Use shifts and boolean operations to store VALUE
493: into a bit field of width BITSIZE
494: in a memory location specified by OP0 except offset by OFFSET bytes.
495: (OFFSET must be 0 if OP0 is a register.)
496: The field starts at position BITPOS within the byte.
497: (If OP0 is a register, it may be a full word or a narrower mode,
498: but BITPOS still counts within a full word,
499: which is significant on bigendian machines.)
500: STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
501:
502: Note that protect_from_queue has already been done on OP0 and VALUE. */
503:
504: static void
505: store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
506: register rtx op0;
507: register int offset, bitsize, bitpos;
508: register rtx value;
509: int struct_align;
510: {
511: register enum machine_mode mode;
512: int total_bits = BITS_PER_WORD;
513: rtx subtarget, temp;
514: int all_zero = 0;
515: int all_one = 0;
516:
517: /* Add OFFSET to OP0's address (if it is in memory)
518: and if a single byte contains the whole bit field
519: change OP0 to a byte. */
520:
521: /* There is a case not handled here:
522: a structure with a known alignment of just a halfword
523: and a field split across two aligned halfwords within the structure.
524: Or likewise a structure with a known alignment of just a byte
525: and a field split across two bytes.
526: Such cases are not supposed to be able to occur. */
527:
528: if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
529: {
530: if (offset != 0)
531: abort ();
532: /* Special treatment for a bit field split across two registers. */
533: if (bitsize + bitpos > BITS_PER_WORD)
534: {
535: store_split_bit_field (op0, bitsize, bitpos, value, BITS_PER_WORD);
536: return;
537: }
538: }
539: else
540: {
541: /* Get the proper mode to use for this field. We want a mode that
542: includes the entire field. If such a mode would be larger than
543: a word, we won't be doing the extraction the normal way. */
544:
545: mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
546: struct_align * BITS_PER_UNIT, word_mode,
547: GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
548:
549: if (mode == VOIDmode)
550: {
551: /* The only way this should occur is if the field spans word
552: boundaries. */
553: store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
554: value, struct_align);
555: return;
556: }
557:
558: total_bits = GET_MODE_BITSIZE (mode);
559:
560: /* Get ref to an aligned byte, halfword, or word containing the field.
561: Adjust BITPOS to be position within a word,
562: and OFFSET to be the offset of that word.
563: Then alter OP0 to refer to that word. */
564: bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
565: offset -= (offset % (total_bits / BITS_PER_UNIT));
566: op0 = change_address (op0, mode,
567: plus_constant (XEXP (op0, 0), offset));
568: }
569:
570: mode = GET_MODE (op0);
571:
572: /* Now MODE is either some integral mode for a MEM as OP0,
573: or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
574: The bit field is contained entirely within OP0.
575: BITPOS is the starting bit number within OP0.
576: (OP0's mode may actually be narrower than MODE.) */
577:
578: #if BYTES_BIG_ENDIAN
579: /* BITPOS is the distance between our msb
580: and that of the containing datum.
581: Convert it to the distance from the lsb. */
582:
583: bitpos = total_bits - bitsize - bitpos;
584: #endif
585: /* Now BITPOS is always the distance between our lsb
586: and that of OP0. */
587:
588: /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
589: we must first convert its mode to MODE. */
590:
591: if (GET_CODE (value) == CONST_INT)
592: {
1.1.1.4 root 593: register HOST_WIDE_INT v = INTVAL (value);
1.1 root 594:
1.1.1.4 root 595: if (bitsize < HOST_BITS_PER_WIDE_INT)
596: v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
1.1 root 597:
598: if (v == 0)
599: all_zero = 1;
1.1.1.4 root 600: else if ((bitsize < HOST_BITS_PER_WIDE_INT
601: && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
602: || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
1.1 root 603: all_one = 1;
604:
605: value = lshift_value (mode, value, bitpos, bitsize);
606: }
607: else
608: {
609: int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
610: && bitpos + bitsize != GET_MODE_BITSIZE (mode));
611:
612: if (GET_MODE (value) != mode)
613: {
614: /* If VALUE is a floating-point mode, access it as an integer
615: of the corresponding size, then convert it. This can occur on
616: a machine with 64 bit registers that uses SFmode for float. */
617: if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
618: {
619: if (GET_CODE (value) != REG)
620: value = copy_to_reg (value);
621: value
622: = gen_rtx (SUBREG, word_mode, value, 0);
623: }
624:
625: if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
626: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
627: value = gen_lowpart (mode, value);
628: else
629: value = convert_to_mode (mode, value, 1);
630: }
631:
632: if (must_and)
633: value = expand_binop (mode, and_optab, value,
634: mask_rtx (mode, 0, bitsize, 0),
1.1.1.4 root 635: NULL_RTX, 1, OPTAB_LIB_WIDEN);
1.1 root 636: if (bitpos > 0)
637: value = expand_shift (LSHIFT_EXPR, mode, value,
1.1.1.4 root 638: build_int_2 (bitpos, 0), NULL_RTX, 1);
1.1 root 639: }
640:
641: /* Now clear the chosen bits in OP0,
642: except that if VALUE is -1 we need not bother. */
643:
644: subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
645:
646: if (! all_one)
647: {
648: temp = expand_binop (mode, and_optab, op0,
649: mask_rtx (mode, bitpos, bitsize, 1),
650: subtarget, 1, OPTAB_LIB_WIDEN);
651: subtarget = temp;
652: }
653: else
654: temp = op0;
655:
656: /* Now logical-or VALUE into OP0, unless it is zero. */
657:
658: if (! all_zero)
659: temp = expand_binop (mode, ior_optab, temp, value,
660: subtarget, 1, OPTAB_LIB_WIDEN);
661: if (op0 != temp)
662: emit_move_insn (op0, temp);
663: }
664:
665: /* Store a bit field that is split across two words.
666:
667: OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
668: BITSIZE is the field width; BITPOS the position of its first bit
669: (within the word).
670: VALUE is the value to store. */
671:
672: static void
673: store_split_bit_field (op0, bitsize, bitpos, value, align)
674: rtx op0;
675: int bitsize, bitpos;
676: rtx value;
677: int align;
678: {
679: /* BITSIZE_1 is size of the part in the first word. */
680: int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
681: /* BITSIZE_2 is size of the rest (in the following word). */
682: int bitsize_2 = bitsize - bitsize_1;
683: rtx part1, part2;
684: int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
685: int offset = bitpos / unit;
686: rtx word;
687:
688: /* The field must span exactly one word boundary. */
689: if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
690: abort ();
691:
692: if (GET_MODE (value) != VOIDmode)
693: value = convert_to_mode (word_mode, value, 1);
1.1.1.5 ! root 694:
! 695: if (GET_CODE (value) == CONST_DOUBLE
! 696: && (part1 = gen_lowpart_common (word_mode, value)) != 0)
! 697: value = part1;
! 698:
1.1 root 699: if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
1.1.1.5 ! root 700: value = copy_to_mode_reg (word_mode, value);
1.1 root 701:
702: /* Split the value into two parts:
703: PART1 gets that which goes in the first word; PART2 the other. */
704: #if BYTES_BIG_ENDIAN
705: /* PART1 gets the more significant part. */
706: if (GET_CODE (value) == CONST_INT)
707: {
1.1.1.4 root 708: part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_2);
709: part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value))
710: & (((HOST_WIDE_INT) 1 << bitsize_2) - 1));
1.1 root 711: }
712: else
713: {
714: part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1,
1.1.1.4 root 715: BITS_PER_WORD - bitsize, NULL_RTX, 1,
1.1 root 716: BITS_PER_WORD);
717: part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
1.1.1.4 root 718: BITS_PER_WORD - bitsize_2, NULL_RTX, 1,
1.1 root 719: BITS_PER_WORD);
720: }
721: #else
722: /* PART1 gets the less significant part. */
723: if (GET_CODE (value) == CONST_INT)
724: {
1.1.1.4 root 725: part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value))
726: & (((HOST_WIDE_INT) 1 << bitsize_1) - 1));
727: part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_1);
1.1 root 728: }
729: else
730: {
731: part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1, 0,
1.1.1.4 root 732: NULL_RTX, 1, BITS_PER_WORD);
1.1 root 733: part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
1.1.1.4 root 734: bitsize_1, NULL_RTX, 1, BITS_PER_WORD);
1.1 root 735: }
736: #endif
737:
738: /* Store PART1 into the first word. If OP0 is a MEM, pass OP0 and the
739: offset computed above. Otherwise, get the proper word and pass an
740: offset of zero. */
741: word = (GET_CODE (op0) == MEM ? op0
742: : operand_subword (op0, offset, 1, GET_MODE (op0)));
743: if (word == 0)
744: abort ();
745:
746: store_fixed_bit_field (word, GET_CODE (op0) == MEM ? offset : 0,
747: bitsize_1, bitpos % unit, part1, align);
748:
749: /* Offset op0 by 1 word to get to the following one. */
750: if (GET_CODE (op0) == SUBREG)
751: word = operand_subword (SUBREG_REG (op0), SUBREG_WORD (op0) + offset + 1,
752: 1, VOIDmode);
753: else if (GET_CODE (op0) == MEM)
754: word = op0;
755: else
756: word = operand_subword (op0, offset + 1, 1, GET_MODE (op0));
757:
758: if (word == 0)
759: abort ();
760:
761: /* Store PART2 into the second word. */
762: store_fixed_bit_field (word,
763: (GET_CODE (op0) == MEM
764: ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
765: : 0),
766: bitsize_2, 0, part2, align);
767: }
768:
769: /* Generate code to extract a byte-field from STR_RTX
770: containing BITSIZE bits, starting at BITNUM,
771: and put it in TARGET if possible (if TARGET is nonzero).
772: Regardless of TARGET, we return the rtx for where the value is placed.
773: It may be a QUEUED.
774:
775: STR_RTX is the structure containing the byte (a REG or MEM).
776: UNSIGNEDP is nonzero if this is an unsigned bit field.
777: MODE is the natural mode of the field value once extracted.
778: TMODE is the mode the caller would like the value to have;
779: but the value may be returned with type MODE instead.
780:
781: ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
782: TOTAL_SIZE is the size in bytes of the containing structure,
783: or -1 if varying.
784:
785: If a TARGET is specified and we can store in it at no extra cost,
786: we do so, and return TARGET.
787: Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
788: if they are equally easy. */
789:
790: rtx
791: extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
792: target, mode, tmode, align, total_size)
793: rtx str_rtx;
794: register int bitsize;
795: int bitnum;
796: int unsignedp;
797: rtx target;
798: enum machine_mode mode, tmode;
799: int align;
800: int total_size;
801: {
802: int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
803: register int offset = bitnum / unit;
804: register int bitpos = bitnum % unit;
805: register rtx op0 = str_rtx;
806: rtx spec_target = target;
807: rtx spec_target_subreg = 0;
808:
809: if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
810: abort ();
811:
812: /* Discount the part of the structure before the desired byte.
813: We need to know how many bytes are safe to reference after it. */
814: if (total_size >= 0)
815: total_size -= (bitpos / BIGGEST_ALIGNMENT
816: * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
817:
818: if (tmode == VOIDmode)
819: tmode = mode;
820: while (GET_CODE (op0) == SUBREG)
821: {
822: offset += SUBREG_WORD (op0);
823: op0 = SUBREG_REG (op0);
824: }
825:
826: #if BYTES_BIG_ENDIAN
827: /* If OP0 is a register, BITPOS must count within a word.
828: But as we have it, it counts within whatever size OP0 now has.
829: On a bigendian machine, these are not the same, so convert. */
830: if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
831: bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
832: #endif
833:
834: /* Extracting a full-word or multi-word value
835: from a structure in a register.
836: This can be done with just SUBREG.
837: So too extracting a subword value in
838: the least significant part of the register. */
839:
840: if (GET_CODE (op0) == REG
841: && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
842: && bitpos % BITS_PER_WORD == 0)
843: || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
844: #if BYTES_BIG_ENDIAN
845: && bitpos + bitsize == BITS_PER_WORD
846: #else
847: && bitpos == 0
848: #endif
849: )))
850: {
851: enum machine_mode mode1
852: = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
853:
854: if (mode1 != GET_MODE (op0))
855: op0 = gen_rtx (SUBREG, mode1, op0, offset);
856:
857: if (mode1 != mode)
858: return convert_to_mode (tmode, op0, unsignedp);
859: return op0;
860: }
861:
862: /* Handle fields bigger than a word. */
863:
864: if (bitsize > BITS_PER_WORD)
865: {
866: /* Here we transfer the words of the field
867: in the order least significant first.
868: This is because the most significant word is the one which may
869: be less than full. */
870:
871: int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
872: int i;
873:
874: if (target == 0 || GET_CODE (target) != REG)
875: target = gen_reg_rtx (mode);
876:
877: for (i = 0; i < nwords; i++)
878: {
879: /* If I is 0, use the low-order word in both field and target;
880: if I is 1, use the next to lowest word; and so on. */
881: int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
882: int bit_offset = (WORDS_BIG_ENDIAN
883: ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
884: : i * BITS_PER_WORD);
885: rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
886: rtx result_part
887: = extract_bit_field (op0, MIN (BITS_PER_WORD,
888: bitsize - i * BITS_PER_WORD),
889: bitnum + bit_offset,
890: 1, target_part, mode, word_mode,
891: align, total_size);
892:
893: if (target_part == 0)
894: abort ();
895:
896: if (result_part != target_part)
897: emit_move_insn (target_part, result_part);
898: }
899:
900: return target;
901: }
902:
903: /* From here on we know the desired field is smaller than a word
904: so we can assume it is an integer. So we can safely extract it as one
905: size of integer, if necessary, and then truncate or extend
906: to the size that is wanted. */
907:
908: /* OFFSET is the number of words or bytes (UNIT says which)
909: from STR_RTX to the first word or byte containing part of the field. */
910:
911: if (GET_CODE (op0) == REG)
912: {
913: if (offset != 0
914: || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
915: op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
916: op0, offset);
917: offset = 0;
918: }
919: else
920: {
921: op0 = protect_from_queue (str_rtx, 1);
922: }
923:
924: /* Now OFFSET is nonzero only for memory operands. */
925:
926: if (unsignedp)
927: {
928: #ifdef HAVE_extzv
929: if (HAVE_extzv
930: && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
931: >= bitsize))
932: {
933: int xbitpos = bitpos, xoffset = offset;
934: rtx bitsize_rtx, bitpos_rtx;
935: rtx last = get_last_insn();
936: rtx xop0 = op0;
937: rtx xtarget = target;
938: rtx xspec_target = spec_target;
939: rtx xspec_target_subreg = spec_target_subreg;
940: rtx pat;
941: enum machine_mode maxmode
942: = insn_operand_mode[(int) CODE_FOR_extzv][0];
943:
944: if (GET_CODE (xop0) == MEM)
945: {
946: int save_volatile_ok = volatile_ok;
947: volatile_ok = 1;
948:
949: /* Is the memory operand acceptable? */
950: if (flag_force_mem
951: || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
952: (xop0, GET_MODE (xop0))))
953: {
954: /* No, load into a reg and extract from there. */
955: enum machine_mode bestmode;
956:
957: /* Get the mode to use for inserting into this field. If
958: OP0 is BLKmode, get the smallest mode consistent with the
959: alignment. If OP0 is a non-BLKmode object that is no
960: wider than MAXMODE, use its mode. Otherwise, use the
961: smallest mode containing the field. */
962:
963: if (GET_MODE (xop0) == BLKmode
964: || (GET_MODE_SIZE (GET_MODE (op0))
965: > GET_MODE_SIZE (maxmode)))
966: bestmode = get_best_mode (bitsize, bitnum,
967: align * BITS_PER_UNIT, maxmode,
1.1.1.3 root 968: MEM_VOLATILE_P (xop0));
1.1 root 969: else
970: bestmode = GET_MODE (xop0);
971:
972: if (bestmode == VOIDmode)
973: goto extzv_loses;
974:
975: /* Compute offset as multiple of this unit,
976: counting in bytes. */
977: unit = GET_MODE_BITSIZE (bestmode);
978: xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
979: xbitpos = bitnum % unit;
980: xop0 = change_address (xop0, bestmode,
981: plus_constant (XEXP (xop0, 0),
982: xoffset));
983: /* Fetch it to a register in that size. */
984: xop0 = force_reg (bestmode, xop0);
985:
986: /* XBITPOS counts within UNIT, which is what is expected. */
987: }
988: else
989: /* Get ref to first byte containing part of the field. */
990: xop0 = change_address (xop0, byte_mode,
991: plus_constant (XEXP (xop0, 0), xoffset));
992:
993: volatile_ok = save_volatile_ok;
994: }
995:
996: /* If op0 is a register, we need it in MAXMODE (which is usually
997: SImode). to make it acceptable to the format of extzv. */
998: if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
999: abort ();
1000: if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1001: xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1002:
1003: /* On big-endian machines, we count bits from the most significant.
1004: If the bit field insn does not, we must invert. */
1005: #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1006: xbitpos = unit - bitsize - xbitpos;
1007: #endif
1008: /* Now convert from counting within UNIT to counting in MAXMODE. */
1009: #if BITS_BIG_ENDIAN
1010: if (GET_CODE (xop0) != MEM)
1011: xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1012: #endif
1013: unit = GET_MODE_BITSIZE (maxmode);
1014:
1015: if (xtarget == 0
1016: || (flag_force_mem && GET_CODE (xtarget) == MEM))
1017: xtarget = xspec_target = gen_reg_rtx (tmode);
1018:
1019: if (GET_MODE (xtarget) != maxmode)
1020: {
1021: if (GET_CODE (xtarget) == REG)
1.1.1.3 root 1022: {
1023: int wider = (GET_MODE_SIZE (maxmode)
1024: > GET_MODE_SIZE (GET_MODE (xtarget)));
1025: xtarget = gen_lowpart (maxmode, xtarget);
1026: if (wider)
1027: xspec_target_subreg = xtarget;
1028: }
1.1 root 1029: else
1030: xtarget = gen_reg_rtx (maxmode);
1031: }
1032:
1033: /* If this machine's extzv insists on a register target,
1034: make sure we have one. */
1035: if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1036: (xtarget, maxmode)))
1037: xtarget = gen_reg_rtx (maxmode);
1038:
1.1.1.4 root 1039: bitsize_rtx = GEN_INT (bitsize);
1040: bitpos_rtx = GEN_INT (xbitpos);
1.1 root 1041:
1042: pat = gen_extzv (protect_from_queue (xtarget, 1),
1043: xop0, bitsize_rtx, bitpos_rtx);
1044: if (pat)
1045: {
1046: emit_insn (pat);
1047: target = xtarget;
1048: spec_target = xspec_target;
1049: spec_target_subreg = xspec_target_subreg;
1050: }
1051: else
1052: {
1053: delete_insns_since (last);
1054: target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1055: bitpos, target, 1, align);
1056: }
1057: }
1058: else
1059: extzv_loses:
1060: #endif
1061: target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1062: target, 1, align);
1063: }
1064: else
1065: {
1066: #ifdef HAVE_extv
1067: if (HAVE_extv
1068: && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1069: >= bitsize))
1070: {
1071: int xbitpos = bitpos, xoffset = offset;
1072: rtx bitsize_rtx, bitpos_rtx;
1073: rtx last = get_last_insn();
1074: rtx xop0 = op0, xtarget = target;
1075: rtx xspec_target = spec_target;
1076: rtx xspec_target_subreg = spec_target_subreg;
1077: rtx pat;
1078: enum machine_mode maxmode
1079: = insn_operand_mode[(int) CODE_FOR_extv][0];
1080:
1081: if (GET_CODE (xop0) == MEM)
1082: {
1083: /* Is the memory operand acceptable? */
1084: if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1085: (xop0, GET_MODE (xop0))))
1086: {
1087: /* No, load into a reg and extract from there. */
1088: enum machine_mode bestmode;
1089:
1090: /* Get the mode to use for inserting into this field. If
1091: OP0 is BLKmode, get the smallest mode consistent with the
1092: alignment. If OP0 is a non-BLKmode object that is no
1093: wider than MAXMODE, use its mode. Otherwise, use the
1094: smallest mode containing the field. */
1095:
1096: if (GET_MODE (xop0) == BLKmode
1097: || (GET_MODE_SIZE (GET_MODE (op0))
1098: > GET_MODE_SIZE (maxmode)))
1099: bestmode = get_best_mode (bitsize, bitnum,
1100: align * BITS_PER_UNIT, maxmode,
1.1.1.3 root 1101: MEM_VOLATILE_P (xop0));
1.1 root 1102: else
1103: bestmode = GET_MODE (xop0);
1104:
1105: if (bestmode == VOIDmode)
1106: goto extv_loses;
1107:
1108: /* Compute offset as multiple of this unit,
1109: counting in bytes. */
1110: unit = GET_MODE_BITSIZE (bestmode);
1111: xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1112: xbitpos = bitnum % unit;
1113: xop0 = change_address (xop0, bestmode,
1114: plus_constant (XEXP (xop0, 0),
1115: xoffset));
1116: /* Fetch it to a register in that size. */
1117: xop0 = force_reg (bestmode, xop0);
1118:
1119: /* XBITPOS counts within UNIT, which is what is expected. */
1120: }
1121: else
1122: /* Get ref to first byte containing part of the field. */
1123: xop0 = change_address (xop0, byte_mode,
1124: plus_constant (XEXP (xop0, 0), xoffset));
1125: }
1126:
1127: /* If op0 is a register, we need it in MAXMODE (which is usually
1128: SImode) to make it acceptable to the format of extv. */
1129: if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1130: abort ();
1131: if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1132: xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1133:
1134: /* On big-endian machines, we count bits from the most significant.
1135: If the bit field insn does not, we must invert. */
1136: #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1137: xbitpos = unit - bitsize - xbitpos;
1138: #endif
1139: /* XBITPOS counts within a size of UNIT.
1140: Adjust to count within a size of MAXMODE. */
1141: #if BITS_BIG_ENDIAN
1142: if (GET_CODE (xop0) != MEM)
1143: xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1144: #endif
1145: unit = GET_MODE_BITSIZE (maxmode);
1146:
1147: if (xtarget == 0
1148: || (flag_force_mem && GET_CODE (xtarget) == MEM))
1149: xtarget = xspec_target = gen_reg_rtx (tmode);
1150:
1151: if (GET_MODE (xtarget) != maxmode)
1152: {
1153: if (GET_CODE (xtarget) == REG)
1.1.1.3 root 1154: {
1155: int wider = (GET_MODE_SIZE (maxmode)
1156: > GET_MODE_SIZE (GET_MODE (xtarget)));
1157: xtarget = gen_lowpart (maxmode, xtarget);
1158: if (wider)
1159: xspec_target_subreg = xtarget;
1160: }
1.1 root 1161: else
1162: xtarget = gen_reg_rtx (maxmode);
1163: }
1164:
1165: /* If this machine's extv insists on a register target,
1166: make sure we have one. */
1167: if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1168: (xtarget, maxmode)))
1169: xtarget = gen_reg_rtx (maxmode);
1170:
1.1.1.4 root 1171: bitsize_rtx = GEN_INT (bitsize);
1172: bitpos_rtx = GEN_INT (xbitpos);
1.1 root 1173:
1174: pat = gen_extv (protect_from_queue (xtarget, 1),
1175: xop0, bitsize_rtx, bitpos_rtx);
1176: if (pat)
1177: {
1178: emit_insn (pat);
1179: target = xtarget;
1180: spec_target = xspec_target;
1181: spec_target_subreg = xspec_target_subreg;
1182: }
1183: else
1184: {
1185: delete_insns_since (last);
1186: target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1187: bitpos, target, 0, align);
1188: }
1189: }
1190: else
1191: extv_loses:
1192: #endif
1193: target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1194: target, 0, align);
1195: }
1196: if (target == spec_target)
1197: return target;
1198: if (target == spec_target_subreg)
1199: return spec_target;
1200: if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1201: {
1202: /* If the target mode is floating-point, first convert to the
1203: integer mode of that size and then access it as a floating-point
1204: value via a SUBREG. */
1205: if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1206: {
1207: target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1208: MODE_INT, 0),
1209: target, unsignedp);
1210: if (GET_CODE (target) != REG)
1211: target = copy_to_reg (target);
1212: return gen_rtx (SUBREG, tmode, target, 0);
1213: }
1214: else
1215: return convert_to_mode (tmode, target, unsignedp);
1216: }
1217: return target;
1218: }
1219:
1220: /* Extract a bit field using shifts and boolean operations
1221: Returns an rtx to represent the value.
1222: OP0 addresses a register (word) or memory (byte).
1223: BITPOS says which bit within the word or byte the bit field starts in.
1224: OFFSET says how many bytes farther the bit field starts;
1225: it is 0 if OP0 is a register.
1226: BITSIZE says how many bits long the bit field is.
1227: (If OP0 is a register, it may be narrower than a full word,
1228: but BITPOS still counts within a full word,
1229: which is significant on bigendian machines.)
1230:
1231: UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1232: If TARGET is nonzero, attempts to store the value there
1233: and return TARGET, but this is not guaranteed.
1234: If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1235:
1236: ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1237:
1238: static rtx
1239: extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1240: target, unsignedp, align)
1241: enum machine_mode tmode;
1242: register rtx op0, target;
1243: register int offset, bitsize, bitpos;
1244: int unsignedp;
1245: int align;
1246: {
1247: int total_bits = BITS_PER_WORD;
1248: enum machine_mode mode;
1249:
1250: if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1251: {
1252: /* Special treatment for a bit field split across two registers. */
1253: if (bitsize + bitpos > BITS_PER_WORD)
1254: return extract_split_bit_field (op0, bitsize, bitpos,
1255: unsignedp, align);
1256: }
1257: else
1258: {
1259: /* Get the proper mode to use for this field. We want a mode that
1260: includes the entire field. If such a mode would be larger than
1261: a word, we won't be doing the extraction the normal way. */
1262:
1263: mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1264: align * BITS_PER_UNIT, word_mode,
1265: GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1266:
1267: if (mode == VOIDmode)
1268: /* The only way this should occur is if the field spans word
1269: boundaries. */
1270: return extract_split_bit_field (op0, bitsize,
1271: bitpos + offset * BITS_PER_UNIT,
1272: unsignedp, align);
1273:
1274: total_bits = GET_MODE_BITSIZE (mode);
1275:
1.1.1.5 ! root 1276: /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
! 1277: be be in the range 0 to total_bits-1, and put any excess bytes in
! 1278: OFFSET. */
! 1279: if (bitpos >= total_bits)
! 1280: {
! 1281: offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
! 1282: bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
! 1283: * BITS_PER_UNIT);
! 1284: }
! 1285:
1.1 root 1286: /* Get ref to an aligned byte, halfword, or word containing the field.
1287: Adjust BITPOS to be position within a word,
1288: and OFFSET to be the offset of that word.
1289: Then alter OP0 to refer to that word. */
1290: bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1291: offset -= (offset % (total_bits / BITS_PER_UNIT));
1292: op0 = change_address (op0, mode,
1293: plus_constant (XEXP (op0, 0), offset));
1294: }
1295:
1296: mode = GET_MODE (op0);
1297:
1298: #if BYTES_BIG_ENDIAN
1299: /* BITPOS is the distance between our msb and that of OP0.
1300: Convert it to the distance from the lsb. */
1301:
1302: bitpos = total_bits - bitsize - bitpos;
1303: #endif
1304: /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1305: We have reduced the big-endian case to the little-endian case. */
1306:
1307: if (unsignedp)
1308: {
1309: if (bitpos)
1310: {
1311: /* If the field does not already start at the lsb,
1312: shift it so it does. */
1313: tree amount = build_int_2 (bitpos, 0);
1314: /* Maybe propagate the target for the shift. */
1315: /* But not if we will return it--could confuse integrate.c. */
1316: rtx subtarget = (target != 0 && GET_CODE (target) == REG
1317: && !REG_FUNCTION_VALUE_P (target)
1318: ? target : 0);
1319: if (tmode != mode) subtarget = 0;
1320: op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1321: }
1322: /* Convert the value to the desired mode. */
1323: if (mode != tmode)
1324: op0 = convert_to_mode (tmode, op0, 1);
1325:
1326: /* Unless the msb of the field used to be the msb when we shifted,
1327: mask out the upper bits. */
1328:
1329: if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1330: #if 0
1331: #ifdef SLOW_ZERO_EXTEND
1332: /* Always generate an `and' if
1333: we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1334: will combine fruitfully with the zero-extend. */
1335: || tmode != mode
1336: #endif
1337: #endif
1338: )
1339: return expand_binop (GET_MODE (op0), and_optab, op0,
1340: mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1341: target, 1, OPTAB_LIB_WIDEN);
1342: return op0;
1343: }
1344:
1345: /* To extract a signed bit-field, first shift its msb to the msb of the word,
1346: then arithmetic-shift its lsb to the lsb of the word. */
1347: op0 = force_reg (mode, op0);
1348: if (mode != tmode)
1349: target = 0;
1350:
1351: /* Find the narrowest integer mode that contains the field. */
1352:
1353: for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1354: mode = GET_MODE_WIDER_MODE (mode))
1355: if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1356: {
1357: op0 = convert_to_mode (mode, op0, 0);
1358: break;
1359: }
1360:
1361: if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1362: {
1363: tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1364: /* Maybe propagate the target for the shift. */
1365: /* But not if we will return the result--could confuse integrate.c. */
1366: rtx subtarget = (target != 0 && GET_CODE (target) == REG
1367: && ! REG_FUNCTION_VALUE_P (target)
1368: ? target : 0);
1369: op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1370: }
1371:
1372: return expand_shift (RSHIFT_EXPR, mode, op0,
1373: build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1374: target, 0);
1375: }
1376:
1377: /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1378: of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1379: complement of that if COMPLEMENT. The mask is truncated if
1380: necessary to the width of mode MODE. */
1381:
1382: static rtx
1383: mask_rtx (mode, bitpos, bitsize, complement)
1384: enum machine_mode mode;
1385: int bitpos, bitsize, complement;
1386: {
1.1.1.4 root 1387: HOST_WIDE_INT masklow, maskhigh;
1.1 root 1388:
1.1.1.4 root 1389: if (bitpos < HOST_BITS_PER_WIDE_INT)
1390: masklow = (HOST_WIDE_INT) -1 << bitpos;
1.1 root 1391: else
1392: masklow = 0;
1393:
1.1.1.4 root 1394: if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1395: masklow &= ((unsigned HOST_WIDE_INT) -1
1396: >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1.1 root 1397:
1.1.1.4 root 1398: if (bitpos <= HOST_BITS_PER_WIDE_INT)
1.1 root 1399: maskhigh = -1;
1400: else
1.1.1.4 root 1401: maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1.1 root 1402:
1.1.1.4 root 1403: if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1404: maskhigh &= ((unsigned HOST_WIDE_INT) -1
1405: >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1.1 root 1406: else
1407: maskhigh = 0;
1408:
1409: if (complement)
1410: {
1411: maskhigh = ~maskhigh;
1412: masklow = ~masklow;
1413: }
1414:
1415: return immed_double_const (masklow, maskhigh, mode);
1416: }
1417:
1418: /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1419: VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1420:
1421: static rtx
1422: lshift_value (mode, value, bitpos, bitsize)
1423: enum machine_mode mode;
1424: rtx value;
1425: int bitpos, bitsize;
1426: {
1.1.1.4 root 1427: unsigned HOST_WIDE_INT v = INTVAL (value);
1428: HOST_WIDE_INT low, high;
1.1 root 1429:
1.1.1.4 root 1430: if (bitsize < HOST_BITS_PER_WIDE_INT)
1431: v &= ~((HOST_WIDE_INT) -1 << bitsize);
1.1 root 1432:
1.1.1.4 root 1433: if (bitpos < HOST_BITS_PER_WIDE_INT)
1.1 root 1434: {
1435: low = v << bitpos;
1.1.1.4 root 1436: high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1.1 root 1437: }
1438: else
1439: {
1440: low = 0;
1.1.1.4 root 1441: high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1.1 root 1442: }
1443:
1444: return immed_double_const (low, high, mode);
1445: }
1446:
1447: /* Extract a bit field that is split across two words
1448: and return an RTX for the result.
1449:
1450: OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1451: BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1452: UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1453:
1454: static rtx
1455: extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1456: rtx op0;
1457: int bitsize, bitpos, unsignedp, align;
1458: {
1459: /* BITSIZE_1 is size of the part in the first word. */
1460: int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
1461: /* BITSIZE_2 is size of the rest (in the following word). */
1462: int bitsize_2 = bitsize - bitsize_1;
1463: rtx part1, part2, result;
1464: int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
1465: int offset = bitpos / unit;
1466: rtx word;
1467:
1468: /* The field must span exactly one word boundary. */
1469: if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
1470: abort ();
1471:
1472: /* Get the part of the bit field from the first word. If OP0 is a MEM,
1473: pass OP0 and the offset computed above. Otherwise, get the proper
1474: word and pass an offset of zero. */
1475: word = (GET_CODE (op0) == MEM ? op0
1476: : operand_subword_force (op0, offset, GET_MODE (op0)));
1477: part1 = extract_fixed_bit_field (word_mode, word,
1478: GET_CODE (op0) == MEM ? offset : 0,
1.1.1.4 root 1479: bitsize_1, bitpos % unit, NULL_RTX,
1480: 1, align);
1.1 root 1481:
1482: /* Offset op0 by 1 word to get to the following one. */
1483: if (GET_CODE (op0) == SUBREG)
1484: word = operand_subword_force (SUBREG_REG (op0),
1485: SUBREG_WORD (op0) + offset + 1, VOIDmode);
1486: else if (GET_CODE (op0) == MEM)
1487: word = op0;
1488: else
1489: word = operand_subword_force (op0, offset + 1, GET_MODE (op0));
1490:
1491: /* Get the part of the bit field from the second word. */
1492: part2 = extract_fixed_bit_field (word_mode, word,
1493: (GET_CODE (op0) == MEM
1494: ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
1495: : 0),
1.1.1.4 root 1496: bitsize_2, 0, NULL_RTX, 1, align);
1.1 root 1497:
1498: /* Shift the more significant part up to fit above the other part. */
1499: #if BYTES_BIG_ENDIAN
1500: part1 = expand_shift (LSHIFT_EXPR, word_mode, part1,
1501: build_int_2 (bitsize_2, 0), 0, 1);
1502: #else
1503: part2 = expand_shift (LSHIFT_EXPR, word_mode, part2,
1504: build_int_2 (bitsize_1, 0), 0, 1);
1505: #endif
1506:
1507: /* Combine the two parts with bitwise or. This works
1508: because we extracted both parts as unsigned bit fields. */
1.1.1.4 root 1509: result = expand_binop (word_mode, ior_optab, part1, part2, NULL_RTX, 1,
1.1 root 1510: OPTAB_LIB_WIDEN);
1511:
1512: /* Unsigned bit field: we are done. */
1513: if (unsignedp)
1514: return result;
1515: /* Signed bit field: sign-extend with two arithmetic shifts. */
1516: result = expand_shift (LSHIFT_EXPR, word_mode, result,
1.1.1.4 root 1517: build_int_2 (BITS_PER_WORD - bitsize, 0),
1518: NULL_RTX, 0);
1.1 root 1519: return expand_shift (RSHIFT_EXPR, word_mode, result,
1.1.1.4 root 1520: build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1.1 root 1521: }
1522:
1523: /* Add INC into TARGET. */
1524:
1525: void
1526: expand_inc (target, inc)
1527: rtx target, inc;
1528: {
1529: rtx value = expand_binop (GET_MODE (target), add_optab,
1530: target, inc,
1531: target, 0, OPTAB_LIB_WIDEN);
1532: if (value != target)
1533: emit_move_insn (target, value);
1534: }
1535:
1.1.1.2 root 1536: /* Subtract DEC from TARGET. */
1.1 root 1537:
1538: void
1539: expand_dec (target, dec)
1540: rtx target, dec;
1541: {
1542: rtx value = expand_binop (GET_MODE (target), sub_optab,
1543: target, dec,
1544: target, 0, OPTAB_LIB_WIDEN);
1545: if (value != target)
1546: emit_move_insn (target, value);
1547: }
1548:
1549: /* Output a shift instruction for expression code CODE,
1550: with SHIFTED being the rtx for the value to shift,
1551: and AMOUNT the tree for the amount to shift by.
1552: Store the result in the rtx TARGET, if that is convenient.
1553: If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1554: Return the rtx for where the value is. */
1555:
1556: rtx
1557: expand_shift (code, mode, shifted, amount, target, unsignedp)
1558: enum tree_code code;
1559: register enum machine_mode mode;
1560: rtx shifted;
1561: tree amount;
1562: register rtx target;
1563: int unsignedp;
1564: {
1565: register rtx op1, temp = 0;
1566: register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1567: register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1568: int try;
1569:
1570: /* Previously detected shift-counts computed by NEGATE_EXPR
1571: and shifted in the other direction; but that does not work
1572: on all machines. */
1573:
1.1.1.4 root 1574: op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1.1 root 1575:
1576: if (op1 == const0_rtx)
1577: return shifted;
1578:
1579: for (try = 0; temp == 0 && try < 3; try++)
1580: {
1581: enum optab_methods methods;
1582:
1583: if (try == 0)
1584: methods = OPTAB_DIRECT;
1585: else if (try == 1)
1586: methods = OPTAB_WIDEN;
1587: else
1588: methods = OPTAB_LIB_WIDEN;
1589:
1590: if (rotate)
1591: {
1592: /* Widening does not work for rotation. */
1593: if (methods == OPTAB_WIDEN)
1594: continue;
1595: else if (methods == OPTAB_LIB_WIDEN)
1.1.1.5 ! root 1596: {
! 1597: /* If we are rotating by a constant that is valid and
! 1598: we have been unable to open-code this by a rotation,
! 1599: do it as the IOR of two shifts. I.e., to rotate A
! 1600: by N bits, compute (A << N) | ((unsigned) A >> (C - N))
! 1601: where C is the bitsize of A.
! 1602:
! 1603: It is theoretically possible that the target machine might
! 1604: not be able to perform either shift and hence we would
! 1605: be making two libcalls rather than just the one for the
! 1606: shift (similarly if IOR could not be done). We will allow
! 1607: this extremely unlikely lossage to avoid complicating the
! 1608: code below. */
! 1609:
! 1610: if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0
! 1611: && INTVAL (op1) < GET_MODE_BITSIZE (mode))
! 1612: {
! 1613: rtx subtarget = target == shifted ? 0 : target;
! 1614: rtx temp1;
! 1615: tree other_amount
! 1616: = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0);
! 1617:
! 1618: shifted = force_reg (mode, shifted);
! 1619:
! 1620: temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
! 1621: mode, shifted, amount, subtarget, 1);
! 1622: temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
! 1623: mode, shifted, other_amount, 0, 1);
! 1624: return expand_binop (mode, ior_optab, temp, temp1, target,
! 1625: unsignedp, methods);
! 1626: }
! 1627: else
! 1628: methods = OPTAB_LIB;
! 1629: }
1.1 root 1630:
1631: temp = expand_binop (mode,
1632: left ? rotl_optab : rotr_optab,
1633: shifted, op1, target, unsignedp, methods);
1.1.1.5 ! root 1634:
! 1635: /* If we don't have the rotate, but we are rotating by a constant
! 1636: that is in range, try a rotate in the opposite direction. */
! 1637:
! 1638: if (temp == 0 && GET_CODE (op1) == CONST_INT
! 1639: && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
! 1640: temp = expand_binop (mode,
! 1641: left ? rotr_optab : rotl_optab,
! 1642: shifted,
! 1643: GEN_INT (GET_MODE_BITSIZE (mode)
! 1644: - INTVAL (op1)),
! 1645: target, unsignedp, methods);
1.1 root 1646: }
1647: else if (unsignedp)
1648: {
1649: temp = expand_binop (mode,
1650: left ? lshl_optab : lshr_optab,
1651: shifted, op1, target, unsignedp, methods);
1652: if (temp == 0 && left)
1653: temp = expand_binop (mode, ashl_optab,
1654: shifted, op1, target, unsignedp, methods);
1655: }
1656:
1657: /* Do arithmetic shifts.
1658: Also, if we are going to widen the operand, we can just as well
1659: use an arithmetic right-shift instead of a logical one. */
1660: if (temp == 0 && ! rotate
1661: && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1662: {
1663: enum optab_methods methods1 = methods;
1664:
1665: /* If trying to widen a log shift to an arithmetic shift,
1666: don't accept an arithmetic shift of the same size. */
1667: if (unsignedp)
1668: methods1 = OPTAB_MUST_WIDEN;
1669:
1670: /* Arithmetic shift */
1671:
1672: temp = expand_binop (mode,
1673: left ? ashl_optab : ashr_optab,
1674: shifted, op1, target, unsignedp, methods1);
1675: }
1676:
1677: #ifdef HAVE_extzv
1678: /* We can do a logical (unsigned) right shift with a bit-field
1679: extract insn. But first check if one of the above methods worked. */
1680: if (temp != 0)
1681: return temp;
1682:
1683: if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv)
1684: {
1685: enum machine_mode output_mode
1686: = insn_operand_mode[(int) CODE_FOR_extzv][0];
1687:
1688: if ((methods == OPTAB_DIRECT && mode == output_mode)
1689: || (methods == OPTAB_WIDEN
1690: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode)))
1691: {
1.1.1.4 root 1692: rtx shifted1 = convert_to_mode (output_mode,
1693: protect_from_queue (shifted, 0),
1694: 1);
1.1 root 1695: enum machine_mode length_mode
1696: = insn_operand_mode[(int) CODE_FOR_extzv][2];
1697: enum machine_mode pos_mode
1698: = insn_operand_mode[(int) CODE_FOR_extzv][3];
1699: rtx target1 = 0;
1700: rtx last = get_last_insn ();
1701: rtx width;
1702: rtx xop1 = op1;
1703: rtx pat;
1704:
1705: if (target != 0)
1706: target1 = protect_from_queue (target, 1);
1707:
1708: /* We define extract insns as having OUTPUT_MODE in a register
1709: and the mode of operand 1 in memory. Since we want
1710: OUTPUT_MODE, we will always force the operand into a
1711: register. At some point we might want to support MEM
1712: directly. */
1713: shifted1 = force_reg (output_mode, shifted1);
1714:
1715: /* If we don't have or cannot use a suggested target,
1716: make a place for the result, in the proper mode. */
1717: if (methods == OPTAB_WIDEN || target1 == 0
1718: || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1719: (target1, output_mode)))
1720: target1 = gen_reg_rtx (output_mode);
1721:
1.1.1.4 root 1722: xop1 = protect_from_queue (xop1, 0);
1.1 root 1723: xop1 = convert_to_mode (pos_mode, xop1,
1724: TREE_UNSIGNED (TREE_TYPE (amount)));
1725:
1726: /* If this machine's extzv insists on a register for
1727: operand 3 (position), arrange for that. */
1728: if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3])
1729: (xop1, pos_mode)))
1730: xop1 = force_reg (pos_mode, xop1);
1731:
1732: /* WIDTH gets the width of the bit field to extract:
1733: wordsize minus # bits to shift by. */
1734: if (GET_CODE (xop1) == CONST_INT)
1.1.1.4 root 1735: width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1));
1.1 root 1736: else
1737: {
1738: /* Now get the width in the proper mode. */
1.1.1.4 root 1739: op1 = protect_from_queue (op1, 0);
1.1 root 1740: width = convert_to_mode (length_mode, op1,
1741: TREE_UNSIGNED (TREE_TYPE (amount)));
1742:
1743: width = expand_binop (length_mode, sub_optab,
1.1.1.4 root 1744: GEN_INT (GET_MODE_BITSIZE (mode)),
1745: width, NULL_RTX, 0, OPTAB_LIB_WIDEN);
1.1 root 1746: }
1747:
1748: /* If this machine's extzv insists on a register for
1749: operand 2 (length), arrange for that. */
1750: if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2])
1751: (width, length_mode)))
1752: width = force_reg (length_mode, width);
1753:
1754: /* Now extract with WIDTH, omitting OP1 least sig bits. */
1755: pat = gen_extzv (target1, shifted1, width, xop1);
1756: if (pat)
1757: {
1758: emit_insn (pat);
1759: temp = convert_to_mode (mode, target1, 1);
1760: }
1761: else
1762: delete_insns_since (last);
1763: }
1764:
1765: /* Can also do logical shift with signed bit-field extract
1766: followed by inserting the bit-field at a different position.
1767: That strategy is not yet implemented. */
1768: }
1769: #endif /* HAVE_extzv */
1770: }
1771:
1772: if (temp == 0)
1773: abort ();
1774: return temp;
1775: }
1776:
1.1.1.5 ! root 1777: enum alg_code { alg_zero, alg_m, alg_shift,
! 1778: alg_add_t_m2, alg_sub_t_m2,
! 1779: alg_add_factor, alg_sub_factor,
! 1780: alg_add_t2_m, alg_sub_t2_m,
! 1781: alg_add, alg_subtract, alg_factor, alg_shiftop };
1.1 root 1782:
1783: /* This structure records a sequence of operations.
1784: `ops' is the number of operations recorded.
1785: `cost' is their total cost.
1786: The operations are stored in `op' and the corresponding
1.1.1.5 ! root 1787: logarithms of the integer coefficients in `log'.
! 1788:
1.1 root 1789: These are the operations:
1.1.1.5 ! root 1790: alg_zero total := 0;
! 1791: alg_m total := multiplicand;
! 1792: alg_shift total := total * coeff
! 1793: alg_add_t_m2 total := total + multiplicand * coeff;
! 1794: alg_sub_t_m2 total := total - multiplicand * coeff;
! 1795: alg_add_factor total := total * coeff + total;
! 1796: alg_sub_factor total := total * coeff - total;
! 1797: alg_add_t2_m total := total * coeff + multiplicand;
! 1798: alg_sub_t2_m total := total * coeff - multiplicand;
1.1 root 1799:
1.1.1.5 ! root 1800: The first operand must be either alg_zero or alg_m. */
1.1 root 1801:
1802: struct algorithm
1803: {
1.1.1.5 ! root 1804: short cost;
! 1805: short ops;
! 1806: /* The size of the OP and LOG fields are not directly related to the
! 1807: word size, but the worst-case algorithms will be if we have few
! 1808: consecutive ones or zeros, i.e., a multiplicand like 10101010101...
! 1809: In that case we will generate shift-by-2, add, shift-by-2, add,...,
! 1810: in total wordsize operations. */
1.1 root 1811: enum alg_code op[MAX_BITS_PER_WORD];
1.1.1.5 ! root 1812: char log[MAX_BITS_PER_WORD];
1.1 root 1813: };
1814:
1815: /* Compute and return the best algorithm for multiplying by T.
1.1.1.5 ! root 1816: The algorithm must cost less than cost_limit
! 1817: If retval.cost >= COST_LIMIT, no algorithm was found and all
! 1818: other field of the returned struct are undefined. */
1.1 root 1819:
1820: static struct algorithm
1.1.1.5 ! root 1821: synth_mult (t, cost_limit)
1.1.1.4 root 1822: unsigned HOST_WIDE_INT t;
1.1.1.5 ! root 1823: int cost_limit;
1.1 root 1824: {
1.1.1.5 ! root 1825: int m;
1.1.1.4 root 1826: struct algorithm *best_alg
1827: = (struct algorithm *)alloca (sizeof (struct algorithm));
1828: struct algorithm *alg_in
1829: = (struct algorithm *)alloca (sizeof (struct algorithm));
1.1 root 1830: unsigned int cost;
1.1.1.5 ! root 1831: unsigned HOST_WIDE_INT q;
1.1 root 1832:
1.1.1.5 ! root 1833: /* Indicate that no algorithm is yet found. If no algorithm
! 1834: is found, this value will be returned and indicate failure. */
! 1835: best_alg->cost = cost_limit;
1.1 root 1836:
1.1.1.5 ! root 1837: if (cost_limit <= 0)
! 1838: return *best_alg;
1.1 root 1839:
1.1.1.5 ! root 1840: /* t == 1 can be done in zero cost. */
! 1841: if (t == 1)
1.1 root 1842: {
1.1.1.5 ! root 1843: best_alg->ops = 1;
! 1844: best_alg->cost = 0;
! 1845: best_alg->op[0] = alg_m;
1.1 root 1846: return *best_alg;
1847: }
1848:
1.1.1.5 ! root 1849: /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
! 1850: fail now. */
1.1 root 1851:
1.1.1.5 ! root 1852: else if (t == 0)
1.1 root 1853: {
1.1.1.5 ! root 1854: if (zero_cost >= cost_limit)
! 1855: return *best_alg;
! 1856: else
1.1 root 1857: {
1.1.1.5 ! root 1858: best_alg->ops = 1;
! 1859: best_alg->cost = zero_cost;
! 1860: best_alg->op[0] = alg_zero;
! 1861: return *best_alg;
1.1 root 1862: }
1.1.1.5 ! root 1863: }
1.1 root 1864:
1.1.1.5 ! root 1865: /* If we have a group of zero bits at the low-order part of T, try
! 1866: multiplying by the remaining bits and then doing a shift. */
1.1 root 1867:
1.1.1.5 ! root 1868: if ((t & 1) == 0)
! 1869: {
! 1870: m = floor_log2 (t & -t); /* m = number of low zero bits */
! 1871: q = t >> m;
! 1872: cost = shift_cost[m];
! 1873: if (cost < cost_limit)
! 1874: {
! 1875: *alg_in = synth_mult (q, cost_limit - cost);
1.1 root 1876:
1.1.1.5 ! root 1877: cost += alg_in->cost;
! 1878: if (cost < best_alg->cost)
1.1 root 1879: {
1.1.1.5 ! root 1880: struct algorithm *x;
! 1881: x = alg_in, alg_in = best_alg, best_alg = x;
! 1882: best_alg->log[best_alg->ops] = m;
! 1883: best_alg->op[best_alg->ops++] = alg_shift;
! 1884: best_alg->cost = cost_limit = cost;
1.1 root 1885: }
1886: }
1887: }
1888:
1.1.1.5 ! root 1889: /* If we have an odd number, add or subtract one. */
! 1890: if ((t & 1) != 0)
1.1 root 1891: {
1.1.1.5 ! root 1892: unsigned HOST_WIDE_INT w;
1.1 root 1893:
1.1.1.5 ! root 1894: for (w = 1; (w & t) != 0; w <<= 1)
! 1895: ;
! 1896: if (w > 2
! 1897: /* Reject the case where t is 3.
! 1898: Thus we prefer addition in that case. */
! 1899: && t != 3)
1.1 root 1900: {
1.1.1.5 ! root 1901: /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
1.1 root 1902:
1.1.1.5 ! root 1903: cost = add_cost;
! 1904: *alg_in = synth_mult (t + 1, cost_limit - cost);
1.1 root 1905:
1.1.1.5 ! root 1906: cost += alg_in->cost;
! 1907: if (cost < best_alg->cost)
1.1 root 1908: {
1.1.1.5 ! root 1909: struct algorithm *x;
! 1910: x = alg_in, alg_in = best_alg, best_alg = x;
! 1911: best_alg->log[best_alg->ops] = 0;
! 1912: best_alg->op[best_alg->ops++] = alg_sub_t_m2;
! 1913: best_alg->cost = cost_limit = cost;
! 1914: }
! 1915: }
! 1916: else
! 1917: {
! 1918: /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
1.1 root 1919:
1.1.1.5 ! root 1920: cost = add_cost;
! 1921: *alg_in = synth_mult (t - 1, cost_limit - cost);
! 1922:
! 1923: cost += alg_in->cost;
! 1924: if (cost < best_alg->cost)
! 1925: {
! 1926: struct algorithm *x;
! 1927: x = alg_in, alg_in = best_alg, best_alg = x;
! 1928: best_alg->log[best_alg->ops] = 0;
! 1929: best_alg->op[best_alg->ops++] = alg_add_t_m2;
! 1930: best_alg->cost = cost_limit = cost;
1.1 root 1931: }
1932: }
1933: }
1934:
1.1.1.5 ! root 1935: /* Look for factors of t of the form
! 1936: t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
! 1937: If we find such a factor, we can multiply by t using an algorithm that
! 1938: multiplies by q, shift the result by m and add/subtract it to itself.
1.1 root 1939:
1.1.1.5 ! root 1940: We search for large factors first and loop down, even if large factors
! 1941: are less probable than small; if we find a large factor we will find a
! 1942: good sequence quickly, and therefore be able to prune (by decreasing
! 1943: COST_LIMIT) the search. */
1.1 root 1944:
1.1.1.5 ! root 1945: for (m = floor_log2 (t - 1); m >= 2; m--)
! 1946: {
! 1947: unsigned HOST_WIDE_INT d;
1.1 root 1948:
1.1.1.5 ! root 1949: d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
! 1950: if (t % d == 0 && t > d)
! 1951: {
! 1952: cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
! 1953: *alg_in = synth_mult (t / d, cost_limit - cost);
1.1 root 1954:
1.1.1.5 ! root 1955: cost += alg_in->cost;
! 1956: if (cost < best_alg->cost)
! 1957: {
! 1958: struct algorithm *x;
! 1959: x = alg_in, alg_in = best_alg, best_alg = x;
! 1960: best_alg->log[best_alg->ops] = m;
! 1961: best_alg->op[best_alg->ops++] = alg_add_factor;
! 1962: best_alg->cost = cost_limit = cost;
! 1963: }
! 1964: }
1.1 root 1965:
1.1.1.5 ! root 1966: d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
! 1967: if (t % d == 0 && t > d)
! 1968: {
! 1969: cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
! 1970: *alg_in = synth_mult (t / d, cost_limit - cost);
1.1 root 1971:
1.1.1.5 ! root 1972: cost += alg_in->cost;
! 1973: if (cost < best_alg->cost)
! 1974: {
! 1975: struct algorithm *x;
! 1976: x = alg_in, alg_in = best_alg, best_alg = x;
! 1977: best_alg->log[best_alg->ops] = m;
! 1978: best_alg->op[best_alg->ops++] = alg_sub_factor;
! 1979: best_alg->cost = cost_limit = cost;
! 1980: }
! 1981: }
! 1982: }
1.1 root 1983:
1.1.1.5 ! root 1984: /* Try shift-and-add (load effective address) instructions,
! 1985: i.e. do a*3, a*5, a*9. */
! 1986: if ((t & 1) != 0)
! 1987: {
! 1988: q = t - 1;
! 1989: q = q & -q;
! 1990: m = exact_log2 (q);
! 1991: if (m >= 0)
! 1992: {
! 1993: cost = shiftadd_cost[m];
! 1994: *alg_in = synth_mult ((t - 1) >> m, cost_limit - cost);
! 1995:
! 1996: cost += alg_in->cost;
! 1997: if (cost < best_alg->cost)
! 1998: {
! 1999: struct algorithm *x;
! 2000: x = alg_in, alg_in = best_alg, best_alg = x;
! 2001: best_alg->log[best_alg->ops] = m;
! 2002: best_alg->op[best_alg->ops++] = alg_add_t2_m;
! 2003: best_alg->cost = cost_limit = cost;
! 2004: }
! 2005: }
1.1 root 2006:
1.1.1.5 ! root 2007: q = t + 1;
! 2008: q = q & -q;
! 2009: m = exact_log2 (q);
! 2010: if (m >= 0)
! 2011: {
! 2012: cost = shiftsub_cost[m];
! 2013: *alg_in = synth_mult ((t + 1) >> m, cost_limit - cost);
1.1 root 2014:
1.1.1.5 ! root 2015: cost += alg_in->cost;
! 2016: if (cost < best_alg->cost)
! 2017: {
! 2018: struct algorithm *x;
! 2019: x = alg_in, alg_in = best_alg, best_alg = x;
! 2020: best_alg->log[best_alg->ops] = m;
! 2021: best_alg->op[best_alg->ops++] = alg_sub_t2_m;
! 2022: best_alg->cost = cost_limit = cost;
! 2023: }
! 2024: }
! 2025: }
1.1 root 2026:
1.1.1.5 ! root 2027: /* If we are getting a too long sequence for `struct algorithm'
! 2028: to record, store a fake cost to make this search fail. */
! 2029: if (best_alg->ops == MAX_BITS_PER_WORD)
! 2030: best_alg->cost = cost_limit;
1.1 root 2031:
2032: return *best_alg;
2033: }
2034:
2035: /* Perform a multiplication and return an rtx for the result.
2036: MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2037: TARGET is a suggestion for where to store the result (an rtx).
2038:
2039: We check specially for a constant integer as OP1.
2040: If you want this check for OP0 as well, then before calling
2041: you should swap the two operands if OP0 would be constant. */
2042:
2043: rtx
2044: expand_mult (mode, op0, op1, target, unsignedp)
2045: enum machine_mode mode;
2046: register rtx op0, op1, target;
2047: int unsignedp;
2048: {
2049: rtx const_op1 = op1;
2050:
2051: /* If we are multiplying in DImode, it may still be a win
2052: to try to work with shifts and adds. */
2053: if (GET_CODE (op1) == CONST_DOUBLE
2054: && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2055: && HOST_BITS_PER_INT <= BITS_PER_WORD)
2056: {
2057: if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0)
2058: || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0))
1.1.1.4 root 2059: const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1.1 root 2060: }
2061:
1.1.1.3 root 2062: /* We used to test optimize here, on the grounds that it's better to
2063: produce a smaller program when -O is not used.
2064: But this causes such a terrible slowdown sometimes
2065: that it seems better to use synth_mult always. */
1.1.1.5 ! root 2066:
1.1.1.3 root 2067: if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap)
1.1 root 2068: {
2069: struct algorithm alg;
2070: struct algorithm neg_alg;
2071: int negate = 0;
1.1.1.5 ! root 2072: HOST_WIDE_INT val = INTVAL (op1);
! 2073: HOST_WIDE_INT val_so_far;
! 2074: rtx insn;
1.1 root 2075:
2076: /* Try to do the computation two ways: multiply by the negative of OP1
2077: and then negate, or do the multiplication directly. The latter is
2078: usually faster for positive numbers and the former for negative
2079: numbers, but the opposite can be faster if the original value
2080: has a factor of 2**m +/- 1, while the negated value does not or
2081: vice versa. */
2082:
1.1.1.5 ! root 2083: alg = synth_mult (val, mult_cost);
! 2084: neg_alg = synth_mult (- val,
! 2085: (alg.cost < mult_cost ? alg.cost : mult_cost)
1.1.1.4 root 2086: - negate_cost);
1.1 root 2087:
1.1.1.5 ! root 2088: if (neg_alg.cost + negate_cost < alg.cost)
! 2089: alg = neg_alg, negate = 1;
1.1 root 2090:
1.1.1.5 ! root 2091: if (alg.cost < mult_cost)
1.1 root 2092: {
1.1.1.5 ! root 2093: /* We found something cheaper than a multiply insn. */
! 2094: int opno;
1.1 root 2095: rtx accum, tem;
2096:
2097: op0 = protect_from_queue (op0, 0);
2098:
2099: /* Avoid referencing memory over and over.
2100: For speed, but also for correctness when mem is volatile. */
2101: if (GET_CODE (op0) == MEM)
2102: op0 = force_reg (mode, op0);
2103:
1.1.1.5 ! root 2104: /* ACCUM starts out either as OP0 or as a zero, depending on
! 2105: the first operation. */
! 2106:
! 2107: if (alg.op[0] == alg_zero)
! 2108: {
! 2109: accum = copy_to_mode_reg (mode, const0_rtx);
! 2110: val_so_far = 0;
! 2111: }
! 2112: else if (alg.op[0] == alg_m)
! 2113: {
! 2114: accum = copy_to_mode_reg (mode, op0);
! 2115: val_so_far = 1;
! 2116: }
1.1 root 2117: else
1.1.1.5 ! root 2118: abort ();
! 2119:
! 2120: for (opno = 1; opno < alg.ops; opno++)
1.1 root 2121: {
1.1.1.5 ! root 2122: int log = alg.log[opno];
! 2123: rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum;
! 2124: rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0;
! 2125:
1.1 root 2126: switch (alg.op[opno])
2127: {
1.1.1.5 ! root 2128: case alg_shift:
! 2129: accum = expand_shift (LSHIFT_EXPR, mode, accum,
! 2130: build_int_2 (log, 0), NULL_RTX, 0);
! 2131: val_so_far <<= log;
1.1 root 2132: break;
2133:
1.1.1.5 ! root 2134: case alg_add_t_m2:
! 2135: tem = expand_shift (LSHIFT_EXPR, mode, op0,
! 2136: build_int_2 (log, 0), NULL_RTX, 0);
! 2137: accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
! 2138: add_target ? add_target : accum);
! 2139: val_so_far += (HOST_WIDE_INT) 1 << log;
! 2140: break;
! 2141:
! 2142: case alg_sub_t_m2:
! 2143: tem = expand_shift (LSHIFT_EXPR, mode, op0,
! 2144: build_int_2 (log, 0), NULL_RTX, 0);
! 2145: accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
! 2146: add_target ? add_target : accum);
! 2147: val_so_far -= (HOST_WIDE_INT) 1 << log;
! 2148: break;
! 2149:
! 2150: case alg_add_t2_m:
! 2151: accum = expand_shift (LSHIFT_EXPR, mode, accum,
! 2152: build_int_2 (log, 0), accum, 0);
! 2153: accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
! 2154: add_target ? add_target : accum);
! 2155: val_so_far = (val_so_far << log) + 1;
! 2156: break;
! 2157:
! 2158: case alg_sub_t2_m:
! 2159: accum = expand_shift (LSHIFT_EXPR, mode, accum,
! 2160: build_int_2 (log, 0), accum, 0);
! 2161: accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
! 2162: add_target ? add_target : accum);
! 2163: val_so_far = (val_so_far << log) - 1;
! 2164: break;
1.1 root 2165:
1.1.1.5 ! root 2166: case alg_add_factor:
! 2167: tem = expand_shift (LSHIFT_EXPR, mode, accum,
! 2168: build_int_2 (log, 0), NULL_RTX, 0);
! 2169: accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
! 2170: add_target ? add_target : accum);
! 2171: val_so_far += val_so_far << log;
1.1 root 2172: break;
2173:
1.1.1.5 ! root 2174: case alg_sub_factor:
1.1 root 2175: tem = expand_shift (LSHIFT_EXPR, mode, accum,
1.1.1.4 root 2176: build_int_2 (log, 0), NULL_RTX, 0);
1.1.1.5 ! root 2177: accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
! 2178: add_target ? add_target : tem);
! 2179: val_so_far = (val_so_far << log) - val_so_far;
! 2180: break;
1.1 root 2181:
1.1.1.5 ! root 2182: default:
! 2183: abort ();;
1.1 root 2184: }
2185:
1.1.1.5 ! root 2186: /* Write a REG_EQUAL note on the last insn so that we can cse
! 2187: multiplication sequences. */
1.1 root 2188:
1.1.1.5 ! root 2189: insn = get_last_insn ();
! 2190: REG_NOTES (insn)
! 2191: = gen_rtx (EXPR_LIST, REG_EQUAL,
! 2192: gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)),
! 2193: REG_NOTES (insn));
! 2194: }
1.1 root 2195:
1.1.1.5 ! root 2196: if (negate)
1.1 root 2197: {
1.1.1.5 ! root 2198: val_so_far = - val_so_far;
! 2199: accum = expand_unop (mode, neg_optab, accum, target, 0);
1.1 root 2200: }
2201:
1.1.1.5 ! root 2202: if (val != val_so_far)
! 2203: abort ();
! 2204:
! 2205: return accum;
1.1 root 2206: }
2207: }
2208:
2209: /* This used to use umul_optab if unsigned,
1.1.1.5 ! root 2210: but for non-widening multiply there is no difference
1.1 root 2211: between signed and unsigned. */
2212: op0 = expand_binop (mode, smul_optab,
2213: op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2214: if (op0 == 0)
2215: abort ();
2216: return op0;
2217: }
2218:
2219: /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2220: if that is convenient, and returning where the result is.
2221: You may request either the quotient or the remainder as the result;
2222: specify REM_FLAG nonzero to get the remainder.
2223:
2224: CODE is the expression code for which kind of division this is;
2225: it controls how rounding is done. MODE is the machine mode to use.
2226: UNSIGNEDP nonzero means do unsigned division. */
2227:
2228: /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2229: and then correct it by or'ing in missing high bits
2230: if result of ANDI is nonzero.
2231: For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2232: This could optimize to a bfexts instruction.
2233: But C doesn't use these operations, so their optimizations are
2234: left for later. */
2235:
2236: rtx
2237: expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2238: int rem_flag;
2239: enum tree_code code;
2240: enum machine_mode mode;
2241: register rtx op0, op1, target;
2242: int unsignedp;
2243: {
2244: register rtx result = 0;
2245: enum machine_mode compute_mode;
2246: int log = -1;
1.1.1.4 root 2247: int size;
1.1 root 2248: int can_clobber_op0;
2249: int mod_insn_no_good = 0;
2250: rtx adjusted_op0 = op0;
2251: optab optab1, optab2;
2252:
1.1.1.4 root 2253: /* We shouldn't be called with op1 == const1_rtx, but some of the
2254: code below will malfunction if we are, so check here and handle
2255: the special case if so. */
2256: if (op1 == const1_rtx)
2257: return rem_flag ? const0_rtx : op0;
2258:
1.1 root 2259: /* Don't use the function value register as a target
2260: since we have to read it as well as write it,
2261: and function-inlining gets confused by this. */
2262: if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target))
2263: target = 0;
2264:
2265: /* Don't clobber an operand while doing a multi-step calculation. */
2266: if (target)
2267: if ((rem_flag && (reg_mentioned_p (target, op0)
2268: || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2269: || reg_mentioned_p (target, op1)
2270: || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))
2271: target = 0;
2272:
2273: can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target);
2274:
2275: if (GET_CODE (op1) == CONST_INT)
2276: log = exact_log2 (INTVAL (op1));
2277:
2278: /* If log is >= 0, we are dividing by 2**log, and will do it by shifting,
2279: which is really floor-division. Otherwise we will really do a divide,
2280: and we assume that is trunc-division.
2281:
2282: We must correct the dividend by adding or subtracting something
2283: based on the divisor, in order to do the kind of rounding specified
2284: by CODE. The correction depends on what kind of rounding is actually
2285: available, and that depends on whether we will shift or divide.
2286:
2287: In many of these cases it is possible to perform the operation by a
2288: clever series of logical operations (shifts and/or exclusive-ors).
2289: Although avoiding the jump has the advantage that it extends the basic
2290: block and allows further optimization, the branch-free code is normally
2291: at least one instruction longer in the (most common) case where the
2292: dividend is non-negative. Performance measurements of the two
2293: alternatives show that the branch-free code is slightly faster on the
2294: IBM ROMP but slower on CISC processors (significantly slower on the
2295: VAX). Accordingly, the jump code has been retained.
2296:
2297: On machines where the jump code is slower, the cost of a DIV or MOD
2298: operation can be set small (less than twice that of an addition); in
2299: that case, we pretend that we don't have a power of two and perform
2300: a normal division or modulus operation. */
2301:
2302: if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR)
2303: && ! unsignedp
2304: && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2305: log = -1;
2306:
2307: /* Get the mode in which to perform this computation. Normally it will
2308: be MODE, but sometimes we can't do the desired operation in MODE.
2309: If so, pick a wider mode in which we can do the operation. Convert
2310: to that mode at the start to avoid repeated conversions.
2311:
2312: First see what operations we need. These depend on the expression
2313: we are evaluating. (We assume that divxx3 insns exist under the
2314: same conditions that modxx3 insns and that these insns don't normally
2315: fail. If these assumptions are not correct, we may generate less
2316: efficient code in some cases.)
2317:
2318: Then see if we find a mode in which we can open-code that operation
2319: (either a division, modulus, or shift). Finally, check for the smallest
2320: mode for which we can do the operation with a library call. */
2321:
2322: optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab)
2323: : (unsignedp ? udiv_optab : sdiv_optab));
2324: optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2325:
2326: for (compute_mode = mode; compute_mode != VOIDmode;
2327: compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2328: if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2329: || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2330: break;
2331:
2332: if (compute_mode == VOIDmode)
2333: for (compute_mode = mode; compute_mode != VOIDmode;
2334: compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2335: if (optab1->handlers[(int) compute_mode].libfunc
2336: || optab2->handlers[(int) compute_mode].libfunc)
2337: break;
2338:
2339: /* If we still couldn't find a mode, use MODE; we'll probably abort in
2340: expand_binop. */
2341: if (compute_mode == VOIDmode)
2342: compute_mode = mode;
2343:
1.1.1.4 root 2344: size = GET_MODE_BITSIZE (compute_mode);
2345:
1.1 root 2346: /* Now convert to the best mode to use. Show we made a copy of OP0
2347: and hence we can clobber it (we cannot use a SUBREG to widen
2348: something. */
2349: if (compute_mode != mode)
2350: {
2351: adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp);
2352: can_clobber_op0 = 1;
2353: op1 = convert_to_mode (compute_mode, op1, unsignedp);
2354: }
2355:
1.1.1.3 root 2356: /* If we are computing the remainder and one of the operands is a volatile
2357: MEM, copy it into a register. */
2358:
2359: if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2360: adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1;
2361: if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2362: op1 = force_reg (compute_mode, op1);
2363:
2364: /* If we are computing the remainder, op0 will be needed later to calculate
2365: X - Y * (X / Y), therefore cannot be clobbered. */
2366: if (rem_flag)
2367: can_clobber_op0 = 0;
2368:
1.1 root 2369: if (target == 0 || GET_MODE (target) != compute_mode)
2370: target = gen_reg_rtx (compute_mode);
2371:
2372: switch (code)
2373: {
2374: case TRUNC_MOD_EXPR:
2375: case TRUNC_DIV_EXPR:
2376: if (log >= 0 && ! unsignedp)
2377: {
1.1.1.4 root 2378: /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise.
2379: This can be computed without jumps by arithmetically shifting
2380: OP0 right LOG-1 places and then shifting right logically
2381: SIZE-LOG bits. The resulting value is unconditionally added
2382: to OP0. */
2383: if (log == 1 || BRANCH_COST >= 3)
2384: {
2385: rtx temp = gen_reg_rtx (compute_mode);
1.1.1.5 ! root 2386: if (! can_clobber_op0)
! 2387: /* Copy op0 to a reg, to play safe,
! 2388: since this is done in the other path. */
! 2389: op0 = force_reg (compute_mode, op0);
1.1.1.4 root 2390: temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2391: temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2392: build_int_2 (log - 1, 0), NULL_RTX, 0);
2393: temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2394: build_int_2 (size - log, 0),
2395: temp, 1);
1.1.1.5 ! root 2396: /* We supply 0 as the target to make a new pseudo
! 2397: for the value; that helps loop.c optimize the result. */
! 2398: adjusted_op0 = expand_binop (compute_mode, add_optab,
! 2399: adjusted_op0, temp,
! 2400: 0, 0, OPTAB_LIB_WIDEN);
1.1.1.4 root 2401: }
2402: else
2403: {
2404: rtx label = gen_label_rtx ();
1.1.1.5 ! root 2405: if (! can_clobber_op0)
! 2406: {
! 2407: adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
! 2408: compute_mode);
! 2409: /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
! 2410: which will screw up mem refs for autoincrements. */
! 2411: op0 = force_reg (compute_mode, op0);
! 2412: }
1.1.1.4 root 2413: emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2414: NULL_RTX, compute_mode, 0, 0);
2415: emit_jump_insn (gen_bge (label));
2416: expand_inc (adjusted_op0, plus_constant (op1, -1));
2417: emit_label (label);
2418: }
1.1 root 2419: mod_insn_no_good = 1;
2420: }
2421: break;
2422:
2423: case FLOOR_DIV_EXPR:
2424: case FLOOR_MOD_EXPR:
2425: if (log < 0 && ! unsignedp)
2426: {
2427: rtx label = gen_label_rtx ();
2428: if (! can_clobber_op0)
2429: {
1.1.1.2 root 2430: adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2431: compute_mode);
1.1 root 2432: /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2433: which will screw up mem refs for autoincrements. */
2434: op0 = force_reg (compute_mode, op0);
2435: }
1.1.1.4 root 2436: emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2437: NULL_RTX, compute_mode, 0, 0);
1.1 root 2438: emit_jump_insn (gen_bge (label));
2439: expand_dec (adjusted_op0, op1);
2440: expand_inc (adjusted_op0, const1_rtx);
2441: emit_label (label);
2442: mod_insn_no_good = 1;
2443: }
2444: break;
2445:
2446: case CEIL_DIV_EXPR:
2447: case CEIL_MOD_EXPR:
2448: if (! can_clobber_op0)
2449: {
1.1.1.2 root 2450: adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2451: compute_mode);
1.1 root 2452: /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2453: which will screw up mem refs for autoincrements. */
2454: op0 = force_reg (compute_mode, op0);
2455: }
2456: if (log < 0)
2457: {
2458: rtx label = 0;
2459: if (! unsignedp)
2460: {
2461: label = gen_label_rtx ();
1.1.1.4 root 2462: emit_cmp_insn (adjusted_op0, const0_rtx, LE,
2463: NULL_RTX, compute_mode, 0, 0);
1.1 root 2464: emit_jump_insn (gen_ble (label));
2465: }
2466: expand_inc (adjusted_op0, op1);
2467: expand_dec (adjusted_op0, const1_rtx);
2468: if (! unsignedp)
2469: emit_label (label);
2470: }
2471: else
2472: {
2473: adjusted_op0 = expand_binop (compute_mode, add_optab,
2474: adjusted_op0, plus_constant (op1, -1),
1.1.1.4 root 2475: NULL_RTX, 0, OPTAB_LIB_WIDEN);
1.1 root 2476: }
2477: mod_insn_no_good = 1;
2478: break;
2479:
2480: case ROUND_DIV_EXPR:
2481: case ROUND_MOD_EXPR:
2482: if (! can_clobber_op0)
2483: {
1.1.1.2 root 2484: adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2485: compute_mode);
1.1 root 2486: /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2487: which will screw up mem refs for autoincrements. */
2488: op0 = force_reg (compute_mode, op0);
2489: }
2490: if (log < 0)
2491: {
2492: op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1,
1.1.1.4 root 2493: integer_one_node, NULL_RTX, 0);
1.1 root 2494: if (! unsignedp)
2495: {
1.1.1.4 root 2496: if (BRANCH_COST >= 2)
2497: {
2498: /* Negate OP1 if OP0 < 0. Do this by computing a temporary
2499: that has all bits equal to the sign bit and exclusive
2500: or-ing it with OP1. */
2501: rtx temp = gen_reg_rtx (compute_mode);
2502: temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2503: temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2504: build_int_2 (size - 1, 0),
2505: NULL_RTX, 0);
2506: op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1,
2507: unsignedp, OPTAB_LIB_WIDEN);
2508: }
2509: else
2510: {
2511: rtx label = gen_label_rtx ();
2512: emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX,
2513: compute_mode, 0, 0);
2514: emit_jump_insn (gen_bge (label));
2515: expand_unop (compute_mode, neg_optab, op1, op1, 0);
2516: emit_label (label);
2517: }
1.1 root 2518: }
2519: expand_inc (adjusted_op0, op1);
2520: }
2521: else
2522: {
1.1.1.4 root 2523: op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2);
1.1 root 2524: expand_inc (adjusted_op0, op1);
2525: }
2526: mod_insn_no_good = 1;
2527: break;
2528: }
2529:
2530: if (rem_flag && !mod_insn_no_good)
2531: {
2532: /* Try to produce the remainder directly */
2533: if (log >= 0)
2534: result = expand_binop (compute_mode, and_optab, adjusted_op0,
1.1.1.4 root 2535: GEN_INT (((HOST_WIDE_INT) 1 << log) - 1),
1.1 root 2536: target, 1, OPTAB_LIB_WIDEN);
2537: else
2538: {
2539: /* See if we can do remainder without a library call. */
2540: result = sign_expand_binop (mode, umod_optab, smod_optab,
2541: adjusted_op0, op1, target,
2542: unsignedp, OPTAB_WIDEN);
2543: if (result == 0)
2544: {
2545: /* No luck there. Can we do remainder and divide at once
2546: without a library call? */
2547: result = gen_reg_rtx (compute_mode);
2548: if (! expand_twoval_binop (unsignedp
2549: ? udivmod_optab : sdivmod_optab,
2550: adjusted_op0, op1,
1.1.1.4 root 2551: NULL_RTX, result, unsignedp))
1.1 root 2552: result = 0;
2553: }
2554: }
2555: }
2556:
2557: if (result)
2558: return gen_lowpart (mode, result);
2559:
2560: /* Produce the quotient. */
2561: if (log >= 0)
2562: result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0,
2563: build_int_2 (log, 0), target, unsignedp);
2564: else if (rem_flag && !mod_insn_no_good)
2565: /* If producing quotient in order to subtract for remainder,
2566: and a remainder subroutine would be ok,
2567: don't use a divide subroutine. */
2568: result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
1.1.1.4 root 2569: adjusted_op0, op1, NULL_RTX, unsignedp,
2570: OPTAB_WIDEN);
1.1 root 2571: else
2572: {
2573: /* Try a quotient insn, but not a library call. */
2574: result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
1.1.1.4 root 2575: adjusted_op0, op1,
2576: rem_flag ? NULL_RTX : target,
1.1 root 2577: unsignedp, OPTAB_WIDEN);
2578: if (result == 0)
2579: {
2580: /* No luck there. Try a quotient-and-remainder insn,
2581: keeping the quotient alone. */
2582: result = gen_reg_rtx (mode);
2583: if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
2584: adjusted_op0, op1,
1.1.1.4 root 2585: result, NULL_RTX, unsignedp))
1.1 root 2586: result = 0;
2587: }
2588:
2589: /* If still no luck, use a library call. */
2590: if (result == 0)
2591: result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
1.1.1.4 root 2592: adjusted_op0, op1,
2593: rem_flag ? NULL_RTX : target,
1.1 root 2594: unsignedp, OPTAB_LIB_WIDEN);
2595: }
2596:
2597: /* If we really want the remainder, get it by subtraction. */
2598: if (rem_flag)
2599: {
2600: if (result == 0)
2601: /* No divide instruction either. Use library for remainder. */
2602: result = sign_expand_binop (compute_mode, umod_optab, smod_optab,
2603: op0, op1, target,
2604: unsignedp, OPTAB_LIB_WIDEN);
2605: else
2606: {
2607: /* We divided. Now finish doing X - Y * (X / Y). */
2608: result = expand_mult (compute_mode, result, op1, target, unsignedp);
2609: if (! result) abort ();
2610: result = expand_binop (compute_mode, sub_optab, op0,
2611: result, target, unsignedp, OPTAB_LIB_WIDEN);
2612: }
2613: }
2614:
2615: if (result == 0)
2616: abort ();
2617:
2618: return gen_lowpart (mode, result);
2619: }
2620:
2621: /* Return a tree node with data type TYPE, describing the value of X.
2622: Usually this is an RTL_EXPR, if there is no obvious better choice.
2623: X may be an expression, however we only support those expressions
2624: generated by loop.c. */
2625:
2626: tree
2627: make_tree (type, x)
2628: tree type;
2629: rtx x;
2630: {
2631: tree t;
2632:
2633: switch (GET_CODE (x))
2634: {
2635: case CONST_INT:
2636: t = build_int_2 (INTVAL (x),
2637: ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1);
2638: TREE_TYPE (t) = type;
2639: return t;
2640:
2641: case CONST_DOUBLE:
2642: if (GET_MODE (x) == VOIDmode)
2643: {
2644: t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
2645: TREE_TYPE (t) = type;
2646: }
2647: else
2648: {
2649: REAL_VALUE_TYPE d;
2650:
2651: REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2652: t = build_real (type, d);
2653: }
2654:
2655: return t;
2656:
2657: case PLUS:
2658: return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2659: make_tree (type, XEXP (x, 1))));
2660:
2661: case MINUS:
2662: return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2663: make_tree (type, XEXP (x, 1))));
2664:
2665: case NEG:
2666: return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
2667:
2668: case MULT:
2669: return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
2670: make_tree (type, XEXP (x, 1))));
2671:
2672: case ASHIFT:
2673: return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
2674: make_tree (type, XEXP (x, 1))));
2675:
2676: case LSHIFTRT:
2677: return fold (convert (type,
2678: build (RSHIFT_EXPR, unsigned_type (type),
2679: make_tree (unsigned_type (type),
2680: XEXP (x, 0)),
2681: make_tree (type, XEXP (x, 1)))));
2682:
2683: case ASHIFTRT:
2684: return fold (convert (type,
2685: build (RSHIFT_EXPR, signed_type (type),
2686: make_tree (signed_type (type), XEXP (x, 0)),
2687: make_tree (type, XEXP (x, 1)))));
2688:
2689: case DIV:
2690: if (TREE_CODE (type) != REAL_TYPE)
2691: t = signed_type (type);
2692: else
2693: t = type;
2694:
2695: return fold (convert (type,
2696: build (TRUNC_DIV_EXPR, t,
2697: make_tree (t, XEXP (x, 0)),
2698: make_tree (t, XEXP (x, 1)))));
2699: case UDIV:
2700: t = unsigned_type (type);
2701: return fold (convert (type,
2702: build (TRUNC_DIV_EXPR, t,
2703: make_tree (t, XEXP (x, 0)),
2704: make_tree (t, XEXP (x, 1)))));
2705: default:
2706: t = make_node (RTL_EXPR);
2707: TREE_TYPE (t) = type;
2708: RTL_EXPR_RTL (t) = x;
2709: /* There are no insns to be output
2710: when this rtl_expr is used. */
2711: RTL_EXPR_SEQUENCE (t) = 0;
2712: return t;
2713: }
2714: }
2715:
2716: /* Return an rtx representing the value of X * MULT + ADD.
2717: TARGET is a suggestion for where to store the result (an rtx).
2718: MODE is the machine mode for the computation.
2719: X and MULT must have mode MODE. ADD may have a different mode.
2720: So can X (defaults to same as MODE).
2721: UNSIGNEDP is non-zero to do unsigned multiplication.
2722: This may emit insns. */
2723:
2724: rtx
2725: expand_mult_add (x, target, mult, add, mode, unsignedp)
2726: rtx x, target, mult, add;
2727: enum machine_mode mode;
2728: int unsignedp;
2729: {
2730: tree type = type_for_mode (mode, unsignedp);
2731: tree add_type = (GET_MODE (add) == VOIDmode
1.1.1.2 root 2732: ? type : type_for_mode (GET_MODE (add), unsignedp));
1.1 root 2733: tree result = fold (build (PLUS_EXPR, type,
2734: fold (build (MULT_EXPR, type,
2735: make_tree (type, x),
2736: make_tree (type, mult))),
2737: make_tree (add_type, add)));
2738:
2739: return expand_expr (result, target, VOIDmode, 0);
2740: }
2741:
2742: /* Compute the logical-and of OP0 and OP1, storing it in TARGET
2743: and returning TARGET.
2744:
2745: If TARGET is 0, a pseudo-register or constant is returned. */
2746:
2747: rtx
2748: expand_and (op0, op1, target)
2749: rtx op0, op1, target;
2750: {
2751: enum machine_mode mode = VOIDmode;
2752: rtx tem;
2753:
2754: if (GET_MODE (op0) != VOIDmode)
2755: mode = GET_MODE (op0);
2756: else if (GET_MODE (op1) != VOIDmode)
2757: mode = GET_MODE (op1);
2758:
2759: if (mode != VOIDmode)
2760: tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
2761: else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
1.1.1.4 root 2762: tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
1.1 root 2763: else
2764: abort ();
2765:
2766: if (target == 0)
2767: target = tem;
2768: else if (tem != target)
2769: emit_move_insn (target, tem);
2770: return target;
2771: }
2772:
2773: /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
2774: and storing in TARGET. Normally return TARGET.
2775: Return 0 if that cannot be done.
2776:
2777: MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
2778: it is VOIDmode, they cannot both be CONST_INT.
2779:
2780: UNSIGNEDP is for the case where we have to widen the operands
2781: to perform the operation. It says to use zero-extension.
2782:
2783: NORMALIZEP is 1 if we should convert the result to be either zero
2784: or one one. Normalize is -1 if we should convert the result to be
2785: either zero or -1. If NORMALIZEP is zero, the result will be left
2786: "raw" out of the scc insn. */
2787:
2788: rtx
2789: emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
2790: rtx target;
2791: enum rtx_code code;
2792: rtx op0, op1;
2793: enum machine_mode mode;
2794: int unsignedp;
2795: int normalizep;
2796: {
2797: rtx subtarget;
2798: enum insn_code icode;
2799: enum machine_mode compare_mode;
2800: enum machine_mode target_mode = GET_MODE (target);
2801: rtx tem;
2802: rtx last = 0;
2803: rtx pattern, comparison;
2804:
2805: if (mode == VOIDmode)
2806: mode = GET_MODE (op0);
2807:
1.1.1.5 ! root 2808: /* If one operand is constant, make it the second one. Only do this
! 2809: if the other operand is not constant as well. */
! 2810:
! 2811: if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
! 2812: || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
! 2813: {
! 2814: tem = op0;
! 2815: op0 = op1;
! 2816: op1 = tem;
! 2817: code = swap_condition (code);
! 2818: }
! 2819:
1.1 root 2820: /* For some comparisons with 1 and -1, we can convert this to
2821: comparisons with zero. This will often produce more opportunities for
2822: store-flag insns. */
2823:
2824: switch (code)
2825: {
2826: case LT:
2827: if (op1 == const1_rtx)
2828: op1 = const0_rtx, code = LE;
2829: break;
2830: case LE:
2831: if (op1 == constm1_rtx)
2832: op1 = const0_rtx, code = LT;
2833: break;
2834: case GE:
2835: if (op1 == const1_rtx)
2836: op1 = const0_rtx, code = GT;
2837: break;
2838: case GT:
2839: if (op1 == constm1_rtx)
2840: op1 = const0_rtx, code = GE;
2841: break;
2842: case GEU:
2843: if (op1 == const1_rtx)
2844: op1 = const0_rtx, code = NE;
2845: break;
2846: case LTU:
2847: if (op1 == const1_rtx)
2848: op1 = const0_rtx, code = EQ;
2849: break;
2850: }
2851:
2852: /* From now on, we won't change CODE, so set ICODE now. */
2853: icode = setcc_gen_code[(int) code];
2854:
2855: /* If this is A < 0 or A >= 0, we can do this by taking the ones
2856: complement of A (for GE) and shifting the sign bit to the low bit. */
2857: if (op1 == const0_rtx && (code == LT || code == GE)
2858: && GET_MODE_CLASS (mode) == MODE_INT
2859: && (normalizep || STORE_FLAG_VALUE == 1
1.1.1.4 root 2860: || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2861: && (STORE_FLAG_VALUE
2862: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
1.1 root 2863: {
1.1.1.5 ! root 2864: subtarget = target;
1.1 root 2865:
2866: /* If the result is to be wider than OP0, it is best to convert it
2867: first. If it is to be narrower, it is *incorrect* to convert it
2868: first. */
2869: if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
2870: {
1.1.1.4 root 2871: op0 = protect_from_queue (op0, 0);
1.1 root 2872: op0 = convert_to_mode (target_mode, op0, 0);
2873: mode = target_mode;
2874: }
2875:
2876: if (target_mode != mode)
2877: subtarget = 0;
2878:
2879: if (code == GE)
2880: op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
2881:
2882: if (normalizep || STORE_FLAG_VALUE == 1)
2883: /* If we are supposed to produce a 0/1 value, we want to do
2884: a logical shift from the sign bit to the low-order bit; for
2885: a -1/0 value, we do an arithmetic shift. */
2886: op0 = expand_shift (RSHIFT_EXPR, mode, op0,
2887: size_int (GET_MODE_BITSIZE (mode) - 1),
2888: subtarget, normalizep != -1);
2889:
2890: if (mode != target_mode)
2891: op0 = convert_to_mode (target_mode, op0, 0);
2892:
2893: return op0;
2894: }
2895:
2896: if (icode != CODE_FOR_nothing)
2897: {
2898: /* We think we may be able to do this with a scc insn. Emit the
2899: comparison and then the scc insn.
2900:
2901: compare_from_rtx may call emit_queue, which would be deleted below
2902: if the scc insn fails. So call it ourselves before setting LAST. */
2903:
2904: emit_queue ();
2905: last = get_last_insn ();
2906:
1.1.1.4 root 2907: comparison
2908: = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
1.1 root 2909: if (GET_CODE (comparison) == CONST_INT)
2910: return (comparison == const0_rtx ? const0_rtx
2911: : normalizep == 1 ? const1_rtx
2912: : normalizep == -1 ? constm1_rtx
2913: : const_true_rtx);
2914:
1.1.1.5 ! root 2915: /* If the code of COMPARISON doesn't match CODE, something is
! 2916: wrong; we can no longer be sure that we have the operation.
! 2917: We could handle this case, but it should not happen. */
! 2918:
! 2919: if (GET_CODE (comparison) != code)
! 2920: abort ();
! 2921:
1.1 root 2922: /* Get a reference to the target in the proper mode for this insn. */
2923: compare_mode = insn_operand_mode[(int) icode][0];
2924: subtarget = target;
2925: if (preserve_subexpressions_p ()
2926: || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
2927: subtarget = gen_reg_rtx (compare_mode);
2928:
2929: pattern = GEN_FCN (icode) (subtarget);
2930: if (pattern)
2931: {
2932: emit_insn (pattern);
2933:
2934: /* If we are converting to a wider mode, first convert to
2935: TARGET_MODE, then normalize. This produces better combining
2936: opportunities on machines that have a SIGN_EXTRACT when we are
2937: testing a single bit. This mostly benefits the 68k.
2938:
2939: If STORE_FLAG_VALUE does not have the sign bit set when
2940: interpreted in COMPARE_MODE, we can do this conversion as
2941: unsigned, which is usually more efficient. */
2942: if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
2943: {
2944: convert_move (target, subtarget,
2945: (GET_MODE_BITSIZE (compare_mode)
1.1.1.4 root 2946: <= HOST_BITS_PER_WIDE_INT)
1.1 root 2947: && 0 == (STORE_FLAG_VALUE
1.1.1.4 root 2948: & ((HOST_WIDE_INT) 1
2949: << (GET_MODE_BITSIZE (compare_mode) -1))));
1.1 root 2950: op0 = target;
2951: compare_mode = target_mode;
2952: }
2953: else
2954: op0 = subtarget;
2955:
1.1.1.4 root 2956: /* If we want to keep subexpressions around, don't reuse our
2957: last target. */
2958:
2959: if (preserve_subexpressions_p ())
2960: subtarget = 0;
2961:
1.1 root 2962: /* Now normalize to the proper value in COMPARE_MODE. Sometimes
2963: we don't have to do anything. */
2964: if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
2965: ;
2966: else if (normalizep == - STORE_FLAG_VALUE)
2967: op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
2968:
2969: /* We don't want to use STORE_FLAG_VALUE < 0 below since this
2970: makes it hard to use a value of just the sign bit due to
2971: ANSI integer constant typing rules. */
1.1.1.4 root 2972: else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
1.1 root 2973: && (STORE_FLAG_VALUE
1.1.1.4 root 2974: & ((HOST_WIDE_INT) 1
2975: << (GET_MODE_BITSIZE (compare_mode) - 1))))
1.1 root 2976: op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
2977: size_int (GET_MODE_BITSIZE (compare_mode) - 1),
2978: subtarget, normalizep == 1);
2979: else if (STORE_FLAG_VALUE & 1)
2980: {
2981: op0 = expand_and (op0, const1_rtx, subtarget);
2982: if (normalizep == -1)
2983: op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
2984: }
2985: else
2986: abort ();
2987:
2988: /* If we were converting to a smaller mode, do the
2989: conversion now. */
2990: if (target_mode != compare_mode)
2991: {
1.1.1.5 ! root 2992: convert_move (target, op0, 0);
1.1 root 2993: return target;
2994: }
2995: else
2996: return op0;
2997: }
2998: }
2999:
3000: if (last)
3001: delete_insns_since (last);
3002:
3003: subtarget = target_mode == mode ? target : 0;
3004:
3005: /* If we reached here, we can't do this with a scc insn. However, there
3006: are some comparisons that can be done directly. For example, if
3007: this is an equality comparison of integers, we can try to exclusive-or
3008: (or subtract) the two operands and use a recursive call to try the
3009: comparison with zero. Don't do any of these cases if branches are
3010: very cheap. */
3011:
1.1.1.5 ! root 3012: if (BRANCH_COST > 0
1.1 root 3013: && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
3014: && op1 != const0_rtx)
3015: {
3016: tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
3017: OPTAB_WIDEN);
3018:
3019: if (tem == 0)
3020: tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
3021: OPTAB_WIDEN);
3022: if (tem != 0)
3023: tem = emit_store_flag (target, code, tem, const0_rtx,
3024: mode, unsignedp, normalizep);
3025: if (tem == 0)
3026: delete_insns_since (last);
3027: return tem;
3028: }
3029:
3030: /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
3031: the constant zero. Reject all other comparisons at this point. Only
3032: do LE and GT if branches are expensive since they are expensive on
3033: 2-operand machines. */
3034:
3035: if (BRANCH_COST == 0
3036: || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
3037: || (code != EQ && code != NE
3038: && (BRANCH_COST <= 1 || (code != LE && code != GT))))
3039: return 0;
3040:
3041: /* See what we need to return. We can only return a 1, -1, or the
3042: sign bit. */
3043:
3044: if (normalizep == 0)
3045: {
3046: if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
3047: normalizep = STORE_FLAG_VALUE;
3048:
1.1.1.4 root 3049: else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3050: && (STORE_FLAG_VALUE
3051: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
1.1 root 3052: ;
3053: else
3054: return 0;
3055: }
3056:
3057: /* Try to put the result of the comparison in the sign bit. Assume we can't
3058: do the necessary operation below. */
3059:
3060: tem = 0;
3061:
3062: /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
3063: the sign bit set. */
3064:
3065: if (code == LE)
3066: {
3067: /* This is destructive, so SUBTARGET can't be OP0. */
3068: if (rtx_equal_p (subtarget, op0))
3069: subtarget = 0;
3070:
3071: tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
3072: OPTAB_WIDEN);
3073: if (tem)
3074: tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
3075: OPTAB_WIDEN);
3076: }
3077:
3078: /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
3079: number of bits in the mode of OP0, minus one. */
3080:
3081: if (code == GT)
3082: {
3083: if (rtx_equal_p (subtarget, op0))
3084: subtarget = 0;
3085:
3086: tem = expand_shift (RSHIFT_EXPR, mode, op0,
3087: size_int (GET_MODE_BITSIZE (mode) - 1),
3088: subtarget, 0);
3089: tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
3090: OPTAB_WIDEN);
3091: }
3092:
3093: if (code == EQ || code == NE)
3094: {
3095: /* For EQ or NE, one way to do the comparison is to apply an operation
3096: that converts the operand into a positive number if it is non-zero
3097: or zero if it was originally zero. Then, for EQ, we subtract 1 and
3098: for NE we negate. This puts the result in the sign bit. Then we
3099: normalize with a shift, if needed.
3100:
3101: Two operations that can do the above actions are ABS and FFS, so try
3102: them. If that doesn't work, and MODE is smaller than a full word,
1.1.1.2 root 3103: we can use zero-extension to the wider mode (an unsigned conversion)
1.1 root 3104: as the operation. */
3105:
3106: if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3107: tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
3108: else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3109: tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
3110: else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3111: {
3112: mode = word_mode;
1.1.1.4 root 3113: op0 = protect_from_queue (op0, 0);
1.1 root 3114: tem = convert_to_mode (mode, op0, 1);
3115: }
3116:
3117: if (tem != 0)
3118: {
3119: if (code == EQ)
3120: tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
3121: 0, OPTAB_WIDEN);
3122: else
3123: tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
3124: }
3125:
3126: /* If we couldn't do it that way, for NE we can "or" the two's complement
3127: of the value with itself. For EQ, we take the one's complement of
3128: that "or", which is an extra insn, so we only handle EQ if branches
3129: are expensive. */
3130:
3131: if (tem == 0 && (code == NE || BRANCH_COST > 1))
3132: {
1.1.1.2 root 3133: if (rtx_equal_p (subtarget, op0))
3134: subtarget = 0;
3135:
1.1 root 3136: tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
3137: tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
3138: OPTAB_WIDEN);
3139:
3140: if (tem && code == EQ)
3141: tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
3142: }
3143: }
3144:
3145: if (tem && normalizep)
3146: tem = expand_shift (RSHIFT_EXPR, mode, tem,
3147: size_int (GET_MODE_BITSIZE (mode) - 1),
3148: tem, normalizep == 1);
3149:
3150: if (tem && GET_MODE (tem) != target_mode)
3151: {
3152: convert_move (target, tem, 0);
3153: tem = target;
3154: }
3155:
3156: if (tem == 0)
3157: delete_insns_since (last);
3158:
3159: return tem;
3160: }
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