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1.1.1.3 ! root 1: This is Info file gcc.info, produced by Makeinfo-1.47 from the input 1.1 root 2: file gcc.texi. 3: 4: This file documents the use and the internals of the GNU compiler. 5: 6: Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc. 7: 1.1.1.3 ! root 8: Permission is granted to make and distribute verbatim copies of this ! 9: manual provided the copyright notice and this permission notice are ! 10: preserved on all copies. 1.1 root 11: 12: Permission is granted to copy and distribute modified versions of 13: this manual under the conditions for verbatim copying, provided also 1.1.1.3 ! root 14: that the sections entitled "GNU General Public License" and "Boycott" ! 15: are included exactly as in the original, and provided that the entire ! 16: resulting derived work is distributed under the terms of a permission ! 17: notice identical to this one. 1.1 root 18: 19: Permission is granted to copy and distribute translations of this 20: manual into another language, under the above conditions for modified 1.1.1.3 ! root 21: versions, except that the sections entitled "GNU General Public ! 22: License" and "Boycott", and this permission notice, may be included in ! 23: translations approved by the Free Software Foundation instead of in the ! 24: original English. ! 25: ! 26: ! 27: File: gcc.info, Node: Standard Names, Next: Pattern Ordering, Prev: Constraints, Up: Machine Desc ! 28: ! 29: Standard Names for Patterns Used in Generation ! 30: ============================================== ! 31: ! 32: Here is a table of the instruction names that are meaningful in the ! 33: RTL generation pass of the compiler. Giving one of these names to an ! 34: instruction pattern tells the RTL generation pass that it can use the ! 35: pattern in to accomplish a certain task. ! 36: ! 37: `movM' ! 38: Here M stands for a two-letter machine mode name, in lower case. ! 39: This instruction pattern moves data with that machine mode from ! 40: operand 1 to operand 0. For example, `movsi' moves full-word data. ! 41: ! 42: If operand 0 is a `subreg' with mode M of a register whose own ! 43: mode is wider than M, the effect of this instruction is to store ! 44: the specified value in the part of the register that corresponds ! 45: to mode M. The effect on the rest of the register is undefined. ! 46: ! 47: This class of patterns is special in several ways. First of all, ! 48: each of these names *must* be defined, because there is no other ! 49: way to copy a datum from one place to another. ! 50: ! 51: Second, these patterns are not used solely in the RTL generation ! 52: pass. Even the reload pass can generate move insns to copy values ! 53: from stack slots into temporary registers. When it does so, one ! 54: of the operands is a hard register and the other is an operand ! 55: that can need to be reloaded into a register. ! 56: ! 57: Therefore, when given such a pair of operands, the pattern must ! 58: generate RTL which needs no reloading and needs no temporary ! 59: registers--no registers other than the operands. For example, if ! 60: you support the pattern with a `define_expand', then in such a ! 61: case the `define_expand' mustn't call `force_reg' or any other such ! 62: function which might generate new pseudo registers. ! 63: ! 64: This requirement exists even for subword modes on a RISC machine ! 65: where fetching those modes from memory normally requires several ! 66: insns and some temporary registers. Look in `spur.md' to see how ! 67: the requirement can be satisfied. ! 68: ! 69: During reload a memory reference with an invalid address may be ! 70: passed as an operand. Such an address will be replaced with a ! 71: valid address later in the reload pass. In this case, nothing may ! 72: be done with the address except to use it as it stands. If it is ! 73: copied, it will not be replaced with a valid address. No attempt ! 74: should be made to make such an address into a valid address and no ! 75: routine (such as `change_address') that will do so may be called. ! 76: Note that `general_operand' will fail when applied to such an ! 77: address. ! 78: ! 79: The global variable `reload_in_progress' (which must be explicitly ! 80: declared if required) can be used to determine whether such special ! 81: handling is required. ! 82: ! 83: The variety of operands that have reloads depends on the rest of ! 84: the machine description, but typically on a RISC machine these can ! 85: only be pseudo registers that did not get hard registers, while on ! 86: other machines explicit memory references will get optional ! 87: reloads. ! 88: ! 89: If a scratch register is required to move an object to or from ! 90: memory, it can be allocated using `gen_reg_rtx' prior to reload. ! 91: But this is impossible during and after reload. If there are ! 92: cases needing scratch registers after reload, you must define ! 93: `SECONDARY_INPUT_RELOAD_CLASS' and/or ! 94: `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide ! 95: patterns `reload_inM' or `reload_outM' to handle them. *Note ! 96: Register Classes::. ! 97: ! 98: The constraints on a `moveM' must permit moving any hard register ! 99: to any other hard register provided that `HARD_REGNO_MODE_OK' ! 100: permits mode M in both registers and `REGISTER_MOVE_COST' applied ! 101: to their classes returns a value of 2. ! 102: ! 103: It is obligatory to support floating point `moveM' instructions ! 104: into and out of any registers that can hold fixed point values, ! 105: because unions and structures (which have modes `SImode' or ! 106: `DImode') can be in those registers and they may have floating ! 107: point members. ! 108: ! 109: There may also be a need to support fixed point `moveM' ! 110: instructions in and out of floating point registers. ! 111: Unfortunately, I have forgotten why this was so, and I don't know ! 112: whether it is still true. If `HARD_REGNO_MODE_OK' rejects fixed ! 113: point values in floating point registers, then the constraints of ! 114: the fixed point `moveM' instructions must be designed to avoid ! 115: ever trying to reload into a floating point register. ! 116: ! 117: `reload_inM' ! 118: `reload_outM' ! 119: Like `movM', but used when a scratch register is required to move ! 120: between operand 0 and operand 1. Operand 2 describes the scratch ! 121: register. See the discussion of the `SECONDARY_RELOAD_CLASS' ! 122: macro in *note Register Classes::.. ! 123: ! 124: `movstrictM' ! 125: Like `movM' except that if operand 0 is a `subreg' with mode M of ! 126: a register whose natural mode is wider, the `movstrictM' ! 127: instruction is guaranteed not to alter any of the register except ! 128: the part which belongs to mode M. ! 129: ! 130: `load_multiple' ! 131: Load several consecutive memory locations into consecutive ! 132: registers. Operand 0 is the first of the consecutive registers, ! 133: operand 1 is the first memory location, and operand 2 is a ! 134: constant: the number of consecutive registers. ! 135: ! 136: Define this only if the target machine really has such an ! 137: instruction; do not define this if the most efficient way of ! 138: loading consecutive registers from memory is to do them one at a ! 139: time. ! 140: ! 141: On some machines, there are restrictions as to which consecutive ! 142: registers can be stored into memory, such as particular starting or ! 143: ending register numbers or only a range of valid counts. For those ! 144: machines, use a `define_expand' (*note Expander Definitions::.) ! 145: and make the pattern fail if the restrictions are not met. ! 146: ! 147: Write the generated insn as a `parallel' with elements being a ! 148: `set' of one register from the appropriate memory location (you may ! 149: also need `use' or `clobber' elements). Use a `match_parallel' ! 150: (*note RTL Template::.) to recognize the insn. See `a29k.md' and ! 151: `rs6000.md' for examples of the use of this insn pattern. ! 152: ! 153: `store_multiple' ! 154: Similar to `load_multiple', but store several consecutive registers ! 155: into consecutive memory locations. Operand 0 is the first of the ! 156: consecutive memory locations, operand 1 is the first register, and ! 157: operand 2 is a constant: the number of consecutive registers. ! 158: ! 159: `addM3' ! 160: Add operand 2 and operand 1, storing the result in operand 0. All ! 161: operands must have mode M. This can be used even on two-address ! 162: machines, by means of constraints requiring operands 1 and 0 to be ! 163: the same location. ! 164: ! 165: `subM3', `mulM3' ! 166: `divM3', `udivM3', `modM3', `umodM3' ! 167: `sminM3', `smaxM3', `uminM3', `umaxM3' ! 168: `andM3', `iorM3', `xorM3' ! 169: Similar, for other arithmetic operations. ! 170: ! 171: `mulhisi3' ! 172: Multiply operands 1 and 2, which have mode `HImode', and store a ! 173: `SImode' product in operand 0. ! 174: ! 175: `mulqihi3', `mulsidi3' ! 176: Similar widening-multiplication instructions of other widths. ! 177: ! 178: `umulqihi3', `umulhisi3', `umulsidi3' ! 179: Similar widening-multiplication instructions that do unsigned ! 180: multiplication. ! 181: ! 182: `divmodM4' ! 183: Signed division that produces both a quotient and a remainder. ! 184: Operand 1 is divided by operand 2 to produce a quotient stored in ! 185: operand 0 and a remainder stored in operand 3. ! 186: ! 187: For machines with an instruction that produces both a quotient and ! 188: a remainder, provide a pattern for `divmodM4' but do not provide ! 189: patterns for `divM3' and `modM3'. This allows optimization in the ! 190: relatively common case when both the quotient and remainder are ! 191: computed. ! 192: ! 193: If an instruction that just produces a quotient or just a remainder ! 194: exists and is more efficient than the instruction that produces ! 195: both, write the output routine of `divmodM4' to call ! 196: `find_reg_note' and look for a `REG_UNUSED' note on the quotient ! 197: or remainder and generate the appropriate instruction. ! 198: ! 199: `udivmodM4' ! 200: Similar, but does unsigned division. ! 201: ! 202: `ashlM3' ! 203: Arithmetic-shift operand 1 left by a number of bits specified by ! 204: operand 2, and store the result in operand 0. Here M is the mode ! 205: of operand 0 and operand 1; operand 2's mode is specified by the ! 206: instruction pattern, and the compiler will convert the operand to ! 207: that mode before generating the instruction. ! 208: ! 209: `ashrM3', `lshlM3', `lshrM3', `rotlM3', `rotrM3' ! 210: Other shift and rotate instructions, analogous to the `ashlM3' ! 211: instructions. ! 212: ! 213: Logical and arithmetic left shift are the same. Machines that do ! 214: not allow negative shift counts often have only one instruction for ! 215: shifting left. On such machines, you should define a pattern named ! 216: `ashlM3' and leave `lshlM3' undefined. ! 217: ! 218: `negM2' ! 219: Negate operand 1 and store the result in operand 0. ! 220: ! 221: `absM2' ! 222: Store the absolute value of operand 1 into operand 0. ! 223: ! 224: `sqrtM2' ! 225: Store the square root of operand 1 into operand 0. ! 226: ! 227: The `sqrt' built-in function of C always uses the mode which ! 228: corresponds to the C data type `double'. ! 229: ! 230: `ffsM2' ! 231: Store into operand 0 one plus the index of the least significant ! 232: 1-bit of operand 1. If operand 1 is zero, store zero. M is the ! 233: mode of operand 0; operand 1's mode is specified by the instruction ! 234: pattern, and the compiler will convert the operand to that mode ! 235: before generating the instruction. ! 236: ! 237: The `ffs' built-in function of C always uses the mode which ! 238: corresponds to the C data type `int'. ! 239: ! 240: `one_cmplM2' ! 241: Store the bitwise-complement of operand 1 into operand 0. ! 242: ! 243: `cmpM' ! 244: Compare operand 0 and operand 1, and set the condition codes. The ! 245: RTL pattern should look like this: ! 246: ! 247: (set (cc0) (compare (match_operand:M 0 ...) ! 248: (match_operand:M 1 ...))) ! 249: ! 250: `tstM' ! 251: Compare operand 0 against zero, and set the condition codes. The ! 252: RTL pattern should look like this: ! 253: ! 254: (set (cc0) (match_operand:M 0 ...)) ! 255: ! 256: `tstM' patterns should not be defined for machines that do not use ! 257: `(cc0)'. Doing so would confuse the optimizer since it would no ! 258: longer be clear which `set' operations were comparisons. The ! 259: `cmpM' patterns should be used instead. ! 260: ! 261: `movstrM' ! 262: Block move instruction. The addresses of the destination and ! 263: source strings are the first two operands, and both are in mode ! 264: `Pmode'. The number of bytes to move is the third operand, in mode ! 265: M. ! 266: ! 267: The fourth operand is the known shared alignment of the source and ! 268: destination, in the form of a `const_int' rtx. Thus, if the ! 269: compiler knows that both source and destination are word-aligned, ! 270: it may provide the value 4 for this operand. ! 271: ! 272: These patterns need not give special consideration to the ! 273: possibility that the source and destination strings might overlap. ! 274: ! 275: `cmpstrM' ! 276: Block compare instruction, with five operands. Operand 0 is the ! 277: output; it has mode M. The remaining four operands are like the ! 278: operands of `movstrM'. The two memory blocks specified are ! 279: compared byte by byte in lexicographic order. The effect of the ! 280: instruction is to store a value in operand 0 whose sign indicates ! 281: the result of the comparison. ! 282: ! 283: `floatMN2' ! 284: Convert signed integer operand 1 (valid for fixed point mode M) to ! 285: floating point mode N and store in operand 0 (which has mode N). ! 286: ! 287: `floatunsMN2' ! 288: Convert unsigned integer operand 1 (valid for fixed point mode M) ! 289: to floating point mode N and store in operand 0 (which has mode N). ! 290: ! 291: `fixMN2' ! 292: Convert operand 1 (valid for floating point mode M) to fixed point ! 293: mode N as a signed number and store in operand 0 (which has mode ! 294: N). This instruction's result is defined only when the value of ! 295: operand 1 is an integer. ! 296: ! 297: `fixunsMN2' ! 298: Convert operand 1 (valid for floating point mode M) to fixed point ! 299: mode N as an unsigned number and store in operand 0 (which has ! 300: mode N). This instruction's result is defined only when the value ! 301: of operand 1 is an integer. ! 302: ! 303: `ftruncM2' ! 304: Convert operand 1 (valid for floating point mode M) to an integer ! 305: value, still represented in floating point mode M, and store it in ! 306: operand 0 (valid for floating point mode M). ! 307: ! 308: `fix_truncMN2' ! 309: Like `fixMN2' but works for any floating point value of mode M by ! 310: converting the value to an integer. ! 311: ! 312: `fixuns_truncMN2' ! 313: Like `fixunsMN2' but works for any floating point value of mode M ! 314: by converting the value to an integer. ! 315: ! 316: `truncMN' ! 317: Truncate operand 1 (valid for mode M) to mode N and store in ! 318: operand 0 (which has mode N). Both modes must be fixed point or ! 319: both floating point. ! 320: ! 321: `extendMN' ! 322: Sign-extend operand 1 (valid for mode M) to mode N and store in ! 323: operand 0 (which has mode N). Both modes must be fixed point or ! 324: both floating point. ! 325: ! 326: `zero_extendMN' ! 327: Zero-extend operand 1 (valid for mode M) to mode N and store in ! 328: operand 0 (which has mode N). Both modes must be fixed point. ! 329: ! 330: `extv' ! 331: Extract a bit field from operand 1 (a register or memory operand), ! 332: where operand 2 specifies the width in bits and operand 3 the ! 333: starting bit, and store it in operand 0. Operand 0 must have mode ! 334: `word_mode'. Operand 1 may have mode `byte_mode' or `word_mode'; ! 335: often `word_mode' is allowed only for registers. Operands 2 and 3 ! 336: must be valid for `word_mode'. ! 337: ! 338: The RTL generation pass generates this instruction only with ! 339: constants for operands 2 and 3. ! 340: ! 341: The bit-field value is sign-extended to a full word integer before ! 342: it is stored in operand 0. ! 343: ! 344: `extzv' ! 345: Like `extv' except that the bit-field value is zero-extended. ! 346: ! 347: `insv' ! 348: Store operand 3 (which must be valid for `word_mode') into a bit ! 349: field in operand 0, where operand 1 specifies the width in bits and ! 350: operand 2 the starting bit. Operand 0 may have mode `byte_mode' or ! 351: `word_mode'; often `word_mode' is allowed only for registers. ! 352: Operands 1 and 2 must be valid for `word_mode'. ! 353: ! 354: The RTL generation pass generates this instruction only with ! 355: constants for operands 1 and 2. ! 356: ! 357: `sCOND' ! 358: Store zero or nonzero in the operand according to the condition ! 359: codes. Value stored is nonzero iff the condition COND is true. ! 360: COND is the name of a comparison operation expression code, such ! 361: as `eq', `lt' or `leu'. ! 362: ! 363: You specify the mode that the operand must have when you write the ! 364: `match_operand' expression. The compiler automatically sees which ! 365: mode you have used and supplies an operand of that mode. ! 366: ! 367: The value stored for a true condition must have 1 as its low bit, ! 368: or else must be negative. Otherwise the instruction is not ! 369: suitable and you should omit it from the machine description. You ! 370: describe to the compiler exactly which value is stored by defining ! 371: the macro `STORE_FLAG_VALUE' (*note Misc::.). If a description ! 372: cannot be found that can be used for all the `sCOND' patterns, you ! 373: should omit those operations from the machine description. ! 374: ! 375: These operations may fail, but should do so only in relatively ! 376: uncommon cases; if they would fail for common cases involving ! 377: integer comparisons, it is best to omit these patterns. ! 378: ! 379: If these operations are omitted, the compiler will usually ! 380: generate code that copies the constant one to the target and ! 381: branches around an assignment of zero to the target. If this code ! 382: is more efficient than the potential instructions used for the ! 383: `sCOND' pattern followed by those required to convert the result ! 384: into a 1 or a zero in `SImode', you should omit the `sCOND' ! 385: operations from the machine description. ! 386: ! 387: `bCOND' ! 388: Conditional branch instruction. Operand 0 is a `label_ref' that ! 389: refers to the label to jump to. Jump if the condition codes meet ! 390: condition COND. ! 391: ! 392: Some machines do not follow the model assumed here where a ! 393: comparison instruction is followed by a conditional branch ! 394: instruction. In that case, the `cmpM' (and `tstM') patterns should ! 395: simply store the operands away and generate all the required insns ! 396: in a `define_expand' (*note Expander Definitions::.) for the ! 397: conditional branch operations. All calls to expand `vCOND' ! 398: patterns are immediately preceded by calls to expand either a ! 399: `cmpM' pattern or a `tstM' pattern. ! 400: ! 401: Machines that use a pseudo register for the condition code value, ! 402: or where the mode used for the comparison depends on the condition ! 403: being tested, should also use the above mechanism. *Note Jump ! 404: Patterns:: ! 405: ! 406: The above discussion also applies to `sCOND' patterns. ! 407: ! 408: `call' ! 409: Subroutine call instruction returning no value. Operand 0 is the ! 410: function to call; operand 1 is the number of bytes of arguments ! 411: pushed (in mode `SImode', except it is normally a `const_int'); ! 412: operand 2 is the number of registers used as operands. ! 413: ! 414: On most machines, operand 2 is not actually stored into the RTL ! 415: pattern. It is supplied for the sake of some RISC machines which ! 416: need to put this information into the assembler code; they can put ! 417: it in the RTL instead of operand 1. ! 418: ! 419: Operand 0 should be a `mem' RTX whose address is the address of the ! 420: function. Note, however, that this address can be a `symbol_ref' ! 421: expression even if it would not be a legitimate memory address on ! 422: the target machine. If it is also not a valid argument for a call ! 423: instruction, the pattern for this operation should be a ! 424: `define_expand' (*note Expander Definitions::.) that places the ! 425: address into a register and uses that register in the call ! 426: instruction. ! 427: ! 428: `call_value' ! 429: Subroutine call instruction returning a value. Operand 0 is the ! 430: hard register in which the value is returned. There are three more ! 431: operands, the same as the three operands of the `call' instruction ! 432: (but with numbers increased by one). ! 433: ! 434: Subroutines that return `BLKmode' objects use the `call' insn. ! 435: ! 436: `call_pop', `call_value_pop' ! 437: Similar to `call' and `call_value', except used if defined and if ! 438: `RETURN_POPS_ARGS' is non-zero. They should emit a `parallel' ! 439: that contains both the function call and a `set' to indicate the ! 440: adjustment made to the frame pointer. ! 441: ! 442: For machines where `RETURN_POPS_ARGS' can be non-zero, the use of ! 443: these patterns increases the number of functions for which the ! 444: frame pointer can be eliminated, if desired. ! 445: ! 446: `return' ! 447: Subroutine return instruction. This instruction pattern name ! 448: should be defined only if a single instruction can do all the work ! 449: of returning from a function. ! 450: ! 451: Like the `movM' patterns, this pattern is also used after the RTL ! 452: generation phase. In this case it is to support machines where ! 453: multiple instructions are usually needed to return from a ! 454: function, but some class of functions only requires one ! 455: instruction to implement a return. Normally, the applicable ! 456: functions are those which do not need to save any registers or ! 457: allocate stack space. ! 458: ! 459: For such machines, the condition specified in this pattern should ! 460: only be true when `reload_completed' is non-zero and the function's ! 461: epilogue would only be a single instruction. For machines with ! 462: register windows, the routine `leaf_function_p' may be used to ! 463: determine if a register window push is required. ! 464: ! 465: Machines that have conditional return instructions should define ! 466: patterns such as ! 467: ! 468: (define_insn "" ! 469: [(set (pc) ! 470: (if_then_else (match_operator 0 "comparison_operator" ! 471: [(cc0) (const_int 0)]) ! 472: (return) ! 473: (pc)))] ! 474: "CONDITION" ! 475: "...") ! 476: ! 477: where CONDITION would normally be the same condition specified on ! 478: the named `return' pattern. ! 479: ! 480: `nop' ! 481: No-op instruction. This instruction pattern name should always be ! 482: defined to output a no-op in assembler code. `(const_int 0)' will ! 483: do as an RTL pattern. ! 484: ! 485: `indirect_jump' ! 486: An instruction to jump to an address which is operand zero. This ! 487: pattern name is mandatory on all machines. ! 488: ! 489: `casesi' ! 490: Instruction to jump through a dispatch table, including bounds ! 491: checking. This instruction takes five operands: ! 492: ! 493: 1. The index to dispatch on, which has mode `SImode'. ! 494: ! 495: 2. The lower bound for indices in the table, an integer constant. ! 496: ! 497: 3. The total range of indices in the table--the largest index ! 498: minus the smallest one (both inclusive). ! 499: ! 500: 4. A label that precedes the table itself. ! 501: ! 502: 5. A label to jump to if the index has a value outside the ! 503: bounds. (If the machine-description macro ! 504: `CASE_DROPS_THROUGH' is defined, then an out-of-bounds index ! 505: drops through to the code following the jump table instead of ! 506: jumping to this label. In that case, this label is not ! 507: actually used by the `casesi' instruction, but it is always ! 508: provided as an operand.) ! 509: ! 510: The table is a `addr_vec' or `addr_diff_vec' inside of a ! 511: `jump_insn'. The number of elements in the table is one plus the ! 512: difference between the upper bound and the lower bound. ! 513: ! 514: `tablejump' ! 515: Instruction to jump to a variable address. This is a low-level ! 516: capability which can be used to implement a dispatch table when ! 517: there is no `casesi' pattern. ! 518: ! 519: This pattern requires two operands: the address or offset, and a ! 520: label which should immediately precede the jump table. If the ! 521: macro `CASE_VECTOR_PC_RELATIVE' is defined then the first operand ! 522: is an offset which counts from the address of the table; ! 523: otherwise, it is an absolute address to jump to. In either case, ! 524: the first operand has mode `Pmode'. ! 525: ! 526: The `tablejump' insn is always the last insn before the jump table ! 527: it uses. Its assembler code normally has no need to use the ! 528: second operand, but you should incorporate it in the RTL pattern so ! 529: that the jump optimizer will not delete the table as unreachable ! 530: code. ! 531: ! 532: `save_stack_block' ! 533: `save_stack_function' ! 534: `save_stack_nonlocal' ! 535: `restore_stack_block' ! 536: `restore_stack_function' ! 537: `restore_stack_nonlocal' ! 538: Most machines save and restore the stack pointer by copying it to ! 539: or from an object of mode `Pmode'. Do not define these patterns on ! 540: such machines. ! 541: ! 542: Some machines require special handling for stack pointer saves and ! 543: restores. On those machines, define the patterns corresponding to ! 544: the non-standard cases by using a `define_expand' (*note Expander ! 545: Definitions::.) that produces the required insns. The three types ! 546: of saves and restores are: ! 547: ! 548: 1. `save_stack_block' saves the stack pointer at the start of a ! 549: block that allocates a variable-sized object and ! 550: `restore_stack_block' restores the stack pointer when the ! 551: block is exited. ! 552: ! 553: 2. `save_stack_function' and `restore_stack_function' operate ! 554: similarly for the outermost block of a function and are used ! 555: when the function allocates variable-sized objects or calls ! 556: `alloca'. Only the epilogue uses the restored stack pointer, ! 557: allowing a simpler save or restore sequence on some machines. ! 558: ! 559: 3. `save_stack_nonlocal' is used in functions that contain labels ! 560: branched to by nested functions. It saves the stack pointer ! 561: in such a way that the inner function can use ! 562: `restore_stack_nonlocal' to restore the stack pointer. The ! 563: compiler generates code to restore the frame and argument ! 564: pointer registers, but some machines require saving and ! 565: restoring additional data such as register window information ! 566: or stack backchains. Place insns in these patterns to save ! 567: and restore any such required data. ! 568: ! 569: When saving the stack pointer, operand 0 is the save area and ! 570: operand 1 is the stack pointer. The mode used to allocate the ! 571: save area is the mode of operand 0. You must specify an integral ! 572: mode, or `VOIDmode' if no save area is needed for a particular ! 573: type of save (either because no save is needed or because a ! 574: machine-specific save area can be used). Operand 0 is the stack ! 575: pointer and operand 1 is the save area for restore operations. If ! 576: `save_stack_block' is defined, operand 0 must not be `VOIDmode' ! 577: since these saves can be arbitrarily nested. ! 578: ! 579: A save area is a `mem' that is at a constant offset from ! 580: `virtual_stack_vars_rtx' when the stack pointer is saved for use by ! 581: nonlocal gotos and a `reg' in the other two cases. ! 582: ! 583: `allocate_stack' ! 584: Subtract operand 0 from the stack pointer to create space for for ! 585: dynamically allocated data. ! 586: ! 587: Do not define this pattern if all that must be done is the ! 588: subtraction. On some machines require other operations such as ! 589: stack probes or maintaining the back chain. Define this pattern ! 590: to emit those operations in addition to updating the stack pointer. ! 591: ! 592: ! 593: File: gcc.info, Node: Pattern Ordering, Next: Dependent Patterns, Prev: Standard Names, Up: Machine Desc ! 594: ! 595: When the Order of Patterns Matters ! 596: ================================== ! 597: ! 598: Sometimes an insn can match more than one instruction pattern. Then ! 599: the pattern that appears first in the machine description is the one ! 600: used. Therefore, more specific patterns (patterns that will match fewer ! 601: things) and faster instructions (those that will produce better code ! 602: when they do match) should usually go first in the description. ! 603: ! 604: In some cases the effect of ordering the patterns can be used to hide ! 605: a pattern when it is not valid. For example, the 68000 has an ! 606: instruction for converting a fullword to floating point and another for ! 607: converting a byte to floating point. An instruction converting an ! 608: integer to floating point could match either one. We put the pattern ! 609: to convert the fullword first to make sure that one will be used rather ! 610: than the other. (Otherwise a large integer might be generated as a ! 611: single-byte immediate quantity, which would not work.) Instead of using ! 612: this pattern ordering it would be possible to make the pattern for ! 613: convert-a-byte smart enough to deal properly with any constant value. ! 614: ! 615: ! 616: File: gcc.info, Node: Dependent Patterns, Next: Jump Patterns, Prev: Pattern Ordering, Up: Machine Desc ! 617: ! 618: Interdependence of Patterns ! 619: =========================== ! 620: ! 621: Every machine description must have a named pattern for each of the ! 622: conditional branch names `bCOND'. The recognition template must always ! 623: have the form ! 624: ! 625: (set (pc) ! 626: (if_then_else (COND (cc0) (const_int 0)) ! 627: (label_ref (match_operand 0 "" "")) ! 628: (pc))) ! 629: ! 630: In addition, every machine description must have an anonymous pattern ! 631: for each of the possible reverse-conditional branches. Their templates ! 632: look like ! 633: ! 634: (set (pc) ! 635: (if_then_else (COND (cc0) (const_int 0)) ! 636: (pc) ! 637: (label_ref (match_operand 0 "" "")))) ! 638: ! 639: They are necessary because jump optimization can turn direct-conditional ! 640: branches into reverse-conditional branches. ! 641: ! 642: It is often convenient to use the `match_operator' construct to ! 643: reduce the number of patterns that must be specified for branches. For ! 644: example, ! 645: ! 646: (define_insn "" ! 647: [(set (pc) ! 648: (if_then_else (match_operator 0 "comparison_operator" ! 649: [(cc0) (const_int 0)]) ! 650: (pc) ! 651: (label_ref (match_operand 1 "" ""))))] ! 652: "CONDITION" ! 653: "...") ! 654: ! 655: In some cases machines support instructions identical except for the ! 656: machine mode of one or more operands. For example, there may be ! 657: "sign-extend halfword" and "sign-extend byte" instructions whose ! 658: patterns are ! 659: ! 660: (set (match_operand:SI 0 ...) ! 661: (extend:SI (match_operand:HI 1 ...))) ! 662: ! 663: (set (match_operand:SI 0 ...) ! 664: (extend:SI (match_operand:QI 1 ...))) ! 665: ! 666: Constant integers do not specify a machine mode, so an instruction to ! 667: extend a constant value could match either pattern. The pattern it ! 668: actually will match is the one that appears first in the file. For ! 669: correct results, this must be the one for the widest possible mode ! 670: (`HImode', here). If the pattern matches the `QImode' instruction, the ! 671: results will be incorrect if the constant value does not actually fit ! 672: that mode. ! 673: ! 674: Such instructions to extend constants are rarely generated because ! 675: they are optimized away, but they do occasionally happen in nonoptimized ! 676: compilations. ! 677: ! 678: If a constraint in a pattern allows a constant, the reload pass may ! 679: replace a register with a constant permitted by the constraint in some ! 680: cases. Similarly for memory references. You must ensure that the ! 681: predicate permits all objects allowed by the constraints to prevent the ! 682: compiler from crashing. ! 683: ! 684: Because of this substitution, you should not provide separate ! 685: patterns for increment and decrement instructions. Instead, they ! 686: should be generated from the same pattern that supports ! 687: register-register add insns by examining the operands and generating ! 688: the appropriate machine instruction. ! 689: ! 690: ! 691: File: gcc.info, Node: Jump Patterns, Next: Insn Canonicalizations, Prev: Dependent Patterns, Up: Machine Desc ! 692: ! 693: Defining Jump Instruction Patterns ! 694: ================================== ! 695: ! 696: For most machines, GNU CC assumes that the machine has a condition ! 697: code. A comparison insn sets the condition code, recording the results ! 698: of both signed and unsigned comparison of the given operands. A ! 699: separate branch insn tests the condition code and branches or not ! 700: according its value. The branch insns come in distinct signed and ! 701: unsigned flavors. Many common machines, such as the Vax, the 68000 and ! 702: the 32000, work this way. ! 703: ! 704: Some machines have distinct signed and unsigned compare ! 705: instructions, and only one set of conditional branch instructions. The ! 706: easiest way to handle these machines is to treat them just like the ! 707: others until the final stage where assembly code is written. At this ! 708: time, when outputting code for the compare instruction, peek ahead at ! 709: the following branch using `next_cc0_user (insn)'. (The variable ! 710: `insn' refers to the insn being output, in the output-writing code in ! 711: an instruction pattern.) If the RTL says that is an unsigned branch, ! 712: output an unsigned compare; otherwise output a signed compare. When ! 713: the branch itself is output, you can treat signed and unsigned branches ! 714: identically. ! 715: ! 716: The reason you can do this is that GNU CC always generates a pair of ! 717: consecutive RTL insns, possibly separated by `note' insns, one to set ! 718: the condition code and one to test it, and keeps the pair inviolate ! 719: until the end. ! 720: ! 721: To go with this technique, you must define the machine-description ! 722: macro `NOTICE_UPDATE_CC' to do `CC_STATUS_INIT'; in other words, no ! 723: compare instruction is superfluous. ! 724: ! 725: Some machines have compare-and-branch instructions and no condition ! 726: code. A similar technique works for them. When it is time to "output" a ! 727: compare instruction, record its operands in two static variables. When ! 728: outputting the branch-on-condition-code instruction that follows, ! 729: actually output a compare-and-branch instruction that uses the ! 730: remembered operands. ! 731: ! 732: It also works to define patterns for compare-and-branch instructions. ! 733: In optimizing compilation, the pair of compare and branch instructions ! 734: will be combined according to these patterns. But this does not happen ! 735: if optimization is not requested. So you must use one of the solutions ! 736: above in addition to any special patterns you define. ! 737: ! 738: In many RISC machines, most instructions do not affect the condition ! 739: code and there may not even be a separate condition code register. On ! 740: these machines, the restriction that the definition and use of the ! 741: condition code be adjacent insns is not necessary and can prevent ! 742: important optimizations. For example, on the IBM RS/6000, there is a ! 743: delay for taken branches unless the condition code register is set three ! 744: instructions earlier than the conditional branch. The instruction ! 745: scheduler cannot perform this optimization if it is not permitted to ! 746: separate the definition and use of the condition code register. ! 747: ! 748: On these machines, do not use `(cc0)', but instead use a register to ! 749: represent the condition code. If there is a specific condition code ! 750: register in the machine, use a hard register. If the condition code or ! 751: comparison result can be placed in any general register, or if there are ! 752: multiple condition registers, use a pseudo register. ! 753: ! 754: On some machines, the type of branch instruction generated may ! 755: depend on the way the condition code was produced; for example, on the ! 756: 68k and Sparc, setting the condition code directly from an add or ! 757: subtract instruction does not clear the overflow bit the way that a test ! 758: instruction does, so a different branch instruction must be used for ! 759: some conditional branches. For machines that use `(cc0)', the set and ! 760: use of the condition code must be adjacent (separated only by `note' ! 761: insns) allowing flags in `cc_status' to be used. (*Note Condition ! 762: Code::.) Also, the comparison and branch insns can be located from ! 763: each other by using the functions `prev_cc0_setter' and `next_cc0_user'. ! 764: ! 765: However, this is not true on machines that do not use `(cc0)'. On ! 766: those machines, no assumptions can be made about the adjacency of the ! 767: compare and branch insns and the above methods cannot be used. Instead, ! 768: we use the machine mode of the condition code register to record ! 769: different formats of the condition code register. ! 770: ! 771: Registers used to store the condition code value should have a mode ! 772: that is in class `MODE_CC'. Normally, it will be `CCmode'. If ! 773: additional modes are required (as for the add example mentioned above in ! 774: the Sparc), define the macro `EXTRA_CC_MODES' to list the additional ! 775: modes required (*note Condition Code::.). Also define `EXTRA_CC_NAMES' ! 776: to list the names of those modes and `SELECT_CC_MODE' to choose a mode ! 777: given an operand of a compare. ! 778: ! 779: If it is known during RTL generation that a different mode will be ! 780: required (for example, if the machine has separate compare instructions ! 781: for signed and unsigned quantities, like most IBM processors), they can ! 782: be specified at that time. ! 783: ! 784: If the cases that require different modes would be made by ! 785: instruction combination, the macro `SELECT_CC_MODE' determines which ! 786: machine mode should be used for the comparison result. The patterns ! 787: should be written using that mode. To support the case of the add on ! 788: the Sparc discussed above, we have the pattern ! 789: ! 790: (define_insn "" ! 791: [(set (reg:CC_NOOV 0) ! 792: (compare:CC_NOOV (plus:SI (match_operand:SI 0 "register_operand" "%r") ! 793: (match_operand:SI 1 "arith_operand" "rI")) ! 794: (const_int 0)))] ! 795: "" ! 796: "...") ! 797: ! 798: The `SELECT_CC_MODE' macro on the Sparc returns `CC_NOOVmode' for ! 799: comparisons whose argument is a `plus'. 1.1 root 800: 801: 1.1.1.2 root 802: File: gcc.info, Node: Insn Canonicalizations, Next: Peephole Definitions, Prev: Jump Patterns, Up: Machine Desc 803: 804: Canonicalization of Instructions 805: ================================ 806: 1.1.1.3 ! root 807: There are often cases where multiple RTL expressions could represent ! 808: an operation performed by a single machine instruction. This situation ! 809: is most commonly encountered with logical, branch, and ! 810: multiply-accumulate instructions. In such cases, the compiler attempts ! 811: to convert these multiple RTL expressions into a single canonical form ! 812: to reduce the number of insn patterns required. 1.1.1.2 root 813: 1.1.1.3 ! root 814: In addition to algebraic simplifications, following canonicalizations ! 815: are performed: 1.1.1.2 root 816: 817: * For commutative and comparison operators, a constant is always 1.1.1.3 ! root 818: made the second operand. If a machine only supports a constant as ! 819: the second operand, only patterns that match a constant in the 1.1.1.2 root 820: second operand need be supplied. 821: 822: For these operators, if only one operand is a `neg', `not', 823: `mult', `plus', or `minus' expression, it will be the first 824: operand. 825: 1.1.1.3 ! root 826: * For the `compare' operator, a constant is always the second operand ! 827: on machines where `cc0' is used (*note Jump Patterns::.). On other ! 828: machines, there are rare cases where the compiler might want to ! 829: construct a `compare' with a constant as the first operand. ! 830: However, these cases are not common enough for it to be worthwhile ! 831: to provide a pattern matching a constant as the first operand ! 832: unless the machine actually has such an instruction. 1.1.1.2 root 833: 1.1.1.3 ! root 834: An operand of `neg', `not', `mult', `plus', or `minus' is made the ! 835: first operand under the same conditions as above. 1.1.1.2 root 836: 837: * `(minus X (const_int N))' is converted to `(plus X (const_int 838: -N))'. 839: 840: * Within address computations (i.e., inside `mem'), a left shift is 841: converted into the appropriate multiplication by a power of two. 842: 843: De`Morgan's Law is used to move bitwise negation inside a bitwise 844: logical-and or logical-or operation. If this results in only one 845: operand being a `not' expression, it will be the first one. 846: 847: A machine that has an instruction that performs a bitwise 848: logical-and of one operand with the bitwise negation of the other 849: should specify the pattern for that instruction as 850: 851: (define_insn "" 852: [(set (match_operand:M 0 ...) 853: (and:M (not:M (match_operand:M 1 ...)) 854: (match_operand:M 2 ...)))] 855: "..." 856: "...") 857: 858: Similarly, a pattern for a "NAND" instruction should be written 859: 860: (define_insn "" 861: [(set (match_operand:M 0 ...) 862: (ior:M (not:M (match_operand:M 1 ...)) 863: (not:M (match_operand:M 2 ...))))] 864: "..." 865: "...") 866: 1.1.1.3 ! root 867: In both cases, it is not necessary to include patterns for the many ! 868: logically equivalent RTL expressions. 1.1.1.2 root 869: 870: * The only possible RTL expressions involving both bitwise 871: exclusive-or and bitwise negation are `(xor:M X) Y)' and `(not:M 872: (xor:M X Y))'. 873: 874: * The sum of three items, one of which is a constant, will only 875: appear in the form 876: 877: (plus:M (plus:M X Y) CONSTANT) 878: 879: * On machines that do not use `cc0', `(compare X (const_int 0))' 880: will be converted to X. 881: 882: * Equality comparisons of a group of bits (usually a single bit) 883: with zero will be written using `zero_extract' rather than the 884: equivalent `and' or `sign_extract' operations. 885: 886: 887: File: gcc.info, Node: Peephole Definitions, Next: Expander Definitions, Prev: Insn Canonicalizations, Up: Machine Desc 888: 889: Defining Machine-Specific Peephole Optimizers 890: ============================================= 891: 892: In addition to instruction patterns the `md' file may contain 893: definitions of machine-specific peephole optimizations. 894: 1.1.1.3 ! root 895: The combiner does not notice certain peephole optimizations when the ! 896: data flow in the program does not suggest that it should try them. For ! 897: example, sometimes two consecutive insns related in purpose can be ! 898: combined even though the second one does not appear to use a register ! 899: computed in the first one. A machine-specific peephole optimizer can ! 900: detect such opportunities. 1.1.1.2 root 901: 902: A definition looks like this: 903: 904: (define_peephole 905: [INSN-PATTERN-1 906: INSN-PATTERN-2 907: ...] 908: "CONDITION" 909: "TEMPLATE" 910: "OPTIONAL INSN-ATTRIBUTES") 911: 912: The last string operand may be omitted if you are not using any 913: machine-specific information in this machine description. If present, 914: it must obey the same rules as in a `define_insn'. 915: 916: In this skeleton, INSN-PATTERN-1 and so on are patterns to match 1.1.1.3 ! root 917: consecutive insns. The optimization applies to a sequence of insns when ! 918: INSN-PATTERN-1 matches the first one, INSN-PATTERN-2 matches the next, ! 919: and so on. 1.1.1.2 root 920: 921: Each of the insns matched by a peephole must also match a 922: `define_insn'. Peepholes are checked only at the last stage just 923: before code generation, and only optionally. Therefore, any insn which 924: would match a peephole but no `define_insn' will cause a crash in code 925: generation in an unoptimized compilation, or at various optimization 926: stages. 927: 928: The operands of the insns are matched with `match_operands', 1.1.1.3 ! root 929: `match_operator', and `match_dup', as usual. What is not usual is that ! 930: the operand numbers apply to all the insn patterns in the definition. ! 931: So, you can check for identical operands in two insns by using ! 932: `match_operand' in one insn and `match_dup' in the other. 1.1.1.2 root 933: 934: The operand constraints used in `match_operand' patterns do not have 935: any direct effect on the applicability of the peephole, but they will 1.1.1.3 ! root 936: be validated afterward, so make sure your constraints are general enough ! 937: to apply whenever the peephole matches. If the peephole matches but ! 938: the constraints are not satisfied, the compiler will crash. 1.1.1.2 root 939: 940: It is safe to omit constraints in all the operands of the peephole; 941: or you can write constraints which serve as a double-check on the 942: criteria previously tested. 943: 944: Once a sequence of insns matches the patterns, the CONDITION is 1.1.1.3 ! root 945: checked. This is a C expression which makes the final decision whether ! 946: to perform the optimization (we do so if the expression is nonzero). If ! 947: CONDITION is omitted (in other words, the string is empty) then the ! 948: optimization is applied to every sequence of insns that matches the ! 949: patterns. 1.1.1.2 root 950: 951: The defined peephole optimizations are applied after register 952: allocation is complete. Therefore, the peephole definition can check 953: which operands have ended up in which kinds of registers, just by 954: looking at the operands. 955: 956: The way to refer to the operands in CONDITION is to write 957: `operands[I]' for operand number I (as matched by `(match_operand I 958: ...)'). Use the variable `insn' to refer to the last of the insns 959: being matched; use `prev_nonnote_insn' to find the preceding insns. 960: 961: When optimizing computations with intermediate results, you can use 962: CONDITION to match only when the intermediate results are not used 1.1.1.3 ! root 963: elsewhere. Use the C expression `dead_or_set_p (INSN, OP)', where INSN ! 964: is the insn in which you expect the value to be used for the last time ! 965: (from the value of `insn', together with use of `prev_nonnote_insn'), ! 966: and OP is the intermediate value (from `operands[I]'). ! 967: ! 968: Applying the optimization means replacing the sequence of insns with ! 969: one new insn. The TEMPLATE controls ultimate output of assembler code ! 970: for this combined insn. It works exactly like the template of a ! 971: `define_insn'. Operand numbers in this template are the same ones used ! 972: in matching the original sequence of insns. 1.1.1.2 root 973: 974: The result of a defined peephole optimizer does not need to match 975: any of the insn patterns in the machine description; it does not even 976: have an opportunity to match them. The peephole optimizer definition 977: itself serves as the insn pattern to control how the insn is output. 978: 979: Defined peephole optimizers are run as assembler code is being 980: output, so the insns they produce are never combined or rearranged in 981: any way. 982: 983: Here is an example, taken from the 68000 machine description: 984: 985: (define_peephole 986: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 1.1.1.3 ! root 987: (set (match_operand:DF 0 "register_operand" "=f") 1.1.1.2 root 988: (match_operand:DF 1 "register_operand" "ad"))] 989: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 990: "* 991: { 992: rtx xoperands[2]; 993: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 994: #ifdef MOTOROLA 995: output_asm_insn (\"move.l %1,(sp)\", xoperands); 996: output_asm_insn (\"move.l %1,-(sp)\", operands); 997: return \"fmove.d (sp)+,%0\"; 998: #else 999: output_asm_insn (\"movel %1,sp@\", xoperands); 1000: output_asm_insn (\"movel %1,sp@-\", operands); 1001: return \"fmoved sp@+,%0\"; 1002: #endif 1003: } 1004: ") 1005: 1006: The effect of this optimization is to change 1007: 1008: jbsr _foobar 1009: addql #4,sp 1010: movel d1,sp@- 1011: movel d0,sp@- 1012: fmoved sp@+,fp0 1013: 1014: into 1015: 1016: jbsr _foobar 1017: movel d1,sp@ 1018: movel d0,sp@- 1019: fmoved sp@+,fp0 1020: 1021: INSN-PATTERN-1 and so on look *almost* like the second operand of 1022: `define_insn'. There is one important difference: the second operand 1023: of `define_insn' consists of one or more RTX's enclosed in square 1024: brackets. Usually, there is only one: then the same action can be 1025: written as an element of a `define_peephole'. But when there are 1026: multiple actions in a `define_insn', they are implicitly enclosed in a 1027: `parallel'. Then you must explicitly write the `parallel', and the 1028: square brackets within it, in the `define_peephole'. Thus, if an insn 1029: pattern looks like this, 1030: 1031: (define_insn "divmodsi4" 1032: [(set (match_operand:SI 0 "general_operand" "=d") 1033: (div:SI (match_operand:SI 1 "general_operand" "0") 1034: (match_operand:SI 2 "general_operand" "dmsK"))) 1035: (set (match_operand:SI 3 "general_operand" "=d") 1036: (mod:SI (match_dup 1) (match_dup 2)))] 1037: "TARGET_68020" 1038: "divsl%.l %2,%3:%0") 1039: 1040: then the way to mention this insn in a peephole is as follows: 1041: 1042: (define_peephole 1043: [... 1044: (parallel 1045: [(set (match_operand:SI 0 "general_operand" "=d") 1046: (div:SI (match_operand:SI 1 "general_operand" "0") 1047: (match_operand:SI 2 "general_operand" "dmsK"))) 1048: (set (match_operand:SI 3 "general_operand" "=d") 1049: (mod:SI (match_dup 1) (match_dup 2)))]) 1050: ...] 1051: ...) 1052: 1.1 root 1053:
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