![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to gcc.info-12 CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc|
Return to gcc.info-12 CVS log | Up to [GCC 2.x] / gcc |
1.1.1.3 ! root 1: This is Info file gcc.info, produced by Makeinfo-1.47 from the input 1.1 root 2: file gcc.texi. 3: 4: This file documents the use and the internals of the GNU compiler. 5: 6: Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc. 7: 1.1.1.3 ! root 8: Permission is granted to make and distribute verbatim copies of this ! 9: manual provided the copyright notice and this permission notice are ! 10: preserved on all copies. 1.1 root 11: 12: Permission is granted to copy and distribute modified versions of 13: this manual under the conditions for verbatim copying, provided also 1.1.1.3 ! root 14: that the sections entitled "GNU General Public License" and "Boycott" ! 15: are included exactly as in the original, and provided that the entire ! 16: resulting derived work is distributed under the terms of a permission ! 17: notice identical to this one. 1.1 root 18: 19: Permission is granted to copy and distribute translations of this 20: manual into another language, under the above conditions for modified 1.1.1.3 ! root 21: versions, except that the sections entitled "GNU General Public ! 22: License" and "Boycott", and this permission notice, may be included in ! 23: translations approved by the Free Software Foundation instead of in the ! 24: original English. ! 25: ! 26: ! 27: File: gcc.info, Node: Expander Definitions, Next: Insn Splitting, Prev: Peephole Definitions, Up: Machine Desc ! 28: ! 29: Defining RTL Sequences for Code Generation ! 30: ========================================== ! 31: ! 32: On some target machines, some standard pattern names for RTL ! 33: generation cannot be handled with single insn, but a sequence of RTL ! 34: insns can represent them. For these target machines, you can write a ! 35: `define_expand' to specify how to generate the sequence of RTL. ! 36: ! 37: A `define_expand' is an RTL expression that looks almost like a ! 38: `define_insn'; but, unlike the latter, a `define_expand' is used only ! 39: for RTL generation and it can produce more than one RTL insn. ! 40: ! 41: A `define_expand' RTX has four operands: ! 42: ! 43: * The name. Each `define_expand' must have a name, since the only ! 44: use for it is to refer to it by name. ! 45: ! 46: * The RTL template. This is just like the RTL template for a ! 47: `define_peephole' in that it is a vector of RTL expressions each ! 48: being one insn. ! 49: ! 50: * The condition, a string containing a C expression. This ! 51: expression is used to express how the availability of this pattern ! 52: depends on subclasses of target machine, selected by command-line ! 53: options when GNU CC is run. This is just like the condition of a ! 54: `define_insn' that has a standard name. ! 55: ! 56: * The preparation statements, a string containing zero or more C ! 57: statements which are to be executed before RTL code is generated ! 58: from the RTL template. ! 59: ! 60: Usually these statements prepare temporary registers for use as ! 61: internal operands in the RTL template, but they can also generate ! 62: RTL insns directly by calling routines such as `emit_insn', etc. ! 63: Any such insns precede the ones that come from the RTL template. ! 64: ! 65: Every RTL insn emitted by a `define_expand' must match some ! 66: `define_insn' in the machine description. Otherwise, the compiler will ! 67: crash when trying to generate code for the insn or trying to optimize ! 68: it. ! 69: ! 70: The RTL template, in addition to controlling generation of RTL insns, ! 71: also describes the operands that need to be specified when this pattern ! 72: is used. In particular, it gives a predicate for each operand. ! 73: ! 74: A true operand, which needs to be specified in order to generate RTL ! 75: from the pattern, should be described with a `match_operand' in its ! 76: first occurrence in the RTL template. This enters information on the ! 77: operand's predicate into the tables that record such things. GNU CC ! 78: uses the information to preload the operand into a register if that is ! 79: required for valid RTL code. If the operand is referred to more than ! 80: once, subsequent references should use `match_dup'. ! 81: ! 82: The RTL template may also refer to internal "operands" which are ! 83: temporary registers or labels used only within the sequence made by the ! 84: `define_expand'. Internal operands are substituted into the RTL ! 85: template with `match_dup', never with `match_operand'. The values of ! 86: the internal operands are not passed in as arguments by the compiler ! 87: when it requests use of this pattern. Instead, they are computed ! 88: within the pattern, in the preparation statements. These statements ! 89: compute the values and store them into the appropriate elements of ! 90: `operands' so that `match_dup' can find them. ! 91: ! 92: There are two special macros defined for use in the preparation ! 93: statements: `DONE' and `FAIL'. Use them with a following semicolon, as ! 94: a statement. ! 95: ! 96: `DONE' ! 97: Use the `DONE' macro to end RTL generation for the pattern. The ! 98: only RTL insns resulting from the pattern on this occasion will be ! 99: those already emitted by explicit calls to `emit_insn' within the ! 100: preparation statements; the RTL template will not be generated. ! 101: ! 102: `FAIL' ! 103: Make the pattern fail on this occasion. When a pattern fails, it ! 104: means that the pattern was not truly available. The calling ! 105: routines in the compiler will try other strategies for code ! 106: generation using other patterns. ! 107: ! 108: Failure is currently supported only for binary (addition, ! 109: multiplication, shifting, etc.) and bitfield (`extv', `extzv', and ! 110: `insv') operations. ! 111: ! 112: Here is an example, the definition of left-shift for the SPUR chip: ! 113: ! 114: (define_expand "ashlsi3" ! 115: [(set (match_operand:SI 0 "register_operand" "") ! 116: (ashift:SI ! 117: (match_operand:SI 1 "register_operand" "") ! 118: (match_operand:SI 2 "nonmemory_operand" "")))] ! 119: "" ! 120: " ! 121: { ! 122: if (GET_CODE (operands[2]) != CONST_INT ! 123: || (unsigned) INTVAL (operands[2]) > 3) ! 124: FAIL; ! 125: }") ! 126: ! 127: This example uses `define_expand' so that it can generate an RTL insn ! 128: for shifting when the shift-count is in the supported range of 0 to 3 ! 129: but fail in other cases where machine insns aren't available. When it ! 130: fails, the compiler tries another strategy using different patterns ! 131: (such as, a library call). ! 132: ! 133: If the compiler were able to handle nontrivial condition-strings in ! 134: patterns with names, then it would be possible to use a `define_insn' ! 135: in that case. Here is another case (zero-extension on the 68000) which ! 136: makes more use of the power of `define_expand': ! 137: ! 138: (define_expand "zero_extendhisi2" ! 139: [(set (match_operand:SI 0 "general_operand" "") ! 140: (const_int 0)) ! 141: (set (strict_low_part ! 142: (subreg:HI ! 143: (match_dup 0) ! 144: 0)) ! 145: (match_operand:HI 1 "general_operand" ""))] ! 146: "" ! 147: "operands[1] = make_safe_from (operands[1], operands[0]);") ! 148: ! 149: Here two RTL insns are generated, one to clear the entire output operand ! 150: and the other to copy the input operand into its low half. This ! 151: sequence is incorrect if the input operand refers to [the old value of] ! 152: the output operand, so the preparation statement makes sure this isn't ! 153: so. The function `make_safe_from' copies the `operands[1]' into a ! 154: temporary register if it refers to `operands[0]'. It does this by ! 155: emitting another RTL insn. ! 156: ! 157: Finally, a third example shows the use of an internal operand. ! 158: Zero-extension on the SPUR chip is done by `and'-ing the result against ! 159: a halfword mask. But this mask cannot be represented by a `const_int' ! 160: because the constant value is too large to be legitimate on this ! 161: machine. So it must be copied into a register with `force_reg' and ! 162: then the register used in the `and'. ! 163: ! 164: (define_expand "zero_extendhisi2" ! 165: [(set (match_operand:SI 0 "register_operand" "") ! 166: (and:SI (subreg:SI ! 167: (match_operand:HI 1 "register_operand" "") ! 168: 0) ! 169: (match_dup 2)))] ! 170: "" ! 171: "operands[2] ! 172: = force_reg (SImode, gen_rtx (CONST_INT, ! 173: VOIDmode, 65535)); ") ! 174: ! 175: *Note:* If the `define_expand' is used to serve a standard binary or ! 176: unary arithmetic operation or a bitfield operation, then the last insn ! 177: it generates must not be a `code_label', `barrier' or `note'. It must ! 178: be an `insn', `jump_insn' or `call_insn'. If you don't need a real insn ! 179: at the end, emit an insn to copy the result of the operation into ! 180: itself. Such an insn will generate no code, but it can avoid problems ! 181: in the compiler. ! 182: ! 183: ! 184: File: gcc.info, Node: Insn Splitting, Next: Insn Attributes, Prev: Expander Definitions, Up: Machine Desc ! 185: ! 186: Splitting Instructions into Multiple Instructions ! 187: ================================================= ! 188: ! 189: There are two cases where you should specify how to split a pattern ! 190: into multiple insns. On machines that have instructions requiring delay ! 191: slots (*note Delay Slots::.) or that have instructions whose output is ! 192: not available for multiple cycles (*note Function Units::.), the ! 193: compiler phases that optimize these cases need to be able to move insns ! 194: into one-cycle delay slots. However, some insns may generate more than ! 195: one machine instruction. These insns cannot be placed into a delay ! 196: slot. ! 197: ! 198: Often you can rewrite the single insn as a list of individual insns, ! 199: each corresponding to one machine instruction. The disadvantage of ! 200: doing so is that it will cause the compilation to be slower and require ! 201: more space. If the resulting insns are too complex, it may also ! 202: suppress some optimizations. The compiler splits the insn if there is a ! 203: reason to believe that it might improve instruction or delay slot ! 204: scheduling. ! 205: ! 206: The insn combiner phase also splits putative insns. If three insns ! 207: are merged into one insn with a complex expression that cannot be ! 208: matched by some `define_insn' pattern, the combiner phase attempts to ! 209: split the complex pattern into two insns that are recognized. Usually ! 210: it can break the complex pattern into two patterns by splitting out some ! 211: subexpression. However, in some other cases, such as performing an ! 212: addition of a large constant in two insns on a RISC machine, the way to ! 213: split the addition into two insns is machine-dependent. ! 214: ! 215: The `define_split' definition tells the compiler how to split a ! 216: complex insn into several simpler insns. It looks like this: ! 217: ! 218: (define_split ! 219: [INSN-PATTERN] ! 220: "CONDITION" ! 221: [NEW-INSN-PATTERN-1 ! 222: NEW-INSN-PATTERN-2 ! 223: ...] ! 224: "PREPARATION STATEMENTS") ! 225: ! 226: INSN-PATTERN is a pattern that needs to be split and CONDITION is ! 227: the final condition to be tested, as in a `define_insn'. When an insn ! 228: matching INSN-PATTERN and satisfying CONDITION is found, it is replaced ! 229: in the insn list with the insns given by NEW-INSN-PATTERN-1, ! 230: NEW-INSN-PATTERN-2, etc. ! 231: ! 232: The PREPARATION STATEMENTS are similar to those specified for ! 233: `define_expand' (*note Expander Definitions::.) and are executed before ! 234: the new RTL is generated to prepare for the generated code or emit some ! 235: insns whose pattern is not fixed. ! 236: ! 237: Patterns are matched against INSN-PATTERN in two different ! 238: circumstances. If an insn needs to be split for delay slot scheduling ! 239: or insn scheduling, the insn is already known to be valid, which means ! 240: that it must have been matched by some `define_insn' and, if ! 241: `reload_completed' is non-zero, is known to satisfy the constraints of ! 242: that `define_insn'. In that case, the new insn patterns must also be ! 243: insns that are matched by some `define_insn' and, if `reload_completed' ! 244: is non-zero, must also satisfy the constraints of those definitions. ! 245: ! 246: As an example of this usage of `define_split', consider the following ! 247: example from `a29k.md', which splits a `sign_extend' from `HImode' to ! 248: `SImode' into a pair of shift insns: ! 249: ! 250: (define_split ! 251: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 252: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] ! 253: "" ! 254: [(set (match_dup 0) ! 255: (ashift:SI (match_dup 1) ! 256: (const_int 16))) ! 257: (set (match_dup 0) ! 258: (ashiftrt:SI (match_dup 0) ! 259: (const_int 16)))] ! 260: " ! 261: { operands[1] = gen_lowpart (SImode, operands[1]); }") ! 262: ! 263: When the combiner phase tries to split an insn pattern, it is always ! 264: the case that the pattern is *not* matched by any `define_insn'. The ! 265: combiner pass first tries to split a single `set' expression and then ! 266: the same `set' expression inside a `parallel', but followed by a ! 267: `clobber' of a pseudo-reg to use as a scratch register. In these ! 268: cases, the combiner expects exactly two new insn patterns to be ! 269: generated. It will verify that these patterns match some `define_insn' ! 270: definitions, so you need not do this test in the `define_split' (of ! 271: course, there is no point in writing a `define_split' that will never ! 272: produce insns that match). ! 273: ! 274: Here is an example of this use of `define_split', taken from ! 275: `rs6000.md': ! 276: ! 277: (define_split ! 278: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 279: (plus:SI (match_operand:SI 1 "gen_reg_operand" "") ! 280: (match_operand:SI 2 "non_add_cint_operand" "")))] ! 281: "" ! 282: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) ! 283: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] ! 284: " ! 285: { ! 286: int low = INTVAL (operands[2]) & 0xffff; ! 287: int high = (unsigned) INTVAL (operands[2]) >> 16; ! 288: ! 289: if (low & 0x8000) ! 290: high++, low |= 0xffff0000; ! 291: ! 292: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); ! 293: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); ! 294: }") ! 295: ! 296: Here the predicate `non_add_cint_operand' matches any `const_int' ! 297: that is *not* a valid operand of a single add insn. Write the add with ! 298: the smaller displacement is written so that it can be substituted into ! 299: the address of a subsequent operation. ! 300: ! 301: An example that uses a scratch register, from the same file, ! 302: generates an equality comparison of a register and a large constant: ! 303: ! 304: (define_split ! 305: [(set (match_operand:CC 0 "cc_reg_operand" "") ! 306: (compare:CC (match_operand:SI 1 "gen_reg_operand" "") ! 307: (match_operand:SI 2 "non_short_cint_operand" ""))) ! 308: (clobber (match_operand:SI 3 "gen_reg_operand" ""))] ! 309: "find_single_use (operands[0], insn, 0) ! 310: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ ! 311: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" ! 312: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) ! 313: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] ! 314: " ! 315: { ! 316: /* Get the constant we are comparing against, C, and see what it looks like ! 317: sign-extended to 16 bits. Then see what constant could be XOR'ed ! 318: with C to get the sign-extended value. */ ! 319: ! 320: int c = INTVAL (operands[2]); ! 321: int sextc = (c << 16) >> 16; ! 322: int xorv = c ^ sextc; ! 323: ! 324: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); ! 325: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); ! 326: }") ! 327: ! 328: To avoid confusion, don't write a single `define_split' that accepts ! 329: some insns that match some `define_insn' as well as some insns that ! 330: don't. Instead, write two separate `define_split' definitions, one for ! 331: the insns that are valid and one for the insns that are not valid. ! 332: ! 333: ! 334: File: gcc.info, Node: Insn Attributes, Prev: Insn Splitting, Up: Machine Desc ! 335: ! 336: Instruction Attributes ! 337: ====================== ! 338: ! 339: In addition to describing the instruction supported by the target ! 340: machine, the `md' file also defines a group of "attributes" and a set of ! 341: values for each. Every generated insn is assigned a value for each ! 342: attribute. One possible attribute would be the effect that the insn has ! 343: on the machine's condition code. This attribute can then be used by ! 344: `NOTICE_UPDATE_CC' to track the condition codes. 1.1 root 345: 346: * Menu: 347: 1.1.1.3 ! root 348: * Defining Attributes:: Specifying attributes and their values. ! 349: * Expressions:: Valid expressions for attribute values. ! 350: * Tagging Insns:: Assigning attribute values to insns. ! 351: * Attr Example:: An example of assigning attributes. ! 352: * Insn Lengths:: Computing the length of insns. ! 353: * Constant Attributes:: Defining attributes that are constant. ! 354: * Delay Slots:: Defining delay slots required for a machine. ! 355: * Function Units:: Specifying information for insn scheduling. ! 356: ! 357: ! 358: File: gcc.info, Node: Defining Attributes, Next: Expressions, Prev: Insn Attributes, Up: Insn Attributes ! 359: ! 360: Defining Attributes and their Values ! 361: ------------------------------------ ! 362: ! 363: The `define_attr' expression is used to define each attribute ! 364: required by the target machine. It looks like: ! 365: ! 366: (define_attr NAME LIST-OF-VALUES DEFAULT) ! 367: ! 368: NAME is a string specifying the name of the attribute being defined. ! 369: ! 370: LIST-OF-VALUES is either a string that specifies a comma-separated ! 371: list of values that can be assigned to the attribute, or a null string ! 372: to indicate that the attribute takes numeric values. ! 373: ! 374: DEFAULT is an attribute expression that gives the value of this ! 375: attribute for insns that match patterns whose definition does not ! 376: include an explicit value for this attribute. *Note Attr Example::, ! 377: for more information on the handling of defaults. *Note Constant ! 378: Attributes::, for information on attributes that do not depend on any ! 379: particular insn. ! 380: ! 381: For each defined attribute, a number of definitions are written to ! 382: the `insn-attr.h' file. For cases where an explicit set of values is ! 383: specified for an attribute, the following are defined: ! 384: ! 385: * A `#define' is written for the symbol `HAVE_ATTR_NAME'. ! 386: ! 387: * An enumeral class is defined for `attr_NAME' with elements of the ! 388: form `UPPER-NAME_UPPER-VALUE' where the attribute name and value ! 389: are first converted to upper case. ! 390: ! 391: * A function `get_attr_NAME' is defined that is passed an insn and ! 392: returns the attribute value for that insn. ! 393: ! 394: For example, if the following is present in the `md' file: ! 395: ! 396: (define_attr "type" "branch,fp,load,store,arith" ...) ! 397: ! 398: the following lines will be written to the file `insn-attr.h'. ! 399: ! 400: #define HAVE_ATTR_type ! 401: enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, ! 402: TYPE_STORE, TYPE_ARITH}; ! 403: extern enum attr_type get_attr_type (); ! 404: ! 405: If the attribute takes numeric values, no `enum' type will be ! 406: defined and the function to obtain the attribute's value will return ! 407: `int'. ! 408: ! 409: ! 410: File: gcc.info, Node: Expressions, Next: Tagging Insns, Prev: Defining Attributes, Up: Insn Attributes ! 411: ! 412: Attribute Expressions ! 413: --------------------- ! 414: ! 415: RTL expressions used to define attributes use the codes described ! 416: above plus a few specific to attribute definitions, to be discussed ! 417: below. Attribute value expressions must have one of the following forms: ! 418: ! 419: `(const_int I)' ! 420: The integer I specifies the value of a numeric attribute. I must ! 421: be non-negative. ! 422: ! 423: The value of a numeric attribute can be specified either with a ! 424: `const_int' or as an integer represented as a string in ! 425: `const_string', `eq_attr' (see below), and `set_attr' (*note ! 426: Tagging Insns::.) expressions. ! 427: ! 428: `(const_string VALUE)' ! 429: The string VALUE specifies a constant attribute value. If VALUE is ! 430: specified as `"*"', it means that the default value of the ! 431: attribute is to be used for the insn containing this expression. ! 432: `"*"' obviously cannot be used in the DEFAULT expression of a ! 433: `define_attr'. ! 434: ! 435: If the attribute whose value is being specified is numeric, VALUE ! 436: must be a string containing a non-negative integer (normally ! 437: `const_int' would be used in this case). Otherwise, it must ! 438: contain one of the valid values for the attribute. ! 439: ! 440: `(if_then_else TEST TRUE-VALUE FALSE-VALUE)' ! 441: TEST specifies an attribute test, whose format is defined below. ! 442: The value of this expression is TRUE-VALUE if TEST is true, ! 443: otherwise it is FALSE-VALUE. ! 444: ! 445: `(cond [TEST1 VALUE1 ...] DEFAULT)' ! 446: The first operand of this expression is a vector containing an even ! 447: number of expressions and consisting of pairs of TEST and VALUE ! 448: expressions. The value of the `cond' expression is that of the ! 449: VALUE corresponding to the first true TEST expression. If none of ! 450: the TEST expressions are true, the value of the `cond' expression ! 451: is that of the DEFAULT expression. ! 452: ! 453: TEST expressions can have one of the following forms: ! 454: ! 455: `(const_int I)' ! 456: This test is true if I is non-zero and false otherwise. ! 457: ! 458: `(not TEST)' ! 459: `(ior TEST1 TEST2)' ! 460: `(and TEST1 TEST2)' ! 461: These tests are true if the indicated logical function is true. ! 462: ! 463: `(match_operand:M N PRED CONSTRAINTS)' ! 464: This test is true if operand N of the insn whose attribute value ! 465: is being determined has mode M (this part of the test is ignored ! 466: if M is `VOIDmode') and the function specified by the string PRED ! 467: returns a non-zero value when passed operand N and mode M (this ! 468: part of the test is ignored if PRED is the null string). ! 469: ! 470: The CONSTRAINTS operand is ignored and should be the null string. ! 471: ! 472: `(le ARITH1 ARITH2)' ! 473: `(leu ARITH1 ARITH2)' ! 474: `(lt ARITH1 ARITH2)' ! 475: `(ltu ARITH1 ARITH2)' ! 476: `(gt ARITH1 ARITH2)' ! 477: `(gtu ARITH1 ARITH2)' ! 478: `(ge ARITH1 ARITH2)' ! 479: `(geu ARITH1 ARITH2)' ! 480: `(ne ARITH1 ARITH2)' ! 481: `(eq ARITH1 ARITH2)' ! 482: These tests are true if the indicated comparison of the two ! 483: arithmetic expressions is true. Arithmetic expressions are formed ! 484: with `plus', `minus', `mult', `div', `mod', `abs', `neg', `and', ! 485: `ior', `xor', `not', `lshift', `ashift', `lshiftrt', and `ashiftrt' ! 486: expressions. ! 487: ! 488: `const_int' and `symbol_ref' are always valid terms (*note Insn ! 489: Lengths::.,for additional forms). `symbol_ref' is a string ! 490: denoting a C expression that yields an `int' when evaluated by the ! 491: `get_attr_...' routine. It should normally be a global variable. ! 492: ! 493: `(eq_attr NAME VALUE)' ! 494: NAME is a string specifying the name of an attribute. ! 495: ! 496: VALUE is a string that is either a valid value for attribute NAME, ! 497: a comma-separated list of values, or `!' followed by a value or ! 498: list. If VALUE does not begin with a `!', this test is true if ! 499: the value of the NAME attribute of the current insn is in the list ! 500: specified by VALUE. If VALUE begins with a `!', this test is true ! 501: if the attribute's value is *not* in the specified list. ! 502: ! 503: For example, ! 504: ! 505: (eq_attr "type" "load,store") ! 506: ! 507: is equivalent to ! 508: ! 509: (ior (eq_attr "type" "load") (eq_attr "type" "store")) ! 510: ! 511: If NAME specifies an attribute of `alternative', it refers to the ! 512: value of the compiler variable `which_alternative' (*note Output ! 513: Statement::.) and the values must be small integers. For example, ! 514: ! 515: (eq_attr "alternative" "2,3") ! 516: ! 517: is equivalent to ! 518: ! 519: (ior (eq (symbol_ref "which_alternative") (const_int 2)) ! 520: (eq (symbol_ref "which_alternative") (const_int 3))) ! 521: ! 522: Note that, for most attributes, an `eq_attr' test is simplified in ! 523: cases where the value of the attribute being tested is known for ! 524: all insns matching a particular pattern. This is by far the most ! 525: common case. ! 526: ! 527: ! 528: File: gcc.info, Node: Tagging Insns, Next: Attr Example, Prev: Expressions, Up: Insn Attributes ! 529: ! 530: Assigning Attribute Values to Insns ! 531: ----------------------------------- ! 532: ! 533: The value assigned to an attribute of an insn is primarily ! 534: determined by which pattern is matched by that insn (or which ! 535: `define_peephole' generated it). Every `define_insn' and ! 536: `define_peephole' can have an optional last argument to specify the ! 537: values of attributes for matching insns. The value of any attribute ! 538: not specified in a particular insn is set to the default value for that ! 539: attribute, as specified in its `define_attr'. Extensive use of default ! 540: values for attributes permits the specification of the values for only ! 541: one or two attributes in the definition of most insn patterns, as seen ! 542: in the example in the next section. ! 543: ! 544: The optional last argument of `define_insn' and `define_peephole' is ! 545: a vector of expressions, each of which defines the value for a single ! 546: attribute. The most general way of assigning an attribute's value is ! 547: to use a `set' expression whose first operand is an `attr' expression ! 548: giving the name of the attribute being set. The second operand of the ! 549: `set' is an attribute expression (*note Expressions::.) giving the ! 550: value of the attribute. ! 551: ! 552: When the attribute value depends on the `alternative' attribute ! 553: (i.e., which is the applicable alternative in the constraint of the ! 554: insn), the `set_attr_alternative' expression can can be used. It ! 555: allows the specification of a vector of attribute expressions, one for ! 556: each alternative. ! 557: ! 558: When the generality of arbitrary attribute expressions is not ! 559: required, the simpler `set_attr' expression can be used, which allows ! 560: specifying a string giving either a single attribute value or a list of ! 561: attribute values, one for each alternative. ! 562: ! 563: The form of each of the above specifications is shown below. In ! 564: each case, NAME is a string specifying the attribute to be set. ! 565: ! 566: `(set_attr NAME VALUE-STRING)' ! 567: VALUE-STRING is either a string giving the desired attribute value, ! 568: or a string containing a comma-separated list giving the values for ! 569: succeeding alternatives. The number of elements must match the ! 570: number of alternatives in the constraint of the insn pattern. ! 571: ! 572: Note that it may be useful to specify `*' for some alternative, in ! 573: which case the attribute will assume its default value for insns ! 574: matching that alternative. ! 575: ! 576: `(set_attr_alternative NAME [VALUE1 VALUE2 ...])' ! 577: Depending on the alternative of the insn, the value will be one of ! 578: the specified values. This is a shorthand for using a `cond' with ! 579: tests on the `alternative' attribute. ! 580: ! 581: `(set (attr NAME) VALUE)' ! 582: The first operand of this `set' must be the special RTL expression ! 583: `attr', whose sole operand is a string giving the name of the ! 584: attribute being set. VALUE is the value of the attribute. ! 585: ! 586: The following shows three different ways of representing the same ! 587: attribute value specification: ! 588: ! 589: (set_attr "type" "load,store,arith") ! 590: ! 591: (set_attr_alternative "type" ! 592: [(const_string "load") (const_string "store") ! 593: (const_string "arith")]) ! 594: ! 595: (set (attr "type") ! 596: (cond [(eq_attr "alternative" "1") (const_string "load") ! 597: (eq_attr "alternative" "2") (const_string "store")] ! 598: (const_string "arith"))) ! 599: ! 600: The `define_asm_attributes' expression provides a mechanism to ! 601: specify the attributes assigned to insns produced from an `asm' ! 602: statement. It has the form: ! 603: ! 604: (define_asm_attributes [ATTR-SETS]) ! 605: ! 606: where ATTR-SETS is specified the same as for `define_insn' and ! 607: `define_peephole' expressions. ! 608: ! 609: These values will typically be the "worst case" attribute values. ! 610: For example, they might indicate that the condition code will be ! 611: clobbered. ! 612: ! 613: A specification for a `length' attribute is handled specially. To ! 614: compute the length of an `asm' insn, the length specified in the ! 615: `define_asm_attributes' expression is multiplied by the number of ! 616: machine instructions specified in the `asm' statement, determined by ! 617: counting the number of semicolons and newlines in the string. ! 618: Therefore, the value of the `length' attribute specified in a ! 619: `define_asm_attributes' should be the maximum possible length of a ! 620: single machine instruction. ! 621: ! 622: ! 623: File: gcc.info, Node: Attr Example, Next: Insn Lengths, Prev: Tagging Insns, Up: Insn Attributes ! 624: ! 625: Example of Attribute Specifications ! 626: ----------------------------------- ! 627: ! 628: The judicious use of defaulting is important in the efficient use of ! 629: insn attributes. Typically, insns are divided into "types" and an ! 630: attribute, customarily called `type', is used to represent this value. ! 631: This attribute is normally used only to define the default value for ! 632: other attributes. An example will clarify this usage. ! 633: ! 634: Assume we have a RISC machine with a condition code and in which only ! 635: full-word operations are performed in registers. Let us assume that we ! 636: can divide all insns into loads, stores, (integer) arithmetic ! 637: operations, floating point operations, and branches. ! 638: ! 639: Here we will concern ourselves with determining the effect of an ! 640: insn on the condition code and will limit ourselves to the following ! 641: possible effects: The condition code can be set unpredictably ! 642: (clobbered), not be changed, be set to agree with the results of the ! 643: operation, or only changed if the item previously set into the ! 644: condition code has been modified. ! 645: ! 646: Here is part of a sample `md' file for such a machine: ! 647: ! 648: (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) ! 649: ! 650: (define_attr "cc" "clobber,unchanged,set,change0" ! 651: (cond [(eq_attr "type" "load") ! 652: (const_string "change0") ! 653: (eq_attr "type" "store,branch") ! 654: (const_string "unchanged") ! 655: (eq_attr "type" "arith") ! 656: (if_then_else (match_operand:SI 0 "" "") ! 657: (const_string "set") ! 658: (const_string "clobber"))] ! 659: (const_string "clobber"))) ! 660: ! 661: (define_insn "" ! 662: [(set (match_operand:SI 0 "general_operand" "=r,r,m") ! 663: (match_operand:SI 1 "general_operand" "r,m,r"))] ! 664: "" ! 665: "@ ! 666: move %0,%1 ! 667: load %0,%1 ! 668: store %0,%1" ! 669: [(set_attr "type" "arith,load,store")]) ! 670: ! 671: Note that we assume in the above example that arithmetic operations ! 672: performed on quantities smaller than a machine word clobber the ! 673: condition code since they will set the condition code to a value ! 674: corresponding to the full-word result. ! 675: ! 676: ! 677: File: gcc.info, Node: Insn Lengths, Next: Constant Attributes, Prev: Attr Example, Up: Insn Attributes ! 678: ! 679: Computing the Length of an Insn ! 680: ------------------------------- ! 681: ! 682: For many machines, multiple types of branch instructions are ! 683: provided, each for different length branch displacements. In most ! 684: cases, the assembler will choose the correct instruction to use. ! 685: However, when the assembler cannot do so, GCC can when a special ! 686: attribute, the `length' attribute, is defined. This attribute must be ! 687: defined to have numeric values by specifying a null string in its ! 688: `define_attr'. ! 689: ! 690: In the case of the `length' attribute, two additional forms of ! 691: arithmetic terms are allowed in test expressions: ! 692: ! 693: `(match_dup N)' ! 694: This refers to the address of operand N of the current insn, which ! 695: must be a `label_ref'. ! 696: ! 697: `(pc)' ! 698: This refers to the address of the *current* insn. It might have ! 699: been more consistent with other usage to make this the address of ! 700: the *next* insn but this would be confusing because the length of ! 701: the current insn is to be computed. ! 702: ! 703: For normal insns, the length will be determined by value of the ! 704: `length' attribute. In the case of `addr_vec' and `addr_diff_vec' insn ! 705: patterns, the length will be computed as the number of vectors ! 706: multiplied by the size of each vector. ! 707: ! 708: The following macros can be used to refine the length computation: ! 709: ! 710: `FIRST_INSN_ADDRESS' ! 711: When the `length' insn attribute is used, this macro specifies the ! 712: value to be assigned to the address of the first insn in a ! 713: function. If not specified, 0 is used. ! 714: ! 715: `ADJUST_INSN_LENGTH (INSN, LENGTH)' ! 716: If defined, modifies the length assigned to instruction INSN as a ! 717: function of the context in which it is used. LENGTH is an lvalue ! 718: that contains the initially computed length of the insn and should ! 719: be updated with the correct length of the insn. If updating is ! 720: required, INSN must not be a varying-length insn. ! 721: ! 722: This macro will normally not be required. A case in which it is ! 723: required is the ROMP. On this machine, the size of an `addr_vec' ! 724: insn must be increased by two to compensate for the fact that ! 725: alignment may be required. ! 726: ! 727: The routine that returns the value of the `length' attribute, ! 728: `get_attr_length', can be used by the output routine to determine the ! 729: form of the branch instruction to be written, as the example below ! 730: illustrates. ! 731: ! 732: As an example of the specification of variable-length branches, ! 733: consider the IBM 360. If we adopt the convention that a register will ! 734: be set to the starting address of a function, we can jump to labels ! 735: within 4K of the start using a four-byte instruction. Otherwise, we ! 736: need a six-byte sequence to load the address from memory and then ! 737: branch to it. ! 738: ! 739: On such a machine, a pattern for a branch instruction might be ! 740: specified as follows: ! 741: ! 742: (define_insn "jump" ! 743: [(set (pc) ! 744: (label_ref (match_operand 0 "" "")))] ! 745: "" ! 746: "* ! 747: { ! 748: return (get_attr_length (insn) == 4 ! 749: ? \"b %l0\" : \"l r15,=a(%l0); br r15\"); ! 750: }" ! 751: [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096)) ! 752: (const_int 4) ! 753: (const_int 6)))]) ! 754: ! 755: ! 756: File: gcc.info, Node: Constant Attributes, Next: Delay Slots, Prev: Insn Lengths, Up: Insn Attributes ! 757: ! 758: Constant Attributes ! 759: ------------------- ! 760: ! 761: A special form of `define_attr', where the expression for the ! 762: default value is a `const' expression, indicates an attribute that is ! 763: constant for a given run of the compiler. Constant attributes may be ! 764: used to specify which variety of processor is used. For example, ! 765: ! 766: (define_attr "cpu" "m88100,m88110,m88000" ! 767: (const ! 768: (cond [(symbol_ref "TARGET_88100") (const_string "m88100") ! 769: (symbol_ref "TARGET_88110") (const_string "m88110")] ! 770: (const_string "m88000")))) ! 771: ! 772: (define_attr "memory" "fast,slow" ! 773: (const ! 774: (if_then_else (symbol_ref "TARGET_FAST_MEM") ! 775: (const_string "fast") ! 776: (const_string "slow")))) ! 777: ! 778: The routine generated for constant attributes has no parameters as it ! 779: does not depend on any particular insn. RTL expressions used to define ! 780: the value of a constant attribute may use the `symbol_ref' form, but ! 781: may not use either the `match_operand' form or `eq_attr' forms ! 782: involving insn attributes. ! 783: ! 784: ! 785: File: gcc.info, Node: Delay Slots, Next: Function Units, Prev: Constant Attributes, Up: Insn Attributes ! 786: ! 787: Delay Slot Scheduling ! 788: --------------------- ! 789: ! 790: The insn attribute mechanism can be used to specify the requirements ! 791: for delay slots, if any, on a target machine. An instruction is said to ! 792: require a "delay slot" if some instructions that are physically after ! 793: the instruction are executed as if they were located before it. Classic ! 794: examples are branch and call instructions, which often execute the ! 795: following instruction before the branch or call is performed. ! 796: ! 797: On some machines, conditional branch instructions can optionally ! 798: "annul" instructions in the delay slot. This means that the ! 799: instruction will not be executed for certain branch outcomes. Both ! 800: instructions that annul if the branch is true and instructions that ! 801: annul if the branch is false are supported. ! 802: ! 803: Delay slot scheduling differs from instruction scheduling in that ! 804: determining whether an instruction needs a delay slot is dependent only ! 805: on the type of instruction being generated, not on data flow between the ! 806: instructions. See the next section for a discussion of data-dependent ! 807: instruction scheduling. ! 808: ! 809: The requirement of an insn needing one or more delay slots is ! 810: indicated via the `define_delay' expression. It has the following form: ! 811: ! 812: (define_delay TEST ! 813: [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1 ! 814: DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2 ! 815: ...]) ! 816: ! 817: TEST is an attribute test that indicates whether this `define_delay' ! 818: applies to a particular insn. If so, the number of required delay ! 819: slots is determined by the length of the vector specified as the second ! 820: argument. An insn placed in delay slot N must satisfy attribute test ! 821: DELAY-N. ANNUL-TRUE-N is an attribute test that specifies which insns ! 822: may be annulled if the branch is true. Similarly, ANNUL-FALSE-N ! 823: specifies which insns in the delay slot may be annulled if the branch ! 824: is false. If annulling is not supported for that delay slot, `(nil)' ! 825: should be coded. ! 826: ! 827: For example, in the common case where branch and call insns require ! 828: a single delay slot, which may contain any insn other than a branch or ! 829: call, the following would be placed in the `md' file: ! 830: ! 831: (define_delay (eq_attr "type" "branch,call") ! 832: [(eq_attr "type" "!branch,call") (nil) (nil)]) ! 833: ! 834: Multiple `define_delay' expressions may be specified. In this case, ! 835: each such expression specifies different delay slot requirements and ! 836: there must be no insn for which tests in two `define_delay' expressions ! 837: are both true. ! 838: ! 839: For example, if we have a machine that requires one delay slot for ! 840: branches but two for calls, no delay slot can contain a branch or call ! 841: insn, and any valid insn in the delay slot for the branch can be ! 842: annulled if the branch is true, we might represent this as follows: ! 843: ! 844: (define_delay (eq_attr "type" "branch") ! 845: [(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)]) ! 846: ! 847: (define_delay (eq_attr "type" "call") ! 848: [(eq_attr "type" "!branch,call") (nil) (nil) ! 849: (eq_attr "type" "!branch,call") (nil) (nil)]) ! 850: ! 851: ! 852: File: gcc.info, Node: Function Units, Prev: Delay Slots, Up: Insn Attributes ! 853: ! 854: Specifying Function Units ! 855: ------------------------- ! 856: ! 857: On most RISC machines, there are instructions whose results are not ! 858: available for a specific number of cycles. Common cases are ! 859: instructions that load data from memory. On many machines, a pipeline ! 860: stall will result if the data is referenced too soon after the load ! 861: instruction. ! 862: ! 863: In addition, many newer microprocessors have multiple function ! 864: units, usually one for integer and one for floating point, and often ! 865: will incur pipeline stalls when a result that is needed is not yet ! 866: ready. ! 867: ! 868: The descriptions in this section allow the specification of how much ! 869: time must elapse between the execution of an instruction and the time ! 870: when its result is used. It also allows specification of when the ! 871: execution of an instruction will delay execution of similar instructions ! 872: due to function unit conflicts. ! 873: ! 874: For the purposes of the specifications in this section, a machine is ! 875: divided into "function units", each of which execute a specific class ! 876: of instructions. Function units that accept one instruction each cycle ! 877: and allow a result to be used in the succeeding instruction (usually ! 878: via forwarding) need not be specified. Classic RISC microprocessors ! 879: will normally have a single function unit, which we can call `memory'. ! 880: The newer "superscalar" processors will often have function units for ! 881: floating point operations, usually at least a floating point adder and ! 882: multiplier. ! 883: ! 884: Each usage of a function units by a class of insns is specified with ! 885: a `define_function_unit' expression, which looks like this: ! 886: ! 887: (define_function_unit NAME MULTIPLICITY SIMULTANEITY ! 888: TEST READY-DELAY BUSY-DELAY ! 889: [CONFLICT-LIST]) ! 890: ! 891: NAME is a string giving the name of the function unit. ! 892: ! 893: MULTIPLICITY is an integer specifying the number of identical units ! 894: in the processor. If more than one unit is specified, they will be ! 895: scheduled independently. Only truly independent units should be ! 896: counted; a pipelined unit should be specified as a single unit. (The ! 897: only common example of a machine that has multiple function units for a ! 898: single instruction class that are truly independent and not pipelined ! 899: are the two multiply and two increment units of the CDC 6600.) ! 900: ! 901: SIMULTANEITY specifies the maximum number of insns that can be ! 902: executing in each instance of the function unit simultaneously or zero ! 903: if the unit is pipelined and has no limit. ! 904: ! 905: All `define_function_unit' definitions referring to function unit ! 906: NAME must have the same name and values for MULTIPLICITY and ! 907: SIMULTANEITY. ! 908: ! 909: TEST is an attribute test that selects the insns we are describing ! 910: in this definition. Note that an insn may use more than one function ! 911: unit and a function unit may be specified in more than one ! 912: `define_function_unit'. ! 913: ! 914: READY-DELAY is an integer that specifies the number of cycles after ! 915: which the result of the instruction can be used without introducing any ! 916: stalls. ! 917: ! 918: BUSY-DELAY is an integer that represents the default cost if an insn ! 919: is scheduled for this unit while the unit is active with another insn. ! 920: If SIMULTANEITY is zero, this specification is ignored. Otherwise, a ! 921: zero value indicates that these insns execute on NAME in a fully ! 922: pipelined fashion, even if SIMULTANEITY is non-zero. A non-zero value ! 923: indicates that scheduling a new insn on this unit while another is ! 924: active will incur a cost. A cost of two indicates a single cycle ! 925: delay. For a normal non-pipelined function unit, BUSY-DELAY will be ! 926: twice READY-DELAY. ! 927: ! 928: CONFLICT-LIST is an optional list giving detailed conflict costs for ! 929: this unit. If specified, it is a list of condition test expressions ! 930: which are applied to insns already executing in NAME. For each insn ! 931: that is in the list, BUSY-DELAY will be used for the conflict cost, ! 932: while a value of zero will be used for insns not in the list. ! 933: ! 934: Typical uses of this vector are where a floating point function unit ! 935: can pipeline either single- or double-precision operations, but not ! 936: both, or where a memory unit can pipeline loads, but not stores, etc. ! 937: ! 938: As an example, consider a classic RISC machine where the result of a ! 939: load instruction is not available for two cycles (a single "delay" ! 940: instruction is required) and where only one load instruction can be ! 941: executed simultaneously. This would be specified as: ! 942: ! 943: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 4) ! 944: ! 945: For the case of a floating point function unit that can pipeline ! 946: either single or double precision, but not both, the following could be ! 947: specified: ! 948: ! 949: (define_function_unit ! 950: "fp" 1 1 (eq_attr "type" "sp_fp") 4 8 (eq_attr "type" "dp_fp")] ! 951: (define_function_unit ! 952: "fp" 1 1 (eq_attr "type" "dp_fp") 4 8 (eq_attr "type" "sp_fp")] ! 953: ! 954: *Note:* No code currently exists to avoid function unit conflicts, ! 955: only data conflicts. Hence MULTIPLICITY, SIMULTANEITY, BUSY-COST, and ! 956: CONFLICT-LIST are currently ignored. When such code is written, it is ! 957: possible that the specifications for these values may be changed. It ! 958: has recently come to our attention that these specifications may not ! 959: allow modeling of some of the newer "superscalar" processors that have ! 960: insns using multiple pipelined units. These insns will cause a ! 961: potential conflict for the second unit used during their execution and ! 962: there is no way of representing that conflict. We welcome any examples ! 963: of how function unit conflicts work in such processors and suggestions ! 964: for their representation. ! 965: ! 966: ! 967: File: gcc.info, Node: Target Macros, Next: Config, Prev: Machine Desc, Up: Top ! 968: ! 969: Target Description Macros ! 970: ************************* ! 971: ! 972: In addition to the file `MACHINE.md', a machine description includes ! 973: a C header file conventionally given the name `MACHINE.h'. This header ! 974: file defines numerous macros that convey the information about the ! 975: target machine that does not fit into the scheme of the `.md' file. ! 976: The file `tm.h' should be a link to `MACHINE.h'. The header file ! 977: `config.h' includes `tm.h' and most compiler source files include ! 978: `config.h'. 1.1 root 979: 1.1.1.3 ! root 980: * Menu: 1.1 root 981: 1.1.1.3 ! root 982: * Driver:: Controlling how the driver runs the compilation passes. ! 983: * Run-time Target:: Defining `-m' options like `-m68000' and `-m68020'. ! 984: * Storage Layout:: Defining sizes and alignments of data. ! 985: * Type Layout:: Defining sizes and properties of basic user data types. ! 986: * Registers:: Naming and describing the hardware registers. ! 987: * Register Classes:: Defining the classes of hardware registers. ! 988: * Stack and Calling:: Defining which way the stack grows and by how much. ! 989: * Varargs:: Defining the varargs macros. ! 990: * Trampolines:: Code set up at run time to enter a nested function. ! 991: * Library Calls:: Controlling how library routines are implicitly called. ! 992: * Addressing Modes:: Defining addressing modes valid for memory operands. ! 993: * Condition Code:: Defining how insns update the condition code. ! 994: * Costs:: Defining relative costs of different operations. ! 995: * Sections:: Dividing storage into text, data, and other sections. ! 996: * PIC:: Macros for position independent code. ! 997: * Assembler Format:: Defining how to write insns and pseudo-ops to output. ! 998: * Debugging Info:: Defining the format of debugging output. ! 999: * Cross-compilation:: Handling floating point for cross-compilers. ! 1000: * Misc:: Everything else. 1.1 root 1001: 1002:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.