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1.1.1.4 ! root 1: This is Info file gcc.info, produced by Makeinfo-1.49 from the input 1.1 root 2: file gcc.texi. 3: 4: This file documents the use and the internals of the GNU compiler. 5: 6: Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc. 7: 1.1.1.3 root 8: Permission is granted to make and distribute verbatim copies of this 9: manual provided the copyright notice and this permission notice are 10: preserved on all copies. 1.1 root 11: 12: Permission is granted to copy and distribute modified versions of 13: this manual under the conditions for verbatim copying, provided also 1.1.1.4 ! root 14: that the sections entitled "GNU General Public License" and "Protect ! 15: Your Freedom--Fight `Look And Feel'" are included exactly as in the ! 16: original, and provided that the entire resulting derived work is ! 17: distributed under the terms of a permission notice identical to this ! 18: one. 1.1 root 19: 20: Permission is granted to copy and distribute translations of this 21: manual into another language, under the above conditions for modified 1.1.1.3 root 22: versions, except that the sections entitled "GNU General Public 1.1.1.4 ! root 23: License" and "Protect Your Freedom--Fight `Look And Feel'", and this ! 24: permission notice, may be included in translations approved by the Free ! 25: Software Foundation instead of in the original English. 1.1.1.3 root 26: 27: 1.1.1.4 ! root 28: File: gcc.info, Node: Standard Names, Next: Pattern Ordering, Prev: Constraints, Up: Machine Desc 1.1.1.3 root 29: 1.1.1.4 ! root 30: Standard Names for Patterns Used in Generation ! 31: ============================================== 1.1.1.3 root 32: 1.1.1.4 ! root 33: Here is a table of the instruction names that are meaningful in the ! 34: RTL generation pass of the compiler. Giving one of these names to an ! 35: instruction pattern tells the RTL generation pass that it can use the ! 36: pattern in to accomplish a certain task. ! 37: ! 38: `movM' ! 39: Here M stands for a two-letter machine mode name, in lower case. ! 40: This instruction pattern moves data with that machine mode from ! 41: operand 1 to operand 0. For example, `movsi' moves full-word data. ! 42: ! 43: If operand 0 is a `subreg' with mode M of a register whose own ! 44: mode is wider than M, the effect of this instruction is to store ! 45: the specified value in the part of the register that corresponds ! 46: to mode M. The effect on the rest of the register is undefined. ! 47: ! 48: This class of patterns is special in several ways. First of all, ! 49: each of these names *must* be defined, because there is no other ! 50: way to copy a datum from one place to another. ! 51: ! 52: Second, these patterns are not used solely in the RTL generation ! 53: pass. Even the reload pass can generate move insns to copy values ! 54: from stack slots into temporary registers. When it does so, one ! 55: of the operands is a hard register and the other is an operand ! 56: that can need to be reloaded into a register. ! 57: ! 58: Therefore, when given such a pair of operands, the pattern must ! 59: generate RTL which needs no reloading and needs no temporary ! 60: registers--no registers other than the operands. For example, if ! 61: you support the pattern with a `define_expand', then in such a ! 62: case the `define_expand' mustn't call `force_reg' or any other such ! 63: function which might generate new pseudo registers. ! 64: ! 65: This requirement exists even for subword modes on a RISC machine ! 66: where fetching those modes from memory normally requires several ! 67: insns and some temporary registers. Look in `spur.md' to see how ! 68: the requirement can be satisfied. ! 69: ! 70: During reload a memory reference with an invalid address may be ! 71: passed as an operand. Such an address will be replaced with a ! 72: valid address later in the reload pass. In this case, nothing may ! 73: be done with the address except to use it as it stands. If it is ! 74: copied, it will not be replaced with a valid address. No attempt ! 75: should be made to make such an address into a valid address and no ! 76: routine (such as `change_address') that will do so may be called. ! 77: Note that `general_operand' will fail when applied to such an ! 78: address. ! 79: ! 80: The global variable `reload_in_progress' (which must be explicitly ! 81: declared if required) can be used to determine whether such special ! 82: handling is required. ! 83: ! 84: The variety of operands that have reloads depends on the rest of ! 85: the machine description, but typically on a RISC machine these can ! 86: only be pseudo registers that did not get hard registers, while on ! 87: other machines explicit memory references will get optional ! 88: reloads. ! 89: ! 90: If a scratch register is required to move an object to or from ! 91: memory, it can be allocated using `gen_reg_rtx' prior to reload. ! 92: But this is impossible during and after reload. If there are ! 93: cases needing scratch registers after reload, you must define ! 94: `SECONDARY_INPUT_RELOAD_CLASS' and/or ! 95: `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide ! 96: patterns `reload_inM' or `reload_outM' to handle them. *Note ! 97: Register Classes::. ! 98: ! 99: The constraints on a `moveM' must permit moving any hard register ! 100: to any other hard register provided that `HARD_REGNO_MODE_OK' ! 101: permits mode M in both registers and `REGISTER_MOVE_COST' applied ! 102: to their classes returns a value of 2. ! 103: ! 104: It is obligatory to support floating point `moveM' instructions ! 105: into and out of any registers that can hold fixed point values, ! 106: because unions and structures (which have modes `SImode' or ! 107: `DImode') can be in those registers and they may have floating ! 108: point members. ! 109: ! 110: There may also be a need to support fixed point `moveM' ! 111: instructions in and out of floating point registers. ! 112: Unfortunately, I have forgotten why this was so, and I don't know ! 113: whether it is still true. If `HARD_REGNO_MODE_OK' rejects fixed ! 114: point values in floating point registers, then the constraints of ! 115: the fixed point `moveM' instructions must be designed to avoid ! 116: ever trying to reload into a floating point register. ! 117: ! 118: `reload_inM' ! 119: `reload_outM' ! 120: Like `movM', but used when a scratch register is required to move ! 121: between operand 0 and operand 1. Operand 2 describes the scratch ! 122: register. See the discussion of the `SECONDARY_RELOAD_CLASS' ! 123: macro in *note Register Classes::.. ! 124: ! 125: `movstrictM' ! 126: Like `movM' except that if operand 0 is a `subreg' with mode M of ! 127: a register whose natural mode is wider, the `movstrictM' ! 128: instruction is guaranteed not to alter any of the register except ! 129: the part which belongs to mode M. ! 130: ! 131: `load_multiple' ! 132: Load several consecutive memory locations into consecutive ! 133: registers. Operand 0 is the first of the consecutive registers, ! 134: operand 1 is the first memory location, and operand 2 is a ! 135: constant: the number of consecutive registers. ! 136: ! 137: Define this only if the target machine really has such an ! 138: instruction; do not define this if the most efficient way of ! 139: loading consecutive registers from memory is to do them one at a ! 140: time. ! 141: ! 142: On some machines, there are restrictions as to which consecutive ! 143: registers can be stored into memory, such as particular starting or ! 144: ending register numbers or only a range of valid counts. For those ! 145: machines, use a `define_expand' (*note Expander Definitions::.) ! 146: and make the pattern fail if the restrictions are not met. ! 147: ! 148: Write the generated insn as a `parallel' with elements being a ! 149: `set' of one register from the appropriate memory location (you may ! 150: also need `use' or `clobber' elements). Use a `match_parallel' ! 151: (*note RTL Template::.) to recognize the insn. See `a29k.md' and ! 152: `rs6000.md' for examples of the use of this insn pattern. ! 153: ! 154: `store_multiple' ! 155: Similar to `load_multiple', but store several consecutive registers ! 156: into consecutive memory locations. Operand 0 is the first of the ! 157: consecutive memory locations, operand 1 is the first register, and ! 158: operand 2 is a constant: the number of consecutive registers. ! 159: ! 160: `addM3' ! 161: Add operand 2 and operand 1, storing the result in operand 0. All ! 162: operands must have mode M. This can be used even on two-address ! 163: machines, by means of constraints requiring operands 1 and 0 to be ! 164: the same location. ! 165: ! 166: `subM3', `mulM3' ! 167: `divM3', `udivM3', `modM3', `umodM3' ! 168: `sminM3', `smaxM3', `uminM3', `umaxM3' ! 169: `andM3', `iorM3', `xorM3' ! 170: Similar, for other arithmetic operations. ! 171: ! 172: `mulhisi3' ! 173: Multiply operands 1 and 2, which have mode `HImode', and store a ! 174: `SImode' product in operand 0. ! 175: ! 176: `mulqihi3', `mulsidi3' ! 177: Similar widening-multiplication instructions of other widths. ! 178: ! 179: `umulqihi3', `umulhisi3', `umulsidi3' ! 180: Similar widening-multiplication instructions that do unsigned ! 181: multiplication. ! 182: ! 183: `divmodM4' ! 184: Signed division that produces both a quotient and a remainder. ! 185: Operand 1 is divided by operand 2 to produce a quotient stored in ! 186: operand 0 and a remainder stored in operand 3. ! 187: ! 188: For machines with an instruction that produces both a quotient and ! 189: a remainder, provide a pattern for `divmodM4' but do not provide ! 190: patterns for `divM3' and `modM3'. This allows optimization in the ! 191: relatively common case when both the quotient and remainder are ! 192: computed. ! 193: ! 194: If an instruction that just produces a quotient or just a remainder ! 195: exists and is more efficient than the instruction that produces ! 196: both, write the output routine of `divmodM4' to call ! 197: `find_reg_note' and look for a `REG_UNUSED' note on the quotient ! 198: or remainder and generate the appropriate instruction. ! 199: ! 200: `udivmodM4' ! 201: Similar, but does unsigned division. ! 202: ! 203: `ashlM3' ! 204: Arithmetic-shift operand 1 left by a number of bits specified by ! 205: operand 2, and store the result in operand 0. Here M is the mode ! 206: of operand 0 and operand 1; operand 2's mode is specified by the ! 207: instruction pattern, and the compiler will convert the operand to ! 208: that mode before generating the instruction. ! 209: ! 210: `ashrM3', `lshlM3', `lshrM3', `rotlM3', `rotrM3' ! 211: Other shift and rotate instructions, analogous to the `ashlM3' ! 212: instructions. ! 213: ! 214: Logical and arithmetic left shift are the same. Machines that do ! 215: not allow negative shift counts often have only one instruction for ! 216: shifting left. On such machines, you should define a pattern named ! 217: `ashlM3' and leave `lshlM3' undefined. ! 218: ! 219: `negM2' ! 220: Negate operand 1 and store the result in operand 0. ! 221: ! 222: `absM2' ! 223: Store the absolute value of operand 1 into operand 0. ! 224: ! 225: `sqrtM2' ! 226: Store the square root of operand 1 into operand 0. ! 227: ! 228: The `sqrt' built-in function of C always uses the mode which ! 229: corresponds to the C data type `double'. ! 230: ! 231: `ffsM2' ! 232: Store into operand 0 one plus the index of the least significant ! 233: 1-bit of operand 1. If operand 1 is zero, store zero. M is the ! 234: mode of operand 0; operand 1's mode is specified by the instruction ! 235: pattern, and the compiler will convert the operand to that mode ! 236: before generating the instruction. ! 237: ! 238: The `ffs' built-in function of C always uses the mode which ! 239: corresponds to the C data type `int'. ! 240: ! 241: `one_cmplM2' ! 242: Store the bitwise-complement of operand 1 into operand 0. ! 243: ! 244: `cmpM' ! 245: Compare operand 0 and operand 1, and set the condition codes. The ! 246: RTL pattern should look like this: ! 247: ! 248: (set (cc0) (compare (match_operand:M 0 ...) ! 249: (match_operand:M 1 ...))) ! 250: ! 251: `tstM' ! 252: Compare operand 0 against zero, and set the condition codes. The ! 253: RTL pattern should look like this: ! 254: ! 255: (set (cc0) (match_operand:M 0 ...)) ! 256: ! 257: `tstM' patterns should not be defined for machines that do not use ! 258: `(cc0)'. Doing so would confuse the optimizer since it would no ! 259: longer be clear which `set' operations were comparisons. The ! 260: `cmpM' patterns should be used instead. ! 261: ! 262: `movstrM' ! 263: Block move instruction. The addresses of the destination and ! 264: source strings are the first two operands, and both are in mode ! 265: `Pmode'. The number of bytes to move is the third operand, in mode ! 266: M. ! 267: ! 268: The fourth operand is the known shared alignment of the source and ! 269: destination, in the form of a `const_int' rtx. Thus, if the ! 270: compiler knows that both source and destination are word-aligned, ! 271: it may provide the value 4 for this operand. ! 272: ! 273: These patterns need not give special consideration to the ! 274: possibility that the source and destination strings might overlap. ! 275: ! 276: `cmpstrM' ! 277: Block compare instruction, with five operands. Operand 0 is the ! 278: output; it has mode M. The remaining four operands are like the ! 279: operands of `movstrM'. The two memory blocks specified are ! 280: compared byte by byte in lexicographic order. The effect of the ! 281: instruction is to store a value in operand 0 whose sign indicates ! 282: the result of the comparison. ! 283: ! 284: `floatMN2' ! 285: Convert signed integer operand 1 (valid for fixed point mode M) to ! 286: floating point mode N and store in operand 0 (which has mode N). ! 287: ! 288: `floatunsMN2' ! 289: Convert unsigned integer operand 1 (valid for fixed point mode M) ! 290: to floating point mode N and store in operand 0 (which has mode N). ! 291: ! 292: `fixMN2' ! 293: Convert operand 1 (valid for floating point mode M) to fixed point ! 294: mode N as a signed number and store in operand 0 (which has mode ! 295: N). This instruction's result is defined only when the value of ! 296: operand 1 is an integer. ! 297: ! 298: `fixunsMN2' ! 299: Convert operand 1 (valid for floating point mode M) to fixed point ! 300: mode N as an unsigned number and store in operand 0 (which has ! 301: mode N). This instruction's result is defined only when the value ! 302: of operand 1 is an integer. ! 303: ! 304: `ftruncM2' ! 305: Convert operand 1 (valid for floating point mode M) to an integer ! 306: value, still represented in floating point mode M, and store it in ! 307: operand 0 (valid for floating point mode M). ! 308: ! 309: `fix_truncMN2' ! 310: Like `fixMN2' but works for any floating point value of mode M by ! 311: converting the value to an integer. ! 312: ! 313: `fixuns_truncMN2' ! 314: Like `fixunsMN2' but works for any floating point value of mode M ! 315: by converting the value to an integer. ! 316: ! 317: `truncMN' ! 318: Truncate operand 1 (valid for mode M) to mode N and store in ! 319: operand 0 (which has mode N). Both modes must be fixed point or ! 320: both floating point. ! 321: ! 322: `extendMN' ! 323: Sign-extend operand 1 (valid for mode M) to mode N and store in ! 324: operand 0 (which has mode N). Both modes must be fixed point or ! 325: both floating point. ! 326: ! 327: `zero_extendMN' ! 328: Zero-extend operand 1 (valid for mode M) to mode N and store in ! 329: operand 0 (which has mode N). Both modes must be fixed point. ! 330: ! 331: `extv' ! 332: Extract a bit field from operand 1 (a register or memory operand), ! 333: where operand 2 specifies the width in bits and operand 3 the ! 334: starting bit, and store it in operand 0. Operand 0 must have mode ! 335: `word_mode'. Operand 1 may have mode `byte_mode' or `word_mode'; ! 336: often `word_mode' is allowed only for registers. Operands 2 and 3 ! 337: must be valid for `word_mode'. ! 338: ! 339: The RTL generation pass generates this instruction only with ! 340: constants for operands 2 and 3. ! 341: ! 342: The bit-field value is sign-extended to a full word integer before ! 343: it is stored in operand 0. ! 344: ! 345: `extzv' ! 346: Like `extv' except that the bit-field value is zero-extended. ! 347: ! 348: `insv' ! 349: Store operand 3 (which must be valid for `word_mode') into a bit ! 350: field in operand 0, where operand 1 specifies the width in bits and ! 351: operand 2 the starting bit. Operand 0 may have mode `byte_mode' or ! 352: `word_mode'; often `word_mode' is allowed only for registers. ! 353: Operands 1 and 2 must be valid for `word_mode'. ! 354: ! 355: The RTL generation pass generates this instruction only with ! 356: constants for operands 1 and 2. ! 357: ! 358: `sCOND' ! 359: Store zero or nonzero in the operand according to the condition ! 360: codes. Value stored is nonzero iff the condition COND is true. ! 361: COND is the name of a comparison operation expression code, such ! 362: as `eq', `lt' or `leu'. ! 363: ! 364: You specify the mode that the operand must have when you write the ! 365: `match_operand' expression. The compiler automatically sees which ! 366: mode you have used and supplies an operand of that mode. ! 367: ! 368: The value stored for a true condition must have 1 as its low bit, ! 369: or else must be negative. Otherwise the instruction is not ! 370: suitable and you should omit it from the machine description. You ! 371: describe to the compiler exactly which value is stored by defining ! 372: the macro `STORE_FLAG_VALUE' (*note Misc::.). If a description ! 373: cannot be found that can be used for all the `sCOND' patterns, you ! 374: should omit those operations from the machine description. ! 375: ! 376: These operations may fail, but should do so only in relatively ! 377: uncommon cases; if they would fail for common cases involving ! 378: integer comparisons, it is best to omit these patterns. ! 379: ! 380: If these operations are omitted, the compiler will usually ! 381: generate code that copies the constant one to the target and ! 382: branches around an assignment of zero to the target. If this code ! 383: is more efficient than the potential instructions used for the ! 384: `sCOND' pattern followed by those required to convert the result ! 385: into a 1 or a zero in `SImode', you should omit the `sCOND' ! 386: operations from the machine description. ! 387: ! 388: `bCOND' ! 389: Conditional branch instruction. Operand 0 is a `label_ref' that ! 390: refers to the label to jump to. Jump if the condition codes meet ! 391: condition COND. ! 392: ! 393: Some machines do not follow the model assumed here where a ! 394: comparison instruction is followed by a conditional branch ! 395: instruction. In that case, the `cmpM' (and `tstM') patterns should ! 396: simply store the operands away and generate all the required insns ! 397: in a `define_expand' (*note Expander Definitions::.) for the ! 398: conditional branch operations. All calls to expand `bCOND' ! 399: patterns are immediately preceded by calls to expand either a ! 400: `cmpM' pattern or a `tstM' pattern. ! 401: ! 402: Machines that use a pseudo register for the condition code value, ! 403: or where the mode used for the comparison depends on the condition ! 404: being tested, should also use the above mechanism. *Note Jump ! 405: Patterns:: ! 406: ! 407: The above discussion also applies to `sCOND' patterns. ! 408: ! 409: `call' ! 410: Subroutine call instruction returning no value. Operand 0 is the ! 411: function to call; operand 1 is the number of bytes of arguments ! 412: pushed (in mode `SImode', except it is normally a `const_int'); ! 413: operand 2 is the number of registers used as operands. ! 414: ! 415: On most machines, operand 2 is not actually stored into the RTL ! 416: pattern. It is supplied for the sake of some RISC machines which ! 417: need to put this information into the assembler code; they can put ! 418: it in the RTL instead of operand 1. ! 419: ! 420: Operand 0 should be a `mem' RTX whose address is the address of the ! 421: function. Note, however, that this address can be a `symbol_ref' ! 422: expression even if it would not be a legitimate memory address on ! 423: the target machine. If it is also not a valid argument for a call ! 424: instruction, the pattern for this operation should be a ! 425: `define_expand' (*note Expander Definitions::.) that places the ! 426: address into a register and uses that register in the call ! 427: instruction. ! 428: ! 429: `call_value' ! 430: Subroutine call instruction returning a value. Operand 0 is the ! 431: hard register in which the value is returned. There are three more ! 432: operands, the same as the three operands of the `call' instruction ! 433: (but with numbers increased by one). ! 434: ! 435: Subroutines that return `BLKmode' objects use the `call' insn. ! 436: ! 437: `call_pop', `call_value_pop' ! 438: Similar to `call' and `call_value', except used if defined and if ! 439: `RETURN_POPS_ARGS' is non-zero. They should emit a `parallel' ! 440: that contains both the function call and a `set' to indicate the ! 441: adjustment made to the frame pointer. ! 442: ! 443: For machines where `RETURN_POPS_ARGS' can be non-zero, the use of ! 444: these patterns increases the number of functions for which the ! 445: frame pointer can be eliminated, if desired. ! 446: ! 447: `return' ! 448: Subroutine return instruction. This instruction pattern name ! 449: should be defined only if a single instruction can do all the work ! 450: of returning from a function. ! 451: ! 452: Like the `movM' patterns, this pattern is also used after the RTL ! 453: generation phase. In this case it is to support machines where ! 454: multiple instructions are usually needed to return from a ! 455: function, but some class of functions only requires one ! 456: instruction to implement a return. Normally, the applicable ! 457: functions are those which do not need to save any registers or ! 458: allocate stack space. ! 459: ! 460: For such machines, the condition specified in this pattern should ! 461: only be true when `reload_completed' is non-zero and the function's ! 462: epilogue would only be a single instruction. For machines with ! 463: register windows, the routine `leaf_function_p' may be used to ! 464: determine if a register window push is required. ! 465: ! 466: Machines that have conditional return instructions should define ! 467: patterns such as ! 468: ! 469: (define_insn "" ! 470: [(set (pc) ! 471: (if_then_else (match_operator 0 "comparison_operator" ! 472: [(cc0) (const_int 0)]) ! 473: (return) ! 474: (pc)))] ! 475: "CONDITION" ! 476: "...") ! 477: ! 478: where CONDITION would normally be the same condition specified on ! 479: the named `return' pattern. ! 480: ! 481: `nop' ! 482: No-op instruction. This instruction pattern name should always be ! 483: defined to output a no-op in assembler code. `(const_int 0)' will ! 484: do as an RTL pattern. ! 485: ! 486: `indirect_jump' ! 487: An instruction to jump to an address which is operand zero. This ! 488: pattern name is mandatory on all machines. ! 489: ! 490: `casesi' ! 491: Instruction to jump through a dispatch table, including bounds ! 492: checking. This instruction takes five operands: ! 493: ! 494: 1. The index to dispatch on, which has mode `SImode'. ! 495: ! 496: 2. The lower bound for indices in the table, an integer constant. ! 497: ! 498: 3. The total range of indices in the table--the largest index ! 499: minus the smallest one (both inclusive). ! 500: ! 501: 4. A label that precedes the table itself. ! 502: ! 503: 5. A label to jump to if the index has a value outside the ! 504: bounds. (If the machine-description macro ! 505: `CASE_DROPS_THROUGH' is defined, then an out-of-bounds index ! 506: drops through to the code following the jump table instead of ! 507: jumping to this label. In that case, this label is not ! 508: actually used by the `casesi' instruction, but it is always ! 509: provided as an operand.) ! 510: ! 511: The table is a `addr_vec' or `addr_diff_vec' inside of a ! 512: `jump_insn'. The number of elements in the table is one plus the ! 513: difference between the upper bound and the lower bound. ! 514: ! 515: `tablejump' ! 516: Instruction to jump to a variable address. This is a low-level ! 517: capability which can be used to implement a dispatch table when ! 518: there is no `casesi' pattern. ! 519: ! 520: This pattern requires two operands: the address or offset, and a ! 521: label which should immediately precede the jump table. If the ! 522: macro `CASE_VECTOR_PC_RELATIVE' is defined then the first operand ! 523: is an offset which counts from the address of the table; ! 524: otherwise, it is an absolute address to jump to. In either case, ! 525: the first operand has mode `Pmode'. ! 526: ! 527: The `tablejump' insn is always the last insn before the jump table ! 528: it uses. Its assembler code normally has no need to use the ! 529: second operand, but you should incorporate it in the RTL pattern so ! 530: that the jump optimizer will not delete the table as unreachable ! 531: code. ! 532: ! 533: `save_stack_block' ! 534: `save_stack_function' ! 535: `save_stack_nonlocal' ! 536: `restore_stack_block' ! 537: `restore_stack_function' ! 538: `restore_stack_nonlocal' ! 539: Most machines save and restore the stack pointer by copying it to ! 540: or from an object of mode `Pmode'. Do not define these patterns on ! 541: such machines. ! 542: ! 543: Some machines require special handling for stack pointer saves and ! 544: restores. On those machines, define the patterns corresponding to ! 545: the non-standard cases by using a `define_expand' (*note Expander ! 546: Definitions::.) that produces the required insns. The three types ! 547: of saves and restores are: ! 548: ! 549: 1. `save_stack_block' saves the stack pointer at the start of a ! 550: block that allocates a variable-sized object and ! 551: `restore_stack_block' restores the stack pointer when the ! 552: block is exited. ! 553: ! 554: 2. `save_stack_function' and `restore_stack_function' operate ! 555: similarly for the outermost block of a function and are used ! 556: when the function allocates variable-sized objects or calls ! 557: `alloca'. Only the epilogue uses the restored stack pointer, ! 558: allowing a simpler save or restore sequence on some machines. ! 559: ! 560: 3. `save_stack_nonlocal' is used in functions that contain labels ! 561: branched to by nested functions. It saves the stack pointer ! 562: in such a way that the inner function can use ! 563: `restore_stack_nonlocal' to restore the stack pointer. The ! 564: compiler generates code to restore the frame and argument ! 565: pointer registers, but some machines require saving and ! 566: restoring additional data such as register window information ! 567: or stack backchains. Place insns in these patterns to save ! 568: and restore any such required data. ! 569: ! 570: When saving the stack pointer, operand 0 is the save area and ! 571: operand 1 is the stack pointer. The mode used to allocate the ! 572: save area is the mode of operand 0. You must specify an integral ! 573: mode, or `VOIDmode' if no save area is needed for a particular ! 574: type of save (either because no save is needed or because a ! 575: machine-specific save area can be used). Operand 0 is the stack ! 576: pointer and operand 1 is the save area for restore operations. If ! 577: `save_stack_block' is defined, operand 0 must not be `VOIDmode' ! 578: since these saves can be arbitrarily nested. ! 579: ! 580: A save area is a `mem' that is at a constant offset from ! 581: `virtual_stack_vars_rtx' when the stack pointer is saved for use by ! 582: nonlocal gotos and a `reg' in the other two cases. ! 583: ! 584: `allocate_stack' ! 585: Subtract operand 0 from the stack pointer to create space for for ! 586: dynamically allocated data. ! 587: ! 588: Do not define this pattern if all that must be done is the ! 589: subtraction. On some machines require other operations such as ! 590: stack probes or maintaining the back chain. Define this pattern ! 591: to emit those operations in addition to updating the stack pointer. 1.1.1.3 root 592: 593: 1.1.1.4 ! root 594: File: gcc.info, Node: Pattern Ordering, Next: Dependent Patterns, Prev: Standard Names, Up: Machine Desc 1.1.1.3 root 595: 1.1.1.4 ! root 596: When the Order of Patterns Matters ! 597: ================================== 1.1.1.3 root 598: 1.1.1.4 ! root 599: Sometimes an insn can match more than one instruction pattern. Then ! 600: the pattern that appears first in the machine description is the one ! 601: used. Therefore, more specific patterns (patterns that will match fewer ! 602: things) and faster instructions (those that will produce better code ! 603: when they do match) should usually go first in the description. ! 604: ! 605: In some cases the effect of ordering the patterns can be used to hide ! 606: a pattern when it is not valid. For example, the 68000 has an ! 607: instruction for converting a fullword to floating point and another for ! 608: converting a byte to floating point. An instruction converting an ! 609: integer to floating point could match either one. We put the pattern ! 610: to convert the fullword first to make sure that one will be used rather ! 611: than the other. (Otherwise a large integer might be generated as a ! 612: single-byte immediate quantity, which would not work.) Instead of using ! 613: this pattern ordering it would be possible to make the pattern for ! 614: convert-a-byte smart enough to deal properly with any constant value. 1.1.1.3 root 615: 616: 1.1.1.4 ! root 617: File: gcc.info, Node: Dependent Patterns, Next: Jump Patterns, Prev: Pattern Ordering, Up: Machine Desc 1.1.1.3 root 618: 1.1.1.4 ! root 619: Interdependence of Patterns ! 620: =========================== 1.1.1.3 root 621: 1.1.1.4 ! root 622: Every machine description must have a named pattern for each of the ! 623: conditional branch names `bCOND'. The recognition template must always ! 624: have the form ! 625: ! 626: (set (pc) ! 627: (if_then_else (COND (cc0) (const_int 0)) ! 628: (label_ref (match_operand 0 "" "")) ! 629: (pc))) ! 630: ! 631: In addition, every machine description must have an anonymous pattern ! 632: for each of the possible reverse-conditional branches. Their templates ! 633: look like ! 634: ! 635: (set (pc) ! 636: (if_then_else (COND (cc0) (const_int 0)) ! 637: (pc) ! 638: (label_ref (match_operand 0 "" "")))) ! 639: ! 640: They are necessary because jump optimization can turn direct-conditional ! 641: branches into reverse-conditional branches. ! 642: ! 643: It is often convenient to use the `match_operator' construct to ! 644: reduce the number of patterns that must be specified for branches. For ! 645: example, 1.1.1.3 root 646: 1.1.1.4 ! root 647: (define_insn "" ! 648: [(set (pc) ! 649: (if_then_else (match_operator 0 "comparison_operator" ! 650: [(cc0) (const_int 0)]) ! 651: (pc) ! 652: (label_ref (match_operand 1 "" ""))))] ! 653: "CONDITION" ! 654: "...") 1.1.1.3 root 655: 1.1.1.4 ! root 656: In some cases machines support instructions identical except for the ! 657: machine mode of one or more operands. For example, there may be ! 658: "sign-extend halfword" and "sign-extend byte" instructions whose ! 659: patterns are 1.1.1.3 root 660: 1.1.1.4 ! root 661: (set (match_operand:SI 0 ...) ! 662: (extend:SI (match_operand:HI 1 ...))) 1.1.1.3 root 663: 1.1.1.4 ! root 664: (set (match_operand:SI 0 ...) ! 665: (extend:SI (match_operand:QI 1 ...))) 1.1.1.3 root 666: 1.1.1.4 ! root 667: Constant integers do not specify a machine mode, so an instruction to ! 668: extend a constant value could match either pattern. The pattern it ! 669: actually will match is the one that appears first in the file. For ! 670: correct results, this must be the one for the widest possible mode ! 671: (`HImode', here). If the pattern matches the `QImode' instruction, the ! 672: results will be incorrect if the constant value does not actually fit ! 673: that mode. ! 674: ! 675: Such instructions to extend constants are rarely generated because ! 676: they are optimized away, but they do occasionally happen in nonoptimized ! 677: compilations. ! 678: ! 679: If a constraint in a pattern allows a constant, the reload pass may ! 680: replace a register with a constant permitted by the constraint in some ! 681: cases. Similarly for memory references. You must ensure that the ! 682: predicate permits all objects allowed by the constraints to prevent the ! 683: compiler from crashing. ! 684: ! 685: Because of this substitution, you should not provide separate ! 686: patterns for increment and decrement instructions. Instead, they ! 687: should be generated from the same pattern that supports ! 688: register-register add insns by examining the operands and generating ! 689: the appropriate machine instruction. 1.1.1.3 root 690: 691: 1.1.1.4 ! root 692: File: gcc.info, Node: Jump Patterns, Next: Insn Canonicalizations, Prev: Dependent Patterns, Up: Machine Desc 1.1.1.3 root 693: 1.1.1.4 ! root 694: Defining Jump Instruction Patterns ! 695: ================================== 1.1.1.3 root 696: 1.1.1.4 ! root 697: For most machines, GNU CC assumes that the machine has a condition ! 698: code. A comparison insn sets the condition code, recording the results ! 699: of both signed and unsigned comparison of the given operands. A ! 700: separate branch insn tests the condition code and branches or not ! 701: according its value. The branch insns come in distinct signed and ! 702: unsigned flavors. Many common machines, such as the Vax, the 68000 and ! 703: the 32000, work this way. ! 704: ! 705: Some machines have distinct signed and unsigned compare ! 706: instructions, and only one set of conditional branch instructions. The ! 707: easiest way to handle these machines is to treat them just like the ! 708: others until the final stage where assembly code is written. At this ! 709: time, when outputting code for the compare instruction, peek ahead at ! 710: the following branch using `next_cc0_user (insn)'. (The variable ! 711: `insn' refers to the insn being output, in the output-writing code in ! 712: an instruction pattern.) If the RTL says that is an unsigned branch, ! 713: output an unsigned compare; otherwise output a signed compare. When ! 714: the branch itself is output, you can treat signed and unsigned branches ! 715: identically. ! 716: ! 717: The reason you can do this is that GNU CC always generates a pair of ! 718: consecutive RTL insns, possibly separated by `note' insns, one to set ! 719: the condition code and one to test it, and keeps the pair inviolate ! 720: until the end. ! 721: ! 722: To go with this technique, you must define the machine-description ! 723: macro `NOTICE_UPDATE_CC' to do `CC_STATUS_INIT'; in other words, no ! 724: compare instruction is superfluous. ! 725: ! 726: Some machines have compare-and-branch instructions and no condition ! 727: code. A similar technique works for them. When it is time to "output" a ! 728: compare instruction, record its operands in two static variables. When ! 729: outputting the branch-on-condition-code instruction that follows, ! 730: actually output a compare-and-branch instruction that uses the ! 731: remembered operands. ! 732: ! 733: It also works to define patterns for compare-and-branch instructions. ! 734: In optimizing compilation, the pair of compare and branch instructions ! 735: will be combined according to these patterns. But this does not happen ! 736: if optimization is not requested. So you must use one of the solutions ! 737: above in addition to any special patterns you define. ! 738: ! 739: In many RISC machines, most instructions do not affect the condition ! 740: code and there may not even be a separate condition code register. On ! 741: these machines, the restriction that the definition and use of the ! 742: condition code be adjacent insns is not necessary and can prevent ! 743: important optimizations. For example, on the IBM RS/6000, there is a ! 744: delay for taken branches unless the condition code register is set three ! 745: instructions earlier than the conditional branch. The instruction ! 746: scheduler cannot perform this optimization if it is not permitted to ! 747: separate the definition and use of the condition code register. ! 748: ! 749: On these machines, do not use `(cc0)', but instead use a register to ! 750: represent the condition code. If there is a specific condition code ! 751: register in the machine, use a hard register. If the condition code or ! 752: comparison result can be placed in any general register, or if there are ! 753: multiple condition registers, use a pseudo register. ! 754: ! 755: On some machines, the type of branch instruction generated may ! 756: depend on the way the condition code was produced; for example, on the ! 757: 68k and Sparc, setting the condition code directly from an add or ! 758: subtract instruction does not clear the overflow bit the way that a test ! 759: instruction does, so a different branch instruction must be used for ! 760: some conditional branches. For machines that use `(cc0)', the set and ! 761: use of the condition code must be adjacent (separated only by `note' ! 762: insns) allowing flags in `cc_status' to be used. (*Note Condition ! 763: Code::.) Also, the comparison and branch insns can be located from ! 764: each other by using the functions `prev_cc0_setter' and `next_cc0_user'. ! 765: ! 766: However, this is not true on machines that do not use `(cc0)'. On ! 767: those machines, no assumptions can be made about the adjacency of the ! 768: compare and branch insns and the above methods cannot be used. Instead, ! 769: we use the machine mode of the condition code register to record ! 770: different formats of the condition code register. ! 771: ! 772: Registers used to store the condition code value should have a mode ! 773: that is in class `MODE_CC'. Normally, it will be `CCmode'. If ! 774: additional modes are required (as for the add example mentioned above in ! 775: the Sparc), define the macro `EXTRA_CC_MODES' to list the additional ! 776: modes required (*note Condition Code::.). Also define `EXTRA_CC_NAMES' ! 777: to list the names of those modes and `SELECT_CC_MODE' to choose a mode ! 778: given an operand of a compare. ! 779: ! 780: If it is known during RTL generation that a different mode will be ! 781: required (for example, if the machine has separate compare instructions ! 782: for signed and unsigned quantities, like most IBM processors), they can ! 783: be specified at that time. ! 784: ! 785: If the cases that require different modes would be made by ! 786: instruction combination, the macro `SELECT_CC_MODE' determines which ! 787: machine mode should be used for the comparison result. The patterns ! 788: should be written using that mode. To support the case of the add on ! 789: the Sparc discussed above, we have the pattern 1.1.1.3 root 790: 1.1.1.4 ! root 791: (define_insn "" ! 792: [(set (reg:CC_NOOV 0) ! 793: (compare:CC_NOOV (plus:SI (match_operand:SI 0 "register_operand" "%r") ! 794: (match_operand:SI 1 "arith_operand" "rI")) ! 795: (const_int 0)))] 1.1.1.3 root 796: "" 1.1.1.4 ! root 797: "...") 1.1.1.3 root 798: 1.1.1.4 ! root 799: The `SELECT_CC_MODE' macro on the Sparc returns `CC_NOOVmode' for ! 800: comparisons whose argument is a `plus'. 1.1.1.3 root 801: 802: 1.1.1.4 ! root 803: File: gcc.info, Node: Insn Canonicalizations, Next: Peephole Definitions, Prev: Jump Patterns, Up: Machine Desc 1.1.1.3 root 804: 1.1.1.4 ! root 805: Canonicalization of Instructions ! 806: ================================ 1.1.1.3 root 807: 1.1.1.4 ! root 808: There are often cases where multiple RTL expressions could represent ! 809: an operation performed by a single machine instruction. This situation ! 810: is most commonly encountered with logical, branch, and ! 811: multiply-accumulate instructions. In such cases, the compiler attempts ! 812: to convert these multiple RTL expressions into a single canonical form ! 813: to reduce the number of insn patterns required. ! 814: ! 815: In addition to algebraic simplifications, following canonicalizations ! 816: are performed: ! 817: ! 818: * For commutative and comparison operators, a constant is always ! 819: made the second operand. If a machine only supports a constant as ! 820: the second operand, only patterns that match a constant in the ! 821: second operand need be supplied. ! 822: ! 823: For these operators, if only one operand is a `neg', `not', ! 824: `mult', `plus', or `minus' expression, it will be the first ! 825: operand. ! 826: ! 827: * For the `compare' operator, a constant is always the second operand ! 828: on machines where `cc0' is used (*note Jump Patterns::.). On other ! 829: machines, there are rare cases where the compiler might want to ! 830: construct a `compare' with a constant as the first operand. ! 831: However, these cases are not common enough for it to be worthwhile ! 832: to provide a pattern matching a constant as the first operand ! 833: unless the machine actually has such an instruction. ! 834: ! 835: An operand of `neg', `not', `mult', `plus', or `minus' is made the ! 836: first operand under the same conditions as above. ! 837: ! 838: * `(minus X (const_int N))' is converted to `(plus X (const_int ! 839: -N))'. ! 840: ! 841: * Within address computations (i.e., inside `mem'), a left shift is ! 842: converted into the appropriate multiplication by a power of two. ! 843: ! 844: De`Morgan's Law is used to move bitwise negation inside a bitwise ! 845: logical-and or logical-or operation. If this results in only one ! 846: operand being a `not' expression, it will be the first one. ! 847: ! 848: A machine that has an instruction that performs a bitwise ! 849: logical-and of one operand with the bitwise negation of the other ! 850: should specify the pattern for that instruction as ! 851: ! 852: (define_insn "" ! 853: [(set (match_operand:M 0 ...) ! 854: (and:M (not:M (match_operand:M 1 ...)) ! 855: (match_operand:M 2 ...)))] ! 856: "..." ! 857: "...") ! 858: ! 859: Similarly, a pattern for a "NAND" instruction should be written ! 860: ! 861: (define_insn "" ! 862: [(set (match_operand:M 0 ...) ! 863: (ior:M (not:M (match_operand:M 1 ...)) ! 864: (not:M (match_operand:M 2 ...))))] ! 865: "..." ! 866: "...") ! 867: ! 868: In both cases, it is not necessary to include patterns for the many ! 869: logically equivalent RTL expressions. ! 870: ! 871: * The only possible RTL expressions involving both bitwise ! 872: exclusive-or and bitwise negation are `(xor:M X) Y)' and `(not:M ! 873: (xor:M X Y))'. ! 874: ! 875: * The sum of three items, one of which is a constant, will only ! 876: appear in the form ! 877: ! 878: (plus:M (plus:M X Y) CONSTANT) ! 879: ! 880: * On machines that do not use `cc0', `(compare X (const_int 0))' ! 881: will be converted to X. ! 882: ! 883: * Equality comparisons of a group of bits (usually a single bit) ! 884: with zero will be written using `zero_extract' rather than the ! 885: equivalent `and' or `sign_extract' operations. 1.1.1.3 root 886: 887: 1.1.1.4 ! root 888: File: gcc.info, Node: Peephole Definitions, Next: Expander Definitions, Prev: Insn Canonicalizations, Up: Machine Desc 1.1.1.3 root 889: 1.1.1.4 ! root 890: Defining Machine-Specific Peephole Optimizers ! 891: ============================================= 1.1.1.3 root 892: 1.1.1.4 ! root 893: In addition to instruction patterns the `md' file may contain ! 894: definitions of machine-specific peephole optimizations. 1.1.1.3 root 895: 1.1.1.4 ! root 896: The combiner does not notice certain peephole optimizations when the ! 897: data flow in the program does not suggest that it should try them. For ! 898: example, sometimes two consecutive insns related in purpose can be ! 899: combined even though the second one does not appear to use a register ! 900: computed in the first one. A machine-specific peephole optimizer can ! 901: detect such opportunities. ! 902: ! 903: A definition looks like this: ! 904: ! 905: (define_peephole ! 906: [INSN-PATTERN-1 ! 907: INSN-PATTERN-2 ! 908: ...] ! 909: "CONDITION" ! 910: "TEMPLATE" ! 911: "OPTIONAL INSN-ATTRIBUTES") 1.1.1.3 root 912: 1.1.1.4 ! root 913: The last string operand may be omitted if you are not using any ! 914: machine-specific information in this machine description. If present, ! 915: it must obey the same rules as in a `define_insn'. ! 916: ! 917: In this skeleton, INSN-PATTERN-1 and so on are patterns to match ! 918: consecutive insns. The optimization applies to a sequence of insns when ! 919: INSN-PATTERN-1 matches the first one, INSN-PATTERN-2 matches the next, ! 920: and so on. ! 921: ! 922: Each of the insns matched by a peephole must also match a ! 923: `define_insn'. Peepholes are checked only at the last stage just ! 924: before code generation, and only optionally. Therefore, any insn which ! 925: would match a peephole but no `define_insn' will cause a crash in code ! 926: generation in an unoptimized compilation, or at various optimization ! 927: stages. ! 928: ! 929: The operands of the insns are matched with `match_operands', ! 930: `match_operator', and `match_dup', as usual. What is not usual is that ! 931: the operand numbers apply to all the insn patterns in the definition. ! 932: So, you can check for identical operands in two insns by using ! 933: `match_operand' in one insn and `match_dup' in the other. ! 934: ! 935: The operand constraints used in `match_operand' patterns do not have ! 936: any direct effect on the applicability of the peephole, but they will ! 937: be validated afterward, so make sure your constraints are general enough ! 938: to apply whenever the peephole matches. If the peephole matches but ! 939: the constraints are not satisfied, the compiler will crash. ! 940: ! 941: It is safe to omit constraints in all the operands of the peephole; ! 942: or you can write constraints which serve as a double-check on the ! 943: criteria previously tested. ! 944: ! 945: Once a sequence of insns matches the patterns, the CONDITION is ! 946: checked. This is a C expression which makes the final decision whether ! 947: to perform the optimization (we do so if the expression is nonzero). If ! 948: CONDITION is omitted (in other words, the string is empty) then the ! 949: optimization is applied to every sequence of insns that matches the ! 950: patterns. ! 951: ! 952: The defined peephole optimizations are applied after register ! 953: allocation is complete. Therefore, the peephole definition can check ! 954: which operands have ended up in which kinds of registers, just by ! 955: looking at the operands. ! 956: ! 957: The way to refer to the operands in CONDITION is to write ! 958: `operands[I]' for operand number I (as matched by `(match_operand I ! 959: ...)'). Use the variable `insn' to refer to the last of the insns ! 960: being matched; use `prev_nonnote_insn' to find the preceding insns. ! 961: ! 962: When optimizing computations with intermediate results, you can use ! 963: CONDITION to match only when the intermediate results are not used ! 964: elsewhere. Use the C expression `dead_or_set_p (INSN, OP)', where INSN ! 965: is the insn in which you expect the value to be used for the last time ! 966: (from the value of `insn', together with use of `prev_nonnote_insn'), ! 967: and OP is the intermediate value (from `operands[I]'). ! 968: ! 969: Applying the optimization means replacing the sequence of insns with ! 970: one new insn. The TEMPLATE controls ultimate output of assembler code ! 971: for this combined insn. It works exactly like the template of a ! 972: `define_insn'. Operand numbers in this template are the same ones used ! 973: in matching the original sequence of insns. ! 974: ! 975: The result of a defined peephole optimizer does not need to match ! 976: any of the insn patterns in the machine description; it does not even ! 977: have an opportunity to match them. The peephole optimizer definition ! 978: itself serves as the insn pattern to control how the insn is output. ! 979: ! 980: Defined peephole optimizers are run as assembler code is being ! 981: output, so the insns they produce are never combined or rearranged in ! 982: any way. ! 983: ! 984: Here is an example, taken from the 68000 machine description: ! 985: ! 986: (define_peephole ! 987: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) ! 988: (set (match_operand:DF 0 "register_operand" "=f") ! 989: (match_operand:DF 1 "register_operand" "ad"))] ! 990: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" ! 991: "* ! 992: { ! 993: rtx xoperands[2]; ! 994: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 995: #ifdef MOTOROLA ! 996: output_asm_insn (\"move.l %1,(sp)\", xoperands); ! 997: output_asm_insn (\"move.l %1,-(sp)\", operands); ! 998: return \"fmove.d (sp)+,%0\"; ! 999: #else ! 1000: output_asm_insn (\"movel %1,sp@\", xoperands); ! 1001: output_asm_insn (\"movel %1,sp@-\", operands); ! 1002: return \"fmoved sp@+,%0\"; ! 1003: #endif ! 1004: } ! 1005: ") ! 1006: ! 1007: The effect of this optimization is to change ! 1008: ! 1009: jbsr _foobar ! 1010: addql #4,sp ! 1011: movel d1,sp@- ! 1012: movel d0,sp@- ! 1013: fmoved sp@+,fp0 ! 1014: ! 1015: into ! 1016: ! 1017: jbsr _foobar ! 1018: movel d1,sp@ ! 1019: movel d0,sp@- ! 1020: fmoved sp@+,fp0 ! 1021: ! 1022: INSN-PATTERN-1 and so on look *almost* like the second operand of ! 1023: `define_insn'. There is one important difference: the second operand ! 1024: of `define_insn' consists of one or more RTX's enclosed in square ! 1025: brackets. Usually, there is only one: then the same action can be ! 1026: written as an element of a `define_peephole'. But when there are ! 1027: multiple actions in a `define_insn', they are implicitly enclosed in a ! 1028: `parallel'. Then you must explicitly write the `parallel', and the ! 1029: square brackets within it, in the `define_peephole'. Thus, if an insn ! 1030: pattern looks like this, ! 1031: ! 1032: (define_insn "divmodsi4" ! 1033: [(set (match_operand:SI 0 "general_operand" "=d") ! 1034: (div:SI (match_operand:SI 1 "general_operand" "0") ! 1035: (match_operand:SI 2 "general_operand" "dmsK"))) ! 1036: (set (match_operand:SI 3 "general_operand" "=d") ! 1037: (mod:SI (match_dup 1) (match_dup 2)))] ! 1038: "TARGET_68020" ! 1039: "divsl%.l %2,%3:%0") ! 1040: ! 1041: then the way to mention this insn in a peephole is as follows: ! 1042: ! 1043: (define_peephole ! 1044: [... ! 1045: (parallel ! 1046: [(set (match_operand:SI 0 "general_operand" "=d") ! 1047: (div:SI (match_operand:SI 1 "general_operand" "0") ! 1048: (match_operand:SI 2 "general_operand" "dmsK"))) ! 1049: (set (match_operand:SI 3 "general_operand" "=d") ! 1050: (mod:SI (match_dup 1) (match_dup 2)))]) ! 1051: ...] ! 1052: ...) 1.1 root 1053: 1054:
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