--- gcc/gcc.info-13 2018/04/24 18:07:11 1.1.1.5 +++ gcc/gcc.info-13 2018/04/24 18:18:07 1.1.1.7 @@ -1,4 +1,4 @@ -This is Info file gcc.info, produced by Makeinfo-1.54 from the input +This is Info file gcc.info, produced by Makeinfo-1.55 from the input file gcc.texi. This file documents the use and the internals of the GNU compiler. @@ -6,7 +6,8 @@ file gcc.texi. Published by the Free Software Foundation 675 Massachusetts Avenue Cambridge, MA 02139 USA - Copyright (C) 1988, 1989, 1992, 1993 Free Software Foundation, Inc. + Copyright (C) 1988, 1989, 1992, 1993, 1994 Free Software Foundation, +Inc. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are @@ -14,1258 +15,988 @@ preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided also -that the sections entitled "GNU General Public License" and "Protect -Your Freedom--Fight `Look And Feel'" are included exactly as in the -original, and provided that the entire resulting derived work is -distributed under the terms of a permission notice identical to this -one. +that the sections entitled "GNU General Public License," "Funding for +Free Software," and "Protect Your Freedom--Fight `Look And Feel'" are +included exactly as in the original, and provided that the entire +resulting derived work is distributed under the terms of a permission +notice identical to this one. Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions, except that the sections entitled "GNU General Public -License" and "Protect Your Freedom--Fight `Look And Feel'", and this -permission notice, may be included in translations approved by the Free -Software Foundation instead of in the original English. +License," "Funding for Free Software," and "Protect Your Freedom--Fight +`Look And Feel'", and this permission notice, may be included in +translations approved by the Free Software Foundation instead of in the +original English.  -File: gcc.info, Node: RTL Template, Next: Output Template, Prev: Example, Up: Machine Desc +File: gcc.info, Node: Regs and Memory, Next: Arithmetic, Prev: Constants, Up: RTL -RTL Template -============ - - The RTL template is used to define which insns match the particular -pattern and how to find their operands. For named patterns, the RTL -template also says how to construct an insn from specified operands. - - Construction involves substituting specified operands into a copy of -the template. Matching involves determining the values that serve as -the operands in the insn being matched. Both of these activities are -controlled by special expression types that direct matching and -substitution of the operands. - -`(match_operand:M N PREDICATE CONSTRAINT)' - This expression is a placeholder for operand number N of the insn. - When constructing an insn, operand number N will be substituted - at this point. When matching an insn, whatever appears at this - position in the insn will be taken as operand number N; but it - must satisfy PREDICATE or this instruction pattern will not match - at all. - - Operand numbers must be chosen consecutively counting from zero in - each instruction pattern. There may be only one `match_operand' - expression in the pattern for each operand number. Usually - operands are numbered in the order of appearance in `match_operand' - expressions. - - PREDICATE is a string that is the name of a C function that - accepts two arguments, an expression and a machine mode. During - matching, the function will be called with the putative operand as - the expression and M as the mode argument (if M is not specified, - `VOIDmode' will be used, which normally causes PREDICATE to accept - any mode). If it returns zero, this instruction pattern fails to - match. PREDICATE may be an empty string; then it means no test is - to be done on the operand, so anything which occurs in this - position is valid. - - Most of the time, PREDICATE will reject modes other than M--but - not always. For example, the predicate `address_operand' uses M - as the mode of memory ref that the address should be valid for. - Many predicates accept `const_int' nodes even though their mode is - `VOIDmode'. - - CONSTRAINT controls reloading and the choice of the best register - class to use for a value, as explained later (*note - Constraints::.). - - People are often unclear on the difference between the constraint - and the predicate. The predicate helps decide whether a given - insn matches the pattern. The constraint plays no role in this - decision; instead, it controls various decisions in the case of an - insn which does match. - - On CISC machines, the most common PREDICATE is - `"general_operand"'. This function checks that the putative - operand is either a constant, a register or a memory reference, - and that it is valid for mode M. - - For an operand that must be a register, PREDICATE should be - `"register_operand"'. Using `"general_operand"' would be valid, - since the reload pass would copy any non-register operands through - registers, but this would make GNU CC do extra work, it would - prevent invariant operands (such as constant) from being removed - from loops, and it would prevent the register allocator from doing - the best possible job. On RISC machines, it is usually most - efficient to allow PREDICATE to accept only objects that the - constraints allow. - - For an operand that must be a constant, you must be sure to either - use `"immediate_operand"' for PREDICATE, or make the instruction - pattern's extra condition require a constant, or both. You cannot - expect the constraints to do this work! If the constraints allow - only constants, but the predicate allows something else, the - compiler will crash when that case arises. - -`(match_scratch:M N CONSTRAINT)' - This expression is also a placeholder for operand number N and - indicates that operand must be a `scratch' or `reg' expression. - - When matching patterns, this is completely equivalent to - - (match_operand:M N "scratch_operand" PRED) - - but, when generating RTL, it produces a (`scratch':M) expression. - - If the last few expressions in a `parallel' are `clobber' - expressions whose operands are either a hard register or - `match_scratch', the combiner can add them when necessary. *Note - Side Effects::. - -`(match_dup N)' - This expression is also a placeholder for operand number N. It is - used when the operand needs to appear more than once in the insn. - - In construction, `match_dup' acts just like `match_operand': the - operand is substituted into the insn being constructed. But in - matching, `match_dup' behaves differently. It assumes that operand - number N has already been determined by a `match_operand' - appearing earlier in the recognition template, and it matches only - an identical-looking expression. - -`(match_operator:M N PREDICATE [OPERANDS...])' - This pattern is a kind of placeholder for a variable RTL expression - code. - - When constructing an insn, it stands for an RTL expression whose - expression code is taken from that of operand N, and whose - operands are constructed from the patterns OPERANDS. - - When matching an expression, it matches an expression if the - function PREDICATE returns nonzero on that expression *and* the - patterns OPERANDS match the operands of the expression. - - Suppose that the function `commutative_operator' is defined as - follows, to match any expression whose operator is one of the - commutative arithmetic operators of RTL and whose mode is MODE: - - int - commutative_operator (x, mode) - rtx x; - enum machine_mode mode; - { - enum rtx_code code = GET_CODE (x); - if (GET_MODE (x) != mode) - return 0; - return (GET_RTX_CLASS (code) == 'c' - || code == EQ || code == NE); - } - - Then the following pattern will match any RTL expression consisting - of a commutative operator applied to two general operands: - - (match_operator:SI 3 "commutative_operator" - [(match_operand:SI 1 "general_operand" "g") - (match_operand:SI 2 "general_operand" "g")]) - - Here the vector `[OPERANDS...]' contains two patterns because the - expressions to be matched all contain two operands. - - When this pattern does match, the two operands of the commutative - operator are recorded as operands 1 and 2 of the insn. (This is - done by the two instances of `match_operand'.) Operand 3 of the - insn will be the entire commutative expression: use `GET_CODE - (operands[3])' to see which commutative operator was used. - - The machine mode M of `match_operator' works like that of - `match_operand': it is passed as the second argument to the - predicate function, and that function is solely responsible for - deciding whether the expression to be matched "has" that mode. - - When constructing an insn, argument 3 of the gen-function will - specify the operation (i.e. the expression code) for the - expression to be made. It should be an RTL expression, whose - expression code is copied into a new expression whose operands are - arguments 1 and 2 of the gen-function. The subexpressions of - argument 3 are not used; only its expression code matters. - - When `match_operator' is used in a pattern for matching an insn, - it usually best if the operand number of the `match_operator' is - higher than that of the actual operands of the insn. This improves - register allocation because the register allocator often looks at - operands 1 and 2 of insns to see if it can do register tying. - - There is no way to specify constraints in `match_operator'. The - operand of the insn which corresponds to the `match_operator' - never has any constraints because it is never reloaded as a whole. - However, if parts of its OPERANDS are matched by `match_operand' - patterns, those parts may have constraints of their own. - -`(match_op_dup:M N[OPERANDS...])' - Like `match_dup', except that it applies to operators instead of - operands. When constructing an insn, operand number N will be - substituted at this point. But in matching, `match_op_dup' behaves - differently. It assumes that operand number N has already been - determined by a `match_operator' appearing earlier in the - recognition template, and it matches only an identical-looking - expression. - -`(match_parallel N PREDICATE [SUBPAT...])' - This pattern is a placeholder for an insn that consists of a - `parallel' expression with a variable number of elements. This - expression should only appear at the top level of an insn pattern. - - When constructing an insn, operand number N will be substituted at - this point. When matching an insn, it matches if the body of the - insn is a `parallel' expression with at least as many elements as - the vector of SUBPAT expressions in the `match_parallel', if each - SUBPAT matches the corresponding element of the `parallel', *and* - the function PREDICATE returns nonzero on the `parallel' that is - the body of the insn. It is the responsibility of the predicate - to validate elements of the `parallel' beyond those listed in the - `match_parallel'. - - A typical use of `match_parallel' is to match load and store - multiple expressions, which can contains a variable number of - elements in a `parallel'. For example, - - (define_insn "" - [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "gpc_reg_operand" "=r") - (match_operand:SI 2 "memory_operand" "m")) - (use (reg:SI 179)) - (clobber (reg:SI 179))])] - "" - "loadm 0,0,%1,%2") - - This example comes from `a29k.md'. The function - `load_multiple_operations' is defined in `a29k.c' and checks that - subsequent elements in the `parallel' are the same as the `set' in - the pattern, except that they are referencing subsequent registers - and memory locations. - - An insn that matches this pattern might look like: - - (parallel - [(set (reg:SI 20) (mem:SI (reg:SI 100))) - (use (reg:SI 179)) - (clobber (reg:SI 179)) - (set (reg:SI 21) - (mem:SI (plus:SI (reg:SI 100) - (const_int 4)))) - (set (reg:SI 22) - (mem:SI (plus:SI (reg:SI 100) - (const_int 8))))]) - -`(match_par_dup N [SUBPAT...])' - Like `match_op_dup', but for `match_parallel' instead of - `match_operator'. - -`(address (match_operand:M N "address_operand" ""))' - This complex of expressions is a placeholder for an operand number - N in a "load address" instruction: an operand which specifies a - memory location in the usual way, but for which the actual operand - value used is the address of the location, not the contents of the - location. - - `address' expressions never appear in RTL code, only in machine - descriptions. And they are used only in machine descriptions that - do not use the operand constraint feature. When operand - constraints are in use, the letter `p' in the constraint serves - this purpose. - - M is the machine mode of the *memory location being addressed*, - not the machine mode of the address itself. That mode is always - the same on a given target machine (it is `Pmode', which normally - is `SImode'), so there is no point in mentioning it; thus, no - machine mode is written in the `address' expression. If some day - support is added for machines in which addresses of different - kinds of objects appear differently or are used differently (such - as the PDP-10), different formats would perhaps need different - machine modes and these modes might be written in the `address' - expression. - - -File: gcc.info, Node: Output Template, Next: Output Statement, Prev: RTL Template, Up: Machine Desc - -Output Templates and Operand Substitution -========================================= +Registers and Memory +==================== - The "output template" is a string which specifies how to output the -assembler code for an instruction pattern. Most of the template is a -fixed string which is output literally. The character `%' is used to -specify where to substitute an operand; it can also be used to identify -places where different variants of the assembler require different -syntax. - - In the simplest case, a `%' followed by a digit N says to output -operand N at that point in the string. - - `%' followed by a letter and a digit says to output an operand in an -alternate fashion. Four letters have standard, built-in meanings -described below. The machine description macro `PRINT_OPERAND' can -define additional letters with nonstandard meanings. - - `%cDIGIT' can be used to substitute an operand that is a constant -value without the syntax that normally indicates an immediate operand. - - `%nDIGIT' is like `%cDIGIT' except that the value of the constant is -negated before printing. - - `%aDIGIT' can be used to substitute an operand as if it were a -memory reference, with the actual operand treated as the address. This -may be useful when outputting a "load address" instruction, because -often the assembler syntax for such an instruction requires you to -write the operand as if it were a memory reference. - - `%lDIGIT' is used to substitute a `label_ref' into a jump -instruction. - - `%=' outputs a number which is unique to each instruction in the -entire compilation. This is useful for making local labels to be -referred to more than once in a single template that generates multiple -assembler instructions. - - `%' followed by a punctuation character specifies a substitution that -does not use an operand. Only one case is standard: `%%' outputs a `%' -into the assembler code. Other nonstandard cases can be defined in the -`PRINT_OPERAND' macro. You must also define which punctuation -characters are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. - - The template may generate multiple assembler instructions. Write -the text for the instructions, with `\;' between them. - - When the RTL contains two operands which are required by constraint -to match each other, the output template must refer only to the -lower-numbered operand. Matching operands are not always identical, -and the rest of the compiler arranges to put the proper RTL expression -for printing into the lower-numbered operand. - - One use of nonstandard letters or punctuation following `%' is to -distinguish between different assembler languages for the same machine; -for example, Motorola syntax versus MIT syntax for the 68000. Motorola -syntax requires periods in most opcode names, while MIT syntax does -not. For example, the opcode `movel' in MIT syntax is `move.l' in -Motorola syntax. The same file of patterns is used for both kinds of -output syntax, but the character sequence `%.' is used in each place -where Motorola syntax wants a period. The `PRINT_OPERAND' macro for -Motorola syntax defines the sequence to output a period; the macro for -MIT syntax defines it to do nothing. - - As a special case, a template consisting of the single character `#' -instructs the compiler to first split the insn, and then output the -resulting instructions separately. This helps eliminate redundancy in -the output templates. If you have a `define_insn' that needs to emit -multiple assembler instructions, and there is an matching `define_split' -already defined, then you can simply use `#' as the output template -instead of writing an output template that emits the multiple assembler -instructions. + Here are the RTL expression types for describing access to machine +registers and to main memory. - -File: gcc.info, Node: Output Statement, Next: Constraints, Prev: Output Template, Up: Machine Desc - -C Statements for Assembler Output -================================= +`(reg:M N)' + For small values of the integer N (those that are less than + `FIRST_PSEUDO_REGISTER'), this stands for a reference to machine + register number N: a "hard register". For larger values of N, it + stands for a temporary value or "pseudo register". The compiler's + strategy is to generate code assuming an unlimited number of such + pseudo registers, and later convert them into hard registers or + into memory references. + + M is the machine mode of the reference. It is necessary because + machines can generally refer to each register in more than one + mode. For example, a register may contain a full word but there + may be instructions to refer to it as a half word or as a single + byte, as well as instructions to refer to it as a floating point + number of various precisions. + + Even for a register that the machine can access in only one mode, + the mode must always be specified. + + The symbol `FIRST_PSEUDO_REGISTER' is defined by the machine + description, since the number of hard registers on the machine is + an invariant characteristic of the machine. Note, however, that + not all of the machine registers must be general registers. All + the machine registers that can be used for storage of data are + given hard register numbers, even those that can be used only in + certain instructions or can hold only certain types of data. + + A hard register may be accessed in various modes throughout one + function, but each pseudo register is given a natural mode and is + accessed only in that mode. When it is necessary to describe an + access to a pseudo register using a nonnatural mode, a `subreg' + expression is used. + + A `reg' expression with a machine mode that specifies more than + one word of data may actually stand for several consecutive + registers. If in addition the register number specifies a + hardware register, then it actually represents several consecutive + hardware registers starting with the specified one. + + Each pseudo register number used in a function's RTL code is + represented by a unique `reg' expression. + + Some pseudo register numbers, those within the range of + `FIRST_VIRTUAL_REGISTER' to `LAST_VIRTUAL_REGISTER' only appear + during the RTL generation phase and are eliminated before the + optimization phases. These represent locations in the stack frame + that cannot be determined until RTL generation for the function + has been completed. The following virtual register numbers are + defined: + + `VIRTUAL_INCOMING_ARGS_REGNUM' + This points to the first word of the incoming arguments + passed on the stack. Normally these arguments are placed + there by the caller, but the callee may have pushed some + arguments that were previously passed in registers. + + When RTL generation is complete, this virtual register is + replaced by the sum of the register given by + `ARG_POINTER_REGNUM' and the value of `FIRST_PARM_OFFSET'. + + `VIRTUAL_STACK_VARS_REGNUM' + If `FRAME_GROWS_DOWNWARD' is defined, this points to + immediately above the first variable on the stack. + Otherwise, it points to the first variable on the stack. + + `VIRTUAL_STACK_VARS_REGNUM' is replaced with the sum of the + register given by `FRAME_POINTER_REGNUM' and the value + `STARTING_FRAME_OFFSET'. + + `VIRTUAL_STACK_DYNAMIC_REGNUM' + This points to the location of dynamically allocated memory + on the stack immediately after the stack pointer has been + adjusted by the amount of memory desired. + + This virtual register is replaced by the sum of the register + given by `STACK_POINTER_REGNUM' and the value + `STACK_DYNAMIC_OFFSET'. + + `VIRTUAL_OUTGOING_ARGS_REGNUM' + This points to the location in the stack at which outgoing + arguments should be written when the stack is pre-pushed + (arguments pushed using push insns should always use + `STACK_POINTER_REGNUM'). + + This virtual register is replaced by the sum of the register + given by `STACK_POINTER_REGNUM' and the value + `STACK_POINTER_OFFSET'. + +`(subreg:M REG WORDNUM)' + `subreg' expressions are used to refer to a register in a machine + mode other than its natural one, or to refer to one register of a + multi-word `reg' that actually refers to several registers. + + Each pseudo-register has a natural mode. If it is necessary to + operate on it in a different mode--for example, to perform a + fullword move instruction on a pseudo-register that contains a + single byte--the pseudo-register must be enclosed in a `subreg'. + In such a case, WORDNUM is zero. + + Usually M is at least as narrow as the mode of REG, in which case + it is restricting consideration to only the bits of REG that are + in M. + + Sometimes M is wider than the mode of REG. These `subreg' + expressions are often called "paradoxical". They are used in + cases where we want to refer to an object in a wider mode but do + not care what value the additional bits have. The reload pass + ensures that paradoxical references are only made to hard + registers. - Often a single fixed template string cannot produce correct and -efficient assembler code for all the cases that are recognized by a -single instruction pattern. For example, the opcodes may depend on the -kinds of operands; or some unfortunate combinations of operands may -require extra machine instructions. - - If the output control string starts with a `@', then it is actually -a series of templates, each on a separate line. (Blank lines and -leading spaces and tabs are ignored.) The templates correspond to the -pattern's constraint alternatives (*note Multi-Alternative::.). For -example, if a target machine has a two-address add instruction `addr' -to add into a register and another `addm' to add a register to memory, -you might write this pattern: - - (define_insn "addsi3" - [(set (match_operand:SI 0 "general_operand" "=r,m") - (plus:SI (match_operand:SI 1 "general_operand" "0,0") - (match_operand:SI 2 "general_operand" "g,r")))] - "" - "@ - addr %2,%0 - addm %2,%0") - - If the output control string starts with a `*', then it is not an -output template but rather a piece of C program that should compute a -template. It should execute a `return' statement to return the -template-string you want. Most such templates use C string literals, -which require doublequote characters to delimit them. To include these -doublequote characters in the string, prefix each one with `\'. - - The operands may be found in the array `operands', whose C data type -is `rtx []'. - - It is very common to select different ways of generating assembler -code based on whether an immediate operand is within a certain range. -Be careful when doing this, because the result of `INTVAL' is an -integer on the host machine. If the host machine has more bits in an -`int' than the target machine has in the mode in which the constant -will be used, then some of the bits you get from `INTVAL' will be -superfluous. For proper results, you must carefully disregard the -values of those bits. - - It is possible to output an assembler instruction and then go on to -output or compute more of them, using the subroutine `output_asm_insn'. -This receives two arguments: a template-string and a vector of -operands. The vector may be `operands', or it may be another array of -`rtx' that you declare locally and initialize yourself. - - When an insn pattern has multiple alternatives in its constraints, -often the appearance of the assembler code is determined mostly by -which alternative was matched. When this is so, the C code can test -the variable `which_alternative', which is the ordinal number of the -alternative that was actually satisfied (0 for the first, 1 for the -second alternative, etc.). - - For example, suppose there are two opcodes for storing zero, `clrreg' -for registers and `clrmem' for memory locations. Here is how a pattern -could use `which_alternative' to choose between them: - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "=r,m") - (const_int 0))] - "" - "* - return (which_alternative == 0 - ? \"clrreg %0\" : \"clrmem %0\"); - ") - - The example above, where the assembler code to generate was *solely* -determined by the alternative, could also have been specified as -follows, having the output control string start with a `@': - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "=r,m") - (const_int 0))] - "" - "@ - clrreg %0 - clrmem %0") + The other use of `subreg' is to extract the individual registers of + a multi-register value. Machine modes such as `DImode' and + `TImode' can indicate values longer than a word, values which + usually require two or more consecutive registers. To access one + of the registers, use a `subreg' with mode `SImode' and a WORDNUM + that says which register. + + Storing in a non-paradoxical `subreg' has undefined results for + bits belonging to the same word as the `subreg'. This laxity makes + it easier to generate efficient code for such instructions. To + represent an instruction that preserves all the bits outside of + those in the `subreg', use `strict_low_part' around the `subreg'. + + The compilation parameter `WORDS_BIG_ENDIAN', if set to 1, says + that word number zero is the most significant part; otherwise, it + is the least significant part. + + Between the combiner pass and the reload pass, it is possible to + have a paradoxical `subreg' which contains a `mem' instead of a + `reg' as its first operand. After the reload pass, it is also + possible to have a non-paradoxical `subreg' which contains a + `mem'; this usually occurs when the `mem' is a stack slot which + replaced a pseudo register. + + Note that it is not valid to access a `DFmode' value in `SFmode' + using a `subreg'. On some machines the most significant part of a + `DFmode' value does not have the same format as a single-precision + floating value. + + It is also not valid to access a single word of a multi-word value + in a hard register when less registers can hold the value than + would be expected from its size. For example, some 32-bit + machines have floating-point registers that can hold an entire + `DFmode' value. If register 10 were such a register `(subreg:SI + (reg:DF 10) 1)' would be invalid because there is no way to + convert that reference to a single machine register. The reload + pass prevents `subreg' expressions such as these from being formed. + + The first operand of a `subreg' expression is customarily accessed + with the `SUBREG_REG' macro and the second operand is customarily + accessed with the `SUBREG_WORD' macro. + +`(scratch:M)' + This represents a scratch register that will be required for the + execution of a single instruction and not used subsequently. It is + converted into a `reg' by either the local register allocator or + the reload pass. + + `scratch' is usually present inside a `clobber' operation (*note + Side Effects::.). + +`(cc0)' + This refers to the machine's condition code register. It has no + operands and may not have a machine mode. There are two ways to + use it: + + * To stand for a complete set of condition code flags. This is + best on most machines, where each comparison sets the entire + series of flags. + + With this technique, `(cc0)' may be validly used in only two + contexts: as the destination of an assignment (in test and + compare instructions) and in comparison operators comparing + against zero (`const_int' with value zero; that is to say, + `const0_rtx'). + + * To stand for a single flag that is the result of a single + condition. This is useful on machines that have only a + single flag bit, and in which comparison instructions must + specify the condition to test. + + With this technique, `(cc0)' may be validly used in only two + contexts: as the destination of an assignment (in test and + compare instructions) where the source is a comparison + operator, and as the first operand of `if_then_else' (in a + conditional branch). + + There is only one expression object of code `cc0'; it is the value + of the variable `cc0_rtx'. Any attempt to create an expression of + code `cc0' will return `cc0_rtx'. + + Instructions can set the condition code implicitly. On many + machines, nearly all instructions set the condition code based on + the value that they compute or store. It is not necessary to + record these actions explicitly in the RTL because the machine + description includes a prescription for recognizing the + instructions that do so (by means of the macro + `NOTICE_UPDATE_CC'). *Note Condition Code::. Only instructions + whose sole purpose is to set the condition code, and instructions + that use the condition code, need mention `(cc0)'. + + On some machines, the condition code register is given a register + number and a `reg' is used instead of `(cc0)'. This is usually the + preferable approach if only a small subset of instructions modify + the condition code. Other machines store condition codes in + general registers; in such cases a pseudo register should be used. + + Some machines, such as the Sparc and RS/6000, have two sets of + arithmetic instructions, one that sets and one that does not set + the condition code. This is best handled by normally generating + the instruction that does not set the condition code, and making a + pattern that both performs the arithmetic and sets the condition + code register (which would not be `(cc0)' in this case). For + examples, search for `addcc' and `andcc' in `sparc.md'. + +`(pc)' + This represents the machine's program counter. It has no operands + and may not have a machine mode. `(pc)' may be validly used only + in certain specific contexts in jump instructions. + + There is only one expression object of code `pc'; it is the value + of the variable `pc_rtx'. Any attempt to create an expression of + code `pc' will return `pc_rtx'. + + All instructions that do not jump alter the program counter + implicitly by incrementing it, but there is no need to mention + this in the RTL. + +`(mem:M ADDR)' + This RTX represents a reference to main memory at an address + represented by the expression ADDR. M specifies how large a unit + of memory is accessed.  -File: gcc.info, Node: Constraints, Next: Standard Names, Prev: Output Statement, Up: Machine Desc +File: gcc.info, Node: Arithmetic, Next: Comparisons, Prev: Regs and Memory, Up: RTL -Operand Constraints -=================== +RTL Expressions for Arithmetic +============================== - Each `match_operand' in an instruction pattern can specify a -constraint for the type of operands allowed. Constraints can say -whether an operand may be in a register, and which kinds of register; -whether the operand can be a memory reference, and which kinds of -address; whether the operand may be an immediate constant, and which -possible values it may have. Constraints can also require two operands -to match. - -* Menu: - -* Simple Constraints:: Basic use of constraints. -* Multi-Alternative:: When an insn has two alternative constraint-patterns. -* Class Preferences:: Constraints guide which hard register to put things in. -* Modifiers:: More precise control over effects of constraints. -* Machine Constraints:: Existing constraints for some particular machines. -* No Constraints:: Describing a clean machine without constraints. + Unless otherwise specified, all the operands of arithmetic +expressions must be valid for mode M. An operand is valid for mode M +if it has mode M, or if it is a `const_int' or `const_double' and M is +a mode of class `MODE_INT'. + + For commutative binary operations, constants should be placed in the +second operand. + +`(plus:M X Y)' + Represents the sum of the values represented by X and Y carried + out in machine mode M. + +`(lo_sum:M X Y)' + Like `plus', except that it represents that sum of X and the + low-order bits of Y. The number of low order bits is + machine-dependent but is normally the number of bits in a `Pmode' + item minus the number of bits set by the `high' code (*note + Constants::.). + + M should be `Pmode'. + +`(minus:M X Y)' + Like `plus' but represents subtraction. + +`(compare:M X Y)' + Represents the result of subtracting Y from X for purposes of + comparison. The result is computed without overflow, as if with + infinite precision. + + Of course, machines can't really subtract with infinite precision. + However, they can pretend to do so when only the sign of the + result will be used, which is the case when the result is stored + in the condition code. And that is the only way this kind of + expression may validly be used: as a value to be stored in the + condition codes. + + The mode M is not related to the modes of X and Y, but instead is + the mode of the condition code value. If `(cc0)' is used, it is + `VOIDmode'. Otherwise it is some mode in class `MODE_CC', often + `CCmode'. *Note Condition Code::. + + Normally, X and Y must have the same mode. Otherwise, `compare' + is valid only if the mode of X is in class `MODE_INT' and Y is a + `const_int' or `const_double' with mode `VOIDmode'. The mode of X + determines what mode the comparison is to be done in; thus it must + not be `VOIDmode'. + + If one of the operands is a constant, it should be placed in the + second operand and the comparison code adjusted as appropriate. + + A `compare' specifying two `VOIDmode' constants is not valid since + there is no way to know in what mode the comparison is to be + performed; the comparison must either be folded during the + compilation or the first operand must be loaded into a register + while its mode is still known. + +`(neg:M X)' + Represents the negation (subtraction from zero) of the value + represented by X, carried out in mode M. + +`(mult:M X Y)' + Represents the signed product of the values represented by X and Y + carried out in machine mode M. + + Some machines support a multiplication that generates a product + wider than the operands. Write the pattern for this as + + (mult:M (sign_extend:M X) (sign_extend:M Y)) + + where M is wider than the modes of X and Y, which need not be the + same. + + Write patterns for unsigned widening multiplication similarly using + `zero_extend'. + +`(div:M X Y)' + Represents the quotient in signed division of X by Y, carried out + in machine mode M. If M is a floating point mode, it represents + the exact quotient; otherwise, the integerized quotient. + + Some machines have division instructions in which the operands and + quotient widths are not all the same; you should represent such + instructions using `truncate' and `sign_extend' as in, + + (truncate:M1 (div:M2 X (sign_extend:M2 Y))) + +`(udiv:M X Y)' + Like `div' but represents unsigned division. + +`(mod:M X Y)' +`(umod:M X Y)' + Like `div' and `udiv' but represent the remainder instead of the + quotient. + +`(smin:M X Y)' +`(smax:M X Y)' + Represents the smaller (for `smin') or larger (for `smax') of X + and Y, interpreted as signed integers in mode M. + +`(umin:M X Y)' +`(umax:M X Y)' + Like `smin' and `smax', but the values are interpreted as unsigned + integers. + +`(not:M X)' + Represents the bitwise complement of the value represented by X, + carried out in mode M, which must be a fixed-point machine mode. + +`(and:M X Y)' + Represents the bitwise logical-and of the values represented by X + and Y, carried out in machine mode M, which must be a fixed-point + machine mode. + +`(ior:M X Y)' + Represents the bitwise inclusive-or of the values represented by X + and Y, carried out in machine mode M, which must be a fixed-point + mode. + +`(xor:M X Y)' + Represents the bitwise exclusive-or of the values represented by X + and Y, carried out in machine mode M, which must be a fixed-point + mode. + +`(ashift:M X C)' + Represents the result of arithmetically shifting X left by C + places. X have mode M, a fixed-point machine mode. C be a + fixed-point mode or be a constant with mode `VOIDmode'; which mode + is determined by the mode called for in the machine description + entry for the left-shift instruction. For example, on the Vax, + the mode of C is `QImode' regardless of M. + +`(lshiftrt:M X C)' +`(ashiftrt:M X C)' + Like `ashift' but for right shift. Unlike the case for left shift, + these two operations are distinct. + +`(rotate:M X C)' +`(rotatert:M X C)' + Similar but represent left and right rotate. If C is a constant, + use `rotate'. + +`(abs:M X)' + Represents the absolute value of X, computed in mode M. + +`(sqrt:M X)' + Represents the square root of X, computed in mode M. Most often M + will be a floating point mode. + +`(ffs:M X)' + Represents one plus the index of the least significant 1-bit in X, + represented as an integer of mode M. (The value is zero if X is + zero.) The mode of X need not be M; depending on the target + machine, various mode combinations may be valid.  -File: gcc.info, Node: Simple Constraints, Next: Multi-Alternative, Up: Constraints +File: gcc.info, Node: Comparisons, Next: Bit Fields, Prev: Arithmetic, Up: RTL -Simple Constraints ------------------- +Comparison Operations +===================== - The simplest kind of constraint is a string full of letters, each of -which describes one kind of operand that is permitted. Here are the -letters that are allowed: - -`m' - A memory operand is allowed, with any kind of address that the - machine supports in general. - -`o' - A memory operand is allowed, but only if the address is - "offsettable". This means that adding a small integer (actually, - the width in bytes of the operand, as determined by its machine - mode) may be added to the address and the result is also a valid - memory address. - - For example, an address which is constant is offsettable; so is an - address that is the sum of a register and a constant (as long as a - slightly larger constant is also within the range of - address-offsets supported by the machine); but an autoincrement or - autodecrement address is not offsettable. More complicated - indirect/indexed addresses may or may not be offsettable depending - on the other addressing modes that the machine supports. - - Note that in an output operand which can be matched by another - operand, the constraint letter `o' is valid only when accompanied - by both `<' (if the target machine has predecrement addressing) - and `>' (if the target machine has preincrement addressing). - -`V' - A memory operand that is not offsettable. In other words, - anything that would fit the `m' constraint but not the `o' - constraint. - -`<' - A memory operand with autodecrement addressing (either - predecrement or postdecrement) is allowed. - -`>' - A memory operand with autoincrement addressing (either - preincrement or postincrement) is allowed. - -`r' - A register operand is allowed provided that it is in a general - register. - -`d', `a', `f', ... - Other letters can be defined in machine-dependent fashion to stand - for particular classes of registers. `d', `a' and `f' are defined - on the 68000/68020 to stand for data, address and floating point - registers. + Comparison operators test a relation on two operands and are +considered to represent a machine-dependent nonzero value described by, +but not necessarily equal to, `STORE_FLAG_VALUE' (*note Misc::.) if the +relation holds, or zero if it does not. The mode of the comparison +operation is independent of the mode of the data being compared. If +the comparison operation is being tested (e.g., the first operand of an +`if_then_else'), the mode must be `VOIDmode'. If the comparison +operation is producing data to be stored in some variable, the mode +must be in class `MODE_INT'. All comparison operations producing data +must use the same mode, which is machine-specific. + + There are two ways that comparison operations may be used. The +comparison operators may be used to compare the condition codes `(cc0)' +against zero, as in `(eq (cc0) (const_int 0))'. Such a construct +actually refers to the result of the preceding instruction in which the +condition codes were set. The instructing setting the condition code +must be adjacent to the instruction using the condition code; only +`note' insns may separate them. + + Alternatively, a comparison operation may directly compare two data +objects. The mode of the comparison is determined by the operands; they +must both be valid for a common machine mode. A comparison with both +operands constant would be invalid as the machine mode could not be +deduced from it, but such a comparison should never exist in RTL due to +constant folding. + + In the example above, if `(cc0)' were last set to `(compare X Y)', +the comparison operation is identical to `(eq X Y)'. Usually only one +style of comparisons is supported on a particular machine, but the +combine pass will try to merge the operations to produce the `eq' shown +in case it exists in the context of the particular insn involved. + + Inequality comparisons come in two flavors, signed and unsigned. +Thus, there are distinct expression codes `gt' and `gtu' for signed and +unsigned greater-than. These can produce different results for the same +pair of integer values: for example, 1 is signed greater-than -1 but not +unsigned greater-than, because -1 when regarded as unsigned is actually +`0xffffffff' which is greater than 1. + + The signed comparisons are also used for floating point values. +Floating point comparisons are distinguished by the machine modes of +the operands. + +`(eq:M X Y)' + 1 if the values represented by X and Y are equal, otherwise 0. + +`(ne:M X Y)' + 1 if the values represented by X and Y are not equal, otherwise 0. + +`(gt:M X Y)' + 1 if the X is greater than Y. If they are fixed-point, the + comparison is done in a signed sense. + +`(gtu:M X Y)' + Like `gt' but does unsigned comparison, on fixed-point numbers + only. + +`(lt:M X Y)' +`(ltu:M X Y)' + Like `gt' and `gtu' but test for "less than". + +`(ge:M X Y)' +`(geu:M X Y)' + Like `gt' and `gtu' but test for "greater than or equal". + +`(le:M X Y)' +`(leu:M X Y)' + Like `gt' and `gtu' but test for "less than or equal". + +`(if_then_else COND THEN ELSE)' + This is not a comparison operation but is listed here because it is + always used in conjunction with a comparison operation. To be + precise, COND is a comparison expression. This expression + represents a choice, according to COND, between the value + represented by THEN and the one represented by ELSE. + + On most machines, `if_then_else' expressions are valid only to + express conditional jumps. + +`(cond [TEST1 VALUE1 TEST2 VALUE2 ...] DEFAULT)' + Similar to `if_then_else', but more general. Each of TEST1, + TEST2, ... is performed in turn. The result of this expression is + the VALUE corresponding to the first non-zero test, or DEFAULT if + none of the tests are non-zero expressions. -`i' - An immediate integer operand (one with constant value) is allowed. - This includes symbolic constants whose values will be known only at - assembly time. - -`n' - An immediate integer operand with a known numeric value is allowed. - Many systems cannot support assembly-time constants for operands - less than a word wide. Constraints for these operands should use - `n' rather than `i'. - -`I', `J', `K', ... `P' - Other letters in the range `I' through `P' may be defined in a - machine-dependent fashion to permit immediate integer operands with - explicit integer values in specified ranges. For example, on the - 68000, `I' is defined to stand for the range of values 1 to 8. - This is the range permitted as a shift count in the shift - instructions. - -`E' - An immediate floating operand (expression code `const_double') is - allowed, but only if the target floating point format is the same - as that of the host machine (on which the compiler is running). - -`F' - An immediate floating operand (expression code `const_double') is - allowed. - -`G', `H' - `G' and `H' may be defined in a machine-dependent fashion to - permit immediate floating operands in particular ranges of values. - -`s' - An immediate integer operand whose value is not an explicit - integer is allowed. - - This might appear strange; if an insn allows a constant operand - with a value not known at compile time, it certainly must allow - any known value. So why use `s' instead of `i'? Sometimes it - allows better code to be generated. - - For example, on the 68000 in a fullword instruction it is possible - to use an immediate operand; but if the immediate value is between - -128 and 127, better code results from loading the value into a - register and using the register. This is because the load into - the register can be done with a `moveq' instruction. We arrange - for this to happen by defining the letter `K' to mean "any integer - outside the range -128 to 127", and then specifying `Ks' in the - operand constraints. - -`g' - Any register, memory or immediate integer operand is allowed, - except for registers that are not general registers. - -`X' - Any operand whatsoever is allowed, even if it does not satisfy - `general_operand'. This is normally used in the constraint of a - `match_scratch' when certain alternatives will not actually - require a scratch register. - -`0', `1', `2', ... `9' - An operand that matches the specified operand number is allowed. - If a digit is used together with letters within the same - alternative, the digit should come last. - - This is called a "matching constraint" and what it really means is - that the assembler has only a single operand that fills two roles - considered separate in the RTL insn. For example, an add insn has - two input operands and one output operand in the RTL, but on most - CISC machines an add instruction really has only two operands, one - of them an input-output operand: - - addl #35,r12 - - Matching constraints are used in these circumstances. More - precisely, the two operands that match must include one input-only - operand and one output-only operand. Moreover, the digit must be a - smaller number than the number of the operand that uses it in the - constraint. - - For operands to match in a particular case usually means that they - are identical-looking RTL expressions. But in a few special cases - specific kinds of dissimilarity are allowed. For example, `*x' as - an input operand will match `*x++' as an output operand. For - proper results in such cases, the output template should always - use the output-operand's number when printing the operand. - -`p' - An operand that is a valid memory address is allowed. This is for - "load address" and "push address" instructions. - - `p' in the constraint must be accompanied by `address_operand' as - the predicate in the `match_operand'. This predicate interprets - the mode specified in the `match_operand' as the mode of the memory - reference for which the address would be valid. - -`Q', `R', `S', ... `U' - Letters in the range `Q' through `U' may be defined in a - machine-dependent fashion to stand for arbitrary operand types. - The machine description macro `EXTRA_CONSTRAINT' is passed the - operand as its first argument and the constraint letter as its - second operand. - - A typical use for this would be to distinguish certain types of - memory references that affect other insn operands. - - Do not define these constraint letters to accept register - references (`reg'); the reload pass does not expect this and would - not handle it properly. - - In order to have valid assembler code, each operand must satisfy its -constraint. But a failure to do so does not prevent the pattern from -applying to an insn. Instead, it directs the compiler to modify the -code so that the constraint will be satisfied. Usually this is done by -copying an operand into a register. - - Contrast, therefore, the two instruction patterns that follow: - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "=r") - (plus:SI (match_dup 0) - (match_operand:SI 1 "general_operand" "r")))] - "" - "...") - -which has two operands, one of which must appear in two places, and - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "=r") - (plus:SI (match_operand:SI 1 "general_operand" "0") - (match_operand:SI 2 "general_operand" "r")))] - "" - "...") - -which has three operands, two of which are required by a constraint to -be identical. If we are considering an insn of the form - - (insn N PREV NEXT - (set (reg:SI 3) - (plus:SI (reg:SI 6) (reg:SI 109))) - ...) - -the first pattern would not apply at all, because this insn does not -contain two identical subexpressions in the right place. The pattern -would say, "That does not look like an add instruction; try other -patterns." The second pattern would say, "Yes, that's an add -instruction, but there is something wrong with it." It would direct -the reload pass of the compiler to generate additional insns to make -the constraint true. The results might look like this: - - (insn N2 PREV N - (set (reg:SI 3) (reg:SI 6)) - ...) - - (insn N N2 NEXT - (set (reg:SI 3) - (plus:SI (reg:SI 3) (reg:SI 109))) - ...) - - It is up to you to make sure that each operand, in each pattern, has -constraints that can handle any RTL expression that could be present for -that operand. (When multiple alternatives are in use, each pattern -must, for each possible combination of operand expressions, have at -least one alternative which can handle that combination of operands.) -The constraints don't need to *allow* any possible operand--when this is -the case, they do not constrain--but they must at least point the way to -reloading any possible operand so that it will fit. - - * If the constraint accepts whatever operands the predicate permits, - there is no problem: reloading is never necessary for this operand. - - For example, an operand whose constraints permit everything except - registers is safe provided its predicate rejects registers. - - An operand whose predicate accepts only constant values is safe - provided its constraints include the letter `i'. If any possible - constant value is accepted, then nothing less than `i' will do; if - the predicate is more selective, then the constraints may also be - more selective. - - * Any operand expression can be reloaded by copying it into a - register. So if an operand's constraints allow some kind of - register, it is certain to be safe. It need not permit all - classes of registers; the compiler knows how to copy a register - into another register of the proper class in order to make an - instruction valid. - - * A nonoffsettable memory reference can be reloaded by copying the - address into a register. So if the constraint uses the letter - `o', all memory references are taken care of. - - * A constant operand can be reloaded by allocating space in memory to - hold it as preinitialized data. Then the memory reference can be - used in place of the constant. So if the constraint uses the - letters `o' or `m', constant operands are not a problem. - - * If the constraint permits a constant and a pseudo register used in - an insn was not allocated to a hard register and is equivalent to - a constant, the register will be replaced with the constant. If - the predicate does not permit a constant and the insn is - re-recognized for some reason, the compiler will crash. Thus the - predicate must always recognize any objects allowed by the - constraint. - - If the operand's predicate can recognize registers, but the -constraint does not permit them, it can make the compiler crash. When -this operand happens to be a register, the reload pass will be stymied, -because it does not know how to copy a register temporarily into memory. + This is currently not valid for instruction patterns and is + supported only for insn attributes. *Note Insn Attributes::.  -File: gcc.info, Node: Multi-Alternative, Next: Class Preferences, Prev: Simple Constraints, Up: Constraints +File: gcc.info, Node: Bit Fields, Next: Conversions, Prev: Comparisons, Up: RTL -Multiple Alternative Constraints --------------------------------- +Bit Fields +========== - Sometimes a single instruction has multiple alternative sets of -possible operands. For example, on the 68000, a logical-or instruction -can combine register or an immediate value into memory, or it can -combine any kind of operand into a register; but it cannot combine one -memory location into another. - - These constraints are represented as multiple alternatives. An -alternative can be described by a series of letters for each operand. -The overall constraint for an operand is made from the letters for this -operand from the first alternative, a comma, the letters for this -operand from the second alternative, a comma, and so on until the last -alternative. Here is how it is done for fullword logical-or on the -68000: - - (define_insn "iorsi3" - [(set (match_operand:SI 0 "general_operand" "=m,d") - (ior:SI (match_operand:SI 1 "general_operand" "%0,0") - (match_operand:SI 2 "general_operand" "dKs,dmKs")))] - ...) - - The first alternative has `m' (memory) for operand 0, `0' for -operand 1 (meaning it must match operand 0), and `dKs' for operand 2. -The second alternative has `d' (data register) for operand 0, `0' for -operand 1, and `dmKs' for operand 2. The `=' and `%' in the -constraints apply to all the alternatives; their meaning is explained -in the next section (*note Class Preferences::.). - - If all the operands fit any one alternative, the instruction is -valid. Otherwise, for each alternative, the compiler counts how many -instructions must be added to copy the operands so that that -alternative applies. The alternative requiring the least copying is -chosen. If two alternatives need the same amount of copying, the one -that comes first is chosen. These choices can be altered with the `?' -and `!' characters: - -`?' - Disparage slightly the alternative that the `?' appears in, as a - choice when no alternative applies exactly. The compiler regards - this alternative as one unit more costly for each `?' that appears - in it. - -`!' - Disparage severely the alternative that the `!' appears in. This - alternative can still be used if it fits without reloading, but if - reloading is needed, some other alternative will be used. - - When an insn pattern has multiple alternatives in its constraints, -often the appearance of the assembler code is determined mostly by which -alternative was matched. When this is so, the C code for writing the -assembler code can use the variable `which_alternative', which is the -ordinal number of the alternative that was actually satisfied (0 for -the first, 1 for the second alternative, etc.). *Note Output -Statement::. + Special expression codes exist to represent bitfield instructions. +These types of expressions are lvalues in RTL; they may appear on the +left side of an assignment, indicating insertion of a value into the +specified bit field. + +`(sign_extract:M LOC SIZE POS)' + This represents a reference to a sign-extended bit field contained + or starting in LOC (a memory or register reference). The bit field + is SIZE bits wide and starts at bit POS. The compilation option + `BITS_BIG_ENDIAN' says which end of the memory unit POS counts + from. + + If LOC is in memory, its mode must be a single-byte integer mode. + If LOC is in a register, the mode to use is specified by the + operand of the `insv' or `extv' pattern (*note Standard Names::.) + and is usually a full-word integer mode. + + The mode of POS is machine-specific and is also specified in the + `insv' or `extv' pattern. + + The mode M is the same as the mode that would be used for LOC if + it were a register. + +`(zero_extract:M LOC SIZE POS)' + Like `sign_extract' but refers to an unsigned or zero-extended bit + field. The same sequence of bits are extracted, but they are + filled to an entire word with zeros instead of by sign-extension.  -File: gcc.info, Node: Class Preferences, Next: Modifiers, Prev: Multi-Alternative, Up: Constraints +File: gcc.info, Node: Conversions, Next: RTL Declarations, Prev: Bit Fields, Up: RTL -Register Class Preferences --------------------------- +Conversions +=========== - The operand constraints have another function: they enable the -compiler to decide which kind of hardware register a pseudo register is -best allocated to. The compiler examines the constraints that apply to -the insns that use the pseudo register, looking for the -machine-dependent letters such as `d' and `a' that specify classes of -registers. The pseudo register is put in whichever class gets the most -"votes". The constraint letters `g' and `r' also vote: they vote in -favor of a general register. The machine description says which -registers are considered general. - - Of course, on some machines all registers are equivalent, and no -register classes are defined. Then none of this complexity is relevant. + All conversions between machine modes must be represented by +explicit conversion operations. For example, an expression which is +the sum of a byte and a full word cannot be written as `(plus:SI +(reg:QI 34) (reg:SI 80))' because the `plus' operation requires two +operands of the same machine mode. Therefore, the byte-sized operand +is enclosed in a conversion operation, as in + + (plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80)) + + The conversion operation is not a mere placeholder, because there +may be more than one way of converting from a given starting mode to +the desired final mode. The conversion operation code says how to do +it. + + For all conversion operations, X must not be `VOIDmode' because the +mode in which to do the conversion would not be known. The conversion +must either be done at compile-time or X must be placed into a register. + +`(sign_extend:M X)' + Represents the result of sign-extending the value X to machine + mode M. M must be a fixed-point mode and X a fixed-point value of + a mode narrower than M. + +`(zero_extend:M X)' + Represents the result of zero-extending the value X to machine + mode M. M must be a fixed-point mode and X a fixed-point value of + a mode narrower than M. + +`(float_extend:M X)' + Represents the result of extending the value X to machine mode M. + m must be a floating point mode and X a floating point value of a + mode narrower than M. + +`(truncate:M X)' + Represents the result of truncating the value X to machine mode M. + M must be a fixed-point mode and X a fixed-point value of a mode + wider than M. + +`(float_truncate:M X)' + Represents the result of truncating the value X to machine mode M. + M must be a floating point mode and X a floating point value of a + mode wider than M. + +`(float:M X)' + Represents the result of converting fixed point value X, regarded + as signed, to floating point mode M. + +`(unsigned_float:M X)' + Represents the result of converting fixed point value X, regarded + as unsigned, to floating point mode M. + +`(fix:M X)' + When M is a fixed point mode, represents the result of converting + floating point value X to mode M, regarded as signed. How + rounding is done is not specified, so this operation may be used + validly in compiling C code only for integer-valued operands. + +`(unsigned_fix:M X)' + Represents the result of converting floating point value X to + fixed point mode M, regarded as unsigned. How rounding is done is + not specified. + +`(fix:M X)' + When M is a floating point mode, represents the result of + converting floating point value X (valid for mode M) to an + integer, still represented in floating point mode M, by rounding + towards zero.  -File: gcc.info, Node: Modifiers, Next: Machine Constraints, Prev: Class Preferences, Up: Constraints +File: gcc.info, Node: RTL Declarations, Next: Side Effects, Prev: Conversions, Up: RTL -Constraint Modifier Characters ------------------------------- +Declarations +============ -`=' - Means that this operand is write-only for this instruction: the - previous value is discarded and replaced by output data. + Declaration expression codes do not represent arithmetic operations +but rather state assertions about their operands. -`+' - Means that this operand is both read and written by the - instruction. +`(strict_low_part (subreg:M (reg:N R) 0))' + This expression code is used in only one context: as the + destination operand of a `set' expression. In addition, the + operand of this expression must be a non-paradoxical `subreg' + expression. - When the compiler fixes up the operands to satisfy the constraints, - it needs to know which operands are inputs to the instruction and - which are outputs from it. `=' identifies an output; `+' - identifies an operand that is both input and output; all other - operands are assumed to be input only. - -`&' - Means (in a particular alternative) that this operand is written - before the instruction is finished using the input operands. - Therefore, this operand may not lie in a register that is used as - an input operand or as part of any memory address. - - `&' applies only to the alternative in which it is written. In - constraints with multiple alternatives, sometimes one alternative - requires `&' while others do not. See, for example, the `movdf' - insn of the 68000. - - `&' does not obviate the need to write `='. - -`%' - Declares the instruction to be commutative for this operand and the - following operand. This means that the compiler may interchange - the two operands if that is the cheapest way to make all operands - fit the constraints. This is often used in patterns for addition - instructions that really have only two operands: the result must - go in one of the arguments. Here for example, is how the 68000 - halfword-add instruction is defined: - - (define_insn "addhi3" - [(set (match_operand:HI 0 "general_operand" "=m,r") - (plus:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "general_operand" "di,g")))] - ...) - -`#' - Says that all following characters, up to the next comma, are to be - ignored as a constraint. They are significant only for choosing - register preferences. - -`*' - Says that the following character should be ignored when choosing - register preferences. `*' has no effect on the meaning of the - constraint as a constraint, and no effect on reloading. - - Here is an example: the 68000 has an instruction to sign-extend a - halfword in a data register, and can also sign-extend a value by - copying it into an address register. While either kind of - register is acceptable, the constraints on an address-register - destination are less strict, so it is best if register allocation - makes an address register its goal. Therefore, `*' is used so - that the `d' constraint letter (for data register) is ignored when - computing register preferences. - - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=*d,a") - (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,g")))] - ...) + The presence of `strict_low_part' says that the part of the + register which is meaningful in mode N, but is not part of mode M, + is not to be altered. Normally, an assignment to such a subreg is + allowed to have undefined effects on the rest of the register when + M is less than a word.  -File: gcc.info, Node: Machine Constraints, Next: No Constraints, Prev: Modifiers, Up: Constraints - -Constraints for Particular Machines ------------------------------------ - - Whenever possible, you should use the general-purpose constraint -letters in `asm' arguments, since they will convey meaning more readily -to people reading your code. Failing that, use the constraint letters -that usually have very similar meanings across architectures. The most -commonly used constraints are `m' and `r' (for memory and -general-purpose registers respectively; *note Simple Constraints::.), -and `I', usually the letter indicating the most common -immediate-constant format. - - For each machine architecture, the `config/MACHINE.h' file defines -additional constraints. These constraints are used by the compiler -itself for instruction generation, as well as for `asm' statements; -therefore, some of the constraints are not particularly interesting for -`asm'. The constraints are defined through these macros: - -`REG_CLASS_FROM_LETTER' - Register class constraints (usually lower case). - -`CONST_OK_FOR_LETTER_P' - Immediate constant constraints, for non-floating point constants of - word size or smaller precision (usually upper case). - -`CONST_DOUBLE_OK_FOR_LETTER_P' - Immediate constant constraints, for all floating point constants - and for constants of greater than word size precision (usually - upper case). - -`EXTRA_CONSTRAINT' - Special cases of registers or memory. This macro is not required, - and is only defined for some machines. - - Inspecting these macro definitions in the compiler source for your -machine is the best way to be certain you have the right constraints. -However, here is a summary of the machine-dependent constraints -available on some particular machines. - -*AMD 29000 family--`a29k.h'* - `l' - Local register 0 - - `b' - Byte Pointer (`BP') register - - `q' - `Q' register - - `h' - Special purpose register - - `A' - First accumulator register - - `a' - Other accumulator register - - `f' - Floating point register - - `I' - Constant greater than 0, less than 0x100 - - `J' - Constant greater than 0, less than 0x10000 - - `K' - Constant whose high 24 bits are on (1) - - `L' - 16 bit constant whose high 8 bits are on (1) - - `M' - 32 bit constant whose high 16 bits are on (1) - - `N' - 32 bit negative constant that fits in 8 bits - - `O' - The constant 0x80000000 or, on the 29050, any 32 bit constant - whose low 16 bits are 0. - - `P' - 16 bit negative constant that fits in 8 bits - - `G' - `H' - A floating point constant (in `asm' statements, use the - machine independent `E' or `F' instead) - -*IBM RS6000--`rs6000.h'* - `b' - Address base register - - `f' - Floating point register - - `h' - `MQ', `CTR', or `LINK' register - - `q' - `MQ' register - - `c' - `CTR' register - - `l' - `LINK' register - - `x' - `CR' register (condition register) number 0 - - `y' - `CR' register (condition register) - - `I' - Signed 16 bit constant - - `J' - Constant whose low 16 bits are 0 - - `K' - Constant whose high 16 bits are 0 - - `L' - Constant suitable as a mask operand - - `M' - Constant larger than 31 - - `N' - Exact power of 2 - - `O' - Zero - - `P' - Constant whose negation is a signed 16 bit constant - - `G' - Floating point constant that can be loaded into a register - with one instruction per word - - `Q' - Memory operand that is an offset from a register (`m' is - preferable for `asm' statements) - -*Intel 386--`i386.h'* - `q' - `a', `b', `c', or `d' register +File: gcc.info, Node: Side Effects, Next: Incdec, Prev: RTL Declarations, Up: RTL - `f' - Floating point register +Side Effect Expressions +======================= - `t' - First (top of stack) floating point register - - `u' - Second floating point register - - `a' - `a' register - - `b' - `b' register - - `c' - `c' register - - `d' - `d' register - - `D' - `di' register - - `S' - `si' register - - `I' - Constant in range 0 to 31 (for 32 bit shifts) - - `J' - Constant in range 0 to 63 (for 64 bit shifts) - - `K' - `0xff' - - `L' - `0xffff' - - `M' - 0, 1, 2, or 3 (shifts for `lea' instruction) - - `G' - Standard 80387 floating point constant - -*Intel 960--`i960.h'* - `f' - Floating point register (`fp0' to `fp3') - - `l' - Local register (`r0' to `r15') - - `b' - Global register (`g0' to `g15') - - `d' - Any local or global register - - `I' - Integers from 0 to 31 - - `J' - 0 - - `K' - Integers from -31 to 0 - - `G' - Floating point 0 - - `H' - Floating point 1 - -*MIPS--`mips.h'* - `d' - General-purpose integer register - - `f' - Floating-point register (if available) - - `h' - `Hi' register - - `l' - `Lo' register - - `x' - `Hi' or `Lo' register - - `y' - General-purpose integer register - - `z' - Floating-point status register - - `I' - Signed 16 bit constant (for arithmetic instructions) - - `J' - Zero - - `K' - Zero-extended 16-bit constant (for logic instructions) - - `L' - Constant with low 16 bits zero (can be loaded with `lui') - - `M' - 32 bit constant which requires two instructions to load (a - constant which is not `I', `K', or `L') - - `N' - Negative 16 bit constant - - `O' - Exact power of two - - `P' - Positive 16 bit constant - - `G' - Floating point zero - - `Q' - Memory reference that can be loaded with more than one - instruction (`m' is preferable for `asm' statements) - - `R' - Memory reference that can be loaded with one instruction (`m' - is preferable for `asm' statements) - - `S' - Memory reference in external OSF/rose PIC format (`m' is - preferable for `asm' statements) - -*Motorola 680x0--`m68k.h'* - `a' - Address register - - `d' - Data register - - `f' - 68881 floating-point register, if available - - `x' - Sun FPA (floating-point) register, if available - - `y' - First 16 Sun FPA registers, if available - - `I' - Integer in the range 1 to 8 - - `J' - 16 bit signed number - - `K' - Signed number whose magnitude is greater than 0x80 - - `L' - Integer in the range -8 to -1 - - `G' - Floating point constant that is not a 68881 constant - - `H' - Floating point constant that can be used by Sun FPA - -*SPARC--`sparc.h'* - `f' - Floating-point register - - `I' - Signed 13 bit constant - - `J' - Zero - - `K' - 32 bit constant with the low 12 bits clear (a constant that - can be loaded with the `sethi' instruction) + The expression codes described so far represent values, not actions. +But machine instructions never produce values; they are meaningful only +for their side effects on the state of the machine. Special expression +codes are used to represent side effects. + + The body of an instruction is always one of these side effect codes; +the codes described above, which represent values, appear only as the +operands of these. + +`(set LVAL X)' + Represents the action of storing the value of X into the place + represented by LVAL. LVAL must be an expression representing a + place that can be stored in: `reg' (or `subreg' or + `strict_low_part'), `mem', `pc' or `cc0'. + + If LVAL is a `reg', `subreg' or `mem', it has a machine mode; then + X must be valid for that mode. + + If LVAL is a `reg' whose machine mode is less than the full width + of the register, then it means that the part of the register + specified by the machine mode is given the specified value and the + rest of the register receives an undefined value. Likewise, if + LVAL is a `subreg' whose machine mode is narrower than the mode of + the register, the rest of the register can be changed in an + undefined way. + + If LVAL is a `strict_low_part' of a `subreg', then the part of the + register specified by the machine mode of the `subreg' is given + the value X and the rest of the register is not changed. + + If LVAL is `(cc0)', it has no machine mode, and X may be either a + `compare' expression or a value that may have any mode. The + latter case represents a "test" instruction. The expression `(set + (cc0) (reg:M N))' is equivalent to `(set (cc0) (compare (reg:M N) + (const_int 0)))'. Use the former expression to save space during + the compilation. + + If LVAL is `(pc)', we have a jump instruction, and the + possibilities for X are very limited. It may be a `label_ref' + expression (unconditional jump). It may be an `if_then_else' + (conditional jump), in which case either the second or the third + operand must be `(pc)' (for the case which does not jump) and the + other of the two must be a `label_ref' (for the case which does + jump). X may also be a `mem' or `(plus:SI (pc) Y)', where Y may + be a `reg' or a `mem'; these unusual patterns are used to + represent jumps through branch tables. + + If LVAL is neither `(cc0)' nor `(pc)', the mode of LVAL must not + be `VOIDmode' and the mode of X must be valid for the mode of LVAL. + + LVAL is customarily accessed with the `SET_DEST' macro and X with + the `SET_SRC' macro. + +`(return)' + As the sole expression in a pattern, represents a return from the + current function, on machines where this can be done with one + instruction, such as Vaxes. On machines where a multi-instruction + "epilogue" must be executed in order to return from the function, + returning is done by jumping to a label which precedes the + epilogue, and the `return' expression code is never used. + + Inside an `if_then_else' expression, represents the value to be + placed in `pc' to return to the caller. + + Note that an insn pattern of `(return)' is logically equivalent to + `(set (pc) (return))', but the latter form is never used. + +`(call FUNCTION NARGS)' + Represents a function call. FUNCTION is a `mem' expression whose + address is the address of the function to be called. NARGS is an + expression which can be used for two purposes: on some machines it + represents the number of bytes of stack argument; on others, it + represents the number of argument registers. + + Each machine has a standard machine mode which FUNCTION must have. + The machine description defines macro `FUNCTION_MODE' to expand + into the requisite mode name. The purpose of this mode is to + specify what kind of addressing is allowed, on machines where the + allowed kinds of addressing depend on the machine mode being + addressed. + +`(clobber X)' + Represents the storing or possible storing of an unpredictable, + undescribed value into X, which must be a `reg', `scratch' or + `mem' expression. + + One place this is used is in string instructions that store + standard values into particular hard registers. It may not be + worth the trouble to describe the values that are stored, but it + is essential to inform the compiler that the registers will be + altered, lest it attempt to keep data in them across the string + instruction. - `G' - Floating-point zero + If X is `(mem:BLK (const_int 0))', it means that all memory + locations must be presumed clobbered. - `H' - Signed 13 bit constant, sign-extended to 32 or 64 bits + Note that the machine description classifies certain hard + registers as "call-clobbered". All function call instructions are + assumed by default to clobber these registers, so there is no need + to use `clobber' expressions to indicate this fact. Also, each + function call is assumed to have the potential to alter any memory + location, unless the function is declared `const'. + + If the last group of expressions in a `parallel' are each a + `clobber' expression whose arguments are `reg' or `match_scratch' + (*note RTL Template::.) expressions, the combiner phase can add + the appropriate `clobber' expressions to an insn it has + constructed when doing so will cause a pattern to be matched. + + This feature can be used, for example, on a machine that whose + multiply and add instructions don't use an MQ register but which + has an add-accumulate instruction that does clobber the MQ + register. Similarly, a combined instruction might require a + temporary register while the constituent instructions might not. + + When a `clobber' expression for a register appears inside a + `parallel' with other side effects, the register allocator + guarantees that the register is unoccupied both before and after + that insn. However, the reload phase may allocate a register used + for one of the inputs unless the `&' constraint is specified for + the selected alternative (*note Modifiers::.). You can clobber + either a specific hard register, a pseudo register, or a `scratch' + expression; in the latter two cases, GNU CC will allocate a hard + register that is available there for use as a temporary. + + For instructions that require a temporary register, you should use + `scratch' instead of a pseudo-register because this will allow the + combiner phase to add the `clobber' when required. You do this by + coding (`clobber' (`match_scratch' ...)). If you do clobber a + pseudo register, use one which appears nowhere else--generate a + new one each time. Otherwise, you may confuse CSE. + + There is one other known use for clobbering a pseudo register in a + `parallel': when one of the input operands of the insn is also + clobbered by the insn. In this case, using the same pseudo + register in the clobber and elsewhere in the insn produces the + expected results. + +`(use X)' + Represents the use of the value of X. It indicates that the value + in X at this point in the program is needed, even though it may + not be apparent why this is so. Therefore, the compiler will not + attempt to delete previous instructions whose only effect is to + store a value in X. X must be a `reg' expression. + + During the delayed branch scheduling phase, X may be an insn. + This indicates that X previously was located at this place in the + code and its data dependencies need to be taken into account. + These `use' insns will be deleted before the delayed branch + scheduling phase exits. + +`(parallel [X0 X1 ...])' + Represents several side effects performed in parallel. The square + brackets stand for a vector; the operand of `parallel' is a vector + of expressions. X0, X1 and so on are individual side effect + expressions--expressions of code `set', `call', `return', + `clobber' or `use'. + + "In parallel" means that first all the values used in the + individual side-effects are computed, and second all the actual + side-effects are performed. For example, + + (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1))) + (set (mem:SI (reg:SI 1)) (reg:SI 1))]) + + says unambiguously that the values of hard register 1 and the + memory location addressed by it are interchanged. In both places + where `(reg:SI 1)' appears as a memory address it refers to the + value in register 1 *before* the execution of the insn. + + It follows that it is *incorrect* to use `parallel' and expect the + result of one `set' to be available for the next one. For + example, people sometimes attempt to represent a jump-if-zero + instruction this way: + + (parallel [(set (cc0) (reg:SI 34)) + (set (pc) (if_then_else + (eq (cc0) (const_int 0)) + (label_ref ...) + (pc)))]) + + But this is incorrect, because it says that the jump condition + depends on the condition code value *before* this instruction, not + on the new value that is set by this instruction. + + Peephole optimization, which takes place together with final + assembly code output, can produce insns whose patterns consist of + a `parallel' whose elements are the operands needed to output the + resulting assembler code--often `reg', `mem' or constant + expressions. This would not be well-formed RTL at any other stage + in compilation, but it is ok then because no further optimization + remains to be done. However, the definition of the macro + `NOTICE_UPDATE_CC', if any, must deal with such insns if you + define any peephole optimizations. + +`(sequence [INSNS ...])' + Represents a sequence of insns. Each of the INSNS that appears in + the vector is suitable for appearing in the chain of insns, so it + must be an `insn', `jump_insn', `call_insn', `code_label', + `barrier' or `note'. + + A `sequence' RTX is never placed in an actual insn during RTL + generation. It represents the sequence of insns that result from a + `define_expand' *before* those insns are passed to `emit_insn' to + insert them in the chain of insns. When actually inserted, the + individual sub-insns are separated out and the `sequence' is + forgotten. + + After delay-slot scheduling is completed, an insn and all the + insns that reside in its delay slots are grouped together into a + `sequence'. The insn requiring the delay slot is the first insn + in the vector; subsequent insns are to be placed in the delay slot. + + `INSN_ANNULLED_BRANCH_P' is set on an insn in a delay slot to + indicate that a branch insn should be used that will conditionally + annul the effect of the insns in the delay slots. In such a case, + `INSN_FROM_TARGET_P' indicates that the insn is from the target of + the branch and should be executed only if the branch is taken; + otherwise the insn should be executed only if the branch is not + taken. *Note Delay Slots::. + + These expression codes appear in place of a side effect, as the body +of an insn, though strictly speaking they do not always describe side +effects as such: + +`(asm_input S)' + Represents literal assembler code as described by the string S. + +`(unspec [OPERANDS ...] INDEX)' +`(unspec_volatile [OPERANDS ...] INDEX)' + Represents a machine-specific operation on OPERANDS. INDEX + selects between multiple machine-specific operations. + `unspec_volatile' is used for volatile operations and operations + that may trap; `unspec' is used for other operations. + + These codes may appear inside a `pattern' of an insn, inside a + `parallel', or inside an expression. + +`(addr_vec:M [LR0 LR1 ...])' + Represents a table of jump addresses. The vector elements LR0, + etc., are `label_ref' expressions. The mode M specifies how much + space is given to each address; normally M would be `Pmode'. + +`(addr_diff_vec:M BASE [LR0 LR1 ...])' + Represents a table of jump addresses expressed as offsets from + BASE. The vector elements LR0, etc., are `label_ref' expressions + and so is BASE. The mode M specifies how much space is given to + each address-difference. - `Q' - Memory reference that can be loaded with one instruction - (`m' is more appropriate for `asm' statements) + +File: gcc.info, Node: Incdec, Next: Assembler, Prev: Side Effects, Up: RTL - `S' - Constant, or memory address +Embedded Side-Effects on Addresses +================================== - `T' - Memory address aligned to an 8-byte boundary + Four special side-effect expression codes appear as memory addresses. - `U' - Even register +`(pre_dec:M X)' + Represents the side effect of decrementing X by a standard amount + and represents also the value that X has after being decremented. + x must be a `reg' or `mem', but most machines allow only a `reg'. + m must be the machine mode for pointers on the machine in use. + The amount X is decremented by is the length in bytes of the + machine mode of the containing memory reference of which this + expression serves as the address. Here is an example of its use: + + (mem:DF (pre_dec:SI (reg:SI 39))) + + This says to decrement pseudo register 39 by the length of a + `DFmode' value and use the result to address a `DFmode' value. + +`(pre_inc:M X)' + Similar, but specifies incrementing X instead of decrementing it. + +`(post_dec:M X)' + Represents the same side effect as `pre_dec' but a different + value. The value represented here is the value X has before being + decremented. + +`(post_inc:M X)' + Similar, but specifies incrementing X instead of decrementing it. + + These embedded side effect expressions must be used with care. +Instruction patterns may not use them. Until the `flow' pass of the +compiler, they may occur only to represent pushes onto the stack. The +`flow' pass finds cases where registers are incremented or decremented +in one instruction and used as an address shortly before or after; +these cases are then transformed to use pre- or post-increment or +-decrement. + + If a register used as the operand of these expressions is used in +another address in an insn, the original value of the register is used. +Uses of the register outside of an address are not permitted within the +same insn as a use in an embedded side effect expression because such +insns behave differently on different machines and hence must be treated +as ambiguous and disallowed. + + An instruction that can be represented with an embedded side effect +could also be represented using `parallel' containing an additional +`set' to describe how the address register is altered. This is not +done because machines that allow these operations at all typically +allow them wherever a memory address is called for. Describing them as +additional parallel stores would require doubling the number of entries +in the machine description.  -File: gcc.info, Node: No Constraints, Prev: Machine Constraints, Up: Constraints +File: gcc.info, Node: Assembler, Next: Insns, Prev: Incdec, Up: RTL -Not Using Constraints ---------------------- +Assembler Instructions as Expressions +===================================== - Some machines are so clean that operand constraints are not -required. For example, on the Vax, an operand valid in one context is -valid in any other context. On such a machine, every operand -constraint would be `g', excepting only operands of "load address" -instructions which are written as if they referred to a memory -location's contents but actual refer to its address. They would have -constraint `p'. - - For such machines, instead of writing `g' and `p' for all the -constraints, you can choose to write a description with empty -constraints. Then you write `""' for the constraint in every -`match_operand'. Address operands are identified by writing an -`address' expression around the `match_operand', not by their -constraints. - - When the machine description has just empty constraints, certain -parts of compilation are skipped, making the compiler faster. However, -few machines actually do not need constraints; all machine descriptions -now in existence use constraints. + The RTX code `asm_operands' represents a value produced by a +user-specified assembler instruction. It is used to represent an `asm' +statement with arguments. An `asm' statement with a single output +operand, like this: + + asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z)); + +is represented using a single `asm_operands' RTX which represents the +value that is stored in `outputvar': + + (set RTX-FOR-OUTPUTVAR + (asm_operands "foo %1,%2,%0" "a" 0 + [RTX-FOR-ADDITION-RESULT RTX-FOR-*Z] + [(asm_input:M1 "g") + (asm_input:M2 "di")])) + +Here the operands of the `asm_operands' RTX are the assembler template +string, the output-operand's constraint, the index-number of the output +operand among the output operands specified, a vector of input operand +RTX's, and a vector of input-operand modes and constraints. The mode +M1 is the mode of the sum `x+y'; M2 is that of `*z'. + + When an `asm' statement has multiple output values, its insn has +several such `set' RTX's inside of a `parallel'. Each `set' contains a +`asm_operands'; all of these share the same assembler template and +vectors, but each contains the constraint for the respective output +operand. They are also distinguished by the output-operand index +number, which is 0, 1, ... for successive output operands.