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1.1.1.4 ! root 1: This is Info file gcc.info, produced by Makeinfo-1.49 from the input 1.1 root 2: file gcc.texi. 3: 4: This file documents the use and the internals of the GNU compiler. 5: 6: Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc. 7: 1.1.1.3 root 8: Permission is granted to make and distribute verbatim copies of this 9: manual provided the copyright notice and this permission notice are 10: preserved on all copies. 1.1 root 11: 12: Permission is granted to copy and distribute modified versions of 13: this manual under the conditions for verbatim copying, provided also 1.1.1.4 ! root 14: that the sections entitled "GNU General Public License" and "Protect ! 15: Your Freedom--Fight `Look And Feel'" are included exactly as in the ! 16: original, and provided that the entire resulting derived work is ! 17: distributed under the terms of a permission notice identical to this ! 18: one. 1.1 root 19: 20: Permission is granted to copy and distribute translations of this 21: manual into another language, under the above conditions for modified 1.1.1.3 root 22: versions, except that the sections entitled "GNU General Public 1.1.1.4 ! root 23: License" and "Protect Your Freedom--Fight `Look And Feel'", and this ! 24: permission notice, may be included in translations approved by the Free ! 25: Software Foundation instead of in the original English. ! 26: ! 27: ! 28: File: gcc.info, Node: Expander Definitions, Next: Insn Splitting, Prev: Peephole Definitions, Up: Machine Desc ! 29: ! 30: Defining RTL Sequences for Code Generation ! 31: ========================================== ! 32: ! 33: On some target machines, some standard pattern names for RTL ! 34: generation cannot be handled with single insn, but a sequence of RTL ! 35: insns can represent them. For these target machines, you can write a ! 36: `define_expand' to specify how to generate the sequence of RTL. ! 37: ! 38: A `define_expand' is an RTL expression that looks almost like a ! 39: `define_insn'; but, unlike the latter, a `define_expand' is used only ! 40: for RTL generation and it can produce more than one RTL insn. ! 41: ! 42: A `define_expand' RTX has four operands: ! 43: ! 44: * The name. Each `define_expand' must have a name, since the only ! 45: use for it is to refer to it by name. ! 46: ! 47: * The RTL template. This is just like the RTL template for a ! 48: `define_peephole' in that it is a vector of RTL expressions each ! 49: being one insn. ! 50: ! 51: * The condition, a string containing a C expression. This ! 52: expression is used to express how the availability of this pattern ! 53: depends on subclasses of target machine, selected by command-line ! 54: options when GNU CC is run. This is just like the condition of a ! 55: `define_insn' that has a standard name. ! 56: ! 57: * The preparation statements, a string containing zero or more C ! 58: statements which are to be executed before RTL code is generated ! 59: from the RTL template. ! 60: ! 61: Usually these statements prepare temporary registers for use as ! 62: internal operands in the RTL template, but they can also generate ! 63: RTL insns directly by calling routines such as `emit_insn', etc. ! 64: Any such insns precede the ones that come from the RTL template. ! 65: ! 66: Every RTL insn emitted by a `define_expand' must match some ! 67: `define_insn' in the machine description. Otherwise, the compiler will ! 68: crash when trying to generate code for the insn or trying to optimize ! 69: it. ! 70: ! 71: The RTL template, in addition to controlling generation of RTL insns, ! 72: also describes the operands that need to be specified when this pattern ! 73: is used. In particular, it gives a predicate for each operand. ! 74: ! 75: A true operand, which needs to be specified in order to generate RTL ! 76: from the pattern, should be described with a `match_operand' in its ! 77: first occurrence in the RTL template. This enters information on the ! 78: operand's predicate into the tables that record such things. GNU CC ! 79: uses the information to preload the operand into a register if that is ! 80: required for valid RTL code. If the operand is referred to more than ! 81: once, subsequent references should use `match_dup'. ! 82: ! 83: The RTL template may also refer to internal "operands" which are ! 84: temporary registers or labels used only within the sequence made by the ! 85: `define_expand'. Internal operands are substituted into the RTL ! 86: template with `match_dup', never with `match_operand'. The values of ! 87: the internal operands are not passed in as arguments by the compiler ! 88: when it requests use of this pattern. Instead, they are computed ! 89: within the pattern, in the preparation statements. These statements ! 90: compute the values and store them into the appropriate elements of ! 91: `operands' so that `match_dup' can find them. ! 92: ! 93: There are two special macros defined for use in the preparation ! 94: statements: `DONE' and `FAIL'. Use them with a following semicolon, as ! 95: a statement. ! 96: ! 97: `DONE' ! 98: Use the `DONE' macro to end RTL generation for the pattern. The ! 99: only RTL insns resulting from the pattern on this occasion will be ! 100: those already emitted by explicit calls to `emit_insn' within the ! 101: preparation statements; the RTL template will not be generated. ! 102: ! 103: `FAIL' ! 104: Make the pattern fail on this occasion. When a pattern fails, it ! 105: means that the pattern was not truly available. The calling ! 106: routines in the compiler will try other strategies for code ! 107: generation using other patterns. ! 108: ! 109: Failure is currently supported only for binary (addition, ! 110: multiplication, shifting, etc.) and bitfield (`extv', `extzv', and ! 111: `insv') operations. ! 112: ! 113: Here is an example, the definition of left-shift for the SPUR chip: ! 114: ! 115: (define_expand "ashlsi3" ! 116: [(set (match_operand:SI 0 "register_operand" "") ! 117: (ashift:SI ! 118: (match_operand:SI 1 "register_operand" "") ! 119: (match_operand:SI 2 "nonmemory_operand" "")))] ! 120: "" ! 121: " ! 122: { ! 123: if (GET_CODE (operands[2]) != CONST_INT ! 124: || (unsigned) INTVAL (operands[2]) > 3) ! 125: FAIL; ! 126: }") ! 127: ! 128: This example uses `define_expand' so that it can generate an RTL insn ! 129: for shifting when the shift-count is in the supported range of 0 to 3 ! 130: but fail in other cases where machine insns aren't available. When it ! 131: fails, the compiler tries another strategy using different patterns ! 132: (such as, a library call). ! 133: ! 134: If the compiler were able to handle nontrivial condition-strings in ! 135: patterns with names, then it would be possible to use a `define_insn' ! 136: in that case. Here is another case (zero-extension on the 68000) which ! 137: makes more use of the power of `define_expand': ! 138: ! 139: (define_expand "zero_extendhisi2" ! 140: [(set (match_operand:SI 0 "general_operand" "") ! 141: (const_int 0)) ! 142: (set (strict_low_part ! 143: (subreg:HI ! 144: (match_dup 0) ! 145: 0)) ! 146: (match_operand:HI 1 "general_operand" ""))] ! 147: "" ! 148: "operands[1] = make_safe_from (operands[1], operands[0]);") ! 149: ! 150: Here two RTL insns are generated, one to clear the entire output operand ! 151: and the other to copy the input operand into its low half. This ! 152: sequence is incorrect if the input operand refers to [the old value of] ! 153: the output operand, so the preparation statement makes sure this isn't ! 154: so. The function `make_safe_from' copies the `operands[1]' into a ! 155: temporary register if it refers to `operands[0]'. It does this by ! 156: emitting another RTL insn. ! 157: ! 158: Finally, a third example shows the use of an internal operand. ! 159: Zero-extension on the SPUR chip is done by `and'-ing the result against ! 160: a halfword mask. But this mask cannot be represented by a `const_int' ! 161: because the constant value is too large to be legitimate on this ! 162: machine. So it must be copied into a register with `force_reg' and ! 163: then the register used in the `and'. ! 164: ! 165: (define_expand "zero_extendhisi2" ! 166: [(set (match_operand:SI 0 "register_operand" "") ! 167: (and:SI (subreg:SI ! 168: (match_operand:HI 1 "register_operand" "") ! 169: 0) ! 170: (match_dup 2)))] ! 171: "" ! 172: "operands[2] ! 173: = force_reg (SImode, gen_rtx (CONST_INT, ! 174: VOIDmode, 65535)); ") ! 175: ! 176: *Note:* If the `define_expand' is used to serve a standard binary or ! 177: unary arithmetic operation or a bitfield operation, then the last insn ! 178: it generates must not be a `code_label', `barrier' or `note'. It must ! 179: be an `insn', `jump_insn' or `call_insn'. If you don't need a real insn ! 180: at the end, emit an insn to copy the result of the operation into ! 181: itself. Such an insn will generate no code, but it can avoid problems ! 182: in the compiler. ! 183: ! 184: ! 185: File: gcc.info, Node: Insn Splitting, Next: Insn Attributes, Prev: Expander Definitions, Up: Machine Desc ! 186: ! 187: Splitting Instructions into Multiple Instructions ! 188: ================================================= ! 189: ! 190: There are two cases where you should specify how to split a pattern ! 191: into multiple insns. On machines that have instructions requiring delay ! 192: slots (*note Delay Slots::.) or that have instructions whose output is ! 193: not available for multiple cycles (*note Function Units::.), the ! 194: compiler phases that optimize these cases need to be able to move insns ! 195: into one-cycle delay slots. However, some insns may generate more than ! 196: one machine instruction. These insns cannot be placed into a delay ! 197: slot. ! 198: ! 199: Often you can rewrite the single insn as a list of individual insns, ! 200: each corresponding to one machine instruction. The disadvantage of ! 201: doing so is that it will cause the compilation to be slower and require ! 202: more space. If the resulting insns are too complex, it may also ! 203: suppress some optimizations. The compiler splits the insn if there is a ! 204: reason to believe that it might improve instruction or delay slot ! 205: scheduling. ! 206: ! 207: The insn combiner phase also splits putative insns. If three insns ! 208: are merged into one insn with a complex expression that cannot be ! 209: matched by some `define_insn' pattern, the combiner phase attempts to ! 210: split the complex pattern into two insns that are recognized. Usually ! 211: it can break the complex pattern into two patterns by splitting out some ! 212: subexpression. However, in some other cases, such as performing an ! 213: addition of a large constant in two insns on a RISC machine, the way to ! 214: split the addition into two insns is machine-dependent. ! 215: ! 216: The `define_split' definition tells the compiler how to split a ! 217: complex insn into several simpler insns. It looks like this: ! 218: ! 219: (define_split ! 220: [INSN-PATTERN] ! 221: "CONDITION" ! 222: [NEW-INSN-PATTERN-1 ! 223: NEW-INSN-PATTERN-2 ! 224: ...] ! 225: "PREPARATION STATEMENTS") ! 226: ! 227: INSN-PATTERN is a pattern that needs to be split and CONDITION is ! 228: the final condition to be tested, as in a `define_insn'. When an insn ! 229: matching INSN-PATTERN and satisfying CONDITION is found, it is replaced ! 230: in the insn list with the insns given by NEW-INSN-PATTERN-1, ! 231: NEW-INSN-PATTERN-2, etc. ! 232: ! 233: The PREPARATION STATEMENTS are similar to those specified for ! 234: `define_expand' (*note Expander Definitions::.) and are executed before ! 235: the new RTL is generated to prepare for the generated code or emit some ! 236: insns whose pattern is not fixed. Unlike those in `define_expand', ! 237: however, these statements must not generate any new pseudo-registers. ! 238: Once reload has completed, they also must not allocate any space in the ! 239: stack frame. ! 240: ! 241: Patterns are matched against INSN-PATTERN in two different ! 242: circumstances. If an insn needs to be split for delay slot scheduling ! 243: or insn scheduling, the insn is already known to be valid, which means ! 244: that it must have been matched by some `define_insn' and, if ! 245: `reload_completed' is non-zero, is known to satisfy the constraints of ! 246: that `define_insn'. In that case, the new insn patterns must also be ! 247: insns that are matched by some `define_insn' and, if `reload_completed' ! 248: is non-zero, must also satisfy the constraints of those definitions. ! 249: ! 250: As an example of this usage of `define_split', consider the following ! 251: example from `a29k.md', which splits a `sign_extend' from `HImode' to ! 252: `SImode' into a pair of shift insns: ! 253: ! 254: (define_split ! 255: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 256: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] ! 257: "" ! 258: [(set (match_dup 0) ! 259: (ashift:SI (match_dup 1) ! 260: (const_int 16))) ! 261: (set (match_dup 0) ! 262: (ashiftrt:SI (match_dup 0) ! 263: (const_int 16)))] ! 264: " ! 265: { operands[1] = gen_lowpart (SImode, operands[1]); }") ! 266: ! 267: When the combiner phase tries to split an insn pattern, it is always ! 268: the case that the pattern is *not* matched by any `define_insn'. The ! 269: combiner pass first tries to split a single `set' expression and then ! 270: the same `set' expression inside a `parallel', but followed by a ! 271: `clobber' of a pseudo-reg to use as a scratch register. In these ! 272: cases, the combiner expects exactly two new insn patterns to be ! 273: generated. It will verify that these patterns match some `define_insn' ! 274: definitions, so you need not do this test in the `define_split' (of ! 275: course, there is no point in writing a `define_split' that will never ! 276: produce insns that match). ! 277: ! 278: Here is an example of this use of `define_split', taken from ! 279: `rs6000.md': ! 280: ! 281: (define_split ! 282: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 283: (plus:SI (match_operand:SI 1 "gen_reg_operand" "") ! 284: (match_operand:SI 2 "non_add_cint_operand" "")))] ! 285: "" ! 286: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) ! 287: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] ! 288: " ! 289: { ! 290: int low = INTVAL (operands[2]) & 0xffff; ! 291: int high = (unsigned) INTVAL (operands[2]) >> 16; ! 292: ! 293: if (low & 0x8000) ! 294: high++, low |= 0xffff0000; ! 295: ! 296: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); ! 297: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); ! 298: }") ! 299: ! 300: Here the predicate `non_add_cint_operand' matches any `const_int' ! 301: that is *not* a valid operand of a single add insn. Write the add with ! 302: the smaller displacement is written so that it can be substituted into ! 303: the address of a subsequent operation. ! 304: ! 305: An example that uses a scratch register, from the same file, ! 306: generates an equality comparison of a register and a large constant: ! 307: ! 308: (define_split ! 309: [(set (match_operand:CC 0 "cc_reg_operand" "") ! 310: (compare:CC (match_operand:SI 1 "gen_reg_operand" "") ! 311: (match_operand:SI 2 "non_short_cint_operand" ""))) ! 312: (clobber (match_operand:SI 3 "gen_reg_operand" ""))] ! 313: "find_single_use (operands[0], insn, 0) ! 314: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ ! 315: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" ! 316: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) ! 317: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] ! 318: " ! 319: { ! 320: /* Get the constant we are comparing against, C, and see what it looks like ! 321: sign-extended to 16 bits. Then see what constant could be XOR'ed ! 322: with C to get the sign-extended value. */ ! 323: ! 324: int c = INTVAL (operands[2]); ! 325: int sextc = (c << 16) >> 16; ! 326: int xorv = c ^ sextc; ! 327: ! 328: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); ! 329: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); ! 330: }") ! 331: ! 332: To avoid confusion, don't write a single `define_split' that accepts ! 333: some insns that match some `define_insn' as well as some insns that ! 334: don't. Instead, write two separate `define_split' definitions, one for ! 335: the insns that are valid and one for the insns that are not valid. ! 336: ! 337: ! 338: File: gcc.info, Node: Insn Attributes, Prev: Insn Splitting, Up: Machine Desc ! 339: ! 340: Instruction Attributes ! 341: ====================== ! 342: ! 343: In addition to describing the instruction supported by the target ! 344: machine, the `md' file also defines a group of "attributes" and a set of ! 345: values for each. Every generated insn is assigned a value for each ! 346: attribute. One possible attribute would be the effect that the insn has ! 347: on the machine's condition code. This attribute can then be used by ! 348: `NOTICE_UPDATE_CC' to track the condition codes. 1.1.1.3 root 349: 350: * Menu: 351: 1.1.1.4 ! root 352: * Defining Attributes:: Specifying attributes and their values. ! 353: * Expressions:: Valid expressions for attribute values. ! 354: * Tagging Insns:: Assigning attribute values to insns. ! 355: * Attr Example:: An example of assigning attributes. ! 356: * Insn Lengths:: Computing the length of insns. ! 357: * Constant Attributes:: Defining attributes that are constant. ! 358: * Delay Slots:: Defining delay slots required for a machine. ! 359: * Function Units:: Specifying information for insn scheduling. ! 360: ! 361: ! 362: File: gcc.info, Node: Defining Attributes, Next: Expressions, Prev: Insn Attributes, Up: Insn Attributes ! 363: ! 364: Defining Attributes and their Values ! 365: ------------------------------------ ! 366: ! 367: The `define_attr' expression is used to define each attribute ! 368: required by the target machine. It looks like: ! 369: ! 370: (define_attr NAME LIST-OF-VALUES DEFAULT) ! 371: ! 372: NAME is a string specifying the name of the attribute being defined. ! 373: ! 374: LIST-OF-VALUES is either a string that specifies a comma-separated ! 375: list of values that can be assigned to the attribute, or a null string ! 376: to indicate that the attribute takes numeric values. ! 377: ! 378: DEFAULT is an attribute expression that gives the value of this ! 379: attribute for insns that match patterns whose definition does not ! 380: include an explicit value for this attribute. *Note Attr Example::, ! 381: for more information on the handling of defaults. *Note Constant ! 382: Attributes::, for information on attributes that do not depend on any ! 383: particular insn. ! 384: ! 385: For each defined attribute, a number of definitions are written to ! 386: the `insn-attr.h' file. For cases where an explicit set of values is ! 387: specified for an attribute, the following are defined: ! 388: ! 389: * A `#define' is written for the symbol `HAVE_ATTR_NAME'. ! 390: ! 391: * An enumeral class is defined for `attr_NAME' with elements of the ! 392: form `UPPER-NAME_UPPER-VALUE' where the attribute name and value ! 393: are first converted to upper case. ! 394: ! 395: * A function `get_attr_NAME' is defined that is passed an insn and ! 396: returns the attribute value for that insn. ! 397: ! 398: For example, if the following is present in the `md' file: ! 399: ! 400: (define_attr "type" "branch,fp,load,store,arith" ...) ! 401: ! 402: the following lines will be written to the file `insn-attr.h'. ! 403: ! 404: #define HAVE_ATTR_type ! 405: enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, ! 406: TYPE_STORE, TYPE_ARITH}; ! 407: extern enum attr_type get_attr_type (); ! 408: ! 409: If the attribute takes numeric values, no `enum' type will be ! 410: defined and the function to obtain the attribute's value will return ! 411: `int'. ! 412: ! 413: ! 414: File: gcc.info, Node: Expressions, Next: Tagging Insns, Prev: Defining Attributes, Up: Insn Attributes ! 415: ! 416: Attribute Expressions ! 417: --------------------- ! 418: ! 419: RTL expressions used to define attributes use the codes described ! 420: above plus a few specific to attribute definitions, to be discussed ! 421: below. Attribute value expressions must have one of the following forms: ! 422: ! 423: `(const_int I)' ! 424: The integer I specifies the value of a numeric attribute. I must ! 425: be non-negative. ! 426: ! 427: The value of a numeric attribute can be specified either with a ! 428: `const_int' or as an integer represented as a string in ! 429: `const_string', `eq_attr' (see below), and `set_attr' (*note ! 430: Tagging Insns::.) expressions. ! 431: ! 432: `(const_string VALUE)' ! 433: The string VALUE specifies a constant attribute value. If VALUE is ! 434: specified as `"*"', it means that the default value of the ! 435: attribute is to be used for the insn containing this expression. ! 436: `"*"' obviously cannot be used in the DEFAULT expression of a ! 437: `define_attr'. ! 438: ! 439: If the attribute whose value is being specified is numeric, VALUE ! 440: must be a string containing a non-negative integer (normally ! 441: `const_int' would be used in this case). Otherwise, it must ! 442: contain one of the valid values for the attribute. ! 443: ! 444: `(if_then_else TEST TRUE-VALUE FALSE-VALUE)' ! 445: TEST specifies an attribute test, whose format is defined below. ! 446: The value of this expression is TRUE-VALUE if TEST is true, ! 447: otherwise it is FALSE-VALUE. ! 448: ! 449: `(cond [TEST1 VALUE1 ...] DEFAULT)' ! 450: The first operand of this expression is a vector containing an even ! 451: number of expressions and consisting of pairs of TEST and VALUE ! 452: expressions. The value of the `cond' expression is that of the ! 453: VALUE corresponding to the first true TEST expression. If none of ! 454: the TEST expressions are true, the value of the `cond' expression ! 455: is that of the DEFAULT expression. ! 456: ! 457: TEST expressions can have one of the following forms: ! 458: ! 459: `(const_int I)' ! 460: This test is true if I is non-zero and false otherwise. ! 461: ! 462: `(not TEST)' ! 463: `(ior TEST1 TEST2)' ! 464: `(and TEST1 TEST2)' ! 465: These tests are true if the indicated logical function is true. ! 466: ! 467: `(match_operand:M N PRED CONSTRAINTS)' ! 468: This test is true if operand N of the insn whose attribute value ! 469: is being determined has mode M (this part of the test is ignored ! 470: if M is `VOIDmode') and the function specified by the string PRED ! 471: returns a non-zero value when passed operand N and mode M (this ! 472: part of the test is ignored if PRED is the null string). ! 473: ! 474: The CONSTRAINTS operand is ignored and should be the null string. ! 475: ! 476: `(le ARITH1 ARITH2)' ! 477: `(leu ARITH1 ARITH2)' ! 478: `(lt ARITH1 ARITH2)' ! 479: `(ltu ARITH1 ARITH2)' ! 480: `(gt ARITH1 ARITH2)' ! 481: `(gtu ARITH1 ARITH2)' ! 482: `(ge ARITH1 ARITH2)' ! 483: `(geu ARITH1 ARITH2)' ! 484: `(ne ARITH1 ARITH2)' ! 485: `(eq ARITH1 ARITH2)' ! 486: These tests are true if the indicated comparison of the two ! 487: arithmetic expressions is true. Arithmetic expressions are formed ! 488: with `plus', `minus', `mult', `div', `mod', `abs', `neg', `and', ! 489: `ior', `xor', `not', `lshift', `ashift', `lshiftrt', and `ashiftrt' ! 490: expressions. ! 491: ! 492: `const_int' and `symbol_ref' are always valid terms (*note Insn ! 493: Lengths::.,for additional forms). `symbol_ref' is a string ! 494: denoting a C expression that yields an `int' when evaluated by the ! 495: `get_attr_...' routine. It should normally be a global variable. ! 496: ! 497: `(eq_attr NAME VALUE)' ! 498: NAME is a string specifying the name of an attribute. ! 499: ! 500: VALUE is a string that is either a valid value for attribute NAME, ! 501: a comma-separated list of values, or `!' followed by a value or ! 502: list. If VALUE does not begin with a `!', this test is true if ! 503: the value of the NAME attribute of the current insn is in the list ! 504: specified by VALUE. If VALUE begins with a `!', this test is true ! 505: if the attribute's value is *not* in the specified list. ! 506: ! 507: For example, ! 508: ! 509: (eq_attr "type" "load,store") ! 510: ! 511: is equivalent to ! 512: ! 513: (ior (eq_attr "type" "load") (eq_attr "type" "store")) ! 514: ! 515: If NAME specifies an attribute of `alternative', it refers to the ! 516: value of the compiler variable `which_alternative' (*note Output ! 517: Statement::.) and the values must be small integers. For example, ! 518: ! 519: (eq_attr "alternative" "2,3") ! 520: ! 521: is equivalent to ! 522: ! 523: (ior (eq (symbol_ref "which_alternative") (const_int 2)) ! 524: (eq (symbol_ref "which_alternative") (const_int 3))) ! 525: ! 526: Note that, for most attributes, an `eq_attr' test is simplified in ! 527: cases where the value of the attribute being tested is known for ! 528: all insns matching a particular pattern. This is by far the most ! 529: common case. ! 530: ! 531: ! 532: File: gcc.info, Node: Tagging Insns, Next: Attr Example, Prev: Expressions, Up: Insn Attributes ! 533: ! 534: Assigning Attribute Values to Insns ! 535: ----------------------------------- ! 536: ! 537: The value assigned to an attribute of an insn is primarily ! 538: determined by which pattern is matched by that insn (or which ! 539: `define_peephole' generated it). Every `define_insn' and ! 540: `define_peephole' can have an optional last argument to specify the ! 541: values of attributes for matching insns. The value of any attribute ! 542: not specified in a particular insn is set to the default value for that ! 543: attribute, as specified in its `define_attr'. Extensive use of default ! 544: values for attributes permits the specification of the values for only ! 545: one or two attributes in the definition of most insn patterns, as seen ! 546: in the example in the next section. ! 547: ! 548: The optional last argument of `define_insn' and `define_peephole' is ! 549: a vector of expressions, each of which defines the value for a single ! 550: attribute. The most general way of assigning an attribute's value is ! 551: to use a `set' expression whose first operand is an `attr' expression ! 552: giving the name of the attribute being set. The second operand of the ! 553: `set' is an attribute expression (*note Expressions::.) giving the ! 554: value of the attribute. ! 555: ! 556: When the attribute value depends on the `alternative' attribute ! 557: (i.e., which is the applicable alternative in the constraint of the ! 558: insn), the `set_attr_alternative' expression can be used. It allows ! 559: the specification of a vector of attribute expressions, one for each ! 560: alternative. ! 561: ! 562: When the generality of arbitrary attribute expressions is not ! 563: required, the simpler `set_attr' expression can be used, which allows ! 564: specifying a string giving either a single attribute value or a list of ! 565: attribute values, one for each alternative. ! 566: ! 567: The form of each of the above specifications is shown below. In ! 568: each case, NAME is a string specifying the attribute to be set. ! 569: ! 570: `(set_attr NAME VALUE-STRING)' ! 571: VALUE-STRING is either a string giving the desired attribute value, ! 572: or a string containing a comma-separated list giving the values for ! 573: succeeding alternatives. The number of elements must match the ! 574: number of alternatives in the constraint of the insn pattern. ! 575: ! 576: Note that it may be useful to specify `*' for some alternative, in ! 577: which case the attribute will assume its default value for insns ! 578: matching that alternative. ! 579: ! 580: `(set_attr_alternative NAME [VALUE1 VALUE2 ...])' ! 581: Depending on the alternative of the insn, the value will be one of ! 582: the specified values. This is a shorthand for using a `cond' with ! 583: tests on the `alternative' attribute. ! 584: ! 585: `(set (attr NAME) VALUE)' ! 586: The first operand of this `set' must be the special RTL expression ! 587: `attr', whose sole operand is a string giving the name of the ! 588: attribute being set. VALUE is the value of the attribute. ! 589: ! 590: The following shows three different ways of representing the same ! 591: attribute value specification: ! 592: ! 593: (set_attr "type" "load,store,arith") ! 594: ! 595: (set_attr_alternative "type" ! 596: [(const_string "load") (const_string "store") ! 597: (const_string "arith")]) ! 598: ! 599: (set (attr "type") ! 600: (cond [(eq_attr "alternative" "1") (const_string "load") ! 601: (eq_attr "alternative" "2") (const_string "store")] ! 602: (const_string "arith"))) ! 603: ! 604: The `define_asm_attributes' expression provides a mechanism to ! 605: specify the attributes assigned to insns produced from an `asm' ! 606: statement. It has the form: ! 607: ! 608: (define_asm_attributes [ATTR-SETS]) ! 609: ! 610: where ATTR-SETS is specified the same as for `define_insn' and ! 611: `define_peephole' expressions. ! 612: ! 613: These values will typically be the "worst case" attribute values. ! 614: For example, they might indicate that the condition code will be ! 615: clobbered. ! 616: ! 617: A specification for a `length' attribute is handled specially. To ! 618: compute the length of an `asm' insn, the length specified in the ! 619: `define_asm_attributes' expression is multiplied by the number of ! 620: machine instructions specified in the `asm' statement, determined by ! 621: counting the number of semicolons and newlines in the string. ! 622: Therefore, the value of the `length' attribute specified in a ! 623: `define_asm_attributes' should be the maximum possible length of a ! 624: single machine instruction. ! 625: ! 626: ! 627: File: gcc.info, Node: Attr Example, Next: Insn Lengths, Prev: Tagging Insns, Up: Insn Attributes ! 628: ! 629: Example of Attribute Specifications ! 630: ----------------------------------- ! 631: ! 632: The judicious use of defaulting is important in the efficient use of ! 633: insn attributes. Typically, insns are divided into "types" and an ! 634: attribute, customarily called `type', is used to represent this value. ! 635: This attribute is normally used only to define the default value for ! 636: other attributes. An example will clarify this usage. ! 637: ! 638: Assume we have a RISC machine with a condition code and in which only ! 639: full-word operations are performed in registers. Let us assume that we ! 640: can divide all insns into loads, stores, (integer) arithmetic ! 641: operations, floating point operations, and branches. ! 642: ! 643: Here we will concern ourselves with determining the effect of an ! 644: insn on the condition code and will limit ourselves to the following ! 645: possible effects: The condition code can be set unpredictably ! 646: (clobbered), not be changed, be set to agree with the results of the ! 647: operation, or only changed if the item previously set into the ! 648: condition code has been modified. ! 649: ! 650: Here is part of a sample `md' file for such a machine: ! 651: ! 652: (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) ! 653: ! 654: (define_attr "cc" "clobber,unchanged,set,change0" ! 655: (cond [(eq_attr "type" "load") ! 656: (const_string "change0") ! 657: (eq_attr "type" "store,branch") ! 658: (const_string "unchanged") ! 659: (eq_attr "type" "arith") ! 660: (if_then_else (match_operand:SI 0 "" "") ! 661: (const_string "set") ! 662: (const_string "clobber"))] ! 663: (const_string "clobber"))) ! 664: ! 665: (define_insn "" ! 666: [(set (match_operand:SI 0 "general_operand" "=r,r,m") ! 667: (match_operand:SI 1 "general_operand" "r,m,r"))] ! 668: "" ! 669: "@ ! 670: move %0,%1 ! 671: load %0,%1 ! 672: store %0,%1" ! 673: [(set_attr "type" "arith,load,store")]) ! 674: ! 675: Note that we assume in the above example that arithmetic operations ! 676: performed on quantities smaller than a machine word clobber the ! 677: condition code since they will set the condition code to a value ! 678: corresponding to the full-word result. ! 679: ! 680: ! 681: File: gcc.info, Node: Insn Lengths, Next: Constant Attributes, Prev: Attr Example, Up: Insn Attributes ! 682: ! 683: Computing the Length of an Insn ! 684: ------------------------------- ! 685: ! 686: For many machines, multiple types of branch instructions are ! 687: provided, each for different length branch displacements. In most ! 688: cases, the assembler will choose the correct instruction to use. ! 689: However, when the assembler cannot do so, GCC can when a special ! 690: attribute, the `length' attribute, is defined. This attribute must be ! 691: defined to have numeric values by specifying a null string in its ! 692: `define_attr'. ! 693: ! 694: In the case of the `length' attribute, two additional forms of ! 695: arithmetic terms are allowed in test expressions: ! 696: ! 697: `(match_dup N)' ! 698: This refers to the address of operand N of the current insn, which ! 699: must be a `label_ref'. ! 700: ! 701: `(pc)' ! 702: This refers to the address of the *current* insn. It might have ! 703: been more consistent with other usage to make this the address of ! 704: the *next* insn but this would be confusing because the length of ! 705: the current insn is to be computed. ! 706: ! 707: For normal insns, the length will be determined by value of the ! 708: `length' attribute. In the case of `addr_vec' and `addr_diff_vec' insn ! 709: patterns, the length will be computed as the number of vectors ! 710: multiplied by the size of each vector. ! 711: ! 712: The following macros can be used to refine the length computation: ! 713: ! 714: `FIRST_INSN_ADDRESS' ! 715: When the `length' insn attribute is used, this macro specifies the ! 716: value to be assigned to the address of the first insn in a ! 717: function. If not specified, 0 is used. ! 718: ! 719: `ADJUST_INSN_LENGTH (INSN, LENGTH)' ! 720: If defined, modifies the length assigned to instruction INSN as a ! 721: function of the context in which it is used. LENGTH is an lvalue ! 722: that contains the initially computed length of the insn and should ! 723: be updated with the correct length of the insn. If updating is ! 724: required, INSN must not be a varying-length insn. ! 725: ! 726: This macro will normally not be required. A case in which it is ! 727: required is the ROMP. On this machine, the size of an `addr_vec' ! 728: insn must be increased by two to compensate for the fact that ! 729: alignment may be required. ! 730: ! 731: The routine that returns the value of the `length' attribute, ! 732: `get_attr_length', can be used by the output routine to determine the ! 733: form of the branch instruction to be written, as the example below ! 734: illustrates. ! 735: ! 736: As an example of the specification of variable-length branches, ! 737: consider the IBM 360. If we adopt the convention that a register will ! 738: be set to the starting address of a function, we can jump to labels ! 739: within 4K of the start using a four-byte instruction. Otherwise, we ! 740: need a six-byte sequence to load the address from memory and then ! 741: branch to it. ! 742: ! 743: On such a machine, a pattern for a branch instruction might be ! 744: specified as follows: ! 745: ! 746: (define_insn "jump" ! 747: [(set (pc) ! 748: (label_ref (match_operand 0 "" "")))] ! 749: "" ! 750: "* ! 751: { ! 752: return (get_attr_length (insn) == 4 ! 753: ? \"b %l0\" : \"l r15,=a(%l0); br r15\"); ! 754: }" ! 755: [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096)) ! 756: (const_int 4) ! 757: (const_int 6)))]) ! 758: ! 759: ! 760: File: gcc.info, Node: Constant Attributes, Next: Delay Slots, Prev: Insn Lengths, Up: Insn Attributes ! 761: ! 762: Constant Attributes ! 763: ------------------- ! 764: ! 765: A special form of `define_attr', where the expression for the ! 766: default value is a `const' expression, indicates an attribute that is ! 767: constant for a given run of the compiler. Constant attributes may be ! 768: used to specify which variety of processor is used. For example, ! 769: ! 770: (define_attr "cpu" "m88100,m88110,m88000" ! 771: (const ! 772: (cond [(symbol_ref "TARGET_88100") (const_string "m88100") ! 773: (symbol_ref "TARGET_88110") (const_string "m88110")] ! 774: (const_string "m88000")))) ! 775: ! 776: (define_attr "memory" "fast,slow" ! 777: (const ! 778: (if_then_else (symbol_ref "TARGET_FAST_MEM") ! 779: (const_string "fast") ! 780: (const_string "slow")))) ! 781: ! 782: The routine generated for constant attributes has no parameters as it ! 783: does not depend on any particular insn. RTL expressions used to define ! 784: the value of a constant attribute may use the `symbol_ref' form, but ! 785: may not use either the `match_operand' form or `eq_attr' forms ! 786: involving insn attributes. ! 787: ! 788: ! 789: File: gcc.info, Node: Delay Slots, Next: Function Units, Prev: Constant Attributes, Up: Insn Attributes ! 790: ! 791: Delay Slot Scheduling ! 792: --------------------- ! 793: ! 794: The insn attribute mechanism can be used to specify the requirements ! 795: for delay slots, if any, on a target machine. An instruction is said to ! 796: require a "delay slot" if some instructions that are physically after ! 797: the instruction are executed as if they were located before it. Classic ! 798: examples are branch and call instructions, which often execute the ! 799: following instruction before the branch or call is performed. ! 800: ! 801: On some machines, conditional branch instructions can optionally ! 802: "annul" instructions in the delay slot. This means that the ! 803: instruction will not be executed for certain branch outcomes. Both ! 804: instructions that annul if the branch is true and instructions that ! 805: annul if the branch is false are supported. ! 806: ! 807: Delay slot scheduling differs from instruction scheduling in that ! 808: determining whether an instruction needs a delay slot is dependent only ! 809: on the type of instruction being generated, not on data flow between the ! 810: instructions. See the next section for a discussion of data-dependent ! 811: instruction scheduling. ! 812: ! 813: The requirement of an insn needing one or more delay slots is ! 814: indicated via the `define_delay' expression. It has the following form: ! 815: ! 816: (define_delay TEST ! 817: [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1 ! 818: DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2 ! 819: ...]) ! 820: ! 821: TEST is an attribute test that indicates whether this `define_delay' ! 822: applies to a particular insn. If so, the number of required delay ! 823: slots is determined by the length of the vector specified as the second ! 824: argument. An insn placed in delay slot N must satisfy attribute test ! 825: DELAY-N. ANNUL-TRUE-N is an attribute test that specifies which insns ! 826: may be annulled if the branch is true. Similarly, ANNUL-FALSE-N ! 827: specifies which insns in the delay slot may be annulled if the branch ! 828: is false. If annulling is not supported for that delay slot, `(nil)' ! 829: should be coded. ! 830: ! 831: For example, in the common case where branch and call insns require ! 832: a single delay slot, which may contain any insn other than a branch or ! 833: call, the following would be placed in the `md' file: ! 834: ! 835: (define_delay (eq_attr "type" "branch,call") ! 836: [(eq_attr "type" "!branch,call") (nil) (nil)]) ! 837: ! 838: Multiple `define_delay' expressions may be specified. In this case, ! 839: each such expression specifies different delay slot requirements and ! 840: there must be no insn for which tests in two `define_delay' expressions ! 841: are both true. ! 842: ! 843: For example, if we have a machine that requires one delay slot for ! 844: branches but two for calls, no delay slot can contain a branch or call ! 845: insn, and any valid insn in the delay slot for the branch can be ! 846: annulled if the branch is true, we might represent this as follows: ! 847: ! 848: (define_delay (eq_attr "type" "branch") ! 849: [(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)]) ! 850: ! 851: (define_delay (eq_attr "type" "call") ! 852: [(eq_attr "type" "!branch,call") (nil) (nil) ! 853: (eq_attr "type" "!branch,call") (nil) (nil)]) ! 854: ! 855: ! 856: File: gcc.info, Node: Function Units, Prev: Delay Slots, Up: Insn Attributes ! 857: ! 858: Specifying Function Units ! 859: ------------------------- ! 860: ! 861: On most RISC machines, there are instructions whose results are not ! 862: available for a specific number of cycles. Common cases are ! 863: instructions that load data from memory. On many machines, a pipeline ! 864: stall will result if the data is referenced too soon after the load ! 865: instruction. ! 866: ! 867: In addition, many newer microprocessors have multiple function ! 868: units, usually one for integer and one for floating point, and often ! 869: will incur pipeline stalls when a result that is needed is not yet ! 870: ready. ! 871: ! 872: The descriptions in this section allow the specification of how much ! 873: time must elapse between the execution of an instruction and the time ! 874: when its result is used. It also allows specification of when the ! 875: execution of an instruction will delay execution of similar instructions ! 876: due to function unit conflicts. ! 877: ! 878: For the purposes of the specifications in this section, a machine is ! 879: divided into "function units", each of which execute a specific class ! 880: of instructions in first-in-first-out order. Function units that ! 881: accept one instruction each cycle and allow a result to be used in the ! 882: succeeding instruction (usually via forwarding) need not be specified. ! 883: Classic RISC microprocessors will normally have a single function unit, ! 884: which we can call `memory'. The newer "superscalar" processors will ! 885: often have function units for floating point operations, usually at ! 886: least a floating point adder and multiplier. ! 887: ! 888: Each usage of a function units by a class of insns is specified with ! 889: a `define_function_unit' expression, which looks like this: ! 890: ! 891: (define_function_unit NAME MULTIPLICITY SIMULTANEITY ! 892: TEST READY-DELAY ISSUE-DELAY ! 893: [CONFLICT-LIST]) ! 894: ! 895: NAME is a string giving the name of the function unit. ! 896: ! 897: MULTIPLICITY is an integer specifying the number of identical units ! 898: in the processor. If more than one unit is specified, they will be ! 899: scheduled independently. Only truly independent units should be ! 900: counted; a pipelined unit should be specified as a single unit. (The ! 901: only common example of a machine that has multiple function units for a ! 902: single instruction class that are truly independent and not pipelined ! 903: are the two multiply and two increment units of the CDC 6600.) ! 904: ! 905: SIMULTANEITY specifies the maximum number of insns that can be ! 906: executing in each instance of the function unit simultaneously or zero ! 907: if the unit is pipelined and has no limit. ! 908: ! 909: All `define_function_unit' definitions referring to function unit ! 910: NAME must have the same name and values for MULTIPLICITY and ! 911: SIMULTANEITY. ! 912: ! 913: TEST is an attribute test that selects the insns we are describing ! 914: in this definition. Note that an insn may use more than one function ! 915: unit and a function unit may be specified in more than one ! 916: `define_function_unit'. ! 917: ! 918: READY-DELAY is an integer that specifies the number of cycles after ! 919: which the result of the instruction can be used without introducing any ! 920: stalls. ! 921: ! 922: ISSUE-DELAY is an integer that specifies the number of cycles after ! 923: the instruction matching the TEST expression begins using this unit ! 924: until a subsequent instruction can begin. A cost of N indicates an N-1 ! 925: cycle delay. A subsequent instruction may also be delayed if an ! 926: earlier instruction has a longer READY-DELAY value. This blocking ! 927: effect is computed using the SIMULTANEITY, READY-DELAY, ISSUE-DELAY, ! 928: and CONFLICT-LIST terms. For a normal non-pipelined function unit, ! 929: SIMULTANEITY is one, the unit is taken to block for the READY-DELAY ! 930: cycles of the executing insn, and smaller values of ISSUE-DELAY are ! 931: ignored. ! 932: ! 933: CONFLICT-LIST is an optional list giving detailed conflict costs for ! 934: this unit. If specified, it is a list of condition test expressions to ! 935: be applied to insns chosen to execute in NAME following the particular ! 936: insn matching TEST that is already executing in NAME. For each insn in ! 937: the list, ISSUE-DELAY specifies the conflict cost; for insns not in the ! 938: list, the cost is zero. If not specified, CONFLICT-LIST defaults to ! 939: all instructions that use the function unit. ! 940: ! 941: Typical uses of this vector are where a floating point function unit ! 942: can pipeline either single- or double-precision operations, but not ! 943: both, or where a memory unit can pipeline loads, but not stores, etc. ! 944: ! 945: As an example, consider a classic RISC machine where the result of a ! 946: load instruction is not available for two cycles (a single "delay" ! 947: instruction is required) and where only one load instruction can be ! 948: executed simultaneously. This would be specified as: ! 949: ! 950: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0) ! 951: ! 952: For the case of a floating point function unit that can pipeline ! 953: either single or double precision, but not both, the following could be ! 954: specified: ! 955: ! 956: (define_function_unit ! 957: "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")]) ! 958: (define_function_unit ! 959: "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")]) ! 960: ! 961: *Note:* The scheduler attempts to avoid function unit conflicts and ! 962: uses all the specifications in the `define_function_unit' expression. ! 963: It has recently come to our attention that these specifications may not ! 964: allow modeling of some of the newer "superscalar" processors that have ! 965: insns using multiple pipelined units. These insns will cause a ! 966: potential conflict for the second unit used during their execution and ! 967: there is no way of representing that conflict. We welcome any examples ! 968: of how function unit conflicts work in such processors and suggestions ! 969: for their representation. ! 970: ! 971: ! 972: File: gcc.info, Node: Target Macros, Next: Config, Prev: Machine Desc, Up: Top ! 973: ! 974: Target Description Macros ! 975: ************************* ! 976: ! 977: In addition to the file `MACHINE.md', a machine description includes ! 978: a C header file conventionally given the name `MACHINE.h'. This header ! 979: file defines numerous macros that convey the information about the ! 980: target machine that does not fit into the scheme of the `.md' file. ! 981: The file `tm.h' should be a link to `MACHINE.h'. The header file ! 982: `config.h' includes `tm.h' and most compiler source files include ! 983: `config.h'. 1.1.1.3 root 984: 1.1.1.4 ! root 985: * Menu: 1.1 root 986: 1.1.1.4 ! root 987: * Driver:: Controlling how the driver runs the compilation passes. ! 988: * Run-time Target:: Defining `-m' options like `-m68000' and `-m68020'. ! 989: * Storage Layout:: Defining sizes and alignments of data. ! 990: * Type Layout:: Defining sizes and properties of basic user data types. ! 991: * Registers:: Naming and describing the hardware registers. ! 992: * Register Classes:: Defining the classes of hardware registers. ! 993: * Stack and Calling:: Defining which way the stack grows and by how much. ! 994: * Varargs:: Defining the varargs macros. ! 995: * Trampolines:: Code set up at run time to enter a nested function. ! 996: * Library Calls:: Controlling how library routines are implicitly called. ! 997: * Addressing Modes:: Defining addressing modes valid for memory operands. ! 998: * Condition Code:: Defining how insns update the condition code. ! 999: * Costs:: Defining relative costs of different operations. ! 1000: * Sections:: Dividing storage into text, data, and other sections. ! 1001: * PIC:: Macros for position independent code. ! 1002: * Assembler Format:: Defining how to write insns and pseudo-ops to output. ! 1003: * Debugging Info:: Defining the format of debugging output. ! 1004: * Cross-compilation:: Handling floating point for cross-compilers. ! 1005: * Misc:: Everything else. 1.1 root 1006: 1007:
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