--- gcc/gcc.info-17 2018/04/24 17:52:17 1.1.1.2 +++ gcc/gcc.info-17 2018/04/24 18:24:36 1.1.1.8 @@ -1,1627 +1,1107 @@ -This is Info file gcc.info, produced by Makeinfo-1.44 from the input +This is Info file gcc.info, produced by Makeinfo-1.55 from the input file gcc.texi. This file documents the use and the internals of the GNU compiler. - Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc. + Published by the Free Software Foundation 59 Temple Place - Suite 330 +Boston, MA 02111-1307 USA - Permission is granted to make and distribute verbatim copies of -this manual provided the copyright notice and this permission notice -are preserved on all copies. + Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995 Free Software +Foundation, Inc. + + Permission is granted to make and distribute verbatim copies of this +manual provided the copyright notice and this permission notice are +preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided also -that the section entitled "GNU General Public License" is included -exactly as in the original, and provided that the entire resulting -derived work is distributed under the terms of a permission notice -identical to this one. +that the sections entitled "GNU General Public License," "Funding for +Free Software," and "Protect Your Freedom--Fight `Look And Feel'" are +included exactly as in the original, and provided that the entire +resulting derived work is distributed under the terms of a permission +notice identical to this one. Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified -versions, except that the section entitled "GNU General Public -License" and this permission notice may be included in translations -approved by the Free Software Foundation instead of in the original -English. +versions, except that the sections entitled "GNU General Public +License," "Funding for Free Software," and "Protect Your Freedom--Fight +`Look And Feel'", and this permission notice, may be included in +translations approved by the Free Software Foundation instead of in the +original English.  -File: gcc.info, Node: Index, Prev: Config, Up: Top +File: gcc.info, Node: Standard Names, Next: Pattern Ordering, Prev: Constraints, Up: Machine Desc + +Standard Pattern Names For Generation +===================================== + + Here is a table of the instruction names that are meaningful in the +RTL generation pass of the compiler. Giving one of these names to an +instruction pattern tells the RTL generation pass that it can use the +pattern in to accomplish a certain task. + +`movM' + Here M stands for a two-letter machine mode name, in lower case. + This instruction pattern moves data with that machine mode from + operand 1 to operand 0. For example, `movsi' moves full-word data. + + If operand 0 is a `subreg' with mode M of a register whose own + mode is wider than M, the effect of this instruction is to store + the specified value in the part of the register that corresponds + to mode M. The effect on the rest of the register is undefined. + + This class of patterns is special in several ways. First of all, + each of these names *must* be defined, because there is no other + way to copy a datum from one place to another. + + Second, these patterns are not used solely in the RTL generation + pass. Even the reload pass can generate move insns to copy values + from stack slots into temporary registers. When it does so, one + of the operands is a hard register and the other is an operand + that can need to be reloaded into a register. + + Therefore, when given such a pair of operands, the pattern must + generate RTL which needs no reloading and needs no temporary + registers--no registers other than the operands. For example, if + you support the pattern with a `define_expand', then in such a + case the `define_expand' mustn't call `force_reg' or any other such + function which might generate new pseudo registers. + + This requirement exists even for subword modes on a RISC machine + where fetching those modes from memory normally requires several + insns and some temporary registers. Look in `spur.md' to see how + the requirement can be satisfied. + + During reload a memory reference with an invalid address may be + passed as an operand. Such an address will be replaced with a + valid address later in the reload pass. In this case, nothing may + be done with the address except to use it as it stands. If it is + copied, it will not be replaced with a valid address. No attempt + should be made to make such an address into a valid address and no + routine (such as `change_address') that will do so may be called. + Note that `general_operand' will fail when applied to such an + address. + + The global variable `reload_in_progress' (which must be explicitly + declared if required) can be used to determine whether such special + handling is required. + + The variety of operands that have reloads depends on the rest of + the machine description, but typically on a RISC machine these can + only be pseudo registers that did not get hard registers, while on + other machines explicit memory references will get optional + reloads. + + If a scratch register is required to move an object to or from + memory, it can be allocated using `gen_reg_rtx' prior to reload. + But this is impossible during and after reload. If there are + cases needing scratch registers after reload, you must define + `SECONDARY_INPUT_RELOAD_CLASS' and perhaps also + `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide + patterns `reload_inM' or `reload_outM' to handle them. *Note + Register Classes::. + + The constraints on a `moveM' must permit moving any hard register + to any other hard register provided that `HARD_REGNO_MODE_OK' + permits mode M in both registers and `REGISTER_MOVE_COST' applied + to their classes returns a value of 2. + + It is obligatory to support floating point `moveM' instructions + into and out of any registers that can hold fixed point values, + because unions and structures (which have modes `SImode' or + `DImode') can be in those registers and they may have floating + point members. + + There may also be a need to support fixed point `moveM' + instructions in and out of floating point registers. + Unfortunately, I have forgotten why this was so, and I don't know + whether it is still true. If `HARD_REGNO_MODE_OK' rejects fixed + point values in floating point registers, then the constraints of + the fixed point `moveM' instructions must be designed to avoid + ever trying to reload into a floating point register. + +`reload_inM' +`reload_outM' + Like `movM', but used when a scratch register is required to move + between operand 0 and operand 1. Operand 2 describes the scratch + register. See the discussion of the `SECONDARY_RELOAD_CLASS' + macro in *note Register Classes::.. + +`movstrictM' + Like `movM' except that if operand 0 is a `subreg' with mode M of + a register whose natural mode is wider, the `movstrictM' + instruction is guaranteed not to alter any of the register except + the part which belongs to mode M. + +`load_multiple' + Load several consecutive memory locations into consecutive + registers. Operand 0 is the first of the consecutive registers, + operand 1 is the first memory location, and operand 2 is a + constant: the number of consecutive registers. + + Define this only if the target machine really has such an + instruction; do not define this if the most efficient way of + loading consecutive registers from memory is to do them one at a + time. + + On some machines, there are restrictions as to which consecutive + registers can be stored into memory, such as particular starting or + ending register numbers or only a range of valid counts. For those + machines, use a `define_expand' (*note Expander Definitions::.) + and make the pattern fail if the restrictions are not met. + + Write the generated insn as a `parallel' with elements being a + `set' of one register from the appropriate memory location (you may + also need `use' or `clobber' elements). Use a `match_parallel' + (*note RTL Template::.) to recognize the insn. See `a29k.md' and + `rs6000.md' for examples of the use of this insn pattern. + +`store_multiple' + Similar to `load_multiple', but store several consecutive registers + into consecutive memory locations. Operand 0 is the first of the + consecutive memory locations, operand 1 is the first register, and + operand 2 is a constant: the number of consecutive registers. + +`addM3' + Add operand 2 and operand 1, storing the result in operand 0. All + operands must have mode M. This can be used even on two-address + machines, by means of constraints requiring operands 1 and 0 to be + the same location. + +`subM3', `mulM3' +`divM3', `udivM3', `modM3', `umodM3' +`sminM3', `smaxM3', `uminM3', `umaxM3' +`andM3', `iorM3', `xorM3' + Similar, for other arithmetic operations. + +`mulhisi3' + Multiply operands 1 and 2, which have mode `HImode', and store a + `SImode' product in operand 0. + +`mulqihi3', `mulsidi3' + Similar widening-multiplication instructions of other widths. + +`umulqihi3', `umulhisi3', `umulsidi3' + Similar widening-multiplication instructions that do unsigned + multiplication. + +`mulM3_highpart' + Perform a signed multiplication of operands 1 and 2, which have + mode M, and store the most significant half of the product in + operand 0. The least significant half of the product is discarded. + +`umulM3_highpart' + Similar, but the multiplication is unsigned. + +`divmodM4' + Signed division that produces both a quotient and a remainder. + Operand 1 is divided by operand 2 to produce a quotient stored in + operand 0 and a remainder stored in operand 3. + + For machines with an instruction that produces both a quotient and + a remainder, provide a pattern for `divmodM4' but do not provide + patterns for `divM3' and `modM3'. This allows optimization in the + relatively common case when both the quotient and remainder are + computed. + + If an instruction that just produces a quotient or just a remainder + exists and is more efficient than the instruction that produces + both, write the output routine of `divmodM4' to call + `find_reg_note' and look for a `REG_UNUSED' note on the quotient + or remainder and generate the appropriate instruction. + +`udivmodM4' + Similar, but does unsigned division. + +`ashlM3' + Arithmetic-shift operand 1 left by a number of bits specified by + operand 2, and store the result in operand 0. Here M is the mode + of operand 0 and operand 1; operand 2's mode is specified by the + instruction pattern, and the compiler will convert the operand to + that mode before generating the instruction. + +`ashrM3', `lshrM3', `rotlM3', `rotrM3' + Other shift and rotate instructions, analogous to the `ashlM3' + instructions. + +`negM2' + Negate operand 1 and store the result in operand 0. + +`absM2' + Store the absolute value of operand 1 into operand 0. + +`sqrtM2' + Store the square root of operand 1 into operand 0. + + The `sqrt' built-in function of C always uses the mode which + corresponds to the C data type `double'. + +`ffsM2' + Store into operand 0 one plus the index of the least significant + 1-bit of operand 1. If operand 1 is zero, store zero. M is the + mode of operand 0; operand 1's mode is specified by the instruction + pattern, and the compiler will convert the operand to that mode + before generating the instruction. + + The `ffs' built-in function of C always uses the mode which + corresponds to the C data type `int'. + +`one_cmplM2' + Store the bitwise-complement of operand 1 into operand 0. + +`cmpM' + Compare operand 0 and operand 1, and set the condition codes. The + RTL pattern should look like this: + + (set (cc0) (compare (match_operand:M 0 ...) + (match_operand:M 1 ...))) + +`tstM' + Compare operand 0 against zero, and set the condition codes. The + RTL pattern should look like this: + + (set (cc0) (match_operand:M 0 ...)) + + `tstM' patterns should not be defined for machines that do not use + `(cc0)'. Doing so would confuse the optimizer since it would no + longer be clear which `set' operations were comparisons. The + `cmpM' patterns should be used instead. + +`movstrM' + Block move instruction. The addresses of the destination and + source strings are the first two operands, and both are in mode + `Pmode'. The number of bytes to move is the third operand, in + mode M. + + The fourth operand is the known shared alignment of the source and + destination, in the form of a `const_int' rtx. Thus, if the + compiler knows that both source and destination are word-aligned, + it may provide the value 4 for this operand. + + These patterns need not give special consideration to the + possibility that the source and destination strings might overlap. + +`cmpstrM' + Block compare instruction, with five operands. Operand 0 is the + output; it has mode M. The remaining four operands are like the + operands of `movstrM'. The two memory blocks specified are + compared byte by byte in lexicographic order. The effect of the + instruction is to store a value in operand 0 whose sign indicates + the result of the comparison. + + Compute the length of a string, with three operands. Operand 0 is + the result (of mode M), operand 1 is a `mem' referring to the + first character of the string, operand 2 is the character to + search for (normally zero), and operand 3 is a constant describing + the known alignment of the beginning of the string. + +`floatMN2' + Convert signed integer operand 1 (valid for fixed point mode M) to + floating point mode N and store in operand 0 (which has mode N). + +`floatunsMN2' + Convert unsigned integer operand 1 (valid for fixed point mode M) + to floating point mode N and store in operand 0 (which has mode N). + +`fixMN2' + Convert operand 1 (valid for floating point mode M) to fixed point + mode N as a signed number and store in operand 0 (which has mode + N). This instruction's result is defined only when the value of + operand 1 is an integer. + +`fixunsMN2' + Convert operand 1 (valid for floating point mode M) to fixed point + mode N as an unsigned number and store in operand 0 (which has + mode N). This instruction's result is defined only when the value + of operand 1 is an integer. + +`ftruncM2' + Convert operand 1 (valid for floating point mode M) to an integer + value, still represented in floating point mode M, and store it in + operand 0 (valid for floating point mode M). + +`fix_truncMN2' + Like `fixMN2' but works for any floating point value of mode M by + converting the value to an integer. + +`fixuns_truncMN2' + Like `fixunsMN2' but works for any floating point value of mode M + by converting the value to an integer. + +`truncMN' + Truncate operand 1 (valid for mode M) to mode N and store in + operand 0 (which has mode N). Both modes must be fixed point or + both floating point. + +`extendMN' + Sign-extend operand 1 (valid for mode M) to mode N and store in + operand 0 (which has mode N). Both modes must be fixed point or + both floating point. + +`zero_extendMN' + Zero-extend operand 1 (valid for mode M) to mode N and store in + operand 0 (which has mode N). Both modes must be fixed point. + +`extv' + Extract a bit field from operand 1 (a register or memory operand), + where operand 2 specifies the width in bits and operand 3 the + starting bit, and store it in operand 0. Operand 0 must have mode + `word_mode'. Operand 1 may have mode `byte_mode' or `word_mode'; + often `word_mode' is allowed only for registers. Operands 2 and 3 + must be valid for `word_mode'. + + The RTL generation pass generates this instruction only with + constants for operands 2 and 3. + + The bit-field value is sign-extended to a full word integer before + it is stored in operand 0. + +`extzv' + Like `extv' except that the bit-field value is zero-extended. + +`insv' + Store operand 3 (which must be valid for `word_mode') into a bit + field in operand 0, where operand 1 specifies the width in bits and + operand 2 the starting bit. Operand 0 may have mode `byte_mode' or + `word_mode'; often `word_mode' is allowed only for registers. + Operands 1 and 2 must be valid for `word_mode'. + + The RTL generation pass generates this instruction only with + constants for operands 1 and 2. + +`movMODEcc' + Conditionally move operand 2 or operand 3 into operand 0 according + to the comparison in operand 1. If the comparison is true, + operand 2 is moved into operand 0, otherwise operand 3 is moved. + + The mode of the operands being compared need not be the same as + the operands being moved. Some machines, sparc64 for example, + have instructions that conditionally move an integer value based + on the floating point condition codes and vice versa. + + If the machine does not have conditional move instructions, do not + define these patterns. + +`sCOND' + Store zero or nonzero in the operand according to the condition + codes. Value stored is nonzero iff the condition COND is true. + cOND is the name of a comparison operation expression code, such + as `eq', `lt' or `leu'. + + You specify the mode that the operand must have when you write the + `match_operand' expression. The compiler automatically sees which + mode you have used and supplies an operand of that mode. + + The value stored for a true condition must have 1 as its low bit, + or else must be negative. Otherwise the instruction is not + suitable and you should omit it from the machine description. You + describe to the compiler exactly which value is stored by defining + the macro `STORE_FLAG_VALUE' (*note Misc::.). If a description + cannot be found that can be used for all the `sCOND' patterns, you + should omit those operations from the machine description. + + These operations may fail, but should do so only in relatively + uncommon cases; if they would fail for common cases involving + integer comparisons, it is best to omit these patterns. + + If these operations are omitted, the compiler will usually + generate code that copies the constant one to the target and + branches around an assignment of zero to the target. If this code + is more efficient than the potential instructions used for the + `sCOND' pattern followed by those required to convert the result + into a 1 or a zero in `SImode', you should omit the `sCOND' + operations from the machine description. + +`bCOND' + Conditional branch instruction. Operand 0 is a `label_ref' that + refers to the label to jump to. Jump if the condition codes meet + condition COND. + + Some machines do not follow the model assumed here where a + comparison instruction is followed by a conditional branch + instruction. In that case, the `cmpM' (and `tstM') patterns should + simply store the operands away and generate all the required insns + in a `define_expand' (*note Expander Definitions::.) for the + conditional branch operations. All calls to expand `bCOND' + patterns are immediately preceded by calls to expand either a + `cmpM' pattern or a `tstM' pattern. + + Machines that use a pseudo register for the condition code value, + or where the mode used for the comparison depends on the condition + being tested, should also use the above mechanism. *Note Jump + Patterns:: + + The above discussion also applies to the `movMODEcc' and `sCOND' + patterns. + +`call' + Subroutine call instruction returning no value. Operand 0 is the + function to call; operand 1 is the number of bytes of arguments + pushed (in mode `SImode', except it is normally a `const_int'); + operand 2 is the number of registers used as operands. + + On most machines, operand 2 is not actually stored into the RTL + pattern. It is supplied for the sake of some RISC machines which + need to put this information into the assembler code; they can put + it in the RTL instead of operand 1. + + Operand 0 should be a `mem' RTX whose address is the address of the + function. Note, however, that this address can be a `symbol_ref' + expression even if it would not be a legitimate memory address on + the target machine. If it is also not a valid argument for a call + instruction, the pattern for this operation should be a + `define_expand' (*note Expander Definitions::.) that places the + address into a register and uses that register in the call + instruction. + +`call_value' + Subroutine call instruction returning a value. Operand 0 is the + hard register in which the value is returned. There are three more + operands, the same as the three operands of the `call' instruction + (but with numbers increased by one). + + Subroutines that return `BLKmode' objects use the `call' insn. + +`call_pop', `call_value_pop' + Similar to `call' and `call_value', except used if defined and if + `RETURN_POPS_ARGS' is non-zero. They should emit a `parallel' + that contains both the function call and a `set' to indicate the + adjustment made to the frame pointer. + + For machines where `RETURN_POPS_ARGS' can be non-zero, the use of + these patterns increases the number of functions for which the + frame pointer can be eliminated, if desired. + +`untyped_call' + Subroutine call instruction returning a value of any type. + Operand 0 is the function to call; operand 1 is a memory location + where the result of calling the function is to be stored; operand + 2 is a `parallel' expression where each element is a `set' + expression that indicates the saving of a function return value + into the result block. + + This instruction pattern should be defined to support + `__builtin_apply' on machines where special instructions are needed + to call a subroutine with arbitrary arguments or to save the value + returned. This instruction pattern is required on machines that + have multiple registers that can hold a return value (i.e. + `FUNCTION_VALUE_REGNO_P' is true for more than one register). + +`return' + Subroutine return instruction. This instruction pattern name + should be defined only if a single instruction can do all the work + of returning from a function. + + Like the `movM' patterns, this pattern is also used after the RTL + generation phase. In this case it is to support machines where + multiple instructions are usually needed to return from a + function, but some class of functions only requires one + instruction to implement a return. Normally, the applicable + functions are those which do not need to save any registers or + allocate stack space. + + For such machines, the condition specified in this pattern should + only be true when `reload_completed' is non-zero and the function's + epilogue would only be a single instruction. For machines with + register windows, the routine `leaf_function_p' may be used to + determine if a register window push is required. + + Machines that have conditional return instructions should define + patterns such as + + (define_insn "" + [(set (pc) + (if_then_else (match_operator + 0 "comparison_operator" + [(cc0) (const_int 0)]) + (return) + (pc)))] + "CONDITION" + "...") + + where CONDITION would normally be the same condition specified on + the named `return' pattern. + +`untyped_return' + Untyped subroutine return instruction. This instruction pattern + should be defined to support `__builtin_return' on machines where + special instructions are needed to return a value of any type. + + Operand 0 is a memory location where the result of calling a + function with `__builtin_apply' is stored; operand 1 is a + `parallel' expression where each element is a `set' expression + that indicates the restoring of a function return value from the + result block. + +`nop' + No-op instruction. This instruction pattern name should always be + defined to output a no-op in assembler code. `(const_int 0)' will + do as an RTL pattern. + +`indirect_jump' + An instruction to jump to an address which is operand zero. This + pattern name is mandatory on all machines. + +`casesi' + Instruction to jump through a dispatch table, including bounds + checking. This instruction takes five operands: + + 1. The index to dispatch on, which has mode `SImode'. + + 2. The lower bound for indices in the table, an integer constant. + + 3. The total range of indices in the table--the largest index + minus the smallest one (both inclusive). + + 4. A label that precedes the table itself. + + 5. A label to jump to if the index has a value outside the + bounds. (If the machine-description macro + `CASE_DROPS_THROUGH' is defined, then an out-of-bounds index + drops through to the code following the jump table instead of + jumping to this label. In that case, this label is not + actually used by the `casesi' instruction, but it is always + provided as an operand.) + + The table is a `addr_vec' or `addr_diff_vec' inside of a + `jump_insn'. The number of elements in the table is one plus the + difference between the upper bound and the lower bound. + +`tablejump' + Instruction to jump to a variable address. This is a low-level + capability which can be used to implement a dispatch table when + there is no `casesi' pattern. + + This pattern requires two operands: the address or offset, and a + label which should immediately precede the jump table. If the + macro `CASE_VECTOR_PC_RELATIVE' is defined then the first operand + is an offset which counts from the address of the table; + otherwise, it is an absolute address to jump to. In either case, + the first operand has mode `Pmode'. + + The `tablejump' insn is always the last insn before the jump table + it uses. Its assembler code normally has no need to use the + second operand, but you should incorporate it in the RTL pattern so + that the jump optimizer will not delete the table as unreachable + code. + +`save_stack_block' +`save_stack_function' +`save_stack_nonlocal' +`restore_stack_block' +`restore_stack_function' +`restore_stack_nonlocal' + Most machines save and restore the stack pointer by copying it to + or from an object of mode `Pmode'. Do not define these patterns on + such machines. + + Some machines require special handling for stack pointer saves and + restores. On those machines, define the patterns corresponding to + the non-standard cases by using a `define_expand' (*note Expander + Definitions::.) that produces the required insns. The three types + of saves and restores are: + + 1. `save_stack_block' saves the stack pointer at the start of a + block that allocates a variable-sized object, and + `restore_stack_block' restores the stack pointer when the + block is exited. + + 2. `save_stack_function' and `restore_stack_function' do a + similar job for the outermost block of a function and are + used when the function allocates variable-sized objects or + calls `alloca'. Only the epilogue uses the restored stack + pointer, allowing a simpler save or restore sequence on some + machines. + + 3. `save_stack_nonlocal' is used in functions that contain labels + branched to by nested functions. It saves the stack pointer + in such a way that the inner function can use + `restore_stack_nonlocal' to restore the stack pointer. The + compiler generates code to restore the frame and argument + pointer registers, but some machines require saving and + restoring additional data such as register window information + or stack backchains. Place insns in these patterns to save + and restore any such required data. + + When saving the stack pointer, operand 0 is the save area and + operand 1 is the stack pointer. The mode used to allocate the + save area is the mode of operand 0. You must specify an integral + mode, or `VOIDmode' if no save area is needed for a particular + type of save (either because no save is needed or because a + machine-specific save area can be used). Operand 0 is the stack + pointer and operand 1 is the save area for restore operations. If + `save_stack_block' is defined, operand 0 must not be `VOIDmode' + since these saves can be arbitrarily nested. + + A save area is a `mem' that is at a constant offset from + `virtual_stack_vars_rtx' when the stack pointer is saved for use by + nonlocal gotos and a `reg' in the other two cases. + +`allocate_stack' + Subtract (or add if `STACK_GROWS_DOWNWARD' is undefined) operand 0 + from the stack pointer to create space for dynamically allocated + data. + + Do not define this pattern if all that must be done is the + subtraction. Some machines require other operations such as stack + probes or maintaining the back chain. Define this pattern to emit + those operations in addition to updating the stack pointer. + + +File: gcc.info, Node: Pattern Ordering, Next: Dependent Patterns, Prev: Standard Names, Up: Machine Desc + +When the Order of Patterns Matters +================================== + + Sometimes an insn can match more than one instruction pattern. Then +the pattern that appears first in the machine description is the one +used. Therefore, more specific patterns (patterns that will match +fewer things) and faster instructions (those that will produce better +code when they do match) should usually go first in the description. + + In some cases the effect of ordering the patterns can be used to hide +a pattern when it is not valid. For example, the 68000 has an +instruction for converting a fullword to floating point and another for +converting a byte to floating point. An instruction converting an +integer to floating point could match either one. We put the pattern +to convert the fullword first to make sure that one will be used rather +than the other. (Otherwise a large integer might be generated as a +single-byte immediate quantity, which would not work.) Instead of using +this pattern ordering it would be possible to make the pattern for +convert-a-byte smart enough to deal properly with any constant value. + + +File: gcc.info, Node: Dependent Patterns, Next: Jump Patterns, Prev: Pattern Ordering, Up: Machine Desc + +Interdependence of Patterns +=========================== + + Every machine description must have a named pattern for each of the +conditional branch names `bCOND'. The recognition template must always +have the form + + (set (pc) + (if_then_else (COND (cc0) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + +In addition, every machine description must have an anonymous pattern +for each of the possible reverse-conditional branches. Their templates +look like + + (set (pc) + (if_then_else (COND (cc0) (const_int 0)) + (pc) + (label_ref (match_operand 0 "" "")))) + +They are necessary because jump optimization can turn direct-conditional +branches into reverse-conditional branches. + + It is often convenient to use the `match_operator' construct to +reduce the number of patterns that must be specified for branches. For +example, + + (define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(cc0) (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "CONDITION" + "...") + + In some cases machines support instructions identical except for the +machine mode of one or more operands. For example, there may be +"sign-extend halfword" and "sign-extend byte" instructions whose +patterns are + + (set (match_operand:SI 0 ...) + (extend:SI (match_operand:HI 1 ...))) + + (set (match_operand:SI 0 ...) + (extend:SI (match_operand:QI 1 ...))) + +Constant integers do not specify a machine mode, so an instruction to +extend a constant value could match either pattern. The pattern it +actually will match is the one that appears first in the file. For +correct results, this must be the one for the widest possible mode +(`HImode', here). If the pattern matches the `QImode' instruction, the +results will be incorrect if the constant value does not actually fit +that mode. + + Such instructions to extend constants are rarely generated because +they are optimized away, but they do occasionally happen in nonoptimized +compilations. + + If a constraint in a pattern allows a constant, the reload pass may +replace a register with a constant permitted by the constraint in some +cases. Similarly for memory references. Because of this substitution, +you should not provide separate patterns for increment and decrement +instructions. Instead, they should be generated from the same pattern +that supports register-register add insns by examining the operands and +generating the appropriate machine instruction. + + +File: gcc.info, Node: Jump Patterns, Next: Insn Canonicalizations, Prev: Dependent Patterns, Up: Machine Desc + +Defining Jump Instruction Patterns +================================== + + For most machines, GNU CC assumes that the machine has a condition +code. A comparison insn sets the condition code, recording the results +of both signed and unsigned comparison of the given operands. A +separate branch insn tests the condition code and branches or not +according its value. The branch insns come in distinct signed and +unsigned flavors. Many common machines, such as the Vax, the 68000 and +the 32000, work this way. + + Some machines have distinct signed and unsigned compare +instructions, and only one set of conditional branch instructions. The +easiest way to handle these machines is to treat them just like the +others until the final stage where assembly code is written. At this +time, when outputting code for the compare instruction, peek ahead at +the following branch using `next_cc0_user (insn)'. (The variable +`insn' refers to the insn being output, in the output-writing code in +an instruction pattern.) If the RTL says that is an unsigned branch, +output an unsigned compare; otherwise output a signed compare. When +the branch itself is output, you can treat signed and unsigned branches +identically. + + The reason you can do this is that GNU CC always generates a pair of +consecutive RTL insns, possibly separated by `note' insns, one to set +the condition code and one to test it, and keeps the pair inviolate +until the end. + + To go with this technique, you must define the machine-description +macro `NOTICE_UPDATE_CC' to do `CC_STATUS_INIT'; in other words, no +compare instruction is superfluous. + + Some machines have compare-and-branch instructions and no condition +code. A similar technique works for them. When it is time to "output" +a compare instruction, record its operands in two static variables. +When outputting the branch-on-condition-code instruction that follows, +actually output a compare-and-branch instruction that uses the +remembered operands. + + It also works to define patterns for compare-and-branch instructions. +In optimizing compilation, the pair of compare and branch instructions +will be combined according to these patterns. But this does not happen +if optimization is not requested. So you must use one of the solutions +above in addition to any special patterns you define. + + In many RISC machines, most instructions do not affect the condition +code and there may not even be a separate condition code register. On +these machines, the restriction that the definition and use of the +condition code be adjacent insns is not necessary and can prevent +important optimizations. For example, on the IBM RS/6000, there is a +delay for taken branches unless the condition code register is set three +instructions earlier than the conditional branch. The instruction +scheduler cannot perform this optimization if it is not permitted to +separate the definition and use of the condition code register. + + On these machines, do not use `(cc0)', but instead use a register to +represent the condition code. If there is a specific condition code +register in the machine, use a hard register. If the condition code or +comparison result can be placed in any general register, or if there are +multiple condition registers, use a pseudo register. + + On some machines, the type of branch instruction generated may +depend on the way the condition code was produced; for example, on the +68k and Sparc, setting the condition code directly from an add or +subtract instruction does not clear the overflow bit the way that a test +instruction does, so a different branch instruction must be used for +some conditional branches. For machines that use `(cc0)', the set and +use of the condition code must be adjacent (separated only by `note' +insns) allowing flags in `cc_status' to be used. (*Note Condition +Code::.) Also, the comparison and branch insns can be located from +each other by using the functions `prev_cc0_setter' and `next_cc0_user'. + + However, this is not true on machines that do not use `(cc0)'. On +those machines, no assumptions can be made about the adjacency of the +compare and branch insns and the above methods cannot be used. Instead, +we use the machine mode of the condition code register to record +different formats of the condition code register. + + Registers used to store the condition code value should have a mode +that is in class `MODE_CC'. Normally, it will be `CCmode'. If +additional modes are required (as for the add example mentioned above in +the Sparc), define the macro `EXTRA_CC_MODES' to list the additional +modes required (*note Condition Code::.). Also define `EXTRA_CC_NAMES' +to list the names of those modes and `SELECT_CC_MODE' to choose a mode +given an operand of a compare. + + If it is known during RTL generation that a different mode will be +required (for example, if the machine has separate compare instructions +for signed and unsigned quantities, like most IBM processors), they can +be specified at that time. + + If the cases that require different modes would be made by +instruction combination, the macro `SELECT_CC_MODE' determines which +machine mode should be used for the comparison result. The patterns +should be written using that mode. To support the case of the add on +the Sparc discussed above, we have the pattern + + (define_insn "" + [(set (reg:CC_NOOV 0) + (compare:CC_NOOV + (plus:SI (match_operand:SI 0 "register_operand" "%r") + (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0)))] + "" + "...") + + The `SELECT_CC_MODE' macro on the Sparc returns `CC_NOOVmode' for +comparisons whose argument is a `plus'. + + +File: gcc.info, Node: Insn Canonicalizations, Next: Peephole Definitions, Prev: Jump Patterns, Up: Machine Desc + +Canonicalization of Instructions +================================ + + There are often cases where multiple RTL expressions could represent +an operation performed by a single machine instruction. This situation +is most commonly encountered with logical, branch, and +multiply-accumulate instructions. In such cases, the compiler attempts +to convert these multiple RTL expressions into a single canonical form +to reduce the number of insn patterns required. + + In addition to algebraic simplifications, following canonicalizations +are performed: + + * For commutative and comparison operators, a constant is always + made the second operand. If a machine only supports a constant as + the second operand, only patterns that match a constant in the + second operand need be supplied. + + For these operators, if only one operand is a `neg', `not', + `mult', `plus', or `minus' expression, it will be the first + operand. + + * For the `compare' operator, a constant is always the second operand + on machines where `cc0' is used (*note Jump Patterns::.). On other + machines, there are rare cases where the compiler might want to + construct a `compare' with a constant as the first operand. + However, these cases are not common enough for it to be worthwhile + to provide a pattern matching a constant as the first operand + unless the machine actually has such an instruction. + + An operand of `neg', `not', `mult', `plus', or `minus' is made the + first operand under the same conditions as above. + + * `(minus X (const_int N))' is converted to `(plus X (const_int + -N))'. + + * Within address computations (i.e., inside `mem'), a left shift is + converted into the appropriate multiplication by a power of two. + + De`Morgan's Law is used to move bitwise negation inside a bitwise + logical-and or logical-or operation. If this results in only one + operand being a `not' expression, it will be the first one. + + A machine that has an instruction that performs a bitwise + logical-and of one operand with the bitwise negation of the other + should specify the pattern for that instruction as + + (define_insn "" + [(set (match_operand:M 0 ...) + (and:M (not:M (match_operand:M 1 ...)) + (match_operand:M 2 ...)))] + "..." + "...") + + Similarly, a pattern for a "NAND" instruction should be written + + (define_insn "" + [(set (match_operand:M 0 ...) + (ior:M (not:M (match_operand:M 1 ...)) + (not:M (match_operand:M 2 ...))))] + "..." + "...") + + In both cases, it is not necessary to include patterns for the many + logically equivalent RTL expressions. + + * The only possible RTL expressions involving both bitwise + exclusive-or and bitwise negation are `(xor:M X Y)' and `(not:M + (xor:M X Y))'. + + * The sum of three items, one of which is a constant, will only + appear in the form + + (plus:M (plus:M X Y) CONSTANT) + + * On machines that do not use `cc0', `(compare X (const_int 0))' + will be converted to X. + + * Equality comparisons of a group of bits (usually a single bit) + with zero will be written using `zero_extract' rather than the + equivalent `and' or `sign_extract' operations. + + +File: gcc.info, Node: Peephole Definitions, Next: Expander Definitions, Prev: Insn Canonicalizations, Up: Machine Desc + +Machine-Specific Peephole Optimizers +==================================== + + In addition to instruction patterns the `md' file may contain +definitions of machine-specific peephole optimizations. + + The combiner does not notice certain peephole optimizations when the +data flow in the program does not suggest that it should try them. For +example, sometimes two consecutive insns related in purpose can be +combined even though the second one does not appear to use a register +computed in the first one. A machine-specific peephole optimizer can +detect such opportunities. + + A definition looks like this: + + (define_peephole + [INSN-PATTERN-1 + INSN-PATTERN-2 + ...] + "CONDITION" + "TEMPLATE" + "OPTIONAL INSN-ATTRIBUTES") + +The last string operand may be omitted if you are not using any +machine-specific information in this machine description. If present, +it must obey the same rules as in a `define_insn'. + + In this skeleton, INSN-PATTERN-1 and so on are patterns to match +consecutive insns. The optimization applies to a sequence of insns when +INSN-PATTERN-1 matches the first one, INSN-PATTERN-2 matches the next, +and so on. + + Each of the insns matched by a peephole must also match a +`define_insn'. Peepholes are checked only at the last stage just +before code generation, and only optionally. Therefore, any insn which +would match a peephole but no `define_insn' will cause a crash in code +generation in an unoptimized compilation, or at various optimization +stages. + + The operands of the insns are matched with `match_operands', +`match_operator', and `match_dup', as usual. What is not usual is that +the operand numbers apply to all the insn patterns in the definition. +So, you can check for identical operands in two insns by using +`match_operand' in one insn and `match_dup' in the other. + + The operand constraints used in `match_operand' patterns do not have +any direct effect on the applicability of the peephole, but they will +be validated afterward, so make sure your constraints are general enough +to apply whenever the peephole matches. If the peephole matches but +the constraints are not satisfied, the compiler will crash. + + It is safe to omit constraints in all the operands of the peephole; +or you can write constraints which serve as a double-check on the +criteria previously tested. + + Once a sequence of insns matches the patterns, the CONDITION is +checked. This is a C expression which makes the final decision whether +to perform the optimization (we do so if the expression is nonzero). If +CONDITION is omitted (in other words, the string is empty) then the +optimization is applied to every sequence of insns that matches the +patterns. + + The defined peephole optimizations are applied after register +allocation is complete. Therefore, the peephole definition can check +which operands have ended up in which kinds of registers, just by +looking at the operands. + + The way to refer to the operands in CONDITION is to write +`operands[I]' for operand number I (as matched by `(match_operand I +...)'). Use the variable `insn' to refer to the last of the insns +being matched; use `prev_active_insn' to find the preceding insns. + + When optimizing computations with intermediate results, you can use +CONDITION to match only when the intermediate results are not used +elsewhere. Use the C expression `dead_or_set_p (INSN, OP)', where INSN +is the insn in which you expect the value to be used for the last time +(from the value of `insn', together with use of `prev_nonnote_insn'), +and OP is the intermediate value (from `operands[I]'). + + Applying the optimization means replacing the sequence of insns with +one new insn. The TEMPLATE controls ultimate output of assembler code +for this combined insn. It works exactly like the template of a +`define_insn'. Operand numbers in this template are the same ones used +in matching the original sequence of insns. + + The result of a defined peephole optimizer does not need to match +any of the insn patterns in the machine description; it does not even +have an opportunity to match them. The peephole optimizer definition +itself serves as the insn pattern to control how the insn is output. + + Defined peephole optimizers are run as assembler code is being +output, so the insns they produce are never combined or rearranged in +any way. + + Here is an example, taken from the 68000 machine description: + + (define_peephole + [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) + (set (match_operand:DF 0 "register_operand" "=f") + (match_operand:DF 1 "register_operand" "ad"))] + "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" + "* + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + #ifdef MOTOROLA + output_asm_insn (\"move.l %1,(sp)\", xoperands); + output_asm_insn (\"move.l %1,-(sp)\", operands); + return \"fmove.d (sp)+,%0\"; + #else + output_asm_insn (\"movel %1,sp@\", xoperands); + output_asm_insn (\"movel %1,sp@-\", operands); + return \"fmoved sp@+,%0\"; + #endif + } + ") + + The effect of this optimization is to change + + jbsr _foobar + addql #4,sp + movel d1,sp@- + movel d0,sp@- + fmoved sp@+,fp0 + +into + + jbsr _foobar + movel d1,sp@ + movel d0,sp@- + fmoved sp@+,fp0 -Index -***** + INSN-PATTERN-1 and so on look *almost* like the second operand of +`define_insn'. There is one important difference: the second operand +of `define_insn' consists of one or more RTX's enclosed in square +brackets. Usually, there is only one: then the same action can be +written as an element of a `define_peephole'. But when there are +multiple actions in a `define_insn', they are implicitly enclosed in a +`parallel'. Then you must explicitly write the `parallel', and the +square brackets within it, in the `define_peephole'. Thus, if an insn +pattern looks like this, -* Menu: + (define_insn "divmodsi4" + [(set (match_operand:SI 0 "general_operand" "=d") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "dmsK"))) + (set (match_operand:SI 3 "general_operand" "=d") + (mod:SI (match_dup 1) (match_dup 2)))] + "TARGET_68020" + "divsl%.l %2,%3:%0") -* #pragma: Misc. -* $: Dollar Signs. -* ': Incompatibilities. -* (nil): RTL Objects. -* 3b1 installation: 3b1 Install. -* ?: side effect: Conditionals. -* #pragma, reason for not using: Function Attributes. -* * in template: Output Statement. -* ?: extensions: Conditionals. -* ?: extensions: Lvalues. -* ACCUMULATE_OUTGOING_ARGS and stack frames: Function Entry. -* ARG_POINTER_REGNUM and virtual registers: Regs and Memory. -* BITS_BIG_ENDIAN, effect on sign_extract: Bit Fields. -* BLKmode, and function return values: Calls. -* ENCODE_SECTION_INFO and address validation: Addressing Modes. -* ENCODE_SECTION_INFO usage: Instruction Output. -* FIRST_PARM_OFFSET and virtual registers: Regs and Memory. -* FRAME_GROWS_DOWNWARD and virtual registers: Regs and Memory. -* FRAME_POINTER_REGNUM and virtual registers: Regs and Memory. -* FUNCTION_EPILOGUE and trampolines: Trampolines. -* FUNCTION_PROLOGUE and trampolines: Trampolines. -* HImode, in insn: Insns. -* MUST_PASS_IN_STACK, and FUNCTION_ARG: Register Arguments. -* PUSH_ROUNDING, interaction with STACK_BOUNDARY: Storage Layout. -* QImode, in insn: Insns. -* REG_PARM_STACK_SPACE, and FUNCTION_ARG: Register Arguments. -* STACK_DYNAMIC_OFFSET and virtual registers: Regs and Memory. -* STACK_POINTER_OFFSET and virtual registers: Regs and Memory. -* STACK_POINTER_REGNUM and virtual registers: Regs and Memory. -* STARTING_FRAME_OFFSET and virtual registers: Regs and Memory. -* SYMBOL_REF_FLAG, in ENCODE_SECTION_INFO: Sections. -* WORDS_BIG_ENDIAN, effect on subreg: Regs and Memory. -* absM2 instruction pattern: Standard Names. -* abs and attributes: Expressions. -* addM3 instruction pattern: Standard Names. -* addr_diff_vec, length of: Insn Lengths. -* addr_vec, length of: Insn Lengths. -* alloca and SunOs: Installation. -* alloca vs variable-length arrays: Variable Length. -* alloca, for SunOs: Sun Install. -* alloca, for Unos: Unos Install. -* andM3 instruction pattern: Standard Names. -* and and attributes: Expressions. -* and, canonicalization of: Insn Canonicalizations. -* ashiftrt and attributes: Expressions. -* ashift and attributes: Expressions. -* ashlM3 instruction pattern: Standard Names. -* ashrM3 instruction pattern: Standard Names. -* asm_operands, RTL sharing: Sharing. -* asm_operands, usage: Assembler. -* asm expressions: Extended Asm. -* bCOND instruction pattern: Standard Names. -* bcopy, implicit usage: Library Calls. -* bzero, implicit usage: Library Calls. -* call_insn and /u: Flags. -* call_pop instruction pattern: Standard Names. -* call_value_pop instruction pattern: Standard Names. -* call_value instruction pattern: Standard Names. -* call instruction pattern: Standard Names. -* call usage: Calls. -* casesi instruction pattern: Standard Names. -* cc0, RTL sharing: Sharing. -* cmpM instruction pattern: Standard Names. -* cmpstrM instruction pattern: Standard Names. -* code_label and /i: Flags. -* compare, canonicalization of: Insn Canonicalizations. -* cond and attributes: Expressions. -* const_double, RTL sharing: Sharing. -* const_int and attribute tests: Expressions. -* const_int and attributes: Expressions. -* const_int, RTL sharing: Sharing. -* const_string and attributes: Expressions. -* const applied to function: Function Attributes. -* define_insn example: Example. -* divM3 instruction pattern: Standard Names. -* divmodM4 instruction pattern: Standard Names. -* div and attributes: Expressions. -* eq and attributes: Expressions. -* extendMN instruction pattern: Standard Names. -* extv instruction pattern: Standard Names. -* extzv instruction pattern: Standard Names. -* ffsM2 instruction pattern: Standard Names. -* fixMN2 instruction pattern: Standard Names. -* fix_truncMN2 instruction pattern: Standard Names. -* fixunsMN2 instruction pattern: Standard Names. -* fixuns_truncMN2 instruction pattern: Standard Names. -* floatMN2 instruction pattern: Standard Names. -* floatunsMN2 instruction pattern: Standard Names. -* float as function value type: Incompatibilities. -* fscanf, and constant strings: Incompatibilities. -* ftruncM2 instruction pattern: Standard Names. -* genflags, crash on Sun 4: Trouble. -* geu and attributes: Expressions. -* ge and attributes: Expressions. -* gprof: Debugging Options. -* gtu and attributes: Expressions. -* gt and attributes: Expressions. -* if_then_else and attributes: Expressions. -* if_then_else usage: Side Effects. -* in_struct, in code_label: Flags. -* in_struct, in insn: Flags. -* in_struct, in insn: Flags. -* in_struct, in label_ref: Flags. -* in_struct, in mem: Flags. -* in_struct, in reg: Flags. -* indirect_jump instruction pattern: Standard Names. -* insn and /i: Flags. -* insn and /s: Flags. -* insn and /u: Flags. -* insv instruction pattern: Standard Names. -* integrated, in insn: Flags. -* integrated, in reg: Flags. -* iorM3 instruction pattern: Standard Names. -* ior and attributes: Expressions. -* ior, canonicalization of: Insn Canonicalizations. -* label_ref and /s: Flags. -* label_ref, RTL sharing: Sharing. -* leu and attributes: Expressions. -* le and attributes: Expressions. -* long long data types: Long Long. -* longjmp and automatic variables: Dialect Options. -* longjmp and automatic variables: Interface. -* longjmp incompatibilities: Incompatibilities. -* longjmp warnings: Warning Options. -* lshiftrt and attributes: Expressions. -* lshift and attributes: Expressions. -* lshlM3 instruction pattern: Standard Names. -* lshrM3 instruction pattern: Standard Names. -* lt and attributes: Expressions. -* main and the exit status: VMS Misc. -* match_dup and attributes: Insn Lengths. -* match_operand and attributes: Expressions. -* maxM3 instruction pattern: Standard Names. -* memcpy, implicit usage: Library Calls. -* memset, implicit usage: Library Calls. -* mem and /s: Flags. -* mem and /u: Flags. -* mem and /v: Flags. -* mem, RTL sharing: Sharing. -* minM3 instruction pattern: Standard Names. -* minus and attributes: Expressions. -* minus, canonicalization of: Insn Canonicalizations. -* mktemp, and constant strings: Incompatibilities. -* modM3 instruction pattern: Standard Names. -* mod and attributes: Expressions. -* movM instruction pattern: Standard Names. -* movstrM instruction pattern: Standard Names. -* movstrictM instruction pattern: Standard Names. -* mulM3 instruction pattern: Standard Names. -* mulhisi3 instruction pattern: Standard Names. -* mulqihi3 instruction pattern: Standard Names. -* mulsidi3 instruction pattern: Standard Names. -* mult and attributes: Expressions. -* mult, canonicalization of: Insn Canonicalizations. -* negM2 instruction pattern: Standard Names. -* neg and attributes: Expressions. -* neg, canonicalization of: Insn Canonicalizations. -* ne and attributes: Expressions. -* nop instruction pattern: Standard Names. -* not and attributes: Expressions. -* not, canonicalization of: Insn Canonicalizations. -* one_cmplM2 instruction pattern: Standard Names. -* pc and attributes: Insn Lengths. -* pc, RTL sharing: Sharing. -* plus and attributes: Expressions. -* plus, canonicalization of: Insn Canonicalizations. -* prof: Debugging Options. -* qsort, and global register variables: Global Reg Vars. -* reg and /i: Flags. -* reg and /s: Flags. -* reg and /u: Flags. -* reg and /v: Flags. -* reg, RTL sharing: Sharing. -* return instruction pattern: Standard Names. -* rotlM3 instruction pattern: Standard Names. -* rotrM3 instruction pattern: Standard Names. -* sCOND instruction pattern: Standard Names. -* scanf, and constant strings: Incompatibilities. -* scratch, RTL sharing: Sharing. -* setjmp incompatibilities: Incompatibilities. -* sign_extract, canonicalization of: Insn Canonicalizations. -* sqrtM2 instruction pattern: Standard Names. -* sscanf, and constant strings: Incompatibilities. -* subM3 instruction pattern: Standard Names. -* subreg, in strict_low_part: RTL Declarations. -* subreg, special reload handling: Regs and Memory. -* symbol_ref and /u: Flags. -* symbol_ref and /v: Flags. -* symbol_ref, RTL sharing: Sharing. -* tablejump instruction pattern: Standard Names. -* tcov: Debugging Options. -* truncMN instruction pattern: Standard Names. -* tstM instruction pattern: Standard Names. -* udivM3 instruction pattern: Standard Names. -* udivmodM4 instruction pattern: Standard Names. -* umaxM3 instruction pattern: Standard Names. -* uminM3 instruction pattern: Standard Names. -* umodM3 instruction pattern: Standard Names. -* umulhisi3 instruction pattern: Standard Names. -* umulqihi3 instruction pattern: Standard Names. -* umulsidi3 instruction pattern: Standard Names. -* unchanging, in call_insn: Flags. -* unchanging, in insn: Flags. -* unchanging, in reg and mem: Flags. -* unchanging, in symbol_ref: Flags. -* used, in symbol_ref: Flags. -* volatile applied to function: Function Attributes. -* volatil, in insn: Flags. -* volatil, in mem: Flags. -* volatil, in reg: Flags. -* volatil, in symbol_ref: Flags. -* xorM3 instruction pattern: Standard Names. -* xor, canonicalization of: Insn Canonicalizations. -* zero_extendMN instruction pattern: Standard Names. -* zero_extract, canonicalization of: Insn Canonicalizations. -* VAXCRTL: VMS Misc. -* libgcc.a: Library Calls. -* stdarg.h and RT PC: RT Options. -* stdarg.h and register arguments: Register Arguments. -* tm.h macros: Target Macros. -* varargs.h and RT PC: RT Options. -* xm-MACHINE.h: Config. -* ! in constraint: Multi-Alternative. -* # in constraint: Modifiers. -* % in constraint: Modifiers. -* % in template: Output Template. -* & in constraint: Modifiers. -* * in constraint: Modifiers. -* + in constraint: Modifiers. -* /i in RTL dump: Flags. -* /s in RTL dump: Flags. -* /s in RTL dump: Flags. -* /u in RTL dump: Flags. -* /v in RTL dump: Flags. -* 0 in constraint: Simple Constraints. -* < in constraint: Simple Constraints. -* = in constraint: Modifiers. -* > in constraint: Simple Constraints. -* ? in constraint: Multi-Alternative. -* E in constraint: Simple Constraints. -* F in constraint: Simple Constraints. -* G in constraint: Simple Constraints. -* H in constraint: Simple Constraints. -* I in constraint: Simple Constraints. -* Q, in constraint: Simple Constraints. -* V in constraint: Simple Constraints. -* X in constraint: Simple Constraints. -* _ in variables in macros: Naming Types. -* d in constraint: Simple Constraints. -* g in constraint: Simple Constraints. -* i in constraint: Simple Constraints. -* m in constraint: Simple Constraints. -* n in constraint: Simple Constraints. -* o in constraint: Simple Constraints. -* p in constraint: Simple Constraints. -* r in constraint: Simple Constraints. -* s in constraint: Simple Constraints. -* ACCUMULATE_OUTGOING_ARGS: Stack Arguments. -* ADDITIONAL_REGISTER_NAMES: Instruction Output. -* ADDRESS_COST: Costs. -* ADJUST_INSN_LENGTH: Insn Lengths. -* ALLOCATE_TRAMPOLINE: Trampolines. -* ALL_REGS: Register Classes. -* AMD29K options: AMD29K Options. -* ANSI support: Dialect Options. -* ARGS_GROW_DOWNWARD: Frame Layout. -* ARG_POINTER_REGNUM: Frame Registers. -* ASM_APP_OFF: File Framework. -* ASM_APP_ON: File Framework. -* ASM_BYTE_OP: Data Output. -* ASM_CLOSE_PAREN: Data Output. -* ASM_COMMENT_START: File Framework. -* ASM_DECLARE_FUNCTION_NAME: Label Output. -* ASM_DECLARE_FUNCTION_SIZE: Label Output. -* ASM_DECLARE_OBJECT_NAME: Label Output. -* ASM_FILE_END: File Framework. -* ASM_FILE_START: File Framework. -* ASM_FINAL_SPEC: Driver. -* ASM_FORMAT_PRIVATE_NAME: Label Output. -* ASM_GENERATE_INTERNAL_LABEL: Label Output. -* ASM_GLOBALIZE_LABEL: Label Output. -* ASM_IDENTIFY_GCC: File Framework. -* ASM_NO_SKIP_IN_TEXT: Alignment Output. -* ASM_OPEN_PAREN: Data Output. -* ASM_OUTPUT_ADDR_DIFF_ELT: Dispatch Tables. -* ASM_OUTPUT_ADDR_VEC_ELT: Dispatch Tables. -* ASM_OUTPUT_ALIGN: Alignment Output. -* ASM_OUTPUT_ALIGNED_COMMON: Uninitialized Data. -* ASM_OUTPUT_ALIGNED_LOCAL: Uninitialized Data. -* ASM_OUTPUT_ALIGN_CODE: Alignment Output. -* ASM_OUTPUT_ASCII: Data Output. -* ASM_OUTPUT_BYTE: Data Output. -* ASM_OUTPUT_CASE_END: Dispatch Tables. -* ASM_OUTPUT_CASE_LABEL: Dispatch Tables. -* ASM_OUTPUT_CHAR: Data Output. -* ASM_OUTPUT_COMMON: Uninitialized Data. -* ASM_OUTPUT_CONSTRUCTOR: Constructor Output. -* ASM_OUTPUT_DESTRUCTOR: Constructor Output. -* ASM_OUTPUT_DOUBLE: Data Output. -* ASM_OUTPUT_DOUBLE_INT: Data Output. -* ASM_OUTPUT_EXTERNAL: Label Output. -* ASM_OUTPUT_EXTERNAL_LIBCALL: Label Output. -* ASM_OUTPUT_FLOAT: Data Output. -* ASM_OUTPUT_IDENT: File Framework. -* ASM_OUTPUT_INT: Data Output. -* ASM_OUTPUT_INTERNAL_LABEL: Label Output. -* ASM_OUTPUT_LABEL: Label Output. -* ASM_OUTPUT_LABELREF: Label Output. -* ASM_OUTPUT_LABELREF_AS_INT: Label Output. -* ASM_OUTPUT_LOCAL: Uninitialized Data. -* ASM_OUTPUT_LONG_DOUBLE: Data Output. -* ASM_OUTPUT_LOOP_ALIGN: Alignment Output. -* ASM_OUTPUT_OPCODE: Instruction Output. -* ASM_OUTPUT_POOL_PROLOGUE: Data Output. -* ASM_OUTPUT_QUADRUPLE_INT: Data Output. -* ASM_OUTPUT_REG_POP: Instruction Output. -* ASM_OUTPUT_REG_PUSH: Instruction Output. -* ASM_OUTPUT_SHARED_COMMON: Uninitialized Data. -* ASM_OUTPUT_SHARED_LOCAL: Uninitialized Data. -* ASM_OUTPUT_SHORT: Data Output. -* ASM_OUTPUT_SKIP: Alignment Output. -* ASM_OUTPUT_SOURCE_FILENAME: File Framework. -* ASM_OUTPUT_SOURCE_LINE: File Framework. -* ASM_OUTPUT_SPECIAL_POOL_ENTRY: Data Output. -* ASM_SPEC: Driver. -* ASM_STABD_OP: Debugging Info. -* ASM_STABN_OP: Debugging Info. -* ASM_STABS_OP: Debugging Info. -* Alliant: Incompatibilities. -* BASE_REG_CLASS: Register Classes. -* BIGGEST_ALIGNMENT: Storage Layout. -* BIGGEST_FIELD_ALIGNMENT: Storage Layout. -* BITFIELD_NBYTES_LIMITED: Storage Layout. -* BITS_BIG_ENDIAN: Storage Layout. -* BITS_PER_UNIT: Storage Layout. -* BITS_PER_WORD: Storage Layout. -* BLKmode: Machine Modes. -* BLOCK_PROFILER: Profiling. -* BRANCH_COST: Costs. -* BYTES_BIG_ENDIAN: Storage Layout. -* BYTE_LOADS_ZERO_EXTEND: Misc. -* Bison parser generator: Installation. -* C language extensions: Extensions. -* C language, traditional: Dialect Options. -* C statements for assembler output: Output Statement. -* CALLER_SAVE_PROFITABLE: Caller Saves. -* CALL_USED_REGISTERS: Register Basics. -* CAN_ELIMINATE: Elimination. -* CASE_DROPS_THROUGH: Misc. -* CASE_VECTOR_MODE: Misc. -* CASE_VECTOR_PC_RELATIVE: Misc. -* CC1PLUS_SPEC: Driver. -* CC1_SPEC: Driver. -* CC_STATUS_MDEP: Condition Code. -* CC_STATUS_MDEP_INIT: Condition Code. -* CCmode: Machine Modes. -* CHAR_TYPE_SIZE: Type Layout. -* CHECK_FLOAT_VALUE: Storage Layout. -* CLASS_MAX_NREGS: Register Classes. -* CODE_LABEL_NUMBER: Insns. -* COMPILER_PATH: Environment Variables. -* CONDITIONAL_REGISTER_USAGE: Register Basics. -* CONST0_RTX: Constants. -* CONST1_RTX: Constants. -* CONST2_RTX: Constants. -* CONSTANT_ADDRESS_P: Addressing Modes. -* CONSTANT_ALIGNMENT: Storage Layout. -* CONSTANT_P: Addressing Modes. -* CONSTANT_POOL_ADDRESS_P: Flags. -* CONST_CALL_P: Flags. -* CONST_COSTS: Costs. -* CONST_DOUBLE_CHAIN: Constants. -* CONST_DOUBLE_LOW: Constants. -* CONST_DOUBLE_MEM: Constants. -* CONST_DOUBLE_OK_FOR_LETTER_P: Register Classes. -* CONST_OK_FOR_LETTER_P: Register Classes. -* COSTS_N_INSNS: Costs. -* CPLUS_INCLUDE_PATH: Environment Variables. -* CPP_PREDEFINES: Run-time Target. -* CPP_SPEC: Driver. -* CUMULATIVE_ARGS: Register Arguments. -* C_INCLUDE_PATH: Environment Variables. -* Convex options: Convex Options. -* DATA_ALIGNMENT: Storage Layout. -* DATA_SECTION_ASM_OP: Sections. -* DBR_OUTPUT_SEQEND: Instruction Output. -* DBX: Incompatibilities. -* DBX_CONTIN_CHAR: Debugging Info. -* DBX_CONTIN_LENGTH: Debugging Info. -* DBX_DEBUGGING_INFO: Debugging Info. -* DBX_FUNCTION_FIRST: Debugging Info. -* DBX_LBRAC_FIRST: Debugging Info. -* DBX_NO_XREFS: Debugging Info. -* DBX_OUTPUT_FUNCTION_END: Debugging Info. -* DBX_OUTPUT_MAIN_SOURCE_DIRECTORY: Debugging Info. -* DBX_OUTPUT_MAIN_SOURCE_FILENAME: Debugging Info. -* DBX_OUTPUT_MAIN_SOURCE_FILE_END: Debugging Info. -* DBX_OUTPUT_SOURCE_FILENAME: Debugging Info. -* DBX_OUTPUT_STANDARD_TYPES: Debugging Info. -* DBX_REGISTER_NUMBER: Debugging Info. -* DBX_STATIC_STAB_DATA_SECTION: Debugging Info. -* DBX_WORKING_DIRECTORY: Debugging Info. -* DCmode: Machine Modes. -* DEBUGGER_ARG_OFFSET: Debugging Info. -* DEBUGGER_AUTO_OFFSET: Debugging Info. -* DEBUG_SYMS_TEXT: Debugging Info. -* DEFAULT_CALLER_SAVES: Caller Saves. -* DEFAULT_GDB_EXTENSIONS: Debugging Info. -* DEFAULT_MAIN_RETURN: Misc. -* DEFAULT_SHORT_ENUMS: Type Layout. -* DEFAULT_SIGNED_CHAR: Type Layout. -* DELAY_SLOTS_FOR_EPILOGUE: Function Entry. -* DEPENDENCIES_OUTPUT: Environment Variables. -* DFmode: Machine Modes. -* DIVDI3_LIBCALL: Library Calls. -* DIVSI3_LIBCALL: Library Calls. -* DImode: Machine Modes. -* DOLLARS_IN_IDENTIFIERS: Misc. -* DONE: Expander Definitions. -* DONT_REDUCE_ADDR: Costs. -* DOUBLE_TYPE_SIZE: Type Layout. -* DWARF_DEBUGGING_INFO: Debugging Info. -* DYNAMIC_CHAIN_ADDRESS: Frame Layout. -* De Morgan's law: Insn Canonicalizations. -* Dependent Patterns: Dependent Patterns. -* EASY_DIV_EXPR: Misc. -* ELIGIBLE_FOR_EPILOGUE_DELAY: Function Entry. -* ELIMINABLE_REGS: Elimination. -* EMPTY_FIELD_BOUNDARY: Storage Layout. -* ENCODE_SECTION_INFO: Sections. -* ENDFILE_SPEC: Driver. -* EXECUTABLE_SUFFIX: Config. -* EXIT_BODY: Misc. -* EXIT_IGNORE_STACK: Function Entry. -* EXPAND_BUILTIN_SAVEREGS: Varargs. -* EXTRA_CC_MODES: Condition Code. -* EXTRA_CC_NAMES: Condition Code. -* EXTRA_CONSTRAINT: Register Classes. -* EXTRA_SECTIONS: Sections. -* EXTRA_SECTION_FUNCTIONS: Sections. -* FAIL: Expander Definitions. -* FAILURE_EXIT_CODE: Config. -* FINALIZE_PIC: PIC. -* FINAL_PRESCAN_INSN: Instruction Output. -* FIRST_INSN_ADDRESS: Insn Lengths. -* FIRST_PARM_OFFSET: Frame Layout. -* FIRST_PSEUDO_REGISTER: Register Basics. -* FIRST_STACK_REG: Stack Registers. -* FIRST_VIRTUAL_REGISTER: Regs and Memory. -* FIXED_REGISTERS: Register Basics. -* FIXUNS_TRUNC_LIKE_FIX_TRUNC: Misc. -* FLOATIFY: Library Calls. -* FLOAT_ARG_TYPE: Library Calls. -* FLOAT_TYPE_SIZE: Type Layout. -* FLOAT_VALUE_TYPE: Library Calls. -* FRAME_GROWS_DOWNWARD: Frame Layout. -* FRAME_POINTER_REGNUM: Frame Registers. -* FRAME_POINTER_REQUIRED: Elimination. -* FUNCTION_ARG: Register Arguments. -* FUNCTION_ARG_ADVANCE: Register Arguments. -* FUNCTION_ARG_BOUNDARY: Register Arguments. -* FUNCTION_ARG_PADDING: Register Arguments. -* FUNCTION_ARG_PARTIAL_NREGS: Register Arguments. -* FUNCTION_ARG_PASS_BY_REFERENCE: Register Arguments. -* FUNCTION_ARG_REGNO_P: Register Arguments. -* FUNCTION_BLOCK_PROFILER: Profiling. -* FUNCTION_BOUNDARY: Storage Layout. -* FUNCTION_CONVERSION_BUG: Config. -* FUNCTION_EPILOGUE: Function Entry. -* FUNCTION_INCOMING_ARG: Register Arguments. -* FUNCTION_MODE: Misc. -* FUNCTION_OUTGOING_VALUE: Scalar Return. -* FUNCTION_PROFILER: Profiling. -* FUNCTION_PROLOGUE: Function Entry. -* FUNCTION_VALUE: Scalar Return. -* FUNCTION_VALUE_REGNO_P: Scalar Return. -* GCC_EXEC_PREFIX: Environment Variables. -* GENERAL_REGS: Register Classes. -* GET_CLASS_NARROWEST_MODE: Machine Modes. -* GET_CODE: RTL Objects. -* GET_MODE: Machine Modes. -* GET_MODE_ALIGNMENT: Machine Modes. -* GET_MODE_BITSIZE: Machine Modes. -* GET_MODE_CLASS: Machine Modes. -* GET_MODE_MASK: Machine Modes. -* GET_MODE_NAME: Machine Modes. -* GET_MODE_NUNITS: Machine Modes. -* GET_MODE_SIZE: Machine Modes. -* GET_MODE_UNIT_SIZE: Machine Modes. -* GET_MODE_WIDER_MODE: Machine Modes. -* GET_RTX_CLASS: Accessors. -* GET_RTX_FORMAT: Accessors. -* GET_RTX_LENGTH: Accessors. -* GLOBALDEF: Global Declarations. -* GLOBALREF: Global Declarations. -* GLOBALVALUEDEF: Global Declarations. -* GLOBALVALUEREF: Global Declarations. -* GNU CC and portability: Portability. -* GNU CC command options: Invoking GCC. -* GNU extensions to the C language: Extensions. -* GO_IF_LEGITIMATE_ADDRESS: Addressing Modes. -* GO_IF_MODE_DEPENDENT_ADDRESS: Addressing Modes. -* HANDLE_PRAGMA: Misc. -* HARD_REGNO_MODE_OK: Values in Registers. -* HARD_REGNO_NREGS: Values in Registers. -* HAVE_ATEXIT: Misc. -* HAVE_POST_DECREMENT: Addressing Modes. -* HAVE_POST_INCREMENT: Addressing Modes. -* HAVE_PRE_DECREMENT: Addressing Modes. -* HAVE_PRE_INCREMENT: Addressing Modes. -* HAVE_PUTENV: Config. -* HAVE_VPRINTF: Config. -* HImode: Machine Modes. -* HOST_BITS_PER_CHAR: Config. -* HOST_BITS_PER_INT: Config. -* HOST_BITS_PER_LONG: Config. -* HOST_BITS_PER_SHORT: Config. -* HOST_FLOAT_FORMAT: Config. -* HOST_WORDS_BIG_ENDIAN: Config. -* IBM RS/6000 Options: RS/6000 Options. -* IBM RT PC: Incompatibilities. -* IBM RT options: RT Options. -* IEEE_FLOAT_FORMAT: Storage Layout. -* IMMEDIATE_PREFIX: Instruction Output. -* IMPLICIT_FIX_EXPR: Misc. -* INCLUDE_DEFAULTS: Driver. -* INDEX_REG_CLASS: Register Classes. -* INITIALIZE_TRAMPOLINE: Trampolines. -* INITIAL_ELIMINATION_OFFSET: Elimination. -* INITIAL_FRAME_POINTER_OFFSET: Elimination. -* INIT_CUMULATIVE_ARGS: Register Arguments. -* INIT_CUMULATIVE_INCOMING_ARGS: Register Arguments. -* INIT_SECTION_ASM_OP: Sections. -* INSN_ANNULLED_BRANCH_P: Flags. -* INSN_CACHE_DEPTH: Trampolines. -* INSN_CACHE_LINE_WIDTH: Trampolines. -* INSN_CACHE_SIZE: Trampolines. -* INSN_CLOBBERS_REGNO_P: Obsolete Register Macros. -* INSN_CODE: Insns. -* INSN_DELETED_P: Flags. -* INSN_FROM_TARGET_P: Flags. -* INSN_UID: Insns. -* INTEGRATE_THRESHOLD: Misc. -* INTIFY: Library Calls. -* INT_TYPE_SIZE: Type Layout. -* Intel 386 Options: i386 Options. -* Interdependence of Patterns: Dependent Patterns. -* JUMP_LABEL: Insns. -* JUMP_TABLES_IN_TEXT_SECTION: Sections. -* LABEL_NUSES: Insns. -* LABEL_OUTSIDE_LOOP_P: Flags. -* LABEL_PRESERVE_P: Flags. -* LAST_STACK_REG: Stack Registers. -* LAST_VIRTUAL_REGISTER: Regs and Memory. -* LEAF_REGISTERS: Leaf Functions. -* LEAF_REG_REMAP: Leaf Functions. -* LEGITIMATE_CONSTANT_P: Addressing Modes. -* LEGITIMATE_PIC_OPERAND_P: Addressing Modes. -* LEGITIMIZE_ADDRESS: Addressing Modes. -* LIBCALL_VALUE: Scalar Return. -* LIBGCC_NEEDS_DOUBLE: Library Calls. -* LIBRARY_PATH: Environment Variables. -* LIB_SPEC: Driver. -* LIMIT_RELOAD_CLASS: Register Classes. -* LINK_LIBGCC_SPECIAL: Driver. -* LINK_SPEC: Driver. -* LOCAL_INCLUDE_DIR: Driver. -* LOCAL_LABEL_PREFIX: Instruction Output. -* LOG_LINKS: Insns. -* LONGJMP_RESTORE_FROM_STACK: Elimination. -* LONG_DOUBLE_TYPE_SIZE: Type Layout. -* LONG_LONG_TYPE_SIZE: Type Layout. -* LONG_TYPE_SIZE: Type Layout. -* Libraries: Link Options. -* M680x0 options: M680x0 Options. -* M88k options: M88K Options. -* MAX_BITS_PER_WORD: Storage Layout. -* MAX_FIXED_MODE_SIZE: Storage Layout. -* MAX_OFILE_ALIGNMENT: Storage Layout. -* MAX_REGS_PER_ADDRESS: Addressing Modes. -* MD_EXEC_PREFIX: Driver. -* MD_STARTFILE_PREFIX: Driver. -* MEMORY_MOVE_COST: Costs. -* MEM_IN_STRUCT_P: Flags. -* MEM_VOLATILE_P: Flags. -* MIPS options: MIPS Options. -* MODDI3_LIBCALL: Library Calls. -* MODES_TIEABLE_P: Values in Registers. -* MODE_CC: Machine Modes. -* MODE_COMPLEX_FLOAT: Machine Modes. -* MODE_COMPLEX_INT: Machine Modes. -* MODE_FLOAT: Machine Modes. -* MODE_FUNCTION: Machine Modes. -* MODE_INT: Machine Modes. -* MODE_PARTIAL_INT: Machine Modes. -* MODE_RANDOM: Machine Modes. -* MODSI3_LIBCALL: Library Calls. -* MOVE_MAX: Misc. -* MOVE_RATIO: Costs. -* MULDI3_LIBCALL: Library Calls. -* MULSI3_LIBCALL: Library Calls. -* MULTIBYTE_CHARS: Type Layout. -* NEXT_INSN: Insns. -* NEXT_OBJC_RUNTIME: Library Calls. -* NON_SAVING_SETJMP: Register Basics. -* NOTE_INSN_BLOCK_BEG: Insns. -* NOTE_INSN_BLOCK_END: Insns. -* NOTE_INSN_DELETED: Insns. -* NOTE_INSN_FUNCTION_END: Insns. -* NOTE_INSN_LOOP_BEG: Insns. -* NOTE_INSN_LOOP_CONT: Insns. -* NOTE_INSN_LOOP_END: Insns. -* NOTE_INSN_LOOP_VTOP: Insns. -* NOTE_INSN_SETJMP: Insns. -* NOTE_LINE_NUMBER: Insns. -* NOTE_SOURCE_FILE: Insns. -* NOTICE_UPDATE_CC: Condition Code. -* NO_DOLLAR_IN_LABEL: Misc. -* NO_FUNCTION_CSE: Costs. -* NO_RECURSIVE_FUNCTION_CSE: Costs. -* NO_REGS: Register Classes. -* NO_STAB_H: Config. -* NO_SYS_SIGLIST: Config. -* NUM_MACHINE_MODES: Machine Modes. -* N_REG_CLASSES: Register Classes. -* OBJC_GEN_METHOD_LABEL: Label Output. -* OBJC_INCLUDE_PATH: Environment Variables. -* OBJC_INT_SELECTORS: Type Layout. -* OBJC_NONUNIQUE_SELECTORS: Type Layout. -* OBJC_PROLOGUE: File Framework. -* OBSTACK_CHUNK_ALLOC: Config. -* OBSTACK_CHUNK_FREE: Config. -* OBSTACK_CHUNK_SIZE: Config. -* OCS (88k): M88K Options. -* ONLY_INT_FIELDS: Config. -* OPTIMIZATION_OPTIONS: Run-time Target. -* ORDER_REGS_FOR_LOCAL_ALLOC: Allocation Order. -* OUTGOING_REG_PARM_STACK_SPACE: Stack Arguments. -* OVERLAPPING_REGNO_P: Obsolete Register Macros. -* OVERRIDE_OPTIONS: Run-time Target. -* Ordering of Patterns: Pattern Ordering. -* PARM_BOUNDARY: Storage Layout. -* PATTERN: Insns. -* PCC_BITFIELD_TYPE_MATTERS: Storage Layout. -* PCC_STATIC_STRUCT_RETURN: Aggregate Return. -* PDImode: Machine Modes. -* PIC: PIC. -* PIC_OFFSET_TABLE_REGNUM: PIC. -* POINTER_SIZE: Storage Layout. -* PREDICATE_CODES: Misc. -* PREFERRED_RELOAD_CLASS: Register Classes. -* PRESERVE_DEATH_INFO_REGNO_P: Obsolete Register Macros. -* PREV_INSN: Insns. -* PRINT_OPERAND: Instruction Output. -* PRINT_OPERAND_ADDRESS: Instruction Output. -* PRINT_OPERAND_PUNCT_VALID_P: Instruction Output. -* PROFILE_BEFORE_PROLOGUE: Profiling. -* PROMOTE_PROTOTYPES: Stack Arguments. -* PSImode: Machine Modes. -* PTRDIFF_TYPE: Type Layout. -* PUSH_ROUNDING: Stack Arguments. -* PUT_CODE: RTL Objects. -* PUT_MODE: Machine Modes. -* PUT_REG_NOTE_KIND: Insns. -* PUT_SDB_...: Debugging Info. -* Pattern Ordering: Pattern Ordering. -* Pmode: Misc. -* QImode: Machine Modes. -* READONLY_DATA_SECTION: Sections. -* REAL_ARITHMETIC: Cross-compilation. -* REAL_INFINITY: Cross-compilation. -* REAL_VALUES_EQUAL: Cross-compilation. -* REAL_VALUES_LESS: Cross-compilation. -* REAL_VALUE_ATOF: Cross-compilation. -* REAL_VALUE_FIX: Cross-compilation. -* REAL_VALUE_FIX_TRUNCATE: Cross-compilation. -* REAL_VALUE_FROM_INT: Cross-compilation. -* REAL_VALUE_ISINF: Cross-compilation. -* REAL_VALUE_ISNAN: Cross-compilation. -* REAL_VALUE_LDEXP: Cross-compilation. -* REAL_VALUE_NEGATE: Cross-compilation. -* REAL_VALUE_TO_INT: Cross-compilation. -* REAL_VALUE_TRUNCATE: Cross-compilation. -* REAL_VALUE_TYPE: Cross-compilation. -* REAL_VALUE_UNSIGNED_FIX: Cross-compilation. -* REAL_VALUE_UNSIGNED_FIX_TRUNCATE: Cross-compilation. -* REGISTER_MOVE_COST: Costs. -* REGISTER_NAMES: Instruction Output. -* REGISTER_PREFIX: Instruction Output. -* REGNO_OK_FOR_BASE_P: Register Classes. -* REGNO_OK_FOR_INDEX_P: Register Classes. -* REGNO_REG_CLASS: Register Classes. -* REG_ALLOC_ORDER: Allocation Order. -* REG_CC_SETTER: Insns. -* REG_CC_USER: Insns. -* REG_CLASS_CONTENTS: Register Classes. -* REG_CLASS_FROM_LETTER: Register Classes. -* REG_CLASS_NAMES: Register Classes. -* REG_DEAD: Insns. -* REG_DEP_ANTI: Insns. -* REG_DEP_OUTPUT: Insns. -* REG_EQUAL: Insns. -* REG_EQUIV: Insns. -* REG_FUNCTION_VALUE_P: Flags. -* REG_INC: Insns. -* REG_LABEL: Insns. -* REG_LEAF_ALLOC_ORDER: Leaf Functions. -* REG_LIBCALL: Insns. -* REG_LOOP_TEST_P: Flags. -* REG_NONNEG: Insns. -* REG_NOTES: Insns. -* REG_NOTE_KIND: Insns. -* REG_NO_CONFLICT: Insns. -* REG_OK_FOR_BASE_P: Addressing Modes. -* REG_OK_FOR_INDEX_P: Addressing Modes. -* REG_OK_STRICT: Addressing Modes. -* REG_PARM_STACK_SPACE: Stack Arguments. -* REG_RETVAL: Insns. -* REG_UNUSED: Insns. -* REG_USERVAR_P: Flags. -* REG_WAS_0: Insns. -* RELATIVE_PREFIX_NOT_LINKDIR: Driver. -* RETURN_IN_MEMORY: Aggregate Return. -* RETURN_POPS_ARGS: Stack Arguments. -* ROUND_TYPE_ALIGN: Storage Layout. -* ROUND_TYPE_SIZE: Storage Layout. -* RS/6000 Options: RS/6000 Options. -* RT PC: Incompatibilities. -* RT options: RT Options. -* RTL addition: Arithmetic. -* RTL comparison: Arithmetic. -* RTL comparison operations: Comparisons. -* RTL constant expression types: Constants. -* RTL constants: Constants. -* RTL declarations: RTL Declarations. -* RTL difference: Arithmetic. -* RTL expression: RTL Objects. -* RTL expressions for arithmetic: Arithmetic. -* RTL format: Accessors. -* RTL format characters: Accessors. -* RTL function-call insns: Calls. -* RTL generation: Passes. -* RTL insn template: RTL Template. -* RTL integers: RTL Objects. -* RTL memory expressions: Regs and Memory. -* RTL object types: RTL Objects. -* RTL postdecrement: Incdec. -* RTL postincrement: Incdec. -* RTL predecrement: Incdec. -* RTL preincrement: Incdec. -* RTL register expressions: Regs and Memory. -* RTL representation: RTL. -* RTL side effect expressions: Side Effects. -* RTL strings: RTL Objects. -* RTL structure sharing assumptions: Sharing. -* RTL subtraction: Arithmetic. -* RTL sum: Arithmetic. -* RTL vectors: RTL Objects. -* RTX (See RTL): RTL Objects. -* RTX_COSTS: Costs. -* RTX_INTEGRATED_P: Flags. -* RTX_UNCHANGING_P: Flags. -* Register Transfer Language (RTL): RTL. -* SCCS_DIRECTIVE: Misc. -* SCHED_GROUP_P: Flags. -* SCmode: Machine Modes. -* SDB_ALLOW_FORWARD_REFERENCES: Debugging Info. -* SDB_ALLOW_UNKNOWN_REFERENCES: Debugging Info. -* SDB_DEBUGGING_INFO: Debugging Info. -* SDB_DELIM: Debugging Info. -* SDB_GENERATE_FAKE: Debugging Info. -* SECONDARY_INPUT_RELOAD_CLASS: Register Classes. -* SECONDARY_OUTPUT_RELOAD_CLASS: Register Classes. -* SECONDARY_RELOAD_CLASS: Register Classes. -* SELECT_CC_MODE: Condition Code. -* SELECT_RTX_SECTION: Sections. -* SELECT_SECTION: Sections. -* SETUP_INCOMING_VARARGS: Varargs. -* SET_DEST: Side Effects. -* SET_SRC: Side Effects. -* SFmode: Machine Modes. -* SHARED_SECTION_ASM_OP: Sections. -* SHIFT_COUNT_TRUNCATED: Misc. -* SHORT_TYPE_SIZE: Type Layout. -* SIGNED_CHAR_SPEC: Driver. -* SIZE_TYPE: Type Layout. -* SImode: Machine Modes. -* SItype: Library Calls. -* SLOW_BYTE_ACCESS: Costs. -* SLOW_UNALIGNED_ACCESS: Costs. -* SLOW_ZERO_EXTEND: Costs. -* SMALL_REGISTER_CLASSES: Register Classes. -* SPARC options: Sparc Options. -* STACK_BOUNDARY: Storage Layout. -* STACK_DYNAMIC_OFFSET: Frame Layout. -* STACK_GROWS_DOWNWARD: Frame Layout. -* STACK_PARMS_IN_REG_PARM_AREA: Stack Arguments. -* STACK_POINTER_OFFSET: Frame Layout. -* STACK_POINTER_REGNUM: Frame Registers. -* STACK_REGS: Stack Registers. -* STANDARD_EXEC_PREFIX: Driver. -* STANDARD_INCLUDE_DIR: Driver. -* STANDARD_STARTFILE_PREFIX: Driver. -* STARTFILE_SPEC: Driver. -* STARTING_FRAME_OFFSET: Frame Layout. -* STATIC_CHAIN: Frame Registers. -* STATIC_CHAIN_INCOMING: Frame Registers. -* STATIC_CHAIN_INCOMING_REGNUM: Frame Registers. -* STATIC_CHAIN_REGNUM: Frame Registers. -* STDC_VALUE: Run-time Target. -* STORE_FLAG_VALUE: Misc. -* STRICT_ALIGNMENT: Storage Layout. -* STRUCTURE_SIZE_BOUNDARY: Storage Layout. -* STRUCT_VALUE: Aggregate Return. -* STRUCT_VALUE_INCOMING: Aggregate Return. -* STRUCT_VALUE_INCOMING_REGNUM: Aggregate Return. -* STRUCT_VALUE_REGNUM: Aggregate Return. -* SUBREG_REG: Regs and Memory. -* SUBREG_WORD: Regs and Memory. -* SUCCESS_EXIT_CODE: Config. -* SVr4: M88K Options. -* SWITCHES_NEED_SPACES: Driver. -* SWITCH_TAKES_ARG: Driver. -* SYMBOL_REF_FLAG: Flags. -* SYMBOL_REF_USED: Flags. -* SYSTEM_INCLUDE_DIR: Driver. -* Sun installation: Sun Install. -* TARGET_BELL: Type Layout. -* TARGET_BS: Type Layout. -* TARGET_CR: Type Layout. -* TARGET_FF: Type Layout. -* TARGET_FLOAT_FORMAT: Storage Layout. -* TARGET_MEM_FUNCTIONS: Library Calls. -* TARGET_NEWLINE: Type Layout. -* TARGET_OPTIONS: Run-time Target. -* TARGET_SWITCHES: Run-time Target. -* TARGET_TAB: Type Layout. -* TARGET_VERSION: Run-time Target. -* TARGET_VT: Type Layout. -* TCmode: Machine Modes. -* TEXT_SECTION_ASM_OP: Sections. -* TFmode: Machine Modes. -* TImode: Machine Modes. -* TMPDIR: Environment Variables. -* TRADITIONAL_RETURN_FLOAT: Scalar Return. -* TRAMPOLINE_ALIGNMENT: Trampolines. -* TRAMPOLINE_SIZE: Trampolines. -* TRAMPOLINE_TEMPLATE: Trampolines. -* TRANSFER_FROM_TRAMPOLINE: Trampolines. -* TRULY_NOOP_TRUNCATION: Misc. -* UDIVDI3_LIBCALL: Library Calls. -* UDIVSI3_LIBCALL: Library Calls. -* UMODDI3_LIBCALL: Library Calls. -* UMODSI3_LIBCALL: Library Calls. -* UNITS_PER_WORD: Storage Layout. -* UNKNOWN_FLOAT_FORMAT: Storage Layout. -* USER_LABEL_PREFIX: Instruction Output. -* USE_C_ALLOCA: Config. -* USG: Config. -* Ultrix calling convention: Incompatibilities. -* Unos installation: Unos Install. -* VAX options: VAX Options. -* VAX_FLOAT_FORMAT: Storage Layout. -* VIRTUAL_INCOMING_ARGS_REGNUM: Regs and Memory. -* VIRTUAL_OUTGOING_ARGS_REGNUM: Regs and Memory. -* VIRTUAL_STACK_DYNAMIC_REGNUM: Regs and Memory. -* VIRTUAL_STACK_VARS_REGNUM: Regs and Memory. -* VMS: Config. -* VMS and case sensitivity: VMS Misc. -* VMS and include files: Include Files and VMS. -* VMS installation: VMS Install. -* VOIDmode: Machine Modes. -* Vax calling convention: Incompatibilities. -* WCHAR_TYPE: Type Layout. -* WCHAR_TYPE_SIZE: Type Layout. -* WORDS_BIG_ENDIAN: Storage Layout. -* WORD_SWITCH_TAKES_ARG: Driver. -* XCOFF_DEBUGGING_INFO: Debugging Info. -* XCmode: Machine Modes. -* XEXP: Accessors. -* XFmode: Machine Modes. -* XINT: Accessors. -* XSTR: Accessors. -* XVEC: Accessors. -* XVECEXP: Accessors. -* XVECLEN: Accessors. -* \: Output Template. -* __bb_init_func: Profiling. -* __builtin_args_info: Varargs. -* __builtin_classify_type: Varargs. -* __builtin_next_arg: Varargs. -* __builtin_saveregs: Varargs. -* abort: Portability. -* abs: Arithmetic. -* absolute value: Arithmetic. -* access to operands: Accessors. -* accessors: Accessors. -* addr_diff_vec: Side Effects. -* addr_vec: Side Effects. -* address: RTL Template. -* address constraints: Simple Constraints. -* address of a label: Labels as Values. -* address_operand: Simple Constraints. -* addressing modes: Addressing Modes. -* aggregates as return values: Aggregate Return. -* alignment: Alignment. -* alternate keywords: Alternate Keywords. -* analysis, data flow: Passes. -* and: Arithmetic. -* apostrophes: Incompatibilities. -* arg_pointer_rtx: Frame Registers. -* argument passing: Interface. -* arguments in frame (88k): M88K Options. -* arguments in registers: Register Arguments. -* arguments on stack: Stack Arguments. -* arithmetic libraries: Interface. -* arithmetic shift: Arithmetic. -* arithmetic simplifications: Passes. -* arithmetic, in RTL: Arithmetic. -* arrays of length zero: Zero Length. -* arrays of variable length: Variable Length. -* arrays, non-lvalue: Subscripting. -* ashift: Arithmetic. -* ashiftrt: Arithmetic. -* asm_fprintf: Instruction Output. -* asm_input: Side Effects. -* asm_noperands: Insns. -* assemble_name: Label Output. -* assembler format: File Framework. -* assembler instructions: Extended Asm. -* assembler instructions in RTL: Assembler. -* assembler names for identifiers: Asm Labels. -* assembler syntax, 88k: M88K Options. -* assembly code, invalid: Bug Criteria. -* assigning attribute values to insns: Tagging Insns. -* asterisk in template: Output Statement. -* atof: Cross-compilation. -* attr: Tagging Insns. -* attribute expressions: Expressions. -* attribute of variables: Variable Attributes. -* attribute specifications: Attr Example. -* attribute specifications example: Attr Example. -* attributes, defining: Defining Attributes. -* autoincrement addressing, availability: Portability. -* autoincrement/decrement addressing: Simple Constraints. -* autoincrement/decrement analysis: Passes. -* backslash: Output Template. -* backtrace for bug reports: Bug Reporting. -* barrier: Insns. -* basic blocks: Passes. -* bcmp: Config. -* bit fields: Bit Fields. -* bit shift overflow (88k): M88K Options. -* bitwise complement: Arithmetic. -* bitwise exclusive-or: Arithmetic. -* bitwise inclusive-or: Arithmetic. -* bitwise logical-and: Arithmetic. -* break_out_memory_refs: Addressing Modes. -* bug criteria: Bug Criteria. -* bug reports: Bug Reporting. -* bugs: Bugs. -* bugs, known: Trouble. -* byte_mode: Machine Modes. -* bzero: Config. -* call: Side Effects. -* call-clobbered register: Register Basics. -* call-saved register: Register Basics. -* call-used register: Register Basics. -* call_insn: Insns. -* call_used_regs: Register Basics. -* calling conventions: Stack and Calling. -* calling functions in RTL: Calls. -* canonicalization of instructions: Insn Canonicalizations. -* case labels in initializers: Labeled Elements. -* case ranges: Case Ranges. -* case sensitivity and VMS: VMS Misc. -* cast to a union: Cast to Union. -* casts as lvalues: Lvalues. -* cc0: Regs and Memory. -* cc0_rtx: Regs and Memory. -* cc_status: Condition Code. -* change_address: Standard Names. -* class definitions, register: Register Classes. -* class preference constraints: Class Preferences. -* classes of RTX codes: Accessors. -* clobber: Side Effects. -* code generation RTL sequences: Expander Definitions. -* code generation conventions: Code Gen Options. -* code motion: Passes. -* code_label: Insns. -* codes, RTL expression: RTL Objects. -* combiner pass: Regs and Memory. -* command options: Invoking GCC. -* common subexpression elimination: Passes. -* compare: Arithmetic. -* compilation in a separate directory: Other Dir. -* compiler bugs, reporting: Bug Reporting. -* compiler passes and files: Passes. -* compiler version, specifying: Target Options. -* complement, bitwise: Arithmetic. -* compound expressions as lvalues: Lvalues. -* computed gotos: Labels as Values. -* computing the length of an insn: Insn Lengths. -* cond: Comparisons. -* condition code register: Regs and Memory. -* condition code status: Condition Code. -* condition codes: Comparisons. -* conditional expressions as lvalues: Lvalues. -* conditional expressions, extensions: Conditionals. -* conditions, in patterns: Patterns. -* configuration file: Config. -* conflicting types: Trouble. -* const0_rtx: Constants. -* const1_rtx: Constants. -* const2_rtx: Constants. -* const_double: Constants. -* const_int: Constants. -* const_string: Constants. -* const_true_rtx: Constants. -* constant attributes: Constant Attributes. -* constant folding: Passes. -* constant folding and floating point: Cross-compilation. -* constant propagation: Passes. -* constants in constraints: Simple Constraints. -* constm1_rtx: Constants. -* constraint modifier characters: Modifiers. -* constraint, matching: Simple Constraints. -* constraints: Constraints. -* constructor expressions: Constructors. -* constructors, output of: Constructor Output. -* contributors: Contributors. -* controlling register usage: Register Basics. -* controlling the compilation driver: Driver. -* conventions, run-time: Interface. -* conversions: Conversions. -* copy_rtx_if_shared: Sharing. -* core dump: Bug Criteria. -* costs of instructions: Costs. -* cross compilation and floating point: Cross-compilation. -* cross compiling: Target Options. -* cross-jumping: Passes. -* current_function_epilogue_delay_list: Function Entry. -* current_function_outgoing_args_size: Stack Arguments. -* current_function_pops_args: Function Entry. -* current_function_pretend_args_size: Function Entry. -* data flow analysis: Passes. -* data_section: Sections. -* dbr_sequence_length: Instruction Output. -* dead code: Passes. -* dead_or_set_p: Peephole Definitions. -* deallocating variable length arrays: Variable Length. -* death notes: Obsolete Register Macros. -* debug_rtx: Bug Reporting. -* debugging information generation: Passes. -* debugging information options: Debugging Options. -* debugging, 88k OCS: M88K Options. -* declaration scope: Incompatibilities. -* declarations inside expressions: Statement Exprs. -* declarations, RTL: RTL Declarations. -* declaring attributes of functions: Function Attributes. -* define_asm_attributes: Tagging Insns. -* define_attr: Defining Attributes. -* define_delay: Delay Slots. -* define_expand: Expander Definitions. -* define_function_unit: Function Units. -* define_insn: Patterns. -* define_peephole: Expander Definitions. -* defining RTL sequences for code generation: Expander Definitions. -* defining attributes and their values: Defining Attributes. -* defining jump instruction patterns: Jump Patterns. -* defining peephole optimizers: Peephole Definitions. -* delay slots, defining: Delay Slots. -* delayed branch scheduling: Passes. -* dependencies for make as output: Environment Variables. -* dependencies, make: Preprocessor Options. -* destructors, output of: Constructor Output. -* dialect options: Dialect Options. -* digits in constraint: Simple Constraints. -* directory options: Directory Options. -* disabling certain registers: Register Basics. -* dispatch table: Dispatch Tables. -* div: Arithmetic. -* divide instruction, 88k: M88K Options. -* division: Arithmetic. -* division: Arithmetic. -* division: Arithmetic. -* dollar signs in identifier names: Dollar Signs. -* double-word arithmetic: Long Long. -* downward funargs: Nested Functions. -* driver: Driver. -* empty constraints: No Constraints. -* endianness: Portability. -* enum machine_mode: Machine Modes. -* enum reg_class: Register Classes. -* environment variables: Environment Variables. -* epilogue: Function Entry. -* eq: Comparisons. -* eq_attr: Expressions. -* equal: Comparisons. -* error: Storage Layout. -* exclamation point: Multi-Alternative. -* exclusive-or, bitwise: Arithmetic. -* exit status and VMS: VMS Misc. -* expander definitions: Expander Definitions. -* explicit register variables: Explicit Reg Vars. -* expr_list: Insns. -* expression codes: RTL Objects. -* expressions containing statements: Statement Exprs. -* expressions, compound, as lvalues: Lvalues. -* expressions, conditional, as lvalues: Lvalues. -* expressions, constructor: Constructors. -* extended asm: Extended Asm. -* extensible constraints: Simple Constraints. -* extensions, ?:: Conditionals. -* extensions, ?:: Lvalues. -* extensions, C language: Extensions. -* extern int target_flags: Run-time Target. -* external declaration scope: Incompatibilities. -* fatal signal: Bug Criteria. -* features, optional, in system conventions: Run-time Target. -* ffs: Arithmetic. -* file name suffix: Overall Options. -* file names: Link Options. -* files and passes of the compiler: Passes. -* final pass: Passes. -* final_scan_insn: Function Entry. -* final_sequence: Instruction Output. -* fix: Conversions. -* fix: Conversions. -* fixed register: Register Basics. -* fixed_regs: Register Basics. -* flags in RTL expression: Flags. -* float: Conversions. -* float_extend: Conversions. -* float_truncate: Conversions. -* floating point format and cross compilation: Cross-compilation. -* force_reg: Standard Names. -* frame layout: Frame Layout. -* frame_pointer_needed: Function Entry. -* frame_pointer_rtx: Frame Registers. -* function attributes: Function Attributes. -* function call conventions: Interface. -* function entry and exit: Function Entry. -* function pointers, arithmetic: Pointer Arith. -* function units, for scheduling: Function Units. -* function, size of pointer to: Pointer Arith. -* function-call insns: Calls. -* functions that have no side effects: Function Attributes. -* functions that never return: Function Attributes. -* functions, leaf: Leaf Functions. -* ge: Comparisons. -* gencodes: Passes. -* genconfig: Passes. -* general_operand: RTL Template. -* generalized lvalues: Lvalues. -* generating assembler output: Output Statement. -* generating insns: RTL Template. -* genflags: Passes. -* get_attr: Expressions. -* get_attr_length: Insn Lengths. -* get_frame_size: Elimination. -* get_insns: Insns. -* get_last_insn: Insns. -* geu: Comparisons. -* global offset table: Code Gen Options. -* global register after longjmp: Global Reg Vars. -* global register allocation: Passes. -* global register variables: Global Reg Vars. -* goto with computed label: Labels as Values. -* gp-relative references (MIPS): MIPS Options. -* greater than: Comparisons. -* greater than: Comparisons. -* greater than: Comparisons. -* grouping options: Invoking GCC. -* gt: Comparisons. -* gtu: Comparisons. -* hard registers: Regs and Memory. -* hardware models and configurations, specifying: Submodel Options. -* header files and VMS: Include Files and VMS. -* high: Constants. -* i386 Options: i386 Options. -* identifier names, dollar signs in: Dollar Signs. -* identifiers, names in assembler code: Asm Labels. -* identifying source, compiler (88k): M88K Options. -* if_then_else: Comparisons. -* immediate_operand: RTL Template. -* in_data: Sections. -* in_struct: Flags. -* in_text: Sections. -* include files and VMS: Include Files and VMS. -* inclusive-or, bitwise: Arithmetic. -* incompatibilities of GNU CC: Incompatibilities. -* increment operators: Bug Criteria. -* initialization routines: Constructor Output. -* initializations in expressions: Constructors. -* initializers with labeled elements: Labeled Elements. -* initializers, non-constant: Initializers. -* inline functions: Inline. -* inline functions, omission of: Inline. -* inline, automatic: Passes. -* insn: Insns. -* insn attributes: Insn Attributes. -* insn canonicalization: Insn Canonicalizations. -* insn lengths, computing: Insn Lengths. -* insn splitting: Insn Splitting. -* insn-attr.h: Defining Attributes. -* insn_list: Insns. -* insns: Insns. -* insns, generating: RTL Template. -* insns, recognizing: RTL Template. -* installation trouble: Trouble. -* installing GNU CC: Installation. -* installing GNU CC on Unos: Unos Install. -* installing GNU CC on VMS: VMS Install. -* installing GNU CC on the 3b1: 3b1 Install. -* installing GNU CC on the Sun: Sun Install. -* instruction attributes: Insn Attributes. -* instruction combination: Passes. -* instruction patterns: Patterns. -* instruction recognizer: Passes. -* instruction scheduling: Passes. -* instruction scheduling: Passes. -* instruction splitting: Insn Splitting. -* integrated: Flags. -* integrating function code: Inline. -* interfacing to GNU CC output: Interface. -* introduction: Top. -* invalid assembly code: Bug Criteria. -* invalid input: Bug Criteria. -* ior: Arithmetic. -* isinf: Cross-compilation. -* isnan: Cross-compilation. -* jump instruction patterns: Jump Patterns. -* jump instructions and set: Side Effects. -* jump optimization: Passes. -* jump threading: Passes. -* jump_insn: Insns. -* keywords, alternate: Alternate Keywords. -* known causes of trouble: Trouble. -* label_ref: Constants. -* labeled elements in initializers: Labeled Elements. -* labels as values: Labels as Values. -* language dialect options: Dialect Options. -* large bit shifts (88k): M88K Options. -* large return values: Aggregate Return. -* ldexp: Cross-compilation. -* le: Comparisons. -* leaf functions: Leaf Functions. -* leaf_function: Leaf Functions. -* leaf_function_p: Standard Names. -* left rotate: Arithmetic. -* left shift: Arithmetic. -* left shift: Arithmetic. -* length-zero arrays: Zero Length. -* less than: Comparisons. -* less than or equal: Comparisons. -* leu: Comparisons. -* library subroutine names: Library Calls. -* link options: Link Options. -* lo_sum: Arithmetic. -* load address instruction: Simple Constraints. -* local labels: Local Labels. -* local register allocation: Passes. -* local variables in macros: Naming Types. -* local variables, specifying registers: Local Reg Vars. -* logical shift: Arithmetic. -* logical-and, bitwise: Arithmetic. -* longjmp: Global Reg Vars. -* loop optimization: Passes. -* lshift: Arithmetic. -* lshiftrt: Arithmetic. -* lt: Comparisons. -* ltu: Comparisons. -* lvalues, generalized: Lvalues. -* machine dependent options: Submodel Options. -* machine description macros: Target Macros. -* machine descriptions: Machine Desc. -* machine mode conversions: Conversions. -* machine modes: Machine Modes. -* macros containing asm: Extended Asm. -* macros, inline alternative: Inline. -* macros, local labels: Local Labels. -* macros, local variables in: Naming Types. -* macros, statements in expressions: Statement Exprs. -* macros, target description: Target Macros. -* macros, types of arguments: Typeof. -* make: Preprocessor Options. -* make_safe_from: Expander Definitions. -* match_dup: RTL Template. -* match_operand: RTL Template. -* match_operator: RTL Template. -* match_scratch: RTL Template. -* matching constraint: Simple Constraints. -* matching operands: Output Template. -* math libraries: Interface. -* math, in RTL: Arithmetic. -* mcount: Profiling. -* mem: Regs and Memory. -* memory reference, nonoffsettable: Simple Constraints. -* memory references in constraints: Simple Constraints. -* messages, warning: Warning Options. -* middle-operands, omitted: Conditionals. -* minus: Arithmetic. -* mod: Arithmetic. -* mode classes: Machine Modes. -* modifiers in constraints: Modifiers. -* mult: Arithmetic. -* multiple alternative constraints: Multi-Alternative. -* multiplication: Arithmetic. -* multiprecision arithmetic: Long Long. -* name augmentation: VMS Misc. -* named patterns and conditions: Patterns. -* names used in assembler code: Asm Labels. -* names, pattern: Standard Names. -* naming types: Naming Types. -* ne: Comparisons. -* neg: Arithmetic. -* nested functions: Nested Functions. -* nested functions, trampolines for: Trampolines. -* next_cc0_user: Jump Patterns. -* nil: RTL Objects. -* no constraints: No Constraints. -* no-op move instructions: Passes. -* non-constant initializers: Initializers. -* non-static inline function: Inline. -* nonoffsettable memory reference: Simple Constraints. -* not: Arithmetic. -* not equal: Comparisons. -* not using constraints: No Constraints. -* note: Insns. -* obstack_free: 3b1 Install. -* offsettable address: Simple Constraints. -* omitted middle-operands: Conditionals. -* open coding: Inline. -* operand access: Accessors. -* operand constraints: Constraints. -* operand substitution: Output Template. -* operands: Patterns. -* optimize options: Optimize Options. -* optional hardware or system features: Run-time Target. -* options to control warnings: Warning Options. -* options, GNU CC command: Invoking GCC. -* options, code generation: Code Gen Options. -* options, debugging: Debugging Options. -* options, dialect: Dialect Options. -* options, directory search: Directory Options. -* options, grouping: Invoking GCC. -* options, linking: Link Options. -* options, optimization: Optimize Options. -* options, order: Invoking GCC. -* options, preprocessor: Preprocessor Options. -* order of options: Invoking GCC. -* order of register allocation: Allocation Order. -* other directory, compilation in: Other Dir. -* output file option: Overall Options. -* output of assembler code: File Framework. -* output statements: Output Statement. -* output templates: Output Template. -* output_addr_const: Data Output. -* output_asm_insn: Output Statement. -* overflow while constant folding: Cross-compilation. -* parallel: Side Effects. -* parameter forward declaration: Variable Length. -* parameters, miscellaneous: Misc. -* parser generator, Bison: Installation. -* parsing pass: Passes. -* passes and files of the compiler: Passes. -* passing arguments: Interface. -* pattern conditions: Patterns. -* pattern names: Standard Names. -* patterns: Patterns. -* pc: Regs and Memory. -* pc_rtx: Regs and Memory. -* peephole optimization: Passes. -* peephole optimization, RTL representation: Side Effects. -* peephole optimizer definitions: Peephole Definitions. -* percent sign: Output Template. -* perform_...: Library Calls. -* plus: Arithmetic. -* pointer arguments: Function Attributes. -* portability: Portability. -* position independent code: PIC. -* post_dec: Incdec. -* post_inc: Incdec. -* pragma: Misc. -* pragma, reason for not using: Function Attributes. -* pre_dec: Incdec. -* pre_inc: Incdec. -* predefined macros: Run-time Target. -* preprocessor options: Preprocessor Options. -* prev_cc0_setter: Jump Patterns. -* prev_nonnote_insn: Peephole Definitions. -* product: Arithmetic. -* profiling, code generation: Profiling. -* program counter: Regs and Memory. -* prologue: Function Entry. -* promotion of formal parameters: Trouble. -* pseudo registers: Regs and Memory. -* push address instruction: Simple Constraints. -* putenv: Config. -* question mark: Multi-Alternative. -* quotient: Arithmetic. -* r0-relative references (88k): M88K Options. -* ranges in case statements: Case Ranges. -* read-only strings: Incompatibilities. -* recog_operand: Instruction Output. -* recognizing insns: RTL Template. -* reg: Regs and Memory. -* reg_names: Instruction Output. -* register allocation: Passes. -* register allocation order: Allocation Order. -* register allocation, stupid: Passes. -* register class definitions: Register Classes. -* register class preference constraints: Class Preferences. -* register class preference pass: Passes. -* register pairs: Values in Registers. -* register positions in frame (88k): M88K Options. -* register positions in frame (88k): M88K Options. -* register usage: Registers. -* register use analysis: Passes. -* register variable after longjmp: Global Reg Vars. -* register-to-stack conversion: Passes. -* register_operand: RTL Template. -* registers: Extended Asm. -* registers arguments: Register Arguments. -* registers for local variables: Local Reg Vars. -* registers in constraints: Simple Constraints. -* registers, global allocation: Explicit Reg Vars. -* registers, global variables in: Global Reg Vars. -* regs_ever_live: Function Entry. -* relative costs: Costs. -* reload pass: Regs and Memory. -* reload_completed: Standard Names. -* reload_in: Standard Names. -* reload_in_progress: Standard Names. -* reload_out: Standard Names. -* reloading: Passes. -* remainder: Arithmetic. -* reporting bugs: Bugs. -* representation of RTL: RTL. -* rest_of_compilation: Passes. -* rest_of_decl_compilation: Passes. -* return: Side Effects. -* return value of main: VMS Misc. -* return values in registers: Scalar Return. -* returning aggregate values: Aggregate Return. -* returning structures and unions: Interface. -* right rotate: Arithmetic. -* right shift: Arithmetic. -* rotate: Arithmetic. -* rotate: Arithmetic. -* rotatert: Arithmetic. -* run-time conventions: Interface. -* run-time options: Code Gen Options. -* run-time target specification: Run-time Target. -* saveable_obstack: Addressing Modes. -* scalars, returned as values: Scalar Return. -* scheduling, delayed branch: Passes. -* scheduling, instruction: Passes. -* scheduling, instruction: Passes. -* scope of a variable length array: Variable Length. -* scope of declaration: Trouble. -* scope of external declarations: Incompatibilities. -* scratch: Regs and Memory. -* scratch operands: Regs and Memory. -* search path: Directory Options. -* separate directory, compilation in: Other Dir. -* sequence: Side Effects. -* set: Side Effects. -* set_attr: Tagging Insns. -* set_attr_alternative: Tagging Insns. -* setjmp: Global Reg Vars. -* shared VMS run time system: VMS Misc. -* shared strings: Incompatibilities. -* sharing of RTL components: Sharing. -* shift: Arithmetic. -* side effect in ?:: Conditionals. -* side effects, macro argument: Statement Exprs. -* sign_extend: Conversions. -* sign_extract: Bit Fields. -* signed division: Arithmetic. -* signed maximum: Arithmetic. -* signed minimum: Arithmetic. -* simple constraints: Simple Constraints. -* simplifications, arithmetic: Passes. -* sizeof: Typeof. -* smaller data references (88k): M88K Options. -* smaller data references (MIPS): MIPS Options. -* smax: Arithmetic. -* smin: Arithmetic. -* specified registers: Explicit Reg Vars. -* specifying compiler version and target machine: Target Options. -* specifying hardware config: Submodel Options. -* specifying machine version: Target Options. -* specifying registers for local variables: Local Reg Vars. -* speed of instructions: Costs. -* splitting instructions: Insn Splitting. -* sqrt: Arithmetic. -* square root: Arithmetic. -* stack arguments: Stack Arguments. -* stack frame layout: Frame Layout. -* stack_pointer_rtx: Frame Registers. -* stage1: Installation. -* standard pattern names: Standard Names. -* statements inside expressions: Statement Exprs. -* storage layout: Storage Layout. -* strcpy: Storage Layout. -* strength-reduction: Passes. -* strict_low_part: RTL Declarations. -* string constants: Incompatibilities. -* structure passing (88k): M88K Options. -* structure value address: Aggregate Return. -* structures: Incompatibilities. -* structures, constructor expression: Constructors. -* structures, returning: Interface. -* stupid register allocation: Passes. -* submodel options: Submodel Options. -* subreg: Regs and Memory. -* subscripting: Subscripting. -* subscripting and function values: Subscripting. -* suppressing warnings: Warning Options. -* symbol_ref: Constants. -* symbolic label: Sharing. -* syntax checking: Warning Options. -* sys_siglist: Config. -* tagging insns: Tagging Insns. -* tail recursion optimization: Passes. -* target description macros: Target Macros. -* target machine, specifying: Target Options. -* target options: Target Options. -* target specifications: Run-time Target. -* target-parameter-dependent code: Passes. -* termination routines: Constructor Output. -* text_section: Sections. -* thunks: Nested Functions. -* top level of compiler: Passes. -* traditional C language: Dialect Options. -* trampolines for nested functions: Trampolines. -* truncate: Conversions. -* type alignment: Alignment. -* typedef names as function parameters: Incompatibilities. -* typeof: Typeof. -* udiv: Arithmetic. -* umax: Arithmetic. -* umin: Arithmetic. -* umod: Arithmetic. -* unchanging: Flags. -* undefined behavior: Bug Criteria. -* undefined function value: Bug Criteria. -* underscores in variables in macros: Naming Types. -* underscores, avoiding (88k): M88K Options. -* union, casting to a: Cast to Union. -* unions: Incompatibilities. -* unions, returning: Interface. -* unreachable code: Passes. -* unshare_all_rtl: Sharing. -* unsigned division: Arithmetic. -* unsigned greater than: Comparisons. -* unsigned greater than: Comparisons. -* unsigned less than: Comparisons. -* unsigned less than: Comparisons. -* unsigned minimum and maximum: Arithmetic. -* unsigned_fix: Conversions. -* unsigned_float: Conversions. -* unspec: Side Effects. -* unspec_volatile: Side Effects. -* use: Side Effects. -* used: Flags. -* value after longjmp: Global Reg Vars. -* values, returned by functions: Scalar Return. -* varargs implementation: Varargs. -* variable alignment: Alignment. -* variable attributes: Variable Attributes. -* variable-length array scope: Variable Length. -* variable-length arrays: Variable Length. -* variables in specified registers: Explicit Reg Vars. -* variables, local, in macros: Naming Types. -* void pointers, arithmetic: Pointer Arith. -* void, size of pointer to: Pointer Arith. -* volatil: Flags. -* volatile memory references: Flags. -* voting between constraint alternatives: Class Preferences. -* vprintf: Config. -* warning messages: Warning Options. -* which_alternative: Output Statement. -* whitespace: Incompatibilities. -* word_mode: Machine Modes. -* xor: Arithmetic. -* zero division on 88k: M88K Options. -* zero-length arrays: Zero Length. -* zero_extend: Conversions. -* zero_extract: Bit Fields. +then the way to mention this insn in a peephole is as follows: + (define_peephole + [... + (parallel + [(set (match_operand:SI 0 "general_operand" "=d") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "dmsK"))) + (set (match_operand:SI 3 "general_operand" "=d") + (mod:SI (match_dup 1) (match_dup 2)))]) + ...] + ...)