--- gcc/internals-4 2018/04/24 16:38:15 1.1.1.1 +++ gcc/internals-4 2018/04/24 16:39:09 1.1.1.2 @@ -1,31 +1,484 @@ -Info file internals, produced by Makeinfo, -*- Text -*- -from input file internals.texinfo. + +File: internals, Node: Side Effects, Next: Incdec, Prev: RTL Declarations, Up: RTL + +Side Effect Expressions +======================= + +The expression codes described so far represent values, not actions. But +machine instructions never produce values; they are meaningful only for +their side effects on the state of the machine. Special expression codes +are used to represent side effects. + +The body of an instruction is always one of these side effect codes; the +codes described above, which represent values, appear only as the operands +of these. + +`(set LVAL X)' + Represents the action of storing the value of X into the place + represented by LVAL. LVAL must be an expression representing a place + that can be stored in: `reg' (or `subreg' or `strict_low_part'), + `mem', `pc' or `cc0'. + + If LVAL is a `reg', `subreg' or `mem', it has a machine mode; then X + must be valid for that mode. + + If LVAL is a `reg' whose machine mode is less than the full width of + the register, then it means that the part of the register specified by + the machine mode is given the specified value and the rest of the + register receives an undefined value. Likewise, if LVAL is a `subreg' + whose machine mode is narrower than `SImode', the rest of the register + can be changed in an undefined way. + + If LVAL is a `strict_low_part' of a `subreg', then the part of the + register specified by the machine mode of the `subreg' is given the + value X and the rest of the register is not changed. + + If LVAL is `(cc0)', it has no machine mode, and X may have any mode. + This represents a ``test'' or ``compare'' instruction. + + If LVAL is `(pc)', we have a jump instruction, and the possibilities + for X are very limited. It may be a `label_ref' expression + (unconditional jump). It may be an `if_then_else' (conditional jump), + in which case either the second or the third operand must be `(pc)' + (for the case which does not jump) and the other of the two must be a + `label_ref' (for the case which does jump). X may also be a `mem' or + `(plus:SI (pc) Y)', where Y may be a `reg' or a `mem'; these unusual + patterns are used to represent jumps through branch tables. + +`(return)' + Represents a return from the current function, on machines where this + can be done with one instruction, such as Vaxes. On machines where a + multi-instruction ``epilogue'' must be executed in order to return + from the function, returning is done by jumping to a label which + precedes the epilogue, and the `return' expression code is never used. + +`(call FUNCTION NARGS)' + Represents a function call. FUNCTION is a `mem' expression whose + address is the address of the function to be called. NARGS is an + expression representing the number of words of argument. + + Each machine has a standard machine mode which FUNCTION must have. + The machine description defines macro `FUNCTION_MODE' to expand into + the requisite mode name. The purpose of this mode is to specify what + kind of addressing is allowed, on machines where the allowed kinds of + addressing depend on the machine mode being addressed. + +`(clobber X)' + Represents the storing or possible storing of an unpredictable, + undescribed value into X, which must be a `reg' or `mem' expression. + + One place this is used is in string instructions that store standard + values into particular hard registers. It may not be worth the + trouble to describe the values that are stored, but it is essential to + inform the compiler that the registers will be altered, lest it + attempt to keep data in them across the string instruction. + + X may also be null---a null C pointer, no expression at all. Such a + `(clobber (null))' expression means that all memory locations must be + presumed clobbered. + + Note that the machine description classifies certain hard registers as + ``call-clobbered''. All function call instructions are assumed by + default to clobber these registers, so there is no need to use + `clobber' expressions to indicate this fact. Also, each function call + is assumed to have the potential to alter any memory location. + +`(use X)' + Represents the use of the value of X. It indicates that the value in + X at this point in the program is needed, even though it may not be + apparent why this is so. Therefore, the compiler will not attempt to + delete instructions whose only effect is to store a value in X. X + must be a `reg' expression. + +`(parallel [X0 X1 ...])' + Represents several side effects performed in parallel. The square + brackets stand for a vector; the operand of `parallel' is a vector of + expressions. X0, X1 and so on are individual side + effects---expressions of code `set', `call', `return', `clobber' or + `use'. + + ``In parallel'' means that first all the values used in the individual + side-effects are computed, and second all the actual side-effects are + performed. For example, + + (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1))) + (set (mem:SI (reg:SI 1)) (reg:SI 1))]) + + says unambiguously that the values of hard register 1 and the memory + location addressed by it are interchanged. In both places where + `(reg:SI 1)' appears as a memory address it refers to the value in + register 1 *before* the execution of the instruction. + +`(sequence [INSNS ...])' + Represents a sequence of insns. Each of the INSNS that appears in the + vector is suitable for appearing in the chain of insns, so it must be + an `insn', `jump_insn', `call_insn', `code_label', `barrier' or `note'. + + A `sequence' RTX never appears in an actual insn. It represents the + sequence of insns that result from a `define_expand' *before* those + insns are passed to `emit_insn' to insert them in the chain of insns. + When actually inserted, the individual sub-insns are separated out and + the `sequence' is forgotten. + +Three expression codes appear in place of a side effect, as the body of an +insn, though strictly speaking they do not describe side effects as such: + +`(asm_input S)' + Represents literal assembler code as described by the string S. + +`(addr_vec:M [LR0 LR1 ...])' + Represents a table of jump addresses. The vector elements LR0, etc., + are `label_ref' expressions. The mode M specifies how much space is + given to each address; normally M would be `Pmode'. + +`(addr_diff_vec:M BASE [LR0 LR1 ...])' + Represents a table of jump addresses expressed as offsets from BASE. + The vector elements LR0, etc., are `label_ref' expressions and so is + BASE. The mode M specifies how much space is given to each + address-difference. + + +File: internals, Node: Incdec, Next: Assembler, Prev: Side Effects, Up: RTL +Embedded Side-Effects on Addresses +================================== -This file documents the internals of the GNU compiler. +Four special side-effect expression codes appear as memory addresses. -Copyright (C) 1988 Free Software Foundation, Inc. +`(pre_dec:M X)' + Represents the side effect of decrementing X by a standard amount and + represents also the value that X has after being decremented. X must + be a `reg' or `mem', but most machines allow only a `reg'. M must be + the machine mode for pointers on the machine in use. The amount X is + decremented by is the length in bytes of the machine mode of the + containing memory reference of which this expression serves as the + address. Here is an example of its use: + + (mem:DF (pre_dec:SI (reg:SI 39))) + + This says to decrement pseudo register 39 by the length of a `DFmode' + value and use the result to address a `DFmode' value. + +`(pre_inc:M X)' + Similar, but specifies incrementing X instead of decrementing it. + +`(post_dec:M X)' + Represents the same side effect as `pre_decrement' but a different + value. The value represented here is the value X has before being + decremented. + +`(post_inc:M X)' + Similar, but specifies incrementing X instead of decrementing it. + +These embedded side effect expressions must be used with care. Instruction +patterns may not use them. Until the `flow' pass of the compiler, they may +occur only to represent pushes onto the stack. The `flow' pass finds cases +where registers are incremented or decremented in one instruction and used +as an address shortly before or after; these cases are then transformed to +use pre- or post-increment or -decrement. + +Explicit popping of the stack could be represented with these embedded side +effect operators, but that would not be safe; the instruction combination +pass could move the popping past pushes, thus changing the meaning of the +code. + +An instruction that can be represented with an embedded side effect could +also be represented using `parallel' containing an additional `set' to +describe how the address register is altered. This is not done because +machines that allow these operations at all typically allow them wherever a +memory address is called for. Describing them as additional parallel +stores would require doubling the number of entries in the machine +description. -Permission is granted to make and distribute verbatim copies of -this manual provided the copyright notice and this permission notice -are preserved on all copies. + +File: internals, Node: Assembler, Next: Insns, Prev: IncDec, Up: RTL -Permission is granted to copy and distribute modified versions of this -manual under the conditions for verbatim copying, provided also that the -section entitled ``GNU CC General Public License'' is included exactly as -in the original, and provided that the entire resulting derived work is -distributed under the terms of a permission notice identical to this one. +Assembler Instructions as Expressions +===================================== -Permission is granted to copy and distribute translations of this manual -into another language, under the above conditions for modified versions, -except that the section entitled ``GNU CC General Public License'' and -this permission notice may be included in translations approved by the -Free Software Foundation instead of in the original English. +The RTX code `asm_operands' represents a value produced by a user-specified +assembler instruction. It is used to represent an `asm' statement with +arguments. An `asm' statement with a single output operand, like this: + + asm ("foo %1,%2,%0" : "a" (outputvar) : "g" (x + y), "di" (*z)); + +is represented using a single `asm_operands' RTX which represents the value +that is stored in `outputvar': + + (set RTX-FOR-OUTPUTVAR + (asm_operands "foo %1,%2,%0" "a" 0 + [RTX-FOR-ADDITION-RESULT RTX-FOR-*Z] + [(asm_input:M1 "g") + (asm_input:M2 "di")])) + +Here the operands of the `asm_operands' RTX are the assembler template +string, the output-operand's constraint, the index-number of the output +operand among the output operands specified, a vector of input operand +RTX's, and a vector of input-operand modes and constraints. The mode M1 is +the mode of the sum `x+y'; M2 is that of `*z'. + +When an `asm' statement has multiple output values, its insn has several +such `set' RTX's inside of a `parallel'. Each `set' contains a +`asm_operands'; all of these share the same assembler template and vectors, +but each contains the constraint for the respective output operand. They +are also distinguished by the output-operand index number, which is 0, 1, +... for successive output operands. + +File: internals, Node: Insns, Next: Calls, Prev: Assembler, Up: RTL +Insns +===== - +The RTL representation of the code for a function is a doubly-linked chain +of objects called "insns". Insns are expressions with special codes that +are used for no other purpose. Some insns are actual instructions; others +represent dispatch tables for `switch' statements; others represent labels +to jump to or various sorts of declarative information. + +In addition to its own specific data, each insn must have a unique +id-number that distinguishes it from all other insns in the current +function, and chain pointers to the preceding and following insns. These +three fields occupy the same position in every insn, independent of the +expression code of the insn. They could be accessed with `XEXP' and +`XINT', but instead three special macros are always used: + +`INSN_UID (I)' + Accesses the unique id of insn I. + +`PREV_INSN (I)' + Accesses the chain pointer to the insn preceding I. If I is the first + insn, this is a null pointer. + +`NEXT_INSN (I)' + Accesses the chain pointer to the insn following I. If I is the last + insn, this is a null pointer. + +The `NEXT_INSN' and `PREV_INSN' pointers must always correspond: if I is +not the first insn, + + NEXT_INSN (PREV_INSN (INSN)) == INSN + +is always true. + +Every insn has one of the following six expression codes: + +`insn' + The expression code `insn' is used for instructions that do not jump + and do not do function calls. Insns with code `insn' have four + additional fields beyond the three mandatory ones listed above. These + four are described in a table below. + +`jump_insn' + The expression code `jump_insn' is used for instructions that may jump + (or, more generally, may contain `label_ref' expressions). + `jump_insn' insns have the same extra fields as `insn' insns, accessed + in the same way. + +`call_insn' + The expression code `call_insn' is used for instructions that may do + function calls. It is important to distinguish these instructions + because they imply that certain registers and memory locations may be + altered unpredictably. + + `call_insn' insns have the same extra fields as `insn' insns, accessed + in the same way. + +`code_label' + A `code_label' insn represents a label that a jump insn can jump to. + It contains one special field of data in addition to the three + standard ones. It is used to hold the "label number", a number that + identifies this label uniquely among all the labels in the compilation + (not just in the current function). Ultimately, the label is + represented in the assembler output as an assembler label `LN' where N + is the label number. + +`barrier' + Barriers are placed in the instruction stream after unconditional jump + instructions to indicate that the jumps are unconditional. They + contain no information beyond the three standard fields. + +`note' + `note' insns are used to represent additional debugging and + declarative information. They contain two nonstandard fields, an + integer which is accessed with the macro `NOTE_LINE_NUMBER' and a + string accessed with `NOTE_SOURCE_FILE'. + + If `NOTE_LINE_NUMBER' is positive, the note represents the position of + a source line and `NOTE_SOURCE_FILE' is the source file name that the + line came from. These notes control generation of line number data in + the assembler output. + + Otherwise, `NOTE_LINE_NUMBER' is not really a line number but a code + with one of the following values (and `NOTE_SOURCE_FILE' must contain + a null pointer): + + `NOTE_INSN_DELETED' + Such a note is completely ignorable. Some passes of the compiler + delete insns by altering them into notes of this kind. + + `NOTE_INSN_BLOCK_BEG' + `NOTE_INSN_BLOCK_END' + These types of notes indicate the position of the beginning and + end of a level of scoping of variable names. They control the + output of debugging information. + + `NOTE_INSN_LOOP_BEG' + `NOTE_INSN_LOOP_END' + These types of notes indicate the position of the beginning and + end of a `while' or `for' loop. They enable the loop optimizer + to find loops quickly. + +Here is a table of the extra fields of `insn', `jump_insn' and `call_insn' +insns: + +`PATTERN (I)' + An expression for the side effect performed by this insn. + +`REG_NOTES (I)' + A list (chain of `expr_list' expressions) giving information about the + usage of registers in this insn. This list is set up by the flow + analysis pass; it is a null pointer until then. + +`LOG_LINKS (I)' + A list (chain of `insn_list' expressions) of previous ``related'' + insns: insns which store into registers values that are used for the + first time in this insn. (An additional constraint is that neither a + jump nor a label may come between the related insns). This list is + set up by the flow analysis pass; it is a null pointer until then. + +`INSN_CODE (I)' + An integer that says which pattern in the machine description matches + this insn, or -1 if the matching has not yet been attempted. + + Such matching is never attempted and this field is not used on an insn + whose pattern consists of a single `use', `clobber', `asm', `addr_vec' + or `addr_diff_vec' expression. + +The `LOG_LINKS' field of an insn is a chain of `insn_list' expressions. +Each of these has two operands: the first is an insn, and the second is +another `insn_list' expression (the next one in the chain). The last +`insn_list' in the chain has a null pointer as second operand. The +significant thing about the chain is which insns appear in it (as first +operands of `insn_list' expressions). Their order is not significant. + +The `REG_NOTES' field of an insn is a similar chain but of `expr_list' +expressions instead of `insn_list'. There are four kinds of register +notes, which are distinguished by the machine mode of the `expr_list', +which a register note is really understood as being an `enum reg_note'. +The first operand OP of the `expr_list' is data whose meaning depends on +the kind of note. Here are the four kinds: + +`REG_DEAD' + The register OP dies in this insn; that is to say, altering the value + immediately after this insn would not affect the future behavior of + the program. + +`REG_INC' + The register OP is incremented (or decremented; at this level there is + no distinction) by an embedded side effect inside this insn. This + means it appears in a `POST_INC', `PRE_INC', `POST_DEC' or `PRE_DEC' + RTX. + +`REG_EQUIV' + The register that is set by this insn will be equal to OP at run time, + and could validly be replaced in all its occurrences by OP. + (``Validly'' here refers to the data flow of the program; simple + replacement may make some insns invalid.) + + The value which the insn explicitly copies into the register may look + different from OP, but they will be equal at run time. + + For example, when a constant is loaded into a register that is never + assigned any other value, this kind of note is used. + + When a parameter is copied into a pseudo-register at entry to a + function, a note of this kind records that the register is equivalent + to the stack slot where the parameter was passed. Although in this + case the register may be set by other insns, it is still valid to + replace the register by the stack slot throughout the function. + +`REG_EQUAL' + The register that is set by this insn will be equal to OP at run time + at the end of this insn (but not necessarily elsewhere in the function). + + The RTX OP is typically an arithmetic expression. For example, when a + sequence of insns such as a library call is used to perform an + arithmetic operation, this kind of note is attached to the insn that + produces or copies the final value. It tells the CSE pass how to + think of that value. + +`REG_RETVAL' + This insn copies the value of a library call, and OP is the first insn + that was generated to set up the arguments for the library call. + + Flow analysis uses this note to delete all of a library call whose + result is dead. + +`REG_WAS_0' + The register OP contained zero before this insn. You can rely on this + note if it is present; its absence implies nothing. + +(The only difference between the expression codes `insn_list' and +`expr_list' is that the first operand of an `insn_list' is assumed to be an +insn and is printed in debugging dumps as the insn's unique id; the first +operand of an `expr_list' is printed in the ordinary way as an expression.) + + +File: internals, Node: Calls, Next: Sharing, Prev: Insns, Up: RTL + +RTL Representation of Function-Call Insns +========================================= + +Insns that call subroutines have the RTL expression code `call_insn'. +These insns must satisfy special rules, and their bodies must use a special +RTL expression code, `call'. + +A `call' expression has two operands, as follows: + + (call NBYTES (mem:FM ADDR)) + +Here NBYTES is an operand that represents the number of bytes of argument +data being passed to the subroutine, FM is a machine mode (which must equal +as the definition of the `FUNCTION_MODE' macro in the machine description) +and ADDR represents the address of the subroutine. + +For a subroutine that returns no value, the `call' RTX as shown above is +the entire body of the insn. + +For a subroutine that returns a value whose mode is not `BLKmode', the +value is returned in a hard register. If this register's number is R, then +the body of the call insn looks like this: + + (set (reg:M R) + (call NBYTES (mem:FM ADDR))) + +This RTL expression makes it clear (to the optimizer passes) that the +appropriate register receives a useful value in this insn. + +Immediately after RTL generation, if the value of the subroutine is +actually used, this call insn is always followed closely by an insn which +refers to the register R. This remains true through all the optimizer +passes until cross jumping occurs. + +The following insn has one of two forms. Either it copies the value into a +pseudo-register, like this: + + (set (reg:M P) (reg:M R)) + +or (in the case where the calling function will simply return whatever +value the call produced, and no operation is needed to do this): + + (use (reg:M R)) + +Between the call insn and this following insn there may intervene only a +stack-adjustment insn (and perhaps some `note' insns). + +When a subroutine returns a `BLKmode' value, it is handled by passing to +the subroutine the address of a place to store the value. So the call insn +itself does not ``return'' any value, and it has the same RTL form as a +call that returns nothing.  File: internals, Node: Sharing, Prev: Calls, Up: RTL @@ -100,7 +553,6 @@ is inside a quoted string. See the next chapter for information on the C header file. - * Menu: * Patterns:: How to write instruction patterns. @@ -195,7 +647,6 @@ Here is an actual example of an instruct return \"tstl %0\"; return \"cmpl #0,%0\"; }") - This is an instruction that sets the condition codes based on the value of a general operand. It has no condition, so any insn whose RTL description has the form shown may be handled according to this pattern. The name @@ -396,7 +847,6 @@ use `which_alternative' to choose betwee ? \"clrreg %0\" : \"clrmem %0\"); ") -  File: internals, Node: Constraints, Next: Standard Names, Prev: Output Statement, Up: Machine Desc @@ -410,7 +860,6 @@ memory reference, and which kinds of add immediate constant, and which possible values it may have. Constraints can also require two operands to match. - * Menu: * Simple Constraints:: Basic use of constraints. @@ -561,7 +1010,6 @@ Contrast, therefore, the two instruction "" "...") - which has two operands, one of which must appear in two places, and (define_insn "" @@ -571,7 +1019,6 @@ which has two operands, one of which mus "" "...") - which has three operands, two of which are required by a constraint to be identical. If we are considering an insn of the form @@ -580,7 +1027,6 @@ identical. If we are considering an ins (plus:SI (reg:SI 6) (reg:SI 109))) ...) - the first pattern would not apply at all, because this insn does not contain two identical subexpressions in the right place. The pattern would say, ``That does not look like an add instruction; try other patterns.'' @@ -598,7 +1044,6 @@ results might look like this: (plus:SI (reg:SI 3) (reg:SI 109))) ...) - Because insns that don't fit the constraints are fixed up by loading operands into registers, every instruction pattern's constraints must permit the case where all the operands are in registers. It need not @@ -610,598 +1055,4 @@ instruction valid. Instruction patterns valid by attaching a condition-expression that refuses to match an insn at all if the crucial operand is a register. - -File: internals, Node: Multi-Alternative, Next: Class Preferences, Prev: Simple Constraints, Up: Constraints - -Multiple Alternative Constraints --------------------------------- - -Sometimes a single instruction has multiple alternative sets of possible -operands. For example, on the 68000, a logical-or instruction can combine -register or an immediate value into memory, or it can combine any kind of -operand into a register; but it cannot combine one memory location into -another. - -These constraints are represented as multiple alternatives. An alternative -can be described by a series of letters for each operand. The overall -constraint for an operand is made from the letters for this operand from -the first alternative, a comma, the letters for this operand from the -second alternative, a comma, and so on until the last alternative. Here is -how it is done for fullword logical-or on the 68000: - - (define_insn "iorsi3" - [(set (match_operand:SI 0 "general_operand" "=%m,d") - (ior:SI (match_operand:SI 1 "general_operand" "0,0") - (match_operand:SI 2 "general_operand" "dKs,dmKs")))] - ...) - - -The first alternative has `m' (memory) for operand 0, `0' for operand 1 -(meaning it must match operand 0), and `dKs' for operand 2. The second -alternative has `d' (data register) for operand 0, `0' for operand 1, and -`dmKs' for operand 2. The `=' and `%' in the constraint for operand 0 are -not part of any alternative; their meaning is explained in the next section. - -If all the operands fit any one alternative, the instruction is valid. -Otherwise, for each alternative, the compiler counts how many instructions -must be added to copy the operands so that that alternative applies. The -alternative requiring the least copying is chosen. If two alternatives -need the same amount of copying, the one that comes first is chosen. These -choices can be altered with the `?' and `!' characters: - -`?' - Disparage slightly the alternative that the `?' appears in, as a - choice when no alternative applies exactly. The compiler regards this - alternative as one unit more costly for each `?' that appears in it. - -`!' - Disparage severely the alternative that the `!' appears in. When - operands must be copied into registers, the compiler will never choose - this alternative as the one to strive for. - -When an insn pattern has multiple alternatives in its constraints, often -the appearance of the assembler code determined mostly by which alternative -was matched. When this is so, the C code for writing the assembler code -can use the variable `which_alternative', which is the ordinal number of -the alternative that was actually satisfied (0 for the first, 1 for the -second alternative, etc.). For example: - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "r,m") - (const_int 0))] - "" - "* - return (which_alternative == 0 - ? \"clrreg %0\" : \"clrmem %0\"); - ") - - - -File: internals, Node: Class Preferences, Next: Modifiers, Prev: Multi-Alternative, Up: Constraints - -Register Class Preferences --------------------------- - -The operand constraints have another function: they enable the compiler to -decide which kind of hardware register a pseudo register is best allocated -to. The compiler examines the constraints that apply to the insns that use -the pseudo register, looking for the machine-dependent letters such as `d' -and `a' that specify classes of registers. The pseudo register is put in -whichever class gets the most ``votes''. The constraint letters `g' and -`r' also vote: they vote in favor of a general register. The machine -description says which registers are considered general. - -Of course, on some machines all registers are equivalent, and no register -classes are defined. Then none of this complexity is relevant. - - -File: internals, Node: Modifiers, Next: No Constraints, Prev: Class Preferences, Up: Constraints - -Constraint Modifier Characters ------------------------------- - -`=' - Means that this operand is write-only for this instruction: the - previous value is discarded and replaced by output data. - -`+' - Means that this operand is both read and written by the instruction. - - When the compiler fixes up the operands to satisfy the constraints, it - needs to know which operands are inputs to the instruction and which - are outputs from it. `=' identifies an output; `+' identifies an - operand that is both input and output; all other operands are assumed - to be input only. - -`&' - Means (in a particular alternative) that this operand is written - before the instruction is finished using the input operands. - Therefore, this operand may not lie in a register that is used as an - input operand or as part of any memory address. - - `&' applies only to the alternative in which it is written. In - constraints with multiple alternatives, sometimes one alternative - requires `&' while others do not. See, for example, the `movdf' insn - of the 68000. - - `&' does not obviate the need to write `='. - -`%' - Declares the instruction to be commutative for this operand and the - following operand. This means that the compiler may interchange the - two operands if that is the cheapest way to make all operands fit the - constraints. This is often used in patterns for addition instructions - that really have only two operands: the result must go in one of the - arguments. Here for example, is how the 68000 halfword-add - instruction is defined: - - (define_insn "addhi3" - [(set (match_operand:HI 0 "general_operand" "=m,r") - (plus:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "general_operand" "di,g")))] - ...) - - - Note that in previous versions of GNU CC the `%' constraint modifier - always applied to operands 1 and 2 regardless of which operand it was - written in. The usual custom was to write it in operand 0. Now it - must be in operand 1 if the operands to be exchanged are 1 and 2. - -`#' - Says that all following characters, up to the next comma, are to be - ignored as a constraint. They are significant only for choosing - register preferences. - -`*' - Says that the following character should be ignored when choosing - register preferences. `*' has no effect on the meaning of the - constraint as a constraint. - - Here is an example: the 68000 has an instruction to sign-extend a - halfword in a data register, and can also sign-extend a value by - copying it into an address register. While either kind of register is - acceptable, the constraints on an address-register destination are - less strict, so it is best if register allocation makes an address - register its goal. Therefore, `*' is used so that the `d' constraint - letter (for data register) is ignored when computing register - preferences. - - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=*d,a") - (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,g")))] - ...) - - - -File: internals, Node: No Constraints, Prev: Modifiers, Up: Constraints - -Not Using Constraints ---------------------- - -Some machines are so clean that operand constraints are not required. For -example, on the Vax, an operand valid in one context is valid in any other -context. On such a machine, every operand constraint would be `g', -excepting only operands of ``load address'' instructions which are written -as if they referred to a memory location's contents but actual refer to its -address. They would have constraint `p'. - -For such machines, instead of writing `g' and `p' for all the constraints, -you can choose to write a description with empty constraints. Then you -write `""' for the constraint in every `match_operand'. Address operands -are identified by writing an `address' expression around the -`match_operand', not by their constraints. - -When the machine description has just empty constraints, certain parts of -compilation are skipped, making the compiler faster. - - -File: internals, Node: Standard Names, Next: Pattern Ordering, Prev: Constraints, Up: Machine Desc - -Standard Names for Patterns Used in Generation -============================================== - -Here is a table of the instruction names that are meaningful in the RTL -generation pass of the compiler. Giving one of these names to an -instruction pattern tells the RTL generation pass that it can use the -pattern in to accomplish a certain task. - -`movM' - Here M is a two-letter machine mode name, in lower case. This - instruction pattern moves data with that machine mode from operand 1 - to operand 0. For example, `movsi' moves full-word data. - - If operand 0 is a `subreg' with mode M of a register whose natural - mode is wider than M, the effect of this instruction is to store the - specified value in the part of the register that corresponds to mode - M. The effect on the rest of the register is undefined. - -`movstrictM' - Like `movM' except that if operand 0 is a `subreg' with mode M of a - register whose natural mode is wider, the `movstrictM' instruction is - guaranteed not to alter any of the register except the part which - belongs to mode M. - -`addM3' - Add operand 2 and operand 1, storing the result in operand 0. All - operands must have mode M. This can be used even on two-address - machines, by means of constraints requiring operands 1 and 0 to be the - same location. - -`subM3', `mulM3', `umulM3', `divM3', `udivM3', `modM3', `umodM3', `andM3', `iorM3', `xorM3' - Similar, for other arithmetic operations. - -`andcbM3' - Bitwise logical-and operand 1 with the complement of operand 2 and - store the result in operand 0. - -`mulhisi3' - Multiply operands 1 and 2, which have mode `HImode', and store a - `SImode' product in operand 0. - -`mulqihi3', `mulsidi3' - Similar widening-multiplication instructions of other widths. - -`umulqihi3', `umulhisi3', `umulsidi3' - Similar widening-multiplication instructions that do unsigned - multiplication. - -`divmodM4' - Signed division that produces both a quotient and a remainder. - Operand 1 is divided by operand 2 to produce a quotient stored in - operand 0 and a remainder stored in operand 3. - -`udivmodM4' - Similar, but does unsigned division. - -`divmodMN4' - Like `divmodM4' except that only the dividend has mode M; the divisor, - quotient and remainder have mode N. For example, the Vax has a - `divmoddisi4' instruction (but it is omitted from the machine - description, because it is so slow that it is faster to compute - remainders by the circumlocution that the compiler will use if this - instruction is not available). - -`ashlM3' - Arithmetic-shift operand 1 left by a number of bits specified by - operand 2, and store the result in operand 0. Operand 2 has mode - `SImode', not mode M. - -`ashrM3', `lshlM3', `lshrM3', `rotlM3', `rotrM3' - Other shift and rotate instructions. - - Logical and arithmetic left shift are the same. Machines that do not - allow negative shift counts often have only one instruction for - shifting left. On such machines, you should define a pattern named - `ashlM3' and leave `lshlM3' undefined. - -`negM2' - Negate operand 1 and store the result in operand 0. - -`absM2' - Store the absolute value of operand 1 into operand 0. - -`sqrtM2' - Store the square root of operand 1 into operand 0. - -`ffsM2' - Store into operand 0 one plus the index of the least significant 1-bit - of operand 1. If operand 1 is zero, store zero. M is the mode of - operand 0; operand 1's mode is specified by the instruction pattern, - and the compiler will convert the operand to that mode before - generating the instruction. - -`one_cmplM2' - Store the bitwise-complement of operand 1 into operand 0. - -`cmpM' - Compare operand 0 and operand 1, and set the condition codes. The RTL - pattern should look like this: - - (set (cc0) (minus (match_operand:M 0 ...) - (match_operand:M 1 ...))) - - - Each such definition in the machine description, for integer mode M, - must have a corresponding `tstM' pattern, because optimization can - simplify the compare into a test when operand 1 is zero. - -`tstM' - Compare operand 0 against zero, and set the condition codes. The RTL - pattern should look like this: - - (set (cc0) (match_operand:M 0 ...)) - - -`movstrM' - Block move instruction. The addresses of the destination and source - strings are the first two operands, and both are in mode `Pmode'. The - number of bytes to move is the third operand, in mode M. - -`cmpstrM' - Block compare instruction, with operands like `movstrM' except that - the two memory blocks are compared byte by byte in lexicographic - order. The effect of the instruction is to set the condition codes. - -`floatMN2' - Convert operand 1 (valid for fixed point mode M) to floating point - MODE N and store in operand 0 (which has mode N). - -`fixMN2' - Convert operand 1 (valid for floating point mode M) to fixed point - MODE N as a signed number and store in operand 0 (which has mode N). - This instruction's result is defined only when the value of operand 1 - is an integer. - -`fixunsMN2' - Convert operand 1 (valid for floating point mode M) to fixed point - MODE N as an unsigned number and store in operand 0 (which has mode - N). This instruction's result is defined only when the value of - operand 1 is an integer. - -`ftruncM2' - Convert operand 1 (valid for floating point mode M) to an integer - value, still represented in floating point mode M, and store it in - operand 0 (valid for floating point mode M). - -`fix_truncMN2' - Like `fixMN2' but works for any floating point value of mode M by - converting the value to an integer. - -`fixuns_truncMN2' - Like `fixunsMN2' but works for any floating point value of mode M by - converting the value to an integer. - -`truncMN' - Truncate operand 1 (valid for mode M) to mode N and store in operand 0 - (which has mode N). Both modes must be fixed point or both floating - point. - -`extendMN' - Sign-extend operand 1 (valid for mode M) to mode N and store in - operand 0 (which has mode N). Both modes must be fixed point or both - floating point. - -`zero_extendMN' - Zero-extend operand 1 (valid for mode M) to mode N and store in - operand 0 (which has mode N). Both modes must be fixed point. - -`extv' - Extract a bit-field from operand 1 (a register or memory operand), - where operand 2 specifies the width in bits and operand 3 the starting - bit, and store it in operand 0. Operand 0 must have `Simode'. - Operand 1 may have mode `QImode' or `SImode'; often `SImode' is - allowed only for registers. Operands 2 and 3 must be valid for - `SImode'. - - The RTL generation pass generates this instruction only with constants - for operands 2 and 3. - - The bit-field value is sign-extended to a full word integer before it - is stored in operand 0. - -`extzv' - Like `extv' except that the bit-field value is zero-extended. - -`insv' - Store operand 3 (which must be valid for `SImode') into a bit-field in - operand 0, where operand 1 specifies the width in bits and operand 2 - the starting bit. Operand 0 may have mode `QImode' or `SImode'; often - `SImode' is allowed only for registers. Operands 1 and 2 must be - valid for `SImode'. - - The RTL generation pass generates this instruction only with constants - for operands 1 and 2. - -`sCOND' - Store zero or nonzero in the operand according to the condition codes. - Value stored is nonzero iff the condition COND is true. COND is the - name of a comparison operation expression code, such as `eq', `lt' or - `leu'. - - You specify the mode that the operand must have when you write the - `match_operand' expression. The compiler automatically sees which - mode you have used and supplies an operand of that mode. - - The value stored for a true condition must have 1 as its low bit. - Otherwise the instruction is not suitable and must be omitted from the - machine description. You must tell the compiler exactly which value - is stored by defining the macro `STORE_FLAG_VALUE'. - -`bCOND' - Conditional branch instruction. Operand 0 is a `label_ref' that - refers to the label to jump to. Jump if the condition codes meet - condition COND. - -`call' - Subroutine call instruction. Operand 1 is the number of bytes of - arguments pushed (in mode `SImode'), and operand 0 is the function to - call. Operand 0 should be a `mem' RTX whose address is the address of - the function. - -`return' - Subroutine return instruction. This instruction pattern name should - be defined only if a single instruction can do all the work of - returning from a function. - -`tablejump' -`caseM' - -File: internals, Node: Pattern Ordering, Next: Dependent Patterns, Prev: Standard Names, Up: Machine Desc - -When the Order of Patterns Matters -================================== - -Sometimes an insn can match more than one instruction pattern. Then the -pattern that appears first in the machine description is the one used. -Therefore, more specific patterns (patterns that will match fewer things) -and faster instructions (those that will produce better code when they do -match) should usually go first in the description. - -In some cases the effect of ordering the patterns can be used to hide a -pattern when it is not valid. For example, the 68000 has an instruction -for converting a fullword to floating point and another for converting a -byte to floating point. An instruction converting an integer to floating -point could match either one. We put the pattern to convert the fullword -first to make sure that one will be used rather than the other. (Otherwise -a large integer might be generated as a single-byte immediate quantity, -which would not work.) Instead of using this pattern ordering it would be -possible to make the pattern for convert-a-byte smart enough to deal -properly with any constant value. - - -File: internals, Node: Dependent Patterns, Next: Jump Patterns, Prev: Pattern Ordering, Up: Machine Desc - -Interdependence of Patterns -=========================== - -Every machine description must have a named pattern for each of the -conditional branch names `bCOND'. The recognition template must always -have the form - - (set (pc) - (if_then_else (COND (cc0) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc))) - - -In addition, every machine description must have an anonymous pattern for -each of the possible reverse-conditional branches. These patterns look like - - (set (pc) - (if_then_else (COND (cc0) (const_int 0)) - (pc) - (label_ref (match_operand 0 "" "")))) - - -They are necessary because jump optimization can turn direct-conditional -branches into reverse-conditional branches. - -The compiler does more with RTL than just create it from patterns and -recognize the patterns: it can perform arithmetic expression codes when -constant values for their operands can be determined. As a result, -sometimes having one pattern can require other patterns. For example, the -Vax has no `and' instruction, but it has `and not' instructions. Here is -the definition of one of them: - - (define_insn "andcbsi2" - [(set (match_operand:SI 0 "general_operand" "") - (and:SI (match_dup 0) - (not:SI (match_operand:SI - 1 "general_operand" ""))))] - "" - "bicl2 %1,%0") - - -If operand 1 is an explicit integer constant, an instruction constructed -using that pattern can be simplified into an `and' like this: - - (set (reg:SI 41) - (and:SI (reg:SI 41) - (const_int 0xffff7fff))) - - -(where the integer constant is the one's complement of what appeared in the -original instruction). - -To avoid a fatal error, the compiler must have a pattern that recognizes -such an instruction. Here is what is used: - - (define_insn "" - [(set (match_operand:SI 0 "general_operand" "") - (and:SI (match_dup 0) - (match_operand:SI 1 "general_operand" "")))] - "GET_CODE (operands[1]) == CONST_INT" - "* - { operands[1] - = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[1])); - return \"bicl2 %1,%0\"; - }") - - -Whereas a pattern to match a general `and' instruction is impossible to -support on the Vax, this pattern is possible because it matches only a -constant second argument: a special case that can be output as an `and not' -instruction. - -A ``compare'' instruction whose RTL looks like this: - - (set (cc0) (minus OPERAND (const_int 0))) - - -may be simplified by optimization into a ``test'' like this: - - (set (cc0) OPERAND) - - -So in the machine description, each ``compare'' pattern for an integer mode -must have a corresponding ``test'' pattern that will match the result of -such simplification. - -In some cases machines support instructions identical except for the -machine mode of one or more operands. For example, there may be -``sign-extend halfword'' and ``sign-extend byte'' instructions whose -patterns are - - (set (match_operand:SI 0 ...) - (extend:SI (match_operand:HI 1 ...))) - - (set (match_operand:SI 0 ...) - (extend:SI (match_operand:QI 1 ...))) - - -Constant integers do not specify a machine mode, so an instruction to -extend a constant value could match either pattern. The pattern it -actually will match is the one that appears first in the file. For correct -results, this must be the one for the widest possible mode (`HImode', -here). If the pattern matches the `QImode' instruction, the results will -be incorrect if the constant value does not actually fit that mode. - -Such instructions to extend constants are rarely generated because they are -optimized away, but they do occasionally happen in nonoptimized compilations. - - -File: internals, Node: Jump Patterns, Next: Peephole Definitions, Prev: Dependent Patterns, Up: Machine Desc - -Defining Jump Instruction Patterns -================================== - -GNU CC assumes that the machine has a condition code. A comparison insn -sets the condition code, recording the results of both signed and unsigned -comparison of the given operands. A separate branch insn tests the -condition code and branches or not according its value. The branch insns -come in distinct signed and unsigned flavors. Many common machines, such -as the Vax, the 68000 and the 32000, work this way. - -Some machines have distinct signed and unsigned compare instructions, and -only one set of conditional branch instructions. The easiest way to handle -these machines is to treat them just like the others until the final stage -where assembly code is written. At this time, when outputting code for the -compare instruction, peek ahead at the following branch using `NEXT_INSN -(insn)'. (The variable `insn' refers to the insn being output, in the -output-writing code in an instruction pattern.) If the RTL says that is an -unsigned branch, output an unsigned compare; otherwise output a signed -compare. When the branch itself is output, you can treat signed and -unsigned branches identically. - -The reason you can do this is that GNU CC always generates a pair of -consecutive RTL insns, one to set the condition code and one to test it, -and keeps the pair inviolate until the end. - -To go with this technique, you must define the machine-description macro -`NOTICE_UPDATE_CC' to do `CC_STATUS_INIT'; in other words, no compare -instruction is superfluous. - -Some machines have compare-and-branch instructions and no condition code. -A similar technique works for them. When it is time to ``output'' a -compare instruction, record its operands in two static variables. When -outputting the branch-on-condition-code instruction that follows, actually -output a compare-and-branch instruction that uses the remembered operands. - -It also works to define patterns for compare-and-branch instructions. In -optimizing compilation, the pair of compare and branch instructions will be -combined accoprding to these patterns. But this does not happen if -optimization is not requested. So you must use one of the solutions above -in addition to any special patterns you define. - - + \ No newline at end of file