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1.1 root 1: /* Allocate registers within a basic block, for GNU compiler. 1.1.1.7 ! root 2: Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 6: GNU CC is free software; you can redistribute it and/or modify 7: it under the terms of the GNU General Public License as published by 8: the Free Software Foundation; either version 2, or (at your option) 9: any later version. 10: 11: GNU CC is distributed in the hope that it will be useful, 12: but WITHOUT ANY WARRANTY; without even the implied warranty of 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: GNU General Public License for more details. 15: 16: You should have received a copy of the GNU General Public License 17: along with GNU CC; see the file COPYING. If not, write to 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 19: 20: 21: /* Allocation of hard register numbers to pseudo registers is done in 22: two passes. In this pass we consider only regs that are born and 23: die once within one basic block. We do this one basic block at a 24: time. Then the next pass allocates the registers that remain. 25: Two passes are used because this pass uses methods that work only 26: on linear code, but that do a better job than the general methods 27: used in global_alloc, and more quickly too. 28: 29: The assignments made are recorded in the vector reg_renumber 30: whose space is allocated here. The rtl code itself is not altered. 31: 32: We assign each instruction in the basic block a number 33: which is its order from the beginning of the block. 34: Then we can represent the lifetime of a pseudo register with 35: a pair of numbers, and check for conflicts easily. 36: We can record the availability of hard registers with a 37: HARD_REG_SET for each instruction. The HARD_REG_SET 38: contains 0 or 1 for each hard reg. 39: 40: To avoid register shuffling, we tie registers together when one 41: dies by being copied into another, or dies in an instruction that 42: does arithmetic to produce another. The tied registers are 43: allocated as one. Registers with different reg class preferences 44: can never be tied unless the class preferred by one is a subclass 45: of the one preferred by the other. 46: 47: Tying is represented with "quantity numbers". 48: A non-tied register is given a new quantity number. 49: Tied registers have the same quantity number. 50: 51: We have provision to exempt registers, even when they are contained 52: within the block, that can be tied to others that are not contained in it. 53: This is so that global_alloc could process them both and tie them then. 54: But this is currently disabled since tying in global_alloc is not 55: yet implemented. */ 56: 57: #include <stdio.h> 58: #include "config.h" 59: #include "rtl.h" 60: #include "flags.h" 61: #include "basic-block.h" 62: #include "regs.h" 63: #include "hard-reg-set.h" 64: #include "insn-config.h" 65: #include "recog.h" 66: #include "output.h" 67: 1.1.1.5 root 68: /* Pseudos allocated here cannot be reallocated by global.c if the hard 69: register is used as a spill register. So we don't allocate such pseudos 70: here if their preferred class is likely to be used by spills. 71: 72: On most machines, the appropriate test is if the class has one 73: register, so we default to that. */ 74: 75: #ifndef CLASS_LIKELY_SPILLED_P 76: #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1) 77: #endif 78: 1.1 root 79: /* Next quantity number available for allocation. */ 80: 81: static int next_qty; 82: 83: /* In all the following vectors indexed by quantity number. */ 84: 85: /* Element Q is the hard reg number chosen for quantity Q, 86: or -1 if none was found. */ 87: 88: static short *qty_phys_reg; 89: 90: /* We maintain two hard register sets that indicate suggested hard registers 91: for each quantity. The first, qty_phys_copy_sugg, contains hard registers 92: that are tied to the quantity by a simple copy. The second contains all 93: hard registers that are tied to the quantity via an arithmetic operation. 94: 95: The former register set is given priority for allocation. This tends to 96: eliminate copy insns. */ 97: 98: /* Element Q is a set of hard registers that are suggested for quantity Q by 99: copy insns. */ 100: 101: static HARD_REG_SET *qty_phys_copy_sugg; 102: 103: /* Element Q is a set of hard registers that are suggested for quantity Q by 104: arithmetic insns. */ 105: 106: static HARD_REG_SET *qty_phys_sugg; 107: 1.1.1.7 ! root 108: /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ 1.1 root 109: 1.1.1.7 ! root 110: static short *qty_phys_num_copy_sugg; 1.1 root 111: 1.1.1.7 ! root 112: /* Element Q is the number of suggested registers in qty_phys_sugg. */ 1.1 root 113: 1.1.1.7 ! root 114: static short *qty_phys_num_sugg; 1.1 root 115: 116: /* Element Q is the number of refs to quantity Q. */ 117: 1.1.1.5 root 118: static int *qty_n_refs; 1.1 root 119: 120: /* Element Q is a reg class contained in (smaller than) the 121: preferred classes of all the pseudo regs that are tied in quantity Q. 122: This is the preferred class for allocating that quantity. */ 123: 124: static enum reg_class *qty_min_class; 125: 126: /* Insn number (counting from head of basic block) 127: where quantity Q was born. -1 if birth has not been recorded. */ 128: 129: static int *qty_birth; 130: 131: /* Insn number (counting from head of basic block) 132: where quantity Q died. Due to the way tying is done, 133: and the fact that we consider in this pass only regs that die but once, 134: a quantity can die only once. Each quantity's life span 135: is a set of consecutive insns. -1 if death has not been recorded. */ 136: 137: static int *qty_death; 138: 139: /* Number of words needed to hold the data in quantity Q. 140: This depends on its machine mode. It is used for these purposes: 141: 1. It is used in computing the relative importances of qtys, 142: which determines the order in which we look for regs for them. 143: 2. It is used in rules that prevent tying several registers of 144: different sizes in a way that is geometrically impossible 145: (see combine_regs). */ 146: 147: static int *qty_size; 148: 149: /* This holds the mode of the registers that are tied to qty Q, 150: or VOIDmode if registers with differing modes are tied together. */ 151: 152: static enum machine_mode *qty_mode; 153: 154: /* Number of times a reg tied to qty Q lives across a CALL_INSN. */ 155: 156: static int *qty_n_calls_crossed; 157: 1.1.1.4 root 158: /* Register class within which we allocate qty Q if we can't get 159: its preferred class. */ 1.1 root 160: 1.1.1.4 root 161: static enum reg_class *qty_alternate_class; 1.1 root 162: 163: /* Element Q is the SCRATCH expression for which this quantity is being 164: allocated or 0 if this quantity is allocating registers. */ 165: 166: static rtx *qty_scratch_rtx; 167: 1.1.1.7 ! root 168: /* Element Q is nonzero if this quantity has been used in a SUBREG ! 169: that changes its size. */ ! 170: ! 171: static char *qty_changes_size; ! 172: 1.1 root 173: /* Element Q is the register number of one pseudo register whose 174: reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This 175: register should be the head of the chain maintained in reg_next_in_qty. */ 176: 1.1.1.5 root 177: static int *qty_first_reg; 1.1 root 178: 179: /* If (REG N) has been assigned a quantity number, is a register number 180: of another register assigned the same quantity number, or -1 for the 181: end of the chain. qty_first_reg point to the head of this chain. */ 182: 1.1.1.5 root 183: static int *reg_next_in_qty; 1.1 root 184: 185: /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg 186: if it is >= 0, 187: of -1 if this register cannot be allocated by local-alloc, 188: or -2 if not known yet. 189: 190: Note that if we see a use or death of pseudo register N with 191: reg_qty[N] == -2, register N must be local to the current block. If 192: it were used in more than one block, we would have reg_qty[N] == -1. 193: This relies on the fact that if reg_basic_block[N] is >= 0, register N 194: will not appear in any other block. We save a considerable number of 195: tests by exploiting this. 196: 197: If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not 198: be referenced. */ 199: 200: static int *reg_qty; 201: 202: /* The offset (in words) of register N within its quantity. 203: This can be nonzero if register N is SImode, and has been tied 204: to a subreg of a DImode register. */ 205: 206: static char *reg_offset; 207: 208: /* Vector of substitutions of register numbers, 209: used to map pseudo regs into hardware regs. 210: This is set up as a result of register allocation. 211: Element N is the hard reg assigned to pseudo reg N, 212: or is -1 if no hard reg was assigned. 213: If N is a hard reg number, element N is N. */ 214: 215: short *reg_renumber; 216: 217: /* Set of hard registers live at the current point in the scan 218: of the instructions in a basic block. */ 219: 220: static HARD_REG_SET regs_live; 221: 222: /* Each set of hard registers indicates registers live at a particular 223: point in the basic block. For N even, regs_live_at[N] says which 224: hard registers are needed *after* insn N/2 (i.e., they may not 225: conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. 226: 227: If an object is to conflict with the inputs of insn J but not the 228: outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, 229: if it is to conflict with the outputs of insn J but not the inputs of 230: insn J + 1, it is said to die at index J*2 + 1. */ 231: 232: static HARD_REG_SET *regs_live_at; 233: 1.1.1.6 root 234: int *scratch_block; 235: rtx *scratch_list; 236: int scratch_list_length; 237: static int scratch_index; 238: 1.1 root 239: /* Communicate local vars `insn_number' and `insn' 240: from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ 241: static int this_insn_number; 242: static rtx this_insn; 243: 1.1.1.7 ! root 244: static void alloc_qty PROTO((int, enum machine_mode, int, int)); ! 245: static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int)); ! 246: static void validate_equiv_mem_from_store PROTO((rtx, rtx)); ! 247: static int validate_equiv_mem PROTO((rtx, rtx, rtx)); ! 248: static int memref_referenced_p PROTO((rtx, rtx)); ! 249: static int memref_used_between_p PROTO((rtx, rtx, rtx)); ! 250: static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx)); ! 251: static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx)); ! 252: static void update_equiv_regs PROTO((void)); ! 253: static void block_alloc PROTO((int)); ! 254: static int qty_sugg_compare PROTO((int, int)); ! 255: static int qty_sugg_compare_1 PROTO((int *, int *)); ! 256: static int qty_compare PROTO((int, int)); ! 257: static int qty_compare_1 PROTO((int *, int *)); ! 258: static int combine_regs PROTO((rtx, rtx, int, int, rtx, int)); ! 259: static int reg_meets_class_p PROTO((int, enum reg_class)); ! 260: static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class, ! 261: int)); ! 262: static void update_qty_class PROTO((int, int)); ! 263: static void reg_is_set PROTO((rtx, rtx)); ! 264: static void reg_is_born PROTO((rtx, int)); ! 265: static void wipe_dead_reg PROTO((rtx, int)); ! 266: static int find_free_reg PROTO((enum reg_class, enum machine_mode, ! 267: int, int, int, int, int)); ! 268: static void mark_life PROTO((int, enum machine_mode, int)); ! 269: static void post_mark_life PROTO((int, enum machine_mode, int, int, int)); ! 270: static int no_conflict_p PROTO((rtx, rtx, rtx)); ! 271: static int requires_inout PROTO((char *)); 1.1 root 272: 273: /* Allocate a new quantity (new within current basic block) 274: for register number REGNO which is born at index BIRTH 275: within the block. MODE and SIZE are info on reg REGNO. */ 276: 277: static void 278: alloc_qty (regno, mode, size, birth) 279: int regno; 280: enum machine_mode mode; 281: int size, birth; 282: { 283: register int qty = next_qty++; 284: 285: reg_qty[regno] = qty; 286: reg_offset[regno] = 0; 287: reg_next_in_qty[regno] = -1; 288: 289: qty_first_reg[qty] = regno; 290: qty_size[qty] = size; 291: qty_mode[qty] = mode; 292: qty_birth[qty] = birth; 293: qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno]; 294: qty_min_class[qty] = reg_preferred_class (regno); 1.1.1.4 root 295: qty_alternate_class[qty] = reg_alternate_class (regno); 1.1 root 296: qty_n_refs[qty] = reg_n_refs[regno]; 1.1.1.7 ! root 297: qty_changes_size[qty] = reg_changes_size[regno]; 1.1 root 298: } 299: 300: /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx 301: used as operand N in INSN. We assume here that the SCRATCH is used in 302: a CLOBBER. */ 303: 304: static void 305: alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number) 306: rtx scratch; 307: int n; 308: rtx insn; 309: int insn_code_num, insn_number; 310: { 311: register int qty; 312: enum reg_class class; 313: char *p, c; 314: int i; 315: 1.1.1.4 root 316: #ifdef REGISTER_CONSTRAINTS 1.1 root 317: /* If we haven't yet computed which alternative will be used, do so now. 318: Then set P to the constraints for that alternative. */ 319: if (which_alternative == -1) 320: if (! constrain_operands (insn_code_num, 0)) 321: return; 322: 323: for (p = insn_operand_constraint[insn_code_num][n], i = 0; 324: *p && i < which_alternative; p++) 325: if (*p == ',') 326: i++; 327: 328: /* Compute the class required for this SCRATCH. If we don't need a 329: register, the class will remain NO_REGS. If we guessed the alternative 330: number incorrectly, reload will fix things up for us. */ 331: 332: class = NO_REGS; 333: while ((c = *p++) != '\0' && c != ',') 334: switch (c) 335: { 336: case '=': case '+': case '?': 337: case '#': case '&': case '!': 338: case '*': case '%': 339: case '0': case '1': case '2': case '3': case '4': 340: case 'm': case '<': case '>': case 'V': case 'o': 341: case 'E': case 'F': case 'G': case 'H': 342: case 's': case 'i': case 'n': 343: case 'I': case 'J': case 'K': case 'L': 344: case 'M': case 'N': case 'O': case 'P': 345: #ifdef EXTRA_CONSTRAINT 346: case 'Q': case 'R': case 'S': case 'T': case 'U': 347: #endif 348: case 'p': 349: /* These don't say anything we care about. */ 350: break; 351: 352: case 'X': 353: /* We don't need to allocate this SCRATCH. */ 354: return; 355: 356: case 'g': case 'r': 357: class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; 358: break; 359: 360: default: 361: class 362: = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)]; 363: break; 364: } 365: 1.1.1.6 root 366: if (class == NO_REGS) 1.1 root 367: return; 368: 1.1.1.4 root 369: #else /* REGISTER_CONSTRAINTS */ 370: 371: class = GENERAL_REGS; 372: #endif 373: 374: 1.1 root 375: qty = next_qty++; 376: 377: qty_first_reg[qty] = -1; 378: qty_scratch_rtx[qty] = scratch; 379: qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch)); 380: qty_mode[qty] = GET_MODE (scratch); 381: qty_birth[qty] = 2 * insn_number - 1; 382: qty_death[qty] = 2 * insn_number + 1; 383: qty_n_calls_crossed[qty] = 0; 384: qty_min_class[qty] = class; 1.1.1.4 root 385: qty_alternate_class[qty] = NO_REGS; 1.1 root 386: qty_n_refs[qty] = 1; 1.1.1.7 ! root 387: qty_changes_size[qty] = 0; 1.1 root 388: } 389: 390: /* Main entry point of this file. */ 391: 392: void 393: local_alloc () 394: { 395: register int b, i; 396: int max_qty; 397: 398: /* Leaf functions and non-leaf functions have different needs. 399: If defined, let the machine say what kind of ordering we 400: should use. */ 401: #ifdef ORDER_REGS_FOR_LOCAL_ALLOC 402: ORDER_REGS_FOR_LOCAL_ALLOC; 403: #endif 404: 405: /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected 406: registers. */ 407: update_equiv_regs (); 408: 409: /* This sets the maximum number of quantities we can have. Quantity 1.1.1.2 root 410: numbers start at zero and we can have one for each pseudo plus the 1.1.1.3 root 411: number of SCRATCHes in the largest block, in the worst case. */ 1.1 root 412: max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch; 413: 414: /* Allocate vectors of temporary data. 415: See the declarations of these variables, above, 416: for what they mean. */ 417: 1.1.1.6 root 418: /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate. 419: Instead of allocating this much memory from now until the end of 420: reload, only allocate space for MAX_QTY SCRATCHes. If there are more 421: reload will allocate them. */ 422: 423: scratch_list_length = max_qty; 424: scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx)); 1.1.1.7 ! root 425: bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx)); 1.1.1.6 root 426: scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int)); 1.1.1.7 ! root 427: bzero ((char *) scratch_block, scratch_list_length * sizeof (int)); 1.1.1.6 root 428: scratch_index = 0; 429: 1.1 root 430: qty_phys_reg = (short *) alloca (max_qty * sizeof (short)); 1.1.1.7 ! root 431: qty_phys_copy_sugg ! 432: = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); ! 433: qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short)); 1.1 root 434: qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); 1.1.1.7 ! root 435: qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short)); 1.1 root 436: qty_birth = (int *) alloca (max_qty * sizeof (int)); 437: qty_death = (int *) alloca (max_qty * sizeof (int)); 438: qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx)); 1.1.1.5 root 439: qty_first_reg = (int *) alloca (max_qty * sizeof (int)); 1.1 root 440: qty_size = (int *) alloca (max_qty * sizeof (int)); 1.1.1.7 ! root 441: qty_mode ! 442: = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode)); 1.1 root 443: qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int)); 1.1.1.7 ! root 444: qty_min_class ! 445: = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); ! 446: qty_alternate_class ! 447: = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); 1.1.1.5 root 448: qty_n_refs = (int *) alloca (max_qty * sizeof (int)); 1.1.1.7 ! root 449: qty_changes_size = (char *) alloca (max_qty * sizeof (char)); 1.1 root 450: 451: reg_qty = (int *) alloca (max_regno * sizeof (int)); 452: reg_offset = (char *) alloca (max_regno * sizeof (char)); 1.1.1.5 root 453: reg_next_in_qty = (int *) alloca (max_regno * sizeof (int)); 1.1 root 454: 455: reg_renumber = (short *) oballoc (max_regno * sizeof (short)); 456: for (i = 0; i < max_regno; i++) 457: reg_renumber[i] = -1; 458: 459: /* Determine which pseudo-registers can be allocated by local-alloc. 460: In general, these are the registers used only in a single block and 461: which only die once. However, if a register's preferred class has only 1.1.1.5 root 462: a few entries, don't allocate this register here unless it is preferred 1.1 root 463: or nothing since retry_global_alloc won't be able to move it to 464: GENERAL_REGS if a reload register of this class is needed. 465: 466: We need not be concerned with which block actually uses the register 467: since we will never see it outside that block. */ 468: 469: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 470: { 471: if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1 1.1.1.4 root 472: && (reg_alternate_class (i) == NO_REGS 1.1.1.5 root 473: || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) 1.1 root 474: reg_qty[i] = -2; 475: else 476: reg_qty[i] = -1; 477: } 478: 479: /* Force loop below to initialize entire quantity array. */ 480: next_qty = max_qty; 481: 482: /* Allocate each block's local registers, block by block. */ 483: 484: for (b = 0; b < n_basic_blocks; b++) 485: { 486: /* NEXT_QTY indicates which elements of the `qty_...' 487: vectors might need to be initialized because they were used 488: for the previous block; it is set to the entire array before 489: block 0. Initialize those, with explicit loop if there are few, 490: else with bzero and bcopy. Do not initialize vectors that are 491: explicit set by `alloc_qty'. */ 492: 493: if (next_qty < 6) 494: { 495: for (i = 0; i < next_qty; i++) 496: { 497: qty_scratch_rtx[i] = 0; 498: CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); 1.1.1.7 ! root 499: qty_phys_num_copy_sugg[i] = 0; 1.1 root 500: CLEAR_HARD_REG_SET (qty_phys_sugg[i]); 1.1.1.7 ! root 501: qty_phys_num_sugg[i] = 0; 1.1 root 502: } 503: } 504: else 505: { 506: #define CLEAR(vector) \ 1.1.1.7 ! root 507: bzero ((char *) (vector), (sizeof (*(vector))) * next_qty); 1.1 root 508: 509: CLEAR (qty_scratch_rtx); 510: CLEAR (qty_phys_copy_sugg); 1.1.1.7 ! root 511: CLEAR (qty_phys_num_copy_sugg); 1.1 root 512: CLEAR (qty_phys_sugg); 1.1.1.7 ! root 513: CLEAR (qty_phys_num_sugg); 1.1 root 514: } 515: 516: next_qty = 0; 517: 518: block_alloc (b); 519: #ifdef USE_C_ALLOCA 520: alloca (0); 521: #endif 522: } 523: } 524: 525: /* Depth of loops we are in while in update_equiv_regs. */ 526: static int loop_depth; 527: 528: /* Used for communication between the following two functions: contains 529: a MEM that we wish to ensure remains unchanged. */ 530: static rtx equiv_mem; 531: 532: /* Set nonzero if EQUIV_MEM is modified. */ 533: static int equiv_mem_modified; 534: 535: /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. 536: Called via note_stores. */ 537: 538: static void 539: validate_equiv_mem_from_store (dest, set) 540: rtx dest; 541: rtx set; 542: { 543: if ((GET_CODE (dest) == REG 544: && reg_overlap_mentioned_p (dest, equiv_mem)) 545: || (GET_CODE (dest) == MEM 546: && true_dependence (dest, equiv_mem))) 547: equiv_mem_modified = 1; 548: } 549: 550: /* Verify that no store between START and the death of REG invalidates 551: MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, 552: by storing into an overlapping memory location, or with a non-const 553: CALL_INSN. 554: 555: Return 1 if MEMREF remains valid. */ 556: 557: static int 558: validate_equiv_mem (start, reg, memref) 559: rtx start; 560: rtx reg; 561: rtx memref; 562: { 563: rtx insn; 564: rtx note; 565: 566: equiv_mem = memref; 567: equiv_mem_modified = 0; 568: 569: /* If the memory reference has side effects or is volatile, it isn't a 570: valid equivalence. */ 571: if (side_effects_p (memref)) 572: return 0; 573: 574: for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) 575: { 576: if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 577: continue; 578: 579: if (find_reg_note (insn, REG_DEAD, reg)) 580: return 1; 581: 582: if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) 583: && ! CONST_CALL_P (insn)) 584: return 0; 585: 586: note_stores (PATTERN (insn), validate_equiv_mem_from_store); 587: 588: /* If a register mentioned in MEMREF is modified via an 589: auto-increment, we lose the equivalence. Do the same if one 590: dies; although we could extend the life, it doesn't seem worth 591: the trouble. */ 592: 593: for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 594: if ((REG_NOTE_KIND (note) == REG_INC 595: || REG_NOTE_KIND (note) == REG_DEAD) 596: && GET_CODE (XEXP (note, 0)) == REG 597: && reg_overlap_mentioned_p (XEXP (note, 0), memref)) 598: return 0; 599: } 600: 601: return 0; 602: } 603: 604: /* TRUE if X references a memory location that would be affected by a store 605: to MEMREF. */ 606: 607: static int 608: memref_referenced_p (memref, x) 609: rtx x; 610: rtx memref; 611: { 612: int i, j; 613: char *fmt; 614: enum rtx_code code = GET_CODE (x); 615: 616: switch (code) 617: { 618: case REG: 619: case CONST_INT: 620: case CONST: 621: case LABEL_REF: 622: case SYMBOL_REF: 623: case CONST_DOUBLE: 624: case PC: 625: case CC0: 626: case HIGH: 627: case LO_SUM: 628: return 0; 629: 630: case MEM: 631: if (true_dependence (memref, x)) 632: return 1; 633: break; 634: 635: case SET: 636: /* If we are setting a MEM, it doesn't count (its address does), but any 637: other SET_DEST that has a MEM in it is referencing the MEM. */ 638: if (GET_CODE (SET_DEST (x)) == MEM) 639: { 640: if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) 641: return 1; 642: } 643: else if (memref_referenced_p (memref, SET_DEST (x))) 644: return 1; 645: 646: return memref_referenced_p (memref, SET_SRC (x)); 647: } 648: 649: fmt = GET_RTX_FORMAT (code); 650: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 651: switch (fmt[i]) 652: { 653: case 'e': 654: if (memref_referenced_p (memref, XEXP (x, i))) 655: return 1; 656: break; 657: case 'E': 658: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 659: if (memref_referenced_p (memref, XVECEXP (x, i, j))) 660: return 1; 661: break; 662: } 663: 664: return 0; 665: } 666: 667: /* TRUE if some insn in the range (START, END] references a memory location 668: that would be affected by a store to MEMREF. */ 669: 670: static int 671: memref_used_between_p (memref, start, end) 672: rtx memref; 673: rtx start; 674: rtx end; 675: { 676: rtx insn; 677: 678: for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); 679: insn = NEXT_INSN (insn)) 680: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 681: && memref_referenced_p (memref, PATTERN (insn))) 682: return 1; 683: 684: return 0; 685: } 686: 687: /* INSN is a copy from SRC to DEST, both registers, and SRC does not die 688: in INSN. 689: 690: Search forward to see if SRC dies before either it or DEST is modified, 691: but don't scan past the end of a basic block. If so, we can replace SRC 692: with DEST and let SRC die in INSN. 693: 694: This will reduce the number of registers live in that range and may enable 695: DEST to be tied to SRC, thus often saving one register in addition to a 696: register-register copy. */ 697: 698: static void 1.1.1.2 root 699: optimize_reg_copy_1 (insn, dest, src) 1.1 root 700: rtx insn; 701: rtx dest; 702: rtx src; 703: { 704: rtx p, q; 705: rtx note; 706: rtx dest_death = 0; 707: int sregno = REGNO (src); 708: int dregno = REGNO (dest); 709: 710: if (sregno == dregno 711: #ifdef SMALL_REGISTER_CLASSES 712: /* We don't want to mess with hard regs if register classes are small. */ 713: || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER 714: #endif 715: /* We don't see all updates to SP if they are in an auto-inc memory 716: reference, so we must disallow this optimization on them. */ 717: || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) 718: return; 719: 720: for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 721: { 722: if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 723: || (GET_CODE (p) == NOTE 724: && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 725: || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 726: break; 727: 728: if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 729: continue; 730: 731: if (reg_set_p (src, p) || reg_set_p (dest, p) 732: /* Don't change a USE of a register. */ 733: || (GET_CODE (PATTERN (p)) == USE 734: && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) 735: break; 736: 1.1.1.4 root 737: /* See if all of SRC dies in P. This test is slightly more 738: conservative than it needs to be. */ 739: if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 740: && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) 1.1 root 741: { 742: int failed = 0; 743: int length = 0; 1.1.1.4 root 744: int d_length = 0; 1.1 root 745: int n_calls = 0; 1.1.1.4 root 746: int d_n_calls = 0; 747: 1.1 root 748: /* We can do the optimization. Scan forward from INSN again, 749: replacing regs as we go. Set FAILED if a replacement can't 750: be done. In that case, we can't move the death note for SRC. 751: This should be rare. */ 752: 753: /* Set to stop at next insn. */ 754: for (q = next_real_insn (insn); 755: q != next_real_insn (p); 756: q = next_real_insn (q)) 757: { 1.1.1.4 root 758: if (reg_overlap_mentioned_p (src, PATTERN (q))) 1.1 root 759: { 1.1.1.4 root 760: /* If SRC is a hard register, we might miss some 761: overlapping registers with validate_replace_rtx, 762: so we would have to undo it. We can't if DEST is 763: present in the insn, so fail in that combination 764: of cases. */ 765: if (sregno < FIRST_PSEUDO_REGISTER 766: && reg_mentioned_p (dest, PATTERN (q))) 767: failed = 1; 768: 769: /* Replace all uses and make sure that the register 770: isn't still present. */ 771: else if (validate_replace_rtx (src, dest, q) 772: && (sregno >= FIRST_PSEUDO_REGISTER 773: || ! reg_overlap_mentioned_p (src, 774: PATTERN (q)))) 1.1 root 775: { 776: /* We assume that a register is used exactly once per 777: insn in the updates below. If this is not correct, 778: no great harm is done. */ 779: if (sregno >= FIRST_PSEUDO_REGISTER) 780: reg_n_refs[sregno] -= loop_depth; 781: if (dregno >= FIRST_PSEUDO_REGISTER) 782: reg_n_refs[dregno] += loop_depth; 783: } 784: else 1.1.1.4 root 785: { 786: validate_replace_rtx (dest, src, q); 787: failed = 1; 788: } 1.1 root 789: } 790: 791: /* Count the insns and CALL_INSNs passed. If we passed the 792: death note of DEST, show increased live length. */ 793: length++; 794: if (dest_death) 1.1.1.4 root 795: d_length++; 1.1 root 796: 1.1.1.7 ! root 797: /* If the insn in which SRC dies is a CALL_INSN, don't count it ! 798: as a call that has been crossed. Otherwise, count it. */ ! 799: if (q != p && GET_CODE (q) == CALL_INSN) 1.1 root 800: { 801: n_calls++; 802: if (dest_death) 1.1.1.4 root 803: d_n_calls++; 1.1 root 804: } 805: 806: /* If DEST dies here, remove the death note and save it for 1.1.1.4 root 807: later. Make sure ALL of DEST dies here; again, this is 808: overly conservative. */ 1.1 root 809: if (dest_death == 0 1.1.1.4 root 810: && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0 811: && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) 1.1 root 812: remove_note (q, dest_death); 813: } 814: 815: if (! failed) 816: { 817: if (sregno >= FIRST_PSEUDO_REGISTER) 818: { 819: reg_live_length[sregno] -= length; 1.1.1.7 ! root 820: /* reg_live_length is only an approximation after combine ! 821: if sched is not run, so make sure that we still have ! 822: a reasonable value. */ ! 823: if (reg_live_length[sregno] < 2) ! 824: reg_live_length[sregno] = 2; 1.1 root 825: reg_n_calls_crossed[sregno] -= n_calls; 826: } 827: 1.1.1.4 root 828: if (dregno >= FIRST_PSEUDO_REGISTER) 829: { 830: reg_live_length[dregno] += d_length; 831: reg_n_calls_crossed[dregno] += d_n_calls; 832: } 833: 1.1 root 834: /* Move death note of SRC from P to INSN. */ 835: remove_note (p, note); 836: XEXP (note, 1) = REG_NOTES (insn); 837: REG_NOTES (insn) = note; 838: } 839: 840: /* Put death note of DEST on P if we saw it die. */ 841: if (dest_death) 842: { 843: XEXP (dest_death, 1) = REG_NOTES (p); 844: REG_NOTES (p) = dest_death; 845: } 846: 847: return; 848: } 1.1.1.4 root 849: 850: /* If SRC is a hard register which is set or killed in some other 851: way, we can't do this optimization. */ 852: else if (sregno < FIRST_PSEUDO_REGISTER 853: && dead_or_set_p (p, src)) 854: break; 1.1 root 855: } 856: } 1.1.1.2 root 857: 858: /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have 859: a sequence of insns that modify DEST followed by an insn that sets 860: SRC to DEST in which DEST dies, with no prior modification of DEST. 861: (There is no need to check if the insns in between actually modify 862: DEST. We should not have cases where DEST is not modified, but 863: the optimization is safe if no such modification is detected.) 864: In that case, we can replace all uses of DEST, starting with INSN and 865: ending with the set of SRC to DEST, with SRC. We do not do this 866: optimization if a CALL_INSN is crossed unless SRC already crosses a 867: call. 868: 869: It is assumed that DEST and SRC are pseudos; it is too complicated to do 870: this for hard registers since the substitutions we may make might fail. */ 871: 872: static void 873: optimize_reg_copy_2 (insn, dest, src) 874: rtx insn; 875: rtx dest; 876: rtx src; 877: { 878: rtx p, q; 879: rtx set; 880: int sregno = REGNO (src); 881: int dregno = REGNO (dest); 882: 883: for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 884: { 885: if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 886: || (GET_CODE (p) == NOTE 887: && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 888: || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 889: break; 890: 891: if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 892: continue; 893: 894: set = single_set (p); 895: if (set && SET_SRC (set) == dest && SET_DEST (set) == src 896: && find_reg_note (p, REG_DEAD, dest)) 897: { 898: /* We can do the optimization. Scan forward from INSN again, 899: replacing regs as we go. */ 900: 901: /* Set to stop at next insn. */ 902: for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) 903: if (GET_RTX_CLASS (GET_CODE (q)) == 'i') 904: { 905: if (reg_mentioned_p (dest, PATTERN (q))) 906: { 907: PATTERN (q) = replace_rtx (PATTERN (q), dest, src); 908: 909: /* We assume that a register is used exactly once per 910: insn in the updates below. If this is not correct, 911: no great harm is done. */ 1.1.1.4 root 912: reg_n_refs[dregno] -= loop_depth; 913: reg_n_refs[sregno] += loop_depth; 1.1.1.2 root 914: } 915: 916: 917: if (GET_CODE (q) == CALL_INSN) 918: { 919: reg_n_calls_crossed[dregno]--; 920: reg_n_calls_crossed[sregno]++; 921: } 922: } 923: 924: remove_note (p, find_reg_note (p, REG_DEAD, dest)); 925: reg_n_deaths[dregno]--; 926: remove_note (insn, find_reg_note (insn, REG_DEAD, src)); 927: reg_n_deaths[sregno]--; 928: return; 929: } 930: 931: if (reg_set_p (src, p) 932: || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0)) 933: break; 934: } 935: } 1.1 root 936: 937: /* Find registers that are equivalent to a single value throughout the 938: compilation (either because they can be referenced in memory or are set once 939: from a single constant). Lower their priority for a register. 940: 941: If such a register is only referenced once, try substituting its value 942: into the using insn. If it succeeds, we can eliminate the register 943: completely. */ 944: 945: static void 946: update_equiv_regs () 947: { 948: rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *)); 949: rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *)); 950: rtx insn; 951: 1.1.1.7 ! root 952: bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *)); ! 953: bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *)); 1.1 root 954: 955: init_alias_analysis (); 956: 957: loop_depth = 1; 958: 959: /* Scan the insns and find which registers have equivalences. Do this 960: in a separate scan of the insns because (due to -fcse-follow-jumps) 961: a register can be set below its use. */ 962: for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 963: { 964: rtx note; 965: rtx set = single_set (insn); 966: rtx dest; 967: int regno; 968: 969: if (GET_CODE (insn) == NOTE) 970: { 971: if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 972: loop_depth++; 973: else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 974: loop_depth--; 975: } 976: 977: /* If this insn contains more (or less) than a single SET, ignore it. */ 978: if (set == 0) 979: continue; 980: 981: dest = SET_DEST (set); 982: 983: /* If this sets a MEM to the contents of a REG that is only used 984: in a single basic block, see if the register is always equivalent 985: to that memory location and if moving the store from INSN to the 986: insn that set REG is safe. If so, put a REG_EQUIV note on the 987: initializing insn. */ 988: 989: if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG 990: && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER 991: && reg_basic_block[regno] >= 0 992: && reg_equiv_init_insn[regno] != 0 993: && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set), 994: dest) 995: && ! memref_used_between_p (SET_DEST (set), 996: reg_equiv_init_insn[regno], insn)) 997: REG_NOTES (reg_equiv_init_insn[regno]) 998: = gen_rtx (EXPR_LIST, REG_EQUIV, dest, 999: REG_NOTES (reg_equiv_init_insn[regno])); 1000: 1001: /* If this is a register-register copy where SRC is not dead, see if we 1002: can optimize it. */ 1003: if (flag_expensive_optimizations && GET_CODE (dest) == REG 1004: && GET_CODE (SET_SRC (set)) == REG 1005: && ! find_reg_note (insn, REG_DEAD, SET_SRC (set))) 1.1.1.2 root 1006: optimize_reg_copy_1 (insn, dest, SET_SRC (set)); 1007: 1008: /* Similarly for a pseudo-pseudo copy when SRC is dead. */ 1009: else if (flag_expensive_optimizations && GET_CODE (dest) == REG 1010: && REGNO (dest) >= FIRST_PSEUDO_REGISTER 1011: && GET_CODE (SET_SRC (set)) == REG 1012: && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER 1013: && find_reg_note (insn, REG_DEAD, SET_SRC (set))) 1014: optimize_reg_copy_2 (insn, dest, SET_SRC (set)); 1.1 root 1015: 1016: /* Otherwise, we only handle the case of a pseudo register being set 1017: once. */ 1018: if (GET_CODE (dest) != REG 1019: || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER 1020: || reg_n_sets[regno] != 1) 1021: continue; 1022: 1.1.1.4 root 1023: note = find_reg_note (insn, REG_EQUAL, NULL_RTX); 1.1 root 1024: 1025: /* Record this insn as initializing this register. */ 1026: reg_equiv_init_insn[regno] = insn; 1027: 1028: /* If this register is known to be equal to a constant, record that 1029: it is always equivalent to the constant. */ 1030: if (note && CONSTANT_P (XEXP (note, 0))) 1031: PUT_MODE (note, (enum machine_mode) REG_EQUIV); 1032: 1033: /* If this insn introduces a "constant" register, decrease the priority 1034: of that register. Record this insn if the register is only used once 1035: more and the equivalence value is the same as our source. 1036: 1037: The latter condition is checked for two reasons: First, it is an 1038: indication that it may be more efficient to actually emit the insn 1039: as written (if no registers are available, reload will substitute 1040: the equivalence). Secondly, it avoids problems with any registers 1041: dying in this insn whose death notes would be missed. 1042: 1043: If we don't have a REG_EQUIV note, see if this insn is loading 1044: a register used only in one basic block from a MEM. If so, and the 1045: MEM remains unchanged for the life of the register, add a REG_EQUIV 1046: note. */ 1047: 1.1.1.4 root 1048: note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 1.1 root 1049: 1050: if (note == 0 && reg_basic_block[regno] >= 0 1051: && GET_CODE (SET_SRC (set)) == MEM 1052: && validate_equiv_mem (insn, dest, SET_SRC (set))) 1053: REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set), 1054: REG_NOTES (insn)); 1055: 1056: /* Don't mess with things live during setjmp. */ 1057: if (note && reg_live_length[regno] >= 0) 1058: { 1059: int regno = REGNO (dest); 1060: 1061: /* Note that the statement below does not affect the priority 1062: in local-alloc! */ 1063: reg_live_length[regno] *= 2; 1064: 1065: /* If the register is referenced exactly twice, meaning it is set 1066: once and used once, indicate that the reference may be replaced 1067: by the equivalence we computed above. If the register is only 1068: used in one basic block, this can't succeed or combine would 1069: have done it. 1070: 1071: It would be nice to use "loop_depth * 2" in the compare 1072: below. Unfortunately, LOOP_DEPTH need not be constant within 1073: a basic block so this would be too complicated. 1074: 1075: This case normally occurs when a parameter is read from memory 1076: and then used exactly once, not in a loop. */ 1077: 1078: if (reg_n_refs[regno] == 2 1079: && reg_basic_block[regno] < 0 1080: && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) 1081: reg_equiv_replacement[regno] = SET_SRC (set); 1082: } 1083: } 1084: 1085: /* Now scan all regs killed in an insn to see if any of them are registers 1086: only used that once. If so, see if we can replace the reference with 1087: the equivalent from. If we can, delete the initializing reference 1088: and this register will go away. */ 1089: for (insn = next_active_insn (get_insns ()); 1090: insn; 1091: insn = next_active_insn (insn)) 1092: { 1093: rtx link; 1094: 1095: for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1096: if (REG_NOTE_KIND (link) == REG_DEAD 1097: /* Make sure this insn still refers to the register. */ 1098: && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) 1099: { 1100: int regno = REGNO (XEXP (link, 0)); 1101: 1102: if (reg_equiv_replacement[regno] 1103: && validate_replace_rtx (regno_reg_rtx[regno], 1104: reg_equiv_replacement[regno], insn)) 1105: { 1106: rtx equiv_insn = reg_equiv_init_insn[regno]; 1107: 1108: remove_death (regno, insn); 1109: reg_n_refs[regno] = 0; 1110: PUT_CODE (equiv_insn, NOTE); 1111: NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 1112: NOTE_SOURCE_FILE (equiv_insn) = 0; 1113: } 1114: } 1115: } 1116: } 1117: 1118: /* Allocate hard regs to the pseudo regs used only within block number B. 1119: Only the pseudos that die but once can be handled. */ 1120: 1121: static void 1122: block_alloc (b) 1123: int b; 1124: { 1125: register int i, q; 1126: register rtx insn; 1127: rtx note; 1128: int insn_number = 0; 1129: int insn_count = 0; 1130: int max_uid = get_max_uid (); 1.1.1.5 root 1131: int *qty_order; 1.1 root 1132: int no_conflict_combined_regno = -1; 1.1.1.6 root 1133: /* Counter to prevent allocating more SCRATCHes than can be stored 1134: in SCRATCH_LIST. */ 1135: int scratches_allocated = scratch_index; 1.1 root 1136: 1137: /* Count the instructions in the basic block. */ 1138: 1139: insn = basic_block_end[b]; 1140: while (1) 1141: { 1142: if (GET_CODE (insn) != NOTE) 1143: if (++insn_count > max_uid) 1144: abort (); 1145: if (insn == basic_block_head[b]) 1146: break; 1147: insn = PREV_INSN (insn); 1148: } 1149: 1150: /* +2 to leave room for a post_mark_life at the last insn and for 1151: the birth of a CLOBBER in the first insn. */ 1152: regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2) 1153: * sizeof (HARD_REG_SET)); 1.1.1.7 ! root 1154: bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET)); 1.1 root 1155: 1156: /* Initialize table of hardware registers currently live. */ 1157: 1158: #ifdef HARD_REG_SET 1159: regs_live = *basic_block_live_at_start[b]; 1160: #else 1161: COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]); 1162: #endif 1163: 1164: /* This loop scans the instructions of the basic block 1165: and assigns quantities to registers. 1166: It computes which registers to tie. */ 1167: 1168: insn = basic_block_head[b]; 1169: while (1) 1170: { 1171: register rtx body = PATTERN (insn); 1172: 1173: if (GET_CODE (insn) != NOTE) 1174: insn_number++; 1175: 1176: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1177: { 1178: register rtx link, set; 1179: register int win = 0; 1180: register rtx r0, r1; 1181: int combined_regno = -1; 1182: int i; 1183: int insn_code_number = recog_memoized (insn); 1184: 1185: this_insn_number = insn_number; 1186: this_insn = insn; 1187: 1188: if (insn_code_number >= 0) 1189: insn_extract (insn); 1190: which_alternative = -1; 1191: 1192: /* Is this insn suitable for tying two registers? 1193: If so, try doing that. 1194: Suitable insns are those with at least two operands and where 1195: operand 0 is an output that is a register that is not 1196: earlyclobber. 1.1.1.5 root 1197: 1198: We can tie operand 0 with some operand that dies in this insn. 1199: First look for operands that are required to be in the same 1200: register as operand 0. If we find such, only try tying that 1201: operand or one that can be put into that operand if the 1202: operation is commutative. If we don't find an operand 1203: that is required to be in the same register as operand 0, 1204: we can tie with any operand. 1205: 1.1 root 1206: Subregs in place of regs are also ok. 1207: 1208: If tying is done, WIN is set nonzero. */ 1209: 1210: if (insn_code_number >= 0 1.1.1.4 root 1211: #ifdef REGISTER_CONSTRAINTS 1.1 root 1212: && insn_n_operands[insn_code_number] > 1 1213: && insn_operand_constraint[insn_code_number][0][0] == '=' 1.1.1.4 root 1214: && insn_operand_constraint[insn_code_number][0][1] != '&' 1215: #else 1216: && GET_CODE (PATTERN (insn)) == SET 1217: && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0]) 1218: #endif 1219: ) 1.1 root 1220: { 1.1.1.4 root 1221: #ifdef REGISTER_CONSTRAINTS 1.1.1.7 ! root 1222: /* If non-negative, is an operand that must match operand 0. */ 1.1.1.5 root 1223: int must_match_0 = -1; 1.1.1.7 ! root 1224: /* Counts number of alternatives that require a match with ! 1225: operand 0. */ ! 1226: int n_matching_alts = 0; 1.1.1.5 root 1227: 1228: for (i = 1; i < insn_n_operands[insn_code_number]; i++) 1.1.1.7 ! root 1229: { ! 1230: char *p = insn_operand_constraint[insn_code_number][i]; ! 1231: int this_match = (requires_inout (p)); ! 1232: ! 1233: n_matching_alts += this_match; ! 1234: if (this_match == insn_n_alternatives[insn_code_number]) ! 1235: must_match_0 = i; ! 1236: } 1.1.1.4 root 1237: #endif 1.1 root 1238: 1.1.1.5 root 1239: r0 = recog_operand[0]; 1240: for (i = 1; i < insn_n_operands[insn_code_number]; i++) 1.1 root 1241: { 1.1.1.4 root 1242: #ifdef REGISTER_CONSTRAINTS 1.1.1.5 root 1243: /* Skip this operand if we found an operand that 1244: must match operand 0 and this operand isn't it 1245: and can't be made to be it by commutativity. */ 1246: 1247: if (must_match_0 >= 0 && i != must_match_0 1248: && ! (i == must_match_0 + 1 1249: && insn_operand_constraint[insn_code_number][i-1][0] == '%') 1250: && ! (i == must_match_0 - 1 1251: && insn_operand_constraint[insn_code_number][i][0] == '%')) 1252: continue; 1.1.1.7 ! root 1253: ! 1254: /* Likewise if each alternative has some operand that ! 1255: must match operand zero. In that case, skip any ! 1256: operand that doesn't list operand 0 since we know that ! 1257: the operand always conflicts with operand 0. We ! 1258: ignore commutatity in this case to keep things simple. */ ! 1259: if (n_matching_alts == insn_n_alternatives[insn_code_number] ! 1260: && (0 == requires_inout ! 1261: (insn_operand_constraint[insn_code_number][i]))) ! 1262: continue; 1.1.1.4 root 1263: #endif 1.1 root 1264: 1.1.1.5 root 1265: r1 = recog_operand[i]; 1.1 root 1266: 1.1.1.5 root 1267: /* If the operand is an address, find a register in it. 1268: There may be more than one register, but we only try one 1269: of them. */ 1270: if ( 1.1.1.4 root 1271: #ifdef REGISTER_CONSTRAINTS 1.1.1.5 root 1272: insn_operand_constraint[insn_code_number][i][0] == 'p' 1.1.1.4 root 1273: #else 1.1.1.5 root 1274: insn_operand_address_p[insn_code_number][i] 1275: #endif 1276: ) 1277: while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) 1278: r1 = XEXP (r1, 0); 1279: 1280: if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) 1281: { 1282: /* We have two priorities for hard register preferences. 1283: If we have a move insn or an insn whose first input 1284: can only be in the same register as the output, give 1285: priority to an equivalence found from that insn. */ 1286: int may_save_copy 1287: = ((SET_DEST (body) == r0 && SET_SRC (body) == r1) 1288: #ifdef REGISTER_CONSTRAINTS 1289: || (r1 == recog_operand[i] && must_match_0 >= 0) 1.1.1.4 root 1290: #endif 1.1.1.5 root 1291: ); 1292: 1293: if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) 1294: win = combine_regs (r1, r0, may_save_copy, 1295: insn_number, insn, 0); 1296: } 1.1 root 1297: } 1298: } 1299: 1300: /* Recognize an insn sequence with an ultimate result 1301: which can safely overlap one of the inputs. 1302: The sequence begins with a CLOBBER of its result, 1303: and ends with an insn that copies the result to itself 1304: and has a REG_EQUAL note for an equivalent formula. 1305: That note indicates what the inputs are. 1306: The result and the input can overlap if each insn in 1307: the sequence either doesn't mention the input 1308: or has a REG_NO_CONFLICT note to inhibit the conflict. 1309: 1310: We do the combining test at the CLOBBER so that the 1311: destination register won't have had a quantity number 1312: assigned, since that would prevent combining. */ 1313: 1314: if (GET_CODE (PATTERN (insn)) == CLOBBER 1315: && (r0 = XEXP (PATTERN (insn), 0), 1316: GET_CODE (r0) == REG) 1.1.1.4 root 1317: && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 1.1.1.5 root 1318: && XEXP (link, 0) != 0 1.1 root 1319: && GET_CODE (XEXP (link, 0)) == INSN 1320: && (set = single_set (XEXP (link, 0))) != 0 1321: && SET_DEST (set) == r0 && SET_SRC (set) == r0 1.1.1.4 root 1322: && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, 1323: NULL_RTX)) != 0) 1.1 root 1324: { 1325: if (r1 = XEXP (note, 0), GET_CODE (r1) == REG 1326: /* Check that we have such a sequence. */ 1327: && no_conflict_p (insn, r0, r1)) 1328: win = combine_regs (r1, r0, 1, insn_number, insn, 1); 1329: else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' 1330: && (r1 = XEXP (XEXP (note, 0), 0), 1331: GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) 1332: && no_conflict_p (insn, r0, r1)) 1333: win = combine_regs (r1, r0, 0, insn_number, insn, 1); 1334: 1335: /* Here we care if the operation to be computed is 1336: commutative. */ 1337: else if ((GET_CODE (XEXP (note, 0)) == EQ 1338: || GET_CODE (XEXP (note, 0)) == NE 1339: || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') 1340: && (r1 = XEXP (XEXP (note, 0), 1), 1341: (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) 1342: && no_conflict_p (insn, r0, r1)) 1343: win = combine_regs (r1, r0, 0, insn_number, insn, 1); 1344: 1345: /* If we did combine something, show the register number 1346: in question so that we know to ignore its death. */ 1347: if (win) 1348: no_conflict_combined_regno = REGNO (r1); 1349: } 1350: 1351: /* If registers were just tied, set COMBINED_REGNO 1352: to the number of the register used in this insn 1353: that was tied to the register set in this insn. 1354: This register's qty should not be "killed". */ 1355: 1356: if (win) 1357: { 1358: while (GET_CODE (r1) == SUBREG) 1359: r1 = SUBREG_REG (r1); 1360: combined_regno = REGNO (r1); 1361: } 1362: 1363: /* Mark the death of everything that dies in this instruction, 1364: except for anything that was just combined. */ 1365: 1366: for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1367: if (REG_NOTE_KIND (link) == REG_DEAD 1368: && GET_CODE (XEXP (link, 0)) == REG 1369: && combined_regno != REGNO (XEXP (link, 0)) 1370: && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) 1371: || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) 1372: wipe_dead_reg (XEXP (link, 0), 0); 1373: 1374: /* Allocate qty numbers for all registers local to this block 1375: that are born (set) in this instruction. 1376: A pseudo that already has a qty is not changed. */ 1377: 1378: note_stores (PATTERN (insn), reg_is_set); 1379: 1380: /* If anything is set in this insn and then unused, mark it as dying 1381: after this insn, so it will conflict with our outputs. This 1382: can't match with something that combined, and it doesn't matter 1383: if it did. Do this after the calls to reg_is_set since these 1384: die after, not during, the current insn. */ 1385: 1386: for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1387: if (REG_NOTE_KIND (link) == REG_UNUSED 1388: && GET_CODE (XEXP (link, 0)) == REG) 1389: wipe_dead_reg (XEXP (link, 0), 1); 1390: 1.1.1.6 root 1391: /* Allocate quantities for any SCRATCH operands of this insn. */ 1.1 root 1392: 1393: if (insn_code_number >= 0) 1394: for (i = 0; i < insn_n_operands[insn_code_number]; i++) 1.1.1.6 root 1395: if (GET_CODE (recog_operand[i]) == SCRATCH 1396: && scratches_allocated++ < scratch_list_length) 1.1 root 1397: alloc_qty_for_scratch (recog_operand[i], i, insn, 1398: insn_code_number, insn_number); 1399: 1400: /* If this is an insn that has a REG_RETVAL note pointing at a 1401: CLOBBER insn, we have reached the end of a REG_NO_CONFLICT 1402: block, so clear any register number that combined within it. */ 1.1.1.4 root 1403: if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 1.1 root 1404: && GET_CODE (XEXP (note, 0)) == INSN 1405: && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) 1406: no_conflict_combined_regno = -1; 1407: } 1408: 1409: /* Set the registers live after INSN_NUMBER. Note that we never 1410: record the registers live before the block's first insn, since no 1411: pseudos we care about are live before that insn. */ 1412: 1413: IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); 1414: IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); 1415: 1416: if (insn == basic_block_end[b]) 1417: break; 1418: 1419: insn = NEXT_INSN (insn); 1420: } 1421: 1422: /* Now every register that is local to this basic block 1423: should have been given a quantity, or else -1 meaning ignore it. 1424: Every quantity should have a known birth and death. 1425: 1.1.1.7 ! root 1426: Order the qtys so we assign them registers in order of the ! 1427: number of suggested registers they need so we allocate those with ! 1428: the most restrictive needs first. */ 1.1 root 1429: 1.1.1.5 root 1430: qty_order = (int *) alloca (next_qty * sizeof (int)); 1.1 root 1431: for (i = 0; i < next_qty; i++) 1432: qty_order[i] = i; 1433: 1434: #define EXCHANGE(I1, I2) \ 1435: { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } 1436: 1437: switch (next_qty) 1438: { 1439: case 3: 1440: /* Make qty_order[2] be the one to allocate last. */ 1.1.1.7 ! root 1441: if (qty_sugg_compare (0, 1) > 0) 1.1 root 1442: EXCHANGE (0, 1); 1.1.1.7 ! root 1443: if (qty_sugg_compare (1, 2) > 0) 1.1 root 1444: EXCHANGE (2, 1); 1445: 1446: /* ... Fall through ... */ 1447: case 2: 1448: /* Put the best one to allocate in qty_order[0]. */ 1.1.1.7 ! root 1449: if (qty_sugg_compare (0, 1) > 0) 1.1 root 1450: EXCHANGE (0, 1); 1451: 1452: /* ... Fall through ... */ 1453: 1454: case 1: 1455: case 0: 1456: /* Nothing to do here. */ 1457: break; 1458: 1459: default: 1.1.1.7 ! root 1460: qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); 1.1 root 1461: } 1462: 1463: /* Try to put each quantity in a suggested physical register, if it has one. 1464: This may cause registers to be allocated that otherwise wouldn't be, but 1465: this seems acceptable in local allocation (unlike global allocation). */ 1466: for (i = 0; i < next_qty; i++) 1467: { 1468: q = qty_order[i]; 1.1.1.7 ! root 1469: if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) 1.1 root 1470: qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q, 1471: 0, 1, qty_birth[q], qty_death[q]); 1472: else 1473: qty_phys_reg[q] = -1; 1474: } 1475: 1.1.1.7 ! root 1476: /* Order the qtys so we assign them registers in order of ! 1477: decreasing length of life. Normally call qsort, but if we ! 1478: have only a very small number of quantities, sort them ourselves. */ ! 1479: ! 1480: for (i = 0; i < next_qty; i++) ! 1481: qty_order[i] = i; ! 1482: ! 1483: #define EXCHANGE(I1, I2) \ ! 1484: { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } ! 1485: ! 1486: switch (next_qty) ! 1487: { ! 1488: case 3: ! 1489: /* Make qty_order[2] be the one to allocate last. */ ! 1490: if (qty_compare (0, 1) > 0) ! 1491: EXCHANGE (0, 1); ! 1492: if (qty_compare (1, 2) > 0) ! 1493: EXCHANGE (2, 1); ! 1494: ! 1495: /* ... Fall through ... */ ! 1496: case 2: ! 1497: /* Put the best one to allocate in qty_order[0]. */ ! 1498: if (qty_compare (0, 1) > 0) ! 1499: EXCHANGE (0, 1); ! 1500: ! 1501: /* ... Fall through ... */ ! 1502: ! 1503: case 1: ! 1504: case 0: ! 1505: /* Nothing to do here. */ ! 1506: break; ! 1507: ! 1508: default: ! 1509: qsort (qty_order, next_qty, sizeof (int), qty_compare_1); ! 1510: } ! 1511: 1.1 root 1512: /* Now for each qty that is not a hardware register, 1513: look for a hardware register to put it in. 1514: First try the register class that is cheapest for this qty, 1515: if there is more than one class. */ 1516: 1517: for (i = 0; i < next_qty; i++) 1518: { 1519: q = qty_order[i]; 1520: if (qty_phys_reg[q] < 0) 1521: { 1522: if (N_REG_CLASSES > 1) 1523: { 1524: qty_phys_reg[q] = find_free_reg (qty_min_class[q], 1525: qty_mode[q], q, 0, 0, 1526: qty_birth[q], qty_death[q]); 1527: if (qty_phys_reg[q] >= 0) 1528: continue; 1529: } 1530: 1.1.1.4 root 1531: if (qty_alternate_class[q] != NO_REGS) 1532: qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], 1.1 root 1533: qty_mode[q], q, 0, 0, 1534: qty_birth[q], qty_death[q]); 1535: } 1536: } 1537: 1538: /* Now propagate the register assignments 1539: to the pseudo regs belonging to the qtys. */ 1540: 1541: for (q = 0; q < next_qty; q++) 1542: if (qty_phys_reg[q] >= 0) 1543: { 1544: for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i]) 1545: reg_renumber[i] = qty_phys_reg[q] + reg_offset[i]; 1546: if (qty_scratch_rtx[q]) 1547: { 1.1.1.6 root 1548: if (GET_CODE (qty_scratch_rtx[q]) == REG) 1549: abort (); 1.1 root 1550: PUT_CODE (qty_scratch_rtx[q], REG); 1551: REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q]; 1552: 1.1.1.6 root 1553: scratch_block[scratch_index] = b; 1554: scratch_list[scratch_index++] = qty_scratch_rtx[q]; 1.1 root 1555: 1556: /* Must clear the USED field, because it will have been set by 1557: copy_rtx_if_shared, but the leaf_register code expects that 1558: it is zero in all REG rtx. copy_rtx_if_shared does not set the 1559: used bit for REGs, but does for SCRATCHes. */ 1560: qty_scratch_rtx[q]->used = 0; 1561: } 1562: } 1563: } 1564: 1565: /* Compare two quantities' priority for getting real registers. 1566: We give shorter-lived quantities higher priority. 1.1.1.3 root 1567: Quantities with more references are also preferred, as are quantities that 1568: require multiple registers. This is the identical prioritization as 1.1 root 1569: done by global-alloc. 1570: 1571: We used to give preference to registers with *longer* lives, but using 1572: the same algorithm in both local- and global-alloc can speed up execution 1573: of some programs by as much as a factor of three! */ 1574: 1575: static int 1576: qty_compare (q1, q2) 1577: int q1, q2; 1578: { 1579: /* Note that the quotient will never be bigger than 1580: the value of floor_log2 times the maximum number of 1581: times a register can occur in one insn (surely less than 100). 1582: Multiplying this by 10000 can't overflow. */ 1583: register int pri1 1.1.1.7 ! root 1584: = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1]) ! 1585: / (qty_death[q1] - qty_birth[q1])) 1.1 root 1586: * 10000); 1587: register int pri2 1.1.1.7 ! root 1588: = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2]) ! 1589: / (qty_death[q2] - qty_birth[q2])) 1.1 root 1590: * 10000); 1591: return pri2 - pri1; 1592: } 1593: 1594: static int 1595: qty_compare_1 (q1, q2) 1.1.1.5 root 1596: int *q1, *q2; 1.1 root 1597: { 1598: register int tem; 1599: 1600: /* Note that the quotient will never be bigger than 1601: the value of floor_log2 times the maximum number of 1602: times a register can occur in one insn (surely less than 100). 1603: Multiplying this by 10000 can't overflow. */ 1604: register int pri1 1.1.1.7 ! root 1605: = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1] ! 1606: * qty_size[*q1]) ! 1607: / (qty_death[*q1] - qty_birth[*q1])) 1.1 root 1608: * 10000); 1609: register int pri2 1.1.1.7 ! root 1610: = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2] ! 1611: * qty_size[*q2]) ! 1612: / (qty_death[*q2] - qty_birth[*q2])) 1.1 root 1613: * 10000); 1614: 1615: tem = pri2 - pri1; 1616: if (tem != 0) return tem; 1617: /* If qtys are equally good, sort by qty number, 1618: so that the results of qsort leave nothing to chance. */ 1619: return *q1 - *q2; 1620: } 1621: 1.1.1.7 ! root 1622: /* Compare two quantities' priority for getting real registers. This version ! 1623: is called for quantities that have suggested hard registers. First priority ! 1624: goes to quantities that have copy preferences, then to those that have ! 1625: normal preferences. Within those groups, quantities with the lower ! 1626: number of preferenes have the highest priority. Of those, we use the same ! 1627: algorithm as above. */ ! 1628: ! 1629: static int ! 1630: qty_sugg_compare (q1, q2) ! 1631: int q1, q2; ! 1632: { ! 1633: register int sugg1 = (qty_phys_num_copy_sugg[q1] ! 1634: ? qty_phys_num_copy_sugg[q1] ! 1635: : qty_phys_num_sugg[q1] * FIRST_PSEUDO_REGISTER); ! 1636: register int sugg2 = (qty_phys_num_copy_sugg[q2] ! 1637: ? qty_phys_num_copy_sugg[q2] ! 1638: : qty_phys_num_sugg[q2] * FIRST_PSEUDO_REGISTER); ! 1639: /* Note that the quotient will never be bigger than ! 1640: the value of floor_log2 times the maximum number of ! 1641: times a register can occur in one insn (surely less than 100). ! 1642: Multiplying this by 10000 can't overflow. */ ! 1643: register int pri1 ! 1644: = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1]) ! 1645: / (qty_death[q1] - qty_birth[q1])) ! 1646: * 10000); ! 1647: register int pri2 ! 1648: = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2]) ! 1649: / (qty_death[q2] - qty_birth[q2])) ! 1650: * 10000); ! 1651: ! 1652: if (sugg1 != sugg2) ! 1653: return sugg1 - sugg2; ! 1654: ! 1655: return pri2 - pri1; ! 1656: } ! 1657: ! 1658: static int ! 1659: qty_sugg_compare_1 (q1, q2) ! 1660: int *q1, *q2; ! 1661: { ! 1662: register int sugg1 = (qty_phys_num_copy_sugg[*q1] ! 1663: ? qty_phys_num_copy_sugg[*q1] ! 1664: : qty_phys_num_sugg[*q1] * FIRST_PSEUDO_REGISTER); ! 1665: register int sugg2 = (qty_phys_num_copy_sugg[*q2] ! 1666: ? qty_phys_num_copy_sugg[*q2] ! 1667: : qty_phys_num_sugg[*q2] * FIRST_PSEUDO_REGISTER); ! 1668: ! 1669: /* Note that the quotient will never be bigger than ! 1670: the value of floor_log2 times the maximum number of ! 1671: times a register can occur in one insn (surely less than 100). ! 1672: Multiplying this by 10000 can't overflow. */ ! 1673: register int pri1 ! 1674: = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1] ! 1675: * qty_size[*q1]) ! 1676: / (qty_death[*q1] - qty_birth[*q1])) ! 1677: * 10000); ! 1678: register int pri2 ! 1679: = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2] ! 1680: * qty_size[*q2]) ! 1681: / (qty_death[*q2] - qty_birth[*q2])) ! 1682: * 10000); ! 1683: ! 1684: if (sugg1 != sugg2) ! 1685: return sugg1 - sugg2; ! 1686: ! 1687: if (pri1 != pri2) ! 1688: return pri2 - pri1; ! 1689: ! 1690: /* If qtys are equally good, sort by qty number, ! 1691: so that the results of qsort leave nothing to chance. */ ! 1692: return *q1 - *q2; ! 1693: } ! 1694: 1.1 root 1695: /* Attempt to combine the two registers (rtx's) USEDREG and SETREG. 1696: Returns 1 if have done so, or 0 if cannot. 1697: 1698: Combining registers means marking them as having the same quantity 1699: and adjusting the offsets within the quantity if either of 1700: them is a SUBREG). 1701: 1702: We don't actually combine a hard reg with a pseudo; instead 1703: we just record the hard reg as the suggestion for the pseudo's quantity. 1704: If we really combined them, we could lose if the pseudo lives 1705: across an insn that clobbers the hard reg (eg, movstr). 1706: 1707: ALREADY_DEAD is non-zero if USEDREG is known to be dead even though 1708: there is no REG_DEAD note on INSN. This occurs during the processing 1709: of REG_NO_CONFLICT blocks. 1710: 1711: MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to 1712: SETREG or if the input and output must share a register. 1713: In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. 1714: 1715: There are elaborate checks for the validity of combining. */ 1716: 1717: 1718: static int 1719: combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) 1720: rtx usedreg, setreg; 1721: int may_save_copy; 1722: int insn_number; 1723: rtx insn; 1724: int already_dead; 1725: { 1726: register int ureg, sreg; 1727: register int offset = 0; 1728: int usize, ssize; 1729: register int sqty; 1730: 1731: /* Determine the numbers and sizes of registers being used. If a subreg 1.1.1.3 root 1732: is present that does not change the entire register, don't consider 1.1 root 1733: this a copy insn. */ 1734: 1735: while (GET_CODE (usedreg) == SUBREG) 1736: { 1737: if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) 1738: may_save_copy = 0; 1739: offset += SUBREG_WORD (usedreg); 1740: usedreg = SUBREG_REG (usedreg); 1741: } 1742: if (GET_CODE (usedreg) != REG) 1743: return 0; 1744: ureg = REGNO (usedreg); 1745: usize = REG_SIZE (usedreg); 1746: 1747: while (GET_CODE (setreg) == SUBREG) 1748: { 1749: if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) 1750: may_save_copy = 0; 1751: offset -= SUBREG_WORD (setreg); 1752: setreg = SUBREG_REG (setreg); 1753: } 1754: if (GET_CODE (setreg) != REG) 1755: return 0; 1756: sreg = REGNO (setreg); 1757: ssize = REG_SIZE (setreg); 1758: 1759: /* If UREG is a pseudo-register that hasn't already been assigned a 1760: quantity number, it means that it is not local to this block or dies 1761: more than once. In either event, we can't do anything with it. */ 1762: if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) 1763: /* Do not combine registers unless one fits within the other. */ 1764: || (offset > 0 && usize + offset > ssize) 1765: || (offset < 0 && usize + offset < ssize) 1766: /* Do not combine with a smaller already-assigned object 1767: if that smaller object is already combined with something bigger. */ 1768: || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER 1769: && usize < qty_size[reg_qty[ureg]]) 1770: /* Can't combine if SREG is not a register we can allocate. */ 1771: || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) 1772: /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. 1773: These have already been taken care of. This probably wouldn't 1774: combine anyway, but don't take any chances. */ 1775: || (ureg >= FIRST_PSEUDO_REGISTER 1776: && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) 1777: /* Don't tie something to itself. In most cases it would make no 1778: difference, but it would screw up if the reg being tied to itself 1779: also dies in this insn. */ 1780: || ureg == sreg 1781: /* Don't try to connect two different hardware registers. */ 1782: || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) 1783: /* Don't connect two different machine modes if they have different 1784: implications as to which registers may be used. */ 1785: || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) 1786: return 0; 1787: 1788: /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in 1789: qty_phys_sugg for the pseudo instead of tying them. 1790: 1791: Return "failure" so that the lifespan of UREG is terminated here; 1792: that way the two lifespans will be disjoint and nothing will prevent 1793: the pseudo reg from being given this hard reg. */ 1794: 1795: if (ureg < FIRST_PSEUDO_REGISTER) 1796: { 1797: /* Allocate a quantity number so we have a place to put our 1798: suggestions. */ 1799: if (reg_qty[sreg] == -2) 1800: reg_is_born (setreg, 2 * insn_number); 1801: 1802: if (reg_qty[sreg] >= 0) 1803: { 1.1.1.7 ! root 1804: if (may_save_copy ! 1805: && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) 1.1 root 1806: { 1807: SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); 1.1.1.7 ! root 1808: qty_phys_num_copy_sugg[reg_qty[sreg]]++; 1.1 root 1809: } 1.1.1.7 ! root 1810: else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) 1.1 root 1811: { 1812: SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); 1.1.1.7 ! root 1813: qty_phys_num_sugg[reg_qty[sreg]]++; 1.1 root 1814: } 1815: } 1816: return 0; 1817: } 1818: 1819: /* Similarly for SREG a hard register and UREG a pseudo register. */ 1820: 1821: if (sreg < FIRST_PSEUDO_REGISTER) 1822: { 1.1.1.7 ! root 1823: if (may_save_copy ! 1824: && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) 1.1 root 1825: { 1826: SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); 1.1.1.7 ! root 1827: qty_phys_num_copy_sugg[reg_qty[ureg]]++; 1.1 root 1828: } 1.1.1.7 ! root 1829: else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) 1.1 root 1830: { 1831: SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); 1.1.1.7 ! root 1832: qty_phys_num_sugg[reg_qty[ureg]]++; 1.1 root 1833: } 1834: return 0; 1835: } 1836: 1837: /* At this point we know that SREG and UREG are both pseudos. 1838: Do nothing if SREG already has a quantity or is a register that we 1839: don't allocate. */ 1840: if (reg_qty[sreg] >= -1 1841: /* If we are not going to let any regs live across calls, 1842: don't tie a call-crossing reg to a non-call-crossing reg. */ 1843: || (current_function_has_nonlocal_label 1844: && ((reg_n_calls_crossed[ureg] > 0) 1845: != (reg_n_calls_crossed[sreg] > 0)))) 1846: return 0; 1847: 1848: /* We don't already know about SREG, so tie it to UREG 1849: if this is the last use of UREG, provided the classes they want 1850: are compatible. */ 1851: 1852: if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) 1853: && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])) 1854: { 1855: /* Add SREG to UREG's quantity. */ 1856: sqty = reg_qty[ureg]; 1857: reg_qty[sreg] = sqty; 1858: reg_offset[sreg] = reg_offset[ureg] + offset; 1859: reg_next_in_qty[sreg] = qty_first_reg[sqty]; 1860: qty_first_reg[sqty] = sreg; 1861: 1862: /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */ 1863: update_qty_class (sqty, sreg); 1864: 1865: /* Update info about quantity SQTY. */ 1866: qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg]; 1867: qty_n_refs[sqty] += reg_n_refs[sreg]; 1868: if (usize < ssize) 1869: { 1870: register int i; 1871: 1872: for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i]) 1873: reg_offset[i] -= offset; 1874: 1875: qty_size[sqty] = ssize; 1876: qty_mode[sqty] = GET_MODE (setreg); 1877: } 1878: } 1879: else 1880: return 0; 1881: 1882: return 1; 1883: } 1884: 1885: /* Return 1 if the preferred class of REG allows it to be tied 1886: to a quantity or register whose class is CLASS. 1887: True if REG's reg class either contains or is contained in CLASS. */ 1888: 1889: static int 1890: reg_meets_class_p (reg, class) 1891: int reg; 1892: enum reg_class class; 1893: { 1894: register enum reg_class rclass = reg_preferred_class (reg); 1895: return (reg_class_subset_p (rclass, class) 1896: || reg_class_subset_p (class, rclass)); 1897: } 1898: 1899: /* Return 1 if the two specified classes have registers in common. 1900: If CALL_SAVED, then consider only call-saved registers. */ 1901: 1902: static int 1903: reg_classes_overlap_p (c1, c2, call_saved) 1904: register enum reg_class c1; 1905: register enum reg_class c2; 1906: int call_saved; 1907: { 1908: HARD_REG_SET c; 1909: int i; 1910: 1911: COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 1912: AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 1913: 1914: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1915: if (TEST_HARD_REG_BIT (c, i) 1916: && (! call_saved || ! call_used_regs[i])) 1917: return 1; 1918: 1919: return 0; 1920: } 1921: 1922: /* Update the class of QTY assuming that REG is being tied to it. */ 1923: 1924: static void 1925: update_qty_class (qty, reg) 1926: int qty; 1927: int reg; 1928: { 1929: enum reg_class rclass = reg_preferred_class (reg); 1930: if (reg_class_subset_p (rclass, qty_min_class[qty])) 1931: qty_min_class[qty] = rclass; 1.1.1.4 root 1932: 1933: rclass = reg_alternate_class (reg); 1934: if (reg_class_subset_p (rclass, qty_alternate_class[qty])) 1935: qty_alternate_class[qty] = rclass; 1.1.1.7 ! root 1936: ! 1937: if (reg_changes_size[reg]) ! 1938: qty_changes_size[qty] = 1; 1.1 root 1939: } 1940: 1941: /* Handle something which alters the value of an rtx REG. 1942: 1943: REG is whatever is set or clobbered. SETTER is the rtx that 1944: is modifying the register. 1945: 1946: If it is not really a register, we do nothing. 1947: The file-global variables `this_insn' and `this_insn_number' 1948: carry info from `block_alloc'. */ 1949: 1950: static void 1951: reg_is_set (reg, setter) 1952: rtx reg; 1953: rtx setter; 1954: { 1955: /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of 1956: a hard register. These may actually not exist any more. */ 1957: 1958: if (GET_CODE (reg) != SUBREG 1959: && GET_CODE (reg) != REG) 1960: return; 1961: 1962: /* Mark this register as being born. If it is used in a CLOBBER, mark 1963: it as being born halfway between the previous insn and this insn so that 1964: it conflicts with our inputs but not the outputs of the previous insn. */ 1965: 1966: reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); 1967: } 1968: 1969: /* Handle beginning of the life of register REG. 1970: BIRTH is the index at which this is happening. */ 1971: 1972: static void 1973: reg_is_born (reg, birth) 1974: rtx reg; 1975: int birth; 1976: { 1977: register int regno; 1978: 1979: if (GET_CODE (reg) == SUBREG) 1980: regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); 1981: else 1982: regno = REGNO (reg); 1983: 1984: if (regno < FIRST_PSEUDO_REGISTER) 1985: { 1986: mark_life (regno, GET_MODE (reg), 1); 1987: 1988: /* If the register was to have been born earlier that the present 1989: insn, mark it as live where it is actually born. */ 1990: if (birth < 2 * this_insn_number) 1991: post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); 1992: } 1993: else 1994: { 1995: if (reg_qty[regno] == -2) 1996: alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); 1997: 1998: /* If this register has a quantity number, show that it isn't dead. */ 1999: if (reg_qty[regno] >= 0) 2000: qty_death[reg_qty[regno]] = -1; 2001: } 2002: } 2003: 2004: /* Record the death of REG in the current insn. If OUTPUT_P is non-zero, 2005: REG is an output that is dying (i.e., it is never used), otherwise it 1.1.1.2 root 2006: is an input (the normal case). 2007: If OUTPUT_P is 1, then we extend the life past the end of this insn. */ 1.1 root 2008: 2009: static void 2010: wipe_dead_reg (reg, output_p) 2011: register rtx reg; 2012: int output_p; 2013: { 2014: register int regno = REGNO (reg); 2015: 1.1.1.2 root 2016: /* If this insn has multiple results, 2017: and the dead reg is used in one of the results, 2018: extend its life to after this insn, 2019: so it won't get allocated together with any other result of this insn. */ 2020: if (GET_CODE (PATTERN (this_insn)) == PARALLEL 2021: && !single_set (this_insn)) 2022: { 2023: int i; 2024: for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) 2025: { 2026: rtx set = XVECEXP (PATTERN (this_insn), 0, i); 2027: if (GET_CODE (set) == SET 2028: && GET_CODE (SET_DEST (set)) != REG 2029: && !rtx_equal_p (reg, SET_DEST (set)) 2030: && reg_overlap_mentioned_p (reg, SET_DEST (set))) 2031: output_p = 1; 2032: } 2033: } 2034: 1.1 root 2035: if (regno < FIRST_PSEUDO_REGISTER) 2036: { 2037: mark_life (regno, GET_MODE (reg), 0); 2038: 2039: /* If a hard register is dying as an output, mark it as in use at 2040: the beginning of this insn (the above statement would cause this 2041: not to happen). */ 2042: if (output_p) 2043: post_mark_life (regno, GET_MODE (reg), 1, 2044: 2 * this_insn_number, 2 * this_insn_number+ 1); 2045: } 2046: 2047: else if (reg_qty[regno] >= 0) 2048: qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p; 2049: } 2050: 2051: /* Find a block of SIZE words of hard regs in reg_class CLASS 2052: that can hold something of machine-mode MODE 2053: (but actually we test only the first of the block for holding MODE) 2054: and still free between insn BORN_INDEX and insn DEAD_INDEX, 2055: and return the number of the first of them. 2056: Return -1 if such a block cannot be found. 2057: If QTY crosses calls, insist on a register preserved by calls, 2058: unless ACCEPT_CALL_CLOBBERED is nonzero. 2059: 2060: If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested 2061: register is available. If not, return -1. */ 2062: 2063: static int 2064: find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested, 2065: born_index, dead_index) 2066: enum reg_class class; 2067: enum machine_mode mode; 1.1.1.7 ! root 2068: int qty; 1.1 root 2069: int accept_call_clobbered; 2070: int just_try_suggested; 2071: int born_index, dead_index; 2072: { 2073: register int i, ins; 2074: #ifdef HARD_REG_SET 2075: register /* Declare it register if it's a scalar. */ 2076: #endif 2077: HARD_REG_SET used, first_used; 2078: #ifdef ELIMINABLE_REGS 2079: static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; 2080: #endif 2081: 2082: /* Validate our parameters. */ 2083: if (born_index < 0 || born_index > dead_index) 2084: abort (); 2085: 2086: /* Don't let a pseudo live in a reg across a function call 2087: if we might get a nonlocal goto. */ 2088: if (current_function_has_nonlocal_label 2089: && qty_n_calls_crossed[qty] > 0) 2090: return -1; 2091: 2092: if (accept_call_clobbered) 2093: COPY_HARD_REG_SET (used, call_fixed_reg_set); 2094: else if (qty_n_calls_crossed[qty] == 0) 2095: COPY_HARD_REG_SET (used, fixed_reg_set); 2096: else 2097: COPY_HARD_REG_SET (used, call_used_reg_set); 2098: 2099: for (ins = born_index; ins < dead_index; ins++) 2100: IOR_HARD_REG_SET (used, regs_live_at[ins]); 2101: 2102: IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); 2103: 2104: /* Don't use the frame pointer reg in local-alloc even if 2105: we may omit the frame pointer, because if we do that and then we 2106: need a frame pointer, reload won't know how to move the pseudo 2107: to another hard reg. It can move only regs made by global-alloc. 2108: 2109: This is true of any register that can be eliminated. */ 2110: #ifdef ELIMINABLE_REGS 2111: for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++) 2112: SET_HARD_REG_BIT (used, eliminables[i].from); 1.1.1.6 root 2113: #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 2114: /* If FRAME_POINTER_REGNUM is not a real register, then protect the one 2115: that it might be eliminated into. */ 2116: SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); 2117: #endif 1.1 root 2118: #else 2119: SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); 2120: #endif 2121: 1.1.1.7 ! root 2122: #ifdef CLASS_CANNOT_CHANGE_SIZE ! 2123: if (qty_changes_size[qty]) ! 2124: IOR_HARD_REG_SET (used, ! 2125: reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]); ! 2126: #endif ! 2127: 1.1 root 2128: /* Normally, the registers that can be used for the first register in 2129: a multi-register quantity are the same as those that can be used for 2130: subsequent registers. However, if just trying suggested registers, 2131: restrict our consideration to them. If there are copy-suggested 2132: register, try them. Otherwise, try the arithmetic-suggested 2133: registers. */ 2134: COPY_HARD_REG_SET (first_used, used); 2135: 2136: if (just_try_suggested) 2137: { 1.1.1.7 ! root 2138: if (qty_phys_num_copy_sugg[qty] != 0) 1.1 root 2139: IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]); 2140: else 2141: IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]); 2142: } 2143: 2144: /* If all registers are excluded, we can't do anything. */ 2145: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); 2146: 2147: /* If at least one would be suitable, test each hard reg. */ 2148: 2149: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2150: { 2151: #ifdef REG_ALLOC_ORDER 2152: int regno = reg_alloc_order[i]; 2153: #else 2154: int regno = i; 2155: #endif 2156: if (! TEST_HARD_REG_BIT (first_used, regno) 2157: && HARD_REGNO_MODE_OK (regno, mode)) 2158: { 2159: register int j; 2160: register int size1 = HARD_REGNO_NREGS (regno, mode); 2161: for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); 2162: if (j == size1) 2163: { 2164: /* Mark that this register is in use between its birth and death 2165: insns. */ 2166: post_mark_life (regno, mode, 1, born_index, dead_index); 2167: return regno; 2168: } 2169: #ifndef REG_ALLOC_ORDER 2170: i += j; /* Skip starting points we know will lose */ 2171: #endif 2172: } 2173: } 2174: 2175: fail: 2176: 2177: /* If we are just trying suggested register, we have just tried copy- 2178: suggested registers, and there are arithmetic-suggested registers, 2179: try them. */ 2180: 2181: /* If it would be profitable to allocate a call-clobbered register 2182: and save and restore it around calls, do that. */ 1.1.1.7 ! root 2183: if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0 ! 2184: && qty_phys_num_sugg[qty] != 0) 1.1 root 2185: { 2186: /* Don't try the copy-suggested regs again. */ 1.1.1.7 ! root 2187: qty_phys_num_copy_sugg[qty] = 0; 1.1 root 2188: return find_free_reg (class, mode, qty, accept_call_clobbered, 1, 2189: born_index, dead_index); 2190: } 2191: 1.1.1.5 root 2192: /* We need not check to see if the current function has nonlocal 2193: labels because we don't put any pseudos that are live over calls in 2194: registers in that case. */ 2195: 1.1 root 2196: if (! accept_call_clobbered 2197: && flag_caller_saves 2198: && ! just_try_suggested 2199: && qty_n_calls_crossed[qty] != 0 2200: && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty])) 2201: { 2202: i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index); 2203: if (i >= 0) 2204: caller_save_needed = 1; 2205: return i; 2206: } 2207: return -1; 2208: } 2209: 2210: /* Mark that REGNO with machine-mode MODE is live starting from the current 2211: insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE 2212: is zero). */ 2213: 2214: static void 2215: mark_life (regno, mode, life) 2216: register int regno; 2217: enum machine_mode mode; 2218: int life; 2219: { 2220: register int j = HARD_REGNO_NREGS (regno, mode); 2221: if (life) 2222: while (--j >= 0) 2223: SET_HARD_REG_BIT (regs_live, regno + j); 2224: else 2225: while (--j >= 0) 2226: CLEAR_HARD_REG_BIT (regs_live, regno + j); 2227: } 2228: 2229: /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE 2230: is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) 2231: to insn number DEATH (exclusive). */ 2232: 2233: static void 2234: post_mark_life (regno, mode, life, birth, death) 1.1.1.7 ! root 2235: int regno; 1.1 root 2236: enum machine_mode mode; 1.1.1.7 ! root 2237: int life, birth, death; 1.1 root 2238: { 2239: register int j = HARD_REGNO_NREGS (regno, mode); 2240: #ifdef HARD_REG_SET 2241: register /* Declare it register if it's a scalar. */ 2242: #endif 2243: HARD_REG_SET this_reg; 2244: 2245: CLEAR_HARD_REG_SET (this_reg); 2246: while (--j >= 0) 2247: SET_HARD_REG_BIT (this_reg, regno + j); 2248: 2249: if (life) 2250: while (birth < death) 2251: { 2252: IOR_HARD_REG_SET (regs_live_at[birth], this_reg); 2253: birth++; 2254: } 2255: else 2256: while (birth < death) 2257: { 2258: AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); 2259: birth++; 2260: } 2261: } 2262: 2263: /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 2264: is the register being clobbered, and R1 is a register being used in 2265: the equivalent expression. 2266: 2267: If R1 dies in the block and has a REG_NO_CONFLICT note on every insn 2268: in which it is used, return 1. 2269: 2270: Otherwise, return 0. */ 2271: 2272: static int 2273: no_conflict_p (insn, r0, r1) 2274: rtx insn, r0, r1; 2275: { 2276: int ok = 0; 1.1.1.4 root 2277: rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); 1.1 root 2278: rtx p, last; 2279: 2280: /* If R1 is a hard register, return 0 since we handle this case 2281: when we scan the insns that actually use it. */ 2282: 2283: if (note == 0 2284: || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) 2285: || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG 2286: && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) 2287: return 0; 2288: 2289: last = XEXP (note, 0); 2290: 2291: for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) 2292: if (GET_RTX_CLASS (GET_CODE (p)) == 'i') 2293: { 2294: if (find_reg_note (p, REG_DEAD, r1)) 2295: ok = 1; 2296: 2297: if (reg_mentioned_p (r1, PATTERN (p)) 2298: && ! find_reg_note (p, REG_NO_CONFLICT, r1)) 2299: return 0; 2300: } 2301: 2302: return ok; 2303: } 2304: 1.1.1.4 root 2305: #ifdef REGISTER_CONSTRAINTS 2306: 1.1.1.7 ! root 2307: /* Return the number of alternatives for which the constraint string P ! 2308: indicates that the operand must be equal to operand 0 and that no register ! 2309: is acceptable. */ 1.1 root 2310: 2311: static int 1.1.1.7 ! root 2312: requires_inout (p) 1.1 root 2313: char *p; 2314: { 2315: char c; 2316: int found_zero = 0; 1.1.1.7 ! root 2317: int reg_allowed = 0; ! 2318: int num_matching_alts = 0; 1.1 root 2319: 2320: while (c = *p++) 2321: switch (c) 2322: { 2323: case '=': case '+': case '?': 2324: case '#': case '&': case '!': 1.1.1.7 ! root 2325: case '*': case '%': 1.1 root 2326: case '1': case '2': case '3': case '4': 2327: case 'm': case '<': case '>': case 'V': case 'o': 2328: case 'E': case 'F': case 'G': case 'H': 2329: case 's': case 'i': case 'n': 2330: case 'I': case 'J': case 'K': case 'L': 2331: case 'M': case 'N': case 'O': case 'P': 2332: #ifdef EXTRA_CONSTRAINT 2333: case 'Q': case 'R': case 'S': case 'T': case 'U': 2334: #endif 2335: case 'X': 2336: /* These don't say anything we care about. */ 2337: break; 2338: 1.1.1.7 ! root 2339: case ',': ! 2340: if (found_zero && ! reg_allowed) ! 2341: num_matching_alts++; ! 2342: ! 2343: found_zero = reg_allowed = 0; ! 2344: break; ! 2345: ! 2346: case '0': ! 2347: found_zero = 1; ! 2348: break; ! 2349: 1.1 root 2350: case 'p': 2351: case 'g': case 'r': 2352: default: 1.1.1.7 ! root 2353: reg_allowed = 1; ! 2354: break; 1.1 root 2355: } 2356: 1.1.1.7 ! root 2357: if (found_zero && ! reg_allowed) ! 2358: num_matching_alts++; ! 2359: ! 2360: return num_matching_alts; 1.1 root 2361: } 1.1.1.4 root 2362: #endif /* REGISTER_CONSTRAINTS */ 1.1 root 2363: 2364: void 2365: dump_local_alloc (file) 2366: FILE *file; 2367: { 2368: register int i; 2369: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 2370: if (reg_renumber[i] != -1) 2371: fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); 2372: }
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