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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Motorola 68000 Version
3: ;; Copyright (C) 1987 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is distributed in the hope that it will be useful,
8: ;; but WITHOUT ANY WARRANTY. No author or distributor
9: ;; accepts responsibility to anyone for the consequences of using it
10: ;; or for whether it serves any particular purpose or works at all,
11: ;; unless he says so in writing. Refer to the GNU CC General Public
12: ;; License for full details.
13:
14: ;; Everyone is granted permission to copy, modify and redistribute
15: ;; GNU CC, but only under the conditions described in the
16: ;; GNU CC General Public License. A copy of this license is
17: ;; supposed to have been given to you along with GNU CC so you
18: ;; can know your rights and responsibilities. It should be in a
19: ;; file named COPYING. Among other things, the copyright notice
20: ;; and this notice must be preserved on all copies.
21:
22:
23: ;;- instruction definitions
24:
25: ;;- @@The original PO technology requires these to be ordered by speed,
26: ;;- @@ so that assigner will pick the fastest.
27:
28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29:
30: ;;- When naming insn's (operand 0 of define_insn) be careful about using
31: ;;- names from other targets machine descriptions.
32:
33: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
34: ;;- updates for most instructions.
35:
36: ;;- Operand classes for the register allocator:
37: ;;- 'a' one of the address registers can be used.
38: ;;- 'd' one of the data registers can be used.
39: ;;- 'r' either a data or an address register can be used.
40:
41: ;;- Some of these insn's are composites of several m68000 op codes.
42: ;;- The assembler (or final @@??) insures that the appropriate one is
43: ;;- selected.
44:
45: ;; Note that DBcc cannot be used, since it deals with a 16-bit count only.
46: ;;- Scc should be added.
47:
48: (define_insn ""
49: [(set (match_operand:DF 0 "push_operand" "=m")
50: (match_operand:DF 1 "general_operand" "rofF"))]
51: ""
52: "*
53: {
54: extern rtx adj_offsetable_operand();
55: extern void output_asm_insn();
56: rtx newops[2];
57:
58: if (FP_REG_P (operands[1]))
59: return \"fmoved %1,%0\";
60: if (REG_P (operands[1]))
61: newops[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
62: else
63: newops[1] = adj_offsetable_operand (operands[1], 4);
64: output_asm_insn (\"movl %1,sp@-\", newops);
65: return \"movl %1,sp@-\";
66: }")
67:
68: (define_insn ""
69: [(set (match_operand:DI 0 "push_operand" "=m")
70: (match_operand:DI 1 "general_operand" "ro"))]
71: ""
72: "*
73: {
74: extern rtx adj_offsetable_operand();
75: extern void output_asm_insn();
76: rtx newops[2];
77:
78: if (REG_P (operands[1]))
79: newops[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
80: else
81: newops[1] = adj_offsetable_operand (operands[1], 4);
82: output_asm_insn (\"movl %1,sp@-\", newops);
83: return \"movl %1,sp@-\";
84: }")
85:
86: (define_insn "tstsi"
87: [(set (cc0)
88: (match_operand:SI 0 "general_operand" "rm"))]
89: ""
90: "*
91: { if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
92: return \"tstl %0\";
93: return \"cmpl #0,%0\"; }")
94:
95: (define_insn "tsthi"
96: [(set (cc0)
97: (match_operand:HI 0 "general_operand" "rm"))]
98: ""
99: "*
100: { if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
101: return \"tstw %0\";
102: return \"cmpw #0,%0\"; }")
103:
104: (define_insn "tstqi"
105: [(set (cc0)
106: (match_operand:QI 0 "general_operand" "dm"))]
107: ""
108: "tstb %0")
109:
110: (define_insn "tstsf"
111: [(set (cc0)
112: (match_operand:SF 0 "general_operand" "fdm"))]
113: "TARGET_68881"
114: "*
115: {
116: cc_status.flags = CC_IN_68881;
117: if (FP_REG_P (operands[0]))
118: return \"ftstx %0\";
119: return \"ftsts %0\";
120: }")
121:
122: (define_insn "tstdf"
123: [(set (cc0)
124: (match_operand:DF 0 "general_operand" "fm"))]
125: "TARGET_68881"
126: "*
127: {
128: cc_status.flags = CC_IN_68881;
129: if (FP_REG_P (operands[0]))
130: return \"ftstx %0\";
131: return \"ftstd %0\";
132: }")
133:
134: ;;- compare instructions
135: ;;- A composite of the cmp, cmpa, & cmpi m68000 op codes.
136: (define_insn "cmpsi"
137: [(set (cc0)
138: (minus (match_operand:SI 0 "general_operand" "rKs,mrKs")
139: (match_operand:SI 1 "general_operand" "mrKs,Ksr")))]
140: ""
141: "*
142: {
143: if (REG_P (operands[1])
144: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
145: { cc_status.flags |= CC_REVERSED; return \"cmpl %0,%1\"; }
146: return \"cmpl %1,%0\";
147: }")
148:
149: (define_insn "cmphi"
150: [(set (cc0)
151: (minus (match_operand:HI 0 "general_operand" "ri,g")
152: (match_operand:HI 1 "general_operand" "g,ir")))]
153: ""
154: "*
155: {
156: if (REG_P (operands[1])
157: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
158: { cc_status.flags |= CC_REVERSED; return \"cmpw %0,%1\"; }
159: return \"cmpw %1,%0\";
160: }")
161:
162: (define_insn ""
163: [(set (cc0)
164: (minus (mem:QI (post_inc:SI (match_operand:SI 0 "general_operand" "+a")))
165: (mem:QI (post_inc:SI (match_operand:SI 1 "general_operand" "+a")))))]
166: ""
167: "cmpmb %1@+,%0@+")
168:
169: (define_insn "cmpqi"
170: [(set (cc0)
171: (minus (match_operand:QI 0 "general_operand" "di,m")
172: (match_operand:QI 1 "general_operand" "dmi,id")))]
173: ""
174: "*
175: {
176: if (REG_P (operands[1])
177: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
178: { cc_status.flags |= CC_REVERSED; return \"cmpb %0,%1\"; }
179: return \"cmpb %1,%0\";
180: }")
181:
182: (define_insn "cmpdf"
183: [(set (cc0)
184: (minus:DF (match_operand:DF 0 "general_operand" "f,m")
185: (match_operand:DF 1 "general_operand" "fm,f")))]
186: "TARGET_68881"
187: "*
188: {
189: cc_status.flags = CC_IN_68881;
190: if (REG_P (operands[0]))
191: {
192: if (REG_P (operands[1]))
193: return \"fcmpx %1,%0\";
194: else
195: return \"fcmpd %1,%0\";
196: }
197: cc_status.flags |= CC_REVERSED;
198: return \"fcmpd %0,%1\";
199: }")
200:
201: (define_insn "cmpsf"
202: [(set (cc0)
203: (minus:SF (match_operand:SF 0 "general_operand" "f,md")
204: (match_operand:SF 1 "general_operand" "fmd,f")))]
205: "TARGET_68881"
206: "*
207: {
208: cc_status.flags = CC_IN_68881;
209: if (FP_REG_P (operands[0]))
210: {
211: if (FP_REG_P (operands[1]))
212: return \"fcmpx %1,%0\";
213: else
214: return \"fcmps %1,%0\";
215: }
216: cc_status.flags |= CC_REVERSED;
217: return \"fcmps %0,%1\";
218: }")
219:
220: ;; Recognizers for btst instructions.
221:
222: (define_insn ""
223: [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "dm")
224: (const_int 1)
225: (minus:SI (const_int 7)
226: (match_operand:SI 1 "general_operand" "di"))))]
227: ""
228: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
229:
230: (define_insn ""
231: [(set (cc0) (zero_extract (match_operand:SI 0 "general_operand" "d")
232: (const_int 1)
233: (minus:SI (const_int 31)
234: (match_operand:SI 1 "general_operand" "di"))))]
235: ""
236: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
237:
238: (define_insn ""
239: [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "dm")
240: (const_int 1)
241: (match_operand:SI 1 "general_operand" "i")))]
242: "GET_CODE (operands[1]) == CONST_INT"
243: "*
244: { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
245: return output_btst (operands, operands[1], operands[0], insn, 7); }")
246:
247: (define_insn ""
248: [(set (cc0) (zero_extract (match_operand:SI 0 "general_operand" "do")
249: (const_int 1)
250: (match_operand:SI 1 "general_operand" "i")))]
251: "GET_CODE (operands[1]) == CONST_INT"
252: "*
253: {
254: if (GET_CODE (operands[0]) == MEM)
255: {
256: operands[0] = adj_offsetable_operand (operands[0],
257: INTVAL (operands[1]) / 8);
258: operands[1] = gen_rtx (CONST_INT, VOIDmode,
259: 7 - INTVAL (operands[1]) % 8);
260: return output_btst (operands, operands[1], operands[0], insn, 7);
261: }
262: operands[1] = gen_rtx (CONST_INT, VOIDmode,
263: 31 - INTVAL (operands[1]));
264: return output_btst (operands, operands[1], operands[0], insn, 31);
265: }")
266:
267: (define_insn ""
268: [(set (cc0) (subreg:SI (lshiftrt:QI (match_operand:QI 0 "general_operand" "dm")
269: (const_int 7))
270: 0))]
271: ""
272: "*
273: {
274: cc_status.flags = CC_Z_IN_NOT_N | CC_NOT_NEGATIVE;
275: return \"tstb %0\";
276: }")
277:
278: (define_insn ""
279: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "general_operand" "dm")))
280: (match_operand:SI 1 "general_operand" "i")))]
281: "(GET_CODE (operands[1]) == CONST_INT
282: && (unsigned) INTVAL (operands[1]) < 0x100
283: && exact_log2 (INTVAL (operands[1])) >= 0)"
284: "*
285: { register int log = exact_log2 (INTVAL (operands[1]));
286: operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
287: return output_btst (operands, operands[1], operands[0], insn, 7);
288: }")
289:
290: ;;- move instructions
291: (define_insn "swapsi"
292: [(set (match_operand:SI 0 "general_operand" "r")
293: (match_operand:SI 1 "general_operand" "r"))
294: (set (match_dup 1) (match_dup 0))]
295: ""
296: "exg %1,%2")
297:
298: ;; Special case of fullword move when source is zero.
299: ;; The reason this is special is to avoid loading a zero
300: ;; into a data reg with moveq in order to store it elsewhere.
301:
302: (define_insn ""
303: [(set (match_operand:SI 0 "general_operand" "=g")
304: (const_int 0))]
305: ""
306: "*
307: {
308: if (ADDRESS_REG_P (operands[0]))
309: return \"movw #0,%0\";
310: return \"clrl %0\";
311: }")
312:
313: ;; Another special case in which it is not desirable
314: ;; to reload the constant into a data register.
315: (define_insn ""
316: [(set (match_operand:SI 0 "push_operand" "=m")
317: (match_operand:SI 1 "general_operand" "J"))]
318: "GET_CODE (operands[1]) == CONST_INT
319: && INTVAL (operands[1]) >= -0x8000
320: && INTVAL (operands[1]) < 0x8000"
321: "pea %a1")
322:
323: ;; General case of fullword move. The register constraints
324: ;; force integer constants in range for a moveq to be reloaded
325: ;; if they are headed for memory.
326: (define_insn "movsi"
327: [(set (match_operand:SI 0 "general_operand" "=g,da")
328: (match_operand:SI 1 "general_operand" "damKs,i"))]
329: ""
330: "*
331: {
332: if (GET_CODE (operands[1]) == CONST_INT)
333: {
334: if (operands[1] == const0_rtx
335: && (DATA_REG_P (operands[0])
336: || GET_CODE (operands[0]) == MEM))
337: return \"clrl %0\";
338: else if (DATA_REG_P (operands[0])
339: && INTVAL (operands[1]) < 128
340: && INTVAL (operands[1]) >= -128)
341: return \"moveq %1,%0\";
342: else if (ADDRESS_REG_P (operands[0])
343: && INTVAL (operands[1]) < 0x8000
344: && INTVAL (operands[1]) >= -0x8000)
345: return \"movw %1,%0\";
346: else if (push_operand (operands[0], SImode)
347: && INTVAL (operands[1]) < 0x8000
348: && INTVAL (operands[1]) >= -0x8000)
349: return \"pea %a1\";
350: }
351: else if ((GET_CODE (operands[1]) == SYMBOL_REF
352: || GET_CODE (operands[1]) == CONST)
353: && push_operand (operands[0], SImode))
354: return \"pea %a1\";
355: else if ((GET_CODE (operands[1]) == SYMBOL_REF
356: || GET_CODE (operands[1]) == CONST)
357: && ADDRESS_REG_P (operands[0]))
358: return \"lea %a1,%0\";
359: return \"movl %1,%0\";
360: }")
361:
362: (define_insn "movhi"
363: [(set (match_operand:HI 0 "general_operand" "=g")
364: (match_operand:HI 1 "general_operand" "g"))]
365: ""
366: "*
367: {
368: if (GET_CODE (operands[1]) == CONST_INT)
369: {
370: if (operands[1] == const0_rtx
371: && (DATA_REG_P (operands[0])
372: || GET_CODE (operands[0]) == MEM))
373: return \"clrw %0\";
374: }
375: return \"movw %1,%0\";
376: }")
377:
378: (define_insn "movstricthi"
379: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm"))
380: (match_operand:HI 1 "general_operand" "g"))]
381: ""
382: "*
383: {
384: if (GET_CODE (operands[1]) == CONST_INT)
385: {
386: if (operands[1] == const0_rtx
387: && (DATA_REG_P (operands[0])
388: || GET_CODE (operands[0]) == MEM))
389: return \"clrw %0\";
390: }
391: return \"movw %1,%0\";
392: }")
393:
394: (define_insn "movqi"
395: [(set (match_operand:QI 0 "general_operand" "=d,a,m")
396: (match_operand:QI 1 "general_operand" "g,d,dmi"))]
397: ""
398: "*
399: {
400: if (operands[1] == const0_rtx)
401: return \"clrb %0\";
402: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
403: return \"movw %1,%0\";
404: return \"movb %1,%0\";
405: }")
406:
407: (define_insn "movestrictqi"
408: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d,m"))
409: (match_operand:QI 1 "general_operand" "g,dmi"))]
410: ""
411: "*
412: {
413: if (operands[1] == const0_rtx)
414: return \"clrb %0\";
415: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
416: return \"movw %1,%0\";
417: return \"movb %1,%0\";
418: }")
419:
420: (define_insn "movsf"
421: [(set (match_operand:SF 0 "general_operand" "=gf")
422: (match_operand:SF 1 "general_operand" "gf"))]
423: ""
424: "*
425: {
426: if (FP_REG_P (operands[0]))
427: {
428: if (FP_REG_P (operands[1]))
429: return \"fmovex %1,%0\";
430: else
431: return \"fmoves %1,%0\";
432: }
433: if (FP_REG_P (operands[1]))
434: return \"fmoves %1,%0\";
435: return \"movl %1,%0\";
436: }")
437:
438: (define_insn "movdf"
439: [(set (match_operand:DF 0 "general_operand" "=rmf")
440: (match_operand:DF 1 "general_operand" "rmfF"))]
441: ""
442: "*
443: {
444: if (FP_REG_P (operands[0]))
445: {
446: if (FP_REG_P (operands[1]))
447: return \"fmovex %1,%0\";
448: if (DATA_REG_P (operands[1]))
449: {
450: rtx xoperands[2];
451: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
452: output_asm_insn (\"movl %1,sp@-\", xoperands);
453: output_asm_insn (\"movl %1,sp@-\", operands);
454: return \"fmoved sp@+,%0\";
455: }
456: if (GET_CODE (operands[1]) == CONST_DOUBLE)
457: return output_move_const_double (operands);
458: return \"fmoved %1,%0\";
459: }
460: else if (FP_REG_P (operands[1]))
461: {
462: if (DATA_REG_P (operands[0]))
463: {
464: output_asm_insn (\"fmoved %1,sp@-\;movl sp@+,%0\", operands);
465: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
466: return \"movl sp@+,%0\";
467: }
468: else
469: return \"fmoved %1,%0\";
470: }
471: return output_move_double (operands);
472: }
473: ")
474:
475: (define_insn "movdi"
476: [(set (match_operand:DI 0 "general_operand" "=rmf")
477: (match_operand:DI 1 "general_operand" "rmifF"))]
478: ""
479: "*
480: {
481: if (FP_REG_P (operands[0]))
482: {
483: if (FP_REG_P (operands[1]))
484: return \"fmovex %1,%0\";
485: if (DATA_REG_P (operands[1]))
486: {
487: rtx xoperands[2];
488: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
489: output_asm_insn (\"movl %1,sp@-\", xoperands);
490: output_asm_insn (\"movl %1,sp@-\", operands);
491: return \"fmoved sp@+,%0\";
492: }
493: if (GET_CODE (operands[1]) == CONST_DOUBLE)
494: return output_move_const_double (operands);
495: return \"fmoved %1,%0\";
496: }
497: else if (FP_REG_P (operands[1]))
498: {
499: if (DATA_REG_P (operands[0]))
500: {
501: output_asm_insn (\"fmoved %1,sp@-\;movl sp@+,%0\", operands);
502: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
503: return \"movl sp@+,%0\";
504: }
505: else
506: return \"fmoved %1,%0\";
507: }
508: return output_move_double (operands);
509: }
510: ")
511:
512: ;; These go after the move instructions
513: ;; because the move instructions are better (require no spilling)
514: ;; when they can apply. But these go before the add and subtract insns
515: ;; because it is often shorter to use these when both apply.
516: (define_insn "pushasi"
517: [(set (match_operand:SI 0 "push_operand" "=m")
518: (match_operand:SI 1 "address_operand" "p"))]
519: ""
520: "pea %a1")
521:
522:
523: (define_insn ""
524: [(set (match_operand:SI 0 "general_operand" "=a")
525: (match_operand:QI 1 "address_operand" "p"))]
526: ""
527: "lea %a1,%0")
528:
529: ;;- conversion instructions
530: ;;- NONE
531:
532: ;;- truncation instructions
533: (define_insn "truncsiqi2"
534: [(set (match_operand:QI 0 "general_operand" "=dm")
535: (truncate:QI
536: (match_operand:SI 1 "general_operand" "doi")))]
537: ""
538: "*
539: {
540: if (! REG_P (operands[1]))
541: operands[1] = adj_offsetable_operand (operands[1], 3);
542: return \"movb %1,%0\";
543: }")
544:
545: (define_insn "trunchiqi2"
546: [(set (match_operand:QI 0 "general_operand" "=dm")
547: (truncate:QI
548: (match_operand:HI 1 "general_operand" "doi")))]
549: ""
550: "*
551: {
552: if (! REG_P (operands[1]))
553: operands[1] = adj_offsetable_operand (operands[1], 1);
554: return \"movb %1,%0\";
555: }")
556:
557: (define_insn "truncsihi2"
558: [(set (match_operand:HI 0 "general_operand" "=dm")
559: (truncate:HI
560: (match_operand:SI 1 "general_operand" "roi")))]
561: ""
562: "*
563: {
564: if (! REG_P (operands[1]))
565: operands[1] = adj_offsetable_operand (operands[1], 2);
566: return \"movw %1,%0\";
567: }")
568:
569: ;;- zero extension instructions
570: (define_insn "zero_extendqihi2"
571: [(set (match_operand:HI 0 "general_operand" "=do<>")
572: (zero_extend:HI
573: (match_operand:QI 1 "general_operand" "dmi")))]
574: ""
575: "*
576: {
577: if (DATA_REG_P (operands[0]))
578: {
579: if (GET_CODE (operands[1]) == REG
580: && REGNO (operands[0]) == REGNO (operands[1]))
581: return \"andw #0xFF,%0\";
582: if (reg_mentioned_p (operands[0], operands[1]))
583: return \"movb %1,%0\;andw #0xFF,%0\";
584: return \"clrw %0\;movb %1,%0\";
585: }
586: else if (GET_CODE (operands[0]) == MEM
587: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
588: {
589: if (REGNO (XEXP (XEXP (operands[0], 0), 0))
590: == STACK_POINTER_REGNUM)
591: return \"clrw sp@-\;movb %1,%0\";
592: else
593: return \"movb %1,%0\;clrb %0\";
594: }
595: else if (GET_CODE (operands[0]) == MEM
596: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
597: return \"clrb %0\;movb %1,%0\";
598: else
599: {
600: output_asm_insn (\"clrb %0\", operands);
601: operands[0] = adj_offsetable_operand (operands[0], 1);
602: return \"movb %1,%0\";
603: }
604: }")
605:
606: (define_insn "zero_extendqisi2"
607: [(set (match_operand:SI 0 "general_operand" "=do<>")
608: (zero_extend:SI
609: (match_operand:QI 1 "general_operand" "dmi")))]
610: ""
611: "*
612: {
613: if (DATA_REG_P (operands[0]))
614: {
615: if (GET_CODE (operands[1]) == REG
616: && REGNO (operands[0]) == REGNO (operands[1]))
617: return \"andl #0xFF,%0\";
618: if (reg_mentioned_p (operands[0], operands[1]))
619: return \"movb %1,%0\;andl #0xFF,%0\";
620: return \"clrl %0\;movb %1,%0\";
621: }
622: else if (GET_CODE (operands[0]) == MEM
623: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
624: {
625: operands[0] = XEXP (XEXP (operands[0], 0), 0);
626: return \"clrl %0@-\;movb %1,%0@(3)\";
627: }
628: else if (GET_CODE (operands[0]) == MEM
629: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
630: {
631: operands[0] = XEXP (XEXP (operands[0], 0), 0);
632: return \"clrl %0@+\;movb %1,%0@(-1)\";
633: }
634: else
635: {
636: output_asm_insn (\"clrl %0\", operands);
637: operands[0] = adj_offsetable_operand (operands[0], 3);
638: return \"movb %1,%0\";
639: }
640: }")
641:
642: (define_insn "zero_extendhisi2"
643: [(set (match_operand:SI 0 "general_operand" "=do<")
644: (zero_extend:SI
645: (match_operand:HI 1 "general_operand" "g")))]
646: ""
647: "*
648: {
649: if (DATA_REG_P (operands[0]))
650: {
651: if (GET_CODE (operands[1]) == REG
652: && REGNO (operands[0]) == REGNO (operands[1]))
653: return \"andl #0xFFFF,%0\";
654: if (reg_mentioned_p (operands[0], operands[1]))
655: return \"movw %1,%0\;andl #0xFFFF,%0\";
656: return \"clrl %0\;movw %1,%0\";
657: }
658: else if (GET_CODE (operands[0]) == MEM
659: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
660: return \"movw %1,%0\;clrw %0\";
661: else if (GET_CODE (operands[0]) == MEM
662: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
663: return \"clrw %0\;movw %1,%0\";
664: else
665: {
666: output_asm_insn (\"clrw %0\", operands);
667: operands[0] = adj_offsetable_operand (operands[0], 2);
668: return \"movw %1,%0\";
669: }
670: }")
671:
672: ;;- sign extension instructions
673: (define_insn "extendqihi2"
674: [(set (match_operand:HI 0 "general_operand" "=d")
675: (sign_extend:HI
676: (match_operand:QI 1 "general_operand" "0")))]
677: ""
678: "extw %0")
679:
680: (define_insn "extendqisi2"
681: [(set (match_operand:SI 0 "general_operand" "=d")
682: (sign_extend:SI
683: (match_operand:QI 1 "general_operand" "0")))]
684: "TARGET_68020"
685: "extbl %0")
686:
687: (define_insn "extendhisi2"
688: [(set (match_operand:SI 0 "general_operand" "=*d,a")
689: (sign_extend:SI
690: (match_operand:HI 1 "general_operand" "0,g")))]
691: ""
692: "*
693: {
694: if (ADDRESS_REG_P (operands[0]))
695: return \"movw %1,%0\";
696: return \"extl %0\";
697: }")
698:
699: ;; Conversions between float and double.
700:
701: (define_insn "extendsfdf2"
702: [(set (match_operand:DF 0 "general_operand" "=*fg,f")
703: (float_extend:DF
704: (match_operand:SF 1 "general_operand" "f,g")))]
705: ""
706: "*
707: {
708: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
709: return \"fmovex %1,%0\";
710: if (FP_REG_P (operands[0]))
711: return \"fmoves %1,%0\";
712: if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
713: {
714: output_asm_insn (\"fmoved %1,sp@-\;movl sp@+,%0\", operands);
715: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
716: return \"movl sp@+,%0\";
717: }
718: return \"fmoved %1,%0\";
719: }")
720:
721: ;; This cannot output into an f-reg because there is no way to be
722: ;; sure of truncating in that case.
723: (define_insn "truncdfsf2"
724: [(set (match_operand:SF 0 "general_operand" "=g")
725: (float_truncate:SF
726: (match_operand:DF 1 "general_operand" "f")))]
727: ""
728: "*
729: {
730: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
731: return \"fmovex %1,%0\";
732: if (FP_REG_P (operands[0]) && DATA_REG_P (operands[1]))
733: {
734: rtx xoperands[2];
735: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
736: output_asm_insn (\"movl %1,sp@-\", xoperands);
737: output_asm_insn (\"movl %1,sp@-\", operands);
738: return \"fmoved sp@+,%0\";
739: }
740: if (FP_REG_P (operands[0]))
741: return \"fmoved %1,%0\";
742: return \"fmoves %1,%0\";
743: }")
744:
745: ;; Conversion between fixed point and floating point.
746:
747: (define_insn "floatqisf2"
748: [(set (match_operand:SF 0 "general_operand" "=f")
749: (float:SF (match_operand:QI 1 "general_operand" "dmi")))]
750: "TARGET_68881"
751: "fmoveb %1,%0")
752:
753: (define_insn "floatqidf2"
754: [(set (match_operand:DF 0 "general_operand" "=f")
755: (float:DF (match_operand:QI 1 "general_operand" "dmi")))]
756: "TARGET_68881"
757: "fmoveb %1,%0")
758:
759: (define_insn "floathisf2"
760: [(set (match_operand:SF 0 "general_operand" "=f")
761: (float:SF (match_operand:HI 1 "general_operand" "dmi")))]
762: "TARGET_68881"
763: "fmovew %1,%0")
764:
765: (define_insn "floathidf2"
766: [(set (match_operand:DF 0 "general_operand" "=f")
767: (float:DF (match_operand:HI 1 "general_operand" "dmi")))]
768: "TARGET_68881"
769: "fmovew %1,%0")
770:
771: (define_insn "floatsisf2"
772: [(set (match_operand:SF 0 "general_operand" "=f")
773: (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
774: "TARGET_68881"
775: "fmovel %1,%0")
776:
777: (define_insn "floatsidf2"
778: [(set (match_operand:DF 0 "general_operand" "=f")
779: (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
780: "TARGET_68881"
781: "fmovel %1,%0")
782:
783: (define_insn "fixsfqi2"
784: [(set (match_operand:QI 0 "general_operand" "=dm")
785: (fix:QI (match_operand:SF 1 "general_operand" "f")))]
786: "TARGET_68881"
787: "fmoveb %1,%0")
788:
789: (define_insn "fixsfhi2"
790: [(set (match_operand:HI 0 "general_operand" "=dm")
791: (fix:HI (match_operand:SF 1 "general_operand" "f")))]
792: "TARGET_68881"
793: "fmovew %1,%0")
794:
795: (define_insn "fixsfsi2"
796: [(set (match_operand:SI 0 "general_operand" "=dm")
797: (fix:SI (match_operand:SF 1 "general_operand" "f")))]
798: "TARGET_68881"
799: "fmovel %1,%0")
800:
801: (define_insn "fixdfqi2"
802: [(set (match_operand:QI 0 "general_operand" "=dm")
803: (fix:QI (match_operand:DF 1 "general_operand" "f")))]
804: "TARGET_68881"
805: "fmoveb %1,%0")
806:
807: (define_insn "fixdfhi2"
808: [(set (match_operand:HI 0 "general_operand" "=dm")
809: (fix:HI (match_operand:DF 1 "general_operand" "f")))]
810: "TARGET_68881"
811: "fmovew %1,%0")
812:
813: (define_insn "fixdfsi2"
814: [(set (match_operand:SI 0 "general_operand" "=dm")
815: (fix:SI (match_operand:DF 1 "general_operand" "f")))]
816: "TARGET_68881"
817: "fmovel %1,%0")
818:
819: ;;- add instructions
820: ;;- A composite of the add, adda, addi, & addq m68000 op codes.
821:
822: (define_insn "addsi3"
823: [(set (match_operand:SI 0 "general_operand" "=%m,r,!a")
824: (plus:SI (match_operand:SI 1 "general_operand" "0,0,a")
825: (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJ")))]
826: ""
827: "*
828: {
829: if (! rtx_equal_p (operands[0], operands[1]))
830: {
831: if (GET_CODE (operands[2]) == REG)
832: return \"lea %1@(%2),%0\";
833: else
834: return \"lea %1@(%c2),%0\";
835: }
836: if (GET_CODE (operands[2]) == CONST_INT)
837: {
838: if (INTVAL (operands[2]) > 0
839: && INTVAL (operands[2]) <= 8)
840: return \"addql %2,%0\";
841: if (INTVAL (operands[2]) < 0
842: && INTVAL (operands[2]) >= -8)
843: {
844: operands[2] = gen_rtx (CONST_INT, VOIDmode,
845: - INTVAL (operands[2]));
846: return \"subql %2,%0\";
847: }
848: if (ADDRESS_REG_P (operands[0])
849: && INTVAL (operands[2]) >= -0x8000
850: && INTVAL (operands[2]) < 0x8000)
851: return \"addw %2,%0\";
852: }
853: return \"addl %2,%0\";
854: }")
855:
856: (define_insn ""
857: [(set (match_operand:SI 0 "general_operand" "=a")
858: (plus:SI (match_operand:SI 1 "general_operand" "0")
859: (sign_extend:SI (match_operand:HI 2 "general_operand" "g"))))]
860: ""
861: "addw %2,%0")
862:
863: (define_insn "addhi3"
864: [(set (match_operand:HI 0 "general_operand" "=%m,r")
865: (plus:HI (match_operand:HI 1 "general_operand" "0,0")
866: (match_operand:HI 2 "general_operand" "di,g")))]
867: ""
868: "*
869: {
870: if (GET_CODE (operands[2]) == CONST_INT)
871: {
872: if (INTVAL (operands[2]) > 0
873: && INTVAL (operands[2]) <= 8)
874: return \"addqw %2,%0\";
875: }
876: return \"addw %2,%0\";
877: }")
878:
879: (define_insn ""
880: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
881: (plus:HI (match_dup 0)
882: (match_operand:HI 1 "general_operand" "di,g")))]
883: ""
884: "addw %1,%0")
885:
886: (define_insn "addqi3"
887: [(set (match_operand:QI 0 "general_operand" "=%m,d")
888: (plus:QI (match_operand:QI 1 "general_operand" "0,0")
889: (match_operand:QI 2 "general_operand" "di,dmi")))]
890: ""
891: "*
892: {
893: if (GET_CODE (operands[2]) == CONST_INT)
894: {
895: if (INTVAL (operands[2]) > 0
896: && INTVAL (operands[2]) <= 8)
897: return \"addqb %2,%0\";
898: }
899: return \"addb %2,%0\";
900: }")
901:
902: (define_insn ""
903: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
904: (plus:QI (match_dup 0)
905: (match_operand:QI 1 "general_operand" "di,dmi")))]
906: ""
907: "addb %1,%0")
908:
909: (define_insn "adddf3"
910: [(set (match_operand:DF 0 "general_operand" "=%f")
911: (plus:DF (match_operand:DF 1 "general_operand" "0")
912: (match_operand:DF 2 "general_operand" "fmG")))]
913: "TARGET_68881"
914: "*
915: {
916: if (REG_P (operands[2]))
917: return \"faddx %2,%0\";
918: return \"faddd %2,%0\";
919: }")
920:
921: (define_insn "addsf3"
922: [(set (match_operand:SF 0 "general_operand" "=%f")
923: (plus:SF (match_operand:SF 1 "general_operand" "0")
924: (match_operand:SF 2 "general_operand" "fdmG")))]
925: "TARGET_68881"
926: "*
927: {
928: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
929: return \"faddx %2,%0\";
930: return \"fadds %2,%0\";
931: }")
932:
933: ;;- subtract instructions
934: ;;- A composite of the sub, suba, subi, & subq m68000 op codes.
935: (define_insn "subsi3"
936: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,r")
937: (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
938: (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
939: ""
940: "*
941: {
942: if (! rtx_equal_p (operands[0], operands[1]))
943: {
944: if (rtx_equal_p (operands[0], operands[2]))
945: {
946: if (GET_CODE (operands[1]) == CONST_INT)
947: {
948: if (INTVAL (operands[1]) > 0
949: && INTVAL (operands[1]) <= 8)
950: return \"subql %1,%0\;negl %0\";
951: if (ADDRESS_REG_P (operands[0])
952: && INTVAL (operands[1]) >= -0x8000
953: && INTVAL (operands[1]) < 0x8000)
954: return \"subw %1,%0\;negl %0\";
955: }
956: return \"subl %1,%0\;negl %0\";
957: }
958: /* This case is matched by J, but negating -0x8000
959: in an lea would give an invalid displacement.
960: So do this specially. */
961: if (INTVAL (operands[2]) == -0x8000)
962: return \"movl %1,%0\;subl %2,%0\";
963: return \"lea %1@(%n2),%0\";
964: }
965: if (GET_CODE (operands[2]) == CONST_INT)
966: {
967: if (INTVAL (operands[2]) > 0
968: && INTVAL (operands[2]) <= 8)
969: return \"subql %2,%0\";
970: if (ADDRESS_REG_P (operands[0])
971: && INTVAL (operands[2]) >= -0x8000
972: && INTVAL (operands[2]) < 0x8000)
973: return \"subw %2,%0\";
974: }
975: return \"subl %2,%0\";
976: }")
977:
978: (define_insn ""
979: [(set (match_operand:SI 0 "general_operand" "=a")
980: (minus:SI (match_operand:SI 1 "general_operand" "0")
981: (sign_extend:SI (match_operand:HI 2 "general_operand" "g"))))]
982: ""
983: "subw %2,%0")
984:
985: (define_insn "subhi3"
986: [(set (match_operand:HI 0 "general_operand" "=m,r")
987: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
988: (match_operand:HI 2 "general_operand" "di,g")))]
989: ""
990: "subw %2,%0")
991:
992: (define_insn ""
993: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
994: (minus:HI (match_dup 0)
995: (match_operand:HI 1 "general_operand" "di,g")))]
996: ""
997: "subw %1,%0")
998:
999: (define_insn "subqi3"
1000: [(set (match_operand:QI 0 "general_operand" "=m,d")
1001: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
1002: (match_operand:QI 2 "general_operand" "di,dmi")))]
1003: ""
1004: "subb %2,%0")
1005:
1006: (define_insn ""
1007: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
1008: (minus:QI (match_dup 0)
1009: (match_operand:QI 1 "general_operand" "di,dmi")))]
1010: ""
1011: "subb %1,%0")
1012:
1013: (define_insn "subdf3"
1014: [(set (match_operand:DF 0 "general_operand" "=f")
1015: (minus:DF (match_operand:DF 1 "general_operand" "0")
1016: (match_operand:DF 2 "general_operand" "fmG")))]
1017: "TARGET_68881"
1018: "*
1019: {
1020: if (REG_P (operands[2]))
1021: return \"fsubx %2,%0\";
1022: return \"fsubd %2,%0\";
1023: }")
1024:
1025: (define_insn "subsf3"
1026: [(set (match_operand:SF 0 "general_operand" "=f")
1027: (minus:SF (match_operand:SF 1 "general_operand" "0")
1028: (match_operand:SF 2 "general_operand" "fdmG")))]
1029: "TARGET_68881"
1030: "*
1031: {
1032: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1033: return \"fsubx %2,%0\";
1034: return \"fsubs %2,%0\";
1035: }")
1036:
1037: ;;- multiply instructions
1038:
1039: (define_insn "mulhi3"
1040: [(set (match_operand:HI 0 "general_operand" "=%d")
1041: (mult:HI (match_operand:HI 1 "general_operand" "0")
1042: (match_operand:HI 2 "general_operand" "dmi")))]
1043: ""
1044: "muls %2,%0")
1045:
1046: (define_insn "mulhisi3"
1047: [(set (match_operand:SI 0 "general_operand" "=%d")
1048: (mult:SI (match_operand:HI 1 "general_operand" "0")
1049: (match_operand:HI 2 "general_operand" "dmi")))]
1050: ""
1051: "muls %2,%0")
1052:
1053: (define_insn "mulsi3"
1054: [(set (match_operand:SI 0 "general_operand" "=%d")
1055: (mult:SI (match_operand:SI 1 "general_operand" "0")
1056: (match_operand:SI 2 "general_operand" "dmsK")))]
1057: "TARGET_68020"
1058: "mulsl %2,%0")
1059:
1060: (define_insn "umulhi3"
1061: [(set (match_operand:HI 0 "general_operand" "=%d")
1062: (umult:HI (match_operand:HI 1 "general_operand" "0")
1063: (match_operand:HI 2 "general_operand" "dmi")))]
1064: ""
1065: "mulu %2,%0")
1066:
1067: (define_insn "umulhisi3"
1068: [(set (match_operand:SI 0 "general_operand" "=%d")
1069: (umult:SI (match_operand:HI 1 "general_operand" "0")
1070: (match_operand:HI 2 "general_operand" "dmi")))]
1071: ""
1072: "mulu %2,%0")
1073:
1074: (define_insn "umulsi3"
1075: [(set (match_operand:SI 0 "general_operand" "=%d")
1076: (umult:SI (match_operand:SI 1 "general_operand" "0")
1077: (match_operand:SI 2 "general_operand" "dmsK")))]
1078: "TARGET_68020"
1079: "mulul %2,%0")
1080:
1081: (define_insn "muldf3"
1082: [(set (match_operand:DF 0 "general_operand" "=%f")
1083: (mult:DF (match_operand:DF 1 "general_operand" "0")
1084: (match_operand:DF 2 "general_operand" "fmG")))]
1085: "TARGET_68881"
1086: "*
1087: {
1088: if (REG_P (operands[2]))
1089: return \"fmulx %2,%0\";
1090: return \"fmuld %2,%0\";
1091: }")
1092:
1093: (define_insn "mulsf3"
1094: [(set (match_operand:SF 0 "general_operand" "=%f")
1095: (mult:SF (match_operand:SF 1 "general_operand" "0")
1096: (match_operand:SF 2 "general_operand" "fdmG")))]
1097: "TARGET_68881"
1098: "*
1099: {
1100: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1101: return \"fsglmulx %2,%0\";
1102: return \"fsglmuls %2,%0\";
1103: }")
1104:
1105: ;;- divide instructions
1106:
1107: (define_insn "divhi3"
1108: [(set (match_operand:HI 0 "general_operand" "=d")
1109: (div:HI (match_operand:HI 1 "general_operand" "0")
1110: (match_operand:HI 2 "general_operand" "dmi")))]
1111: ""
1112: "extw %0\;divs %2,%0")
1113:
1114: (define_insn "divhisi3"
1115: [(set (match_operand:HI 0 "general_operand" "=d")
1116: (div:HI (match_operand:SI 1 "general_operand" "0")
1117: (match_operand:HI 2 "general_operand" "dmi")))]
1118: ""
1119: "divs %2,%0")
1120:
1121: (define_insn "divsi3"
1122: [(set (match_operand:SI 0 "general_operand" "=d")
1123: (div:SI (match_operand:SI 1 "general_operand" "0")
1124: (match_operand:SI 2 "general_operand" "dmsK")))]
1125: ""
1126: "divsl %2,%0")
1127:
1128: (define_insn "udivhi3"
1129: [(set (match_operand:HI 0 "general_operand" "=d")
1130: (udiv:HI (match_operand:HI 1 "general_operand" "0")
1131: (match_operand:HI 2 "general_operand" "dmi")))]
1132: ""
1133: "andl #0xFFFF,%0\;divu %2,%0")
1134:
1135: (define_insn "udivhisi3"
1136: [(set (match_operand:HI 0 "general_operand" "=d")
1137: (udiv:HI (match_operand:SI 1 "general_operand" "0")
1138: (match_operand:HI 2 "general_operand" "dmi")))]
1139: ""
1140: "divu %2,%0")
1141:
1142: (define_insn "udivsi3"
1143: [(set (match_operand:SI 0 "general_operand" "=d")
1144: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1145: (match_operand:SI 2 "general_operand" "dmsK")))]
1146: ""
1147: "divul %2,%0")
1148:
1149: (define_insn "divdf3"
1150: [(set (match_operand:DF 0 "general_operand" "=f")
1151: (div:DF (match_operand:DF 1 "general_operand" "0")
1152: (match_operand:DF 2 "general_operand" "fmG")))]
1153: "TARGET_68881"
1154: "*
1155: {
1156: if (REG_P (operands[2]))
1157: return \"fdivx %2,%0\";
1158: return \"fdivd %2,%0\";
1159: }")
1160:
1161: (define_insn "divsf3"
1162: [(set (match_operand:SF 0 "general_operand" "=f")
1163: (div:SF (match_operand:SF 1 "general_operand" "0")
1164: (match_operand:SF 2 "general_operand" "fdmG")))]
1165: "TARGET_68881"
1166: "*
1167: {
1168: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1169: return \"fsgldivx %2,%0\";
1170: return \"fsgldivs %2,%0\";
1171: }")
1172:
1173: ;; Remainder instructions.
1174:
1175: (define_insn "modhi3"
1176: [(set (match_operand:HI 0 "general_operand" "=d")
1177: (mod:HI (match_operand:HI 1 "general_operand" "0")
1178: (match_operand:HI 2 "general_operand" "dmi")))]
1179: ""
1180: "extw %0\;divs %2,%0\;swap %0")
1181:
1182: (define_insn "modhisi3"
1183: [(set (match_operand:HI 0 "general_operand" "=d")
1184: (mod:HI (match_operand:SI 1 "general_operand" "0")
1185: (match_operand:HI 2 "general_operand" "dmi")))]
1186: ""
1187: "divs %2,%0\;swap %0")
1188:
1189: (define_insn "umodhi3"
1190: [(set (match_operand:HI 0 "general_operand" "=d")
1191: (umod:HI (match_operand:HI 1 "general_operand" "0")
1192: (match_operand:HI 2 "general_operand" "dmi")))]
1193: ""
1194: "andl #0xFFFF,%0\;divu %2,%0\;swap %0")
1195:
1196: (define_insn "umodhisi3"
1197: [(set (match_operand:HI 0 "general_operand" "=d")
1198: (umod:HI (match_operand:SI 1 "general_operand" "0")
1199: (match_operand:HI 2 "general_operand" "dmi")))]
1200: ""
1201: "divu %2,%0\;swap %0")
1202:
1203: (define_insn "divmodsi4"
1204: [(set (match_operand:SI 0 "general_operand" "=d")
1205: (div:SI (match_operand:SI 1 "general_operand" "0")
1206: (match_operand:SI 2 "general_operand" "dmsK")))
1207: (set (match_operand:SI 3 "general_operand" "=d")
1208: (mod:SI (match_dup 1) (match_dup 2)))]
1209: "TARGET_68020"
1210: "divsll %2,%3:%0")
1211:
1212: (define_insn "udivmodsi4"
1213: [(set (match_operand:SI 0 "general_operand" "=d")
1214: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1215: (match_operand:SI 2 "general_operand" "dmsK")))
1216: (set (match_operand:SI 3 "general_operand" "=d")
1217: (umod:SI (match_dup 1) (match_dup 2)))]
1218: "TARGET_68020"
1219: "divull %2,%3:%0")
1220:
1221: ;;- and instructions
1222: ;;- A composite of the and, & andi m68000 op codes.
1223:
1224: ;; First, recognize a subcase of andsi that can usually be optimized.
1225: ;; Doing this with the main pattern for andsi would require a new
1226: ;; register-class letter for negative constants
1227: ;; and that's not worth adding for one use.
1228: (define_insn ""
1229: [(set (match_operand:SI 0 "general_operand" "=%md")
1230: (and:SI (match_operand:SI 1 "general_operand" "0")
1231: (match_operand:SI 2 "general_operand" "i")))]
1232: "(GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) | 0xffff) == 0xffffffff)
1233: || (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) | 0xffff) == 0xffffffff)"
1234: "*
1235: {
1236: if (DATA_REG_P (operands[0])
1237: || offsetable_address_p (operands[0]))
1238: {
1239: if (GET_CODE (operands[0]) != REG)
1240: operands[0] = adj_offsetable_operand (operands[0], 2);
1241: return \"andw %2,%0\";
1242: }
1243: return \"andl %2,%0\";
1244: }")
1245:
1246: (define_insn "andsi3"
1247: [(set (match_operand:SI 0 "general_operand" "=%m,d")
1248: (and:SI (match_operand:SI 1 "general_operand" "0,0")
1249: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1250: ""
1251: "*
1252: {
1253: if (GET_CODE (operands[2]) == CONST_INT
1254: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
1255: && (DATA_REG_P (operands[0])
1256: || offsetable_address_p (operands[0])))
1257: {
1258: if (GET_CODE (operands[0]) != REG)
1259: operands[0] = adj_offsetable_operand (operands[0], 2);
1260: return \"andw %2,%0\";
1261: }
1262: return \"andl %2,%0\";
1263: }")
1264:
1265: (define_insn "andhi3"
1266: [(set (match_operand:HI 0 "general_operand" "=%m,d")
1267: (and:HI (match_operand:HI 1 "general_operand" "0,0")
1268: (match_operand:HI 2 "general_operand" "di,dmi")))]
1269: ""
1270: "andw %2,%0")
1271:
1272: (define_insn "andqi3"
1273: [(set (match_operand:QI 0 "general_operand" "=%m,d")
1274: (and:QI (match_operand:QI 1 "general_operand" "0,0")
1275: (match_operand:QI 2 "general_operand" "di,dmi")))]
1276: ""
1277: "andb %2,%0")
1278:
1279: ;;- Bit set (inclusive or) instructions
1280: ;;- A composite of the or, & ori m68000 op codes.
1281: (define_insn "iorsi3"
1282: [(set (match_operand:SI 0 "general_operand" "=%m,d")
1283: (ior:SI (match_operand:SI 1 "general_operand" "0,0")
1284: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1285: ""
1286: "*
1287: {
1288: register int logval;
1289: if (GET_CODE (operands[2]) == CONST_INT
1290: && INTVAL (operands[2]) >> 16 == 0
1291: && (DATA_REG_P (operands[0])
1292: || offsetable_address_p (operands[0])))
1293: {
1294: if (GET_CODE (operands[0]) != REG)
1295: operands[0] = adj_offsetable_operand (operands[0], 2);
1296: return \"orw %2,%0\";
1297: }
1298: if (GET_CODE (operands[2]) == CONST_INT
1299: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
1300: && (DATA_REG_P (operands[0])
1301: || offsetable_address_p (operands[0])))
1302: {
1303: if (DATA_REG_P (operands[0]))
1304: {
1305: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
1306: }
1307: else
1308: {
1309: operands[0] = adj_offsetable_operand (operands[0], 3 - (logval / 8));
1310: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
1311: }
1312: return \"bset %1,%0\";
1313: }
1314: return \"orl %2,%0\";
1315: }")
1316:
1317: (define_insn "iorhi3"
1318: [(set (match_operand:HI 0 "general_operand" "=%m,d")
1319: (ior:HI (match_operand:HI 1 "general_operand" "0,0")
1320: (match_operand:HI 2 "general_operand" "di,dmi")))]
1321: ""
1322: "orw %2,%0")
1323:
1324: (define_insn "iorqi3"
1325: [(set (match_operand:QI 0 "general_operand" "=%m,d")
1326: (ior:QI (match_operand:QI 1 "general_operand" "0,0")
1327: (match_operand:QI 2 "general_operand" "di,dmi")))]
1328: ""
1329: "orb %2,%0")
1330:
1331: ;;- xor instructions
1332: ;;- A composite of the eor, & eori m68000 op codes.
1333: (define_insn "xorsi3"
1334: [(set (match_operand:SI 0 "general_operand" "=%dm")
1335: (xor:SI (match_operand:SI 1 "general_operand" "0")
1336: (match_operand:SI 2 "general_operand" "dKs")))]
1337: ""
1338: "*
1339: {
1340: if (GET_CODE (operands[2]) == CONST_INT
1341: && INTVAL (operands[2]) >> 16 == 0
1342: && offsetable_address_p (operands[0]))
1343: {
1344: operands[0] = adj_offsetable_operand (operands[0], 2);
1345: return \"eorw %2,%0\";
1346: }
1347: return \"eorl %2,%0\";
1348: }")
1349:
1350: (define_insn "xorhi3"
1351: [(set (match_operand:HI 0 "general_operand" "=%dm")
1352: (xor:HI (match_operand:HI 1 "general_operand" "0")
1353: (match_operand:HI 2 "general_operand" "di")))]
1354: ""
1355: "eorw %2,%0")
1356:
1357: (define_insn "xorqi3"
1358: [(set (match_operand:QI 0 "general_operand" "=%dm")
1359: (xor:QI (match_operand:QI 1 "general_operand" "0")
1360: (match_operand:QI 2 "general_operand" "di")))]
1361: ""
1362: "eorb %2,%0")
1363:
1364: ;;- negation instructions
1365: (define_insn "negsi2"
1366: [(set (match_operand:SI 0 "general_operand" "=dm")
1367: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1368: ""
1369: "negl %0")
1370:
1371: (define_insn "neghi2"
1372: [(set (match_operand:HI 0 "general_operand" "=dm")
1373: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1374: ""
1375: "negw %0")
1376:
1377: (define_insn "negqi2"
1378: [(set (match_operand:QI 0 "general_operand" "=dm")
1379: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1380: ""
1381: "negb %0")
1382:
1383: (define_insn "negsf2"
1384: [(set (match_operand:SF 0 "general_operand" "=f")
1385: (neg:SF (match_operand:SF 1 "general_operand" "fdm")))]
1386: "TARGET_68881"
1387: "*
1388: {
1389: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
1390: return \"fnegx %1,%0\";
1391: return \"fnegs %1,%0\";
1392: }")
1393:
1394: (define_insn "negdf2"
1395: [(set (match_operand:DF 0 "general_operand" "=f")
1396: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1397: "TARGET_68881"
1398: "*
1399: {
1400: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
1401: return \"fnegx %1,%0\";
1402: return \"fnegd %1,%0\";
1403: }")
1404:
1405: ;; Absolute value instructions
1406:
1407: (define_insn "abssf2"
1408: [(set (match_operand:SF 0 "general_operand" "=f")
1409: (abs:SF (match_operand:SF 1 "general_operand" "fdm")))]
1410: "TARGET_68881"
1411: "*
1412: {
1413: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
1414: return \"fabsx %1,%0\";
1415: return \"fabss %1,%0\";
1416: }")
1417:
1418: (define_insn "absdf2"
1419: [(set (match_operand:DF 0 "general_operand" "=f")
1420: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
1421: "TARGET_68881"
1422: "*
1423: {
1424: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
1425: return \"fabsx %1,%0\";
1426: return \"fabsd %1,%0\";
1427: }")
1428:
1429: ;;- one complement instructions
1430: (define_insn "one_cmplsi2"
1431: [(set (match_operand:SI 0 "general_operand" "=dm")
1432: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1433: ""
1434: "notl %0")
1435:
1436: (define_insn "one_cmplhi2"
1437: [(set (match_operand:HI 0 "general_operand" "=dm")
1438: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1439: ""
1440: "notw %0")
1441:
1442: (define_insn "one_cmplqi2"
1443: [(set (match_operand:QI 0 "general_operand" "=dm")
1444: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1445: ""
1446: "notb %0")
1447:
1448: ;; Optimized special case of shifting.
1449: ;; Must precede the general case.
1450:
1451: (define_insn ""
1452: [(set (match_operand:SI 0 "general_operand" "=d")
1453: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1454: (const_int 24)))]
1455: ""
1456: "*
1457: {
1458: if (TARGET_68020)
1459: return \"movb %1,%0\;extbl %0\";
1460: return \"movb %1,%0\;extw %0\;extl %0\";
1461: }")
1462:
1463: (define_insn ""
1464: [(set (match_operand:SI 0 "general_operand" "=d")
1465: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1466: (const_int 24)))]
1467: ""
1468: "*
1469: {
1470: if (reg_mentioned_p (operands[0], operands[1]))
1471: return \"movb %1,%0\;andl #0xFF,%0\";
1472: return \"clrl %0\;movb %1,%0\";
1473: }")
1474:
1475: (define_insn ""
1476: [(set (cc0) (minus (match_operand:QI 0 "general_operand" "i")
1477: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1478: (const_int 24))))]
1479: "(GET_CODE (operands[0]) == CONST_INT
1480: && (INTVAL (operands[0]) & ~0xff) == 0)"
1481: "* cc_status.flags |= CC_REVERSED; return \"cmpb %0,%1\"; ")
1482:
1483: (define_insn ""
1484: [(set (cc0) (minus (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1485: (const_int 24))
1486: (match_operand:QI 1 "general_operand" "i")))]
1487: "(GET_CODE (operands[1]) == CONST_INT
1488: && (INTVAL (operands[1]) & ~0xff) == 0)"
1489: "cmpb %1,%0")
1490:
1491: (define_insn ""
1492: [(set (cc0) (minus (match_operand:QI 0 "general_operand" "i")
1493: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1494: (const_int 24))))]
1495: "(GET_CODE (operands[0]) == CONST_INT
1496: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
1497: "* cc_status.flags |= CC_REVERSED; return \"cmpb %0,%1\"; ")
1498:
1499: (define_insn ""
1500: [(set (cc0) (minus (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1501: (const_int 24))
1502: (match_operand:QI 1 "general_operand" "i")))]
1503: "(GET_CODE (operands[1]) == CONST_INT
1504: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
1505: "cmpb %1,%0")
1506:
1507: ;;- arithmetic shift instructions
1508: ;;- don't need the shift memory by 1 bit instruction
1509: (define_insn "ashlsi3"
1510: [(set (match_operand:SI 0 "general_operand" "=d")
1511: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1512: (match_operand:SI 2 "general_operand" "dI")))]
1513: ""
1514: "asll %2,%0")
1515:
1516: (define_insn "ashlhi3"
1517: [(set (match_operand:HI 0 "general_operand" "=d")
1518: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1519: (match_operand:HI 2 "general_operand" "dI")))]
1520: ""
1521: "aslw %2,%0")
1522:
1523: (define_insn "ashlqi3"
1524: [(set (match_operand:QI 0 "general_operand" "=d")
1525: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1526: (match_operand:QI 2 "general_operand" "dI")))]
1527: ""
1528: "aslb %2,%0")
1529:
1530: (define_insn "ashrsi3"
1531: [(set (match_operand:SI 0 "general_operand" "=d")
1532: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1533: (match_operand:SI 2 "general_operand" "dI")))]
1534: ""
1535: "asrl %2,%0")
1536:
1537: (define_insn "ashrhi3"
1538: [(set (match_operand:HI 0 "general_operand" "=d")
1539: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1540: (match_operand:HI 2 "general_operand" "dI")))]
1541: ""
1542: "asrw %2,%0")
1543:
1544: (define_insn "ashrqi3"
1545: [(set (match_operand:QI 0 "general_operand" "=d")
1546: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1547: (match_operand:QI 2 "general_operand" "dI")))]
1548: ""
1549: "asrb %2,%0")
1550:
1551: ;;- logical shift instructions
1552: ;;- don't need the shift memory by 1 bit instruction
1553: (define_insn "lshlsi3"
1554: [(set (match_operand:SI 0 "general_operand" "=d")
1555: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1556: (match_operand:SI 2 "general_operand" "dI")))]
1557: ""
1558: "lsll %2,%0")
1559:
1560: (define_insn "lshlhi3"
1561: [(set (match_operand:HI 0 "general_operand" "=d")
1562: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1563: (match_operand:HI 2 "general_operand" "dI")))]
1564: ""
1565: "lslw %2,%0")
1566:
1567: (define_insn "lshlqi3"
1568: [(set (match_operand:QI 0 "general_operand" "=d")
1569: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1570: (match_operand:QI 2 "general_operand" "dI")))]
1571: ""
1572: "lslb %2,%0")
1573:
1574: (define_insn "lshrsi3"
1575: [(set (match_operand:SI 0 "general_operand" "=d")
1576: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1577: (match_operand:SI 2 "general_operand" "dI")))]
1578: ""
1579: "lsrl %2,%0")
1580:
1581: (define_insn "lshrhi3"
1582: [(set (match_operand:HI 0 "general_operand" "=d")
1583: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1584: (match_operand:HI 2 "general_operand" "dI")))]
1585: ""
1586: "lsrw %2,%0")
1587:
1588: (define_insn "lshrqi3"
1589: [(set (match_operand:QI 0 "general_operand" "=d")
1590: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1591: (match_operand:QI 2 "general_operand" "dI")))]
1592: ""
1593: "lsrb %2,%0")
1594:
1595: ;;- rotate instructions
1596: ;;- don't need the shift memory by 1 bit instruction
1597:
1598: (define_insn "rotlsi3"
1599: [(set (match_operand:SI 0 "general_operand" "=d")
1600: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1601: (match_operand:SI 2 "general_operand" "dI")))]
1602: ""
1603: "roll %2,%0")
1604:
1605: (define_insn "rotlhi3"
1606: [(set (match_operand:HI 0 "general_operand" "=d")
1607: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1608: (match_operand:HI 2 "general_operand" "dI")))]
1609: ""
1610: "rolw %2,%0")
1611:
1612: (define_insn "rotlqi3"
1613: [(set (match_operand:QI 0 "general_operand" "=d")
1614: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1615: (match_operand:QI 2 "general_operand" "dI")))]
1616: ""
1617: "rolb %2,%0")
1618:
1619: (define_insn "rotrsi3"
1620: [(set (match_operand:SI 0 "general_operand" "=d")
1621: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1622: (match_operand:SI 2 "general_operand" "dI")))]
1623: ""
1624: "rorl %2,%0")
1625:
1626: (define_insn "rotrhi3"
1627: [(set (match_operand:HI 0 "general_operand" "=d")
1628: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1629: (match_operand:HI 2 "general_operand" "dI")))]
1630: ""
1631: "rorw %2,%0")
1632:
1633: (define_insn "rotrqi3"
1634: [(set (match_operand:QI 0 "general_operand" "=d")
1635: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1636: (match_operand:QI 2 "general_operand" "dI")))]
1637: ""
1638: "rorb %2,%0")
1639:
1640: ;; Bit field instructions.
1641:
1642: (define_insn "extv"
1643: [(set (match_operand:SI 0 "general_operand" "=d")
1644: (sign_extract:SI (match_operand:QI 1 "general_operand" "dm")
1645: (match_operand:SI 2 "general_operand" "di")
1646: (match_operand:SI 3 "general_operand" "di")))]
1647: "TARGET_68020 && TARGET_BITFIELD"
1648: "bfexts %1{%3:%2},%0")
1649:
1650: (define_insn "extzv"
1651: [(set (match_operand:SI 0 "general_operand" "=d")
1652: (zero_extract:SI (match_operand:QI 1 "general_operand" "dm")
1653: (match_operand:SI 2 "general_operand" "di")
1654: (match_operand:SI 3 "general_operand" "di")))]
1655: "TARGET_68020 && TARGET_BITFIELD"
1656: "bfextu %1{%3:%2},%0")
1657:
1658: (define_insn ""
1659: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+dm")
1660: (match_operand:SI 1 "general_operand" "di")
1661: (match_operand:SI 2 "general_operand" "di"))
1662: (const_int 0))]
1663: "TARGET_68020 && TARGET_BITFIELD"
1664: "bfclr %0{%2:%1}")
1665:
1666: (define_insn ""
1667: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+dm")
1668: (match_operand:SI 1 "general_operand" "di")
1669: (match_operand:SI 2 "general_operand" "di"))
1670: (const_int -1))]
1671: "TARGET_68020 && TARGET_BITFIELD"
1672: "bfset %0{%2:%1}")
1673:
1674: ;; double d in "+ddm" increases pressure to put operand 0 in data reg.
1675: (define_insn "insv"
1676: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+ddm")
1677: (match_operand:SI 1 "general_operand" "di")
1678: (match_operand:SI 2 "general_operand" "di"))
1679: (match_operand:SI 3 "general_operand" "d"))]
1680: "TARGET_68020 && TARGET_BITFIELD"
1681: "bfins %3,%0{%2:%1}")
1682:
1683: ;; Now recognize bit field insns that operate on registers
1684: ;; (or at least were intended to do so).
1685:
1686: (define_insn ""
1687: [(set (match_operand:SI 0 "general_operand" "=d")
1688: (sign_extract:SI (match_operand:SI 1 "general_operand" "d")
1689: (match_operand:SI 2 "general_operand" "di")
1690: (match_operand:SI 3 "general_operand" "di")))]
1691: "TARGET_68020 && TARGET_BITFIELD"
1692: "bfexts %1{%3:%2},%0")
1693:
1694: (define_insn ""
1695: [(set (match_operand:SI 0 "general_operand" "=d")
1696: (zero_extract:SI (match_operand:SI 1 "general_operand" "d")
1697: (match_operand:SI 2 "general_operand" "di")
1698: (match_operand:SI 3 "general_operand" "di")))]
1699: "TARGET_68020 && TARGET_BITFIELD"
1700: "bfextu %1{%3:%2},%0")
1701:
1702: (define_insn ""
1703: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d")
1704: (match_operand:SI 1 "general_operand" "di")
1705: (match_operand:SI 2 "general_operand" "di"))
1706: (const_int 0))]
1707: "TARGET_68020 && TARGET_BITFIELD"
1708: "bfclr %0{%2:%1}")
1709:
1710: (define_insn ""
1711: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d")
1712: (match_operand:SI 1 "general_operand" "di")
1713: (match_operand:SI 2 "general_operand" "di"))
1714: (const_int -1))]
1715: "TARGET_68020 && TARGET_BITFIELD"
1716: "bfset %0{%2:%1}")
1717:
1718: ;; double d in "+ddm" increases pressure to put operand 0 in data reg.
1719: (define_insn ""
1720: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d")
1721: (match_operand:SI 1 "general_operand" "di")
1722: (match_operand:SI 2 "general_operand" "di"))
1723: (match_operand:SI 3 "general_operand" "d"))]
1724: "TARGET_68020 && TARGET_BITFIELD"
1725: "*
1726: {
1727: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
1728: && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
1729: return \"movw %3,%0\";
1730: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
1731: && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
1732: return \"movb %3,%0\";
1733: return \"bfins %3,%0{%2:%1}\";
1734: }")
1735:
1736: ;; Special patterns for optimizing bit-field instructions.
1737:
1738: (define_insn ""
1739: [(set (cc0)
1740: (zero_extract:SI (match_operand:QI 0 "general_operand" "dm")
1741: (match_operand:SI 1 "general_operand" "di")
1742: (match_operand:SI 2 "general_operand" "di")))]
1743: "TARGET_68020 && TARGET_BITFIELD
1744: && GET_CODE (operands[1]) == CONST_INT"
1745: "*
1746: {
1747: if (operands[1] == const1_rtx
1748: && GET_CODE (operands[2]) == CONST_INT)
1749: {
1750: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
1751: return output_btst (operands,
1752: gen_rtx (CONST_INT, VOIDmode,
1753: width - INTVAL (operands[2])),
1754: operands[0],
1755: insn, 1000);
1756: /* Pass 1000 as SIGNPOS argument so that btst will
1757: not think we are testing the sign bit for an `and'
1758: and assume that nonzero implies a negative result. */
1759: }
1760: if (INTVAL (operands[1]) != 32)
1761: cc_status.flags = CC_NOT_NEGATIVE;
1762: return \"bftst %0{%2:%1}\";
1763: }")
1764:
1765: (define_insn ""
1766: [(set (cc0)
1767: (subreg:QI
1768: (zero_extract:SI (match_operand:QI 0 "general_operand" "dm")
1769: (match_operand:SI 1 "general_operand" "di")
1770: (match_operand:SI 2 "general_operand" "di"))
1771: 0))]
1772: "TARGET_68020 && TARGET_BITFIELD
1773: && GET_CODE (operands[1]) == CONST_INT"
1774: "*
1775: {
1776: if (operands[1] == const1_rtx
1777: && GET_CODE (operands[2]) == CONST_INT)
1778: {
1779: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
1780: return output_btst (operands,
1781: gen_rtx (CONST_INT, VOIDmode,
1782: width - INTVAL (operands[2])),
1783: operands[0],
1784: insn, 1000);
1785: /* Pass 1000 as SIGNPOS argument so that btst will
1786: not think we are testing the sign bit for an `and'
1787: and assume that nonzero implies a negative result. */
1788: }
1789: if (INTVAL (operands[1]) != 32)
1790: cc_status.flags = CC_NOT_NEGATIVE;
1791: return \"bftst %0{%2:%1}\";
1792: }")
1793:
1794: (define_insn ""
1795: [(set (cc0)
1796: (subreg:HI
1797: (zero_extract:SI (match_operand:QI 0 "general_operand" "dm")
1798: (match_operand:SI 1 "general_operand" "di")
1799: (match_operand:SI 2 "general_operand" "di"))
1800: 0))]
1801: "TARGET_68020 && TARGET_BITFIELD
1802: && GET_CODE (operands[1]) == CONST_INT"
1803: "*
1804: {
1805: if (operands[1] == const1_rtx
1806: && GET_CODE (operands[2]) == CONST_INT)
1807: {
1808: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
1809: return output_btst (operands,
1810: gen_rtx (CONST_INT, VOIDmode,
1811: width - INTVAL (operands[2])),
1812: operands[0],
1813: insn, 1000);
1814: /* Pass 1000 as SIGNPOS argument so that btst will
1815: not think we are testing the sign bit for an `and'
1816: and assume that nonzero implies a negative result. */
1817: }
1818: if (INTVAL (operands[1]) != 32)
1819: cc_status.flags = CC_NOT_NEGATIVE;
1820: return \"bftst %0{%2:%1}\";
1821: }")
1822:
1823:
1824: (define_insn "seqsi"
1825: [(set (match_operand:SI 0 "general_operand" "=d")
1826: (eq (cc0) (const_int 0)))]
1827: ""
1828: "* OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); ")
1829:
1830: (define_insn "snesi"
1831: [(set (match_operand:SI 0 "general_operand" "=d")
1832: (ne (cc0) (const_int 0)))]
1833: ""
1834: "* OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); ")
1835:
1836: (define_insn "sgtsi"
1837: [(set (match_operand:SI 0 "general_operand" "=d")
1838: (gt (cc0) (const_int 0)))]
1839: ""
1840: "* OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", \"andb #0xc,cc\;sgt %0\"); ")
1841:
1842: (define_insn "sgtusi"
1843: [(set (match_operand:SI 0 "general_operand" "=d")
1844: (gtu (cc0) (const_int 0)))]
1845: ""
1846: "shi %0")
1847:
1848: (define_insn "sltsi"
1849: [(set (match_operand:SI 0 "general_operand" "=d")
1850: (lt (cc0) (const_int 0)))]
1851: ""
1852: "* OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
1853:
1854: (define_insn "sltusi"
1855: [(set (match_operand:SI 0 "general_operand" "=d")
1856: (ltu (cc0) (const_int 0)))]
1857: ""
1858: "scs %0")
1859:
1860: (define_insn "sgesi"
1861: [(set (match_operand:SI 0 "general_operand" "=d")
1862: (ge (cc0) (const_int 0)))]
1863: ""
1864: "* OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
1865:
1866: (define_insn "sgeusi"
1867: [(set (match_operand:SI 0 "general_operand" "=d")
1868: (geu (cc0) (const_int 0)))]
1869: ""
1870: "scc %0")
1871:
1872: (define_insn "slesi"
1873: [(set (match_operand:SI 0 "general_operand" "=d")
1874: (le (cc0) (const_int 0)))]
1875: ""
1876: "* OUTPUT_JUMP (\"sle %0\", \"fsle %0\", \"andb #0xc,cc\;sle %0\"); ")
1877:
1878: (define_insn "sleusi"
1879: [(set (match_operand:SI 0 "general_operand" "=d")
1880: (leu (cc0) (const_int 0)))]
1881: ""
1882: "sls %0")
1883:
1884: ;; Basic conditional jump instructions.
1885:
1886: (define_insn "beq"
1887: [(set (pc)
1888: (if_then_else (eq (cc0)
1889: (const_int 0))
1890: (label_ref (match_operand 0 "" ""))
1891: (pc)))]
1892: ""
1893: "*
1894: {
1895: if (cc_status.flags & CC_Z_IN_NOT_N)
1896: return \"jpl %l0\";
1897: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
1898: }")
1899:
1900: (define_insn "bne"
1901: [(set (pc)
1902: (if_then_else (ne (cc0)
1903: (const_int 0))
1904: (label_ref (match_operand 0 "" ""))
1905: (pc)))]
1906: ""
1907: "*
1908: {
1909: if (cc_status.flags & CC_Z_IN_NOT_N)
1910: return \"jmi %l0\";
1911: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
1912: }")
1913:
1914: (define_insn "bgt"
1915: [(set (pc)
1916: (if_then_else (gt (cc0)
1917: (const_int 0))
1918: (label_ref (match_operand 0 "" ""))
1919: (pc)))]
1920: ""
1921: "* OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", \"andb #0xc,cc\;jgt %l0\"); ")
1922:
1923: (define_insn "bgtu"
1924: [(set (pc)
1925: (if_then_else (gtu (cc0)
1926: (const_int 0))
1927: (label_ref (match_operand 0 "" ""))
1928: (pc)))]
1929: ""
1930: "jhi %l0")
1931:
1932: (define_insn "blt"
1933: [(set (pc)
1934: (if_then_else (lt (cc0)
1935: (const_int 0))
1936: (label_ref (match_operand 0 "" ""))
1937: (pc)))]
1938: ""
1939: "* OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); ")
1940:
1941: (define_insn "bltu"
1942: [(set (pc)
1943: (if_then_else (ltu (cc0)
1944: (const_int 0))
1945: (label_ref (match_operand 0 "" ""))
1946: (pc)))]
1947: ""
1948: "jcs %l0")
1949:
1950: (define_insn "bge"
1951: [(set (pc)
1952: (if_then_else (ge (cc0)
1953: (const_int 0))
1954: (label_ref (match_operand 0 "" ""))
1955: (pc)))]
1956: ""
1957: "* OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); ")
1958:
1959: (define_insn "bgeu"
1960: [(set (pc)
1961: (if_then_else (geu (cc0)
1962: (const_int 0))
1963: (label_ref (match_operand 0 "" ""))
1964: (pc)))]
1965: ""
1966: "jcc %l0")
1967:
1968: (define_insn "ble"
1969: [(set (pc)
1970: (if_then_else (le (cc0)
1971: (const_int 0))
1972: (label_ref (match_operand 0 "" ""))
1973: (pc)))]
1974: ""
1975: "* OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", \"andb #0xc,cc\;jle %l0\"); ")
1976:
1977: (define_insn "bleu"
1978: [(set (pc)
1979: (if_then_else (leu (cc0)
1980: (const_int 0))
1981: (label_ref (match_operand 0 "" ""))
1982: (pc)))]
1983: ""
1984: "jls %l0")
1985:
1986: ;; Negated conditional jump instructions.
1987:
1988: (define_insn ""
1989: [(set (pc)
1990: (if_then_else (eq (cc0)
1991: (const_int 0))
1992: (pc)
1993: (label_ref (match_operand 0 "" ""))))]
1994: ""
1995: "*
1996: {
1997: if (cc_status.flags & CC_Z_IN_NOT_N)
1998: return \"jmi %l0\";
1999: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
2000: }")
2001:
2002: (define_insn ""
2003: [(set (pc)
2004: (if_then_else (ne (cc0)
2005: (const_int 0))
2006: (pc)
2007: (label_ref (match_operand 0 "" ""))))]
2008: ""
2009: "*
2010: {
2011: if (cc_status.flags & CC_Z_IN_NOT_N)
2012: return \"jpl %l0\";
2013: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
2014: }")
2015:
2016: (define_insn ""
2017: [(set (pc)
2018: (if_then_else (gt (cc0)
2019: (const_int 0))
2020: (pc)
2021: (label_ref (match_operand 0 "" ""))))]
2022: ""
2023: "* OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", \"andb #0xc,cc\;jle %l0\"); ")
2024:
2025: (define_insn ""
2026: [(set (pc)
2027: (if_then_else (gtu (cc0)
2028: (const_int 0))
2029: (pc)
2030: (label_ref (match_operand 0 "" ""))))]
2031: ""
2032: "jls %l0")
2033:
2034: (define_insn ""
2035: [(set (pc)
2036: (if_then_else (lt (cc0)
2037: (const_int 0))
2038: (pc)
2039: (label_ref (match_operand 0 "" ""))))]
2040: ""
2041: "* OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); ")
2042:
2043: (define_insn ""
2044: [(set (pc)
2045: (if_then_else (ltu (cc0)
2046: (const_int 0))
2047: (pc)
2048: (label_ref (match_operand 0 "" ""))))]
2049: ""
2050: "jcc %l0")
2051:
2052: (define_insn ""
2053: [(set (pc)
2054: (if_then_else (ge (cc0)
2055: (const_int 0))
2056: (pc)
2057: (label_ref (match_operand 0 "" ""))))]
2058: ""
2059: "* OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); ")
2060:
2061: (define_insn ""
2062: [(set (pc)
2063: (if_then_else (geu (cc0)
2064: (const_int 0))
2065: (pc)
2066: (label_ref (match_operand 0 "" ""))))]
2067: ""
2068: "jcs %l0")
2069:
2070: (define_insn ""
2071: [(set (pc)
2072: (if_then_else (le (cc0)
2073: (const_int 0))
2074: (pc)
2075: (label_ref (match_operand 0 "" ""))))]
2076: ""
2077: "* OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", \"andb #0xc,cc\;jgt %l0\"); ")
2078:
2079: (define_insn ""
2080: [(set (pc)
2081: (if_then_else (leu (cc0)
2082: (const_int 0))
2083: (pc)
2084: (label_ref (match_operand 0 "" ""))))]
2085: ""
2086: "jhi %l0")
2087:
2088: ;; Unconditional and other jump instructions
2089: (define_insn "jump"
2090: [(set (pc)
2091: (label_ref (match_operand 0 "" "")))]
2092: ""
2093: "jra %l0")
2094:
2095: (define_insn "tablejump"
2096: [(set (pc)
2097: (plus:SI (pc) (match_operand:HI 0 "general_operand" "r")))]
2098: ""
2099: "jmp pc@(2,%0:w)")
2100:
2101: (define_insn ""
2102: [(set (pc)
2103: (if_then_else
2104: (ne (minus (minus:HI (match_operand:HI 0 "general_operand" "g")
2105: (const_int 1))
2106: (const_int -1))
2107: (const_int 0))
2108: (label_ref (match_operand 1 "" "g"))
2109: (pc)))
2110: (set (match_dup 0)
2111: (minus:HI (match_dup 0)
2112: (const_int 1)))]
2113: ""
2114: "*
2115: {
2116: if (DATA_REG_P (operands[0]))
2117: return \"jdbra %0,%l1\";
2118: return \"subqw #1,%0\;cmpw #-1,%0\;jne %l1\";
2119: }")
2120:
2121: (define_insn ""
2122: [(set (pc)
2123: (if_then_else
2124: (ne (minus (const_int -1)
2125: (minus:SI (match_operand:SI 0 "general_operand" "g")
2126: (const_int 1)))
2127: (const_int 0))
2128: (label_ref (match_operand 1 "" "g"))
2129: (pc)))
2130: (set (match_dup 0)
2131: (minus:SI (match_dup 0)
2132: (const_int 1)))]
2133: ""
2134: "*
2135: {
2136: if (DATA_REG_P (operands[0]))
2137: return \"jdbra %0,%l1\;clrw %0\;subql #1,%0\;cmpl #-1,%0\;jne %l1\";
2138: return \"subql #1,%0\;cmpl #-1,%0\;jne %l1\";
2139: }")
2140:
2141: ;;- jump to subroutine
2142: (define_insn "call"
2143: [(call (match_operand:QI 0 "general_operand" "m")
2144: (match_operand:SI 1 "general_operand" "g"))]
2145: ;;- Don't use operand 1 for the m68000.
2146: ""
2147: "jbsr %0")
2148:
2149: (define_insn "return"
2150: [(return)]
2151: ""
2152: "rts")
2153:
2154: ;;- Local variables:
2155: ;;- mode:emacs-lisp
2156: ;;- comment-start: ";;- "
2157: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2158: ;;- eval: (modify-syntax-entry ?[ "(]")
2159: ;;- eval: (modify-syntax-entry ?] ")[")
2160: ;;- eval: (modify-syntax-entry ?{ "(}")
2161: ;;- eval: (modify-syntax-entry ?} "){")
2162: ;;- End:
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