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1.1 root 1: @c Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc.
2: @c This is part of the GCC manual.
3: @c For copying conditions, see the file gcc.texi.
4:
5: @ifset INTERNALS
6: @node Machine Desc, Machine Macros, RTL, Top
7: @chapter Machine Descriptions
8: @cindex machine descriptions
9:
10: A machine description has two parts: a file of instruction patterns
11: (@file{.md} file) and a C header file of macro definitions.
12:
13: The @file{.md} file for a target machine contains a pattern for each
14: instruction that the target machine supports (or at least each instruction
15: that is worth telling the compiler about). It may also contain comments.
16: A semicolon causes the rest of the line to be a comment, unless the semicolon
17: is inside a quoted string.
18:
19: See the next chapter for information on the C header file.
20:
21: @menu
22: * Patterns:: How to write instruction patterns.
23: * Example:: An explained example of a @code{define_insn} pattern.
24: * RTL Template:: The RTL template defines what insns match a pattern.
25: * Output Template:: The output template says how to make assembler code
26: from such an insn.
27: * Output Statement:: For more generality, write C code to output
28: the assembler code.
29: * Constraints:: When not all operands are general operands.
30: * Standard Names:: Names mark patterns to use for code generation.
31: * Pattern Ordering:: When the order of patterns makes a difference.
32: * Dependent Patterns:: Having one pattern may make you need another.
33: * Jump Patterns:: Special considerations for patterns for jump insns.
34: * Insn Canonicalizations::Canonicalization of Instructions
35: * Peephole Definitions::Defining machine-specific peephole optimizations.
36: * Expander Definitions::Generating a sequence of several RTL insns
37: for a standard operation.
38: * Insn Splitting:: Splitting Instructions into Multiple Instructions
39: * Insn Attributes:: Specifying the value of attributes for generated insns.
40: @end menu
41:
42: @node Patterns, Example, Machine Desc, Machine Desc
43: @section Everything about Instruction Patterns
44: @cindex patterns
45: @cindex instruction patterns
46:
47: @findex define_insn
48: Each instruction pattern contains an incomplete RTL expression, with pieces
49: to be filled in later, operand constraints that restrict how the pieces can
50: be filled in, and an output pattern or C code to generate the assembler
51: output, all wrapped up in a @code{define_insn} expression.
52:
53: A @code{define_insn} is an RTL expression containing four or five operands:
54:
55: @enumerate
56: @item
57: An optional name. The presence of a name indicate that this instruction
58: pattern can perform a certain standard job for the RTL-generation
59: pass of the compiler. This pass knows certain names and will use
60: the instruction patterns with those names, if the names are defined
61: in the machine description.
62:
63: The absence of a name is indicated by writing an empty string
64: where the name should go. Nameless instruction patterns are never
65: used for generating RTL code, but they may permit several simpler insns
66: to be combined later on.
67:
68: Names that are not thus known and used in RTL-generation have no
69: effect; they are equivalent to no name at all.
70:
71: @item
72: The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
73: RTL expressions which show what the instruction should look like. It is
74: incomplete because it may contain @code{match_operand},
75: @code{match_operator}, and @code{match_dup} expressions that stand for
76: operands of the instruction.
77:
78: If the vector has only one element, that element is the template for the
79: instruction pattern. If the vector has multiple elements, then the
80: instruction pattern is a @code{parallel} expression containing the
81: elements described.
82:
83: @item
84: @cindex pattern conditions
85: @cindex conditions, in patterns
86: A condition. This is a string which contains a C expression that is
87: the final test to decide whether an insn body matches this pattern.
88:
89: @cindex named patterns and conditions
90: For a named pattern, the condition (if present) may not depend on
91: the data in the insn being matched, but only the target-machine-type
92: flags. The compiler needs to test these conditions during
93: initialization in order to learn exactly which named instructions are
94: available in a particular run.
95:
96: @findex operands
97: For nameless patterns, the condition is applied only when matching an
98: individual insn, and only after the insn has matched the pattern's
99: recognition template. The insn's operands may be found in the vector
100: @code{operands}.
101:
102: @item
103: The @dfn{output template}: a string that says how to output matching
104: insns as assembler code. @samp{%} in this string specifies where
105: to substitute the value of an operand. @xref{Output Template}.
106:
107: When simple substitution isn't general enough, you can specify a piece
108: of C code to compute the output. @xref{Output Statement}.
109:
110: @item
111: Optionally, a vector containing the values of attributes for insns matching
112: this pattern. @xref{Insn Attributes}.
113: @end enumerate
114:
115: @node Example, RTL Template, Patterns, Machine Desc
116: @section Example of @code{define_insn}
117: @cindex @code{define_insn} example
118:
119: Here is an actual example of an instruction pattern, for the 68000/68020.
120:
121: @example
122: (define_insn "tstsi"
123: [(set (cc0)
124: (match_operand:SI 0 "general_operand" "rm"))]
125: ""
126: "*
127: @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
128: return \"tstl %0\";
129: return \"cmpl #0,%0\"; @}")
130: @end example
131:
132: This is an instruction that sets the condition codes based on the value of
133: a general operand. It has no condition, so any insn whose RTL description
134: has the form shown may be handled according to this pattern. The name
135: @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
136: pass that, when it is necessary to test such a value, an insn to do so
137: can be constructed using this pattern.
138:
139: The output control string is a piece of C code which chooses which
140: output template to return based on the kind of operand and the specific
141: type of CPU for which code is being generated.
142:
143: @samp{"rm"} is an operand constraint. Its meaning is explained below.
144:
145: @node RTL Template, Output Template, Example, Machine Desc
146: @section RTL Template for Generating and Recognizing Insns
147: @cindex RTL insn template
148: @cindex generating insns
149: @cindex insns, generating
150: @cindex recognizing insns
151: @cindex insns, recognizing
152:
153: The RTL template is used to define which insns match the particular pattern
154: and how to find their operands. For named patterns, the RTL template also
155: says how to construct an insn from specified operands.
156:
157: Construction involves substituting specified operands into a copy of the
158: template. Matching involves determining the values that serve as the
159: operands in the insn being matched. Both of these activities are
160: controlled by special expression types that direct matching and
161: substitution of the operands.
162:
163: @table @code
164: @findex match_operand
165: @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
166: This expression is a placeholder for operand number @var{n} of
167: the insn. When constructing an insn, operand number @var{n}
168: will be substituted at this point. When matching an insn, whatever
169: appears at this position in the insn will be taken as operand
170: number @var{n}; but it must satisfy @var{predicate} or this instruction
171: pattern will not match at all.
172:
173: Operand numbers must be chosen consecutively counting from zero in
174: each instruction pattern. There may be only one @code{match_operand}
175: expression in the pattern for each operand number. Usually operands
176: are numbered in the order of appearance in @code{match_operand}
177: expressions.
178:
179: @var{predicate} is a string that is the name of a C function that accepts two
180: arguments, an expression and a machine mode. During matching, the
181: function will be called with the putative operand as the expression and
182: @var{m} as the mode argument (if @var{m} is not specified,
183: @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
184: any mode). If it returns zero, this instruction pattern fails to match.
185: @var{predicate} may be an empty string; then it means no test is to be done
186: on the operand, so anything which occurs in this position is valid.
187:
188: Most of the time, @var{predicate} will reject modes other than @var{m}---but
189: not always. For example, the predicate @code{address_operand} uses
190: @var{m} as the mode of memory ref that the address should be valid for.
191: Many predicates accept @code{const_int} nodes even though their mode is
192: @code{VOIDmode}.
193:
194: @var{constraint} controls reloading and the choice of the best register
195: class to use for a value, as explained later (@pxref{Constraints}).
196:
197: People are often unclear on the difference between the constraint and the
198: predicate. The predicate helps decide whether a given insn matches the
199: pattern. The constraint plays no role in this decision; instead, it
200: controls various decisions in the case of an insn which does match.
201:
202: @findex general_operand
203: On CISC machines, @var{predicate} is most often @code{"general_operand"}.
204: This function checks that the putative operand is either a constant, a
205: register or a memory reference, and that it is valid for mode @var{m}.
206:
207: @findex register_operand
208: For an operand that must be a register, @var{predicate} should be
209: @code{"register_operand"}. It would be valid to use
210: @code{"general_operand"}, since the reload pass would copy any
211: non-register operands through registers, but this would make GNU CC do
212: extra work, it would prevent invariant operands (such as constant) from
213: being removed from loops, and it would prevent the register allocator
214: from doing the best possible job. On RISC machines, it is usually most
215: efficient to allow @var{predicate} to accept only objects that the
216: constraints allow.
217:
218: @findex immediate_operand
219: For an operand that must be a constant, either use
220: @code{"immediate_operand"} for @var{predicate}, or make the instruction
221: pattern's extra condition require a constant, or both. You cannot
222: expect the constraints to do this work! If the constraints allow only
223: constants, but the predicate allows something else, the compiler will
224: crash when that case arises.
225:
226: @findex match_scratch
227: @item (match_scratch:@var{m} @var{n} @var{constraint})
228: This expression is also a placeholder for operand number @var{n}
229: and indicates that operand must be a @code{scratch} or @code{reg}
230: expression.
231:
232: When matching patterns, this is completely equivalent to
233:
234: @example
235: (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
236: @end example
237:
238: but, when generating RTL, it produces a (@code{scratch}:@var{m})
239: expression.
240:
241: If the last few expressions in a @code{parallel} are @code{clobber}
242: expressions whose operands are either a hard register or
243: @code{match_scratch}, the combiner can add them when necessary.
244: @xref{Side Effects}.
245:
246: @findex match_dup
247: @item (match_dup @var{n})
248: This expression is also a placeholder for operand number @var{n}.
249: It is used when the operand needs to appear more than once in the
250: insn.
251:
252: In construction, @code{match_dup} behaves exactly like
253: @code{match_operand}: the operand is substituted into the insn being
254: constructed. But in matching, @code{match_dup} behaves differently.
255: It assumes that operand number @var{n} has already been determined by
256: a @code{match_operand} appearing earlier in the recognition template,
257: and it matches only an identical-looking expression.
258:
259: @findex match_operator
260: @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
261: This pattern is a kind of placeholder for a variable RTL expression
262: code.
263:
264: When constructing an insn, it stands for an RTL expression whose
265: expression code is taken from that of operand @var{n}, and whose
266: operands are constructed from the patterns @var{operands}.
267:
268: When matching an expression, it matches an expression if the function
269: @var{predicate} returns nonzero on that expression @emph{and} the
270: patterns @var{operands} match the operands of the expression.
271:
272: Suppose that the function @code{commutative_operator} is defined as
273: follows, to match any expression whose operator is one of the
274: commutative arithmetic operators of RTL and whose mode is @var{mode}:
275:
276: @example
277: int
278: commutative_operator (x, mode)
279: rtx x;
280: enum machine_mode mode;
281: @{
282: enum rtx_code code = GET_CODE (x);
283: if (GET_MODE (x) != mode)
284: return 0;
285: return GET_RTX_CLASS (code) == 'c' || code == EQ || code == NE;
286: @}
287: @end example
288:
289: Then the following pattern will match any RTL expression consisting
290: of a commutative operator applied to two general operands:
291:
292: @example
293: (match_operator:SI 3 "commutative_operator"
294: [(match_operand:SI 1 "general_operand" "g")
295: (match_operand:SI 2 "general_operand" "g")])
296: @end example
297:
298: Here the vector @code{[@var{operands}@dots{}]} contains two patterns
299: because the expressions to be matched all contain two operands.
300:
301: When this pattern does match, the two operands of the commutative
302: operator are recorded as operands 1 and 2 of the insn. (This is done
303: by the two instances of @code{match_operand}.) Operand 3 of the insn
304: will be the entire commutative expression: use @code{GET_CODE
305: (operands[3])} to see which commutative operator was used.
306:
307: The machine mode @var{m} of @code{match_operator} works like that of
308: @code{match_operand}: it is passed as the second argument to the
309: predicate function, and that function is solely responsible for
310: deciding whether the expression to be matched ``has'' that mode.
311:
312: When constructing an insn, argument 3 of the gen-function will specify
313: the operation (i.e. the expression code) for the expression to be
314: made. It should be an RTL expression, whose expression code is copied
315: into a new expression whose operands are arguments 1 and 2 of the
316: gen-function. The subexpressions of argument 3 are not used;
317: only its expression code matters.
318:
319: When @code{match_operator} is used in a pattern for matching an insn,
320: it usually best if the operand number of the @code{match_operator}
321: is higher than that of the actual operands of the insn. This improves
322: register allocation because the register allocator often looks at
323: operands 1 and 2 of insns to see if it can do register tying.
324:
325: There is no way to specify constraints in @code{match_operator}. The
326: operand of the insn which corresponds to the @code{match_operator}
327: never has any constraints because it is never reloaded as a whole.
328: However, if parts of its @var{operands} are matched by
329: @code{match_operand} patterns, those parts may have constraints of
330: their own.
331:
332: @findex address
333: @item (address (match_operand:@var{m} @var{n} "address_operand" ""))
334: This complex of expressions is a placeholder for an operand number
335: @var{n} in a ``load address'' instruction: an operand which specifies
336: a memory location in the usual way, but for which the actual operand
337: value used is the address of the location, not the contents of the
338: location.
339:
340: @code{address} expressions never appear in RTL code, only in machine
341: descriptions. And they are used only in machine descriptions that do
342: not use the operand constraint feature. When operand constraints are
343: in use, the letter @samp{p} in the constraint serves this purpose.
344:
345: @var{m} is the machine mode of the @emph{memory location being
346: addressed}, not the machine mode of the address itself. That mode is
347: always the same on a given target machine (it is @code{Pmode}, which
348: normally is @code{SImode}), so there is no point in mentioning it;
349: thus, no machine mode is written in the @code{address} expression. If
350: some day support is added for machines in which addresses of different
351: kinds of objects appear differently or are used differently (such as
352: the PDP-10), different formats would perhaps need different machine
353: modes and these modes might be written in the @code{address}
354: expression.
355: @end table
356:
357: @node Output Template, Output Statement, RTL Template, Machine Desc
358: @section Output Templates and Operand Substitution
359: @cindex output templates
360: @cindex operand substitution
361:
362: @cindex @samp{%} in template
363: @cindex percent sign
364: The @dfn{output template} is a string which specifies how to output the
365: assembler code for an instruction pattern. Most of the template is a
366: fixed string which is output literally. The character @samp{%} is used
367: to specify where to substitute an operand; it can also be used to
368: identify places where different variants of the assembler require
369: different syntax.
370:
371: In the simplest case, a @samp{%} followed by a digit @var{n} says to output
372: operand @var{n} at that point in the string.
373:
374: @samp{%} followed by a letter and a digit says to output an operand in an
375: alternate fashion. Four letters have standard, built-in meanings described
376: below. The machine description macro @code{PRINT_OPERAND} can define
377: additional letters with nonstandard meanings.
378:
379: @samp{%c@var{digit}} can be used to substitute an operand that is a
380: constant value without the syntax that normally indicates an immediate
381: operand.
382:
383: @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
384: the constant is negated before printing.
385:
386: @samp{%a@var{digit}} can be used to substitute an operand as if it were a
387: memory reference, with the actual operand treated as the address. This may
388: be useful when outputting a ``load address'' instruction, because often the
389: assembler syntax for such an instruction requires you to write the operand
390: as if it were a memory reference.
391:
392: @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
393: instruction.
394:
395: @samp{%} followed by a punctuation character specifies a substitution that
396: does not use an operand. Only one case is standard: @samp{%%} outputs a
397: @samp{%} into the assembler code. Other nonstandard cases can be
398: defined in the @code{PRINT_OPERAND} macro. You must also define
399: which punctuation characters are valid with the
400: @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
401:
402: @cindex \
403: @cindex backslash
404: The template may generate multiple assembler instructions. Write the text
405: for the instructions, with @samp{\;} between them.
406:
407: @cindex matching operands
408: When the RTL contains two operands which are required by constraint to match
409: each other, the output template must refer only to the lower-numbered operand.
410: Matching operands are not always identical, and the rest of the compiler
411: arranges to put the proper RTL expression for printing into the lower-numbered
412: operand.
413:
414: One use of nonstandard letters or punctuation following @samp{%} is to
415: distinguish between different assembler languages for the same machine; for
416: example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
417: requires periods in most opcode names, while MIT syntax does not. For
418: example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
419: syntax. The same file of patterns is used for both kinds of output syntax,
420: but the character sequence @samp{%.} is used in each place where Motorola
421: syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
422: defines the sequence to output a period; the macro for MIT syntax defines
423: it to do nothing.
424:
425: @node Output Statement, Constraints, Output Template, Machine Desc
426: @section C Statements for Generating Assembler Output
427: @cindex output statements
428: @cindex C statements for assembler output
429: @cindex generating assembler output
430:
431: Often a single fixed template string cannot produce correct and efficient
432: assembler code for all the cases that are recognized by a single
433: instruction pattern. For example, the opcodes may depend on the kinds of
434: operands; or some unfortunate combinations of operands may require extra
435: machine instructions.
436:
437: If the output control string starts with a @samp{@@}, then it is actually
438: a series of templates, each on a separate line. (Blank lines and
439: leading spaces and tabs are ignored.) The templates correspond to the
440: pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
441: if a target machine has a two-address add instruction @samp{addr} to add
442: into a register and another @samp{addm} to add a register to memory, you
443: might write this pattern:
444:
445: @example
446: (define_insn "addsi3"
447: [(set (match_operand:SI 0 "general_operand" "r,m")
448: (plus:SI (match_operand:SI 1 "general_operand" "0,0")
449: (match_operand:SI 2 "general_operand" "g,r")))]
450: ""
451: "@@
452: addr %1,%0
453: addm %1,%0")
454: @end example
455:
456: @cindex @code{*} in template
457: @cindex asterisk in template
458: If the output control string starts with a @samp{*}, then it is not an
459: output template but rather a piece of C program that should compute a
460: template. It should execute a @code{return} statement to return the
461: template-string you want. Most such templates use C string literals, which
462: require doublequote characters to delimit them. To include these
463: doublequote characters in the string, prefix each one with @samp{\}.
464:
465: The operands may be found in the array @code{operands}, whose C data type
466: is @code{rtx []}.
467:
468: It is very common to select different ways of generating assembler code
469: based on whether an immediate operand is within a certain range. Be
470: careful when doing this, because the result of @code{INTVAL} is an
471: integer on the host machine. If the host machine has more bits in an
472: @code{int} than the target machine has in the mode in which the constant
473: will be used, then some of the bits you get from @code{INTVAL} will be
474: superfluous. For proper results, you must carefully disregard the
475: values of those bits.
476:
477: @findex output_asm_insn
478: It is possible to output an assembler instruction and then go on to output
479: or compute more of them, using the subroutine @code{output_asm_insn}. This
480: receives two arguments: a template-string and a vector of operands. The
481: vector may be @code{operands}, or it may be another array of @code{rtx}
482: that you declare locally and initialize yourself.
483:
484: @findex which_alternative
485: When an insn pattern has multiple alternatives in its constraints, often
486: the appearance of the assembler code is determined mostly by which alternative
487: was matched. When this is so, the C code can test the variable
488: @code{which_alternative}, which is the ordinal number of the alternative
489: that was actually satisfied (0 for the first, 1 for the second alternative,
490: etc.).
491:
492: For example, suppose there are two opcodes for storing zero, @samp{clrreg}
493: for registers and @samp{clrmem} for memory locations. Here is how
494: a pattern could use @code{which_alternative} to choose between them:
495:
496: @example
497: (define_insn ""
498: [(set (match_operand:SI 0 "general_operand" "r,m")
499: (const_int 0))]
500: ""
501: "*
502: return (which_alternative == 0
503: ? \"clrreg %0\" : \"clrmem %0\");
504: ")
505: @end example
506:
507: The example above, where the assembler code to generate was
508: @emph{solely} determined by the alternative, could also have been specified
509: as follows, having the output control string start with a @samp{@@}:
510:
511: @example
512: (define_insn ""
513: [(set (match_operand:SI 0 "general_operand" "r,m")
514: (const_int 0))]
515: ""
516: "@@
517: clrreg %0
518: clrmem %0")
519: @end example
520:
521: @node Constraints, Standard Names, Output Statement, Machine Desc
522: @section Operand Constraints
523: @cindex operand constraints
524: @cindex constraints
525:
526: Each @code{match_operand} in an instruction pattern can specify a
527: constraint for the type of operands allowed. Constraints can say whether
528: an operand may be in a register, and which kinds of register; whether the
529: operand can be a memory reference, and which kinds of address; whether the
530: operand may be an immediate constant, and which possible values it may
531: have. Constraints can also require two operands to match.
532:
533: @menu
534: * Simple Constraints:: Basic use of constraints.
535: * Multi-Alternative:: When an insn has two alternative constraint-patterns.
536: * Class Preferences:: Constraints guide which hard register to put things in.
537: * Modifiers:: More precise control over effects of constraints.
538: * No Constraints:: Describing a clean machine without constraints.
539: @end menu
540:
541: @node Simple Constraints, Multi-Alternative, Constraints, Constraints
542: @subsection Simple Constraints
543: @cindex simple constraints
544:
545: The simplest kind of constraint is a string full of letters, each of
546: which describes one kind of operand that is permitted. Here are
547: the letters that are allowed:
548:
549: @table @asis
550: @cindex @samp{m} in constraint
551: @cindex memory references in constraints
552: @item @samp{m}
553: A memory operand is allowed, with any kind of address that the machine
554: supports in general.
555:
556: @cindex offsettable address
557: @cindex @samp{o} in constraint
558: @item @samp{o}
559: A memory operand is allowed, but only if the address is
560: @dfn{offsettable}. This means that adding a small integer (actually,
561: the width in bytes of the operand, as determined by its machine mode)
562: may be added to the address and the result is also a valid memory
563: address.
564:
565: @cindex autoincrement/decrement addressing
566: For example, an address which is constant is offsettable; so is an
567: address that is the sum of a register and a constant (as long as a
568: slightly larger constant is also within the range of address-offsets
569: supported by the machine); but an autoincrement or autodecrement
570: address is not offsettable. More complicated indirect/indexed
571: addresses may or may not be offsettable depending on the other
572: addressing modes that the machine supports.
573:
574: Note that in an output operand which can be matched by another
575: operand, the constraint letter @samp{o} is valid only when accompanied
576: by both @samp{<} (if the target machine has predecrement addressing)
577: and @samp{>} (if the target machine has preincrement addressing).
578:
579: @cindex @samp{V} in constraint
580: @item @samp{V}
581: A memory operand that is not offsettable. In other words, anything that
582: would fit the @samp{m} constraint but not the @samp{o} constraint.
583:
584: @cindex @samp{<} in constraint
585: @item @samp{<}
586: A memory operand with autodecrement addressing (either predecrement or
587: postdecrement) is allowed.
588:
589: @cindex @samp{>} in constraint
590: @item @samp{>}
591: A memory operand with autoincrement addressing (either preincrement or
592: postincrement) is allowed.
593:
594: @cindex @samp{r} in constraint
595: @cindex registers in constraints
596: @item @samp{r}
597: A register operand is allowed provided that it is in a general
598: register.
599:
600: @cindex @samp{d} in constraint
601: @item @samp{d}, @samp{a}, @samp{f}, @dots{}
602: Other letters can be defined in machine-dependent fashion to stand for
603: particular classes of registers. @samp{d}, @samp{a} and @samp{f} are
604: defined on the 68000/68020 to stand for data, address and floating
605: point registers.
606:
607: @cindex constants in constraints
608: @cindex @samp{i} in constraint
609: @item @samp{i}
610: An immediate integer operand (one with constant value) is allowed.
611: This includes symbolic constants whose values will be known only at
612: assembly time.
613:
614: @cindex @samp{n} in constraint
615: @item @samp{n}
616: An immediate integer operand with a known numeric value is allowed.
617: Many systems cannot support assembly-time constants for operands less
618: than a word wide. Constraints for these operands should use @samp{n}
619: rather than @samp{i}.
620:
621: @cindex @samp{I} in constraint
622: @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
623: Other letters in the range @samp{I} through @samp{P} may be defined in
624: a machine-dependent fashion to permit immediate integer operands with
625: explicit integer values in specified ranges. For example, on the
626: 68000, @samp{I} is defined to stand for the range of values 1 to 8.
627: This is the range permitted as a shift count in the shift
628: instructions.
629:
630: @cindex @samp{E} in constraint
631: @item @samp{E}
632: An immediate floating operand (expression code @code{const_double}) is
633: allowed, but only if the target floating point format is the same as
634: that of the host machine (on which the compiler is running).
635:
636: @cindex @samp{F} in constraint
637: @item @samp{F}
638: An immediate floating operand (expression code @code{const_double}) is
639: allowed.
640:
641: @cindex @samp{G} in constraint
642: @cindex @samp{H} in constraint
643: @item @samp{G}, @samp{H}
644: @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
645: permit immediate floating operands in particular ranges of values.
646:
647: @cindex @samp{s} in constraint
648: @item @samp{s}
649: An immediate integer operand whose value is not an explicit integer is
650: allowed.
651:
652: This might appear strange; if an insn allows a constant operand with a
653: value not known at compile time, it certainly must allow any known
654: value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
655: better code to be generated.
656:
657: For example, on the 68000 in a fullword instruction it is possible to
658: use an immediate operand; but if the immediate value is between -128
659: and 127, better code results from loading the value into a register and
660: using the register. This is because the load into the register can be
661: done with a @samp{moveq} instruction. We arrange for this to happen
662: by defining the letter @samp{K} to mean ``any integer outside the
663: range -128 to 127'', and then specifying @samp{Ks} in the operand
664: constraints.
665:
666: @cindex @samp{g} in constraint
667: @item @samp{g}
668: Any register, memory or immediate integer operand is allowed, except for
669: registers that are not general registers.
670:
671: @cindex @samp{X} in constraint
672: @item @samp{X}
673: Any operand whatsoever is allowed, even if it does not satisfy
674: @code{general_operand}. This is normally used in the constraint of
675: a @code{match_scratch} when certain alternatives will not actually
676: require a scratch register.
677:
678: @cindex @samp{0} in constraint
679: @cindex digits in constraint
680: @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
681: An operand that matches the specified operand number is allowed. If a
682: digit is used together with letters within the same alternative, the
683: digit should come last.
684:
685: @cindex matching constraint
686: @cindex constraint, matching
687: This is called a @dfn{matching constraint} and what it really means is
688: that the assembler has only a single operand that fills two roles
689: considered separate in the RTL insn. For example, an add insn has two
690: input operands and one output operand in the RTL, but on most machines
691: an add instruction really has only two operands, one of them an
692: input-output operand.
693:
694: Matching constraints work only in circumstances like that add insn.
695: More precisely, the two operands that match must include one input-only
696: operand and one output-only operand. Moreover, the digit must be a
697: smaller number than the number of the operand that uses it in the
698: constraint.
699:
700: For operands to match in a particular case usually means that they
701: are identical-looking RTL expressions. But in a few special cases
702: specific kinds of dissimilarity are allowed. For example, @code{*x}
703: as an input operand will match @code{*x++} as an output operand.
704: For proper results in such cases, the output template should always
705: use the output-operand's number when printing the operand.
706:
707: @cindex load address instruction
708: @cindex push address instruction
709: @cindex address constraints
710: @cindex @samp{p} in constraint
711: @item @samp{p}
712: An operand that is a valid memory address is allowed. This is
713: for ``load address'' and ``push address'' instructions.
714:
715: @findex address_operand
716: @samp{p} in the constraint must be accompanied by @code{address_operand}
717: as the predicate in the @code{match_operand}. This predicate interprets
718: the mode specified in the @code{match_operand} as the mode of the memory
719: reference for which the address would be valid.
720:
721: @cindex extensible constraints
722: @cindex @samp{Q}, in constraint
723: @item @samp{Q}, @samp{R}, @samp{S}, @dots{} @samp{U}
724: Letters in the range @samp{Q} through @samp{U} may be defined in a
725: machine-dependent fashion to stand for arbitrary operand types.
726: The machine description macro @code{EXTRA_CONSTRAINT} is passed the
727: operand as its first argument and the constraint letter as its
728: second operand.
729:
730: A typical use for this would be to distinguish certain types of
731: memory references that affect other insn operands.
732:
733: Do not define these constraint letters to accept register references
734: (@code{reg}); the reload pass does not expect this and would not handle
735: it properly.
736: @end table
737:
738: In order to have valid assembler code, each operand must satisfy
739: its constraint. But a failure to do so does not prevent the pattern
740: from applying to an insn. Instead, it directs the compiler to modify
741: the code so that the constraint will be satisfied. Usually this is
742: done by copying an operand into a register.
743:
744: Contrast, therefore, the two instruction patterns that follow:
745:
746: @example
747: (define_insn ""
748: [(set (match_operand:SI 0 "general_operand" "r")
749: (plus:SI (match_dup 0)
750: (match_operand:SI 1 "general_operand" "r")))]
751: ""
752: "@dots{}")
753: @end example
754:
755: @noindent
756: which has two operands, one of which must appear in two places, and
757:
758: @example
759: (define_insn ""
760: [(set (match_operand:SI 0 "general_operand" "r")
761: (plus:SI (match_operand:SI 1 "general_operand" "0")
762: (match_operand:SI 2 "general_operand" "r")))]
763: ""
764: "@dots{}")
765: @end example
766:
767: @noindent
768: which has three operands, two of which are required by a constraint to be
769: identical. If we are considering an insn of the form
770:
771: @example
772: (insn @var{n} @var{prev} @var{next}
773: (set (reg:SI 3)
774: (plus:SI (reg:SI 6) (reg:SI 109)))
775: @dots{})
776: @end example
777:
778: @noindent
779: the first pattern would not apply at all, because this insn does not
780: contain two identical subexpressions in the right place. The pattern would
781: say, ``That does not look like an add instruction; try other patterns.''
782: The second pattern would say, ``Yes, that's an add instruction, but there
783: is something wrong with it.'' It would direct the reload pass of the
784: compiler to generate additional insns to make the constraint true. The
785: results might look like this:
786:
787: @example
788: (insn @var{n2} @var{prev} @var{n}
789: (set (reg:SI 3) (reg:SI 6))
790: @dots{})
791:
792: (insn @var{n} @var{n2} @var{next}
793: (set (reg:SI 3)
794: (plus:SI (reg:SI 3) (reg:SI 109)))
795: @dots{})
796: @end example
797:
798: It is up to you to make sure that each operand, in each pattern, has
799: constraints that can handle any RTL expression that could be present for
800: that operand. (When multiple alternatives are in use, each pattern must,
801: for each possible combination of operand expressions, have at least one
802: alternative which can handle that combination of operands.) The
803: constraints don't need to @emph{allow} any possible operand---when this is
804: the case, they do not constrain---but they must at least point the way to
805: reloading any possible operand so that it will fit.
806:
807: @itemize @bullet
808: @item
809: If the constraint accepts whatever operands the predicate permits,
810: there is no problem: reloading is never necessary for this operand.
811:
812: For example, an operand whose constraints permit everything except
813: registers is safe provided its predicate rejects registers.
814:
815: An operand whose predicate accepts only constant values is safe
816: provided its constraints include the letter @samp{i}. If any possible
817: constant value is accepted, then nothing less than @samp{i} will do;
818: if the predicate is more selective, then the constraints may also be
819: more selective.
820:
821: @item
822: Any operand expression can be reloaded by copying it into a register.
823: So if an operand's constraints allow some kind of register, it is
824: certain to be safe. It need not permit all classes of registers; the
825: compiler knows how to copy a register into another register of the
826: proper class in order to make an instruction valid.
827:
828: @cindex nonoffsettable memory reference
829: @cindex memory reference, nonoffsettable
830: @item
831: A nonoffsettable memory reference can be reloaded by copying the
832: address into a register. So if the constraint uses the letter
833: @samp{o}, all memory references are taken care of.
834:
835: @item
836: A constant operand can be reloaded by allocating space in memory to
837: hold it as preinitialized data. Then the memory reference can be used
838: in place of the constant. So if the constraint uses the letters
839: @samp{o} or @samp{m}, constant operands are not a problem.
840:
841: @item
842: If the constraint permits a constant and a pseudo register used in an insn
843: was not allocated to a hard register and is equivalent to a constant,
844: the register will be replaced with the constant. If the predicate does
845: not permit a constant and the insn is re-recognized for some reason, the
846: compiler will crash. Thus the predicate must always recognize any
847: objects allowed by the constraint.
848: @end itemize
849:
850: If the operand's predicate can recognize registers, but the constraint does
851: not permit them, it can make the compiler crash. When this operand happens
852: to be a register, the reload pass will be stymied, because it does not know
853: how to copy a register temporarily into memory.
854:
855: @node Multi-Alternative, Class Preferences, Simple Constraints, Constraints
856: @subsection Multiple Alternative Constraints
857: @cindex multiple alternative constraints
858:
859: Sometimes a single instruction has multiple alternative sets of possible
860: operands. For example, on the 68000, a logical-or instruction can combine
861: register or an immediate value into memory, or it can combine any kind of
862: operand into a register; but it cannot combine one memory location into
863: another.
864:
865: These constraints are represented as multiple alternatives. An alternative
866: can be described by a series of letters for each operand. The overall
867: constraint for an operand is made from the letters for this operand
868: from the first alternative, a comma, the letters for this operand from
869: the second alternative, a comma, and so on until the last alternative.
870: Here is how it is done for fullword logical-or on the 68000:
871:
872: @example
873: (define_insn "iorsi3"
874: [(set (match_operand:SI 0 "general_operand" "=m,d")
875: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
876: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
877: @dots{})
878: @end example
879:
880: The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
881: operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
882: 2. The second alternative has @samp{d} (data register) for operand 0,
883: @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
884: @samp{%} in the constraints apply to all the alternatives; their
885: meaning is explained in the next section (@pxref{Class Preferences}).
886:
887: If all the operands fit any one alternative, the instruction is valid.
888: Otherwise, for each alternative, the compiler counts how many instructions
889: must be added to copy the operands so that that alternative applies.
890: The alternative requiring the least copying is chosen. If two alternatives
891: need the same amount of copying, the one that comes first is chosen.
892: These choices can be altered with the @samp{?} and @samp{!} characters:
893:
894: @table @code
895: @cindex @samp{?} in constraint
896: @cindex question mark
897: @item ?
898: Disparage slightly the alternative that the @samp{?} appears in,
899: as a choice when no alternative applies exactly. The compiler regards
900: this alternative as one unit more costly for each @samp{?} that appears
901: in it.
902:
903: @cindex @samp{!} in constraint
904: @cindex exclamation point
905: @item !
906: Disparage severely the alternative that the @samp{!} appears in.
907: This alternative can still be used if it fits without reloading,
908: but if reloading is needed, some other alternative will be used.
909: @end table
910:
911: When an insn pattern has multiple alternatives in its constraints, often
912: the appearance of the assembler code is determined mostly by which
913: alternative was matched. When this is so, the C code for writing the
914: assembler code can use the variable @code{which_alternative}, which is
915: the ordinal number of the alternative that was actually satisfied (0 for
916: the first, 1 for the second alternative, etc.). @xref{Output Statement}.
917:
918: @node Class Preferences, Modifiers, Multi-Alternative, Constraints
919: @subsection Register Class Preferences
920: @cindex class preference constraints
921: @cindex register class preference constraints
922:
923: @cindex voting between constraint alternatives
924: The operand constraints have another function: they enable the compiler
925: to decide which kind of hardware register a pseudo register is best
926: allocated to. The compiler examines the constraints that apply to the
927: insns that use the pseudo register, looking for the machine-dependent
928: letters such as @samp{d} and @samp{a} that specify classes of registers.
929: The pseudo register is put in whichever class gets the most ``votes''.
930: The constraint letters @samp{g} and @samp{r} also vote: they vote in
931: favor of a general register. The machine description says which registers
932: are considered general.
933:
934: Of course, on some machines all registers are equivalent, and no register
935: classes are defined. Then none of this complexity is relevant.
936:
937: @node Modifiers, No Constraints, Class Preferences, Constraints
938: @subsection Constraint Modifier Characters
939: @cindex modifiers in constraints
940: @cindex constraint modifier characters
941:
942: @table @samp
943: @cindex @samp{=} in constraint
944: @item =
945: Means that this operand is write-only for this instruction: the previous
946: value is discarded and replaced by output data.
947:
948: @cindex @samp{+} in constraint
949: @item +
950: Means that this operand is both read and written by the instruction.
951:
952: When the compiler fixes up the operands to satisfy the constraints,
953: it needs to know which operands are inputs to the instruction and
954: which are outputs from it. @samp{=} identifies an output; @samp{+}
955: identifies an operand that is both input and output; all other operands
956: are assumed to be input only.
957:
958: @cindex @samp{&} in constraint
959: @item &
960: Means (in a particular alternative) that this operand is written
961: before the instruction is finished using the input operands.
962: Therefore, this operand may not lie in a register that is used as an
963: input operand or as part of any memory address.
964:
965: @samp{&} applies only to the alternative in which it is written. In
966: constraints with multiple alternatives, sometimes one alternative
967: requires @samp{&} while others do not. See, for example, the
968: @samp{movdf} insn of the 68000.
969:
970: @samp{&} does not obviate the need to write @samp{=}.
971:
972: @cindex @samp{%} in constraint
973: @item %
974: Declares the instruction to be commutative for this operand and the
975: following operand. This means that the compiler may interchange the
976: two operands if that is the cheapest way to make all operands fit the
977: constraints. This is often used in patterns for addition instructions
978: that really have only two operands: the result must go in one of the
979: arguments. Here for example, is how the 68000 halfword-add
980: instruction is defined:
981:
982: @example
983: (define_insn "addhi3"
984: [(set (match_operand:HI 0 "general_operand" "=m,r")
985: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
986: (match_operand:HI 2 "general_operand" "di,g")))]
987: @dots{})
988: @end example
989:
990: @cindex @samp{#} in constraint
991: @item #
992: Says that all following characters, up to the next comma, are to be
993: ignored as a constraint. They are significant only for choosing
994: register preferences.
995:
996: @cindex @samp{*} in constraint
997: @item *
998: Says that the following character should be ignored when choosing
999: register preferences. @samp{*} has no effect on the meaning of the
1000: constraint as a constraint, and no effect on reloading.
1001:
1002: Here is an example: the 68000 has an instruction to sign-extend a
1003: halfword in a data register, and can also sign-extend a value by
1004: copying it into an address register. While either kind of register is
1005: acceptable, the constraints on an address-register destination are
1006: less strict, so it is best if register allocation makes an address
1007: register its goal. Therefore, @samp{*} is used so that the @samp{d}
1008: constraint letter (for data register) is ignored when computing
1009: register preferences.
1010:
1011: @example
1012: (define_insn "extendhisi2"
1013: [(set (match_operand:SI 0 "general_operand" "=*d,a")
1014: (sign_extend:SI
1015: (match_operand:HI 1 "general_operand" "0,g")))]
1016: @dots{})
1017: @end example
1018: @end table
1019:
1020: @node No Constraints,, Modifiers, Constraints
1021: @subsection Not Using Constraints
1022: @cindex no constraints
1023: @cindex not using constraints
1024:
1025: Some machines are so clean that operand constraints are not required. For
1026: example, on the Vax, an operand valid in one context is valid in any other
1027: context. On such a machine, every operand constraint would be @samp{g},
1028: excepting only operands of ``load address'' instructions which are
1029: written as if they referred to a memory location's contents but actual
1030: refer to its address. They would have constraint @samp{p}.
1031:
1032: @cindex empty constraints
1033: For such machines, instead of writing @samp{g} and @samp{p} for all
1034: the constraints, you can choose to write a description with empty constraints.
1035: Then you write @samp{""} for the constraint in every @code{match_operand}.
1036: Address operands are identified by writing an @code{address} expression
1037: around the @code{match_operand}, not by their constraints.
1038:
1039: When the machine description has just empty constraints, certain parts
1040: of compilation are skipped, making the compiler faster. However,
1041: few machines actually do not need constraints; all machine descriptions
1042: now in existence use constraints.
1043:
1044: @node Standard Names, Pattern Ordering, Constraints, Machine Desc
1045: @section Standard Names for Patterns Used in Generation
1046: @cindex standard pattern names
1047: @cindex pattern names
1048: @cindex names, pattern
1049:
1050: Here is a table of the instruction names that are meaningful in the RTL
1051: generation pass of the compiler. Giving one of these names to an
1052: instruction pattern tells the RTL generation pass that it can use the
1053: pattern in to accomplish a certain task.
1054:
1055: @table @asis
1056: @cindex @code{mov@var{m}} instruction pattern
1057: @item @samp{mov@var{m}}
1058: Here @var{m} stands for a two-letter machine mode name, in lower case.
1059: This instruction pattern moves data with that machine mode from operand
1060: 1 to operand 0. For example, @samp{movsi} moves full-word data.
1061:
1062: If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1063: own mode is wider than @var{m}, the effect of this instruction is
1064: to store the specified value in the part of the register that corresponds
1065: to mode @var{m}. The effect on the rest of the register is undefined.
1066:
1067: This class of patterns is special in several ways. First of all, each
1068: of these names @emph{must} be defined, because there is no other way
1069: to copy a datum from one place to another.
1070:
1071: Second, these patterns are not used solely in the RTL generation pass.
1072: Even the reload pass can generate move insns to copy values from stack
1073: slots into temporary registers. When it does so, one of the operands is
1074: a hard register and the other is an operand that can need to be reloaded
1075: into a register.
1076:
1077: @findex force_reg
1078: Therefore, when given such a pair of operands, the pattern must generate
1079: RTL which needs no reloading and needs no temporary registers---no
1080: registers other than the operands. For example, if you support the
1081: pattern with a @code{define_expand}, then in such a case the
1082: @code{define_expand} mustn't call @code{force_reg} or any other such
1083: function which might generate new pseudo registers.
1084:
1085: This requirement exists even for subword modes on a RISC machine where
1086: fetching those modes from memory normally requires several insns and
1087: some temporary registers. Look in @file{spur.md} to see how the
1088: requirement can be satisfied.
1089:
1090: @findex change_address
1091: During reload a memory reference with an invalid address may be passed
1092: as an operand. Such an address will be replaced with a valid address
1093: later in the reload pass. In this case, nothing may be done with the
1094: address except to use it as it stands. If it is copied, it will not be
1095: replaced with a valid address. No attempt should be made to make such
1096: an address into a valid address and no routine (such as
1097: @code{change_address}) that will do so may be called. Note that
1098: @code{general_operand} will fail when applied to such an address.
1099:
1100: @findex reload_in_progress
1101: The global variable @code{reload_in_progress} (which must be explicitly
1102: declared if required) can be used to determine whether such special
1103: handling is required.
1104:
1105: The variety of operands that have reloads depends on the rest of the
1106: machine description, but typically on a RISC machine these can only be
1107: pseudo registers that did not get hard registers, while on other
1108: machines explicit memory references will get optional reloads.
1109:
1110: If a scratch register is required to move an object to or from memory,
1111: it can be allocated using @code{gen_reg_rtx} prior to reload. But this
1112: is impossible during and after reload. If there are cases needing
1113: scratch registers after reload, you must define
1114: @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
1115: @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1116: patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1117: them. @xref{Register Classes}.
1118:
1119: The constraints on a @samp{move@var{m}} must permit moving any hard
1120: register to any other hard register provided that
1121: @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1122: @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1123:
1124: It is obligatory to support floating point @samp{move@var{m}}
1125: instructions into and out of any registers that can hold fixed point
1126: values, because unions and structures (which have modes @code{SImode} or
1127: @code{DImode}) can be in those registers and they may have floating
1128: point members.
1129:
1130: There may also be a need to support fixed point @samp{move@var{m}}
1131: instructions in and out of floating point registers. Unfortunately, I
1132: have forgotten why this was so, and I don't know whether it is still
1133: true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1134: floating point registers, then the constraints of the fixed point
1135: @samp{move@var{m}} instructions must be designed to avoid ever trying to
1136: reload into a floating point register.
1137:
1138: @findex reload_in
1139: @findex reload_out
1140: @item @samp{reload_in@var{m}}
1141: @itemx @samp{reload_out@var{m}}
1142: Like @samp{mov@var{m}}, but used when a scratch register is required to
1143: move between operand 0 and operand 1. Operand 2 describes the scratch
1144: register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1145: macro in @pxref{Register Classes}.
1146:
1147: @cindex @code{movstrict@var{m}} instruction pattern
1148: @item @samp{movstrict@var{m}}
1149: Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1150: with mode @var{m} of a register whose natural mode is wider,
1151: the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1152: any of the register except the part which belongs to mode @var{m}.
1153:
1154: @cindex @code{add@var{m}3} instruction pattern
1155: @item @samp{add@var{m}3}
1156: Add operand 2 and operand 1, storing the result in operand 0. All operands
1157: must have mode @var{m}. This can be used even on two-address machines, by
1158: means of constraints requiring operands 1 and 0 to be the same location.
1159:
1160: @cindex @code{sub@var{m}3} instruction pattern
1161: @cindex @code{mul@var{m}3} instruction pattern
1162: @cindex @code{div@var{m}3} instruction pattern
1163: @cindex @code{udiv@var{m}3} instruction pattern
1164: @cindex @code{mod@var{m}3} instruction pattern
1165: @cindex @code{umod@var{m}3} instruction pattern
1166: @cindex @code{min@var{m}3} instruction pattern
1167: @cindex @code{max@var{m}3} instruction pattern
1168: @cindex @code{umin@var{m}3} instruction pattern
1169: @cindex @code{umax@var{m}3} instruction pattern
1170: @cindex @code{and@var{m}3} instruction pattern
1171: @cindex @code{ior@var{m}3} instruction pattern
1172: @cindex @code{xor@var{m}3} instruction pattern
1173: @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
1174: @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
1175: @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
1176: @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
1177: Similar, for other arithmetic operations.
1178:
1179: @cindex @code{mulhisi3} instruction pattern
1180: @item @samp{mulhisi3}
1181: Multiply operands 1 and 2, which have mode @code{HImode}, and store
1182: a @code{SImode} product in operand 0.
1183:
1184: @cindex @code{mulqihi3} instruction pattern
1185: @cindex @code{mulsidi3} instruction pattern
1186: @item @samp{mulqihi3}, @samp{mulsidi3}
1187: Similar widening-multiplication instructions of other widths.
1188:
1189: @cindex @code{umulqihi3} instruction pattern
1190: @cindex @code{umulhisi3} instruction pattern
1191: @cindex @code{umulsidi3} instruction pattern
1192: @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
1193: Similar widening-multiplication instructions that do unsigned
1194: multiplication.
1195:
1196: @cindex @code{divmod@var{m}4} instruction pattern
1197: @item @samp{divmod@var{m}4}
1198: Signed division that produces both a quotient and a remainder.
1199: Operand 1 is divided by operand 2 to produce a quotient stored
1200: in operand 0 and a remainder stored in operand 3.
1201:
1202: For machines with an instruction that produces both a quotient and a
1203: remainder, provide a pattern for @samp{divmod@var{m}4} but do not
1204: provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
1205: allows optimization in the relatively common case when both the quotient
1206: and remainder are computed.
1207:
1208: If an instruction that just produces a quotient or just a remainder
1209: exists and is more efficient than the instruction that produces both,
1210: write the output routine of @samp{divmod@var{m}4} to call
1211: @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
1212: quotient or remainder and generate the appropriate instruction.
1213:
1214: @cindex @code{udivmod@var{m}4} instruction pattern
1215: @item @samp{udivmod@var{m}4}
1216: Similar, but does unsigned division.
1217:
1218: @cindex @code{ashl@var{m}3} instruction pattern
1219: @item @samp{ashl@var{m}3}
1220: Arithmetic-shift operand 1 left by a number of bits specified by
1221: operand 2, and store the result in operand 0. Operand 2 has
1222: mode @code{SImode}, not mode @var{m}.
1223:
1224: @cindex @code{ashr@var{m}3} instruction pattern
1225: @cindex @code{lshl@var{m}3} instruction pattern
1226: @cindex @code{lshr@var{m}3} instruction pattern
1227: @cindex @code{rotl@var{m}3} instruction pattern
1228: @cindex @code{rotr@var{m}3} instruction pattern
1229: @item @samp{ashr@var{m}3}, @samp{lshl@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
1230: Other shift and rotate instructions.
1231:
1232: Logical and arithmetic left shift are the same. Machines that do not
1233: allow negative shift counts often have only one instruction for
1234: shifting left. On such machines, you should define a pattern named
1235: @samp{ashl@var{m}3} and leave @samp{lshl@var{m}3} undefined.
1236:
1237: @cindex @code{neg@var{m}2} instruction pattern
1238: @item @samp{neg@var{m}2}
1239: Negate operand 1 and store the result in operand 0.
1240:
1241: @cindex @code{abs@var{m}2} instruction pattern
1242: @item @samp{abs@var{m}2}
1243: Store the absolute value of operand 1 into operand 0.
1244:
1245: @cindex @code{sqrt@var{m}2} instruction pattern
1246: @item @samp{sqrt@var{m}2}
1247: Store the square root of operand 1 into operand 0.
1248:
1249: @cindex @code{ffs@var{m}2} instruction pattern
1250: @item @samp{ffs@var{m}2}
1251: Store into operand 0 one plus the index of the least significant 1-bit
1252: of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
1253: of operand 0; operand 1's mode is specified by the instruction
1254: pattern, and the compiler will convert the operand to that mode before
1255: generating the instruction.
1256:
1257: @cindex @code{one_cmpl@var{m}2} instruction pattern
1258: @item @samp{one_cmpl@var{m}2}
1259: Store the bitwise-complement of operand 1 into operand 0.
1260:
1261: @cindex @code{cmp@var{m}} instruction pattern
1262: @item @samp{cmp@var{m}}
1263: Compare operand 0 and operand 1, and set the condition codes.
1264: The RTL pattern should look like this:
1265:
1266: @example
1267: (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
1268: (match_operand:@var{m} 1 @dots{})))
1269: @end example
1270:
1271: @cindex @code{tst@var{m}} instruction pattern
1272: @item @samp{tst@var{m}}
1273: Compare operand 0 against zero, and set the condition codes.
1274: The RTL pattern should look like this:
1275:
1276: @example
1277: (set (cc0) (match_operand:@var{m} 0 @dots{}))
1278: @end example
1279:
1280: @samp{tst@var{m}} patterns should not be defined for machines that do
1281: not use @code{(cc0)}. Doing so would confuse the optimizer since it
1282: would no longer be clear which @code{set} operations were comparisons.
1283: The @samp{cmp@var{m}} patterns should be used instead.
1284:
1285: @cindex @code{movstr@var{m}} instruction pattern
1286: @item @samp{movstr@var{m}}
1287: Block move instruction. The addresses of the destination and source
1288: strings are the first two operands, and both are in mode @code{Pmode}.
1289: The number of bytes to move is the third operand, in mode @var{m}.
1290:
1291: The fourth operand is the known shared alignment of the source and
1292: destination, in the form of a @code{const_int} rtx. Thus, if the
1293: compiler knows that both source and destination are word-aligned,
1294: it may provide the value 4 for this operand.
1295:
1296: These patterns need not give special consideration to the possibility
1297: that the source and destination strings might overlap.
1298:
1299: @cindex @code{cmpstr@var{m}} instruction pattern
1300: @item @samp{cmpstr@var{m}}
1301: Block compare instruction, with five operands. Operand 0 is the output;
1302: it has mode @var{m}. The remaining four operands are like the operands
1303: of @samp{movstr@var{m}}. The two memory blocks specified are compared
1304: byte by byte in lexicographic order. The effect of the instruction is
1305: to store a value in operand 0 whose sign indicates the result of the
1306: comparison.
1307:
1308: @cindex @code{float@var{mn}2} instruction pattern
1309: @item @samp{float@var{m}@var{n}2}
1310: Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
1311: floating point mode @var{n} and store in operand 0 (which has mode
1312: @var{n}).
1313:
1314: @cindex @code{floatuns@var{mn}2} instruction pattern
1315: @item @samp{floatuns@var{m}@var{n}2}
1316: Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
1317: to floating point mode @var{n} and store in operand 0 (which has mode
1318: @var{n}).
1319:
1320: @cindex @code{fix@var{mn}2} instruction pattern
1321: @item @samp{fix@var{m}@var{n}2}
1322: Convert operand 1 (valid for floating point mode @var{m}) to fixed
1323: point mode @var{n} as a signed number and store in operand 0 (which
1324: has mode @var{n}). This instruction's result is defined only when
1325: the value of operand 1 is an integer.
1326:
1327: @cindex @code{fixuns@var{mn}2} instruction pattern
1328: @item @samp{fixuns@var{m}@var{n}2}
1329: Convert operand 1 (valid for floating point mode @var{m}) to fixed
1330: point mode @var{n} as an unsigned number and store in operand 0 (which
1331: has mode @var{n}). This instruction's result is defined only when the
1332: value of operand 1 is an integer.
1333:
1334: @cindex @code{ftrunc@var{m}2} instruction pattern
1335: @item @samp{ftrunc@var{m}2}
1336: Convert operand 1 (valid for floating point mode @var{m}) to an
1337: integer value, still represented in floating point mode @var{m}, and
1338: store it in operand 0 (valid for floating point mode @var{m}).
1339:
1340: @cindex @code{fix_trunc@var{mn}2} instruction pattern
1341: @item @samp{fix_trunc@var{m}@var{n}2}
1342: Like @samp{fix@var{m}@var{n}2} but works for any floating point value
1343: of mode @var{m} by converting the value to an integer.
1344:
1345: @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
1346: @item @samp{fixuns_trunc@var{m}@var{n}2}
1347: Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
1348: value of mode @var{m} by converting the value to an integer.
1349:
1350: @cindex @code{trunc@var{mn}} instruction pattern
1351: @item @samp{trunc@var{m}@var{n}}
1352: Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
1353: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1354: point or both floating point.
1355:
1356: @cindex @code{extend@var{mn}} instruction pattern
1357: @item @samp{extend@var{m}@var{n}}
1358: Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
1359: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1360: point or both floating point.
1361:
1362: @cindex @code{zero_extend@var{mn}} instruction pattern
1363: @item @samp{zero_extend@var{m}@var{n}}
1364: Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
1365: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1366: point.
1367:
1368: @cindex @code{extv} instruction pattern
1369: @item @samp{extv}
1370: Extract a bit field from operand 1 (a register or memory operand), where
1371: operand 2 specifies the width in bits and operand 3 the starting bit,
1372: and store it in operand 0. Operand 0 must have mode @code{word_mode}.
1373: Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
1374: @code{word_mode} is allowed only for registers. Operands 2 and 3 must
1375: be valid for @code{word_mode}.
1376:
1377: The RTL generation pass generates this instruction only with constants
1378: for operands 2 and 3.
1379:
1380: The bit-field value is sign-extended to a full word integer
1381: before it is stored in operand 0.
1382:
1383: @cindex @code{extzv} instruction pattern
1384: @item @samp{extzv}
1385: Like @samp{extv} except that the bit-field value is zero-extended.
1386:
1387: @cindex @code{insv} instruction pattern
1388: @item @samp{insv}
1389: Store operand 3 (which must be valid for @code{word_mode}) into a bit
1390: field in operand 0, where operand 1 specifies the width in bits and
1391: operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
1392: @code{word_mode}; often @code{word_mode} is allowed only for registers.
1393: Operands 1 and 2 must be valid for @code{word_mode}.
1394:
1395: The RTL generation pass generates this instruction only with constants
1396: for operands 1 and 2.
1397:
1398: @cindex @code{s@var{cond}} instruction pattern
1399: @item @samp{s@var{cond}}
1400: Store zero or nonzero in the operand according to the condition codes.
1401: Value stored is nonzero iff the condition @var{cond} is true.
1402: @var{cond} is the name of a comparison operation expression code, such
1403: as @code{eq}, @code{lt} or @code{leu}.
1404:
1405: You specify the mode that the operand must have when you write the
1406: @code{match_operand} expression. The compiler automatically sees
1407: which mode you have used and supplies an operand of that mode.
1408:
1409: The value stored for a true condition must have 1 as its low bit, or
1410: else must be negative. Otherwise the instruction is not suitable and
1411: you should omit it from the machine description. You describe to the
1412: compiler exactly which value is stored by defining the macro
1413: @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
1414: found that can be used for all the @samp{s@var{cond}} patterns, you
1415: should omit those operations from the machine description.
1416:
1417: These operations may fail, but should do so only in relatively
1418: uncommon cases; if they would fail for common cases involving
1419: integer comparisons, it is best to omit these patterns.
1420:
1421: If these operations are omitted, the compiler will usually generate code
1422: that copies the constant one to the target and branches around an
1423: assignment of zero to the target. If this code is more efficient than
1424: the potential instructions used for the @samp{s@var{cond}} pattern
1425: followed by those required to convert the result into a 1 or a zero in
1426: @code{SImode}, you should omit the @samp{s@var{cond}} operations from
1427: the machine description.
1428:
1429: @cindex @code{b@var{cond}} instruction pattern
1430: @item @samp{b@var{cond}}
1431: Conditional branch instruction. Operand 0 is a @code{label_ref} that
1432: refers to the label to jump to. Jump if the condition codes meet
1433: condition @var{cond}.
1434:
1435: Some machines do not follow the model assumed here where a comparison
1436: instruction is followed by a conditional branch instruction. In that
1437: case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
1438: simply store the operands away and generate all the required insns in a
1439: @code{define_expand} (@pxref{Expander Definitions}) for the conditional
1440: branch operations. All calls to expand @samp{v@var{cond}} patterns are
1441: immediately preceded by calls to expand either a @samp{cmp@var{m}}
1442: pattern or a @samp{tst@var{m}} pattern.
1443:
1444: Machines that use a pseudo register for the condition code value, or
1445: where the mode used for the comparison depends on the condition being
1446: tested, should also use the above mechanism. @xref{Jump Patterns}
1447:
1448: The above discussion also applies to @samp{s@var{cond}} patterns.
1449:
1450: @cindex @code{call} instruction pattern
1451: @item @samp{call}
1452: Subroutine call instruction returning no value. Operand 0 is the
1453: function to call; operand 1 is the number of bytes of arguments pushed
1454: (in mode @code{SImode}, except it is normally a @code{const_int});
1455: operand 2 is the number of registers used as operands.
1456:
1457: On most machines, operand 2 is not actually stored into the RTL
1458: pattern. It is supplied for the sake of some RISC machines which need
1459: to put this information into the assembler code; they can put it in
1460: the RTL instead of operand 1.
1461:
1462: Operand 0 should be a @code{mem} RTX whose address is the address of the
1463: function. Note, however, that this address can be a @code{symbol_ref}
1464: expression even if it would not be a legitimate memory address on the
1465: target machine. If it is also not a valid argument for a call
1466: instruction, the pattern for this operation should be a
1467: @code{define_expand} (@pxref{Expander Definitions}) that places the
1468: address into a register and uses that register in the call instruction.
1469:
1470: @cindex @code{call_value} instruction pattern
1471: @item @samp{call_value}
1472: Subroutine call instruction returning a value. Operand 0 is the hard
1473: register in which the value is returned. There are three more
1474: operands, the same as the three operands of the @samp{call}
1475: instruction (but with numbers increased by one).
1476:
1477: Subroutines that return @code{BLKmode} objects use the @samp{call}
1478: insn.
1479:
1480: @cindex @code{call_pop} instruction pattern
1481: @cindex @code{call_value_pop} instruction pattern
1482: @item @samp{call_pop}, @samp{call_value_pop}
1483: Similar to @samp{call} and @samp{call_value}, except used if defined and
1484: if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
1485: that contains both the function call and a @code{set} to indicate the
1486: adjustment made to the frame pointer.
1487:
1488: For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
1489: patterns increases the number of functions for which the frame pointer
1490: can be eliminated, if desired.
1491:
1492: @cindex @code{return} instruction pattern
1493: @item @samp{return}
1494: Subroutine return instruction. This instruction pattern name should be
1495: defined only if a single instruction can do all the work of returning
1496: from a function.
1497:
1498: Like the @samp{mov@var{m}} patterns, this pattern is also used after the
1499: RTL generation phase. In this case it is to support machines where
1500: multiple instructions are usually needed to return from a function, but
1501: some class of functions only requires one instruction to implement a
1502: return. Normally, the applicable functions are those which do not need
1503: to save any registers or allocate stack space.
1504:
1505: @findex reload_completed
1506: @findex leaf_function_p
1507: For such machines, the condition specified in this pattern should only
1508: be true when @code{reload_completed} is non-zero and the function's
1509: epilogue would only be a single instruction. For machines with register
1510: windows, the routine @code{leaf_function_p} may be used to determine if
1511: a register window push is required.
1512:
1513: Machines that have conditional return instructions should define patterns
1514: such as
1515:
1516: @example
1517: (define_insn ""
1518: [(set (pc)
1519: (if_then_else (match_operator 0 "comparison_operator"
1520: [(cc0) (const_int 0)])
1521: (return)
1522: (pc)))]
1523: "@var{condition}"
1524: "@dots{}")
1525: @end example
1526:
1527: where @var{condition} would normally be the same condition specified on the
1528: named @samp{return} pattern.
1529:
1530: @cindex @code{nop} instruction pattern
1531: @item @samp{nop}
1532: No-op instruction. This instruction pattern name should always be defined
1533: to output a no-op in assembler code. @code{(const_int 0)} will do as an
1534: RTL pattern.
1535:
1536: @cindex @code{indirect_jump} instruction pattern
1537: @item @samp{indirect_jump}
1538: An instruction to jump to an address which is operand zero.
1539: This pattern name is mandatory on all machines.
1540:
1541: @cindex @code{casesi} instruction pattern
1542: @item @samp{casesi}
1543: Instruction to jump through a dispatch table, including bounds checking.
1544: This instruction takes five operands:
1545:
1546: @enumerate
1547: @item
1548: The index to dispatch on, which has mode @code{SImode}.
1549:
1550: @item
1551: The lower bound for indices in the table, an integer constant.
1552:
1553: @item
1554: The total range of indices in the table---the largest index
1555: minus the smallest one (both inclusive).
1556:
1557: @item
1558: A label that precedes the table itself.
1559:
1560: @item
1561: A label to jump to if the index has a value outside the bounds.
1562: (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
1563: then an out-of-bounds index drops through to the code following
1564: the jump table instead of jumping to this label. In that case,
1565: this label is not actually used by the @samp{casesi} instruction,
1566: but it is always provided as an operand.)
1567: @end enumerate
1568:
1569: The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
1570: @code{jump_insn}. The number of elements in the table is one plus the
1571: difference between the upper bound and the lower bound.
1572:
1573: @cindex @code{tablejump} instruction pattern
1574: @item @samp{tablejump}
1575: Instruction to jump to a variable address. This is a low-level
1576: capability which can be used to implement a dispatch table when there
1577: is no @samp{casesi} pattern.
1578:
1579: This pattern requires two operands: the address or offset, and a label
1580: which should immediately precede the jump table. If the macro
1581: @code{CASE_VECTOR_PC_RELATIVE} is defined then the first operand is an
1582: offset which counts from the address of the table; otherwise, it is an
1583: absolute address to jump to.
1584:
1585: The @samp{tablejump} insn is always the last insn before the jump
1586: table it uses. Its assembler code normally has no need to use the
1587: second operand, but you should incorporate it in the RTL pattern so
1588: that the jump optimizer will not delete the table as unreachable code.
1589: @end table
1590:
1591: @node Pattern Ordering, Dependent Patterns, Standard Names, Machine Desc
1592: @section When the Order of Patterns Matters
1593: @cindex Pattern Ordering
1594: @cindex Ordering of Patterns
1595:
1596: Sometimes an insn can match more than one instruction pattern. Then the
1597: pattern that appears first in the machine description is the one used.
1598: Therefore, more specific patterns (patterns that will match fewer things)
1599: and faster instructions (those that will produce better code when they
1600: do match) should usually go first in the description.
1601:
1602: In some cases the effect of ordering the patterns can be used to hide
1603: a pattern when it is not valid. For example, the 68000 has an
1604: instruction for converting a fullword to floating point and another
1605: for converting a byte to floating point. An instruction converting
1606: an integer to floating point could match either one. We put the
1607: pattern to convert the fullword first to make sure that one will
1608: be used rather than the other. (Otherwise a large integer might
1609: be generated as a single-byte immediate quantity, which would not work.)
1610: Instead of using this pattern ordering it would be possible to make the
1611: pattern for convert-a-byte smart enough to deal properly with any
1612: constant value.
1613:
1614: @node Dependent Patterns, Jump Patterns, Pattern Ordering, Machine Desc
1615: @section Interdependence of Patterns
1616: @cindex Dependent Patterns
1617: @cindex Interdependence of Patterns
1618:
1619: Every machine description must have a named pattern for each of the
1620: conditional branch names @samp{b@var{cond}}. The recognition template
1621: must always have the form
1622:
1623: @example
1624: (set (pc)
1625: (if_then_else (@var{cond} (cc0) (const_int 0))
1626: (label_ref (match_operand 0 "" ""))
1627: (pc)))
1628: @end example
1629:
1630: @noindent
1631: In addition, every machine description must have an anonymous pattern
1632: for each of the possible reverse-conditional branches. Their templates
1633: look like
1634:
1635: @example
1636: (set (pc)
1637: (if_then_else (@var{cond} (cc0) (const_int 0))
1638: (pc)
1639: (label_ref (match_operand 0 "" ""))))
1640: @end example
1641:
1642: @noindent
1643: They are necessary because jump optimization can turn direct-conditional
1644: branches into reverse-conditional branches.
1645:
1646: It is often convenient to use the @code{match_operator} construct to
1647: reduce the number of patterns that must be specified for branches. For
1648: example,
1649:
1650: @example
1651: (define_insn ""
1652: [(set (pc)
1653: (if_then_else (match_operator 0 "comparison_operator"
1654: [(cc0) (const_int 0)])
1655: (pc)
1656: (label_ref (match_operand 1 "" ""))))]
1657: "@var{condition}"
1658: "@dots{}")
1659: @end example
1660:
1661: In some cases machines support instructions identical except for the
1662: machine mode of one or more operands. For example, there may be
1663: ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
1664: patterns are
1665:
1666: @example
1667: (set (match_operand:SI 0 @dots{})
1668: (extend:SI (match_operand:HI 1 @dots{})))
1669:
1670: (set (match_operand:SI 0 @dots{})
1671: (extend:SI (match_operand:QI 1 @dots{})))
1672: @end example
1673:
1674: @noindent
1675: Constant integers do not specify a machine mode, so an instruction to
1676: extend a constant value could match either pattern. The pattern it
1677: actually will match is the one that appears first in the file. For correct
1678: results, this must be the one for the widest possible mode (@code{HImode},
1679: here). If the pattern matches the @code{QImode} instruction, the results
1680: will be incorrect if the constant value does not actually fit that mode.
1681:
1682: Such instructions to extend constants are rarely generated because they are
1683: optimized away, but they do occasionally happen in nonoptimized
1684: compilations.
1685:
1686: If a constraint in a pattern allows a constant, the reload pass may
1687: replace a register with a constant permitted by the constraint in some
1688: cases. Similarly for memory references. You must ensure that the
1689: predicate permits all objects allowed by the constraints to prevent the
1690: compiler from crashing.
1691:
1692: Because of this substitution, you should not provide separate patterns
1693: for increment and decrement instructions. Instead, they should be
1694: generated from the same pattern that supports register-register add
1695: insns by examining the operands and generating the appropriate machine
1696: instruction.
1697:
1698: @node Jump Patterns, Insn Canonicalizations, Dependent Patterns, Machine Desc
1699: @section Defining Jump Instruction Patterns
1700: @cindex jump instruction patterns
1701: @cindex defining jump instruction patterns
1702:
1703: For most machines, GNU CC assumes that the machine has a condition code.
1704: A comparison insn sets the condition code, recording the results of both
1705: signed and unsigned comparison of the given operands. A separate branch
1706: insn tests the condition code and branches or not according its value.
1707: The branch insns come in distinct signed and unsigned flavors. Many
1708: common machines, such as the Vax, the 68000 and the 32000, work this
1709: way.
1710:
1711: Some machines have distinct signed and unsigned compare instructions, and
1712: only one set of conditional branch instructions. The easiest way to handle
1713: these machines is to treat them just like the others until the final stage
1714: where assembly code is written. At this time, when outputting code for the
1715: compare instruction, peek ahead at the following branch using
1716: @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
1717: being output, in the output-writing code in an instruction pattern.) If
1718: the RTL says that is an unsigned branch, output an unsigned compare;
1719: otherwise output a signed compare. When the branch itself is output, you
1720: can treat signed and unsigned branches identically.
1721:
1722: The reason you can do this is that GNU CC always generates a pair of
1723: consecutive RTL insns, possibly separated by @code{note} insns, one to
1724: set the condition code and one to test it, and keeps the pair inviolate
1725: until the end.
1726:
1727: To go with this technique, you must define the machine-description macro
1728: @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
1729: compare instruction is superfluous.
1730:
1731: Some machines have compare-and-branch instructions and no condition code.
1732: A similar technique works for them. When it is time to ``output'' a
1733: compare instruction, record its operands in two static variables. When
1734: outputting the branch-on-condition-code instruction that follows, actually
1735: output a compare-and-branch instruction that uses the remembered operands.
1736:
1737: It also works to define patterns for compare-and-branch instructions.
1738: In optimizing compilation, the pair of compare and branch instructions
1739: will be combined according to these patterns. But this does not happen
1740: if optimization is not requested. So you must use one of the solutions
1741: above in addition to any special patterns you define.
1742:
1743: In many RISC machines, most instructions do not affect the condition
1744: code and there may not even be a separate condition code register. On
1745: these machines, the restriction that the definition and use of the
1746: condition code be adjacent insns is not necessary and can prevent
1747: important optimizations. For example, on the IBM RS/6000, there is a
1748: delay for taken branches unless the condition code register is set three
1749: instructions earlier than the conditional branch. The instruction
1750: scheduler cannot perform this optimization if it is not permitted to
1751: separate the definition and use of the condition code register.
1752:
1753: On these machines, do not use @code{(cc0)}, but instead use a register
1754: to represent the condition code. If there is a specific condition code
1755: register in the machine, use a hard register. If the condition code or
1756: comparison result can be placed in any general register, or if there are
1757: multiple condition registers, use a pseudo register.
1758:
1759: @findex prev_cc0_setter
1760: @findex next_cc0_user
1761: On some machines, the type of branch instruction generated may depend on
1762: the way the condition code was produced; for example, on the 68k and
1763: Sparc, setting the condition code directly from an add or subtract
1764: instruction does not clear the overflow bit the way that a test
1765: instruction does, so a different branch instruction must be used for
1766: some conditional branches. For machines that use @code{(cc0)}, the set
1767: and use of the condition code must be adjacent (separated only by
1768: @code{note} insns) allowing flags in @code{cc_status} to be used.
1769: (@xref{Condition Code}.) Also, the comparison and branch insns can be
1770: located from each other by using the functions @code{prev_cc0_setter}
1771: and @code{next_cc0_user}.
1772:
1773: However, this is not true on machines that do not use @code{(cc0)}. On
1774: those machines, no assumptions can be made about the adjacency of the
1775: compare and branch insns and the above methods cannot be used. Instead,
1776: we use the machine mode of the condition code register to record
1777: different formats of the condition code register.
1778:
1779: Registers used to store the condition code value should have a mode that
1780: is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
1781: additional modes are required (as for the add example mentioned above in
1782: the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
1783: additional modes required (@pxref{Condition Code}). Also define
1784: @code{EXTRA_CC_NAMES} to list the names of those modes and
1785: @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
1786:
1787: If it is known during RTL generation that a different mode will be
1788: required (for example, if the machine has separate compare instructions
1789: for signed and unsigned quantities, like most IBM processors), they can
1790: be specified at that time.
1791:
1792: If the cases that require different modes would be made by instruction
1793: combination, the macro @code{SELECT_CC_MODE} determines which machine
1794: mode should be used for the comparison result. The patterns should be
1795: written using that mode. To support the case of the add on the Sparc
1796: discussed above, we have the pattern
1797:
1798: @example
1799: (define_insn ""
1800: [(set (reg:CC_NOOV 0)
1801: (compare:CC_NOOV (plus:SI (match_operand:SI 0 "register_operand" "%r")
1802: (match_operand:SI 1 "arith_operand" "rI"))
1803: (const_int 0)))]
1804: ""
1805: "@dots{}")
1806: @end example
1807:
1808: The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
1809: for comparisons whose argument is a @code{plus}.
1810:
1811: @node Insn Canonicalizations, Peephole Definitions, Jump Patterns, Machine Desc
1812: @section Canonicalization of Instructions
1813: @cindex canonicalization of instructions
1814: @cindex insn canonicalization
1815:
1816: There are often cases where multiple RTL expressions could represent an
1817: operation peformed by a single machine instruction. This situation is
1818: most commonly encountered with logical, branch, and multiply-accumulate
1819: instructions. In such cases, the compiler attempts to convert these
1820: multiple RTL expressions into a single canonical form to reduce the
1821: number of insn patterns required.
1822:
1823: In addition to algebraic simplifications, following canonicalizations
1824: are performed:
1825:
1826: @itemize @bullet
1827: @item
1828: For commutative and comparison operators, a constant is always made the
1829: second operand. If a machine only supports a constant as the second
1830: operand, only patterns that match a constant in the second operand need
1831: be supplied.
1832:
1833: @cindex @code{neg}, canonicalization of
1834: @cindex @code{not}, canonicalization of
1835: @cindex @code{mult}, canonicalization of
1836: @cindex @code{plus}, canonicalization of
1837: @cindex @code{minus}, canonicalization of
1838: For these operators, if only one operand is a @code{neg}, @code{not},
1839: @code{mult}, @code{plus}, or @code{minus} expression, it will be the
1840: first operand.
1841:
1842: @cindex @code{compare}, canonicalization of
1843: @item
1844: For the @code{compare} operator, a constant is always the second operand
1845: on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
1846: machines, there are rare cases where the compiler might want to construct
1847: a @code{compare} with a constant as the first operand. However, these
1848: cases are not common enough for it to be worthwhile to provide a pattern
1849: matching a constant as the first operand unless the machine actually has
1850: such an instruction.
1851:
1852: An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
1853: @code{minus} is made the first operand under the same conditions as
1854: above.
1855:
1856: @item
1857: @code{(minus @var{x} (const_int @var{n}))} is converted to
1858: @code{(plus @var{x} (const_int @var{-n}))}.
1859:
1860: @item
1861: Within address computations (i.e., inside @code{mem}), a left shift is
1862: converted into the appropriate multiplication by a power of two.
1863:
1864: @cindex @code{ior}, canonicalization of
1865: @cindex @code{and}, canonicalization of
1866: @cindex De Morgan's law
1867: De`Morgan's Law is used to move bitwise negation inside a bitwise
1868: logical-and or logical-or operation. If this results in only one
1869: operand being a @code{not} expression, it will be the first one.
1870:
1871: A machine that has an instruction that performs a bitwise logical-and of one
1872: operand with the bitwise negation of the other should specify the pattern
1873: for that instruction as
1874:
1875: @example
1876: (define_insn ""
1877: [(set (match_operand:@var{m} 0 @dots{})
1878: (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
1879: (match_operand:@var{m} 2 @dots{})))]
1880: "@dots{}"
1881: "@dots{}")
1882: @end example
1883:
1884: @noindent
1885: Similarly, a pattern for a ``NAND'' instruction should be written
1886:
1887: @example
1888: (define_insn ""
1889: [(set (match_operand:@var{m} 0 @dots{})
1890: (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
1891: (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
1892: "@dots{}"
1893: "@dots{}")
1894: @end example
1895:
1896: In both cases, it is not necessary to include patterns for the many
1897: logically equivalent RTL expressions.
1898:
1899: @cindex @code{xor}, canonicalization of
1900: @item
1901: The only possible RTL expressions involving both bitwise exclusive-or
1902: and bitwise negation are @code{(xor:@var{m} @var{x}) @var{y})}
1903: and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
1904:
1905: @item
1906: The sum of three items, one of which is a constant, will only appear in
1907: the form
1908:
1909: @example
1910: (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
1911: @end example
1912:
1913: @item
1914: On machines that do not use @code{cc0},
1915: @code{(compare @var{x} (const_int 0))} will be converted to
1916: @var{x}.@refill
1917:
1918: @cindex @code{zero_extract}, canonicalization of
1919: @cindex @code{sign_extract}, canonicalization of
1920: @item
1921: Equality comparisons of a group of bits (usually a single bit) with zero
1922: will be written using @code{zero_extract} rather than the equivalent
1923: @code{and} or @code{sign_extract} operations.
1924:
1925: @end itemize
1926:
1927: @node Peephole Definitions, Expander Definitions, Insn Canonicalizations, Machine Desc
1928: @section Defining Machine-Specific Peephole Optimizers
1929: @cindex peephole optimizer definitions
1930: @cindex defining peephole optimizers
1931:
1932: In addition to instruction patterns the @file{md} file may contain
1933: definitions of machine-specific peephole optimizations.
1934:
1935: The combiner does not notice certain peephole optimizations when the data
1936: flow in the program does not suggest that it should try them. For example,
1937: sometimes two consecutive insns related in purpose can be combined even
1938: though the second one does not appear to use a register computed in the
1939: first one. A machine-specific peephole optimizer can detect such
1940: opportunities.
1941:
1942: A definition looks like this:
1943:
1944: @example
1945: (define_peephole
1946: [@var{insn-pattern-1}
1947: @var{insn-pattern-2}
1948: @dots{}]
1949: "@var{condition}"
1950: "@var{template}"
1951: "@var{optional insn-attributes}")
1952: @end example
1953:
1954: @noindent
1955: The last string operand may be omitted if you are not using any
1956: machine-specific information in this machine description. If present,
1957: it must obey the same rules as in a @code{define_insn}.
1958:
1959: In this skeleton, @var{insn-pattern-1} and so on are patterns to match
1960: consecutive insns. The optimization applies to a sequence of insns when
1961: @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
1962: the next, and so on.@refill
1963:
1964: Each of the insns matched by a peephole must also match a
1965: @code{define_insn}. Peepholes are checked only at the last stage just
1966: before code generation, and only optionally. Therefore, any insn which
1967: would match a peephole but no @code{define_insn} will cause a crash in code
1968: generation in an unoptimized compilation, or at various optimization
1969: stages.
1970:
1971: The operands of the insns are matched with @code{match_operands},
1972: @code{match_operator}, and @code{match_dup}, as usual. What is not
1973: usual is that the operand numbers apply to all the insn patterns in the
1974: definition. So, you can check for identical operands in two insns by
1975: using @code{match_operand} in one insn and @code{match_dup} in the
1976: other.
1977:
1978: The operand constraints used in @code{match_operand} patterns do not have
1979: any direct effect on the applicability of the peephole, but they will
1980: be validated afterward, so make sure your constraints are general enough
1981: to apply whenever the peephole matches. If the peephole matches
1982: but the constraints are not satisfied, the compiler will crash.
1983:
1984: It is safe to omit constraints in all the operands of the peephole; or
1985: you can write constraints which serve as a double-check on the criteria
1986: previously tested.
1987:
1988: Once a sequence of insns matches the patterns, the @var{condition} is
1989: checked. This is a C expression which makes the final decision whether to
1990: perform the optimization (we do so if the expression is nonzero). If
1991: @var{condition} is omitted (in other words, the string is empty) then the
1992: optimization is applied to every sequence of insns that matches the
1993: patterns.
1994:
1995: The defined peephole optimizations are applied after register allocation
1996: is complete. Therefore, the peephole definition can check which
1997: operands have ended up in which kinds of registers, just by looking at
1998: the operands.
1999:
2000: @findex prev_nonnote_insn
2001: The way to refer to the operands in @var{condition} is to write
2002: @code{operands[@var{i}]} for operand number @var{i} (as matched by
2003: @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
2004: to refer to the last of the insns being matched; use
2005: @code{prev_nonnote_insn} to find the preceding insns.
2006:
2007: @findex dead_or_set_p
2008: When optimizing computations with intermediate results, you can use
2009: @var{condition} to match only when the intermediate results are not used
2010: elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
2011: @var{op})}, where @var{insn} is the insn in which you expect the value
2012: to be used for the last time (from the value of @code{insn}, together
2013: with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
2014: value (from @code{operands[@var{i}]}).@refill
2015:
2016: Applying the optimization means replacing the sequence of insns with one
2017: new insn. The @var{template} controls ultimate output of assembler code
2018: for this combined insn. It works exactly like the template of a
2019: @code{define_insn}. Operand numbers in this template are the same ones
2020: used in matching the original sequence of insns.
2021:
2022: The result of a defined peephole optimizer does not need to match any of
2023: the insn patterns in the machine description; it does not even have an
2024: opportunity to match them. The peephole optimizer definition itself serves
2025: as the insn pattern to control how the insn is output.
2026:
2027: Defined peephole optimizers are run as assembler code is being output,
2028: so the insns they produce are never combined or rearranged in any way.
2029:
2030: Here is an example, taken from the 68000 machine description:
2031:
2032: @example
2033: (define_peephole
2034: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
2035: (set (match_operand:DF 0 "register_operand" "f")
2036: (match_operand:DF 1 "register_operand" "ad"))]
2037: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
2038: "*
2039: @{
2040: rtx xoperands[2];
2041: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2042: #ifdef MOTOROLA
2043: output_asm_insn (\"move.l %1,(sp)\", xoperands);
2044: output_asm_insn (\"move.l %1,-(sp)\", operands);
2045: return \"fmove.d (sp)+,%0\";
2046: #else
2047: output_asm_insn (\"movel %1,sp@@\", xoperands);
2048: output_asm_insn (\"movel %1,sp@@-\", operands);
2049: return \"fmoved sp@@+,%0\";
2050: #endif
2051: @}
2052: ")
2053: @end example
2054:
2055: The effect of this optimization is to change
2056:
2057: @example
2058: jbsr _foobar
2059: addql #4,sp
2060: movel d1,sp@@-
2061: movel d0,sp@@-
2062: fmoved sp@@+,fp0
2063: @end example
2064:
2065: @noindent
2066: into
2067:
2068: @example
2069: jbsr _foobar
2070: movel d1,sp@@
2071: movel d0,sp@@-
2072: fmoved sp@@+,fp0
2073: @end example
2074:
2075: @ignore
2076: @findex CC_REVERSED
2077: If a peephole matches a sequence including one or more jump insns, you must
2078: take account of the flags such as @code{CC_REVERSED} which specify that the
2079: condition codes are represented in an unusual manner. The compiler
2080: automatically alters any ordinary conditional jumps which occur in such
2081: situations, but the compiler cannot alter jumps which have been replaced by
2082: peephole optimizations. So it is up to you to alter the assembler code
2083: that the peephole produces. Supply C code to write the assembler output,
2084: and in this C code check the condition code status flags and change the
2085: assembler code as appropriate.
2086: @end ignore
2087:
2088: @var{insn-pattern-1} and so on look @emph{almost} like the second
2089: operand of @code{define_insn}. There is one important difference: the
2090: second operand of @code{define_insn} consists of one or more RTX's
2091: enclosed in square brackets. Usually, there is only one: then the same
2092: action can be written as an element of a @code{define_peephole}. But
2093: when there are multiple actions in a @code{define_insn}, they are
2094: implicitly enclosed in a @code{parallel}. Then you must explicitly
2095: write the @code{parallel}, and the square brackets within it, in the
2096: @code{define_peephole}. Thus, if an insn pattern looks like this,
2097:
2098: @example
2099: (define_insn "divmodsi4"
2100: [(set (match_operand:SI 0 "general_operand" "=d")
2101: (div:SI (match_operand:SI 1 "general_operand" "0")
2102: (match_operand:SI 2 "general_operand" "dmsK")))
2103: (set (match_operand:SI 3 "general_operand" "=d")
2104: (mod:SI (match_dup 1) (match_dup 2)))]
2105: "TARGET_68020"
2106: "divsl%.l %2,%3:%0")
2107: @end example
2108:
2109: @noindent
2110: then the way to mention this insn in a peephole is as follows:
2111:
2112: @example
2113: (define_peephole
2114: [@dots{}
2115: (parallel
2116: [(set (match_operand:SI 0 "general_operand" "=d")
2117: (div:SI (match_operand:SI 1 "general_operand" "0")
2118: (match_operand:SI 2 "general_operand" "dmsK")))
2119: (set (match_operand:SI 3 "general_operand" "=d")
2120: (mod:SI (match_dup 1) (match_dup 2)))])
2121: @dots{}]
2122: @dots{})
2123: @end example
2124:
2125: @node Expander Definitions, Insn Splitting, Peephole Definitions, Machine Desc
2126: @section Defining RTL Sequences for Code Generation
2127: @cindex expander definitions
2128: @cindex code generation RTL sequences
2129: @cindex defining RTL sequences for code generation
2130:
2131: On some target machines, some standard pattern names for RTL generation
2132: cannot be handled with single insn, but a sequence of RTL insns can
2133: represent them. For these target machines, you can write a
2134: @code{define_expand} to specify how to generate the sequence of RTL.
2135:
2136: @findex define_expand
2137: A @code{define_expand} is an RTL expression that looks almost like a
2138: @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
2139: only for RTL generation and it can produce more than one RTL insn.
2140:
2141: A @code{define_expand} RTX has four operands:
2142:
2143: @itemize @bullet
2144: @item
2145: The name. Each @code{define_expand} must have a name, since the only
2146: use for it is to refer to it by name.
2147:
2148: @findex define_peephole
2149: @item
2150: The RTL template. This is just like the RTL template for a
2151: @code{define_peephole} in that it is a vector of RTL expressions
2152: each being one insn.
2153:
2154: @item
2155: The condition, a string containing a C expression. This expression is
2156: used to express how the availability of this pattern depends on
2157: subclasses of target machine, selected by command-line options when
2158: GNU CC is run. This is just like the condition of a
2159: @code{define_insn} that has a standard name.
2160:
2161: @item
2162: The preparation statements, a string containing zero or more C
2163: statements which are to be executed before RTL code is generated from
2164: the RTL template.
2165:
2166: Usually these statements prepare temporary registers for use as
2167: internal operands in the RTL template, but they can also generate RTL
2168: insns directly by calling routines such as @code{emit_insn}, etc.
2169: Any such insns precede the ones that come from the RTL template.
2170: @end itemize
2171:
2172: Every RTL insn emitted by a @code{define_expand} must match some
2173: @code{define_insn} in the machine description. Otherwise, the compiler
2174: will crash when trying to generate code for the insn or trying to optimize
2175: it.
2176:
2177: The RTL template, in addition to controlling generation of RTL insns,
2178: also describes the operands that need to be specified when this pattern
2179: is used. In particular, it gives a predicate for each operand.
2180:
2181: A true operand, which needs to be specified in order to generate RTL from
2182: the pattern, should be described with a @code{match_operand} in its first
2183: occurrence in the RTL template. This enters information on the operand's
2184: predicate into the tables that record such things. GNU CC uses the
2185: information to preload the operand into a register if that is required for
2186: valid RTL code. If the operand is referred to more than once, subsequent
2187: references should use @code{match_dup}.
2188:
2189: The RTL template may also refer to internal ``operands'' which are
2190: temporary registers or labels used only within the sequence made by the
2191: @code{define_expand}. Internal operands are substituted into the RTL
2192: template with @code{match_dup}, never with @code{match_operand}. The
2193: values of the internal operands are not passed in as arguments by the
2194: compiler when it requests use of this pattern. Instead, they are computed
2195: within the pattern, in the preparation statements. These statements
2196: compute the values and store them into the appropriate elements of
2197: @code{operands} so that @code{match_dup} can find them.
2198:
2199: There are two special macros defined for use in the preparation statements:
2200: @code{DONE} and @code{FAIL}. Use them with a following semicolon,
2201: as a statement.
2202:
2203: @table @code
2204:
2205: @findex DONE
2206: @item DONE
2207: Use the @code{DONE} macro to end RTL generation for the pattern. The
2208: only RTL insns resulting from the pattern on this occasion will be
2209: those already emitted by explicit calls to @code{emit_insn} within the
2210: preparation statements; the RTL template will not be generated.
2211:
2212: @findex FAIL
2213: @item FAIL
2214: Make the pattern fail on this occasion. When a pattern fails, it means
2215: that the pattern was not truly available. The calling routines in the
2216: compiler will try other strategies for code generation using other patterns.
2217:
2218: Failure is currently supported only for binary (addition, multiplication,
2219: shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
2220: operations.
2221: @end table
2222:
2223: Here is an example, the definition of left-shift for the SPUR chip:
2224:
2225: @example
2226: (define_expand "ashlsi3"
2227: [(set (match_operand:SI 0 "register_operand" "")
2228: (ashift:SI
2229: (match_operand:SI 1 "register_operand" "")
2230: (match_operand:SI 2 "nonmemory_operand" "")))]
2231: ""
2232: "
2233: @{
2234: if (GET_CODE (operands[2]) != CONST_INT
2235: || (unsigned) INTVAL (operands[2]) > 3)
2236: FAIL;
2237: @}")
2238: @end example
2239:
2240: @noindent
2241: This example uses @code{define_expand} so that it can generate an RTL insn
2242: for shifting when the shift-count is in the supported range of 0 to 3 but
2243: fail in other cases where machine insns aren't available. When it fails,
2244: the compiler tries another strategy using different patterns (such as, a
2245: library call).
2246:
2247: If the compiler were able to handle nontrivial condition-strings in
2248: patterns with names, then it would be possible to use a
2249: @code{define_insn} in that case. Here is another case (zero-extension
2250: on the 68000) which makes more use of the power of @code{define_expand}:
2251:
2252: @example
2253: (define_expand "zero_extendhisi2"
2254: [(set (match_operand:SI 0 "general_operand" "")
2255: (const_int 0))
2256: (set (strict_low_part
2257: (subreg:HI
2258: (match_dup 0)
2259: 0))
2260: (match_operand:HI 1 "general_operand" ""))]
2261: ""
2262: "operands[1] = make_safe_from (operands[1], operands[0]);")
2263: @end example
2264:
2265: @noindent
2266: @findex make_safe_from
2267: Here two RTL insns are generated, one to clear the entire output operand
2268: and the other to copy the input operand into its low half. This sequence
2269: is incorrect if the input operand refers to [the old value of] the output
2270: operand, so the preparation statement makes sure this isn't so. The
2271: function @code{make_safe_from} copies the @code{operands[1]} into a
2272: temporary register if it refers to @code{operands[0]}. It does this
2273: by emitting another RTL insn.
2274:
2275: Finally, a third example shows the use of an internal operand.
2276: Zero-extension on the SPUR chip is done by @code{and}-ing the result
2277: against a halfword mask. But this mask cannot be represented by a
2278: @code{const_int} because the constant value is too large to be legitimate
2279: on this machine. So it must be copied into a register with
2280: @code{force_reg} and then the register used in the @code{and}.
2281:
2282: @example
2283: (define_expand "zero_extendhisi2"
2284: [(set (match_operand:SI 0 "register_operand" "")
2285: (and:SI (subreg:SI
2286: (match_operand:HI 1 "register_operand" "")
2287: 0)
2288: (match_dup 2)))]
2289: ""
2290: "operands[2]
2291: = force_reg (SImode, gen_rtx (CONST_INT,
2292: VOIDmode, 65535)); ")
2293: @end example
2294:
2295: @strong{Note:} If the @code{define_expand} is used to serve a
2296: standard binary or unary arithmetic operation or a bitfield operation,
2297: then the last insn it generates must not be a @code{code_label},
2298: @code{barrier} or @code{note}. It must be an @code{insn},
2299: @code{jump_insn} or @code{call_insn}. If you don't need a real insn
2300: at the end, emit an insn to copy the result of the operation into
2301: itself. Such an insn will generate no code, but it can avoid problems
2302: in the compiler.@refill
2303:
2304: @node Insn Splitting, Insn Attributes, Expander Definitions, Machine Desc
2305: @section Splitting Instructions into Multiple Instructions
2306: @cindex insn splitting
2307: @cindex instruction splitting
2308: @cindex splitting instructions
2309:
2310: On machines that have instructions requiring delay slots (@pxref{Delay
2311: Slots}) or that have instructions whose output is not available for
2312: multiple cycles (@pxref{Function Units}), the compiler phases that
2313: optimize these cases need to be able to move insns into one-cycle
2314: delay slots. However, some insns may generate more than one machine
2315: instruction. These insns would be unable to be placed into a delay
2316: slot.
2317:
2318: It is often possible to write the single insn as a list of individual
2319: insns, each corresponding to one machine instruction. The disadvantage
2320: of doing so is that it will cause the compilation to be slower and
2321: require more space. If the resulting insns are too complex, it may also
2322: suppress some optimizations.
2323:
2324: The @code{define_split} definition tells the compiler how to split a
2325: complex insn into several simpler insns. This spilling will be
2326: performed if there is a reason to believe that it might improve
2327: instruction or delay slot scheduling. The definition looks like this:
2328:
2329: @example
2330: (define_split
2331: [@var{insn-pattern}]
2332: "@var{condition}"
2333: [@var{new-insn-pattern-1}
2334: @var{new-insn-pattern-2}
2335: @dots{}]
2336: "@var{preparation statements}")
2337: @end example
2338:
2339: @var{insn-pattern} is a pattern that needs to be split and
2340: @var{condition} is the final condition to be tested, as in a
2341: @code{define_insn}. Any insn matched by a @code{define_split} must also
2342: be matched by a @code{define_insn} in case it does not need to be split.
2343:
2344: When an insn matching @var{insn-pattern} and satisfying @var{condition}
2345: is found, it is replaced in the insn list with the insns given by
2346: @var{new-insn-pattern-1}, @var{new-insn-pattern-2}, etc.
2347:
2348: The @var{preparation statements} are similar to those specified for
2349: @code{define_expand} (@pxref{Expander Definitions}) and are executed
2350: before the new RTL is generated to prepare for the generated code
2351: or emit some insns whose pattern is not fixed.
2352:
2353: As a simple case, consider the following example from the AMD 29000
2354: machine description, which splits a @code{sign_extend} from
2355: @code{HImode} to @code{SImode} into a pair of shift insns:
2356:
2357: @example
2358: (define_split
2359: [(set (match_operand:SI 0 "gen_reg_operand" "")
2360: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
2361: ""
2362: [(set (match_dup 0)
2363: (ashift:SI (match_dup 1)
2364: (const_int 16)))
2365: (set (match_dup 0)
2366: (ashiftrt:SI (match_dup 0)
2367: (const_int 16)))]
2368: "
2369: @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
2370: @end example
2371:
2372: @node Insn Attributes,, Insn Splitting, Machine Desc
2373: @section Instruction Attributes
2374: @cindex insn attributes
2375: @cindex instruction attributes
2376:
2377: In addition to describing the instruction supported by the target machine,
2378: the @file{md} file also defines a group of @dfn{attributes} and a set of
2379: values for each. Every generated insn is assigned a value for each attribute.
2380: One possible attribute would be the effect that the insn has on the machine's
2381: condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
2382: to track the condition codes.
2383:
2384: @menu
2385: * Defining Attributes:: Specifying attributes and their values.
2386: * Expressions:: Valid expressions for attribute values.
2387: * Tagging Insns:: Assigning attribute values to insns.
2388: * Attr Example:: An example of assigning attributes.
2389: * Insn Lengths:: Computing the length of insns.
2390: * Delay Slots:: Defining delay slots required for a machine.
2391: * Function Units:: Specifying information for insn scheduling.
2392: @end menu
2393:
2394: @node Defining Attributes, Expressions, Insn Attributes, Insn Attributes
2395: @subsection Defining Attributes and their Values
2396: @cindex defining attributes and their values
2397: @cindex attributes, defining
2398:
2399: @findex define_attr
2400: The @code{define_attr} expression is used to define each attribute required
2401: by the target machine. It looks like:
2402:
2403: @example
2404: (define_attr @var{name} @var{list-of-values} @var{default})
2405: @end example
2406:
2407: @var{name} is a string specifying the name of the attribute being defined.
2408:
2409: @var{list-of-values} is either a string that specifies a comma-separated
2410: list of values that can be assigned to the attribute, or a null string to
2411: indicate that the attribute takes numeric values.
2412:
2413: @var{default} is an attribute expression that gives the value of this
2414: attribute for insns that match patterns whose definition does not include
2415: an explicit value for this attribute. @xref{Attr Example}, for more
2416: information on the handling of defaults.
2417:
2418: @findex insn-attr.h
2419: For each defined attribute, a number of definitions are written to the
2420: @file{insn-attr.h} file. For cases where an explicit set of values is
2421: specified for an attribute, the following are defined:
2422:
2423: @itemize @bullet
2424: @item
2425: A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
2426:
2427: @item
2428: An enumeral class is defined for @samp{attr_@var{name}} with
2429: elements of the form @samp{@var{upper-name}_@var{upper-value}} where
2430: the attribute name and value are first converted to upper case.
2431:
2432: @item
2433: A function @samp{get_attr_@var{name}} is defined that is passed an insn and
2434: returns the attribute value for that insn.
2435: @end itemize
2436:
2437: For example, if the following is present in the @file{md} file:
2438:
2439: @example
2440: (define_attr "type" "branch,fp,load,store,arith" @dots{})
2441: @end example
2442:
2443: @noindent
2444: the following lines will be written to the file @file{insn-attr.h}.
2445:
2446: @example
2447: #define HAVE_ATTR_type
2448: enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
2449: TYPE_STORE, TYPE_ARITH@};
2450: extern enum attr_type get_attr_type ();
2451: @end example
2452:
2453: If the attribute takes numeric values, no @code{enum} type will be
2454: defined and the function to obtain the attribute's value will return
2455: @code{int}.
2456:
2457: @node Expressions, Tagging Insns, Defining Attributes, Insn Attributes
2458: @subsection Attribute Expressions
2459: @cindex attribute expressions
2460:
2461: RTL expressions used to define attributes use the codes described above
2462: plus a few specific to attribute definitions, to be discussed below.
2463: Attribute value expressions must have one of the following forms:
2464:
2465: @table @code
2466: @cindex @code{const_int} and attributes
2467: @item (const_int @var{i})
2468: The integer @var{i} specifies the value of a numeric attribute. @var{i}
2469: must be non-negative.
2470:
2471: The value of a numeric attribute can be specified either with a
2472: @code{const_int} or as an integer represented as a string in
2473: @code{const_string}, @code{eq_attr} (see below), and @code{set_attr}
2474: (@pxref{Tagging Insns}) expressions.
2475:
2476: @cindex @code{const_string} and attributes
2477: @item (const_string @var{value})
2478: The string @var{value} specifies a constant attribute value.
2479: If @var{value} is specified as @samp{"*"}, it means that the default value of
2480: the attribute is to be used for the insn containing this expression.
2481: @samp{"*"} obviously cannot be used in the @var{default} expression
2482: of a @code{define_attr}.@refill
2483:
2484: If the attribute whose value is being specified is numeric, @var{value}
2485: must be a string containing a non-negative integer (normally
2486: @code{const_int} would be used in this case). Otherwise, it must
2487: contain one of the valid values for the attribute.
2488:
2489: @cindex @code{if_then_else} and attributes
2490: @item (if_then_else @var{test} @var{true-value} @var{false-value})
2491: @var{test} specifies an attribute test, whose format is defined below.
2492: The value of this expression is @var{true-value} if @var{test} is true,
2493: otherwise it is @var{false-value}.
2494:
2495: @cindex @code{cond} and attributes
2496: @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
2497: The first operand of this expression is a vector containing an even
2498: number of expressions and consisting of pairs of @var{test} and @var{value}
2499: expressions. The value of the @code{cond} expression is that of the
2500: @var{value} corresponding to the first true @var{test} expression. If
2501: none of the @var{test} expressions are true, the value of the @code{cond}
2502: expression is that of the @var{default} expression.
2503: @end table
2504:
2505: @var{test} expressions can have one of the following forms:
2506:
2507: @table @code
2508: @cindex @code{const_int} and attribute tests
2509: @item (const_int @var{i})
2510: This test is true if @var{i} is non-zero and false otherwise.
2511:
2512: @cindex @code{not} and attributes
2513: @cindex @code{ior} and attributes
2514: @cindex @code{and} and attributes
2515: @item (not @var{test})
2516: @itemx (ior @var{test1} @var{test2})
2517: @itemx (and @var{test1} @var{test2})
2518: These tests are true if the indicated logical function is true.
2519:
2520: @cindex @code{match_operand} and attributes
2521: @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
2522: This test is true if operand @var{n} of the insn whose attribute value
2523: is being determined has mode @var{m} (this part of the test is ignored
2524: if @var{m} is @code{VOIDmode}) and the function specified by the string
2525: @var{pred} returns a non-zero value when passed operand @var{n} and mode
2526: @var{m} (this part of the test is ignored if @var{pred} is the null
2527: string).
2528:
2529: The @var{constraints} operand is ignored and should be the null string.
2530:
2531: @cindex @code{le} and attributes
2532: @cindex @code{leu} and attributes
2533: @cindex @code{lt} and attributes
2534: @cindex @code{gt} and attributes
2535: @cindex @code{gtu} and attributes
2536: @cindex @code{ge} and attributes
2537: @cindex @code{geu} and attributes
2538: @cindex @code{ne} and attributes
2539: @cindex @code{eq} and attributes
2540: @cindex @code{plus} and attributes
2541: @cindex @code{minus} and attributes
2542: @cindex @code{mult} and attributes
2543: @cindex @code{div} and attributes
2544: @cindex @code{mod} and attributes
2545: @cindex @code{abs} and attributes
2546: @cindex @code{neg} and attributes
2547: @cindex @code{lshift} and attributes
2548: @cindex @code{ashift} and attributes
2549: @cindex @code{lshiftrt} and attributes
2550: @cindex @code{ashiftrt} and attributes
2551: @item (le @var{arith1} @var{arith2})
2552: @itemx (leu @var{arith1} @var{arith2})
2553: @itemx (lt @var{arith1} @var{arith2})
2554: @itemx (ltu @var{arith1} @var{arith2})
2555: @itemx (gt @var{arith1} @var{arith2})
2556: @itemx (gtu @var{arith1} @var{arith2})
2557: @itemx (ge @var{arith1} @var{arith2})
2558: @itemx (geu @var{arith1} @var{arith2})
2559: @itemx (ne @var{arith1} @var{arith2})
2560: @itemx (eq @var{arith1} @var{arith2})
2561: These tests are true if the indicated comparison of the two arithmetic
2562: expressions is true. Arithmetic expressions are formed with
2563: @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
2564: @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
2565: @code{lshift}, @code{ashift}, @code{lshiftrt}, and @code{ashiftrt}
2566: expressions.@refill
2567:
2568: @findex get_attr
2569: @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
2570: Lengths},for additional forms). @code{symbol_ref} is a string
2571: denoting a C expression that yields an @code{int} when evaluated by the
2572: @samp{get_attr_@dots{}} routine. It should normally be a global
2573: variable.@refill
2574:
2575: @findex eq_attr
2576: @item (eq_attr @var{name} @var{value})
2577: @var{name} is a string specifying the name of an attribute.
2578:
2579: @var{value} is a string that is either a valid value for attribute
2580: @var{name}, a comma-separated list of values, or @samp{!} followed by a
2581: value or list. If @var{value} does not begin with a @samp{!}, this
2582: test is true if the value of the @var{name} attribute of the current
2583: insn is in the list specified by @var{value}. If @var{value} begins
2584: with a @samp{!}, this test is true if the attribute's value is
2585: @emph{not} in the specified list.
2586:
2587: For example,
2588:
2589: @example
2590: (eq_attr "type" "load,store")
2591: @end example
2592:
2593: @noindent
2594: is equivalent to
2595:
2596: @example
2597: (ior (eq_attr "type" "load") (eq_attr "type" "store"))
2598: @end example
2599:
2600: If @var{name} specifies an attribute of @samp{alternative}, it refers to the
2601: value of the compiler variable @code{which_alternative}
2602: (@pxref{Output Statement}) and the values must be small integers. For
2603: example,@refill
2604:
2605: @example
2606: (eq_attr "alternative" "2,3")
2607: @end example
2608:
2609: @noindent
2610: is equivalent to
2611:
2612: @example
2613: (ior (eq (symbol_ref "which_alternative") (const_int 2))
2614: (eq (symbol_ref "which_alternative") (const_int 3)))
2615: @end example
2616:
2617: Note that, for most attributes, an @code{eq_attr} test is simplified in cases
2618: where the value of the attribute being tested is known for all insns matching
2619: a particular pattern. This is by far the most common case.@refill
2620: @end table
2621:
2622: @node Tagging Insns, Attr Example, Expressions, Insn Attributes
2623: @subsection Assigning Attribute Values to Insns
2624: @cindex tagging insns
2625: @cindex assigning attribute values to insns
2626:
2627: The value assigned to an attribute of an insn is primarily determined by
2628: which pattern is matched by that insn (or which @code{define_peephole}
2629: generated it). Every @code{define_insn} and @code{define_peephole} can
2630: have an optional last argument to specify the values of attributes for
2631: matching insns. The value of any attribute not specified in a particular
2632: insn is set to the default value for that attribute, as specified in its
2633: @code{define_attr}. Extensive use of default values for attributes
2634: permits the specification of the values for only one or two attributes
2635: in the definition of most insn patterns, as seen in the example in the
2636: next section.@refill
2637:
2638: The optional last argument of @code{define_insn} and
2639: @code{define_peephole} is a vector of expressions, each of which defines
2640: the value for a single attribute. The most general way of assigning an
2641: attribute's value is to use a @code{set} expression whose first operand is an
2642: @code{attr} expression giving the name of the attribute being set. The
2643: second operand of the @code{set} is an attribute expression
2644: (@pxref{Expressions}) giving the value of the attribute.@refill
2645:
2646: When the attribute value depends on the @samp{alternative} attribute
2647: (i.e., which is the applicable alternative in the constraint of the
2648: insn), the @code{set_attr_alternative} expression can can be used. It
2649: allows the specification of a vector of attribute expressions, one for
2650: each alternative.
2651:
2652: @findex set_attr
2653: When the generality of arbitrary attribute expressions is not required,
2654: the simpler @code{set_attr} expression can be used, which allows
2655: specifying a string giving either a single attribute value or a list
2656: of attribute values, one for each alternative.
2657:
2658: The form of each of the above specifications is shown below. In each case,
2659: @var{name} is a string specifying the attribute to be set.
2660:
2661: @table @code
2662: @item (set_attr @var{name} @var{value-string})
2663: @var{value-string} is either a string giving the desired attribute value,
2664: or a string containing a comma-separated list giving the values for
2665: succeeding alternatives. The number of elements must match the number
2666: of alternatives in the constraint of the insn pattern.
2667:
2668: Note that it may be useful to specify @samp{*} for some alternative, in
2669: which case the attribute will assume its default value for insns matching
2670: that alternative.
2671:
2672: @findex set_attr_alternative
2673: @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
2674: Depending on the alternative of the insn, the value will be one of the
2675: specified values. This is a shorthand for using a @code{cond} with
2676: tests on the @samp{alternative} attribute.
2677:
2678: @findex attr
2679: @item (set (attr @var{name}) @var{value})
2680: The first operand of this @code{set} must be the special RTL expression
2681: @code{attr}, whose sole operand is a string giving the name of the
2682: attribute being set. @var{value} is the value of the attribute.
2683: @end table
2684:
2685: The following shows three different ways of representing the same
2686: attribute value specification:
2687:
2688: @example
2689: (set_attr "type" "load,store,arith")
2690:
2691: (set_attr_alternative "type"
2692: [(const_string "load") (const_string "store")
2693: (const_string "arith")])
2694:
2695: (set (attr "type")
2696: (cond [(eq_attr "alternative" "1") (const_string "load")
2697: (eq_attr "alternative" "2") (const_string "store")]
2698: (const_string "arith")))
2699: @end example
2700:
2701: @findex define_asm_attributes
2702: The @code{define_asm_attributes} expression provides a mechanism to
2703: specify the attributes assigned to insns produced from an @code{asm}
2704: statement. It has the form:
2705:
2706: @example
2707: (define_asm_attributes [@var{attr-sets}])
2708: @end example
2709:
2710: @noindent
2711: where @var{attr-sets} is specified the same as for @code{define_insn}
2712: and @code{define_peephole} expressions.
2713:
2714: These values will typically be the ``worst case'' attribute values. For
2715: example, they might indicate that the condition code will be clobbered.
2716:
2717: A specification for a @code{length} attribute is handled specially. To
2718: compute the length of an @code{asm} insn, the length specified in the
2719: @code{define_asm_attributes} expression is multiplied by the number of
2720: machine instructions specified in the @code{asm} statement, determined
2721: by counting the number of semicolons and newlines in the string.
2722: Therefore, the value of the @code{length} attribute specified in a
2723: @code{define_asm_attributes} should be the maximum possible length of a
2724: single machine instruction.
2725:
2726: @node Attr Example, Insn Lengths, Tagging Insns, Insn Attributes
2727: @subsection Example of Attribute Specifications
2728: @cindex attribute specifications example
2729: @cindex attribute specifications
2730:
2731: The judicious use of defaulting is important in the efficient use of
2732: insn attributes. Typically, insns are divided into @dfn{types} and an
2733: attribute, customarily called @code{type}, is used to represent this
2734: value. This attribute is normally used only to define the default value
2735: for other attributes. An example will clarify this usage.
2736:
2737: Assume we have a RISC machine with a condition code and in which only
2738: full-word operations are performed in registers. Let us assume that we
2739: can divide all insns into loads, stores, (integer) arithmetic
2740: operations, floating point operations, and branches.
2741:
2742: Here we will concern ourselves with determining the effect of an insn on
2743: the condition code and will limit ourselves to the following possible
2744: effects: The condition code can be set unpredictably (clobbered), not
2745: be changed, be set to agree with the results of the operation, or only
2746: changed if the item previously set into the condition code has been
2747: modified.
2748:
2749: Here is part of a sample @file{md} file for such a machine:
2750:
2751: @example
2752: (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
2753:
2754: (define_attr "cc" "clobber,unchanged,set,change0"
2755: (cond [(eq_attr "type" "load")
2756: (const_string "change0")
2757: (eq_attr "type" "store,branch")
2758: (const_string "unchanged")
2759: (eq_attr "type" "arith")
2760: (if_then_else (match_operand:SI 0 "" "")
2761: (const_string "set")
2762: (const_string "clobber"))]
2763: (const_string "clobber")))
2764:
2765: (define_insn ""
2766: [(set (match_operand:SI 0 "general_operand" "=r,r,m")
2767: (match_operand:SI 1 "general_operand" "r,m,r"))]
2768: ""
2769: "@@
2770: move %0,%1
2771: load %0,%1
2772: store %0,%1"
2773: [(set_attr "type" "arith,load,store")])
2774: @end example
2775:
2776: Note that we assume in the above example that arithmetic operations
2777: performed on quantities smaller than a machine word clobber the condition
2778: code since they will set the condition code to a value corresponding to the
2779: full-word result.
2780:
2781: @node Insn Lengths, Delay Slots, Attr Example, Insn Attributes
2782: @subsection Computing the Length of an Insn
2783: @cindex insn lengths, computing
2784: @cindex computing the length of an insn
2785:
2786: For many machines, multiple types of branch instructions are provided, each
2787: for different length branch displacements. In most cases, the assembler
2788: will choose the correct instruction to use. However, when the assembler
2789: cannot do so, GCC can when a special attribute, the @samp{length}
2790: attribute, is defined. This attribute must be defined to have numeric
2791: values by specifying a null string in its @code{define_attr}.
2792:
2793: In the case of the @samp{length} attribute, two additional forms of
2794: arithmetic terms are allowed in test expressions:
2795:
2796: @table @code
2797: @cindex @code{match_dup} and attributes
2798: @item (match_dup @var{n})
2799: This refers to the address of operand @var{n} of the current insn, which
2800: must be a @code{label_ref}.
2801:
2802: @cindex @code{pc} and attributes
2803: @item (pc)
2804: This refers to the address of the @emph{current} insn. It might have
2805: been more consistent with other usage to make this the address of the
2806: @emph{next} insn but this would be confusing because the length of the
2807: current insn is to be computed.
2808: @end table
2809:
2810: @cindex @code{addr_vec}, length of
2811: @cindex @code{addr_diff_vec}, length of
2812: For normal insns, the length will be determined by value of the
2813: @samp{length} attribute. In the case of @code{addr_vec} and
2814: @code{addr_diff_vec} insn patterns, the length will be computed as
2815: the number of vectors multiplied by the size of each vector.@refill
2816:
2817: The following macros can be used to refine the length computation:
2818:
2819: @table @code
2820: @findex FIRST_INSN_ADDRESS
2821: @item FIRST_INSN_ADDRESS
2822: When the @code{length} insn attribute is used, this macro specifies the
2823: value to be assigned to the address of the first insn in a function. If
2824: not specified, 0 is used.
2825:
2826: @findex ADJUST_INSN_LENGTH
2827: @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
2828: If defined, modifies the length assigned to instruction @var{insn} as a
2829: function of the context in which it is used. @var{length} is an lvalue
2830: that contains the initially computed length of the insn and should be
2831: updated with the correct length of the insn. If updating is required,
2832: @var{insn} must not be a varying-length insn.
2833:
2834: This macro will normally not be required. A case in which it is
2835: required is the ROMP. On this machine, the size of an @code{addr_vec}
2836: insn must be increased by two to compensate for the fact that alignment
2837: may be required.
2838: @end table
2839:
2840: @findex get_attr_value
2841: The routine that returns the value of the @code{length} attribute,
2842: @code{get_attr_value}, can be used by the output routine to determine
2843: the form of the branch instruction to be written, as the example
2844: below illustrates.
2845:
2846: As an example of the specification of variable-length branches, consider
2847: the IBM 360. If we adopt the convention that a register will be set to
2848: the starting address of a function, we can jump to labels within 4K of
2849: the start using a four-byte instruction. Otherwise, we need a six-byte
2850: sequence to load the address from memory and then branch to it.
2851:
2852: On such a machine, a pattern for a branch instruction might be specified
2853: as follows:
2854:
2855: @example
2856: (define_insn "jump"
2857: [(set (pc)
2858: (label_ref (match_operand 0 "" "")))]
2859: ""
2860: "*
2861: @{
2862: return (get_attr_length (insn) == 4
2863: ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
2864: @}"
2865: [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
2866: (const_int 4)
2867: (const_int 6)))])
2868: @end example
2869:
2870: @node Delay Slots, Function Units, Insn Lengths, Insn Attributes
2871: @subsection Delay Slot Scheduling
2872: @cindex delay slots, defining
2873:
2874: The insn attribute mechanism can be used to specify the requirements for
2875: delay slots, if any, on a target machine. An instruction is said to
2876: require a @dfn{delay slot} if some instructions that are physically
2877: after the instruction are executed as if they were located before it.
2878: Classic examples are branch and call instructions, which often execute
2879: the following instruction before the branch or call is performed.
2880:
2881: On some machines, conditional branch instructions can optionally
2882: @dfn{annul} instructions in the delay slot. This means that the
2883: instruction will not be executed for certain branch outcomes. Both
2884: instructions that annul if the branch is true and instructions that
2885: annul if the branch is false are supported.
2886:
2887: Delay slot scheduling differs from instruction scheduling in that
2888: determining whether an instruction needs a delay slot is dependent only
2889: on the type of instruction being generated, not on data flow between the
2890: instructions. See the next section for a discussion of data-dependent
2891: instruction scheduling.
2892:
2893: @findex define_delay
2894: The requirement of an insn needing one or more delay slots is indicated
2895: via the @code{define_delay} expression. It has the following form:
2896:
2897: @example
2898: (define_delay @var{test}
2899: [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
2900: @var{delay-2} @var{annul-true-2} @var{annul-false-2}
2901: @dots{}])
2902: @end example
2903:
2904: @var{test} is an attribute test that indicates whether this
2905: @code{define_delay} applies to a particular insn. If so, the number of
2906: required delay slots is determined by the length of the vector specified
2907: as the second argument. An insn placed in delay slot @var{n} must
2908: satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
2909: attribute test that specifies which insns may be annulled if the branch
2910: is true. Similarly, @var{annul-false-n} specifies which insns in the
2911: delay slot may be annulled if the branch is false. If annulling is not
2912: supported for that delay slot, @code{(nil)} should be coded.@refill
2913:
2914: For example, in the common case where branch and call insns require
2915: a single delay slot, which may contain any insn other than a branch or
2916: call, the following would be placed in the @file{md} file:
2917:
2918: @example
2919: (define_delay (eq_attr "type" "branch,call")
2920: [(eq_attr "type" "!branch,call") (nil) (nil)])
2921: @end example
2922:
2923: Multiple @code{define_delay} expressions may be specified. In this
2924: case, each such expression specifies different delay slot requirements
2925: and there must be no insn for which tests in two @code{define_delay}
2926: expressions are both true.
2927:
2928: For example, if we have a machine that requires one delay slot for branches
2929: but two for calls, no delay slot can contain a branch or call insn,
2930: and any valid insn in the delay slot for the branch can be annulled if the
2931: branch is true, we might represent this as follows:
2932:
2933: @example
2934: (define_delay (eq_attr "type" "branch")
2935: [(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)])
2936:
2937: (define_delay (eq_attr "type" "call")
2938: [(eq_attr "type" "!branch,call") (nil) (nil)
2939: (eq_attr "type" "!branch,call") (nil) (nil)])
2940: @end example
2941:
2942: @node Function Units,, Delay Slots, Insn Attributes
2943: @subsection Specifying Function Units
2944: @cindex function units, for scheduling
2945:
2946: On most RISC machines, there are instructions whose results are not
2947: available for a specific number of cycles. Common cases are instructions
2948: that load data from memory. On many machines, a pipeline stall will result
2949: if the data is referenced too soon after the load instruction.
2950:
2951: In addition, many newer microprocessors have multiple function units, usually
2952: one for integer and one for floating point, and often will incur pipeline
2953: stalls when a result that is needed is not yet ready.
2954:
2955: The descriptions in this section allow the specification of how much
2956: time must elapse between the execution of an instruction and the time
2957: when its result is used. It also allows specification of when the
2958: execution of an instruction will delay execution of similar instructions
2959: due to function unit conflicts.
2960:
2961: For the purposes of the specifications in this section, a machine is
2962: divided into @dfn{function units}, each of which execute a specific
2963: class of instructions. Function units that accept one instruction each
2964: cycle and allow a result to be used in the succeeding instruction
2965: (usually via forwarding) need not be specified. Classic RISC
2966: microprocessors will normally have a single function unit, which we can
2967: call @samp{memory}. The newer ``superscalar'' processors will often
2968: have function units for floating point operations, usually at least
2969: a floating point adder and multiplier.
2970:
2971: @findex define_function_unit
2972: Each usage of a function units by a class of insns is specified with a
2973: @code{define_function_unit} expression, which looks like this:
2974:
2975: @example
2976: (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
2977: @var{test} @var{ready-delay} @var{busy-delay}
2978: [@var{conflict-list}])
2979: @end example
2980:
2981: @var{name} is a string giving the name of the function unit.
2982:
2983: @var{multiplicity} is an integer specifying the number of identical
2984: units in the processor. If more than one unit is specified, they will
2985: be scheduled independently. Only truly independent units should be
2986: counted; a pipelined unit should be specified as a single unit. (The
2987: only common example of a machine that has multiple function units for a
2988: single instruction class that are truly independent and not pipelined
2989: are the two multiply and two increment units of the CDC 6600.)
2990:
2991: @var{simultaneity} specifies the maximum number of insns that can be
2992: executing in each instance of the function unit simultaneously or zero
2993: if the unit is pipelined and has no limit.
2994:
2995: All @code{define_function_unit} definitions referring to function unit
2996: @var{name} must have the same name and values for @var{multiplicity} and
2997: @var{simultaneity}.
2998:
2999: @var{test} is an attribute test that selects the insns we are describing
3000: in this definition. Note that an insn may use more than one function
3001: unit and a function unit may be specified in more than one
3002: @code{define_function_unit}.
3003:
3004: @var{ready-delay} is an integer that specifies the number of cycles
3005: after which the result of the instruction can be used without
3006: introducing any stalls.
3007:
3008: @var{busy-delay} is an integer that represents the default cost if an
3009: insn is scheduled for this unit while the unit is active with another
3010: insn. If @var{simultaneity} is zero, this specification is ignored.
3011: Otherwise, a zero value indicates that these insns execute on @var{name}
3012: in a fully pipelined fashion, even if @var{simultaneity} is non-zero. A
3013: non-zero value indicates that scheduling a new insn on this unit while
3014: another is active will incur a cost. A cost of two indicates a single
3015: cycle delay. For a normal non-pipelined function unit, @var{busy-delay}
3016: will be twice @var{ready-delay}.
3017:
3018: @var{conflict-list} is an optional list giving detailed conflict costs
3019: for this unit. If specified, it is a list of condition test expressions
3020: which are applied to insns already executing in @var{name}. For each
3021: insn that is in the list, @var{busy-delay} will be used for the conflict
3022: cost, while a value of zero will be used for insns not in the list.
3023:
3024: Typical uses of this vector are where a floating point function unit can
3025: pipeline either single- or double-precision operations, but not both, or
3026: where a memory unit can pipeline loads, but not stores, etc.
3027:
3028: As an example, consider a classic RISC machine where the result of a
3029: load instruction is not available for two cycles (a single ``delay''
3030: instruction is required) and where only one load instruction can be executed
3031: simultaneously. This would be specified as:
3032:
3033: @example
3034: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 4)
3035: @end example
3036:
3037: For the case of a floating point function unit that can pipeline either
3038: single or double precision, but not both, the following could be specified:
3039:
3040: @example
3041: (define_function_unit
3042: "fp" 1 1 (eq_attr "type" "sp_fp") 4 8 (eq_attr "type" "dp_fp")]
3043: (define_function_unit
3044: "fp" 1 1 (eq_attr "type" "dp_fp") 4 8 (eq_attr "type" "sp_fp")]
3045: @end example
3046:
3047: @strong{Note:} No code currently exists to avoid function unit
3048: conflicts, only data conflicts. Hence @var{multiplicity},
3049: @var{simultaneity}, @var{busy-cost}, and @var{conflict-list} are
3050: currently ignored. When such code is written, it is possible that the
3051: specifications for these values may be changed. It has recently come to
3052: our attention that these specifications may not allow modeling of some
3053: of the newer ``superscalar'' processors that have insns using multiple
3054: pipelined units. These insns will cause a potential conflict for the
3055: second unit used during their execution and there is no way of
3056: representing that conflict. We welcome any examples of how function
3057: unit conflicts work in such processors and suggestions for their
3058: representation.
3059: @end ifset
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