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1.1 root 1: @c Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc.
2: @c This is part of the GCC manual.
3: @c For copying conditions, see the file gcc.texi.
4:
5: @ifset INTERNALS
1.1.1.3 root 6: @node Machine Desc
1.1 root 7: @chapter Machine Descriptions
8: @cindex machine descriptions
9:
10: A machine description has two parts: a file of instruction patterns
11: (@file{.md} file) and a C header file of macro definitions.
12:
13: The @file{.md} file for a target machine contains a pattern for each
14: instruction that the target machine supports (or at least each instruction
15: that is worth telling the compiler about). It may also contain comments.
16: A semicolon causes the rest of the line to be a comment, unless the semicolon
17: is inside a quoted string.
18:
19: See the next chapter for information on the C header file.
20:
21: @menu
22: * Patterns:: How to write instruction patterns.
23: * Example:: An explained example of a @code{define_insn} pattern.
24: * RTL Template:: The RTL template defines what insns match a pattern.
25: * Output Template:: The output template says how to make assembler code
26: from such an insn.
27: * Output Statement:: For more generality, write C code to output
28: the assembler code.
29: * Constraints:: When not all operands are general operands.
30: * Standard Names:: Names mark patterns to use for code generation.
31: * Pattern Ordering:: When the order of patterns makes a difference.
32: * Dependent Patterns:: Having one pattern may make you need another.
33: * Jump Patterns:: Special considerations for patterns for jump insns.
34: * Insn Canonicalizations::Canonicalization of Instructions
35: * Peephole Definitions::Defining machine-specific peephole optimizations.
36: * Expander Definitions::Generating a sequence of several RTL insns
37: for a standard operation.
38: * Insn Splitting:: Splitting Instructions into Multiple Instructions
39: * Insn Attributes:: Specifying the value of attributes for generated insns.
40: @end menu
41:
42: @node Patterns, Example, Machine Desc, Machine Desc
43: @section Everything about Instruction Patterns
44: @cindex patterns
45: @cindex instruction patterns
46:
47: @findex define_insn
48: Each instruction pattern contains an incomplete RTL expression, with pieces
49: to be filled in later, operand constraints that restrict how the pieces can
50: be filled in, and an output pattern or C code to generate the assembler
51: output, all wrapped up in a @code{define_insn} expression.
52:
53: A @code{define_insn} is an RTL expression containing four or five operands:
54:
55: @enumerate
56: @item
57: An optional name. The presence of a name indicate that this instruction
58: pattern can perform a certain standard job for the RTL-generation
59: pass of the compiler. This pass knows certain names and will use
60: the instruction patterns with those names, if the names are defined
61: in the machine description.
62:
63: The absence of a name is indicated by writing an empty string
64: where the name should go. Nameless instruction patterns are never
65: used for generating RTL code, but they may permit several simpler insns
66: to be combined later on.
67:
68: Names that are not thus known and used in RTL-generation have no
69: effect; they are equivalent to no name at all.
70:
71: @item
72: The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
73: RTL expressions which show what the instruction should look like. It is
74: incomplete because it may contain @code{match_operand},
75: @code{match_operator}, and @code{match_dup} expressions that stand for
76: operands of the instruction.
77:
78: If the vector has only one element, that element is the template for the
79: instruction pattern. If the vector has multiple elements, then the
80: instruction pattern is a @code{parallel} expression containing the
81: elements described.
82:
83: @item
84: @cindex pattern conditions
85: @cindex conditions, in patterns
86: A condition. This is a string which contains a C expression that is
87: the final test to decide whether an insn body matches this pattern.
88:
89: @cindex named patterns and conditions
90: For a named pattern, the condition (if present) may not depend on
91: the data in the insn being matched, but only the target-machine-type
92: flags. The compiler needs to test these conditions during
93: initialization in order to learn exactly which named instructions are
94: available in a particular run.
95:
96: @findex operands
97: For nameless patterns, the condition is applied only when matching an
98: individual insn, and only after the insn has matched the pattern's
99: recognition template. The insn's operands may be found in the vector
100: @code{operands}.
101:
102: @item
103: The @dfn{output template}: a string that says how to output matching
104: insns as assembler code. @samp{%} in this string specifies where
105: to substitute the value of an operand. @xref{Output Template}.
106:
107: When simple substitution isn't general enough, you can specify a piece
108: of C code to compute the output. @xref{Output Statement}.
109:
110: @item
111: Optionally, a vector containing the values of attributes for insns matching
112: this pattern. @xref{Insn Attributes}.
113: @end enumerate
114:
115: @node Example, RTL Template, Patterns, Machine Desc
116: @section Example of @code{define_insn}
117: @cindex @code{define_insn} example
118:
119: Here is an actual example of an instruction pattern, for the 68000/68020.
120:
121: @example
122: (define_insn "tstsi"
123: [(set (cc0)
124: (match_operand:SI 0 "general_operand" "rm"))]
125: ""
126: "*
127: @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
128: return \"tstl %0\";
129: return \"cmpl #0,%0\"; @}")
130: @end example
131:
132: This is an instruction that sets the condition codes based on the value of
133: a general operand. It has no condition, so any insn whose RTL description
134: has the form shown may be handled according to this pattern. The name
135: @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
136: pass that, when it is necessary to test such a value, an insn to do so
137: can be constructed using this pattern.
138:
139: The output control string is a piece of C code which chooses which
140: output template to return based on the kind of operand and the specific
141: type of CPU for which code is being generated.
142:
143: @samp{"rm"} is an operand constraint. Its meaning is explained below.
144:
145: @node RTL Template, Output Template, Example, Machine Desc
146: @section RTL Template for Generating and Recognizing Insns
147: @cindex RTL insn template
148: @cindex generating insns
149: @cindex insns, generating
150: @cindex recognizing insns
151: @cindex insns, recognizing
152:
153: The RTL template is used to define which insns match the particular pattern
154: and how to find their operands. For named patterns, the RTL template also
155: says how to construct an insn from specified operands.
156:
157: Construction involves substituting specified operands into a copy of the
158: template. Matching involves determining the values that serve as the
159: operands in the insn being matched. Both of these activities are
160: controlled by special expression types that direct matching and
161: substitution of the operands.
162:
163: @table @code
164: @findex match_operand
165: @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
166: This expression is a placeholder for operand number @var{n} of
167: the insn. When constructing an insn, operand number @var{n}
168: will be substituted at this point. When matching an insn, whatever
169: appears at this position in the insn will be taken as operand
170: number @var{n}; but it must satisfy @var{predicate} or this instruction
171: pattern will not match at all.
172:
173: Operand numbers must be chosen consecutively counting from zero in
174: each instruction pattern. There may be only one @code{match_operand}
175: expression in the pattern for each operand number. Usually operands
176: are numbered in the order of appearance in @code{match_operand}
177: expressions.
178:
179: @var{predicate} is a string that is the name of a C function that accepts two
180: arguments, an expression and a machine mode. During matching, the
181: function will be called with the putative operand as the expression and
182: @var{m} as the mode argument (if @var{m} is not specified,
183: @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
184: any mode). If it returns zero, this instruction pattern fails to match.
185: @var{predicate} may be an empty string; then it means no test is to be done
186: on the operand, so anything which occurs in this position is valid.
187:
188: Most of the time, @var{predicate} will reject modes other than @var{m}---but
189: not always. For example, the predicate @code{address_operand} uses
190: @var{m} as the mode of memory ref that the address should be valid for.
191: Many predicates accept @code{const_int} nodes even though their mode is
192: @code{VOIDmode}.
193:
194: @var{constraint} controls reloading and the choice of the best register
195: class to use for a value, as explained later (@pxref{Constraints}).
196:
197: People are often unclear on the difference between the constraint and the
198: predicate. The predicate helps decide whether a given insn matches the
199: pattern. The constraint plays no role in this decision; instead, it
200: controls various decisions in the case of an insn which does match.
201:
202: @findex general_operand
203: On CISC machines, @var{predicate} is most often @code{"general_operand"}.
204: This function checks that the putative operand is either a constant, a
205: register or a memory reference, and that it is valid for mode @var{m}.
206:
207: @findex register_operand
208: For an operand that must be a register, @var{predicate} should be
209: @code{"register_operand"}. It would be valid to use
210: @code{"general_operand"}, since the reload pass would copy any
211: non-register operands through registers, but this would make GNU CC do
212: extra work, it would prevent invariant operands (such as constant) from
213: being removed from loops, and it would prevent the register allocator
214: from doing the best possible job. On RISC machines, it is usually most
215: efficient to allow @var{predicate} to accept only objects that the
216: constraints allow.
217:
218: @findex immediate_operand
219: For an operand that must be a constant, either use
220: @code{"immediate_operand"} for @var{predicate}, or make the instruction
221: pattern's extra condition require a constant, or both. You cannot
222: expect the constraints to do this work! If the constraints allow only
223: constants, but the predicate allows something else, the compiler will
224: crash when that case arises.
225:
226: @findex match_scratch
227: @item (match_scratch:@var{m} @var{n} @var{constraint})
228: This expression is also a placeholder for operand number @var{n}
229: and indicates that operand must be a @code{scratch} or @code{reg}
230: expression.
231:
232: When matching patterns, this is completely equivalent to
233:
234: @example
235: (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
236: @end example
237:
238: but, when generating RTL, it produces a (@code{scratch}:@var{m})
239: expression.
240:
241: If the last few expressions in a @code{parallel} are @code{clobber}
242: expressions whose operands are either a hard register or
243: @code{match_scratch}, the combiner can add them when necessary.
244: @xref{Side Effects}.
245:
246: @findex match_dup
247: @item (match_dup @var{n})
248: This expression is also a placeholder for operand number @var{n}.
249: It is used when the operand needs to appear more than once in the
250: insn.
251:
252: In construction, @code{match_dup} behaves exactly like
253: @code{match_operand}: the operand is substituted into the insn being
254: constructed. But in matching, @code{match_dup} behaves differently.
255: It assumes that operand number @var{n} has already been determined by
256: a @code{match_operand} appearing earlier in the recognition template,
257: and it matches only an identical-looking expression.
258:
259: @findex match_operator
260: @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
261: This pattern is a kind of placeholder for a variable RTL expression
262: code.
263:
264: When constructing an insn, it stands for an RTL expression whose
265: expression code is taken from that of operand @var{n}, and whose
266: operands are constructed from the patterns @var{operands}.
267:
268: When matching an expression, it matches an expression if the function
269: @var{predicate} returns nonzero on that expression @emph{and} the
270: patterns @var{operands} match the operands of the expression.
271:
272: Suppose that the function @code{commutative_operator} is defined as
273: follows, to match any expression whose operator is one of the
274: commutative arithmetic operators of RTL and whose mode is @var{mode}:
275:
276: @example
277: int
278: commutative_operator (x, mode)
279: rtx x;
280: enum machine_mode mode;
281: @{
282: enum rtx_code code = GET_CODE (x);
283: if (GET_MODE (x) != mode)
284: return 0;
285: return GET_RTX_CLASS (code) == 'c' || code == EQ || code == NE;
286: @}
287: @end example
288:
289: Then the following pattern will match any RTL expression consisting
290: of a commutative operator applied to two general operands:
291:
292: @example
293: (match_operator:SI 3 "commutative_operator"
294: [(match_operand:SI 1 "general_operand" "g")
295: (match_operand:SI 2 "general_operand" "g")])
296: @end example
297:
298: Here the vector @code{[@var{operands}@dots{}]} contains two patterns
299: because the expressions to be matched all contain two operands.
300:
301: When this pattern does match, the two operands of the commutative
302: operator are recorded as operands 1 and 2 of the insn. (This is done
303: by the two instances of @code{match_operand}.) Operand 3 of the insn
304: will be the entire commutative expression: use @code{GET_CODE
305: (operands[3])} to see which commutative operator was used.
306:
307: The machine mode @var{m} of @code{match_operator} works like that of
308: @code{match_operand}: it is passed as the second argument to the
309: predicate function, and that function is solely responsible for
310: deciding whether the expression to be matched ``has'' that mode.
311:
312: When constructing an insn, argument 3 of the gen-function will specify
313: the operation (i.e. the expression code) for the expression to be
314: made. It should be an RTL expression, whose expression code is copied
315: into a new expression whose operands are arguments 1 and 2 of the
316: gen-function. The subexpressions of argument 3 are not used;
317: only its expression code matters.
318:
319: When @code{match_operator} is used in a pattern for matching an insn,
320: it usually best if the operand number of the @code{match_operator}
321: is higher than that of the actual operands of the insn. This improves
322: register allocation because the register allocator often looks at
323: operands 1 and 2 of insns to see if it can do register tying.
324:
325: There is no way to specify constraints in @code{match_operator}. The
326: operand of the insn which corresponds to the @code{match_operator}
327: never has any constraints because it is never reloaded as a whole.
328: However, if parts of its @var{operands} are matched by
329: @code{match_operand} patterns, those parts may have constraints of
330: their own.
331:
1.1.1.4 ! root 332: @findex match_op_dup
! 333: @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
! 334: Like @code{match_dup}, except that it applies to operators instead of
! 335: operands. When constructing an insn, operand number @var{n} will be
! 336: substituted at this point. But in matching, @code{match_op_dup} behaves
! 337: differently. It assumes that operand number @var{n} has already been
! 338: determined by a @code{match_operator} appearing earlier in the
! 339: recognition template, and it matches only an identical-looking
! 340: expression.
! 341:
1.1.1.3 root 342: @findex match_parallel
343: @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
344: This pattern is a placeholder for an insn that consists of a
345: @code{parallel} expression with a variable number of elements. This
346: expression should only appear at the top level of an insn pattern.
347:
348: When constructing an insn, operand number @var{n} will be substituted at
349: this point. When matching an insn, it matches if the body of the insn
350: is a @code{parallel} expression with at least as many elements as the
351: vector of @var{subpat} expressions in the @code{match_parallel}, if each
352: @var{subpat} matches the corresponding element of the @code{parallel},
353: @emph{and} the function @var{predicate} returns nonzero on the
354: @code{parallel} that is the body of the insn. It is the responsibility
355: of the predicate to validate elements of the @code{parallel} beyond
356: those listed in the @code{match_parallel}.@refill
357:
358: A typical use of @code{match_parallel} is to match load and store
359: multiple expressions, which can contains a variable number of elements
360: in a @code{parallel}. For example,
361:
362: @example
363: (define_insn ""
364: [(match_parallel 0 "load_multiple_operation"
1.1.1.4 ! root 365: [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
! 366: (match_operand:SI 2 "memory_operand" "m"))
! 367: (use (reg:SI 179))
! 368: (clobber (reg:SI 179))])]
1.1.1.3 root 369: ""
370: "loadm 0,0,%1,%2")
371: @end example
372:
373: This example comes from @file{a29k.md}. The function
374: @code{load_multiple_operations} is defined in @file{a29k.c} and checks
375: that subsequent elements in the @code{parallel} are the same as the
376: @code{set} in the pattern, except that they are referencing subsequent
377: registers and memory locations.
378:
379: An insn that matches this pattern might look like:
380:
381: @example
382: (parallel [(set (reg:SI 20) (mem:SI (reg:SI 100)))
1.1.1.4 ! root 383: (use (reg:SI 179))
! 384: (clobber (reg:SI 179))
! 385: (set (reg:SI 21) (mem:SI (plus:SI (reg:SI 100) (const_int 4))))
! 386: (set (reg:SI 22) (mem:SI (plus:SI (reg:SI 100) (const_int 8))))])
1.1.1.3 root 387: @end example
388:
1.1.1.4 ! root 389: @findex match_par_dup
! 390: @item (match_par_dup @var{n} [@var{subpat}@dots{}])
! 391: Like @code{match_op_dup}, but for @code{match_parallel} instead of
! 392: @code{match_operator}.
! 393:
1.1 root 394: @findex address
395: @item (address (match_operand:@var{m} @var{n} "address_operand" ""))
396: This complex of expressions is a placeholder for an operand number
397: @var{n} in a ``load address'' instruction: an operand which specifies
398: a memory location in the usual way, but for which the actual operand
399: value used is the address of the location, not the contents of the
400: location.
401:
402: @code{address} expressions never appear in RTL code, only in machine
403: descriptions. And they are used only in machine descriptions that do
404: not use the operand constraint feature. When operand constraints are
405: in use, the letter @samp{p} in the constraint serves this purpose.
406:
407: @var{m} is the machine mode of the @emph{memory location being
408: addressed}, not the machine mode of the address itself. That mode is
409: always the same on a given target machine (it is @code{Pmode}, which
410: normally is @code{SImode}), so there is no point in mentioning it;
411: thus, no machine mode is written in the @code{address} expression. If
412: some day support is added for machines in which addresses of different
413: kinds of objects appear differently or are used differently (such as
414: the PDP-10), different formats would perhaps need different machine
415: modes and these modes might be written in the @code{address}
416: expression.
417: @end table
418:
419: @node Output Template, Output Statement, RTL Template, Machine Desc
420: @section Output Templates and Operand Substitution
421: @cindex output templates
422: @cindex operand substitution
423:
424: @cindex @samp{%} in template
425: @cindex percent sign
426: The @dfn{output template} is a string which specifies how to output the
427: assembler code for an instruction pattern. Most of the template is a
428: fixed string which is output literally. The character @samp{%} is used
429: to specify where to substitute an operand; it can also be used to
430: identify places where different variants of the assembler require
431: different syntax.
432:
433: In the simplest case, a @samp{%} followed by a digit @var{n} says to output
434: operand @var{n} at that point in the string.
435:
436: @samp{%} followed by a letter and a digit says to output an operand in an
437: alternate fashion. Four letters have standard, built-in meanings described
438: below. The machine description macro @code{PRINT_OPERAND} can define
439: additional letters with nonstandard meanings.
440:
441: @samp{%c@var{digit}} can be used to substitute an operand that is a
442: constant value without the syntax that normally indicates an immediate
443: operand.
444:
445: @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
446: the constant is negated before printing.
447:
448: @samp{%a@var{digit}} can be used to substitute an operand as if it were a
449: memory reference, with the actual operand treated as the address. This may
450: be useful when outputting a ``load address'' instruction, because often the
451: assembler syntax for such an instruction requires you to write the operand
452: as if it were a memory reference.
453:
454: @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
455: instruction.
456:
1.1.1.4 ! root 457: @samp{%=} outputs a number which is unique to each instruction in the
! 458: entire compilation. This is useful for making local labels to be
! 459: referred to more than once in a single template that generates multiple
! 460: assembler instructions.
! 461:
1.1 root 462: @samp{%} followed by a punctuation character specifies a substitution that
463: does not use an operand. Only one case is standard: @samp{%%} outputs a
464: @samp{%} into the assembler code. Other nonstandard cases can be
465: defined in the @code{PRINT_OPERAND} macro. You must also define
466: which punctuation characters are valid with the
467: @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
468:
469: @cindex \
470: @cindex backslash
471: The template may generate multiple assembler instructions. Write the text
472: for the instructions, with @samp{\;} between them.
473:
474: @cindex matching operands
475: When the RTL contains two operands which are required by constraint to match
476: each other, the output template must refer only to the lower-numbered operand.
477: Matching operands are not always identical, and the rest of the compiler
478: arranges to put the proper RTL expression for printing into the lower-numbered
479: operand.
480:
481: One use of nonstandard letters or punctuation following @samp{%} is to
482: distinguish between different assembler languages for the same machine; for
483: example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
484: requires periods in most opcode names, while MIT syntax does not. For
485: example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
486: syntax. The same file of patterns is used for both kinds of output syntax,
487: but the character sequence @samp{%.} is used in each place where Motorola
488: syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
489: defines the sequence to output a period; the macro for MIT syntax defines
490: it to do nothing.
491:
492: @node Output Statement, Constraints, Output Template, Machine Desc
493: @section C Statements for Generating Assembler Output
494: @cindex output statements
495: @cindex C statements for assembler output
496: @cindex generating assembler output
497:
498: Often a single fixed template string cannot produce correct and efficient
499: assembler code for all the cases that are recognized by a single
500: instruction pattern. For example, the opcodes may depend on the kinds of
501: operands; or some unfortunate combinations of operands may require extra
502: machine instructions.
503:
504: If the output control string starts with a @samp{@@}, then it is actually
505: a series of templates, each on a separate line. (Blank lines and
506: leading spaces and tabs are ignored.) The templates correspond to the
507: pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
508: if a target machine has a two-address add instruction @samp{addr} to add
509: into a register and another @samp{addm} to add a register to memory, you
510: might write this pattern:
511:
512: @example
513: (define_insn "addsi3"
1.1.1.3 root 514: [(set (match_operand:SI 0 "general_operand" "=r,m")
1.1 root 515: (plus:SI (match_operand:SI 1 "general_operand" "0,0")
516: (match_operand:SI 2 "general_operand" "g,r")))]
517: ""
518: "@@
1.1.1.4 ! root 519: addr %2,%0
! 520: addm %2,%0")
1.1 root 521: @end example
522:
523: @cindex @code{*} in template
524: @cindex asterisk in template
525: If the output control string starts with a @samp{*}, then it is not an
526: output template but rather a piece of C program that should compute a
527: template. It should execute a @code{return} statement to return the
528: template-string you want. Most such templates use C string literals, which
529: require doublequote characters to delimit them. To include these
530: doublequote characters in the string, prefix each one with @samp{\}.
531:
532: The operands may be found in the array @code{operands}, whose C data type
533: is @code{rtx []}.
534:
535: It is very common to select different ways of generating assembler code
536: based on whether an immediate operand is within a certain range. Be
537: careful when doing this, because the result of @code{INTVAL} is an
538: integer on the host machine. If the host machine has more bits in an
539: @code{int} than the target machine has in the mode in which the constant
540: will be used, then some of the bits you get from @code{INTVAL} will be
541: superfluous. For proper results, you must carefully disregard the
542: values of those bits.
543:
544: @findex output_asm_insn
545: It is possible to output an assembler instruction and then go on to output
546: or compute more of them, using the subroutine @code{output_asm_insn}. This
547: receives two arguments: a template-string and a vector of operands. The
548: vector may be @code{operands}, or it may be another array of @code{rtx}
549: that you declare locally and initialize yourself.
550:
551: @findex which_alternative
552: When an insn pattern has multiple alternatives in its constraints, often
553: the appearance of the assembler code is determined mostly by which alternative
554: was matched. When this is so, the C code can test the variable
555: @code{which_alternative}, which is the ordinal number of the alternative
556: that was actually satisfied (0 for the first, 1 for the second alternative,
557: etc.).
558:
559: For example, suppose there are two opcodes for storing zero, @samp{clrreg}
560: for registers and @samp{clrmem} for memory locations. Here is how
561: a pattern could use @code{which_alternative} to choose between them:
562:
563: @example
564: (define_insn ""
1.1.1.3 root 565: [(set (match_operand:SI 0 "general_operand" "=r,m")
1.1 root 566: (const_int 0))]
567: ""
568: "*
569: return (which_alternative == 0
570: ? \"clrreg %0\" : \"clrmem %0\");
571: ")
572: @end example
573:
574: The example above, where the assembler code to generate was
575: @emph{solely} determined by the alternative, could also have been specified
576: as follows, having the output control string start with a @samp{@@}:
577:
578: @example
579: (define_insn ""
1.1.1.3 root 580: [(set (match_operand:SI 0 "general_operand" "=r,m")
1.1 root 581: (const_int 0))]
582: ""
583: "@@
584: clrreg %0
585: clrmem %0")
586: @end example
587:
588: @node Constraints, Standard Names, Output Statement, Machine Desc
589: @section Operand Constraints
590: @cindex operand constraints
591: @cindex constraints
592:
593: Each @code{match_operand} in an instruction pattern can specify a
594: constraint for the type of operands allowed. Constraints can say whether
595: an operand may be in a register, and which kinds of register; whether the
596: operand can be a memory reference, and which kinds of address; whether the
597: operand may be an immediate constant, and which possible values it may
598: have. Constraints can also require two operands to match.
599:
600: @menu
601: * Simple Constraints:: Basic use of constraints.
602: * Multi-Alternative:: When an insn has two alternative constraint-patterns.
603: * Class Preferences:: Constraints guide which hard register to put things in.
604: * Modifiers:: More precise control over effects of constraints.
605: * No Constraints:: Describing a clean machine without constraints.
606: @end menu
607:
608: @node Simple Constraints, Multi-Alternative, Constraints, Constraints
609: @subsection Simple Constraints
610: @cindex simple constraints
611:
612: The simplest kind of constraint is a string full of letters, each of
613: which describes one kind of operand that is permitted. Here are
614: the letters that are allowed:
615:
616: @table @asis
617: @cindex @samp{m} in constraint
618: @cindex memory references in constraints
619: @item @samp{m}
620: A memory operand is allowed, with any kind of address that the machine
621: supports in general.
622:
623: @cindex offsettable address
624: @cindex @samp{o} in constraint
625: @item @samp{o}
626: A memory operand is allowed, but only if the address is
627: @dfn{offsettable}. This means that adding a small integer (actually,
628: the width in bytes of the operand, as determined by its machine mode)
629: may be added to the address and the result is also a valid memory
630: address.
631:
632: @cindex autoincrement/decrement addressing
633: For example, an address which is constant is offsettable; so is an
634: address that is the sum of a register and a constant (as long as a
635: slightly larger constant is also within the range of address-offsets
636: supported by the machine); but an autoincrement or autodecrement
637: address is not offsettable. More complicated indirect/indexed
638: addresses may or may not be offsettable depending on the other
639: addressing modes that the machine supports.
640:
641: Note that in an output operand which can be matched by another
642: operand, the constraint letter @samp{o} is valid only when accompanied
643: by both @samp{<} (if the target machine has predecrement addressing)
644: and @samp{>} (if the target machine has preincrement addressing).
645:
646: @cindex @samp{V} in constraint
647: @item @samp{V}
648: A memory operand that is not offsettable. In other words, anything that
649: would fit the @samp{m} constraint but not the @samp{o} constraint.
650:
651: @cindex @samp{<} in constraint
652: @item @samp{<}
653: A memory operand with autodecrement addressing (either predecrement or
654: postdecrement) is allowed.
655:
656: @cindex @samp{>} in constraint
657: @item @samp{>}
658: A memory operand with autoincrement addressing (either preincrement or
659: postincrement) is allowed.
660:
661: @cindex @samp{r} in constraint
662: @cindex registers in constraints
663: @item @samp{r}
664: A register operand is allowed provided that it is in a general
665: register.
666:
667: @cindex @samp{d} in constraint
668: @item @samp{d}, @samp{a}, @samp{f}, @dots{}
669: Other letters can be defined in machine-dependent fashion to stand for
670: particular classes of registers. @samp{d}, @samp{a} and @samp{f} are
671: defined on the 68000/68020 to stand for data, address and floating
672: point registers.
673:
674: @cindex constants in constraints
675: @cindex @samp{i} in constraint
676: @item @samp{i}
677: An immediate integer operand (one with constant value) is allowed.
678: This includes symbolic constants whose values will be known only at
679: assembly time.
680:
681: @cindex @samp{n} in constraint
682: @item @samp{n}
683: An immediate integer operand with a known numeric value is allowed.
684: Many systems cannot support assembly-time constants for operands less
685: than a word wide. Constraints for these operands should use @samp{n}
686: rather than @samp{i}.
687:
688: @cindex @samp{I} in constraint
689: @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
690: Other letters in the range @samp{I} through @samp{P} may be defined in
691: a machine-dependent fashion to permit immediate integer operands with
692: explicit integer values in specified ranges. For example, on the
693: 68000, @samp{I} is defined to stand for the range of values 1 to 8.
694: This is the range permitted as a shift count in the shift
695: instructions.
696:
697: @cindex @samp{E} in constraint
698: @item @samp{E}
699: An immediate floating operand (expression code @code{const_double}) is
700: allowed, but only if the target floating point format is the same as
701: that of the host machine (on which the compiler is running).
702:
703: @cindex @samp{F} in constraint
704: @item @samp{F}
705: An immediate floating operand (expression code @code{const_double}) is
706: allowed.
707:
708: @cindex @samp{G} in constraint
709: @cindex @samp{H} in constraint
710: @item @samp{G}, @samp{H}
711: @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
712: permit immediate floating operands in particular ranges of values.
713:
714: @cindex @samp{s} in constraint
715: @item @samp{s}
716: An immediate integer operand whose value is not an explicit integer is
717: allowed.
718:
719: This might appear strange; if an insn allows a constant operand with a
720: value not known at compile time, it certainly must allow any known
721: value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
722: better code to be generated.
723:
724: For example, on the 68000 in a fullword instruction it is possible to
725: use an immediate operand; but if the immediate value is between -128
726: and 127, better code results from loading the value into a register and
727: using the register. This is because the load into the register can be
728: done with a @samp{moveq} instruction. We arrange for this to happen
729: by defining the letter @samp{K} to mean ``any integer outside the
730: range -128 to 127'', and then specifying @samp{Ks} in the operand
731: constraints.
732:
733: @cindex @samp{g} in constraint
734: @item @samp{g}
735: Any register, memory or immediate integer operand is allowed, except for
736: registers that are not general registers.
737:
738: @cindex @samp{X} in constraint
739: @item @samp{X}
740: Any operand whatsoever is allowed, even if it does not satisfy
741: @code{general_operand}. This is normally used in the constraint of
742: a @code{match_scratch} when certain alternatives will not actually
743: require a scratch register.
744:
745: @cindex @samp{0} in constraint
746: @cindex digits in constraint
747: @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
748: An operand that matches the specified operand number is allowed. If a
749: digit is used together with letters within the same alternative, the
750: digit should come last.
751:
752: @cindex matching constraint
753: @cindex constraint, matching
754: This is called a @dfn{matching constraint} and what it really means is
755: that the assembler has only a single operand that fills two roles
756: considered separate in the RTL insn. For example, an add insn has two
1.1.1.3 root 757: input operands and one output operand in the RTL, but on most CISC
758: machines an add instruction really has only two operands, one of them an
759: input-output operand:
760:
761: @example
762: addl #35,r12
763: @end example
1.1 root 764:
1.1.1.3 root 765: Matching constraints are used in these circumstances.
1.1 root 766: More precisely, the two operands that match must include one input-only
767: operand and one output-only operand. Moreover, the digit must be a
768: smaller number than the number of the operand that uses it in the
769: constraint.
770:
771: For operands to match in a particular case usually means that they
772: are identical-looking RTL expressions. But in a few special cases
773: specific kinds of dissimilarity are allowed. For example, @code{*x}
774: as an input operand will match @code{*x++} as an output operand.
775: For proper results in such cases, the output template should always
776: use the output-operand's number when printing the operand.
777:
778: @cindex load address instruction
779: @cindex push address instruction
780: @cindex address constraints
781: @cindex @samp{p} in constraint
782: @item @samp{p}
783: An operand that is a valid memory address is allowed. This is
784: for ``load address'' and ``push address'' instructions.
785:
786: @findex address_operand
787: @samp{p} in the constraint must be accompanied by @code{address_operand}
788: as the predicate in the @code{match_operand}. This predicate interprets
789: the mode specified in the @code{match_operand} as the mode of the memory
790: reference for which the address would be valid.
791:
792: @cindex extensible constraints
793: @cindex @samp{Q}, in constraint
794: @item @samp{Q}, @samp{R}, @samp{S}, @dots{} @samp{U}
795: Letters in the range @samp{Q} through @samp{U} may be defined in a
796: machine-dependent fashion to stand for arbitrary operand types.
797: The machine description macro @code{EXTRA_CONSTRAINT} is passed the
798: operand as its first argument and the constraint letter as its
799: second operand.
800:
801: A typical use for this would be to distinguish certain types of
802: memory references that affect other insn operands.
803:
804: Do not define these constraint letters to accept register references
805: (@code{reg}); the reload pass does not expect this and would not handle
806: it properly.
807: @end table
808:
809: In order to have valid assembler code, each operand must satisfy
810: its constraint. But a failure to do so does not prevent the pattern
811: from applying to an insn. Instead, it directs the compiler to modify
812: the code so that the constraint will be satisfied. Usually this is
813: done by copying an operand into a register.
814:
815: Contrast, therefore, the two instruction patterns that follow:
816:
817: @example
818: (define_insn ""
1.1.1.3 root 819: [(set (match_operand:SI 0 "general_operand" "=r")
1.1 root 820: (plus:SI (match_dup 0)
821: (match_operand:SI 1 "general_operand" "r")))]
822: ""
823: "@dots{}")
824: @end example
825:
826: @noindent
827: which has two operands, one of which must appear in two places, and
828:
829: @example
830: (define_insn ""
1.1.1.3 root 831: [(set (match_operand:SI 0 "general_operand" "=r")
1.1 root 832: (plus:SI (match_operand:SI 1 "general_operand" "0")
833: (match_operand:SI 2 "general_operand" "r")))]
834: ""
835: "@dots{}")
836: @end example
837:
838: @noindent
839: which has three operands, two of which are required by a constraint to be
840: identical. If we are considering an insn of the form
841:
842: @example
843: (insn @var{n} @var{prev} @var{next}
844: (set (reg:SI 3)
845: (plus:SI (reg:SI 6) (reg:SI 109)))
846: @dots{})
847: @end example
848:
849: @noindent
850: the first pattern would not apply at all, because this insn does not
851: contain two identical subexpressions in the right place. The pattern would
852: say, ``That does not look like an add instruction; try other patterns.''
853: The second pattern would say, ``Yes, that's an add instruction, but there
854: is something wrong with it.'' It would direct the reload pass of the
855: compiler to generate additional insns to make the constraint true. The
856: results might look like this:
857:
858: @example
859: (insn @var{n2} @var{prev} @var{n}
860: (set (reg:SI 3) (reg:SI 6))
861: @dots{})
862:
863: (insn @var{n} @var{n2} @var{next}
864: (set (reg:SI 3)
865: (plus:SI (reg:SI 3) (reg:SI 109)))
866: @dots{})
867: @end example
868:
869: It is up to you to make sure that each operand, in each pattern, has
870: constraints that can handle any RTL expression that could be present for
871: that operand. (When multiple alternatives are in use, each pattern must,
872: for each possible combination of operand expressions, have at least one
873: alternative which can handle that combination of operands.) The
874: constraints don't need to @emph{allow} any possible operand---when this is
875: the case, they do not constrain---but they must at least point the way to
876: reloading any possible operand so that it will fit.
877:
878: @itemize @bullet
879: @item
880: If the constraint accepts whatever operands the predicate permits,
881: there is no problem: reloading is never necessary for this operand.
882:
883: For example, an operand whose constraints permit everything except
884: registers is safe provided its predicate rejects registers.
885:
886: An operand whose predicate accepts only constant values is safe
887: provided its constraints include the letter @samp{i}. If any possible
888: constant value is accepted, then nothing less than @samp{i} will do;
889: if the predicate is more selective, then the constraints may also be
890: more selective.
891:
892: @item
893: Any operand expression can be reloaded by copying it into a register.
894: So if an operand's constraints allow some kind of register, it is
895: certain to be safe. It need not permit all classes of registers; the
896: compiler knows how to copy a register into another register of the
897: proper class in order to make an instruction valid.
898:
899: @cindex nonoffsettable memory reference
900: @cindex memory reference, nonoffsettable
901: @item
902: A nonoffsettable memory reference can be reloaded by copying the
903: address into a register. So if the constraint uses the letter
904: @samp{o}, all memory references are taken care of.
905:
906: @item
907: A constant operand can be reloaded by allocating space in memory to
908: hold it as preinitialized data. Then the memory reference can be used
909: in place of the constant. So if the constraint uses the letters
910: @samp{o} or @samp{m}, constant operands are not a problem.
911:
912: @item
913: If the constraint permits a constant and a pseudo register used in an insn
914: was not allocated to a hard register and is equivalent to a constant,
915: the register will be replaced with the constant. If the predicate does
916: not permit a constant and the insn is re-recognized for some reason, the
917: compiler will crash. Thus the predicate must always recognize any
918: objects allowed by the constraint.
919: @end itemize
920:
921: If the operand's predicate can recognize registers, but the constraint does
922: not permit them, it can make the compiler crash. When this operand happens
923: to be a register, the reload pass will be stymied, because it does not know
924: how to copy a register temporarily into memory.
925:
926: @node Multi-Alternative, Class Preferences, Simple Constraints, Constraints
927: @subsection Multiple Alternative Constraints
928: @cindex multiple alternative constraints
929:
930: Sometimes a single instruction has multiple alternative sets of possible
931: operands. For example, on the 68000, a logical-or instruction can combine
932: register or an immediate value into memory, or it can combine any kind of
933: operand into a register; but it cannot combine one memory location into
934: another.
935:
936: These constraints are represented as multiple alternatives. An alternative
937: can be described by a series of letters for each operand. The overall
938: constraint for an operand is made from the letters for this operand
939: from the first alternative, a comma, the letters for this operand from
940: the second alternative, a comma, and so on until the last alternative.
941: Here is how it is done for fullword logical-or on the 68000:
942:
943: @example
944: (define_insn "iorsi3"
945: [(set (match_operand:SI 0 "general_operand" "=m,d")
946: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
947: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
948: @dots{})
949: @end example
950:
951: The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
952: operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
953: 2. The second alternative has @samp{d} (data register) for operand 0,
954: @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
955: @samp{%} in the constraints apply to all the alternatives; their
956: meaning is explained in the next section (@pxref{Class Preferences}).
957:
958: If all the operands fit any one alternative, the instruction is valid.
959: Otherwise, for each alternative, the compiler counts how many instructions
960: must be added to copy the operands so that that alternative applies.
961: The alternative requiring the least copying is chosen. If two alternatives
962: need the same amount of copying, the one that comes first is chosen.
963: These choices can be altered with the @samp{?} and @samp{!} characters:
964:
965: @table @code
966: @cindex @samp{?} in constraint
967: @cindex question mark
968: @item ?
969: Disparage slightly the alternative that the @samp{?} appears in,
970: as a choice when no alternative applies exactly. The compiler regards
971: this alternative as one unit more costly for each @samp{?} that appears
972: in it.
973:
974: @cindex @samp{!} in constraint
975: @cindex exclamation point
976: @item !
977: Disparage severely the alternative that the @samp{!} appears in.
978: This alternative can still be used if it fits without reloading,
979: but if reloading is needed, some other alternative will be used.
980: @end table
981:
982: When an insn pattern has multiple alternatives in its constraints, often
983: the appearance of the assembler code is determined mostly by which
984: alternative was matched. When this is so, the C code for writing the
985: assembler code can use the variable @code{which_alternative}, which is
986: the ordinal number of the alternative that was actually satisfied (0 for
987: the first, 1 for the second alternative, etc.). @xref{Output Statement}.
988:
989: @node Class Preferences, Modifiers, Multi-Alternative, Constraints
990: @subsection Register Class Preferences
991: @cindex class preference constraints
992: @cindex register class preference constraints
993:
994: @cindex voting between constraint alternatives
995: The operand constraints have another function: they enable the compiler
996: to decide which kind of hardware register a pseudo register is best
997: allocated to. The compiler examines the constraints that apply to the
998: insns that use the pseudo register, looking for the machine-dependent
999: letters such as @samp{d} and @samp{a} that specify classes of registers.
1000: The pseudo register is put in whichever class gets the most ``votes''.
1001: The constraint letters @samp{g} and @samp{r} also vote: they vote in
1002: favor of a general register. The machine description says which registers
1003: are considered general.
1004:
1005: Of course, on some machines all registers are equivalent, and no register
1006: classes are defined. Then none of this complexity is relevant.
1007:
1008: @node Modifiers, No Constraints, Class Preferences, Constraints
1009: @subsection Constraint Modifier Characters
1010: @cindex modifiers in constraints
1011: @cindex constraint modifier characters
1012:
1013: @table @samp
1014: @cindex @samp{=} in constraint
1015: @item =
1016: Means that this operand is write-only for this instruction: the previous
1017: value is discarded and replaced by output data.
1018:
1019: @cindex @samp{+} in constraint
1020: @item +
1021: Means that this operand is both read and written by the instruction.
1022:
1023: When the compiler fixes up the operands to satisfy the constraints,
1024: it needs to know which operands are inputs to the instruction and
1025: which are outputs from it. @samp{=} identifies an output; @samp{+}
1026: identifies an operand that is both input and output; all other operands
1027: are assumed to be input only.
1028:
1029: @cindex @samp{&} in constraint
1030: @item &
1031: Means (in a particular alternative) that this operand is written
1032: before the instruction is finished using the input operands.
1033: Therefore, this operand may not lie in a register that is used as an
1034: input operand or as part of any memory address.
1035:
1036: @samp{&} applies only to the alternative in which it is written. In
1037: constraints with multiple alternatives, sometimes one alternative
1038: requires @samp{&} while others do not. See, for example, the
1039: @samp{movdf} insn of the 68000.
1040:
1041: @samp{&} does not obviate the need to write @samp{=}.
1042:
1043: @cindex @samp{%} in constraint
1044: @item %
1045: Declares the instruction to be commutative for this operand and the
1046: following operand. This means that the compiler may interchange the
1047: two operands if that is the cheapest way to make all operands fit the
1048: constraints. This is often used in patterns for addition instructions
1049: that really have only two operands: the result must go in one of the
1050: arguments. Here for example, is how the 68000 halfword-add
1051: instruction is defined:
1052:
1053: @example
1054: (define_insn "addhi3"
1055: [(set (match_operand:HI 0 "general_operand" "=m,r")
1056: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1057: (match_operand:HI 2 "general_operand" "di,g")))]
1058: @dots{})
1059: @end example
1060:
1061: @cindex @samp{#} in constraint
1062: @item #
1063: Says that all following characters, up to the next comma, are to be
1064: ignored as a constraint. They are significant only for choosing
1065: register preferences.
1066:
1067: @cindex @samp{*} in constraint
1068: @item *
1069: Says that the following character should be ignored when choosing
1070: register preferences. @samp{*} has no effect on the meaning of the
1071: constraint as a constraint, and no effect on reloading.
1072:
1073: Here is an example: the 68000 has an instruction to sign-extend a
1074: halfword in a data register, and can also sign-extend a value by
1075: copying it into an address register. While either kind of register is
1076: acceptable, the constraints on an address-register destination are
1077: less strict, so it is best if register allocation makes an address
1078: register its goal. Therefore, @samp{*} is used so that the @samp{d}
1079: constraint letter (for data register) is ignored when computing
1080: register preferences.
1081:
1082: @example
1083: (define_insn "extendhisi2"
1084: [(set (match_operand:SI 0 "general_operand" "=*d,a")
1085: (sign_extend:SI
1086: (match_operand:HI 1 "general_operand" "0,g")))]
1087: @dots{})
1088: @end example
1089: @end table
1090:
1091: @node No Constraints,, Modifiers, Constraints
1092: @subsection Not Using Constraints
1093: @cindex no constraints
1094: @cindex not using constraints
1095:
1096: Some machines are so clean that operand constraints are not required. For
1097: example, on the Vax, an operand valid in one context is valid in any other
1098: context. On such a machine, every operand constraint would be @samp{g},
1099: excepting only operands of ``load address'' instructions which are
1100: written as if they referred to a memory location's contents but actual
1101: refer to its address. They would have constraint @samp{p}.
1102:
1103: @cindex empty constraints
1104: For such machines, instead of writing @samp{g} and @samp{p} for all
1105: the constraints, you can choose to write a description with empty constraints.
1106: Then you write @samp{""} for the constraint in every @code{match_operand}.
1107: Address operands are identified by writing an @code{address} expression
1108: around the @code{match_operand}, not by their constraints.
1109:
1110: When the machine description has just empty constraints, certain parts
1111: of compilation are skipped, making the compiler faster. However,
1112: few machines actually do not need constraints; all machine descriptions
1113: now in existence use constraints.
1114:
1115: @node Standard Names, Pattern Ordering, Constraints, Machine Desc
1116: @section Standard Names for Patterns Used in Generation
1117: @cindex standard pattern names
1118: @cindex pattern names
1119: @cindex names, pattern
1120:
1121: Here is a table of the instruction names that are meaningful in the RTL
1122: generation pass of the compiler. Giving one of these names to an
1123: instruction pattern tells the RTL generation pass that it can use the
1124: pattern in to accomplish a certain task.
1125:
1126: @table @asis
1127: @cindex @code{mov@var{m}} instruction pattern
1128: @item @samp{mov@var{m}}
1129: Here @var{m} stands for a two-letter machine mode name, in lower case.
1130: This instruction pattern moves data with that machine mode from operand
1131: 1 to operand 0. For example, @samp{movsi} moves full-word data.
1132:
1133: If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1134: own mode is wider than @var{m}, the effect of this instruction is
1135: to store the specified value in the part of the register that corresponds
1136: to mode @var{m}. The effect on the rest of the register is undefined.
1137:
1138: This class of patterns is special in several ways. First of all, each
1139: of these names @emph{must} be defined, because there is no other way
1140: to copy a datum from one place to another.
1141:
1142: Second, these patterns are not used solely in the RTL generation pass.
1143: Even the reload pass can generate move insns to copy values from stack
1144: slots into temporary registers. When it does so, one of the operands is
1145: a hard register and the other is an operand that can need to be reloaded
1146: into a register.
1147:
1148: @findex force_reg
1149: Therefore, when given such a pair of operands, the pattern must generate
1150: RTL which needs no reloading and needs no temporary registers---no
1151: registers other than the operands. For example, if you support the
1152: pattern with a @code{define_expand}, then in such a case the
1153: @code{define_expand} mustn't call @code{force_reg} or any other such
1154: function which might generate new pseudo registers.
1155:
1156: This requirement exists even for subword modes on a RISC machine where
1157: fetching those modes from memory normally requires several insns and
1158: some temporary registers. Look in @file{spur.md} to see how the
1159: requirement can be satisfied.
1160:
1161: @findex change_address
1162: During reload a memory reference with an invalid address may be passed
1163: as an operand. Such an address will be replaced with a valid address
1164: later in the reload pass. In this case, nothing may be done with the
1165: address except to use it as it stands. If it is copied, it will not be
1166: replaced with a valid address. No attempt should be made to make such
1167: an address into a valid address and no routine (such as
1168: @code{change_address}) that will do so may be called. Note that
1169: @code{general_operand} will fail when applied to such an address.
1170:
1171: @findex reload_in_progress
1172: The global variable @code{reload_in_progress} (which must be explicitly
1173: declared if required) can be used to determine whether such special
1174: handling is required.
1175:
1176: The variety of operands that have reloads depends on the rest of the
1177: machine description, but typically on a RISC machine these can only be
1178: pseudo registers that did not get hard registers, while on other
1179: machines explicit memory references will get optional reloads.
1180:
1181: If a scratch register is required to move an object to or from memory,
1182: it can be allocated using @code{gen_reg_rtx} prior to reload. But this
1183: is impossible during and after reload. If there are cases needing
1184: scratch registers after reload, you must define
1185: @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
1186: @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1187: patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1188: them. @xref{Register Classes}.
1189:
1190: The constraints on a @samp{move@var{m}} must permit moving any hard
1191: register to any other hard register provided that
1192: @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1193: @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1194:
1195: It is obligatory to support floating point @samp{move@var{m}}
1196: instructions into and out of any registers that can hold fixed point
1197: values, because unions and structures (which have modes @code{SImode} or
1198: @code{DImode}) can be in those registers and they may have floating
1199: point members.
1200:
1201: There may also be a need to support fixed point @samp{move@var{m}}
1202: instructions in and out of floating point registers. Unfortunately, I
1203: have forgotten why this was so, and I don't know whether it is still
1204: true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1205: floating point registers, then the constraints of the fixed point
1206: @samp{move@var{m}} instructions must be designed to avoid ever trying to
1207: reload into a floating point register.
1208:
1.1.1.3 root 1209: @cindex @code{reload_in} instruction pattern
1210: @cindex @code{reload_out} instruction pattern
1.1 root 1211: @item @samp{reload_in@var{m}}
1212: @itemx @samp{reload_out@var{m}}
1213: Like @samp{mov@var{m}}, but used when a scratch register is required to
1214: move between operand 0 and operand 1. Operand 2 describes the scratch
1215: register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1216: macro in @pxref{Register Classes}.
1217:
1218: @cindex @code{movstrict@var{m}} instruction pattern
1219: @item @samp{movstrict@var{m}}
1220: Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1221: with mode @var{m} of a register whose natural mode is wider,
1222: the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1223: any of the register except the part which belongs to mode @var{m}.
1224:
1.1.1.3 root 1225: @cindex @code{load_multiple} instruction pattern
1226: @item @code{load_multiple}
1227: Load several consecutive memory locations into consecutive registers.
1228: Operand 0 is the first of the consecutive registers, operand 1
1229: is the first memory location, and operand 2 is a constant: the
1230: number of consecutive registers.
1231:
1232: Define this only if the target machine really has such an instruction;
1233: do not define this if the most efficient way of loading consecutive
1234: registers from memory is to do them one at a time.
1235:
1236: On some machines, there are restrictions as to which consecutive
1237: registers can be stored into memory, such as particular starting or
1238: ending register numbers or only a range of valid counts. For those
1239: machines, use a @code{define_expand} (@pxref{Expander Definitions})
1240: and make the pattern fail if the restrictions are not met.
1241:
1242: Write the generated insn as a @code{parallel} with elements being a
1243: @code{set} of one register from the appropriate memory location (you may
1244: also need @code{use} or @code{clobber} elements). Use a
1245: @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
1246: @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
1247: pattern.
1248:
1249: @cindex @samp{store_multiple} instruction pattern
1250: @item @code{store_multiple}
1251: Similar to @samp{load_multiple}, but store several consecutive registers
1252: into consecutive memory locations. Operand 0 is the first of the
1253: consecutive memory locations, operand 1 is the first register, and
1254: operand 2 is a constant: the number of consecutive registers.
1255:
1.1 root 1256: @cindex @code{add@var{m}3} instruction pattern
1257: @item @samp{add@var{m}3}
1258: Add operand 2 and operand 1, storing the result in operand 0. All operands
1259: must have mode @var{m}. This can be used even on two-address machines, by
1260: means of constraints requiring operands 1 and 0 to be the same location.
1261:
1262: @cindex @code{sub@var{m}3} instruction pattern
1263: @cindex @code{mul@var{m}3} instruction pattern
1264: @cindex @code{div@var{m}3} instruction pattern
1265: @cindex @code{udiv@var{m}3} instruction pattern
1266: @cindex @code{mod@var{m}3} instruction pattern
1267: @cindex @code{umod@var{m}3} instruction pattern
1268: @cindex @code{min@var{m}3} instruction pattern
1269: @cindex @code{max@var{m}3} instruction pattern
1270: @cindex @code{umin@var{m}3} instruction pattern
1271: @cindex @code{umax@var{m}3} instruction pattern
1272: @cindex @code{and@var{m}3} instruction pattern
1273: @cindex @code{ior@var{m}3} instruction pattern
1274: @cindex @code{xor@var{m}3} instruction pattern
1275: @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
1276: @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
1277: @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
1278: @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
1279: Similar, for other arithmetic operations.
1280:
1281: @cindex @code{mulhisi3} instruction pattern
1282: @item @samp{mulhisi3}
1283: Multiply operands 1 and 2, which have mode @code{HImode}, and store
1284: a @code{SImode} product in operand 0.
1285:
1286: @cindex @code{mulqihi3} instruction pattern
1287: @cindex @code{mulsidi3} instruction pattern
1288: @item @samp{mulqihi3}, @samp{mulsidi3}
1289: Similar widening-multiplication instructions of other widths.
1290:
1291: @cindex @code{umulqihi3} instruction pattern
1292: @cindex @code{umulhisi3} instruction pattern
1293: @cindex @code{umulsidi3} instruction pattern
1294: @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
1295: Similar widening-multiplication instructions that do unsigned
1296: multiplication.
1297:
1298: @cindex @code{divmod@var{m}4} instruction pattern
1299: @item @samp{divmod@var{m}4}
1300: Signed division that produces both a quotient and a remainder.
1301: Operand 1 is divided by operand 2 to produce a quotient stored
1302: in operand 0 and a remainder stored in operand 3.
1303:
1304: For machines with an instruction that produces both a quotient and a
1305: remainder, provide a pattern for @samp{divmod@var{m}4} but do not
1306: provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
1307: allows optimization in the relatively common case when both the quotient
1308: and remainder are computed.
1309:
1310: If an instruction that just produces a quotient or just a remainder
1311: exists and is more efficient than the instruction that produces both,
1312: write the output routine of @samp{divmod@var{m}4} to call
1313: @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
1314: quotient or remainder and generate the appropriate instruction.
1315:
1316: @cindex @code{udivmod@var{m}4} instruction pattern
1317: @item @samp{udivmod@var{m}4}
1318: Similar, but does unsigned division.
1319:
1320: @cindex @code{ashl@var{m}3} instruction pattern
1321: @item @samp{ashl@var{m}3}
1.1.1.3 root 1322: Arithmetic-shift operand 1 left by a number of bits specified by operand
1323: 2, and store the result in operand 0. Here @var{m} is the mode of
1324: operand 0 and operand 1; operand 2's mode is specified by the
1325: instruction pattern, and the compiler will convert the operand to that
1326: mode before generating the instruction.
1.1 root 1327:
1328: @cindex @code{ashr@var{m}3} instruction pattern
1329: @cindex @code{lshl@var{m}3} instruction pattern
1330: @cindex @code{lshr@var{m}3} instruction pattern
1331: @cindex @code{rotl@var{m}3} instruction pattern
1332: @cindex @code{rotr@var{m}3} instruction pattern
1333: @item @samp{ashr@var{m}3}, @samp{lshl@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
1.1.1.3 root 1334: Other shift and rotate instructions, analogous to the
1335: @code{ashl@var{m}3} instructions.
1.1 root 1336:
1337: Logical and arithmetic left shift are the same. Machines that do not
1338: allow negative shift counts often have only one instruction for
1339: shifting left. On such machines, you should define a pattern named
1340: @samp{ashl@var{m}3} and leave @samp{lshl@var{m}3} undefined.
1341:
1342: @cindex @code{neg@var{m}2} instruction pattern
1343: @item @samp{neg@var{m}2}
1344: Negate operand 1 and store the result in operand 0.
1345:
1346: @cindex @code{abs@var{m}2} instruction pattern
1347: @item @samp{abs@var{m}2}
1348: Store the absolute value of operand 1 into operand 0.
1349:
1350: @cindex @code{sqrt@var{m}2} instruction pattern
1351: @item @samp{sqrt@var{m}2}
1352: Store the square root of operand 1 into operand 0.
1353:
1.1.1.3 root 1354: The @code{sqrt} built-in function of C always uses the mode which
1355: corresponds to the C data type @code{double}.
1356:
1.1 root 1357: @cindex @code{ffs@var{m}2} instruction pattern
1358: @item @samp{ffs@var{m}2}
1359: Store into operand 0 one plus the index of the least significant 1-bit
1360: of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
1361: of operand 0; operand 1's mode is specified by the instruction
1362: pattern, and the compiler will convert the operand to that mode before
1363: generating the instruction.
1364:
1.1.1.3 root 1365: The @code{ffs} built-in function of C always uses the mode which
1366: corresponds to the C data type @code{int}.
1367:
1.1 root 1368: @cindex @code{one_cmpl@var{m}2} instruction pattern
1369: @item @samp{one_cmpl@var{m}2}
1370: Store the bitwise-complement of operand 1 into operand 0.
1371:
1372: @cindex @code{cmp@var{m}} instruction pattern
1373: @item @samp{cmp@var{m}}
1374: Compare operand 0 and operand 1, and set the condition codes.
1375: The RTL pattern should look like this:
1376:
1377: @example
1378: (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
1379: (match_operand:@var{m} 1 @dots{})))
1380: @end example
1381:
1382: @cindex @code{tst@var{m}} instruction pattern
1383: @item @samp{tst@var{m}}
1384: Compare operand 0 against zero, and set the condition codes.
1385: The RTL pattern should look like this:
1386:
1387: @example
1388: (set (cc0) (match_operand:@var{m} 0 @dots{}))
1389: @end example
1390:
1391: @samp{tst@var{m}} patterns should not be defined for machines that do
1392: not use @code{(cc0)}. Doing so would confuse the optimizer since it
1393: would no longer be clear which @code{set} operations were comparisons.
1394: The @samp{cmp@var{m}} patterns should be used instead.
1395:
1396: @cindex @code{movstr@var{m}} instruction pattern
1397: @item @samp{movstr@var{m}}
1398: Block move instruction. The addresses of the destination and source
1399: strings are the first two operands, and both are in mode @code{Pmode}.
1400: The number of bytes to move is the third operand, in mode @var{m}.
1401:
1402: The fourth operand is the known shared alignment of the source and
1403: destination, in the form of a @code{const_int} rtx. Thus, if the
1404: compiler knows that both source and destination are word-aligned,
1405: it may provide the value 4 for this operand.
1406:
1407: These patterns need not give special consideration to the possibility
1408: that the source and destination strings might overlap.
1409:
1410: @cindex @code{cmpstr@var{m}} instruction pattern
1411: @item @samp{cmpstr@var{m}}
1412: Block compare instruction, with five operands. Operand 0 is the output;
1413: it has mode @var{m}. The remaining four operands are like the operands
1414: of @samp{movstr@var{m}}. The two memory blocks specified are compared
1415: byte by byte in lexicographic order. The effect of the instruction is
1416: to store a value in operand 0 whose sign indicates the result of the
1417: comparison.
1418:
1419: @cindex @code{float@var{mn}2} instruction pattern
1420: @item @samp{float@var{m}@var{n}2}
1421: Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
1422: floating point mode @var{n} and store in operand 0 (which has mode
1423: @var{n}).
1424:
1425: @cindex @code{floatuns@var{mn}2} instruction pattern
1426: @item @samp{floatuns@var{m}@var{n}2}
1427: Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
1428: to floating point mode @var{n} and store in operand 0 (which has mode
1429: @var{n}).
1430:
1431: @cindex @code{fix@var{mn}2} instruction pattern
1432: @item @samp{fix@var{m}@var{n}2}
1433: Convert operand 1 (valid for floating point mode @var{m}) to fixed
1434: point mode @var{n} as a signed number and store in operand 0 (which
1435: has mode @var{n}). This instruction's result is defined only when
1436: the value of operand 1 is an integer.
1437:
1438: @cindex @code{fixuns@var{mn}2} instruction pattern
1439: @item @samp{fixuns@var{m}@var{n}2}
1440: Convert operand 1 (valid for floating point mode @var{m}) to fixed
1441: point mode @var{n} as an unsigned number and store in operand 0 (which
1442: has mode @var{n}). This instruction's result is defined only when the
1443: value of operand 1 is an integer.
1444:
1445: @cindex @code{ftrunc@var{m}2} instruction pattern
1446: @item @samp{ftrunc@var{m}2}
1447: Convert operand 1 (valid for floating point mode @var{m}) to an
1448: integer value, still represented in floating point mode @var{m}, and
1449: store it in operand 0 (valid for floating point mode @var{m}).
1450:
1451: @cindex @code{fix_trunc@var{mn}2} instruction pattern
1452: @item @samp{fix_trunc@var{m}@var{n}2}
1453: Like @samp{fix@var{m}@var{n}2} but works for any floating point value
1454: of mode @var{m} by converting the value to an integer.
1455:
1456: @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
1457: @item @samp{fixuns_trunc@var{m}@var{n}2}
1458: Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
1459: value of mode @var{m} by converting the value to an integer.
1460:
1461: @cindex @code{trunc@var{mn}} instruction pattern
1462: @item @samp{trunc@var{m}@var{n}}
1463: Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
1464: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1465: point or both floating point.
1466:
1467: @cindex @code{extend@var{mn}} instruction pattern
1468: @item @samp{extend@var{m}@var{n}}
1469: Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
1470: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1471: point or both floating point.
1472:
1473: @cindex @code{zero_extend@var{mn}} instruction pattern
1474: @item @samp{zero_extend@var{m}@var{n}}
1475: Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
1476: store in operand 0 (which has mode @var{n}). Both modes must be fixed
1477: point.
1478:
1479: @cindex @code{extv} instruction pattern
1480: @item @samp{extv}
1481: Extract a bit field from operand 1 (a register or memory operand), where
1482: operand 2 specifies the width in bits and operand 3 the starting bit,
1483: and store it in operand 0. Operand 0 must have mode @code{word_mode}.
1484: Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
1485: @code{word_mode} is allowed only for registers. Operands 2 and 3 must
1486: be valid for @code{word_mode}.
1487:
1488: The RTL generation pass generates this instruction only with constants
1489: for operands 2 and 3.
1490:
1491: The bit-field value is sign-extended to a full word integer
1492: before it is stored in operand 0.
1493:
1494: @cindex @code{extzv} instruction pattern
1495: @item @samp{extzv}
1496: Like @samp{extv} except that the bit-field value is zero-extended.
1497:
1498: @cindex @code{insv} instruction pattern
1499: @item @samp{insv}
1500: Store operand 3 (which must be valid for @code{word_mode}) into a bit
1501: field in operand 0, where operand 1 specifies the width in bits and
1502: operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
1503: @code{word_mode}; often @code{word_mode} is allowed only for registers.
1504: Operands 1 and 2 must be valid for @code{word_mode}.
1505:
1506: The RTL generation pass generates this instruction only with constants
1507: for operands 1 and 2.
1508:
1509: @cindex @code{s@var{cond}} instruction pattern
1510: @item @samp{s@var{cond}}
1511: Store zero or nonzero in the operand according to the condition codes.
1512: Value stored is nonzero iff the condition @var{cond} is true.
1513: @var{cond} is the name of a comparison operation expression code, such
1514: as @code{eq}, @code{lt} or @code{leu}.
1515:
1516: You specify the mode that the operand must have when you write the
1517: @code{match_operand} expression. The compiler automatically sees
1518: which mode you have used and supplies an operand of that mode.
1519:
1520: The value stored for a true condition must have 1 as its low bit, or
1521: else must be negative. Otherwise the instruction is not suitable and
1522: you should omit it from the machine description. You describe to the
1523: compiler exactly which value is stored by defining the macro
1524: @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
1525: found that can be used for all the @samp{s@var{cond}} patterns, you
1526: should omit those operations from the machine description.
1527:
1528: These operations may fail, but should do so only in relatively
1529: uncommon cases; if they would fail for common cases involving
1530: integer comparisons, it is best to omit these patterns.
1531:
1532: If these operations are omitted, the compiler will usually generate code
1533: that copies the constant one to the target and branches around an
1534: assignment of zero to the target. If this code is more efficient than
1535: the potential instructions used for the @samp{s@var{cond}} pattern
1536: followed by those required to convert the result into a 1 or a zero in
1537: @code{SImode}, you should omit the @samp{s@var{cond}} operations from
1538: the machine description.
1539:
1540: @cindex @code{b@var{cond}} instruction pattern
1541: @item @samp{b@var{cond}}
1542: Conditional branch instruction. Operand 0 is a @code{label_ref} that
1543: refers to the label to jump to. Jump if the condition codes meet
1544: condition @var{cond}.
1545:
1546: Some machines do not follow the model assumed here where a comparison
1547: instruction is followed by a conditional branch instruction. In that
1548: case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
1549: simply store the operands away and generate all the required insns in a
1550: @code{define_expand} (@pxref{Expander Definitions}) for the conditional
1.1.1.4 ! root 1551: branch operations. All calls to expand @samp{b@var{cond}} patterns are
1.1 root 1552: immediately preceded by calls to expand either a @samp{cmp@var{m}}
1553: pattern or a @samp{tst@var{m}} pattern.
1554:
1555: Machines that use a pseudo register for the condition code value, or
1556: where the mode used for the comparison depends on the condition being
1557: tested, should also use the above mechanism. @xref{Jump Patterns}
1558:
1559: The above discussion also applies to @samp{s@var{cond}} patterns.
1560:
1561: @cindex @code{call} instruction pattern
1562: @item @samp{call}
1563: Subroutine call instruction returning no value. Operand 0 is the
1564: function to call; operand 1 is the number of bytes of arguments pushed
1565: (in mode @code{SImode}, except it is normally a @code{const_int});
1566: operand 2 is the number of registers used as operands.
1567:
1568: On most machines, operand 2 is not actually stored into the RTL
1569: pattern. It is supplied for the sake of some RISC machines which need
1570: to put this information into the assembler code; they can put it in
1571: the RTL instead of operand 1.
1572:
1573: Operand 0 should be a @code{mem} RTX whose address is the address of the
1574: function. Note, however, that this address can be a @code{symbol_ref}
1575: expression even if it would not be a legitimate memory address on the
1576: target machine. If it is also not a valid argument for a call
1577: instruction, the pattern for this operation should be a
1578: @code{define_expand} (@pxref{Expander Definitions}) that places the
1579: address into a register and uses that register in the call instruction.
1580:
1581: @cindex @code{call_value} instruction pattern
1582: @item @samp{call_value}
1583: Subroutine call instruction returning a value. Operand 0 is the hard
1584: register in which the value is returned. There are three more
1585: operands, the same as the three operands of the @samp{call}
1586: instruction (but with numbers increased by one).
1587:
1588: Subroutines that return @code{BLKmode} objects use the @samp{call}
1589: insn.
1590:
1591: @cindex @code{call_pop} instruction pattern
1592: @cindex @code{call_value_pop} instruction pattern
1593: @item @samp{call_pop}, @samp{call_value_pop}
1594: Similar to @samp{call} and @samp{call_value}, except used if defined and
1595: if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
1596: that contains both the function call and a @code{set} to indicate the
1597: adjustment made to the frame pointer.
1598:
1599: For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
1600: patterns increases the number of functions for which the frame pointer
1601: can be eliminated, if desired.
1602:
1603: @cindex @code{return} instruction pattern
1604: @item @samp{return}
1605: Subroutine return instruction. This instruction pattern name should be
1606: defined only if a single instruction can do all the work of returning
1607: from a function.
1608:
1609: Like the @samp{mov@var{m}} patterns, this pattern is also used after the
1610: RTL generation phase. In this case it is to support machines where
1611: multiple instructions are usually needed to return from a function, but
1612: some class of functions only requires one instruction to implement a
1613: return. Normally, the applicable functions are those which do not need
1614: to save any registers or allocate stack space.
1615:
1616: @findex reload_completed
1617: @findex leaf_function_p
1618: For such machines, the condition specified in this pattern should only
1619: be true when @code{reload_completed} is non-zero and the function's
1620: epilogue would only be a single instruction. For machines with register
1621: windows, the routine @code{leaf_function_p} may be used to determine if
1622: a register window push is required.
1623:
1624: Machines that have conditional return instructions should define patterns
1625: such as
1626:
1627: @example
1628: (define_insn ""
1629: [(set (pc)
1.1.1.4 ! root 1630: (if_then_else (match_operator 0 "comparison_operator"
! 1631: [(cc0) (const_int 0)])
! 1632: (return)
! 1633: (pc)))]
1.1 root 1634: "@var{condition}"
1635: "@dots{}")
1636: @end example
1637:
1638: where @var{condition} would normally be the same condition specified on the
1639: named @samp{return} pattern.
1640:
1641: @cindex @code{nop} instruction pattern
1642: @item @samp{nop}
1643: No-op instruction. This instruction pattern name should always be defined
1644: to output a no-op in assembler code. @code{(const_int 0)} will do as an
1645: RTL pattern.
1646:
1647: @cindex @code{indirect_jump} instruction pattern
1648: @item @samp{indirect_jump}
1649: An instruction to jump to an address which is operand zero.
1650: This pattern name is mandatory on all machines.
1651:
1652: @cindex @code{casesi} instruction pattern
1653: @item @samp{casesi}
1654: Instruction to jump through a dispatch table, including bounds checking.
1655: This instruction takes five operands:
1656:
1657: @enumerate
1658: @item
1659: The index to dispatch on, which has mode @code{SImode}.
1660:
1661: @item
1662: The lower bound for indices in the table, an integer constant.
1663:
1664: @item
1665: The total range of indices in the table---the largest index
1666: minus the smallest one (both inclusive).
1667:
1668: @item
1669: A label that precedes the table itself.
1670:
1671: @item
1672: A label to jump to if the index has a value outside the bounds.
1673: (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
1674: then an out-of-bounds index drops through to the code following
1675: the jump table instead of jumping to this label. In that case,
1676: this label is not actually used by the @samp{casesi} instruction,
1677: but it is always provided as an operand.)
1678: @end enumerate
1679:
1680: The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
1681: @code{jump_insn}. The number of elements in the table is one plus the
1682: difference between the upper bound and the lower bound.
1683:
1684: @cindex @code{tablejump} instruction pattern
1685: @item @samp{tablejump}
1686: Instruction to jump to a variable address. This is a low-level
1687: capability which can be used to implement a dispatch table when there
1688: is no @samp{casesi} pattern.
1689:
1690: This pattern requires two operands: the address or offset, and a label
1691: which should immediately precede the jump table. If the macro
1692: @code{CASE_VECTOR_PC_RELATIVE} is defined then the first operand is an
1693: offset which counts from the address of the table; otherwise, it is an
1.1.1.3 root 1694: absolute address to jump to. In either case, the first operand has
1695: mode @code{Pmode}.
1.1 root 1696:
1697: The @samp{tablejump} insn is always the last insn before the jump
1698: table it uses. Its assembler code normally has no need to use the
1699: second operand, but you should incorporate it in the RTL pattern so
1700: that the jump optimizer will not delete the table as unreachable code.
1.1.1.3 root 1701:
1702: @cindex @code{save_stack_block} instruction pattern
1703: @cindex @code{save_stack_function} instruction pattern
1704: @cindex @code{save_stack_nonlocal} instruction pattern
1705: @cindex @code{restore_stack_block} instruction pattern
1706: @cindex @code{restore_stack_function} instruction pattern
1707: @cindex @code{restore_stack_nonlocal} instruction pattern
1708: @item @samp{save_stack_block}
1709: @itemx @samp{save_stack_function}
1710: @itemx @samp{save_stack_nonlocal}
1711: @itemx @samp{restore_stack_block}
1712: @itemx @samp{restore_stack_function}
1713: @itemx @samp{restore_stack_nonlocal}
1714: Most machines save and restore the stack pointer by copying it to or
1715: from an object of mode @code{Pmode}. Do not define these patterns on
1716: such machines.
1717:
1718: Some machines require special handling for stack pointer saves and
1719: restores. On those machines, define the patterns corresponding to the
1720: non-standard cases by using a @code{define_expand} (@pxref{Expander
1721: Definitions}) that produces the required insns. The three types of
1722: saves and restores are:
1723:
1724: @enumerate
1725: @item
1726: @samp{save_stack_block} saves the stack pointer at the start of a block
1727: that allocates a variable-sized object and @samp{restore_stack_block}
1728: restores the stack pointer when the block is exited.
1729:
1730: @item
1731: @samp{save_stack_function} and @samp{restore_stack_function} operate
1732: similarly for the outermost block of a function and are used when the
1733: function allocates variable-sized objects or calls @code{alloca}. Only
1734: the epilogue uses the restored stack pointer, allowing a simpler save or
1735: restore sequence on some machines.
1736:
1737: @item
1738: @samp{save_stack_nonlocal} is used in functions that contain labels
1739: branched to by nested functions. It saves the stack pointer in such a
1740: way that the inner function can use @samp{restore_stack_nonlocal} to
1741: restore the stack pointer. The compiler generates code to restore the
1742: frame and argument pointer registers, but some machines require saving
1743: and restoring additional data such as register window information or
1744: stack backchains. Place insns in these patterns to save and restore any
1745: such required data.
1746: @end enumerate
1747:
1748: When saving the stack pointer, operand 0 is the save area and operand 1
1749: is the stack pointer. The mode used to allocate the save area is the
1750: mode of operand 0. You must specify an integral mode, or
1751: @code{VOIDmode} if no save area is needed for a particular type of save
1752: (either because no save is needed or because a machine-specific save
1753: area can be used). Operand 0 is the stack pointer and operand 1 is the
1754: save area for restore operations. If @samp{save_stack_block} is
1755: defined, operand 0 must not be @code{VOIDmode} since these saves can be
1756: arbitrarily nested.
1757:
1758: A save area is a @code{mem} that is at a constant offset from
1759: @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
1760: nonlocal gotos and a @code{reg} in the other two cases.
1761:
1762: @cindex @code{allocate_stack} instruction pattern
1763: @item @samp{allocate_stack}
1764: Subtract operand 0 from the stack pointer to create space for
1765: for dynamically allocated data.
1766:
1767: Do not define this pattern if all that must be done is the subtraction.
1768: On some machines require other operations such as stack probes or
1769: maintaining the back chain. Define this pattern to emit those
1770: operations in addition to updating the stack pointer.
1.1 root 1771: @end table
1772:
1773: @node Pattern Ordering, Dependent Patterns, Standard Names, Machine Desc
1774: @section When the Order of Patterns Matters
1775: @cindex Pattern Ordering
1776: @cindex Ordering of Patterns
1777:
1778: Sometimes an insn can match more than one instruction pattern. Then the
1779: pattern that appears first in the machine description is the one used.
1780: Therefore, more specific patterns (patterns that will match fewer things)
1781: and faster instructions (those that will produce better code when they
1782: do match) should usually go first in the description.
1783:
1784: In some cases the effect of ordering the patterns can be used to hide
1785: a pattern when it is not valid. For example, the 68000 has an
1786: instruction for converting a fullword to floating point and another
1787: for converting a byte to floating point. An instruction converting
1788: an integer to floating point could match either one. We put the
1789: pattern to convert the fullword first to make sure that one will
1790: be used rather than the other. (Otherwise a large integer might
1791: be generated as a single-byte immediate quantity, which would not work.)
1792: Instead of using this pattern ordering it would be possible to make the
1793: pattern for convert-a-byte smart enough to deal properly with any
1794: constant value.
1795:
1796: @node Dependent Patterns, Jump Patterns, Pattern Ordering, Machine Desc
1797: @section Interdependence of Patterns
1798: @cindex Dependent Patterns
1799: @cindex Interdependence of Patterns
1800:
1801: Every machine description must have a named pattern for each of the
1802: conditional branch names @samp{b@var{cond}}. The recognition template
1803: must always have the form
1804:
1805: @example
1806: (set (pc)
1807: (if_then_else (@var{cond} (cc0) (const_int 0))
1808: (label_ref (match_operand 0 "" ""))
1809: (pc)))
1810: @end example
1811:
1812: @noindent
1813: In addition, every machine description must have an anonymous pattern
1814: for each of the possible reverse-conditional branches. Their templates
1815: look like
1816:
1817: @example
1818: (set (pc)
1819: (if_then_else (@var{cond} (cc0) (const_int 0))
1820: (pc)
1821: (label_ref (match_operand 0 "" ""))))
1822: @end example
1823:
1824: @noindent
1825: They are necessary because jump optimization can turn direct-conditional
1826: branches into reverse-conditional branches.
1827:
1828: It is often convenient to use the @code{match_operator} construct to
1829: reduce the number of patterns that must be specified for branches. For
1830: example,
1831:
1832: @example
1833: (define_insn ""
1834: [(set (pc)
1835: (if_then_else (match_operator 0 "comparison_operator"
1.1.1.4 ! root 1836: [(cc0) (const_int 0)])
! 1837: (pc)
! 1838: (label_ref (match_operand 1 "" ""))))]
1.1 root 1839: "@var{condition}"
1840: "@dots{}")
1841: @end example
1842:
1843: In some cases machines support instructions identical except for the
1844: machine mode of one or more operands. For example, there may be
1845: ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
1846: patterns are
1847:
1848: @example
1849: (set (match_operand:SI 0 @dots{})
1850: (extend:SI (match_operand:HI 1 @dots{})))
1851:
1852: (set (match_operand:SI 0 @dots{})
1853: (extend:SI (match_operand:QI 1 @dots{})))
1854: @end example
1855:
1856: @noindent
1857: Constant integers do not specify a machine mode, so an instruction to
1858: extend a constant value could match either pattern. The pattern it
1859: actually will match is the one that appears first in the file. For correct
1860: results, this must be the one for the widest possible mode (@code{HImode},
1861: here). If the pattern matches the @code{QImode} instruction, the results
1862: will be incorrect if the constant value does not actually fit that mode.
1863:
1864: Such instructions to extend constants are rarely generated because they are
1865: optimized away, but they do occasionally happen in nonoptimized
1866: compilations.
1867:
1868: If a constraint in a pattern allows a constant, the reload pass may
1869: replace a register with a constant permitted by the constraint in some
1870: cases. Similarly for memory references. You must ensure that the
1871: predicate permits all objects allowed by the constraints to prevent the
1872: compiler from crashing.
1873:
1874: Because of this substitution, you should not provide separate patterns
1875: for increment and decrement instructions. Instead, they should be
1876: generated from the same pattern that supports register-register add
1877: insns by examining the operands and generating the appropriate machine
1878: instruction.
1879:
1880: @node Jump Patterns, Insn Canonicalizations, Dependent Patterns, Machine Desc
1881: @section Defining Jump Instruction Patterns
1882: @cindex jump instruction patterns
1883: @cindex defining jump instruction patterns
1884:
1885: For most machines, GNU CC assumes that the machine has a condition code.
1886: A comparison insn sets the condition code, recording the results of both
1887: signed and unsigned comparison of the given operands. A separate branch
1888: insn tests the condition code and branches or not according its value.
1889: The branch insns come in distinct signed and unsigned flavors. Many
1890: common machines, such as the Vax, the 68000 and the 32000, work this
1891: way.
1892:
1893: Some machines have distinct signed and unsigned compare instructions, and
1894: only one set of conditional branch instructions. The easiest way to handle
1895: these machines is to treat them just like the others until the final stage
1896: where assembly code is written. At this time, when outputting code for the
1897: compare instruction, peek ahead at the following branch using
1898: @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
1899: being output, in the output-writing code in an instruction pattern.) If
1900: the RTL says that is an unsigned branch, output an unsigned compare;
1901: otherwise output a signed compare. When the branch itself is output, you
1902: can treat signed and unsigned branches identically.
1903:
1904: The reason you can do this is that GNU CC always generates a pair of
1905: consecutive RTL insns, possibly separated by @code{note} insns, one to
1906: set the condition code and one to test it, and keeps the pair inviolate
1907: until the end.
1908:
1909: To go with this technique, you must define the machine-description macro
1910: @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
1911: compare instruction is superfluous.
1912:
1913: Some machines have compare-and-branch instructions and no condition code.
1914: A similar technique works for them. When it is time to ``output'' a
1915: compare instruction, record its operands in two static variables. When
1916: outputting the branch-on-condition-code instruction that follows, actually
1917: output a compare-and-branch instruction that uses the remembered operands.
1918:
1919: It also works to define patterns for compare-and-branch instructions.
1920: In optimizing compilation, the pair of compare and branch instructions
1921: will be combined according to these patterns. But this does not happen
1922: if optimization is not requested. So you must use one of the solutions
1923: above in addition to any special patterns you define.
1924:
1925: In many RISC machines, most instructions do not affect the condition
1926: code and there may not even be a separate condition code register. On
1927: these machines, the restriction that the definition and use of the
1928: condition code be adjacent insns is not necessary and can prevent
1929: important optimizations. For example, on the IBM RS/6000, there is a
1930: delay for taken branches unless the condition code register is set three
1931: instructions earlier than the conditional branch. The instruction
1932: scheduler cannot perform this optimization if it is not permitted to
1933: separate the definition and use of the condition code register.
1934:
1935: On these machines, do not use @code{(cc0)}, but instead use a register
1936: to represent the condition code. If there is a specific condition code
1937: register in the machine, use a hard register. If the condition code or
1938: comparison result can be placed in any general register, or if there are
1939: multiple condition registers, use a pseudo register.
1940:
1941: @findex prev_cc0_setter
1942: @findex next_cc0_user
1943: On some machines, the type of branch instruction generated may depend on
1944: the way the condition code was produced; for example, on the 68k and
1945: Sparc, setting the condition code directly from an add or subtract
1946: instruction does not clear the overflow bit the way that a test
1947: instruction does, so a different branch instruction must be used for
1948: some conditional branches. For machines that use @code{(cc0)}, the set
1949: and use of the condition code must be adjacent (separated only by
1950: @code{note} insns) allowing flags in @code{cc_status} to be used.
1951: (@xref{Condition Code}.) Also, the comparison and branch insns can be
1952: located from each other by using the functions @code{prev_cc0_setter}
1953: and @code{next_cc0_user}.
1954:
1955: However, this is not true on machines that do not use @code{(cc0)}. On
1956: those machines, no assumptions can be made about the adjacency of the
1957: compare and branch insns and the above methods cannot be used. Instead,
1958: we use the machine mode of the condition code register to record
1959: different formats of the condition code register.
1960:
1961: Registers used to store the condition code value should have a mode that
1962: is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
1963: additional modes are required (as for the add example mentioned above in
1964: the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
1965: additional modes required (@pxref{Condition Code}). Also define
1966: @code{EXTRA_CC_NAMES} to list the names of those modes and
1967: @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
1968:
1969: If it is known during RTL generation that a different mode will be
1970: required (for example, if the machine has separate compare instructions
1971: for signed and unsigned quantities, like most IBM processors), they can
1972: be specified at that time.
1973:
1974: If the cases that require different modes would be made by instruction
1975: combination, the macro @code{SELECT_CC_MODE} determines which machine
1976: mode should be used for the comparison result. The patterns should be
1977: written using that mode. To support the case of the add on the Sparc
1978: discussed above, we have the pattern
1979:
1980: @example
1981: (define_insn ""
1982: [(set (reg:CC_NOOV 0)
1.1.1.4 ! root 1983: (compare:CC_NOOV (plus:SI (match_operand:SI 0 "register_operand" "%r")
! 1984: (match_operand:SI 1 "arith_operand" "rI"))
! 1985: (const_int 0)))]
1.1 root 1986: ""
1987: "@dots{}")
1988: @end example
1989:
1990: The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
1991: for comparisons whose argument is a @code{plus}.
1992:
1993: @node Insn Canonicalizations, Peephole Definitions, Jump Patterns, Machine Desc
1994: @section Canonicalization of Instructions
1995: @cindex canonicalization of instructions
1996: @cindex insn canonicalization
1997:
1998: There are often cases where multiple RTL expressions could represent an
1.1.1.2 root 1999: operation performed by a single machine instruction. This situation is
1.1 root 2000: most commonly encountered with logical, branch, and multiply-accumulate
2001: instructions. In such cases, the compiler attempts to convert these
2002: multiple RTL expressions into a single canonical form to reduce the
2003: number of insn patterns required.
2004:
2005: In addition to algebraic simplifications, following canonicalizations
2006: are performed:
2007:
2008: @itemize @bullet
2009: @item
2010: For commutative and comparison operators, a constant is always made the
2011: second operand. If a machine only supports a constant as the second
2012: operand, only patterns that match a constant in the second operand need
2013: be supplied.
2014:
2015: @cindex @code{neg}, canonicalization of
2016: @cindex @code{not}, canonicalization of
2017: @cindex @code{mult}, canonicalization of
2018: @cindex @code{plus}, canonicalization of
2019: @cindex @code{minus}, canonicalization of
2020: For these operators, if only one operand is a @code{neg}, @code{not},
2021: @code{mult}, @code{plus}, or @code{minus} expression, it will be the
2022: first operand.
2023:
2024: @cindex @code{compare}, canonicalization of
2025: @item
2026: For the @code{compare} operator, a constant is always the second operand
2027: on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
2028: machines, there are rare cases where the compiler might want to construct
2029: a @code{compare} with a constant as the first operand. However, these
2030: cases are not common enough for it to be worthwhile to provide a pattern
2031: matching a constant as the first operand unless the machine actually has
2032: such an instruction.
2033:
2034: An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
2035: @code{minus} is made the first operand under the same conditions as
2036: above.
2037:
2038: @item
2039: @code{(minus @var{x} (const_int @var{n}))} is converted to
2040: @code{(plus @var{x} (const_int @var{-n}))}.
2041:
2042: @item
2043: Within address computations (i.e., inside @code{mem}), a left shift is
2044: converted into the appropriate multiplication by a power of two.
2045:
2046: @cindex @code{ior}, canonicalization of
2047: @cindex @code{and}, canonicalization of
2048: @cindex De Morgan's law
2049: De`Morgan's Law is used to move bitwise negation inside a bitwise
2050: logical-and or logical-or operation. If this results in only one
2051: operand being a @code{not} expression, it will be the first one.
2052:
2053: A machine that has an instruction that performs a bitwise logical-and of one
2054: operand with the bitwise negation of the other should specify the pattern
2055: for that instruction as
2056:
2057: @example
2058: (define_insn ""
2059: [(set (match_operand:@var{m} 0 @dots{})
1.1.1.4 ! root 2060: (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
! 2061: (match_operand:@var{m} 2 @dots{})))]
1.1 root 2062: "@dots{}"
2063: "@dots{}")
2064: @end example
2065:
2066: @noindent
2067: Similarly, a pattern for a ``NAND'' instruction should be written
2068:
2069: @example
2070: (define_insn ""
2071: [(set (match_operand:@var{m} 0 @dots{})
1.1.1.4 ! root 2072: (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
! 2073: (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
1.1 root 2074: "@dots{}"
2075: "@dots{}")
2076: @end example
2077:
2078: In both cases, it is not necessary to include patterns for the many
2079: logically equivalent RTL expressions.
2080:
2081: @cindex @code{xor}, canonicalization of
2082: @item
2083: The only possible RTL expressions involving both bitwise exclusive-or
2084: and bitwise negation are @code{(xor:@var{m} @var{x}) @var{y})}
2085: and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
2086:
2087: @item
2088: The sum of three items, one of which is a constant, will only appear in
2089: the form
2090:
2091: @example
2092: (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
2093: @end example
2094:
2095: @item
2096: On machines that do not use @code{cc0},
2097: @code{(compare @var{x} (const_int 0))} will be converted to
2098: @var{x}.@refill
2099:
2100: @cindex @code{zero_extract}, canonicalization of
2101: @cindex @code{sign_extract}, canonicalization of
2102: @item
2103: Equality comparisons of a group of bits (usually a single bit) with zero
2104: will be written using @code{zero_extract} rather than the equivalent
2105: @code{and} or @code{sign_extract} operations.
2106:
2107: @end itemize
2108:
2109: @node Peephole Definitions, Expander Definitions, Insn Canonicalizations, Machine Desc
2110: @section Defining Machine-Specific Peephole Optimizers
2111: @cindex peephole optimizer definitions
2112: @cindex defining peephole optimizers
2113:
2114: In addition to instruction patterns the @file{md} file may contain
2115: definitions of machine-specific peephole optimizations.
2116:
2117: The combiner does not notice certain peephole optimizations when the data
2118: flow in the program does not suggest that it should try them. For example,
2119: sometimes two consecutive insns related in purpose can be combined even
2120: though the second one does not appear to use a register computed in the
2121: first one. A machine-specific peephole optimizer can detect such
2122: opportunities.
2123:
2124: A definition looks like this:
2125:
2126: @example
2127: (define_peephole
2128: [@var{insn-pattern-1}
2129: @var{insn-pattern-2}
2130: @dots{}]
2131: "@var{condition}"
2132: "@var{template}"
2133: "@var{optional insn-attributes}")
2134: @end example
2135:
2136: @noindent
2137: The last string operand may be omitted if you are not using any
2138: machine-specific information in this machine description. If present,
2139: it must obey the same rules as in a @code{define_insn}.
2140:
2141: In this skeleton, @var{insn-pattern-1} and so on are patterns to match
2142: consecutive insns. The optimization applies to a sequence of insns when
2143: @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
2144: the next, and so on.@refill
2145:
2146: Each of the insns matched by a peephole must also match a
2147: @code{define_insn}. Peepholes are checked only at the last stage just
2148: before code generation, and only optionally. Therefore, any insn which
2149: would match a peephole but no @code{define_insn} will cause a crash in code
2150: generation in an unoptimized compilation, or at various optimization
2151: stages.
2152:
2153: The operands of the insns are matched with @code{match_operands},
2154: @code{match_operator}, and @code{match_dup}, as usual. What is not
2155: usual is that the operand numbers apply to all the insn patterns in the
2156: definition. So, you can check for identical operands in two insns by
2157: using @code{match_operand} in one insn and @code{match_dup} in the
2158: other.
2159:
2160: The operand constraints used in @code{match_operand} patterns do not have
2161: any direct effect on the applicability of the peephole, but they will
2162: be validated afterward, so make sure your constraints are general enough
2163: to apply whenever the peephole matches. If the peephole matches
2164: but the constraints are not satisfied, the compiler will crash.
2165:
2166: It is safe to omit constraints in all the operands of the peephole; or
2167: you can write constraints which serve as a double-check on the criteria
2168: previously tested.
2169:
2170: Once a sequence of insns matches the patterns, the @var{condition} is
2171: checked. This is a C expression which makes the final decision whether to
2172: perform the optimization (we do so if the expression is nonzero). If
2173: @var{condition} is omitted (in other words, the string is empty) then the
2174: optimization is applied to every sequence of insns that matches the
2175: patterns.
2176:
2177: The defined peephole optimizations are applied after register allocation
2178: is complete. Therefore, the peephole definition can check which
2179: operands have ended up in which kinds of registers, just by looking at
2180: the operands.
2181:
2182: @findex prev_nonnote_insn
2183: The way to refer to the operands in @var{condition} is to write
2184: @code{operands[@var{i}]} for operand number @var{i} (as matched by
2185: @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
2186: to refer to the last of the insns being matched; use
2187: @code{prev_nonnote_insn} to find the preceding insns.
2188:
2189: @findex dead_or_set_p
2190: When optimizing computations with intermediate results, you can use
2191: @var{condition} to match only when the intermediate results are not used
2192: elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
2193: @var{op})}, where @var{insn} is the insn in which you expect the value
2194: to be used for the last time (from the value of @code{insn}, together
2195: with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
2196: value (from @code{operands[@var{i}]}).@refill
2197:
2198: Applying the optimization means replacing the sequence of insns with one
2199: new insn. The @var{template} controls ultimate output of assembler code
2200: for this combined insn. It works exactly like the template of a
2201: @code{define_insn}. Operand numbers in this template are the same ones
2202: used in matching the original sequence of insns.
2203:
2204: The result of a defined peephole optimizer does not need to match any of
2205: the insn patterns in the machine description; it does not even have an
2206: opportunity to match them. The peephole optimizer definition itself serves
2207: as the insn pattern to control how the insn is output.
2208:
2209: Defined peephole optimizers are run as assembler code is being output,
2210: so the insns they produce are never combined or rearranged in any way.
2211:
2212: Here is an example, taken from the 68000 machine description:
2213:
2214: @example
2215: (define_peephole
2216: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
1.1.1.3 root 2217: (set (match_operand:DF 0 "register_operand" "=f")
1.1 root 2218: (match_operand:DF 1 "register_operand" "ad"))]
2219: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
2220: "*
2221: @{
2222: rtx xoperands[2];
2223: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2224: #ifdef MOTOROLA
2225: output_asm_insn (\"move.l %1,(sp)\", xoperands);
2226: output_asm_insn (\"move.l %1,-(sp)\", operands);
2227: return \"fmove.d (sp)+,%0\";
2228: #else
2229: output_asm_insn (\"movel %1,sp@@\", xoperands);
2230: output_asm_insn (\"movel %1,sp@@-\", operands);
2231: return \"fmoved sp@@+,%0\";
2232: #endif
2233: @}
2234: ")
2235: @end example
2236:
2237: The effect of this optimization is to change
2238:
2239: @example
2240: jbsr _foobar
2241: addql #4,sp
2242: movel d1,sp@@-
2243: movel d0,sp@@-
2244: fmoved sp@@+,fp0
2245: @end example
2246:
2247: @noindent
2248: into
2249:
2250: @example
2251: jbsr _foobar
2252: movel d1,sp@@
2253: movel d0,sp@@-
2254: fmoved sp@@+,fp0
2255: @end example
2256:
2257: @ignore
2258: @findex CC_REVERSED
2259: If a peephole matches a sequence including one or more jump insns, you must
2260: take account of the flags such as @code{CC_REVERSED} which specify that the
2261: condition codes are represented in an unusual manner. The compiler
2262: automatically alters any ordinary conditional jumps which occur in such
2263: situations, but the compiler cannot alter jumps which have been replaced by
2264: peephole optimizations. So it is up to you to alter the assembler code
2265: that the peephole produces. Supply C code to write the assembler output,
2266: and in this C code check the condition code status flags and change the
2267: assembler code as appropriate.
2268: @end ignore
2269:
2270: @var{insn-pattern-1} and so on look @emph{almost} like the second
2271: operand of @code{define_insn}. There is one important difference: the
2272: second operand of @code{define_insn} consists of one or more RTX's
2273: enclosed in square brackets. Usually, there is only one: then the same
2274: action can be written as an element of a @code{define_peephole}. But
2275: when there are multiple actions in a @code{define_insn}, they are
2276: implicitly enclosed in a @code{parallel}. Then you must explicitly
2277: write the @code{parallel}, and the square brackets within it, in the
2278: @code{define_peephole}. Thus, if an insn pattern looks like this,
2279:
2280: @example
2281: (define_insn "divmodsi4"
2282: [(set (match_operand:SI 0 "general_operand" "=d")
2283: (div:SI (match_operand:SI 1 "general_operand" "0")
2284: (match_operand:SI 2 "general_operand" "dmsK")))
2285: (set (match_operand:SI 3 "general_operand" "=d")
2286: (mod:SI (match_dup 1) (match_dup 2)))]
2287: "TARGET_68020"
2288: "divsl%.l %2,%3:%0")
2289: @end example
2290:
2291: @noindent
2292: then the way to mention this insn in a peephole is as follows:
2293:
2294: @example
2295: (define_peephole
2296: [@dots{}
2297: (parallel
2298: [(set (match_operand:SI 0 "general_operand" "=d")
2299: (div:SI (match_operand:SI 1 "general_operand" "0")
2300: (match_operand:SI 2 "general_operand" "dmsK")))
2301: (set (match_operand:SI 3 "general_operand" "=d")
2302: (mod:SI (match_dup 1) (match_dup 2)))])
2303: @dots{}]
2304: @dots{})
2305: @end example
2306:
2307: @node Expander Definitions, Insn Splitting, Peephole Definitions, Machine Desc
2308: @section Defining RTL Sequences for Code Generation
2309: @cindex expander definitions
2310: @cindex code generation RTL sequences
2311: @cindex defining RTL sequences for code generation
2312:
2313: On some target machines, some standard pattern names for RTL generation
2314: cannot be handled with single insn, but a sequence of RTL insns can
2315: represent them. For these target machines, you can write a
2316: @code{define_expand} to specify how to generate the sequence of RTL.
2317:
2318: @findex define_expand
2319: A @code{define_expand} is an RTL expression that looks almost like a
2320: @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
2321: only for RTL generation and it can produce more than one RTL insn.
2322:
2323: A @code{define_expand} RTX has four operands:
2324:
2325: @itemize @bullet
2326: @item
2327: The name. Each @code{define_expand} must have a name, since the only
2328: use for it is to refer to it by name.
2329:
2330: @findex define_peephole
2331: @item
2332: The RTL template. This is just like the RTL template for a
2333: @code{define_peephole} in that it is a vector of RTL expressions
2334: each being one insn.
2335:
2336: @item
2337: The condition, a string containing a C expression. This expression is
2338: used to express how the availability of this pattern depends on
2339: subclasses of target machine, selected by command-line options when
2340: GNU CC is run. This is just like the condition of a
2341: @code{define_insn} that has a standard name.
2342:
2343: @item
2344: The preparation statements, a string containing zero or more C
2345: statements which are to be executed before RTL code is generated from
2346: the RTL template.
2347:
2348: Usually these statements prepare temporary registers for use as
2349: internal operands in the RTL template, but they can also generate RTL
2350: insns directly by calling routines such as @code{emit_insn}, etc.
2351: Any such insns precede the ones that come from the RTL template.
2352: @end itemize
2353:
2354: Every RTL insn emitted by a @code{define_expand} must match some
2355: @code{define_insn} in the machine description. Otherwise, the compiler
2356: will crash when trying to generate code for the insn or trying to optimize
2357: it.
2358:
2359: The RTL template, in addition to controlling generation of RTL insns,
2360: also describes the operands that need to be specified when this pattern
2361: is used. In particular, it gives a predicate for each operand.
2362:
2363: A true operand, which needs to be specified in order to generate RTL from
2364: the pattern, should be described with a @code{match_operand} in its first
2365: occurrence in the RTL template. This enters information on the operand's
2366: predicate into the tables that record such things. GNU CC uses the
2367: information to preload the operand into a register if that is required for
2368: valid RTL code. If the operand is referred to more than once, subsequent
2369: references should use @code{match_dup}.
2370:
2371: The RTL template may also refer to internal ``operands'' which are
2372: temporary registers or labels used only within the sequence made by the
2373: @code{define_expand}. Internal operands are substituted into the RTL
2374: template with @code{match_dup}, never with @code{match_operand}. The
2375: values of the internal operands are not passed in as arguments by the
2376: compiler when it requests use of this pattern. Instead, they are computed
2377: within the pattern, in the preparation statements. These statements
2378: compute the values and store them into the appropriate elements of
2379: @code{operands} so that @code{match_dup} can find them.
2380:
2381: There are two special macros defined for use in the preparation statements:
2382: @code{DONE} and @code{FAIL}. Use them with a following semicolon,
2383: as a statement.
2384:
2385: @table @code
2386:
2387: @findex DONE
2388: @item DONE
2389: Use the @code{DONE} macro to end RTL generation for the pattern. The
2390: only RTL insns resulting from the pattern on this occasion will be
2391: those already emitted by explicit calls to @code{emit_insn} within the
2392: preparation statements; the RTL template will not be generated.
2393:
2394: @findex FAIL
2395: @item FAIL
2396: Make the pattern fail on this occasion. When a pattern fails, it means
2397: that the pattern was not truly available. The calling routines in the
2398: compiler will try other strategies for code generation using other patterns.
2399:
2400: Failure is currently supported only for binary (addition, multiplication,
2401: shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
2402: operations.
2403: @end table
2404:
2405: Here is an example, the definition of left-shift for the SPUR chip:
2406:
2407: @example
2408: (define_expand "ashlsi3"
2409: [(set (match_operand:SI 0 "register_operand" "")
2410: (ashift:SI
2411: (match_operand:SI 1 "register_operand" "")
2412: (match_operand:SI 2 "nonmemory_operand" "")))]
2413: ""
2414: "
2415: @{
2416: if (GET_CODE (operands[2]) != CONST_INT
2417: || (unsigned) INTVAL (operands[2]) > 3)
2418: FAIL;
2419: @}")
2420: @end example
2421:
2422: @noindent
2423: This example uses @code{define_expand} so that it can generate an RTL insn
2424: for shifting when the shift-count is in the supported range of 0 to 3 but
2425: fail in other cases where machine insns aren't available. When it fails,
2426: the compiler tries another strategy using different patterns (such as, a
2427: library call).
2428:
2429: If the compiler were able to handle nontrivial condition-strings in
2430: patterns with names, then it would be possible to use a
2431: @code{define_insn} in that case. Here is another case (zero-extension
2432: on the 68000) which makes more use of the power of @code{define_expand}:
2433:
2434: @example
2435: (define_expand "zero_extendhisi2"
2436: [(set (match_operand:SI 0 "general_operand" "")
2437: (const_int 0))
2438: (set (strict_low_part
2439: (subreg:HI
2440: (match_dup 0)
2441: 0))
2442: (match_operand:HI 1 "general_operand" ""))]
2443: ""
2444: "operands[1] = make_safe_from (operands[1], operands[0]);")
2445: @end example
2446:
2447: @noindent
2448: @findex make_safe_from
2449: Here two RTL insns are generated, one to clear the entire output operand
2450: and the other to copy the input operand into its low half. This sequence
2451: is incorrect if the input operand refers to [the old value of] the output
2452: operand, so the preparation statement makes sure this isn't so. The
2453: function @code{make_safe_from} copies the @code{operands[1]} into a
2454: temporary register if it refers to @code{operands[0]}. It does this
2455: by emitting another RTL insn.
2456:
2457: Finally, a third example shows the use of an internal operand.
2458: Zero-extension on the SPUR chip is done by @code{and}-ing the result
2459: against a halfword mask. But this mask cannot be represented by a
2460: @code{const_int} because the constant value is too large to be legitimate
2461: on this machine. So it must be copied into a register with
2462: @code{force_reg} and then the register used in the @code{and}.
2463:
2464: @example
2465: (define_expand "zero_extendhisi2"
2466: [(set (match_operand:SI 0 "register_operand" "")
2467: (and:SI (subreg:SI
2468: (match_operand:HI 1 "register_operand" "")
2469: 0)
2470: (match_dup 2)))]
2471: ""
2472: "operands[2]
2473: = force_reg (SImode, gen_rtx (CONST_INT,
2474: VOIDmode, 65535)); ")
2475: @end example
2476:
2477: @strong{Note:} If the @code{define_expand} is used to serve a
2478: standard binary or unary arithmetic operation or a bitfield operation,
2479: then the last insn it generates must not be a @code{code_label},
2480: @code{barrier} or @code{note}. It must be an @code{insn},
2481: @code{jump_insn} or @code{call_insn}. If you don't need a real insn
2482: at the end, emit an insn to copy the result of the operation into
2483: itself. Such an insn will generate no code, but it can avoid problems
2484: in the compiler.@refill
2485:
2486: @node Insn Splitting, Insn Attributes, Expander Definitions, Machine Desc
2487: @section Splitting Instructions into Multiple Instructions
2488: @cindex insn splitting
2489: @cindex instruction splitting
2490: @cindex splitting instructions
2491:
1.1.1.3 root 2492: There are two cases where you should specify how to split a pattern into
2493: multiple insns. On machines that have instructions requiring delay
2494: slots (@pxref{Delay Slots}) or that have instructions whose output is
2495: not available for multiple cycles (@pxref{Function Units}), the compiler
2496: phases that optimize these cases need to be able to move insns into
2497: one-cycle delay slots. However, some insns may generate more than one
2498: machine instruction. These insns cannot be placed into a delay slot.
2499:
2500: Often you can rewrite the single insn as a list of individual insns,
2501: each corresponding to one machine instruction. The disadvantage of
2502: doing so is that it will cause the compilation to be slower and require
2503: more space. If the resulting insns are too complex, it may also
2504: suppress some optimizations. The compiler splits the insn if there is a
2505: reason to believe that it might improve instruction or delay slot
2506: scheduling.
2507:
2508: The insn combiner phase also splits putative insns. If three insns are
2509: merged into one insn with a complex expression that cannot be matched by
2510: some @code{define_insn} pattern, the combiner phase attempts to split
2511: the complex pattern into two insns that are recognized. Usually it can
2512: break the complex pattern into two patterns by splitting out some
2513: subexpression. However, in some other cases, such as performing an
2514: addition of a large constant in two insns on a RISC machine, the way to
2515: split the addition into two insns is machine-dependent.
1.1 root 2516:
1.1.1.3 root 2517: @cindex define_split
1.1 root 2518: The @code{define_split} definition tells the compiler how to split a
1.1.1.3 root 2519: complex insn into several simpler insns. It looks like this:
1.1 root 2520:
2521: @example
2522: (define_split
2523: [@var{insn-pattern}]
2524: "@var{condition}"
2525: [@var{new-insn-pattern-1}
2526: @var{new-insn-pattern-2}
2527: @dots{}]
2528: "@var{preparation statements}")
2529: @end example
2530:
2531: @var{insn-pattern} is a pattern that needs to be split and
2532: @var{condition} is the final condition to be tested, as in a
1.1.1.3 root 2533: @code{define_insn}. When an insn matching @var{insn-pattern} and
2534: satisfying @var{condition} is found, it is replaced in the insn list
2535: with the insns given by @var{new-insn-pattern-1},
2536: @var{new-insn-pattern-2}, etc.
1.1 root 2537:
2538: The @var{preparation statements} are similar to those specified for
2539: @code{define_expand} (@pxref{Expander Definitions}) and are executed
2540: before the new RTL is generated to prepare for the generated code
1.1.1.4 ! root 2541: or emit some insns whose pattern is not fixed. Unlike those in
! 2542: @code{define_expand}, however, these statements must not generate
! 2543: any new pseudo-registers. Once reload has completed, they also
! 2544: must not allocate any space in the stack frame.
1.1 root 2545:
1.1.1.3 root 2546: Patterns are matched against @var{insn-pattern} in two different
2547: circumstances. If an insn needs to be split for delay slot scheduling
2548: or insn scheduling, the insn is already known to be valid, which means
2549: that it must have been matched by some @code{define_insn} and, if
2550: @code{reload_completed} is non-zero, is known to satisfy the constraints
2551: of that @code{define_insn}. In that case, the new insn patterns must
2552: also be insns that are matched by some @code{define_insn} and, if
2553: @code{reload_completed} is non-zero, must also satisfy the constraints
2554: of those definitions.
2555:
2556: As an example of this usage of @code{define_split}, consider the following
2557: example from @file{a29k.md}, which splits a @code{sign_extend} from
1.1 root 2558: @code{HImode} to @code{SImode} into a pair of shift insns:
2559:
2560: @example
2561: (define_split
2562: [(set (match_operand:SI 0 "gen_reg_operand" "")
1.1.1.4 ! root 2563: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
1.1 root 2564: ""
2565: [(set (match_dup 0)
1.1.1.4 ! root 2566: (ashift:SI (match_dup 1)
! 2567: (const_int 16)))
1.1 root 2568: (set (match_dup 0)
1.1.1.4 ! root 2569: (ashiftrt:SI (match_dup 0)
! 2570: (const_int 16)))]
1.1 root 2571: "
2572: @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
2573: @end example
2574:
1.1.1.3 root 2575: When the combiner phase tries to split an insn pattern, it is always the
2576: case that the pattern is @emph{not} matched by any @code{define_insn}.
2577: The combiner pass first tries to split a single @code{set} expression
2578: and then the same @code{set} expression inside a @code{parallel}, but
2579: followed by a @code{clobber} of a pseudo-reg to use as a scratch
2580: register. In these cases, the combiner expects exactly two new insn
2581: patterns to be generated. It will verify that these patterns match some
2582: @code{define_insn} definitions, so you need not do this test in the
2583: @code{define_split} (of course, there is no point in writing a
2584: @code{define_split} that will never produce insns that match).
2585:
2586: Here is an example of this use of @code{define_split}, taken from
2587: @file{rs6000.md}:
2588:
2589: @example
2590: (define_split
2591: [(set (match_operand:SI 0 "gen_reg_operand" "")
1.1.1.4 ! root 2592: (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
! 2593: (match_operand:SI 2 "non_add_cint_operand" "")))]
1.1.1.3 root 2594: ""
2595: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
2596: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
2597: "
2598: @{
2599: int low = INTVAL (operands[2]) & 0xffff;
2600: int high = (unsigned) INTVAL (operands[2]) >> 16;
2601:
2602: if (low & 0x8000)
2603: high++, low |= 0xffff0000;
2604:
2605: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
2606: operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
2607: @}")
2608: @end example
2609:
2610: Here the predicate @code{non_add_cint_operand} matches any
2611: @code{const_int} that is @emph{not} a valid operand of a single add
2612: insn. Write the add with the smaller displacement is written so that it
2613: can be substituted into the address of a subsequent operation.
2614:
2615: An example that uses a scratch register, from the same file, generates
2616: an equality comparison of a register and a large constant:
2617:
2618: @example
2619: (define_split
2620: [(set (match_operand:CC 0 "cc_reg_operand" "")
1.1.1.4 ! root 2621: (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
! 2622: (match_operand:SI 2 "non_short_cint_operand" "")))
1.1.1.3 root 2623: (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
2624: "find_single_use (operands[0], insn, 0)
2625: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
2626: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
2627: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
2628: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
2629: "
2630: @{
2631: /* Get the constant we are comparing against, C, and see what it looks like
2632: sign-extended to 16 bits. Then see what constant could be XOR'ed
2633: with C to get the sign-extended value. */
2634:
2635: int c = INTVAL (operands[2]);
2636: int sextc = (c << 16) >> 16;
2637: int xorv = c ^ sextc;
2638:
2639: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
2640: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
2641: @}")
2642: @end example
2643:
2644: To avoid confusion, don't write a single @code{define_split} that
2645: accepts some insns that match some @code{define_insn} as well as some
2646: insns that don't. Instead, write two separate @code{define_split}
2647: definitions, one for the insns that are valid and one for the insns that
2648: are not valid.
2649:
1.1 root 2650: @node Insn Attributes,, Insn Splitting, Machine Desc
2651: @section Instruction Attributes
2652: @cindex insn attributes
2653: @cindex instruction attributes
2654:
2655: In addition to describing the instruction supported by the target machine,
2656: the @file{md} file also defines a group of @dfn{attributes} and a set of
2657: values for each. Every generated insn is assigned a value for each attribute.
2658: One possible attribute would be the effect that the insn has on the machine's
2659: condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
2660: to track the condition codes.
2661:
2662: @menu
2663: * Defining Attributes:: Specifying attributes and their values.
2664: * Expressions:: Valid expressions for attribute values.
2665: * Tagging Insns:: Assigning attribute values to insns.
2666: * Attr Example:: An example of assigning attributes.
2667: * Insn Lengths:: Computing the length of insns.
1.1.1.2 root 2668: * Constant Attributes:: Defining attributes that are constant.
1.1 root 2669: * Delay Slots:: Defining delay slots required for a machine.
2670: * Function Units:: Specifying information for insn scheduling.
2671: @end menu
2672:
2673: @node Defining Attributes, Expressions, Insn Attributes, Insn Attributes
2674: @subsection Defining Attributes and their Values
2675: @cindex defining attributes and their values
2676: @cindex attributes, defining
2677:
2678: @findex define_attr
2679: The @code{define_attr} expression is used to define each attribute required
2680: by the target machine. It looks like:
2681:
2682: @example
2683: (define_attr @var{name} @var{list-of-values} @var{default})
2684: @end example
2685:
2686: @var{name} is a string specifying the name of the attribute being defined.
2687:
2688: @var{list-of-values} is either a string that specifies a comma-separated
2689: list of values that can be assigned to the attribute, or a null string to
2690: indicate that the attribute takes numeric values.
2691:
2692: @var{default} is an attribute expression that gives the value of this
2693: attribute for insns that match patterns whose definition does not include
2694: an explicit value for this attribute. @xref{Attr Example}, for more
1.1.1.2 root 2695: information on the handling of defaults. @xref{Constant Attributes},
2696: for information on attributes that do not depend on any particular insn.
1.1 root 2697:
2698: @findex insn-attr.h
2699: For each defined attribute, a number of definitions are written to the
2700: @file{insn-attr.h} file. For cases where an explicit set of values is
2701: specified for an attribute, the following are defined:
2702:
2703: @itemize @bullet
2704: @item
2705: A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
2706:
2707: @item
2708: An enumeral class is defined for @samp{attr_@var{name}} with
2709: elements of the form @samp{@var{upper-name}_@var{upper-value}} where
2710: the attribute name and value are first converted to upper case.
2711:
2712: @item
2713: A function @samp{get_attr_@var{name}} is defined that is passed an insn and
2714: returns the attribute value for that insn.
2715: @end itemize
2716:
2717: For example, if the following is present in the @file{md} file:
2718:
2719: @example
2720: (define_attr "type" "branch,fp,load,store,arith" @dots{})
2721: @end example
2722:
2723: @noindent
2724: the following lines will be written to the file @file{insn-attr.h}.
2725:
2726: @example
2727: #define HAVE_ATTR_type
2728: enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
1.1.1.4 ! root 2729: TYPE_STORE, TYPE_ARITH@};
1.1 root 2730: extern enum attr_type get_attr_type ();
2731: @end example
2732:
2733: If the attribute takes numeric values, no @code{enum} type will be
2734: defined and the function to obtain the attribute's value will return
2735: @code{int}.
2736:
2737: @node Expressions, Tagging Insns, Defining Attributes, Insn Attributes
2738: @subsection Attribute Expressions
2739: @cindex attribute expressions
2740:
2741: RTL expressions used to define attributes use the codes described above
2742: plus a few specific to attribute definitions, to be discussed below.
2743: Attribute value expressions must have one of the following forms:
2744:
2745: @table @code
2746: @cindex @code{const_int} and attributes
2747: @item (const_int @var{i})
2748: The integer @var{i} specifies the value of a numeric attribute. @var{i}
2749: must be non-negative.
2750:
2751: The value of a numeric attribute can be specified either with a
2752: @code{const_int} or as an integer represented as a string in
2753: @code{const_string}, @code{eq_attr} (see below), and @code{set_attr}
2754: (@pxref{Tagging Insns}) expressions.
2755:
2756: @cindex @code{const_string} and attributes
2757: @item (const_string @var{value})
2758: The string @var{value} specifies a constant attribute value.
2759: If @var{value} is specified as @samp{"*"}, it means that the default value of
2760: the attribute is to be used for the insn containing this expression.
2761: @samp{"*"} obviously cannot be used in the @var{default} expression
2762: of a @code{define_attr}.@refill
2763:
2764: If the attribute whose value is being specified is numeric, @var{value}
2765: must be a string containing a non-negative integer (normally
2766: @code{const_int} would be used in this case). Otherwise, it must
2767: contain one of the valid values for the attribute.
2768:
2769: @cindex @code{if_then_else} and attributes
2770: @item (if_then_else @var{test} @var{true-value} @var{false-value})
2771: @var{test} specifies an attribute test, whose format is defined below.
2772: The value of this expression is @var{true-value} if @var{test} is true,
2773: otherwise it is @var{false-value}.
2774:
2775: @cindex @code{cond} and attributes
2776: @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
2777: The first operand of this expression is a vector containing an even
2778: number of expressions and consisting of pairs of @var{test} and @var{value}
2779: expressions. The value of the @code{cond} expression is that of the
2780: @var{value} corresponding to the first true @var{test} expression. If
2781: none of the @var{test} expressions are true, the value of the @code{cond}
2782: expression is that of the @var{default} expression.
2783: @end table
2784:
2785: @var{test} expressions can have one of the following forms:
2786:
2787: @table @code
2788: @cindex @code{const_int} and attribute tests
2789: @item (const_int @var{i})
2790: This test is true if @var{i} is non-zero and false otherwise.
2791:
2792: @cindex @code{not} and attributes
2793: @cindex @code{ior} and attributes
2794: @cindex @code{and} and attributes
2795: @item (not @var{test})
2796: @itemx (ior @var{test1} @var{test2})
2797: @itemx (and @var{test1} @var{test2})
2798: These tests are true if the indicated logical function is true.
2799:
2800: @cindex @code{match_operand} and attributes
2801: @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
2802: This test is true if operand @var{n} of the insn whose attribute value
2803: is being determined has mode @var{m} (this part of the test is ignored
2804: if @var{m} is @code{VOIDmode}) and the function specified by the string
2805: @var{pred} returns a non-zero value when passed operand @var{n} and mode
2806: @var{m} (this part of the test is ignored if @var{pred} is the null
2807: string).
2808:
2809: The @var{constraints} operand is ignored and should be the null string.
2810:
2811: @cindex @code{le} and attributes
2812: @cindex @code{leu} and attributes
2813: @cindex @code{lt} and attributes
2814: @cindex @code{gt} and attributes
2815: @cindex @code{gtu} and attributes
2816: @cindex @code{ge} and attributes
2817: @cindex @code{geu} and attributes
2818: @cindex @code{ne} and attributes
2819: @cindex @code{eq} and attributes
2820: @cindex @code{plus} and attributes
2821: @cindex @code{minus} and attributes
2822: @cindex @code{mult} and attributes
2823: @cindex @code{div} and attributes
2824: @cindex @code{mod} and attributes
2825: @cindex @code{abs} and attributes
2826: @cindex @code{neg} and attributes
2827: @cindex @code{lshift} and attributes
2828: @cindex @code{ashift} and attributes
2829: @cindex @code{lshiftrt} and attributes
2830: @cindex @code{ashiftrt} and attributes
2831: @item (le @var{arith1} @var{arith2})
2832: @itemx (leu @var{arith1} @var{arith2})
2833: @itemx (lt @var{arith1} @var{arith2})
2834: @itemx (ltu @var{arith1} @var{arith2})
2835: @itemx (gt @var{arith1} @var{arith2})
2836: @itemx (gtu @var{arith1} @var{arith2})
2837: @itemx (ge @var{arith1} @var{arith2})
2838: @itemx (geu @var{arith1} @var{arith2})
2839: @itemx (ne @var{arith1} @var{arith2})
2840: @itemx (eq @var{arith1} @var{arith2})
2841: These tests are true if the indicated comparison of the two arithmetic
2842: expressions is true. Arithmetic expressions are formed with
2843: @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
2844: @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
2845: @code{lshift}, @code{ashift}, @code{lshiftrt}, and @code{ashiftrt}
2846: expressions.@refill
2847:
2848: @findex get_attr
2849: @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
2850: Lengths},for additional forms). @code{symbol_ref} is a string
2851: denoting a C expression that yields an @code{int} when evaluated by the
2852: @samp{get_attr_@dots{}} routine. It should normally be a global
2853: variable.@refill
2854:
2855: @findex eq_attr
2856: @item (eq_attr @var{name} @var{value})
2857: @var{name} is a string specifying the name of an attribute.
2858:
2859: @var{value} is a string that is either a valid value for attribute
2860: @var{name}, a comma-separated list of values, or @samp{!} followed by a
2861: value or list. If @var{value} does not begin with a @samp{!}, this
2862: test is true if the value of the @var{name} attribute of the current
2863: insn is in the list specified by @var{value}. If @var{value} begins
2864: with a @samp{!}, this test is true if the attribute's value is
2865: @emph{not} in the specified list.
2866:
2867: For example,
2868:
2869: @example
2870: (eq_attr "type" "load,store")
2871: @end example
2872:
2873: @noindent
2874: is equivalent to
2875:
2876: @example
2877: (ior (eq_attr "type" "load") (eq_attr "type" "store"))
2878: @end example
2879:
2880: If @var{name} specifies an attribute of @samp{alternative}, it refers to the
2881: value of the compiler variable @code{which_alternative}
2882: (@pxref{Output Statement}) and the values must be small integers. For
2883: example,@refill
2884:
2885: @example
2886: (eq_attr "alternative" "2,3")
2887: @end example
2888:
2889: @noindent
2890: is equivalent to
2891:
2892: @example
2893: (ior (eq (symbol_ref "which_alternative") (const_int 2))
2894: (eq (symbol_ref "which_alternative") (const_int 3)))
2895: @end example
2896:
2897: Note that, for most attributes, an @code{eq_attr} test is simplified in cases
2898: where the value of the attribute being tested is known for all insns matching
2899: a particular pattern. This is by far the most common case.@refill
2900: @end table
2901:
2902: @node Tagging Insns, Attr Example, Expressions, Insn Attributes
2903: @subsection Assigning Attribute Values to Insns
2904: @cindex tagging insns
2905: @cindex assigning attribute values to insns
2906:
2907: The value assigned to an attribute of an insn is primarily determined by
2908: which pattern is matched by that insn (or which @code{define_peephole}
2909: generated it). Every @code{define_insn} and @code{define_peephole} can
2910: have an optional last argument to specify the values of attributes for
2911: matching insns. The value of any attribute not specified in a particular
2912: insn is set to the default value for that attribute, as specified in its
2913: @code{define_attr}. Extensive use of default values for attributes
2914: permits the specification of the values for only one or two attributes
2915: in the definition of most insn patterns, as seen in the example in the
2916: next section.@refill
2917:
2918: The optional last argument of @code{define_insn} and
2919: @code{define_peephole} is a vector of expressions, each of which defines
2920: the value for a single attribute. The most general way of assigning an
2921: attribute's value is to use a @code{set} expression whose first operand is an
2922: @code{attr} expression giving the name of the attribute being set. The
2923: second operand of the @code{set} is an attribute expression
2924: (@pxref{Expressions}) giving the value of the attribute.@refill
2925:
2926: When the attribute value depends on the @samp{alternative} attribute
2927: (i.e., which is the applicable alternative in the constraint of the
1.1.1.4 ! root 2928: insn), the @code{set_attr_alternative} expression can be used. It
1.1 root 2929: allows the specification of a vector of attribute expressions, one for
2930: each alternative.
2931:
2932: @findex set_attr
2933: When the generality of arbitrary attribute expressions is not required,
2934: the simpler @code{set_attr} expression can be used, which allows
2935: specifying a string giving either a single attribute value or a list
2936: of attribute values, one for each alternative.
2937:
2938: The form of each of the above specifications is shown below. In each case,
2939: @var{name} is a string specifying the attribute to be set.
2940:
2941: @table @code
2942: @item (set_attr @var{name} @var{value-string})
2943: @var{value-string} is either a string giving the desired attribute value,
2944: or a string containing a comma-separated list giving the values for
2945: succeeding alternatives. The number of elements must match the number
2946: of alternatives in the constraint of the insn pattern.
2947:
2948: Note that it may be useful to specify @samp{*} for some alternative, in
2949: which case the attribute will assume its default value for insns matching
2950: that alternative.
2951:
2952: @findex set_attr_alternative
2953: @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
2954: Depending on the alternative of the insn, the value will be one of the
2955: specified values. This is a shorthand for using a @code{cond} with
2956: tests on the @samp{alternative} attribute.
2957:
2958: @findex attr
2959: @item (set (attr @var{name}) @var{value})
2960: The first operand of this @code{set} must be the special RTL expression
2961: @code{attr}, whose sole operand is a string giving the name of the
2962: attribute being set. @var{value} is the value of the attribute.
2963: @end table
2964:
2965: The following shows three different ways of representing the same
2966: attribute value specification:
2967:
2968: @example
2969: (set_attr "type" "load,store,arith")
2970:
2971: (set_attr_alternative "type"
2972: [(const_string "load") (const_string "store")
2973: (const_string "arith")])
2974:
2975: (set (attr "type")
2976: (cond [(eq_attr "alternative" "1") (const_string "load")
2977: (eq_attr "alternative" "2") (const_string "store")]
2978: (const_string "arith")))
2979: @end example
2980:
2981: @findex define_asm_attributes
2982: The @code{define_asm_attributes} expression provides a mechanism to
2983: specify the attributes assigned to insns produced from an @code{asm}
2984: statement. It has the form:
2985:
2986: @example
2987: (define_asm_attributes [@var{attr-sets}])
2988: @end example
2989:
2990: @noindent
2991: where @var{attr-sets} is specified the same as for @code{define_insn}
2992: and @code{define_peephole} expressions.
2993:
2994: These values will typically be the ``worst case'' attribute values. For
2995: example, they might indicate that the condition code will be clobbered.
2996:
2997: A specification for a @code{length} attribute is handled specially. To
2998: compute the length of an @code{asm} insn, the length specified in the
2999: @code{define_asm_attributes} expression is multiplied by the number of
3000: machine instructions specified in the @code{asm} statement, determined
3001: by counting the number of semicolons and newlines in the string.
3002: Therefore, the value of the @code{length} attribute specified in a
3003: @code{define_asm_attributes} should be the maximum possible length of a
3004: single machine instruction.
3005:
3006: @node Attr Example, Insn Lengths, Tagging Insns, Insn Attributes
3007: @subsection Example of Attribute Specifications
3008: @cindex attribute specifications example
3009: @cindex attribute specifications
3010:
3011: The judicious use of defaulting is important in the efficient use of
3012: insn attributes. Typically, insns are divided into @dfn{types} and an
3013: attribute, customarily called @code{type}, is used to represent this
3014: value. This attribute is normally used only to define the default value
3015: for other attributes. An example will clarify this usage.
3016:
3017: Assume we have a RISC machine with a condition code and in which only
3018: full-word operations are performed in registers. Let us assume that we
3019: can divide all insns into loads, stores, (integer) arithmetic
3020: operations, floating point operations, and branches.
3021:
3022: Here we will concern ourselves with determining the effect of an insn on
3023: the condition code and will limit ourselves to the following possible
3024: effects: The condition code can be set unpredictably (clobbered), not
3025: be changed, be set to agree with the results of the operation, or only
3026: changed if the item previously set into the condition code has been
3027: modified.
3028:
3029: Here is part of a sample @file{md} file for such a machine:
3030:
3031: @example
3032: (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
3033:
3034: (define_attr "cc" "clobber,unchanged,set,change0"
3035: (cond [(eq_attr "type" "load")
3036: (const_string "change0")
3037: (eq_attr "type" "store,branch")
3038: (const_string "unchanged")
3039: (eq_attr "type" "arith")
3040: (if_then_else (match_operand:SI 0 "" "")
3041: (const_string "set")
3042: (const_string "clobber"))]
3043: (const_string "clobber")))
3044:
3045: (define_insn ""
3046: [(set (match_operand:SI 0 "general_operand" "=r,r,m")
3047: (match_operand:SI 1 "general_operand" "r,m,r"))]
3048: ""
3049: "@@
3050: move %0,%1
3051: load %0,%1
3052: store %0,%1"
3053: [(set_attr "type" "arith,load,store")])
3054: @end example
3055:
3056: Note that we assume in the above example that arithmetic operations
3057: performed on quantities smaller than a machine word clobber the condition
3058: code since they will set the condition code to a value corresponding to the
3059: full-word result.
3060:
1.1.1.2 root 3061: @node Insn Lengths, Constant Attributes, Attr Example, Insn Attributes
1.1 root 3062: @subsection Computing the Length of an Insn
3063: @cindex insn lengths, computing
3064: @cindex computing the length of an insn
3065:
3066: For many machines, multiple types of branch instructions are provided, each
3067: for different length branch displacements. In most cases, the assembler
3068: will choose the correct instruction to use. However, when the assembler
3069: cannot do so, GCC can when a special attribute, the @samp{length}
3070: attribute, is defined. This attribute must be defined to have numeric
3071: values by specifying a null string in its @code{define_attr}.
3072:
3073: In the case of the @samp{length} attribute, two additional forms of
3074: arithmetic terms are allowed in test expressions:
3075:
3076: @table @code
3077: @cindex @code{match_dup} and attributes
3078: @item (match_dup @var{n})
3079: This refers to the address of operand @var{n} of the current insn, which
3080: must be a @code{label_ref}.
3081:
3082: @cindex @code{pc} and attributes
3083: @item (pc)
3084: This refers to the address of the @emph{current} insn. It might have
3085: been more consistent with other usage to make this the address of the
3086: @emph{next} insn but this would be confusing because the length of the
3087: current insn is to be computed.
3088: @end table
3089:
3090: @cindex @code{addr_vec}, length of
3091: @cindex @code{addr_diff_vec}, length of
3092: For normal insns, the length will be determined by value of the
3093: @samp{length} attribute. In the case of @code{addr_vec} and
3094: @code{addr_diff_vec} insn patterns, the length will be computed as
3095: the number of vectors multiplied by the size of each vector.@refill
3096:
3097: The following macros can be used to refine the length computation:
3098:
3099: @table @code
3100: @findex FIRST_INSN_ADDRESS
3101: @item FIRST_INSN_ADDRESS
3102: When the @code{length} insn attribute is used, this macro specifies the
3103: value to be assigned to the address of the first insn in a function. If
3104: not specified, 0 is used.
3105:
3106: @findex ADJUST_INSN_LENGTH
3107: @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
3108: If defined, modifies the length assigned to instruction @var{insn} as a
3109: function of the context in which it is used. @var{length} is an lvalue
3110: that contains the initially computed length of the insn and should be
3111: updated with the correct length of the insn. If updating is required,
3112: @var{insn} must not be a varying-length insn.
3113:
3114: This macro will normally not be required. A case in which it is
3115: required is the ROMP. On this machine, the size of an @code{addr_vec}
3116: insn must be increased by two to compensate for the fact that alignment
3117: may be required.
3118: @end table
3119:
1.1.1.2 root 3120: @findex get_attr_length
1.1 root 3121: The routine that returns the value of the @code{length} attribute,
1.1.1.2 root 3122: @code{get_attr_length}, can be used by the output routine to determine
1.1 root 3123: the form of the branch instruction to be written, as the example
3124: below illustrates.
3125:
3126: As an example of the specification of variable-length branches, consider
3127: the IBM 360. If we adopt the convention that a register will be set to
3128: the starting address of a function, we can jump to labels within 4K of
3129: the start using a four-byte instruction. Otherwise, we need a six-byte
3130: sequence to load the address from memory and then branch to it.
3131:
3132: On such a machine, a pattern for a branch instruction might be specified
3133: as follows:
3134:
3135: @example
3136: (define_insn "jump"
3137: [(set (pc)
3138: (label_ref (match_operand 0 "" "")))]
3139: ""
3140: "*
3141: @{
3142: return (get_attr_length (insn) == 4
3143: ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
3144: @}"
3145: [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
3146: (const_int 4)
3147: (const_int 6)))])
3148: @end example
3149:
1.1.1.2 root 3150: @node Constant Attributes, Delay Slots, Insn Lengths, Insn Attributes
3151: @subsection Constant Attributes
3152: @cindex constant attributes
3153:
1.1.1.3 root 3154: A special form of @code{define_attr}, where the expression for the
3155: default value is a @code{const} expression, indicates an attribute that
3156: is constant for a given run of the compiler. Constant attributes may be
3157: used to specify which variety of processor is used. For example,
1.1.1.2 root 3158:
3159: @example
3160: (define_attr "cpu" "m88100,m88110,m88000"
3161: (const
3162: (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
1.1.1.4 ! root 3163: (symbol_ref "TARGET_88110") (const_string "m88110")]
! 3164: (const_string "m88000"))))
1.1.1.2 root 3165:
3166: (define_attr "memory" "fast,slow"
3167: (const
3168: (if_then_else (symbol_ref "TARGET_FAST_MEM")
1.1.1.4 ! root 3169: (const_string "fast")
! 3170: (const_string "slow"))))
1.1.1.2 root 3171: @end example
3172:
3173: The routine generated for constant attributes has no parameters as it
1.1.1.3 root 3174: does not depend on any particular insn. RTL expressions used to define
3175: the value of a constant attribute may use the @code{symbol_ref} form,
3176: but may not use either the @code{match_operand} form or @code{eq_attr}
3177: forms involving insn attributes.
1.1.1.2 root 3178:
3179: @node Delay Slots, Function Units, Constant Attributes, Insn Attributes
1.1 root 3180: @subsection Delay Slot Scheduling
3181: @cindex delay slots, defining
3182:
3183: The insn attribute mechanism can be used to specify the requirements for
3184: delay slots, if any, on a target machine. An instruction is said to
3185: require a @dfn{delay slot} if some instructions that are physically
3186: after the instruction are executed as if they were located before it.
3187: Classic examples are branch and call instructions, which often execute
3188: the following instruction before the branch or call is performed.
3189:
3190: On some machines, conditional branch instructions can optionally
3191: @dfn{annul} instructions in the delay slot. This means that the
3192: instruction will not be executed for certain branch outcomes. Both
3193: instructions that annul if the branch is true and instructions that
3194: annul if the branch is false are supported.
3195:
3196: Delay slot scheduling differs from instruction scheduling in that
3197: determining whether an instruction needs a delay slot is dependent only
3198: on the type of instruction being generated, not on data flow between the
3199: instructions. See the next section for a discussion of data-dependent
3200: instruction scheduling.
3201:
3202: @findex define_delay
3203: The requirement of an insn needing one or more delay slots is indicated
3204: via the @code{define_delay} expression. It has the following form:
3205:
3206: @example
3207: (define_delay @var{test}
3208: [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
3209: @var{delay-2} @var{annul-true-2} @var{annul-false-2}
3210: @dots{}])
3211: @end example
3212:
3213: @var{test} is an attribute test that indicates whether this
3214: @code{define_delay} applies to a particular insn. If so, the number of
3215: required delay slots is determined by the length of the vector specified
3216: as the second argument. An insn placed in delay slot @var{n} must
3217: satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
3218: attribute test that specifies which insns may be annulled if the branch
3219: is true. Similarly, @var{annul-false-n} specifies which insns in the
3220: delay slot may be annulled if the branch is false. If annulling is not
3221: supported for that delay slot, @code{(nil)} should be coded.@refill
3222:
3223: For example, in the common case where branch and call insns require
3224: a single delay slot, which may contain any insn other than a branch or
3225: call, the following would be placed in the @file{md} file:
3226:
3227: @example
3228: (define_delay (eq_attr "type" "branch,call")
3229: [(eq_attr "type" "!branch,call") (nil) (nil)])
3230: @end example
3231:
3232: Multiple @code{define_delay} expressions may be specified. In this
3233: case, each such expression specifies different delay slot requirements
3234: and there must be no insn for which tests in two @code{define_delay}
3235: expressions are both true.
3236:
3237: For example, if we have a machine that requires one delay slot for branches
3238: but two for calls, no delay slot can contain a branch or call insn,
3239: and any valid insn in the delay slot for the branch can be annulled if the
3240: branch is true, we might represent this as follows:
3241:
3242: @example
3243: (define_delay (eq_attr "type" "branch")
3244: [(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)])
3245:
3246: (define_delay (eq_attr "type" "call")
3247: [(eq_attr "type" "!branch,call") (nil) (nil)
3248: (eq_attr "type" "!branch,call") (nil) (nil)])
3249: @end example
3250:
3251: @node Function Units,, Delay Slots, Insn Attributes
3252: @subsection Specifying Function Units
3253: @cindex function units, for scheduling
3254:
3255: On most RISC machines, there are instructions whose results are not
3256: available for a specific number of cycles. Common cases are instructions
3257: that load data from memory. On many machines, a pipeline stall will result
3258: if the data is referenced too soon after the load instruction.
3259:
3260: In addition, many newer microprocessors have multiple function units, usually
3261: one for integer and one for floating point, and often will incur pipeline
3262: stalls when a result that is needed is not yet ready.
3263:
3264: The descriptions in this section allow the specification of how much
3265: time must elapse between the execution of an instruction and the time
3266: when its result is used. It also allows specification of when the
3267: execution of an instruction will delay execution of similar instructions
3268: due to function unit conflicts.
3269:
3270: For the purposes of the specifications in this section, a machine is
3271: divided into @dfn{function units}, each of which execute a specific
1.1.1.4 ! root 3272: class of instructions in first-in-first-out order. Function units that
! 3273: accept one instruction each cycle and allow a result to be used in the
! 3274: succeeding instruction (usually via forwarding) need not be specified.
! 3275: Classic RISC microprocessors will normally have a single function unit,
! 3276: which we can call @samp{memory}. The newer ``superscalar'' processors
! 3277: will often have function units for floating point operations, usually at
! 3278: least a floating point adder and multiplier.
1.1 root 3279:
3280: @findex define_function_unit
3281: Each usage of a function units by a class of insns is specified with a
3282: @code{define_function_unit} expression, which looks like this:
3283:
3284: @example
3285: (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
1.1.1.4 ! root 3286: @var{test} @var{ready-delay} @var{issue-delay}
! 3287: [@var{conflict-list}])
1.1 root 3288: @end example
3289:
3290: @var{name} is a string giving the name of the function unit.
3291:
3292: @var{multiplicity} is an integer specifying the number of identical
3293: units in the processor. If more than one unit is specified, they will
3294: be scheduled independently. Only truly independent units should be
3295: counted; a pipelined unit should be specified as a single unit. (The
3296: only common example of a machine that has multiple function units for a
3297: single instruction class that are truly independent and not pipelined
3298: are the two multiply and two increment units of the CDC 6600.)
3299:
3300: @var{simultaneity} specifies the maximum number of insns that can be
3301: executing in each instance of the function unit simultaneously or zero
3302: if the unit is pipelined and has no limit.
3303:
3304: All @code{define_function_unit} definitions referring to function unit
3305: @var{name} must have the same name and values for @var{multiplicity} and
3306: @var{simultaneity}.
3307:
3308: @var{test} is an attribute test that selects the insns we are describing
3309: in this definition. Note that an insn may use more than one function
3310: unit and a function unit may be specified in more than one
3311: @code{define_function_unit}.
3312:
3313: @var{ready-delay} is an integer that specifies the number of cycles
3314: after which the result of the instruction can be used without
3315: introducing any stalls.
3316:
1.1.1.4 ! root 3317: @var{issue-delay} is an integer that specifies the number of cycles
! 3318: after the instruction matching the @var{test} expression begins using
! 3319: this unit until a subsequent instruction can begin. A cost of @var{N}
! 3320: indicates an @var{N-1} cycle delay. A subsequent instruction may also
! 3321: be delayed if an earlier instruction has a longer @var{ready-delay}
! 3322: value. This blocking effect is computed using the @var{simultaneity},
! 3323: @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
! 3324: For a normal non-pipelined function unit, @var{simultaneity} is one, the
! 3325: unit is taken to block for the @var{ready-delay} cycles of the executing
! 3326: insn, and smaller values of @var{issue-delay} are ignored.
1.1 root 3327:
3328: @var{conflict-list} is an optional list giving detailed conflict costs
3329: for this unit. If specified, it is a list of condition test expressions
1.1.1.4 ! root 3330: to be applied to insns chosen to execute in @var{name} following the
! 3331: particular insn matching @var{test} that is already executing in
! 3332: @var{name}. For each insn in the list, @var{issue-delay} specifies the
! 3333: conflict cost; for insns not in the list, the cost is zero. If not
! 3334: specified, @var{conflict-list} defaults to all instructions that use the
! 3335: function unit.
1.1 root 3336:
3337: Typical uses of this vector are where a floating point function unit can
3338: pipeline either single- or double-precision operations, but not both, or
3339: where a memory unit can pipeline loads, but not stores, etc.
3340:
3341: As an example, consider a classic RISC machine where the result of a
3342: load instruction is not available for two cycles (a single ``delay''
3343: instruction is required) and where only one load instruction can be executed
3344: simultaneously. This would be specified as:
3345:
3346: @example
1.1.1.4 ! root 3347: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
1.1 root 3348: @end example
3349:
3350: For the case of a floating point function unit that can pipeline either
3351: single or double precision, but not both, the following could be specified:
3352:
3353: @example
3354: (define_function_unit
1.1.1.4 ! root 3355: "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
1.1 root 3356: (define_function_unit
1.1.1.4 ! root 3357: "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
1.1 root 3358: @end example
3359:
1.1.1.4 ! root 3360: @strong{Note:} The scheduler attempts to avoid function unit conflicts
! 3361: and uses all the specifications in the @code{define_function_unit}
! 3362: expression. It has recently come to our attention that these
! 3363: specifications may not allow modeling of some of the newer
! 3364: ``superscalar'' processors that have insns using multiple pipelined
! 3365: units. These insns will cause a potential conflict for the second unit
! 3366: used during their execution and there is no way of representing that
! 3367: conflict. We welcome any examples of how function unit conflicts work
! 3368: in such processors and suggestions for their representation.
1.1 root 3369: @end ifset
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