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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
48: { cc_status.flags |= CC_REVERSED; return \"cmpqd %$0,%0\"; }")
49:
50: (define_insn "tsthi"
51: [(set (cc0)
52: (match_operand:HI 0 "general_operand" "g"))]
53: ""
54: "*
55: { cc_status.flags |= CC_REVERSED; return \"cmpqw %$0,%0\"; }")
56:
57: (define_insn "tstqi"
58: [(set (cc0)
59: (match_operand:QI 0 "general_operand" "g"))]
60: ""
61: "*
62: { cc_status.flags |= CC_REVERSED; return \"cmpqb %$0,%0\"; }")
63:
64: (define_insn "tstdf"
65: [(set (cc0)
66: (match_operand:DF 0 "general_operand" "fmF"))]
67: "TARGET_32081"
68: "*
69: { cc_status.flags |= CC_REVERSED; return \"cmpl %$0d0.0,%0\"; }")
70:
71: (define_insn "tstsf"
72: [(set (cc0)
73: (match_operand:SF 0 "general_operand" "fmF"))]
74: "TARGET_32081"
75: "*
76: { cc_status.flags |= CC_REVERSED; return \"cmpf %$0f0.0,%0\"; }")
77:
78: (define_insn "cmpdf"
79: [(set (cc0)
80: (minus (match_operand:DF 0 "general_operand" "fmF")
81: (match_operand:DF 1 "general_operand" "fmF")))]
82: "TARGET_32081"
83: "cmpl %0,%1")
84:
85: (define_insn "cmpsf"
86: [(set (cc0)
87: (minus (match_operand:SF 0 "general_operand" "fmF")
88: (match_operand:SF 1 "general_operand" "fmF")))]
89: "TARGET_32081"
90: "cmpf %0,%1")
91:
92: (define_insn "cmpsi"
93: [(set (cc0)
94: (minus (match_operand:SI 0 "general_operand" "rmn")
95: (match_operand:SI 1 "general_operand" "rmn")))]
96: ""
97: "*
98: {
99: if (GET_CODE (operands[1]) == CONST_INT)
100: {
101: int i = INTVAL (operands[1]);
102: if (i <= 7 && i >= -8)
103: {
104: cc_status.flags |= CC_REVERSED;
105: return \"cmpqd %1,%0\";
106: }
107: }
108: cc_status.flags &= ~CC_REVERSED;
109: if (GET_CODE (operands[0]) == CONST_INT)
110: {
111: int i = INTVAL (operands[0]);
112: if (i <= 7 && i >= -8)
113: return \"cmpqd %0,%1\";
114: }
115: return \"cmpd %0,%1\";
116: }")
117:
118: (define_insn "cmphi"
119: [(set (cc0)
120: (minus (match_operand:HI 0 "general_operand" "g")
121: (match_operand:HI 1 "general_operand" "g")))]
122: ""
123: "*
124: {
125: if (GET_CODE (operands[1]) == CONST_INT)
126: {
127: short i = INTVAL (operands[1]);
128: if (i <= 7 && i >= -8)
129: {
130: cc_status.flags |= CC_REVERSED;
131: if (INTVAL (operands[1]) > 7)
132: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
133: return \"cmpqw %1,%0\";
134: }
135: }
136: cc_status.flags &= ~CC_REVERSED;
137: if (GET_CODE (operands[0]) == CONST_INT)
138: {
139: short i = INTVAL (operands[0]);
140: if (i <= 7 && i >= -8)
141: {
142: if (INTVAL (operands[0]) > 7)
143: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
144: return \"cmpqw %0,%1\";
145: }
146: }
147: return \"cmpw %0,%1\";
148: }")
149:
150: (define_insn "cmpqi"
151: [(set (cc0)
152: (minus (match_operand:QI 0 "general_operand" "g")
153: (match_operand:QI 1 "general_operand" "g")))]
154: ""
155: "*
156: {
157: if (GET_CODE (operands[1]) == CONST_INT)
158: {
159: char i = INTVAL (operands[1]);
160: if (i <= 7 && i >= -8)
161: {
162: cc_status.flags |= CC_REVERSED;
163: if (INTVAL (operands[1]) > 7)
164: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
165: return \"cmpqb %1,%0\";
166: }
167: }
168: cc_status.flags &= ~CC_REVERSED;
169: if (GET_CODE (operands[0]) == CONST_INT)
170: {
171: char i = INTVAL (operands[0]);
172: if (i <= 7 && i >= -8)
173: {
174: if (INTVAL (operands[0]) > 7)
175: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
176: return \"cmpqb %0,%1\";
177: }
178: }
179: return \"cmpb %0,%1\";
180: }")
181:
182: (define_insn "movdf"
183: [(set (match_operand:DF 0 "general_operand" "=fg<")
184: (match_operand:DF 1 "general_operand" "fFg"))]
185: ""
186: "*
187: {
188: if (FP_REG_P (operands[0]))
189: {
190: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
191: return \"movl %1,%0\";
192: if (REG_P (operands[1]))
193: {
194: rtx xoperands[2];
195: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
196: output_asm_insn (\"movd %1,tos\", xoperands);
197: output_asm_insn (\"movd %1,tos\", operands);
198: return \"movl tos,%0\";
199: }
200: return \"movl %1,%0\";
201: }
202: else if (FP_REG_P (operands[1]))
203: {
204: if (REG_P (operands[0]))
205: {
206: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
207: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
208: return \"movd tos,%0\";
209: }
210: else
211: return \"movl %1,%0\";
212: }
213: return output_move_double (operands);
214: }")
215:
216: (define_insn "movsf"
217: [(set (match_operand:SF 0 "general_operand" "=fg<")
218: (match_operand:SF 1 "general_operand" "fFg"))]
219: ""
220: "*
221: {
222: if (FP_REG_P (operands[0]))
223: {
224: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
225: return \"movd %1,tos\;movf tos,%0\";
226: else
227: return \"movf %1,%0\";
228: }
229: else if (FP_REG_P (operands[1]))
230: {
231: if (REG_P (operands[0]))
232: return \"movf %1,tos\;movd tos,%0\";
233: return \"movf %1,%0\";
234: }
235: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
236: {
237: /* Is there a better machine-independent way to to this? */
238: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
239: return \"movd %1,%0\";
240: }
241: else return \"movd %1,%0\";
242: }")
243:
244: (define_insn ""
245: [(set (match_operand:TI 0 "memory_operand" "=m")
246: (match_operand:TI 1 "memory_operand" "m"))]
247: ""
248: "movmd %1,%0,4")
249:
250: (define_insn "movdi"
251: [(set (match_operand:DI 0 "general_operand" "=g<")
252: (match_operand:DI 1 "general_operand" "g"))]
253: ""
254: "* return output_move_double (operands); ")
255:
256: (define_insn "movsi"
257: [(set (match_operand:SI 0 "general_operand" "=g<")
258: (match_operand:SI 1 "general_operand" "gx"))]
259: ""
260: "*
261: { if (GET_CODE (operands[1]) == CONST_INT)
262: {
263: int i = INTVAL (operands[1]);
264: if (i <= 7 && i >= -8)
265: return \"movqd %1,%0\";
266: if (i < 0x4000 && i >= -0x4000)
267: return \"addr @%1,%0\";
268: return \"movd %1,%0\";
269: }
270: else if (GET_CODE (operands[1]) == REG)
271: if (REGNO (operands[1]) < 16)
272: return \"movd %1,%0\";
273: else if (REGNO (operands[1]) == 16)
274: return \"addr 0(fp),%0\";
275: else return \"addr tos,%0\";
276: else if (GET_CODE (operands[1]) == MEM)
277: return \"movd %1,%0\";
278: return \"addr %a1,%0\";
279: }")
280:
281: (define_insn "movhi"
282: [(set (match_operand:HI 0 "general_operand" "=g<")
283: (match_operand:HI 1 "general_operand" "g"))]
284: ""
285: "*
286: {
287: if (GET_CODE (operands[1]) == CONST_INT)
288: {
289: short i = INTVAL (operands[1]);
290: if (i <= 7 && i >= -8)
291: {
292: if (INTVAL (operands[1]) > 7)
293: operands[1] =
294: gen_rtx (CONST_INT, VOIDmode, i);
295: return \"movqw %1,%0\";
296: }
297: }
298: return \"movw %1,%0\";
299: }")
300:
301: (define_insn "movstricthi"
302: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
303: (match_operand:HI 1 "general_operand" "g"))]
304: ""
305: "*
306: {
307: if (GET_CODE (operands[1]) == CONST_INT
308: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
309: return \"movqw %1,%0\";
310: return \"movw %1,%0\";
311: }")
312:
313: (define_insn "movqi"
314: [(set (match_operand:QI 0 "general_operand" "=g<")
315: (match_operand:QI 1 "general_operand" "g"))]
316: ""
317: "*
318: { if (GET_CODE (operands[1]) == CONST_INT)
319: {
320: char char_val = (char)INTVAL (operands[1]);
321: if (char_val <= 7 && char_val >= -8)
322: {
323: if (INTVAL (operands[1]) > 7)
324: operands[1] =
325: gen_rtx (CONST_INT, VOIDmode, char_val);
326: return \"movqb %1,%0\";
327: }
328: }
329: return \"movb %1,%0\";
330: }")
331:
332: (define_insn "movstrictqi"
333: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
334: (match_operand:QI 1 "general_operand" "g"))]
335: ""
336: "*
337: {
338: if (GET_CODE (operands[1]) == CONST_INT
339: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
340: return \"movqb %1,%0\";
341: return \"movb %1,%0\";
342: }")
343:
344: (define_insn ""
345: [(set (reg:SI 17)
346: (match_operand:SI 0 "general_operand" "g"))]
347: ""
348: "lprd sp,%0")
349:
350: ;; The definition of this insn does not really explain what it does,
351: ;; but it should suffice
352: ;; that anything generated as this insn will be recognized as one
353: ;; and that it won't successfully combine with anything.
354: (define_insn "movstrsi"
355: [(set (match_operand:BLK 0 "general_operand" "=g")
356: (match_operand:BLK 1 "general_operand" "g"))
357: (use (match_operand:SI 2 "general_operand" "rmn"))
358: (clobber (reg:SI 0))
359: (clobber (reg:SI 1))
360: (clobber (reg:SI 2))]
361: ""
362: "*
363: {
364: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
365: abort ();
366: operands[0] = XEXP (operands[0], 0);
367: operands[1] = XEXP (operands[1], 0);
368: if (GET_CODE (operands[0]) == MEM)
369: if (GET_CODE (operands[1]) == MEM)
370: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
371: else
372: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
373: else if (GET_CODE (operands[1]) == MEM)
374: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
375: else
376: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
377:
378: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
379: {
380: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
381: if ((unsigned) INTVAL (operands[2]) <= 7)
382: return \"movqd %2,r0\;movsd\";
383: else
384: return \"movd %2,r0\;movsd\";
385: }
386: else
387: {
388: return \"movd %2,r0\;movsb\";
389: }
390: }")
391:
392: ;; Extension and truncation insns.
393: ;; Those for integer source operand
394: ;; are ordered widest source type first.
395:
396: (define_insn "truncsiqi2"
397: [(set (match_operand:QI 0 "general_operand" "=g<")
398: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
399: ""
400: "movb %1,%0")
401:
402: (define_insn "truncsihi2"
403: [(set (match_operand:HI 0 "general_operand" "=g<")
404: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
405: ""
406: "movw %1,%0")
407:
408: (define_insn "trunchiqi2"
409: [(set (match_operand:QI 0 "general_operand" "=g<")
410: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
411: ""
412: "movb %1,%0")
413:
414: (define_insn "extendhisi2"
415: [(set (match_operand:SI 0 "general_operand" "=g<")
416: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
417: ""
418: "movxwd %1,%0")
419:
420: (define_insn "extendqihi2"
421: [(set (match_operand:HI 0 "general_operand" "=g<")
422: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
423: ""
424: "movxbw %1,%0")
425:
426: (define_insn "extendqisi2"
427: [(set (match_operand:SI 0 "general_operand" "=g<")
428: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
429: ""
430: "movxbd %1,%0")
431:
432: (define_insn "extendsfdf2"
433: [(set (match_operand:DF 0 "general_operand" "=fm<")
434: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
435: "TARGET_32081"
436: "movfl %1,%0")
437:
438: (define_insn "truncdfsf2"
439: [(set (match_operand:SF 0 "general_operand" "=fm<")
440: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
441: "TARGET_32081"
442: "movlf %1,%0")
443:
444: (define_insn "zero_extendhisi2"
445: [(set (match_operand:SI 0 "general_operand" "=g<")
446: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
447: ""
448: "movzwd %1,%0")
449:
450: (define_insn "zero_extendqihi2"
451: [(set (match_operand:HI 0 "general_operand" "=g<")
452: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
453: ""
454: "movzbw %1,%0")
455:
456: (define_insn "zero_extendqisi2"
457: [(set (match_operand:SI 0 "general_operand" "=g<")
458: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
459: ""
460: "movzbd %1,%0")
461:
462: ;; Fix-to-float conversion insns.
463: ;; Note that the ones that start with SImode come first.
464: ;; That is so that an operand that is a CONST_INT
465: ;; (and therefore lacks a specific machine mode).
466: ;; will be recognized as SImode (which is always valid)
467: ;; rather than as QImode or HImode.
468:
469: ;; Rumor has it that the National part does not correctly convert
470: ;; constant ints to floats. This conversion is therefore disabled.
471: ;; A register must be used to perform the conversion.
472:
473: (define_insn "floatsisf2"
474: [(set (match_operand:SF 0 "general_operand" "=fm<")
475: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
476: "TARGET_32081"
477: "movdf %1,%0")
478:
479: (define_insn "floatsidf2"
480: [(set (match_operand:DF 0 "general_operand" "=fm<")
481: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
482: "TARGET_32081"
483: "movdl %1,%0")
484:
485: (define_insn "floathisf2"
486: [(set (match_operand:SF 0 "general_operand" "=fm<")
487: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
488: "TARGET_32081"
489: "movwf %1,%0")
490:
491: (define_insn "floathidf2"
492: [(set (match_operand:DF 0 "general_operand" "=fm<")
493: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
494: "TARGET_32081"
495: "movwl %1,%0")
496:
497: (define_insn "floatqisf2"
498: [(set (match_operand:SF 0 "general_operand" "=fm<")
499: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
500: "TARGET_32081"
501: "movbf %1,%0")
502:
503: (define_insn "floatqidf2"
504: [(set (match_operand:DF 0 "general_operand" "=fm<")
505: (float:DF (match_operand:QI 1 "general_operand" "rm")))]
506: "TARGET_32081"
507: "movbl %1,%0")
508:
509: ;; Float-to-fix conversion insns.
510: ;; The sequent compiler always generates "trunc" insns.
511:
512: (define_insn "fixsfqi2"
513: [(set (match_operand:QI 0 "general_operand" "=g<")
514: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
515: "TARGET_32081"
516: "truncfb %1,%0")
517:
518: (define_insn "fixsfhi2"
519: [(set (match_operand:HI 0 "general_operand" "=g<")
520: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
521: "TARGET_32081"
522: "truncfw %1,%0")
523:
524: (define_insn "fixsfsi2"
525: [(set (match_operand:SI 0 "general_operand" "=g<")
526: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
527: "TARGET_32081"
528: "truncfd %1,%0")
529:
530: (define_insn "fixdfqi2"
531: [(set (match_operand:QI 0 "general_operand" "=g<")
532: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
533: "TARGET_32081"
534: "trunclb %1,%0")
535:
536: (define_insn "fixdfhi2"
537: [(set (match_operand:HI 0 "general_operand" "=g<")
538: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
539: "TARGET_32081"
540: "trunclw %1,%0")
541:
542: (define_insn "fixdfsi2"
543: [(set (match_operand:SI 0 "general_operand" "=g<")
544: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
545: "TARGET_32081"
546: "truncld %1,%0")
547:
548: ;; Unsigned
549:
550: (define_insn "fixunssfqi2"
551: [(set (match_operand:QI 0 "general_operand" "=g<")
552: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
553: "TARGET_32081"
554: "truncfb %1,%0")
555:
556: (define_insn "fixunssfhi2"
557: [(set (match_operand:HI 0 "general_operand" "=g<")
558: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
559: "TARGET_32081"
560: "truncfw %1,%0")
561:
562: (define_insn "fixunssfsi2"
563: [(set (match_operand:SI 0 "general_operand" "=g<")
564: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
565: "TARGET_32081"
566: "truncfd %1,%0")
567:
568: (define_insn "fixunsdfqi2"
569: [(set (match_operand:QI 0 "general_operand" "=g<")
570: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
571: "TARGET_32081"
572: "trunclb %1,%0")
573:
574: (define_insn "fixunsdfhi2"
575: [(set (match_operand:HI 0 "general_operand" "=g<")
576: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
577: "TARGET_32081"
578: "trunclw %1,%0")
579:
580: (define_insn "fixunsdfsi2"
581: [(set (match_operand:SI 0 "general_operand" "=g<")
582: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
583: "TARGET_32081"
584: "truncld %1,%0")
585:
586: ;;; These are not yet used by GCC
587: (define_insn "fix_truncsfqi2"
588: [(set (match_operand:QI 0 "general_operand" "=g<")
589: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
590: "TARGET_32081"
591: "truncfb %1,%0")
592:
593: (define_insn "fix_truncsfhi2"
594: [(set (match_operand:HI 0 "general_operand" "=g<")
595: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
596: "TARGET_32081"
597: "truncfw %1,%0")
598:
599: (define_insn "fix_truncsfsi2"
600: [(set (match_operand:SI 0 "general_operand" "=g<")
601: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
602: "TARGET_32081"
603: "truncfd %1,%0")
604:
605: (define_insn "fix_truncdfqi2"
606: [(set (match_operand:QI 0 "general_operand" "=g<")
607: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
608: "TARGET_32081"
609: "trunclb %1,%0")
610:
611: (define_insn "fix_truncdfhi2"
612: [(set (match_operand:HI 0 "general_operand" "=g<")
613: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
614: "TARGET_32081"
615: "trunclw %1,%0")
616:
617: (define_insn "fix_truncdfsi2"
618: [(set (match_operand:SI 0 "general_operand" "=g<")
619: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
620: "TARGET_32081"
621: "truncld %1,%0")
622:
623: ;;- All kinds of add instructions.
624:
625: (define_insn "adddf3"
626: [(set (match_operand:DF 0 "general_operand" "=fm")
627: (plus:DF (match_operand:DF 1 "general_operand" "%0")
628: (match_operand:DF 2 "general_operand" "fmF")))]
629: "TARGET_32081"
630: "addl %2,%0")
631:
632:
633: (define_insn "addsf3"
634: [(set (match_operand:SF 0 "general_operand" "=fm")
635: (plus:SF (match_operand:SF 1 "general_operand" "%0")
636: (match_operand:SF 2 "general_operand" "fmF")))]
637: "TARGET_32081"
638: "addf %2,%0")
639:
640: (define_insn ""
641: [(set (reg:SI 17)
642: (plus:SI (reg:SI 17)
643: (match_operand:SI 0 "immediate_operand" "i")))]
644: "GET_CODE (operands[0]) == CONST_INT"
645: "*
646: {
647: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
648: return \"adjspb %$%n0\";
649: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
650: return \"adjspw %$%n0\";
651: return \"adjspd %$%n0\";
652: }")
653:
654: (define_insn ""
655: [(set (match_operand:SI 0 "general_operand" "=g<")
656: (plus:SI (reg:SI 16)
657: (match_operand:SI 1 "immediate_operand" "i")))]
658: "GET_CODE (operands[1]) == CONST_INT"
659: "addr %1(fp),%0")
660:
661: (define_insn ""
662: [(set (match_operand:SI 0 "general_operand" "=g<")
663: (plus:SI (reg:SI 17)
664: (match_operand:SI 1 "immediate_operand" "i")))]
665: "GET_CODE (operands[1]) == CONST_INT"
666: "addr %1(sp),%0")
667:
668: (define_insn "addsi3"
669: [(set (match_operand:SI 0 "general_operand" "=g")
670: (plus:SI (match_operand:SI 1 "general_operand" "%0")
671: (match_operand:SI 2 "general_operand" "rmn")))]
672: ""
673: "*
674: {
675: if (GET_CODE (operands[2]) == CONST_INT)
676: {
677: int i = INTVAL (operands[2]);
678:
679: if (i <= 7 && i >= -8)
680: return \"addqd %2,%0\";
681: else if (GET_CODE (operands[0]) == REG
682: && i < 0x4000 && i >= -0x4000)
683: return \"addr %2(%0),%0\";
684: }
685: return \"addd %2,%0\";
686: }")
687:
688: (define_insn "addhi3"
689: [(set (match_operand:HI 0 "general_operand" "=g")
690: (plus:HI (match_operand:HI 1 "general_operand" "%0")
691: (match_operand:HI 2 "general_operand" "g")))]
692: ""
693: "*
694: { if (GET_CODE (operands[2]) == CONST_INT)
695: {
696: int i = INTVAL (operands[2]);
697: if (i <= 7 && i >= -8)
698: return \"addqw %2,%0\";
699: }
700: return \"addw %2,%0\";
701: }")
702:
703: (define_insn ""
704: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
705: (plus:HI (match_operand:HI 1 "general_operand" "0")
706: (match_operand:HI 2 "general_operand" "g")))]
707: ""
708: "*
709: {
710: if (GET_CODE (operands[1]) == CONST_INT
711: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
712: return \"addqw %1,%0\";
713: return \"addw %1,%0\";
714: }")
715:
716: (define_insn "addqi3"
717: [(set (match_operand:QI 0 "general_operand" "=g")
718: (plus:QI (match_operand:QI 1 "general_operand" "%0")
719: (match_operand:QI 2 "general_operand" "g")))]
720: ""
721: "*
722: { if (GET_CODE (operands[2]) == CONST_INT)
723: {
724: int i = INTVAL (operands[2]);
725: if (i <= 7 && i >= -8)
726: return \"addqb %2,%0\";
727: }
728: return \"addb %2,%0\";
729: }")
730:
731: (define_insn ""
732: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
733: (plus:QI (match_operand:QI 1 "general_operand" "0")
734: (match_operand:QI 2 "general_operand" "g")))]
735: ""
736: "*
737: {
738: if (GET_CODE (operands[1]) == CONST_INT
739: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
740: return \"addqb %1,%0\";
741: return \"addb %1,%0\";
742: }")
743:
744: ;;- All kinds of subtract instructions.
745:
746: (define_insn "subdf3"
747: [(set (match_operand:DF 0 "general_operand" "=fm")
748: (minus:DF (match_operand:DF 1 "general_operand" "0")
749: (match_operand:DF 2 "general_operand" "fmF")))]
750: "TARGET_32081"
751: "subl %2,%0")
752:
753: (define_insn "subsf3"
754: [(set (match_operand:SF 0 "general_operand" "=fm")
755: (minus:SF (match_operand:SF 1 "general_operand" "0")
756: (match_operand:SF 2 "general_operand" "fmF")))]
757: "TARGET_32081"
758: "subf %2,%0")
759:
760: (define_insn ""
761: [(set (reg:SI 17)
762: (minus:SI (reg:SI 17)
763: (match_operand:SI 0 "immediate_operand" "i")))]
764: "GET_CODE (operands[0]) == CONST_INT"
765: "*
766: {
767: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
768: && INTVAL(operands[0]) > -64)
769: return \"adjspb %0\";
770: return \"adjspd %0\";
771: }")
772:
773: (define_insn "subsi3"
774: [(set (match_operand:SI 0 "general_operand" "=g")
775: (minus:SI (match_operand:SI 1 "general_operand" "0")
776: (match_operand:SI 2 "general_operand" "rmn")))]
777: ""
778: "*
779: { if (GET_CODE (operands[2]) == CONST_INT)
780: {
781: int i = INTVAL (operands[2]);
782:
783: if (i <= 8 && i >= -7)
784: return \"addqd %$%n2,%0\";
785: }
786: return \"subd %2,%0\";
787: }")
788:
789: (define_insn "subhi3"
790: [(set (match_operand:HI 0 "general_operand" "=g")
791: (minus:HI (match_operand:HI 1 "general_operand" "0")
792: (match_operand:HI 2 "general_operand" "g")))]
793: ""
794: "*
795: { if (GET_CODE (operands[2]) == CONST_INT)
796: {
797: int i = INTVAL (operands[2]);
798:
799: if (i <= 8 && i >= -7)
800: return \"addqw %$%n2,%0\";
801: }
802: return \"subw %2,%0\";
803: }")
804:
805: (define_insn ""
806: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
807: (minus:HI (match_operand:HI 1 "general_operand" "0")
808: (match_operand:HI 2 "general_operand" "g")))]
809: ""
810: "*
811: {
812: if (GET_CODE (operands[1]) == CONST_INT
813: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
814: return \"addqw %$%n1,%0\";
815: return \"subw %1,%0\";
816: }")
817:
818: (define_insn "subqi3"
819: [(set (match_operand:QI 0 "general_operand" "=g")
820: (minus:QI (match_operand:QI 1 "general_operand" "0")
821: (match_operand:QI 2 "general_operand" "g")))]
822: ""
823: "*
824: { if (GET_CODE (operands[2]) == CONST_INT)
825: {
826: int i = INTVAL (operands[2]);
827:
828: if (i <= 8 && i >= -7)
829: return \"addqb %$%n2,%0\";
830: }
831: return \"subb %2,%0\";
832: }")
833:
834: (define_insn ""
835: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
836: (minus:QI (match_operand:QI 1 "general_operand" "0")
837: (match_operand:QI 2 "general_operand" "g")))]
838: ""
839: "*
840: {
841: if (GET_CODE (operands[1]) == CONST_INT
842: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
843: return \"addqb %$%n1,%0\";
844: return \"subb %1,%0\";
845: }")
846:
847: ;;- Multiply instructions.
848:
849: (define_insn "muldf3"
850: [(set (match_operand:DF 0 "general_operand" "=fm")
851: (mult:DF (match_operand:DF 1 "general_operand" "%0")
852: (match_operand:DF 2 "general_operand" "fmF")))]
853: "TARGET_32081"
854: "mull %2,%0")
855:
856: (define_insn "mulsf3"
857: [(set (match_operand:SF 0 "general_operand" "=fm")
858: (mult:SF (match_operand:SF 1 "general_operand" "%0")
859: (match_operand:SF 2 "general_operand" "fmF")))]
860: "TARGET_32081"
861: "mulf %2,%0")
862:
863: (define_insn "mulsi3"
864: [(set (match_operand:SI 0 "general_operand" "=g")
865: (mult:SI (match_operand:SI 1 "general_operand" "%0")
866: (match_operand:SI 2 "general_operand" "rmn")))]
867: ""
868: "muld %2,%0")
869:
870: (define_insn "mulhi3"
871: [(set (match_operand:HI 0 "general_operand" "=g")
872: (mult:HI (match_operand:HI 1 "general_operand" "%0")
873: (match_operand:HI 2 "general_operand" "g")))]
874: ""
875: "mulw %2,%0")
876:
877: (define_insn "mulqi3"
878: [(set (match_operand:QI 0 "general_operand" "=g")
879: (mult:QI (match_operand:QI 1 "general_operand" "%0")
880: (match_operand:QI 2 "general_operand" "g")))]
881: ""
882: "mulb %2,%0")
883:
884: (define_insn "umulsi3"
885: [(set (match_operand:SI 0 "general_operand" "=g")
886: (umult:SI (match_operand:SI 1 "general_operand" "%0")
887: (match_operand:SI 2 "general_operand" "g")))]
888: ""
889: "muld %2,%0")
890:
891: (define_insn "umulhi3"
892: [(set (match_operand:HI 0 "general_operand" "=g")
893: (umult:HI (match_operand:HI 1 "general_operand" "%0")
894: (match_operand:HI 2 "general_operand" "g")))]
895: ""
896: "mulw %2,%0")
897:
898: (define_insn "umulqi3"
899: [(set (match_operand:QI 0 "general_operand" "=g")
900: (umult:QI (match_operand:QI 1 "general_operand" "%0")
901: (match_operand:QI 2 "general_operand" "g")))]
902: ""
903: "mulb %2,%0")
904:
905: (define_insn "umulsidi3"
906: [(set (match_operand:DI 0 "general_operand" "=g")
907: (umult:DI (match_operand:SI 1 "general_operand" "0")
908: (match_operand:SI 2 "general_operand" "rmn")))]
909: ""
910: "meid %2,%0")
911:
912: ;;- Divide instructions.
913:
914: (define_insn "divdf3"
915: [(set (match_operand:DF 0 "general_operand" "=fm")
916: (div:DF (match_operand:DF 1 "general_operand" "0")
917: (match_operand:DF 2 "general_operand" "fmF")))]
918: "TARGET_32081"
919: "divl %2,%0")
920:
921: (define_insn "divsf3"
922: [(set (match_operand:SF 0 "general_operand" "=fm")
923: (div:SF (match_operand:SF 1 "general_operand" "0")
924: (match_operand:SF 2 "general_operand" "fmF")))]
925: "TARGET_32081"
926: "divf %2,%0")
927:
928: (define_insn "divsi3"
929: [(set (match_operand:SI 0 "general_operand" "=g")
930: (div:SI (match_operand:SI 1 "general_operand" "0")
931: (match_operand:SI 2 "general_operand" "rmn")))]
932: ""
933: "quod %2,%0")
934:
935: (define_insn "divhi3"
936: [(set (match_operand:HI 0 "general_operand" "=g")
937: (div:HI (match_operand:HI 1 "general_operand" "0")
938: (match_operand:HI 2 "general_operand" "g")))]
939: ""
940: "quow %2,%0")
941:
942: (define_insn "divqi3"
943: [(set (match_operand:QI 0 "general_operand" "=g")
944: (div:QI (match_operand:QI 1 "general_operand" "0")
945: (match_operand:QI 2 "general_operand" "g")))]
946: ""
947: "quob %2,%0")
948:
949: (define_insn "udivsi3"
950: [(set (match_operand:SI 0 "register_operand" "=r")
951: (udiv:SI (subreg:SI (match_operand:DI 1 "general_operand" "0") 0)
952: (match_operand:SI 2 "general_operand" "rmn")))]
953: ""
954: "*
955: {
956: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
957: return \"deid %2,%0\;movd %1,%0\";
958: }")
959:
960: (define_insn "udivhi3"
961: [(set (match_operand:HI 0 "register_operand" "=r")
962: (udiv:HI (subreg:HI (match_operand:DI 1 "general_operand" "0") 0)
963: (match_operand:HI 2 "general_operand" "g")))]
964: ""
965: "*
966: {
967: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
968: return \"deiw %2,%0\;movw %1,%0\";
969: }")
970:
971: (define_insn "udivqi3"
972: [(set (match_operand:QI 0 "register_operand" "=r")
973: (udiv:QI (subreg:QI (match_operand:DI 1 "general_operand" "0") 0)
974: (match_operand:QI 2 "general_operand" "g")))]
975: ""
976: "*
977: {
978: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
979: return \"deib %2,%0\;movb %1,%0\";
980: }")
981:
982: ;; Remainder instructions.
983:
984: (define_insn "modsi3"
985: [(set (match_operand:SI 0 "general_operand" "=g")
986: (mod:SI (match_operand:SI 1 "general_operand" "0")
987: (match_operand:SI 2 "general_operand" "rmn")))]
988: ""
989: "remd %2,%0")
990:
991: (define_insn "modhi3"
992: [(set (match_operand:HI 0 "general_operand" "=g")
993: (mod:HI (match_operand:HI 1 "general_operand" "0")
994: (match_operand:HI 2 "general_operand" "g")))]
995: ""
996: "remw %2,%0")
997:
998: (define_insn "modqi3"
999: [(set (match_operand:QI 0 "general_operand" "=g")
1000: (mod:QI (match_operand:QI 1 "general_operand" "0")
1001: (match_operand:QI 2 "general_operand" "g")))]
1002: ""
1003: "remb %2,%0")
1004:
1005: (define_insn "umodsi3"
1006: [(set (match_operand:SI 0 "register_operand" "=r")
1007: (umod:SI (subreg:SI (match_operand:DI 1 "general_operand" "0") 0)
1008: (match_operand:SI 2 "general_operand" "rmn")))]
1009: ""
1010: "deid %2,%0")
1011:
1012: (define_insn "umodhi3"
1013: [(set (match_operand:HI 0 "register_operand" "=r")
1014: (umod:HI (subreg:HI (match_operand:DI 1 "general_operand" "0") 0)
1015: (match_operand:HI 2 "general_operand" "g")))]
1016: ""
1017: "deiw %2,%0")
1018:
1019: (define_insn "umodqi3"
1020: [(set (match_operand:QI 0 "register_operand" "=r")
1021: (umod:QI (subreg:QI (match_operand:DI 1 "general_operand" "0") 0)
1022: (match_operand:QI 2 "general_operand" "g")))]
1023: ""
1024: "deib %2,%0")
1025:
1026: ; This isn't be usable in its current form.
1027: ;(define_insn "udivmoddisi4"
1028: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1029: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1030: ; (match_operand:SI 2 "general_operand" "rmn")))
1031: ; (set (subreg:SI (match_dup 0) 0)
1032: ; (umod:SI (match_dup 1) (match_dup 2)))]
1033: ; ""
1034: ; "deid %2,%0")
1035:
1036: ;;- Logical Instructions: AND
1037:
1038: (define_insn "andsi3"
1039: [(set (match_operand:SI 0 "general_operand" "=g")
1040: (and:SI (match_operand:SI 1 "general_operand" "%0")
1041: (match_operand:SI 2 "general_operand" "rmn")))]
1042: ""
1043: "*
1044: {
1045: if (GET_CODE (operands[2]) == CONST_INT) {
1046: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1047: if (INTVAL (operands[2]) == 0xffffff00)
1048: return \"movqb %$0,%0\";
1049: else {
1050: INTVAL (operands[2]) &= 0xff;
1051: return \"andb %2,%0\";
1052: }
1053: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1054: if (INTVAL (operands[2]) == 0xffff0000)
1055: return \"movqw %$0,%0\";
1056: else {
1057: INTVAL (operands[2]) &= 0xffff;
1058: return \"andw %2,%0\";
1059: }
1060: }
1061: return \"andd %2,%0\";
1062: }")
1063:
1064: (define_insn "andhi3"
1065: [(set (match_operand:HI 0 "general_operand" "=g")
1066: (and:HI (match_operand:HI 1 "general_operand" "%0")
1067: (match_operand:HI 2 "general_operand" "g")))]
1068: ""
1069: "*
1070: {
1071: if (GET_CODE (operands[2]) == CONST_INT
1072: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1073: if (INTVAL (operands[2]) == 0xffffff00)
1074: return \"movqb %$0,%0\";
1075: else {
1076: INTVAL (operands[2]) &= 0xff;
1077: return \"andb %2,%0\";
1078: }
1079: return \"andw %2,%0\";
1080: }")
1081:
1082: (define_insn "andqi3"
1083: [(set (match_operand:QI 0 "general_operand" "=g")
1084: (and:QI (match_operand:QI 1 "general_operand" "%0")
1085: (match_operand:QI 2 "general_operand" "g")))]
1086: ""
1087: "andb %2,%0")
1088:
1089: (define_insn "andcbsi3"
1090: [(set (match_operand:SI 0 "general_operand" "=g")
1091: (and:SI (match_operand:SI 1 "general_operand" "0")
1092: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1093: ""
1094: "*
1095: {
1096: if (GET_CODE (operands[2]) == CONST_INT)
1097: {
1098: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1099: return \"bicb %2,%0\";
1100: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1101: return \"bicw %2,%0\";
1102: }
1103: return \"bicd %2,%0\";
1104: }")
1105:
1106: (define_insn ""
1107: [(set (match_operand:SI 0 "general_operand" "=g")
1108: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1109: (match_operand:SI 2 "general_operand" "0")))]
1110: ""
1111: "*
1112: {
1113: if (GET_CODE (operands[1]) == CONST_INT)
1114: {
1115: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1116: return \"bicb %1,%0\";
1117: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1118: return \"bicw %1,%0\";
1119: }
1120: return \"bicd %1,%0\";
1121: }")
1122:
1123: (define_insn "andcbhi3"
1124: [(set (match_operand:HI 0 "general_operand" "=g")
1125: (and:HI (match_operand:HI 1 "general_operand" "%0")
1126: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1127: ""
1128: "*
1129: {
1130: if (GET_CODE (operands[2]) == CONST_INT
1131: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1132: return \"bicb %2,%0\";
1133: return \"bicw %2,%0\";
1134: }")
1135:
1136: (define_insn ""
1137: [(set (match_operand:HI 0 "general_operand" "=g")
1138: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1139: (match_operand:HI 2 "general_operand" "0")))]
1140: ""
1141: "*
1142: {
1143: if (GET_CODE (operands[1]) == CONST_INT
1144: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1145: return \"bicb %1,%0\";
1146: return \"bicw %1,%0\";
1147: }")
1148:
1149: (define_insn "andcbqi3"
1150: [(set (match_operand:QI 0 "general_operand" "=g")
1151: (and:QI (match_operand:QI 1 "general_operand" "%0")
1152: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1153: ""
1154: "bicb %2,%0")
1155:
1156: (define_insn ""
1157: [(set (match_operand:QI 0 "general_operand" "=g")
1158: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1159: (match_operand:QI 2 "general_operand" "0")))]
1160: ""
1161: "bicb %1,%0")
1162:
1163: ;;- Bit set instructions.
1164:
1165: (define_insn "iorsi3"
1166: [(set (match_operand:SI 0 "general_operand" "=g")
1167: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1168: (match_operand:SI 2 "general_operand" "rmn")))]
1169: ""
1170: "*
1171: {
1172: if (GET_CODE (operands[2]) == CONST_INT) {
1173: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1174: return \"orb %2,%0\";
1175: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1176: return \"orw %2,%0\";
1177: }
1178: return \"ord %2,%0\";
1179: }")
1180:
1181: (define_insn "iorhi3"
1182: [(set (match_operand:HI 0 "general_operand" "=g")
1183: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1184: (match_operand:HI 2 "general_operand" "g")))]
1185: ""
1186: "*
1187: {
1188: if (GET_CODE(operands[2]) == CONST_INT &&
1189: (INTVAL(operands[2]) & 0xffffff00) == 0)
1190: return \"orb %2,%0\";
1191: return \"orw %2,%0\";
1192: }")
1193:
1194: (define_insn "iorqi3"
1195: [(set (match_operand:QI 0 "general_operand" "=g")
1196: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1197: (match_operand:QI 2 "general_operand" "g")))]
1198: ""
1199: "orb %2,%0")
1200:
1201: ;;- xor instructions.
1202:
1203: (define_insn "xorsi3"
1204: [(set (match_operand:SI 0 "general_operand" "=g")
1205: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1206: (match_operand:SI 2 "general_operand" "rmn")))]
1207: ""
1208: "*
1209: {
1210: if (GET_CODE (operands[2]) == CONST_INT) {
1211: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1212: return \"xorb %2,%0\";
1213: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1214: return \"xorw %2,%0\";
1215: }
1216: return \"xord %2,%0\";
1217: }")
1218:
1219: (define_insn "xorhi3"
1220: [(set (match_operand:HI 0 "general_operand" "=g")
1221: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1222: (match_operand:HI 2 "general_operand" "g")))]
1223: ""
1224: "*
1225: {
1226: if (GET_CODE(operands[2]) == CONST_INT &&
1227: (INTVAL(operands[2]) & 0xffffff00) == 0)
1228: return \"xorb %2,%0\";
1229: return \"xorw %2,%0\";
1230: }")
1231:
1232: (define_insn "xorqi3"
1233: [(set (match_operand:QI 0 "general_operand" "=g")
1234: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1235: (match_operand:QI 2 "general_operand" "g")))]
1236: ""
1237: "xorb %2,%0")
1238:
1239: (define_insn "negdf2"
1240: [(set (match_operand:DF 0 "general_operand" "=fm<")
1241: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1242: "TARGET_32081"
1243: "negl %1,%0")
1244:
1245: (define_insn "negsf2"
1246: [(set (match_operand:SF 0 "general_operand" "=fm<")
1247: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1248: "TARGET_32081"
1249: "negf %1,%0")
1250:
1251: (define_insn "negsi2"
1252: [(set (match_operand:SI 0 "general_operand" "=g<")
1253: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1254: ""
1255: "negd %1,%0")
1256:
1257: (define_insn "neghi2"
1258: [(set (match_operand:HI 0 "general_operand" "=g<")
1259: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1260: ""
1261: "negw %1,%0")
1262:
1263: (define_insn "negqi2"
1264: [(set (match_operand:QI 0 "general_operand" "=g<")
1265: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1266: ""
1267: "negb %1,%0")
1268:
1269: (define_insn "one_cmplsi2"
1270: [(set (match_operand:SI 0 "general_operand" "=g<")
1271: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1272: ""
1273: "comd %1,%0")
1274:
1275: (define_insn "one_cmplhi2"
1276: [(set (match_operand:HI 0 "general_operand" "=g<")
1277: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1278: ""
1279: "comw %1,%0")
1280:
1281: (define_insn "one_cmplqi2"
1282: [(set (match_operand:QI 0 "general_operand" "=g<")
1283: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1284: ""
1285: "comb %1,%0")
1286:
1287: ;; arithmetic left and right shift operations
1288:
1289: (define_insn "ashlsi3"
1290: [(set (match_operand:SI 0 "general_operand" "=g,g")
1291: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1292: (match_operand:SI 2 "general_operand" "I,rmn")))]
1293: ""
1294: "*
1295: { if (GET_CODE (operands[2]) == CONST_INT
1296: && INTVAL (operands[2]) > 0
1297: && INTVAL (operands[2]) <= 3)
1298: if (GET_CODE (operands[0]) == REG)
1299: {
1300: if (GET_CODE (operands[1]) == REG)
1301: {
1302: if (REGNO (operands[0]) == REGNO (operands[1]))
1303: {
1304: if (operands[2] == const1_rtx)
1305: return \"addd %0,%0\";
1306: else if (INTVAL (operands[2]) == 2)
1307: return \"addd %0,%0\;addd %0,%0\";
1308: }
1309: operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
1310: return \"addr %a1,%0\";
1311: }
1312: else if (operands[2] == const1_rtx)
1313: return \"movd %1,%0\;addd %0,%0\";
1314: }
1315: else if (GET_CODE (operands[1]) == REG)
1316: {
1317: operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
1318: return \"addr %a1,%0\";
1319: }
1320: else if (INTVAL (operands[2]) == 1
1321: && GET_CODE (operands[1]) == MEM
1322: && rtx_equal_p (operands [0], operands[1]))
1323: {
1324: rtx temp = XEXP (operands[1], 0);
1325:
1326: if (GET_CODE (temp) == REG
1327: || (GET_CODE (temp) == PLUS
1328: && GET_CODE (XEXP (temp, 0)) == REG
1329: && GET_CODE (XEXP (temp, 1)) == CONST_INT))
1330: return \"addd %0,%0\";
1331: }
1332: return \"ashd %2,%0\";
1333: }")
1334:
1335: (define_insn ""
1336: [(set (match_operand:SI 0 "general_operand" "=g")
1337: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1338: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1339: (const_int 31))))]
1340: ""
1341: "ashd %2,%0")
1342:
1343: (define_insn "ashlhi3"
1344: [(set (match_operand:HI 0 "general_operand" "=g")
1345: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1346: (match_operand:SI 2 "general_operand" "rmn")))]
1347: ""
1348: "*
1349: { if (GET_CODE (operands[2]) == CONST_INT)
1350: if (INTVAL (operands[2]) == 1)
1351: return \"addw %1,%0\";
1352: else if (INTVAL (operands[2]) == 2)
1353: return \"addw %1,%0\;addw %0,%0\";
1354: return \"ashw %2,%0\";
1355: }")
1356:
1357: (define_insn "ashlqi3"
1358: [(set (match_operand:QI 0 "general_operand" "=g")
1359: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1360: (match_operand:SI 2 "general_operand" "rmn")))]
1361: ""
1362: "*
1363: { if (GET_CODE (operands[2]) == CONST_INT)
1364: if (INTVAL (operands[2]) == 1)
1365: return \"addb %1,%0\";
1366: else if (INTVAL (operands[2]) == 2)
1367: return \"addb %1,%0\;addb %0,%0\";
1368: return \"ashb %2,%0\";
1369: }")
1370:
1371: ;; logical shift instructions
1372:
1373: (define_insn "lshlsi3"
1374: [(set (match_operand:SI 0 "general_operand" "=g")
1375: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1376: (match_operand:SI 2 "general_operand" "rmn")))]
1377: ""
1378: "lshd %2,%0")
1379:
1380: (define_insn ""
1381: [(set (match_operand:SI 0 "general_operand" "=g")
1382: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1383: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1384: (const_int 31))))]
1385: ""
1386: "lshd %2,%0")
1387:
1388: (define_insn "lshlhi3"
1389: [(set (match_operand:HI 0 "general_operand" "=g")
1390: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1391: (match_operand:SI 2 "general_operand" "rmn")))]
1392: ""
1393: "lshw %2,%0")
1394:
1395: (define_insn "lshlqi3"
1396: [(set (match_operand:QI 0 "general_operand" "=g")
1397: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1398: (match_operand:SI 2 "general_operand" "rmn")))]
1399: ""
1400: "lshb %2,%0")
1401:
1402: ;; Rotate instructions
1403:
1404: (define_insn "rotlsi3"
1405: [(set (match_operand:SI 0 "general_operand" "=g")
1406: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1407: (match_operand:SI 2 "general_operand" "rmn")))]
1408: ""
1409: "rotd %2,%0")
1410:
1411: (define_insn "rotlhi3"
1412: [(set (match_operand:HI 0 "general_operand" "=g")
1413: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1414: (match_operand:SI 2 "general_operand" "rmn")))]
1415: ""
1416: "rotw %2,%0")
1417:
1418: (define_insn "rotlqi3"
1419: [(set (match_operand:QI 0 "general_operand" "=g")
1420: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1421: (match_operand:SI 2 "general_operand" "rmn")))]
1422: ""
1423: "rotb %2,%0")
1424:
1425: ;;- load or push effective address
1426: ;; These come after the move, add, and multiply patterns
1427: ;; because we don't want pushl $1 turned into pushad 1.
1428:
1429: (define_insn ""
1430: [(set (match_operand:SI 0 "general_operand" "=g<")
1431: (match_operand:QI 1 "address_operand" "p"))]
1432: ""
1433: "addr %a1,%0")
1434:
1435: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1436: ;;; but slower then using power-of-2 shifts if we can use them
1437: ;
1438: ;(define_insn ""
1439: ; [(set (match_operand:SI 0 "register_operand" "=r")
1440: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1441: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1442: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1443: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1444: ; "indexd %0,%3,%1")
1445: ;
1446: ;(define_insn ""
1447: ; [(set (match_operand:SI 0 "register_operand" "=r")
1448: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1449: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1450: ; (match_operand:SI 3 "general_operand" "rmn")))]
1451: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1452: ; "indexd %0,%2,%3")
1453:
1454: ;; Set, Clear, and Invert bit
1455:
1456: (define_insn ""
1457: [(set (match_operand:SI 0 "general_operand" "=g")
1458: (ior:SI
1459: (ashift:SI (const_int 1)
1460: (match_operand:SI 1 "general_operand" "rmn"))
1461: (match_dup 0)))]
1462: ""
1463: "sbitd %1,%0")
1464:
1465: (define_insn ""
1466: [(set (match_operand:SI 0 "general_operand" "=g")
1467: (ior:SI
1468: (match_dup 0)
1469: (ashift:SI (const_int 1)
1470: (match_operand:SI 1 "general_operand" "rmn"))))]
1471: ""
1472: "sbitd %1,%0")
1473:
1474: (define_insn ""
1475: [(set (match_operand:QI 0 "general_operand" "=g")
1476: (ior:QI
1477: (subreg:QI
1478: (ashift:SI (const_int 1)
1479: (match_operand:QI 1 "general_operand" "rmn")) 0)
1480: (match_dup 0)))]
1481: ""
1482: "sbitb %1,%0")
1483:
1484: (define_insn ""
1485: [(set (match_operand:QI 0 "general_operand" "=g")
1486: (ior:QI
1487: (match_dup 0)
1488: (subreg:QI
1489: (ashift:SI (const_int 1)
1490: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1491: ""
1492: "sbitb %1,%0")
1493:
1494: (define_insn ""
1495: [(set (match_operand:SI 0 "general_operand" "=g")
1496: (and:SI
1497: (not:SI
1498: (ashift:SI (const_int 1)
1499: (match_operand:SI 1 "general_operand" "rmn")))
1500: (match_dup 0)))]
1501: ""
1502: "cbitd %1,%0")
1503:
1504: (define_insn ""
1505: [(set (match_operand:SI 0 "general_operand" "=g")
1506: (and:SI
1507: (match_dup 0)
1508: (not:SI
1509: (ashift:SI (const_int 1)
1510: (match_operand:SI 1 "general_operand" "rmn")))))]
1511: ""
1512: "cbitd %1,%0")
1513:
1514: (define_insn ""
1515: [(set (match_operand:QI 0 "general_operand" "=g")
1516: (and:QI
1517: (subreg:QI
1518: (not:SI
1519: (ashift:SI (const_int 1)
1520: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1521: (match_dup 0)))]
1522: ""
1523: "cbitb %1,%0")
1524:
1525: (define_insn ""
1526: [(set (match_operand:QI 0 "general_operand" "=g")
1527: (and:QI
1528: (match_dup 0)
1529: (subreg:QI
1530: (not:SI
1531: (ashift:SI (const_int 1)
1532: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1533: ""
1534: "cbitb %1,%0")
1535:
1536: (define_insn ""
1537: [(set (match_operand:SI 0 "general_operand" "=g")
1538: (xor:SI
1539: (ashift:SI (const_int 1)
1540: (match_operand:SI 1 "general_operand" "rmn"))
1541: (match_dup 0)))]
1542: ""
1543: "ibitd %1,%0")
1544:
1545: (define_insn ""
1546: [(set (match_operand:SI 0 "general_operand" "=g")
1547: (xor:SI
1548: (match_dup 0)
1549: (ashift:SI (const_int 1)
1550: (match_operand:SI 1 "general_operand" "rmn"))))]
1551: ""
1552: "ibitd %1,%0")
1553:
1554: (define_insn ""
1555: [(set (match_operand:QI 0 "general_operand" "=g")
1556: (xor:QI
1557: (subreg:QI
1558: (ashift:SI (const_int 1)
1559: (match_operand:QI 1 "general_operand" "rmn")) 0)
1560: (match_dup 0)))]
1561: ""
1562: "ibitb %1,%0")
1563:
1564: (define_insn ""
1565: [(set (match_operand:QI 0 "general_operand" "=g")
1566: (xor:QI
1567: (match_dup 0)
1568: (subreg:QI
1569: (ashift:SI (const_int 1)
1570: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1571: ""
1572: "ibitb %1,%0")
1573:
1574: ;; Recognize jbs and jbc instructions.
1575:
1576: (define_insn ""
1577: [(set (cc0)
1578: (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1579: (const_int 1)
1580: (match_operand:SI 1 "general_operand" "rmn")))]
1581: ""
1582: "*
1583: { cc_status.flags = CC_Z_IN_F;
1584: return \"tbitd %1,%0\";
1585: }")
1586:
1587: (define_insn ""
1588: [(set (cc0)
1589: (minus (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1590: (const_int 1)
1591: (match_operand:SI 1 "general_operand" "rmn"))
1592: (const_int 1)))]
1593: ""
1594: "*
1595: { cc_status.flags = CC_Z_IN_NOT_F;
1596: return \"tbitd %1,%0\";
1597: }")
1598:
1599: (define_insn ""
1600: [(set (cc0)
1601: (zero_extract (match_operand:HI 0 "general_operand" "g")
1602: (const_int 1)
1603: (match_operand:HI 1 "general_operand" "g")))]
1604: ""
1605: "*
1606: { cc_status.flags = CC_Z_IN_F;
1607: return \"tbitw %1,%0\";
1608: }")
1609:
1610: (define_insn ""
1611: [(set (cc0)
1612: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1613: (const_int 1)
1614: (match_operand:HI 1 "general_operand" "rmn"))
1615: (const_int 1)))]
1616: ""
1617: "*
1618: { cc_status.flags = CC_Z_IN_NOT_F;
1619: return \"tbitw %1,%0\";
1620: }")
1621:
1622: (define_insn ""
1623: [(set (cc0)
1624: (zero_extract (match_operand:QI 0 "general_operand" "g")
1625: (const_int 1)
1626: (match_operand:QI 1 "general_operand" "g")))]
1627: ""
1628: "*
1629: { cc_status.flags = CC_Z_IN_F;
1630: return \"tbitb %1,%0\";
1631: }")
1632:
1633: (define_insn ""
1634: [(set (cc0)
1635: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1636: (const_int 1)
1637: (match_operand:QI 1 "general_operand" "rmn"))
1638: (const_int 1)))]
1639: ""
1640: "*
1641: { cc_status.flags = CC_Z_IN_NOT_F;
1642: return \"tbitb %1,%0\";
1643: }")
1644:
1645: (define_insn ""
1646: [(set (cc0)
1647: (and:SI (match_operand:SI 0 "general_operand" "rmn")
1648: (match_operand:SI 1 "immediate_operand" "i")))]
1649: "GET_CODE (operands[1]) == CONST_INT
1650: && exact_log2 (INTVAL (operands[1])) >= 0"
1651: "*
1652: {
1653: operands[1]
1654: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1655: cc_status.flags = CC_Z_IN_F;
1656: return \"tbitd %1,%0\";
1657: }")
1658:
1659: ;; extract(base, width, offset)
1660: ;; Signed bitfield extraction is not supported in hardware on the
1661: ;; NS 32032. It is therefore better to let GCC figure out a
1662: ;; good strategy for generating the proper instruction sequence
1663: ;; and represent it as rtl.
1664:
1665: (define_insn "extzv"
1666: [(set (match_operand:SI 0 "general_operand" "=g<")
1667: (zero_extract:SI (match_operand:SI 1 "general_operand" "rmn")
1668: (match_operand:SI 2 "const_int" "i")
1669: (match_operand:SI 3 "general_operand" "ri")))]
1670: ""
1671: "*
1672: { if (GET_CODE (operands[3]) == CONST_INT)
1673: return \"extsd %1,%0,%3,%2\";
1674: else return \"extd %3,%1,%0,%2\";
1675: }")
1676:
1677: (define_insn ""
1678: [(set (match_operand:SI 0 "general_operand" "=g<")
1679: (zero_extract:SI (match_operand:HI 1 "general_operand" "g")
1680: (match_operand:SI 2 "const_int" "i")
1681: (match_operand:SI 3 "general_operand" "ri")))]
1682: ""
1683: "*
1684: { if (GET_CODE (operands[3]) == CONST_INT)
1685: return \"extsd %1,%0,%3,%2\";
1686: else return \"extd %3,%1,%0,%2\";
1687: }")
1688:
1689: (define_insn ""
1690: [(set (match_operand:SI 0 "general_operand" "=g<")
1691: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1692: (match_operand:SI 2 "const_int" "i")
1693: (match_operand:SI 3 "general_operand" "ri")))]
1694: ""
1695: "*
1696: { if (GET_CODE (operands[3]) == CONST_INT)
1697: return \"extsd %1,%0,%3,%2\";
1698: else return \"extd %3,%1,%0,%2\";
1699: }")
1700:
1701: (define_insn "insv"
1702: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "=g")
1703: (match_operand:SI 1 "const_int" "i")
1704: (match_operand:SI 2 "general_operand" "ri"))
1705: (match_operand:SI 3 "general_operand" "rmn"))]
1706: ""
1707: "*
1708: { if (GET_CODE (operands[2]) == CONST_INT)
1709: if (INTVAL (operands[1]) <= 8)
1710: return \"inssb %3,%0,%2,%1\";
1711: else if (INTVAL (operands[1]) <= 16)
1712: return \"inssw %3,%0,%2,%1\";
1713: else
1714: return \"inssd %3,%0,%2,%1\";
1715: else return \"insd %2,%3,%0,%1\";
1716: }")
1717:
1718: (define_insn ""
1719: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "=g")
1720: (match_operand:SI 1 "const_int" "i")
1721: (match_operand:SI 2 "general_operand" "ri"))
1722: (match_operand:SI 3 "general_operand" "rmn"))]
1723: ""
1724: "*
1725: { if (GET_CODE (operands[2]) == CONST_INT)
1726: if (INTVAL (operands[1]) <= 8)
1727: return \"inssb %3,%0,%2,%1\";
1728: else if (INTVAL (operands[1]) <= 16)
1729: return \"inssw %3,%0,%2,%1\";
1730: else
1731: return \"inssd %3,%0,%2,%1\";
1732: else return \"insd %2,%3,%0,%1\";
1733: }")
1734:
1735: (define_insn ""
1736: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1737: (match_operand:SI 1 "const_int" "i")
1738: (match_operand:SI 2 "general_operand" "ri"))
1739: (match_operand:SI 3 "general_operand" "rmn"))]
1740: ""
1741: "*
1742: { if (GET_CODE (operands[2]) == CONST_INT)
1743: if (INTVAL (operands[1]) <= 8)
1744: return \"inssb %3,%0,%2,%1\";
1745: else if (INTVAL (operands[1]) <= 16)
1746: return \"inssw %3,%0,%2,%1\";
1747: else
1748: return \"inssd %3,%0,%2,%1\";
1749: else return \"insd %2,%3,%0,%1\";
1750: }")
1751:
1752:
1753: (define_insn "jump"
1754: [(set (pc)
1755: (label_ref (match_operand 0 "" "")))]
1756: ""
1757: "br %l0")
1758:
1759: (define_insn "beq"
1760: [(set (pc)
1761: (if_then_else (eq (cc0)
1762: (const_int 0))
1763: (label_ref (match_operand 0 "" ""))
1764: (pc)))]
1765: ""
1766: "*
1767: { if (cc_prev_status.flags & CC_Z_IN_F)
1768: return \"bfc %l0\";
1769: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1770: return \"bfs %l0\";
1771: else return \"beq %l0\";
1772: }")
1773:
1774: (define_insn "bne"
1775: [(set (pc)
1776: (if_then_else (ne (cc0)
1777: (const_int 0))
1778: (label_ref (match_operand 0 "" ""))
1779: (pc)))]
1780: ""
1781: "*
1782: { if (cc_prev_status.flags & CC_Z_IN_F)
1783: return \"bfs %l0\";
1784: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1785: return \"bfc %l0\";
1786: else return \"bne %l0\";
1787: }")
1788:
1789: (define_insn "bgt"
1790: [(set (pc)
1791: (if_then_else (gt (cc0)
1792: (const_int 0))
1793: (label_ref (match_operand 0 "" ""))
1794: (pc)))]
1795: ""
1796: "bgt %l0")
1797:
1798: (define_insn "bgtu"
1799: [(set (pc)
1800: (if_then_else (gtu (cc0)
1801: (const_int 0))
1802: (label_ref (match_operand 0 "" ""))
1803: (pc)))]
1804: ""
1805: "bhi %l0")
1806:
1807: (define_insn "blt"
1808: [(set (pc)
1809: (if_then_else (lt (cc0)
1810: (const_int 0))
1811: (label_ref (match_operand 0 "" ""))
1812: (pc)))]
1813: ""
1814: "blt %l0")
1815:
1816: (define_insn "bltu"
1817: [(set (pc)
1818: (if_then_else (ltu (cc0)
1819: (const_int 0))
1820: (label_ref (match_operand 0 "" ""))
1821: (pc)))]
1822: ""
1823: "blo %l0")
1824:
1825: (define_insn "bge"
1826: [(set (pc)
1827: (if_then_else (ge (cc0)
1828: (const_int 0))
1829: (label_ref (match_operand 0 "" ""))
1830: (pc)))]
1831: ""
1832: "bge %l0")
1833:
1834: (define_insn "bgeu"
1835: [(set (pc)
1836: (if_then_else (geu (cc0)
1837: (const_int 0))
1838: (label_ref (match_operand 0 "" ""))
1839: (pc)))]
1840: ""
1841: "bhs %l0")
1842:
1843: (define_insn "ble"
1844: [(set (pc)
1845: (if_then_else (le (cc0)
1846: (const_int 0))
1847: (label_ref (match_operand 0 "" ""))
1848: (pc)))]
1849: ""
1850: "ble %l0")
1851:
1852: (define_insn "bleu"
1853: [(set (pc)
1854: (if_then_else (leu (cc0)
1855: (const_int 0))
1856: (label_ref (match_operand 0 "" ""))
1857: (pc)))]
1858: ""
1859: "bls %l0")
1860:
1861: (define_insn ""
1862: [(set (pc)
1863: (if_then_else (eq (cc0)
1864: (const_int 0))
1865: (pc)
1866: (label_ref (match_operand 0 "" ""))))]
1867: ""
1868: "*
1869: { if (cc_prev_status.flags & CC_Z_IN_F)
1870: return \"bfs %l0\";
1871: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1872: return \"bfc %l0\";
1873: else return \"bne %l0\";
1874: }")
1875:
1876: (define_insn ""
1877: [(set (pc)
1878: (if_then_else (ne (cc0)
1879: (const_int 0))
1880: (pc)
1881: (label_ref (match_operand 0 "" ""))))]
1882: ""
1883: "*
1884: { if (cc_prev_status.flags & CC_Z_IN_F)
1885: return \"bfc %l0\";
1886: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1887: return \"bfs %l0\";
1888: else return \"beq %l0\";
1889: }")
1890:
1891: (define_insn ""
1892: [(set (pc)
1893: (if_then_else (gt (cc0)
1894: (const_int 0))
1895: (pc)
1896: (label_ref (match_operand 0 "" ""))))]
1897: ""
1898: "ble %l0")
1899:
1900: (define_insn ""
1901: [(set (pc)
1902: (if_then_else (gtu (cc0)
1903: (const_int 0))
1904: (pc)
1905: (label_ref (match_operand 0 "" ""))))]
1906: ""
1907: "bls %l0")
1908:
1909: (define_insn ""
1910: [(set (pc)
1911: (if_then_else (lt (cc0)
1912: (const_int 0))
1913: (pc)
1914: (label_ref (match_operand 0 "" ""))))]
1915: ""
1916: "bge %l0")
1917:
1918: (define_insn ""
1919: [(set (pc)
1920: (if_then_else (ltu (cc0)
1921: (const_int 0))
1922: (pc)
1923: (label_ref (match_operand 0 "" ""))))]
1924: ""
1925: "bhs %l0")
1926:
1927: (define_insn ""
1928: [(set (pc)
1929: (if_then_else (ge (cc0)
1930: (const_int 0))
1931: (pc)
1932: (label_ref (match_operand 0 "" ""))))]
1933: ""
1934: "blt %l0")
1935:
1936: (define_insn ""
1937: [(set (pc)
1938: (if_then_else (geu (cc0)
1939: (const_int 0))
1940: (pc)
1941: (label_ref (match_operand 0 "" ""))))]
1942: ""
1943: "blo %l0")
1944:
1945: (define_insn ""
1946: [(set (pc)
1947: (if_then_else (le (cc0)
1948: (const_int 0))
1949: (pc)
1950: (label_ref (match_operand 0 "" ""))))]
1951: ""
1952: "bgt %l0")
1953:
1954: (define_insn ""
1955: [(set (pc)
1956: (if_then_else (leu (cc0)
1957: (const_int 0))
1958: (pc)
1959: (label_ref (match_operand 0 "" ""))))]
1960: ""
1961: "bhi %l0")
1962:
1963: ;; Subtract-and-jump and Add-and-jump insns.
1964: ;; These can actually be used for adding numbers in the range -8 to 7
1965:
1966: (define_insn ""
1967: [(set (pc)
1968: (if_then_else
1969: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
1970: (match_operand:SI 1 "general_operand" "i"))
1971: (const_int 0))
1972: (label_ref (match_operand 2 "" ""))
1973: (pc)))
1974: (set (match_dup 0)
1975: (minus:SI (match_dup 0)
1976: (match_dup 1)))]
1977: "GET_CODE (operands[1]) == CONST_INT
1978: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
1979: "acbd %$%n1,%0,%l2")
1980:
1981: (define_insn ""
1982: [(set (pc)
1983: (if_then_else
1984: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
1985: (match_operand:SI 1 "general_operand" "i"))
1986: (const_int 0))
1987: (label_ref (match_operand 2 "" ""))
1988: (pc)))
1989: (set (match_dup 0)
1990: (plus:SI (match_dup 0)
1991: (match_dup 1)))]
1992: "GET_CODE (operands[1]) == CONST_INT
1993: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
1994: "acbd %1,%0,%l2")
1995:
1996: ;; Reversed
1997:
1998: (define_insn ""
1999: [(set (pc)
2000: (if_then_else
2001: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2002: (match_operand:SI 1 "general_operand" "i"))
2003: (const_int 0))
2004: (pc)
2005: (label_ref (match_operand 2 "" ""))))
2006: (set (match_dup 0)
2007: (minus:SI (match_dup 0)
2008: (match_dup 1)))]
2009: "GET_CODE (operands[1]) == CONST_INT
2010: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2011: "acbd %$%n1,%0,%l2")
2012:
2013: (define_insn ""
2014: [(set (pc)
2015: (if_then_else
2016: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2017: (match_operand:SI 1 "general_operand" "i"))
2018: (const_int 0))
2019: (pc)
2020: (label_ref (match_operand 2 "" ""))))
2021: (set (match_dup 0)
2022: (plus:SI (match_dup 0)
2023: (match_dup 1)))]
2024: "GET_CODE (operands[1]) == CONST_INT
2025: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2026: "acbd %1,%0,%l2")
2027:
2028: (define_insn "call"
2029: [(call (match_operand:QI 0 "general_operand" "g")
2030: (match_operand:QI 1 "general_operand" "g"))]
2031: ""
2032: "*
2033: {
2034: if (GET_CODE (operands[0]) == MEM)
2035: {
2036: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
2037: return \"bsr %a0\";
2038: if (GET_CODE (XEXP (operands[0], 0)) == REG)
2039: return \"jsr %a0\";
2040: }
2041: return \"jsr %0\";
2042: }")
2043:
2044: (define_insn "call_value"
2045: [(set (match_operand 0 "" "fg")
2046: (call (match_operand:QI 1 "general_operand" "g")
2047: (match_operand:QI 2 "general_operand" "g")))]
2048: ""
2049: "*
2050: {
2051: if (GET_CODE (operands[1]) == MEM)
2052: {
2053: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
2054: return \"bsr %a1\";
2055: if (GET_CODE (XEXP (operands[1], 0)) == REG)
2056: return \"jsr %a1\";
2057: }
2058: return \"jsr %1\";
2059: }")
2060:
2061: (define_insn "return"
2062: [(return)]
2063: ""
2064: "ret 0")
2065:
2066: (define_insn "abssf2"
2067: [(set (match_operand:SF 0 "general_operand" "=fm<")
2068: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2069: "TARGET_32081"
2070: "absf %1,%0")
2071:
2072: (define_insn "absdf2"
2073: [(set (match_operand:DF 0 "general_operand" "=fm<")
2074: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2075: "TARGET_32081"
2076: "absl %1,%0")
2077:
2078: (define_insn "abssi2"
2079: [(set (match_operand:SI 0 "general_operand" "=g<")
2080: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2081: ""
2082: "absd %1,%0")
2083:
2084: (define_insn "abshi2"
2085: [(set (match_operand:HI 0 "general_operand" "=g<")
2086: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2087: ""
2088: "absw %1,%0")
2089:
2090: (define_insn "absqi2"
2091: [(set (match_operand:QI 0 "general_operand" "=g<")
2092: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2093: ""
2094: "absb %1,%0")
2095:
2096: ;;(define_insn "tablejump"
2097: ;; [(set (pc)
2098: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2099: ;; (pc)))]
2100: ;; ""
2101: ;; "cased %0")
2102:
2103: (define_insn "tablejump"
2104: [(set (pc)
2105: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2106: (use (label_ref (match_operand 1 "" "")))]
2107: ""
2108: "*
2109: {
2110: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2111: CODE_LABEL_NUMBER (operands[1]));
2112: return \"casew %0\";
2113: }")
2114:
2115: ;;(define_insn ""
2116: ;; [(set (pc)
2117: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2118: ;; (pc)))]
2119: ;; ""
2120: ;; "caseb %0")
2121:
2122: ;; Scondi instructions
2123: (define_insn "seq"
2124: [(set (match_operand:SI 0 "general_operand" "=g<")
2125: (eq (cc0) (const_int 0)))]
2126: ""
2127: "*
2128: { if (cc_prev_status.flags & CC_Z_IN_F)
2129: return \"sfcd %0\";
2130: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2131: return \"sfsd %0\";
2132: else return \"seqd %0\";
2133: }")
2134:
2135: (define_insn ""
2136: [(set (match_operand:HI 0 "general_operand" "=g<")
2137: (eq (cc0) (const_int 0)))]
2138: ""
2139: "*
2140: { if (cc_prev_status.flags & CC_Z_IN_F)
2141: return \"sfcw %0\";
2142: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2143: return \"sfsw %0\";
2144: else return \"seqw %0\";
2145: }")
2146:
2147: (define_insn ""
2148: [(set (match_operand:QI 0 "general_operand" "=g<")
2149: (eq (cc0) (const_int 0)))]
2150: ""
2151: "*
2152: { if (cc_prev_status.flags & CC_Z_IN_F)
2153: return \"sfcb %0\";
2154: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2155: return \"sfsb %0\";
2156: else return \"seqb %0\";
2157: }")
2158:
2159: (define_insn "sne"
2160: [(set (match_operand:SI 0 "general_operand" "=g<")
2161: (ne (cc0) (const_int 0)))]
2162: ""
2163: "*
2164: { if (cc_prev_status.flags & CC_Z_IN_F)
2165: return \"sfsd %0\";
2166: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2167: return \"sfcd %0\";
2168: else return \"sned %0\";
2169: }")
2170:
2171: (define_insn ""
2172: [(set (match_operand:HI 0 "general_operand" "=g<")
2173: (ne (cc0) (const_int 0)))]
2174: ""
2175: "*
2176: { if (cc_prev_status.flags & CC_Z_IN_F)
2177: return \"sfsw %0\";
2178: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2179: return \"sfcw %0\";
2180: else return \"snew %0\";
2181: }")
2182:
2183: (define_insn ""
2184: [(set (match_operand:QI 0 "general_operand" "=g<")
2185: (ne (cc0) (const_int 0)))]
2186: ""
2187: "*
2188: { if (cc_prev_status.flags & CC_Z_IN_F)
2189: return \"sfsb %0\";
2190: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2191: return \"sfcb %0\";
2192: else return \"sneb %0\";
2193: }")
2194:
2195: (define_insn "sgt"
2196: [(set (match_operand:SI 0 "general_operand" "=g<")
2197: (gt (cc0) (const_int 0)))]
2198: ""
2199: "sgtd %0")
2200:
2201: (define_insn ""
2202: [(set (match_operand:HI 0 "general_operand" "=g<")
2203: (gt (cc0) (const_int 0)))]
2204: ""
2205: "sgtw %0")
2206:
2207: (define_insn ""
2208: [(set (match_operand:QI 0 "general_operand" "=g<")
2209: (gt (cc0) (const_int 0)))]
2210: ""
2211: "sgtb %0")
2212:
2213: (define_insn "sgtu"
2214: [(set (match_operand:SI 0 "general_operand" "=g<")
2215: (gtu (cc0) (const_int 0)))]
2216: ""
2217: "shid %0")
2218:
2219: (define_insn ""
2220: [(set (match_operand:HI 0 "general_operand" "=g<")
2221: (gtu (cc0) (const_int 0)))]
2222: ""
2223: "shiw %0")
2224:
2225: (define_insn ""
2226: [(set (match_operand:QI 0 "general_operand" "=g<")
2227: (gtu (cc0) (const_int 0)))]
2228: ""
2229: "shib %0")
2230:
2231: (define_insn "slt"
2232: [(set (match_operand:SI 0 "general_operand" "=g<")
2233: (lt (cc0) (const_int 0)))]
2234: ""
2235: "sltd %0")
2236:
2237: (define_insn ""
2238: [(set (match_operand:HI 0 "general_operand" "=g<")
2239: (lt (cc0) (const_int 0)))]
2240: ""
2241: "sltw %0")
2242:
2243: (define_insn ""
2244: [(set (match_operand:QI 0 "general_operand" "=g<")
2245: (lt (cc0) (const_int 0)))]
2246: ""
2247: "sltb %0")
2248:
2249: (define_insn "sltu"
2250: [(set (match_operand:SI 0 "general_operand" "=g<")
2251: (ltu (cc0) (const_int 0)))]
2252: ""
2253: "slod %0")
2254:
2255: (define_insn ""
2256: [(set (match_operand:HI 0 "general_operand" "=g<")
2257: (ltu (cc0) (const_int 0)))]
2258: ""
2259: "slow %0")
2260:
2261: (define_insn ""
2262: [(set (match_operand:QI 0 "general_operand" "=g<")
2263: (ltu (cc0) (const_int 0)))]
2264: ""
2265: "slob %0")
2266:
2267: (define_insn "sge"
2268: [(set (match_operand:SI 0 "general_operand" "=g<")
2269: (ge (cc0) (const_int 0)))]
2270: ""
2271: "sged %0")
2272:
2273: (define_insn ""
2274: [(set (match_operand:HI 0 "general_operand" "=g<")
2275: (ge (cc0) (const_int 0)))]
2276: ""
2277: "sgew %0")
2278:
2279: (define_insn ""
2280: [(set (match_operand:QI 0 "general_operand" "=g<")
2281: (ge (cc0) (const_int 0)))]
2282: ""
2283: "sgeb %0")
2284:
2285: (define_insn "sgeu"
2286: [(set (match_operand:SI 0 "general_operand" "=g<")
2287: (geu (cc0) (const_int 0)))]
2288: ""
2289: "shsd %0")
2290:
2291: (define_insn ""
2292: [(set (match_operand:HI 0 "general_operand" "=g<")
2293: (geu (cc0) (const_int 0)))]
2294: ""
2295: "shsw %0")
2296:
2297: (define_insn ""
2298: [(set (match_operand:QI 0 "general_operand" "=g<")
2299: (geu (cc0) (const_int 0)))]
2300: ""
2301: "shsb %0")
2302:
2303: (define_insn "sle"
2304: [(set (match_operand:SI 0 "general_operand" "=g<")
2305: (le (cc0) (const_int 0)))]
2306: ""
2307: "sled %0")
2308:
2309: (define_insn ""
2310: [(set (match_operand:HI 0 "general_operand" "=g<")
2311: (le (cc0) (const_int 0)))]
2312: ""
2313: "slew %0")
2314:
2315: (define_insn ""
2316: [(set (match_operand:QI 0 "general_operand" "=g<")
2317: (le (cc0) (const_int 0)))]
2318: ""
2319: "sleb %0")
2320:
2321: (define_insn "sleu"
2322: [(set (match_operand:SI 0 "general_operand" "=g<")
2323: (leu (cc0) (const_int 0)))]
2324: ""
2325: "slsd %0")
2326:
2327: (define_insn ""
2328: [(set (match_operand:HI 0 "general_operand" "=g<")
2329: (leu (cc0) (const_int 0)))]
2330: ""
2331: "slsw %0")
2332:
2333: (define_insn ""
2334: [(set (match_operand:QI 0 "general_operand" "=g<")
2335: (leu (cc0) (const_int 0)))]
2336: ""
2337: "slsb %0")
2338:
2339: ;;- Local variables:
2340: ;;- mode:emacs-lisp
2341: ;;- comment-start: ";;- "
2342: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2343: ;;- eval: (modify-syntax-entry ?[ "(]")
2344: ;;- eval: (modify-syntax-entry ?] ")[")
2345: ;;- eval: (modify-syntax-entry ?{ "(}")
2346: ;;- eval: (modify-syntax-entry ?} "){")
2347: ;;- End:
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