![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to ns32k.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 1.x] / gcc|
Return to ns32k.md CVS log | Up to [GCC 1.x] / gcc |
1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
1.1.1.2 root 48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
1.1 root 51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "general_operand" "g"))]
55: ""
56: "*
1.1.1.2 root 57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
1.1 root 60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "general_operand" "g"))]
64: ""
65: "*
1.1.1.2 root 66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
1.1 root 69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
1.1.1.2 root 75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = dconst0_rtx;
77: return \"cmpl %1,%0\"; }")
1.1 root 78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
1.1.1.2 root 84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = fconst0_rtx;
86: return \"cmpf %1,%0\"; }")
1.1 root 87:
88: (define_insn "cmpdf"
89: [(set (cc0)
90: (minus (match_operand:DF 0 "general_operand" "fmF")
91: (match_operand:DF 1 "general_operand" "fmF")))]
92: "TARGET_32081"
93: "cmpl %0,%1")
94:
95: (define_insn "cmpsf"
96: [(set (cc0)
97: (minus (match_operand:SF 0 "general_operand" "fmF")
98: (match_operand:SF 1 "general_operand" "fmF")))]
99: "TARGET_32081"
100: "cmpf %0,%1")
101:
102: (define_insn "cmpsi"
103: [(set (cc0)
104: (minus (match_operand:SI 0 "general_operand" "rmn")
105: (match_operand:SI 1 "general_operand" "rmn")))]
106: ""
107: "*
108: {
109: if (GET_CODE (operands[1]) == CONST_INT)
110: {
111: int i = INTVAL (operands[1]);
112: if (i <= 7 && i >= -8)
113: {
114: cc_status.flags |= CC_REVERSED;
115: return \"cmpqd %1,%0\";
116: }
117: }
118: cc_status.flags &= ~CC_REVERSED;
119: if (GET_CODE (operands[0]) == CONST_INT)
120: {
121: int i = INTVAL (operands[0]);
122: if (i <= 7 && i >= -8)
123: return \"cmpqd %0,%1\";
124: }
125: return \"cmpd %0,%1\";
126: }")
127:
128: (define_insn "cmphi"
129: [(set (cc0)
130: (minus (match_operand:HI 0 "general_operand" "g")
131: (match_operand:HI 1 "general_operand" "g")))]
132: ""
133: "*
134: {
135: if (GET_CODE (operands[1]) == CONST_INT)
136: {
137: short i = INTVAL (operands[1]);
138: if (i <= 7 && i >= -8)
139: {
140: cc_status.flags |= CC_REVERSED;
141: if (INTVAL (operands[1]) > 7)
142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
143: return \"cmpqw %1,%0\";
144: }
145: }
146: cc_status.flags &= ~CC_REVERSED;
147: if (GET_CODE (operands[0]) == CONST_INT)
148: {
149: short i = INTVAL (operands[0]);
150: if (i <= 7 && i >= -8)
151: {
152: if (INTVAL (operands[0]) > 7)
153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
154: return \"cmpqw %0,%1\";
155: }
156: }
157: return \"cmpw %0,%1\";
158: }")
159:
160: (define_insn "cmpqi"
161: [(set (cc0)
162: (minus (match_operand:QI 0 "general_operand" "g")
163: (match_operand:QI 1 "general_operand" "g")))]
164: ""
165: "*
166: {
167: if (GET_CODE (operands[1]) == CONST_INT)
168: {
169: char i = INTVAL (operands[1]);
170: if (i <= 7 && i >= -8)
171: {
172: cc_status.flags |= CC_REVERSED;
173: if (INTVAL (operands[1]) > 7)
174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
175: return \"cmpqb %1,%0\";
176: }
177: }
178: cc_status.flags &= ~CC_REVERSED;
179: if (GET_CODE (operands[0]) == CONST_INT)
180: {
181: char i = INTVAL (operands[0]);
182: if (i <= 7 && i >= -8)
183: {
184: if (INTVAL (operands[0]) > 7)
185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
186: return \"cmpqb %0,%1\";
187: }
188: }
189: return \"cmpb %0,%1\";
190: }")
191:
192: (define_insn "movdf"
1.1.1.8 root 193: [(set (match_operand:DF 0 "general_operand" "=&fg<")
1.1 root 194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
246: {
247: /* Is there a better machine-independent way to to this? */
248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
249: return \"movd %1,%0\";
250: }
251: else return \"movd %1,%0\";
252: }")
253:
254: (define_insn ""
255: [(set (match_operand:TI 0 "memory_operand" "=m")
256: (match_operand:TI 1 "memory_operand" "m"))]
257: ""
258: "movmd %1,%0,4")
259:
260: (define_insn "movdi"
1.1.1.8 root 261: [(set (match_operand:DI 0 "general_operand" "=&g<")
1.1.1.3 root 262: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 263: ""
264: "* return output_move_double (operands); ")
265:
1.1.1.9 root 266: ;; This special case must precede movsi.
267: (define_insn ""
268: [(set (reg:SI 17)
269: (match_operand:SI 0 "general_operand" "rmn"))]
270: ""
271: "lprd sp,%0")
272:
1.1 root 273: (define_insn "movsi"
274: [(set (match_operand:SI 0 "general_operand" "=g<")
275: (match_operand:SI 1 "general_operand" "gx"))]
276: ""
277: "*
278: { if (GET_CODE (operands[1]) == CONST_INT)
279: {
280: int i = INTVAL (operands[1]);
281: if (i <= 7 && i >= -8)
282: return \"movqd %1,%0\";
283: if (i < 0x4000 && i >= -0x4000)
1.1.1.4 root 284: #ifdef GNX_V3
285: return \"addr %c1,%0\";
286: #else
1.1.1.2 root 287: return \"addr @%c1,%0\";
1.1.1.4 root 288: #endif
1.1 root 289: return \"movd %1,%0\";
290: }
291: else if (GET_CODE (operands[1]) == REG)
292: if (REGNO (operands[1]) < 16)
293: return \"movd %1,%0\";
294: else if (REGNO (operands[1]) == 16)
295: return \"addr 0(fp),%0\";
296: else return \"addr tos,%0\";
297: else if (GET_CODE (operands[1]) == MEM)
298: return \"movd %1,%0\";
1.1.1.2 root 299: /* Check if this effective address can be
300: calculated faster by pulling it apart. */
301: if (REG_P (operands[0])
302: && GET_CODE (operands[1]) == MULT
303: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
304: && (INTVAL (XEXP (operands[1], 1)) == 2
305: || INTVAL (XEXP (operands[1], 1)) == 4))
306: {
307: rtx xoperands[3];
308: xoperands[0] = operands[0];
309: xoperands[1] = XEXP (operands[1], 0);
310: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
311: return output_shift_insn (xoperands);
312: }
1.1 root 313: return \"addr %a1,%0\";
314: }")
315:
316: (define_insn "movhi"
317: [(set (match_operand:HI 0 "general_operand" "=g<")
318: (match_operand:HI 1 "general_operand" "g"))]
319: ""
320: "*
321: {
322: if (GET_CODE (operands[1]) == CONST_INT)
323: {
324: short i = INTVAL (operands[1]);
325: if (i <= 7 && i >= -8)
326: {
327: if (INTVAL (operands[1]) > 7)
328: operands[1] =
329: gen_rtx (CONST_INT, VOIDmode, i);
330: return \"movqw %1,%0\";
331: }
332: }
333: return \"movw %1,%0\";
334: }")
335:
336: (define_insn "movstricthi"
337: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
338: (match_operand:HI 1 "general_operand" "g"))]
339: ""
340: "*
341: {
342: if (GET_CODE (operands[1]) == CONST_INT
343: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
344: return \"movqw %1,%0\";
345: return \"movw %1,%0\";
346: }")
347:
348: (define_insn "movqi"
349: [(set (match_operand:QI 0 "general_operand" "=g<")
350: (match_operand:QI 1 "general_operand" "g"))]
351: ""
352: "*
353: { if (GET_CODE (operands[1]) == CONST_INT)
354: {
355: char char_val = (char)INTVAL (operands[1]);
356: if (char_val <= 7 && char_val >= -8)
357: {
358: if (INTVAL (operands[1]) > 7)
359: operands[1] =
360: gen_rtx (CONST_INT, VOIDmode, char_val);
361: return \"movqb %1,%0\";
362: }
363: }
364: return \"movb %1,%0\";
365: }")
366:
367: (define_insn "movstrictqi"
368: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
369: (match_operand:QI 1 "general_operand" "g"))]
370: ""
371: "*
372: {
373: if (GET_CODE (operands[1]) == CONST_INT
374: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
375: return \"movqb %1,%0\";
376: return \"movb %1,%0\";
377: }")
378:
379: ;; The definition of this insn does not really explain what it does,
380: ;; but it should suffice
381: ;; that anything generated as this insn will be recognized as one
382: ;; and that it won't successfully combine with anything.
383: (define_insn "movstrsi"
384: [(set (match_operand:BLK 0 "general_operand" "=g")
385: (match_operand:BLK 1 "general_operand" "g"))
386: (use (match_operand:SI 2 "general_operand" "rmn"))
387: (clobber (reg:SI 0))
388: (clobber (reg:SI 1))
389: (clobber (reg:SI 2))]
390: ""
391: "*
392: {
393: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
394: abort ();
395: operands[0] = XEXP (operands[0], 0);
396: operands[1] = XEXP (operands[1], 0);
397: if (GET_CODE (operands[0]) == MEM)
398: if (GET_CODE (operands[1]) == MEM)
399: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
400: else
401: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
402: else if (GET_CODE (operands[1]) == MEM)
403: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
404: else
405: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
406:
407: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
408: {
409: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
410: if ((unsigned) INTVAL (operands[2]) <= 7)
411: return \"movqd %2,r0\;movsd\";
412: else
413: return \"movd %2,r0\;movsd\";
414: }
415: else
416: {
417: return \"movd %2,r0\;movsb\";
418: }
419: }")
420:
421: ;; Extension and truncation insns.
422: ;; Those for integer source operand
423: ;; are ordered widest source type first.
424:
425: (define_insn "truncsiqi2"
426: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 427: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 428: ""
429: "movb %1,%0")
430:
431: (define_insn "truncsihi2"
432: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 433: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 434: ""
435: "movw %1,%0")
436:
437: (define_insn "trunchiqi2"
438: [(set (match_operand:QI 0 "general_operand" "=g<")
439: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
440: ""
441: "movb %1,%0")
442:
443: (define_insn "extendhisi2"
444: [(set (match_operand:SI 0 "general_operand" "=g<")
445: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
446: ""
447: "movxwd %1,%0")
448:
449: (define_insn "extendqihi2"
450: [(set (match_operand:HI 0 "general_operand" "=g<")
451: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
452: ""
453: "movxbw %1,%0")
454:
455: (define_insn "extendqisi2"
456: [(set (match_operand:SI 0 "general_operand" "=g<")
457: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
458: ""
459: "movxbd %1,%0")
460:
461: (define_insn "extendsfdf2"
462: [(set (match_operand:DF 0 "general_operand" "=fm<")
463: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
464: "TARGET_32081"
465: "movfl %1,%0")
466:
467: (define_insn "truncdfsf2"
468: [(set (match_operand:SF 0 "general_operand" "=fm<")
469: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
470: "TARGET_32081"
471: "movlf %1,%0")
472:
473: (define_insn "zero_extendhisi2"
474: [(set (match_operand:SI 0 "general_operand" "=g<")
475: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
476: ""
477: "movzwd %1,%0")
478:
479: (define_insn "zero_extendqihi2"
480: [(set (match_operand:HI 0 "general_operand" "=g<")
481: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
482: ""
483: "movzbw %1,%0")
484:
485: (define_insn "zero_extendqisi2"
486: [(set (match_operand:SI 0 "general_operand" "=g<")
487: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
488: ""
489: "movzbd %1,%0")
490:
491: ;; Fix-to-float conversion insns.
492: ;; Note that the ones that start with SImode come first.
493: ;; That is so that an operand that is a CONST_INT
494: ;; (and therefore lacks a specific machine mode).
495: ;; will be recognized as SImode (which is always valid)
496: ;; rather than as QImode or HImode.
497:
498: ;; Rumor has it that the National part does not correctly convert
499: ;; constant ints to floats. This conversion is therefore disabled.
500: ;; A register must be used to perform the conversion.
501:
502: (define_insn "floatsisf2"
503: [(set (match_operand:SF 0 "general_operand" "=fm<")
504: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
505: "TARGET_32081"
506: "movdf %1,%0")
507:
508: (define_insn "floatsidf2"
509: [(set (match_operand:DF 0 "general_operand" "=fm<")
510: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
511: "TARGET_32081"
512: "movdl %1,%0")
513:
514: (define_insn "floathisf2"
515: [(set (match_operand:SF 0 "general_operand" "=fm<")
516: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
517: "TARGET_32081"
518: "movwf %1,%0")
519:
520: (define_insn "floathidf2"
521: [(set (match_operand:DF 0 "general_operand" "=fm<")
522: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
523: "TARGET_32081"
524: "movwl %1,%0")
525:
526: (define_insn "floatqisf2"
527: [(set (match_operand:SF 0 "general_operand" "=fm<")
528: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
529: "TARGET_32081"
530: "movbf %1,%0")
531:
1.1.1.3 root 532: ; Some assemblers warn that this insn doesn't work.
533: ; Maybe they know something we don't.
534: ;(define_insn "floatqidf2"
535: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
536: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
537: ; "TARGET_32081"
538: ; "movbl %1,%0")
1.1 root 539:
540: ;; Float-to-fix conversion insns.
541: ;; The sequent compiler always generates "trunc" insns.
542:
543: (define_insn "fixsfqi2"
544: [(set (match_operand:QI 0 "general_operand" "=g<")
545: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
546: "TARGET_32081"
547: "truncfb %1,%0")
548:
549: (define_insn "fixsfhi2"
550: [(set (match_operand:HI 0 "general_operand" "=g<")
551: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
552: "TARGET_32081"
553: "truncfw %1,%0")
554:
555: (define_insn "fixsfsi2"
556: [(set (match_operand:SI 0 "general_operand" "=g<")
557: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
558: "TARGET_32081"
559: "truncfd %1,%0")
560:
561: (define_insn "fixdfqi2"
562: [(set (match_operand:QI 0 "general_operand" "=g<")
563: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
564: "TARGET_32081"
565: "trunclb %1,%0")
566:
567: (define_insn "fixdfhi2"
568: [(set (match_operand:HI 0 "general_operand" "=g<")
569: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
570: "TARGET_32081"
571: "trunclw %1,%0")
572:
573: (define_insn "fixdfsi2"
574: [(set (match_operand:SI 0 "general_operand" "=g<")
575: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
576: "TARGET_32081"
577: "truncld %1,%0")
578:
579: ;; Unsigned
580:
581: (define_insn "fixunssfqi2"
582: [(set (match_operand:QI 0 "general_operand" "=g<")
583: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
584: "TARGET_32081"
585: "truncfb %1,%0")
586:
587: (define_insn "fixunssfhi2"
588: [(set (match_operand:HI 0 "general_operand" "=g<")
589: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
590: "TARGET_32081"
591: "truncfw %1,%0")
592:
593: (define_insn "fixunssfsi2"
594: [(set (match_operand:SI 0 "general_operand" "=g<")
595: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
596: "TARGET_32081"
597: "truncfd %1,%0")
598:
599: (define_insn "fixunsdfqi2"
600: [(set (match_operand:QI 0 "general_operand" "=g<")
601: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
602: "TARGET_32081"
603: "trunclb %1,%0")
604:
605: (define_insn "fixunsdfhi2"
606: [(set (match_operand:HI 0 "general_operand" "=g<")
607: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
608: "TARGET_32081"
609: "trunclw %1,%0")
610:
611: (define_insn "fixunsdfsi2"
612: [(set (match_operand:SI 0 "general_operand" "=g<")
613: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
614: "TARGET_32081"
615: "truncld %1,%0")
616:
617: ;;; These are not yet used by GCC
618: (define_insn "fix_truncsfqi2"
619: [(set (match_operand:QI 0 "general_operand" "=g<")
620: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
621: "TARGET_32081"
622: "truncfb %1,%0")
623:
624: (define_insn "fix_truncsfhi2"
625: [(set (match_operand:HI 0 "general_operand" "=g<")
626: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
627: "TARGET_32081"
628: "truncfw %1,%0")
629:
630: (define_insn "fix_truncsfsi2"
631: [(set (match_operand:SI 0 "general_operand" "=g<")
632: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
633: "TARGET_32081"
634: "truncfd %1,%0")
635:
636: (define_insn "fix_truncdfqi2"
637: [(set (match_operand:QI 0 "general_operand" "=g<")
638: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
639: "TARGET_32081"
640: "trunclb %1,%0")
641:
642: (define_insn "fix_truncdfhi2"
643: [(set (match_operand:HI 0 "general_operand" "=g<")
644: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
645: "TARGET_32081"
646: "trunclw %1,%0")
647:
648: (define_insn "fix_truncdfsi2"
649: [(set (match_operand:SI 0 "general_operand" "=g<")
650: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
651: "TARGET_32081"
652: "truncld %1,%0")
653:
654: ;;- All kinds of add instructions.
655:
656: (define_insn "adddf3"
657: [(set (match_operand:DF 0 "general_operand" "=fm")
658: (plus:DF (match_operand:DF 1 "general_operand" "%0")
659: (match_operand:DF 2 "general_operand" "fmF")))]
660: "TARGET_32081"
661: "addl %2,%0")
662:
663:
664: (define_insn "addsf3"
665: [(set (match_operand:SF 0 "general_operand" "=fm")
666: (plus:SF (match_operand:SF 1 "general_operand" "%0")
667: (match_operand:SF 2 "general_operand" "fmF")))]
668: "TARGET_32081"
669: "addf %2,%0")
670:
671: (define_insn ""
672: [(set (reg:SI 17)
673: (plus:SI (reg:SI 17)
674: (match_operand:SI 0 "immediate_operand" "i")))]
675: "GET_CODE (operands[0]) == CONST_INT"
676: "*
677: {
1.1.1.6 root 678: #if defined(ns32532)
679: if (INTVAL(operands[0]) == 8)
680: return \"cmpd tos,tos # adjsp -8\";
681: #endif
682: #if defined(ns32532) || defined(ns32332)
683: if (INTVAL(operands[0]) == 4)
684: return \"cmpqd %$0,tos # adjsp -4\";
685: #endif
1.1 root 686: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
687: return \"adjspb %$%n0\";
688: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
689: return \"adjspw %$%n0\";
690: return \"adjspd %$%n0\";
691: }")
692:
693: (define_insn ""
694: [(set (match_operand:SI 0 "general_operand" "=g<")
695: (plus:SI (reg:SI 16)
696: (match_operand:SI 1 "immediate_operand" "i")))]
697: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 698: "addr %c1(fp),%0")
1.1 root 699:
700: (define_insn ""
701: [(set (match_operand:SI 0 "general_operand" "=g<")
702: (plus:SI (reg:SI 17)
703: (match_operand:SI 1 "immediate_operand" "i")))]
704: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 705: "addr %c1(sp),%0")
1.1 root 706:
707: (define_insn "addsi3"
1.1.1.9 root 708: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
709: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
710: (match_operand:SI 2 "general_operand" "rmn,n")))]
1.1 root 711: ""
712: "*
713: {
1.1.1.9 root 714: if (which_alternative == 1)
715: return \"addr %c2(%1),%0\";
1.1 root 716: if (GET_CODE (operands[2]) == CONST_INT)
717: {
718: int i = INTVAL (operands[2]);
719:
720: if (i <= 7 && i >= -8)
721: return \"addqd %2,%0\";
722: else if (GET_CODE (operands[0]) == REG
723: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 724: return \"addr %c2(%0),%0\";
1.1 root 725: }
726: return \"addd %2,%0\";
727: }")
728:
729: (define_insn "addhi3"
730: [(set (match_operand:HI 0 "general_operand" "=g")
731: (plus:HI (match_operand:HI 1 "general_operand" "%0")
732: (match_operand:HI 2 "general_operand" "g")))]
733: ""
734: "*
735: { if (GET_CODE (operands[2]) == CONST_INT)
736: {
737: int i = INTVAL (operands[2]);
738: if (i <= 7 && i >= -8)
739: return \"addqw %2,%0\";
740: }
741: return \"addw %2,%0\";
742: }")
743:
744: (define_insn ""
745: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
746: (plus:HI (match_operand:HI 1 "general_operand" "0")
747: (match_operand:HI 2 "general_operand" "g")))]
748: ""
749: "*
750: {
751: if (GET_CODE (operands[1]) == CONST_INT
752: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
753: return \"addqw %1,%0\";
754: return \"addw %1,%0\";
755: }")
756:
757: (define_insn "addqi3"
758: [(set (match_operand:QI 0 "general_operand" "=g")
759: (plus:QI (match_operand:QI 1 "general_operand" "%0")
760: (match_operand:QI 2 "general_operand" "g")))]
761: ""
762: "*
763: { if (GET_CODE (operands[2]) == CONST_INT)
764: {
765: int i = INTVAL (operands[2]);
766: if (i <= 7 && i >= -8)
767: return \"addqb %2,%0\";
768: }
769: return \"addb %2,%0\";
770: }")
771:
772: (define_insn ""
773: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
774: (plus:QI (match_operand:QI 1 "general_operand" "0")
775: (match_operand:QI 2 "general_operand" "g")))]
776: ""
777: "*
778: {
779: if (GET_CODE (operands[1]) == CONST_INT
780: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
781: return \"addqb %1,%0\";
782: return \"addb %1,%0\";
783: }")
784:
785: ;;- All kinds of subtract instructions.
786:
787: (define_insn "subdf3"
788: [(set (match_operand:DF 0 "general_operand" "=fm")
789: (minus:DF (match_operand:DF 1 "general_operand" "0")
790: (match_operand:DF 2 "general_operand" "fmF")))]
791: "TARGET_32081"
792: "subl %2,%0")
793:
794: (define_insn "subsf3"
795: [(set (match_operand:SF 0 "general_operand" "=fm")
796: (minus:SF (match_operand:SF 1 "general_operand" "0")
797: (match_operand:SF 2 "general_operand" "fmF")))]
798: "TARGET_32081"
799: "subf %2,%0")
800:
801: (define_insn ""
802: [(set (reg:SI 17)
803: (minus:SI (reg:SI 17)
804: (match_operand:SI 0 "immediate_operand" "i")))]
805: "GET_CODE (operands[0]) == CONST_INT"
806: "*
807: {
808: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
809: && INTVAL(operands[0]) > -64)
810: return \"adjspb %0\";
811: return \"adjspd %0\";
812: }")
813:
814: (define_insn "subsi3"
815: [(set (match_operand:SI 0 "general_operand" "=g")
816: (minus:SI (match_operand:SI 1 "general_operand" "0")
817: (match_operand:SI 2 "general_operand" "rmn")))]
818: ""
819: "*
820: { if (GET_CODE (operands[2]) == CONST_INT)
821: {
822: int i = INTVAL (operands[2]);
823:
824: if (i <= 8 && i >= -7)
825: return \"addqd %$%n2,%0\";
826: }
827: return \"subd %2,%0\";
828: }")
829:
830: (define_insn "subhi3"
831: [(set (match_operand:HI 0 "general_operand" "=g")
832: (minus:HI (match_operand:HI 1 "general_operand" "0")
833: (match_operand:HI 2 "general_operand" "g")))]
834: ""
835: "*
836: { if (GET_CODE (operands[2]) == CONST_INT)
837: {
838: int i = INTVAL (operands[2]);
839:
840: if (i <= 8 && i >= -7)
841: return \"addqw %$%n2,%0\";
842: }
843: return \"subw %2,%0\";
844: }")
845:
846: (define_insn ""
847: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
848: (minus:HI (match_operand:HI 1 "general_operand" "0")
849: (match_operand:HI 2 "general_operand" "g")))]
850: ""
851: "*
852: {
853: if (GET_CODE (operands[1]) == CONST_INT
854: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
855: return \"addqw %$%n1,%0\";
856: return \"subw %1,%0\";
857: }")
858:
859: (define_insn "subqi3"
860: [(set (match_operand:QI 0 "general_operand" "=g")
861: (minus:QI (match_operand:QI 1 "general_operand" "0")
862: (match_operand:QI 2 "general_operand" "g")))]
863: ""
864: "*
865: { if (GET_CODE (operands[2]) == CONST_INT)
866: {
867: int i = INTVAL (operands[2]);
868:
869: if (i <= 8 && i >= -7)
870: return \"addqb %$%n2,%0\";
871: }
872: return \"subb %2,%0\";
873: }")
874:
875: (define_insn ""
876: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
877: (minus:QI (match_operand:QI 1 "general_operand" "0")
878: (match_operand:QI 2 "general_operand" "g")))]
879: ""
880: "*
881: {
882: if (GET_CODE (operands[1]) == CONST_INT
883: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
884: return \"addqb %$%n1,%0\";
885: return \"subb %1,%0\";
886: }")
887:
888: ;;- Multiply instructions.
889:
890: (define_insn "muldf3"
891: [(set (match_operand:DF 0 "general_operand" "=fm")
892: (mult:DF (match_operand:DF 1 "general_operand" "%0")
893: (match_operand:DF 2 "general_operand" "fmF")))]
894: "TARGET_32081"
895: "mull %2,%0")
896:
897: (define_insn "mulsf3"
898: [(set (match_operand:SF 0 "general_operand" "=fm")
899: (mult:SF (match_operand:SF 1 "general_operand" "%0")
900: (match_operand:SF 2 "general_operand" "fmF")))]
901: "TARGET_32081"
902: "mulf %2,%0")
903:
904: (define_insn "mulsi3"
905: [(set (match_operand:SI 0 "general_operand" "=g")
906: (mult:SI (match_operand:SI 1 "general_operand" "%0")
907: (match_operand:SI 2 "general_operand" "rmn")))]
908: ""
909: "muld %2,%0")
910:
911: (define_insn "mulhi3"
912: [(set (match_operand:HI 0 "general_operand" "=g")
913: (mult:HI (match_operand:HI 1 "general_operand" "%0")
914: (match_operand:HI 2 "general_operand" "g")))]
915: ""
916: "mulw %2,%0")
917:
918: (define_insn "mulqi3"
919: [(set (match_operand:QI 0 "general_operand" "=g")
920: (mult:QI (match_operand:QI 1 "general_operand" "%0")
921: (match_operand:QI 2 "general_operand" "g")))]
922: ""
923: "mulb %2,%0")
924:
925: (define_insn "umulsi3"
926: [(set (match_operand:SI 0 "general_operand" "=g")
927: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 928: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 929: ""
930: "muld %2,%0")
931:
932: (define_insn "umulhi3"
933: [(set (match_operand:HI 0 "general_operand" "=g")
934: (umult:HI (match_operand:HI 1 "general_operand" "%0")
935: (match_operand:HI 2 "general_operand" "g")))]
936: ""
937: "mulw %2,%0")
938:
939: (define_insn "umulqi3"
940: [(set (match_operand:QI 0 "general_operand" "=g")
941: (umult:QI (match_operand:QI 1 "general_operand" "%0")
942: (match_operand:QI 2 "general_operand" "g")))]
943: ""
944: "mulb %2,%0")
945:
946: (define_insn "umulsidi3"
947: [(set (match_operand:DI 0 "general_operand" "=g")
948: (umult:DI (match_operand:SI 1 "general_operand" "0")
949: (match_operand:SI 2 "general_operand" "rmn")))]
950: ""
951: "meid %2,%0")
952:
953: ;;- Divide instructions.
954:
955: (define_insn "divdf3"
956: [(set (match_operand:DF 0 "general_operand" "=fm")
957: (div:DF (match_operand:DF 1 "general_operand" "0")
958: (match_operand:DF 2 "general_operand" "fmF")))]
959: "TARGET_32081"
960: "divl %2,%0")
961:
962: (define_insn "divsf3"
963: [(set (match_operand:SF 0 "general_operand" "=fm")
964: (div:SF (match_operand:SF 1 "general_operand" "0")
965: (match_operand:SF 2 "general_operand" "fmF")))]
966: "TARGET_32081"
967: "divf %2,%0")
968:
969: (define_insn "divsi3"
970: [(set (match_operand:SI 0 "general_operand" "=g")
971: (div:SI (match_operand:SI 1 "general_operand" "0")
972: (match_operand:SI 2 "general_operand" "rmn")))]
973: ""
974: "quod %2,%0")
975:
976: (define_insn "divhi3"
977: [(set (match_operand:HI 0 "general_operand" "=g")
978: (div:HI (match_operand:HI 1 "general_operand" "0")
979: (match_operand:HI 2 "general_operand" "g")))]
980: ""
981: "quow %2,%0")
982:
983: (define_insn "divqi3"
984: [(set (match_operand:QI 0 "general_operand" "=g")
985: (div:QI (match_operand:QI 1 "general_operand" "0")
986: (match_operand:QI 2 "general_operand" "g")))]
987: ""
988: "quob %2,%0")
989:
990: (define_insn "udivsi3"
991: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 992: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 993: (match_operand:SI 2 "general_operand" "rmn")))]
994: ""
995: "*
996: {
997: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
998: return \"deid %2,%0\;movd %1,%0\";
999: }")
1000:
1001: (define_insn "udivhi3"
1002: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1003: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1004: (match_operand:HI 2 "general_operand" "g")))]
1005: ""
1006: "*
1007: {
1008: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1009: return \"deiw %2,%0\;movw %1,%0\";
1010: }")
1011:
1012: (define_insn "udivqi3"
1013: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1014: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1015: (match_operand:QI 2 "general_operand" "g")))]
1016: ""
1017: "*
1018: {
1019: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1020: return \"deib %2,%0\;movb %1,%0\";
1021: }")
1022:
1023: ;; Remainder instructions.
1024:
1025: (define_insn "modsi3"
1026: [(set (match_operand:SI 0 "general_operand" "=g")
1027: (mod:SI (match_operand:SI 1 "general_operand" "0")
1028: (match_operand:SI 2 "general_operand" "rmn")))]
1029: ""
1030: "remd %2,%0")
1031:
1032: (define_insn "modhi3"
1033: [(set (match_operand:HI 0 "general_operand" "=g")
1034: (mod:HI (match_operand:HI 1 "general_operand" "0")
1035: (match_operand:HI 2 "general_operand" "g")))]
1036: ""
1037: "remw %2,%0")
1038:
1039: (define_insn "modqi3"
1040: [(set (match_operand:QI 0 "general_operand" "=g")
1041: (mod:QI (match_operand:QI 1 "general_operand" "0")
1042: (match_operand:QI 2 "general_operand" "g")))]
1043: ""
1044: "remb %2,%0")
1045:
1046: (define_insn "umodsi3"
1047: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1048: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1049: (match_operand:SI 2 "general_operand" "rmn")))]
1050: ""
1051: "deid %2,%0")
1052:
1053: (define_insn "umodhi3"
1054: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1055: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1056: (match_operand:HI 2 "general_operand" "g")))]
1057: ""
1058: "deiw %2,%0")
1059:
1060: (define_insn "umodqi3"
1061: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1062: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1063: (match_operand:QI 2 "general_operand" "g")))]
1064: ""
1065: "deib %2,%0")
1066:
1067: ; This isn't be usable in its current form.
1068: ;(define_insn "udivmoddisi4"
1069: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1070: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1071: ; (match_operand:SI 2 "general_operand" "rmn")))
1072: ; (set (subreg:SI (match_dup 0) 0)
1073: ; (umod:SI (match_dup 1) (match_dup 2)))]
1074: ; ""
1075: ; "deid %2,%0")
1076:
1077: ;;- Logical Instructions: AND
1078:
1079: (define_insn "andsi3"
1080: [(set (match_operand:SI 0 "general_operand" "=g")
1081: (and:SI (match_operand:SI 1 "general_operand" "%0")
1082: (match_operand:SI 2 "general_operand" "rmn")))]
1083: ""
1084: "*
1085: {
1.1.1.9 root 1086: if (GET_CODE (operands[2]) == CONST_INT)
1087: {
1088: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1089: {
1090: if (INTVAL (operands[2]) == 0xffffff00)
1091: return \"movqb %$0,%0\";
1092: else
1093: {
1094: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1095: INTVAL (operands[2]) & 0xff);
1096: return \"andb %2,%0\";
1097: }
1098: }
1099: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1100: {
1101: if (INTVAL (operands[2]) == 0xffff0000)
1102: return \"movqw %$0,%0\";
1103: else
1104: {
1105: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1106: INTVAL (operands[2]) & 0xffff);
1107: return \"andw %2,%0\";
1108: }
1109: }
1110: }
1.1 root 1111: return \"andd %2,%0\";
1112: }")
1113:
1114: (define_insn "andhi3"
1115: [(set (match_operand:HI 0 "general_operand" "=g")
1116: (and:HI (match_operand:HI 1 "general_operand" "%0")
1117: (match_operand:HI 2 "general_operand" "g")))]
1118: ""
1119: "*
1120: {
1121: if (GET_CODE (operands[2]) == CONST_INT
1122: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1.1.1.9 root 1123: {
1124: if (INTVAL (operands[2]) == 0xffffff00)
1125: return \"movqb %$0,%0\";
1126: else
1127: {
1128: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1129: INTVAL (operands[2]) & 0xff);
1130: return \"andb %2,%0\";
1131: }
1.1 root 1132: }
1133: return \"andw %2,%0\";
1134: }")
1135:
1136: (define_insn "andqi3"
1137: [(set (match_operand:QI 0 "general_operand" "=g")
1138: (and:QI (match_operand:QI 1 "general_operand" "%0")
1139: (match_operand:QI 2 "general_operand" "g")))]
1140: ""
1141: "andb %2,%0")
1142:
1143: (define_insn "andcbsi3"
1144: [(set (match_operand:SI 0 "general_operand" "=g")
1145: (and:SI (match_operand:SI 1 "general_operand" "0")
1146: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1147: ""
1148: "*
1149: {
1150: if (GET_CODE (operands[2]) == CONST_INT)
1151: {
1152: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1153: return \"bicb %2,%0\";
1154: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1155: return \"bicw %2,%0\";
1156: }
1157: return \"bicd %2,%0\";
1158: }")
1159:
1160: (define_insn ""
1161: [(set (match_operand:SI 0 "general_operand" "=g")
1162: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1163: (match_operand:SI 2 "general_operand" "0")))]
1164: ""
1165: "*
1166: {
1167: if (GET_CODE (operands[1]) == CONST_INT)
1168: {
1169: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1170: return \"bicb %1,%0\";
1171: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1172: return \"bicw %1,%0\";
1173: }
1174: return \"bicd %1,%0\";
1175: }")
1176:
1177: (define_insn "andcbhi3"
1178: [(set (match_operand:HI 0 "general_operand" "=g")
1179: (and:HI (match_operand:HI 1 "general_operand" "%0")
1180: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1181: ""
1182: "*
1183: {
1184: if (GET_CODE (operands[2]) == CONST_INT
1185: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1186: return \"bicb %2,%0\";
1187: return \"bicw %2,%0\";
1188: }")
1189:
1190: (define_insn ""
1191: [(set (match_operand:HI 0 "general_operand" "=g")
1192: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1193: (match_operand:HI 2 "general_operand" "0")))]
1194: ""
1195: "*
1196: {
1197: if (GET_CODE (operands[1]) == CONST_INT
1198: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1199: return \"bicb %1,%0\";
1200: return \"bicw %1,%0\";
1201: }")
1202:
1203: (define_insn "andcbqi3"
1204: [(set (match_operand:QI 0 "general_operand" "=g")
1205: (and:QI (match_operand:QI 1 "general_operand" "%0")
1206: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1207: ""
1208: "bicb %2,%0")
1209:
1210: (define_insn ""
1211: [(set (match_operand:QI 0 "general_operand" "=g")
1212: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1213: (match_operand:QI 2 "general_operand" "0")))]
1214: ""
1215: "bicb %1,%0")
1216:
1217: ;;- Bit set instructions.
1218:
1219: (define_insn "iorsi3"
1220: [(set (match_operand:SI 0 "general_operand" "=g")
1221: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1222: (match_operand:SI 2 "general_operand" "rmn")))]
1223: ""
1224: "*
1225: {
1226: if (GET_CODE (operands[2]) == CONST_INT) {
1227: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1228: return \"orb %2,%0\";
1229: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1230: return \"orw %2,%0\";
1231: }
1232: return \"ord %2,%0\";
1233: }")
1234:
1235: (define_insn "iorhi3"
1236: [(set (match_operand:HI 0 "general_operand" "=g")
1237: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1238: (match_operand:HI 2 "general_operand" "g")))]
1239: ""
1240: "*
1241: {
1242: if (GET_CODE(operands[2]) == CONST_INT &&
1243: (INTVAL(operands[2]) & 0xffffff00) == 0)
1244: return \"orb %2,%0\";
1245: return \"orw %2,%0\";
1246: }")
1247:
1248: (define_insn "iorqi3"
1249: [(set (match_operand:QI 0 "general_operand" "=g")
1250: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1251: (match_operand:QI 2 "general_operand" "g")))]
1252: ""
1253: "orb %2,%0")
1254:
1255: ;;- xor instructions.
1256:
1257: (define_insn "xorsi3"
1258: [(set (match_operand:SI 0 "general_operand" "=g")
1259: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1260: (match_operand:SI 2 "general_operand" "rmn")))]
1261: ""
1262: "*
1263: {
1264: if (GET_CODE (operands[2]) == CONST_INT) {
1265: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1266: return \"xorb %2,%0\";
1267: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1268: return \"xorw %2,%0\";
1269: }
1270: return \"xord %2,%0\";
1271: }")
1272:
1273: (define_insn "xorhi3"
1274: [(set (match_operand:HI 0 "general_operand" "=g")
1275: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1276: (match_operand:HI 2 "general_operand" "g")))]
1277: ""
1278: "*
1279: {
1280: if (GET_CODE(operands[2]) == CONST_INT &&
1281: (INTVAL(operands[2]) & 0xffffff00) == 0)
1282: return \"xorb %2,%0\";
1283: return \"xorw %2,%0\";
1284: }")
1285:
1286: (define_insn "xorqi3"
1287: [(set (match_operand:QI 0 "general_operand" "=g")
1288: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1289: (match_operand:QI 2 "general_operand" "g")))]
1290: ""
1291: "xorb %2,%0")
1292:
1293: (define_insn "negdf2"
1294: [(set (match_operand:DF 0 "general_operand" "=fm<")
1295: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1296: "TARGET_32081"
1297: "negl %1,%0")
1298:
1299: (define_insn "negsf2"
1300: [(set (match_operand:SF 0 "general_operand" "=fm<")
1301: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1302: "TARGET_32081"
1303: "negf %1,%0")
1304:
1305: (define_insn "negsi2"
1306: [(set (match_operand:SI 0 "general_operand" "=g<")
1307: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1308: ""
1309: "negd %1,%0")
1310:
1311: (define_insn "neghi2"
1312: [(set (match_operand:HI 0 "general_operand" "=g<")
1313: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1314: ""
1315: "negw %1,%0")
1316:
1317: (define_insn "negqi2"
1318: [(set (match_operand:QI 0 "general_operand" "=g<")
1319: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1320: ""
1321: "negb %1,%0")
1322:
1323: (define_insn "one_cmplsi2"
1324: [(set (match_operand:SI 0 "general_operand" "=g<")
1325: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1326: ""
1327: "comd %1,%0")
1328:
1329: (define_insn "one_cmplhi2"
1330: [(set (match_operand:HI 0 "general_operand" "=g<")
1331: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1332: ""
1333: "comw %1,%0")
1334:
1335: (define_insn "one_cmplqi2"
1336: [(set (match_operand:QI 0 "general_operand" "=g<")
1337: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1338: ""
1339: "comb %1,%0")
1340:
1341: ;; arithmetic left and right shift operations
1342:
1343: (define_insn "ashlsi3"
1344: [(set (match_operand:SI 0 "general_operand" "=g,g")
1345: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1346: (match_operand:SI 2 "general_operand" "I,rmn")))]
1347: ""
1.1.1.2 root 1348: "* output_shift_insn (operands);")
1.1 root 1349:
1350: (define_insn ""
1351: [(set (match_operand:SI 0 "general_operand" "=g")
1352: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1353: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1354: (const_int 31))))]
1355: ""
1356: "ashd %2,%0")
1357:
1358: (define_insn "ashlhi3"
1359: [(set (match_operand:HI 0 "general_operand" "=g")
1360: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1361: (match_operand:SI 2 "general_operand" "rmn")))]
1362: ""
1363: "*
1364: { if (GET_CODE (operands[2]) == CONST_INT)
1365: if (INTVAL (operands[2]) == 1)
1366: return \"addw %1,%0\";
1367: else if (INTVAL (operands[2]) == 2)
1368: return \"addw %1,%0\;addw %0,%0\";
1369: return \"ashw %2,%0\";
1370: }")
1371:
1372: (define_insn "ashlqi3"
1373: [(set (match_operand:QI 0 "general_operand" "=g")
1374: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1375: (match_operand:SI 2 "general_operand" "rmn")))]
1376: ""
1377: "*
1378: { if (GET_CODE (operands[2]) == CONST_INT)
1379: if (INTVAL (operands[2]) == 1)
1380: return \"addb %1,%0\";
1381: else if (INTVAL (operands[2]) == 2)
1382: return \"addb %1,%0\;addb %0,%0\";
1383: return \"ashb %2,%0\";
1384: }")
1385:
1.1.1.6 root 1386: ;; Arithmetic right shift on the 32k works by negating the shift count.
1387: (define_expand "ashrsi3"
1388: [(set (match_operand:SI 0 "general_operand" "=g")
1389: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1390: (match_operand:SI 2 "general_operand" "g")))]
1391: ""
1392: "
1393: {
1.1.1.7 root 1394: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1395: }")
1396:
1397: (define_expand "ashrhi3"
1398: [(set (match_operand:HI 0 "general_operand" "=g")
1399: (ashift:HI (match_operand:HI 1 "general_operand" "g")
1400: (match_operand:SI 2 "general_operand" "g")))]
1401: ""
1402: "
1403: {
1.1.1.7 root 1404: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1405: }")
1406:
1407: (define_expand "ashrqi3"
1408: [(set (match_operand:QI 0 "general_operand" "=g")
1409: (ashift:QI (match_operand:QI 1 "general_operand" "g")
1410: (match_operand:SI 2 "general_operand" "g")))]
1411: ""
1412: "
1413: {
1.1.1.7 root 1414: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1415: }")
1416:
1.1 root 1417: ;; logical shift instructions
1418:
1419: (define_insn "lshlsi3"
1420: [(set (match_operand:SI 0 "general_operand" "=g")
1421: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1422: (match_operand:SI 2 "general_operand" "rmn")))]
1423: ""
1424: "lshd %2,%0")
1425:
1426: (define_insn ""
1427: [(set (match_operand:SI 0 "general_operand" "=g")
1428: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1429: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1430: (const_int 31))))]
1431: ""
1432: "lshd %2,%0")
1433:
1434: (define_insn "lshlhi3"
1435: [(set (match_operand:HI 0 "general_operand" "=g")
1436: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1437: (match_operand:SI 2 "general_operand" "rmn")))]
1438: ""
1439: "lshw %2,%0")
1440:
1441: (define_insn "lshlqi3"
1442: [(set (match_operand:QI 0 "general_operand" "=g")
1443: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1444: (match_operand:SI 2 "general_operand" "rmn")))]
1445: ""
1446: "lshb %2,%0")
1447:
1.1.1.6 root 1448: ;; Logical right shift on the 32k works by negating the shift count.
1449: (define_expand "lshrsi3"
1450: [(set (match_operand:SI 0 "general_operand" "=g")
1451: (lshift:SI (match_operand:SI 1 "general_operand" "g")
1452: (match_operand:SI 2 "general_operand" "g")))]
1453: ""
1454: "
1455: {
1.1.1.7 root 1456: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1457: }")
1458:
1459: (define_expand "lshrhi3"
1460: [(set (match_operand:HI 0 "general_operand" "=g")
1461: (lshift:HI (match_operand:HI 1 "general_operand" "g")
1462: (match_operand:SI 2 "general_operand" "g")))]
1463: ""
1464: "
1465: {
1.1.1.7 root 1466: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1467: }")
1468:
1469: (define_expand "lshrqi3"
1470: [(set (match_operand:QI 0 "general_operand" "=g")
1471: (lshift:QI (match_operand:QI 1 "general_operand" "g")
1472: (match_operand:SI 2 "general_operand" "g")))]
1473: ""
1474: "
1475: {
1.1.1.7 root 1476: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1477: }")
1478:
1.1 root 1479: ;; Rotate instructions
1480:
1481: (define_insn "rotlsi3"
1482: [(set (match_operand:SI 0 "general_operand" "=g")
1483: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1484: (match_operand:SI 2 "general_operand" "rmn")))]
1485: ""
1486: "rotd %2,%0")
1487:
1488: (define_insn "rotlhi3"
1489: [(set (match_operand:HI 0 "general_operand" "=g")
1490: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1491: (match_operand:SI 2 "general_operand" "rmn")))]
1492: ""
1493: "rotw %2,%0")
1494:
1495: (define_insn "rotlqi3"
1496: [(set (match_operand:QI 0 "general_operand" "=g")
1497: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1498: (match_operand:SI 2 "general_operand" "rmn")))]
1499: ""
1500: "rotb %2,%0")
1.1.1.6 root 1501:
1502: ;; Right rotate on the 32k works by negating the shift count.
1503: (define_expand "rotrsi3"
1504: [(set (match_operand:SI 0 "general_operand" "=g")
1505: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1506: (match_operand:SI 2 "general_operand" "g")))]
1507: ""
1508: "
1509: {
1.1.1.7 root 1510: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1511: }")
1512:
1513: (define_expand "rotrhi3"
1514: [(set (match_operand:HI 0 "general_operand" "=g")
1515: (rotate:HI (match_operand:HI 1 "general_operand" "g")
1516: (match_operand:SI 2 "general_operand" "g")))]
1517: ""
1518: "
1519: {
1.1.1.7 root 1520: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1521: }")
1522:
1523: (define_expand "rotrqi3"
1524: [(set (match_operand:QI 0 "general_operand" "=g")
1525: (rotate:QI (match_operand:QI 1 "general_operand" "g")
1526: (match_operand:SI 2 "general_operand" "g")))]
1527: ""
1528: "
1529: {
1.1.1.7 root 1530: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1531: }")
1.1 root 1532:
1533: ;;- load or push effective address
1534: ;; These come after the move, add, and multiply patterns
1535: ;; because we don't want pushl $1 turned into pushad 1.
1536:
1537: (define_insn ""
1538: [(set (match_operand:SI 0 "general_operand" "=g<")
1539: (match_operand:QI 1 "address_operand" "p"))]
1540: ""
1.1.1.2 root 1541: "*
1542: {
1543: if (REG_P (operands[0])
1544: && GET_CODE (operands[1]) == MULT
1545: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1546: && (INTVAL (XEXP (operands[1], 1)) == 2
1547: || INTVAL (XEXP (operands[1], 1)) == 4))
1548: {
1549: rtx xoperands[3];
1550: xoperands[0] = operands[0];
1551: xoperands[1] = XEXP (operands[1], 0);
1552: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1553: return output_shift_insn (xoperands);
1554: }
1555: return \"addr %a1,%0\";
1556: }")
1.1 root 1557:
1558: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1559: ;;; but slower then using power-of-2 shifts if we can use them
1560: ;
1561: ;(define_insn ""
1562: ; [(set (match_operand:SI 0 "register_operand" "=r")
1563: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1564: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1565: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1566: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1567: ; "indexd %0,%3,%1")
1568: ;
1569: ;(define_insn ""
1570: ; [(set (match_operand:SI 0 "register_operand" "=r")
1571: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1572: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1573: ; (match_operand:SI 3 "general_operand" "rmn")))]
1574: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1575: ; "indexd %0,%2,%3")
1576:
1577: ;; Set, Clear, and Invert bit
1578:
1579: (define_insn ""
1580: [(set (match_operand:SI 0 "general_operand" "=g")
1581: (ior:SI
1582: (ashift:SI (const_int 1)
1583: (match_operand:SI 1 "general_operand" "rmn"))
1584: (match_dup 0)))]
1585: ""
1586: "sbitd %1,%0")
1587:
1588: (define_insn ""
1589: [(set (match_operand:SI 0 "general_operand" "=g")
1590: (ior:SI
1591: (match_dup 0)
1592: (ashift:SI (const_int 1)
1593: (match_operand:SI 1 "general_operand" "rmn"))))]
1594: ""
1595: "sbitd %1,%0")
1596:
1597: (define_insn ""
1598: [(set (match_operand:QI 0 "general_operand" "=g")
1599: (ior:QI
1600: (subreg:QI
1601: (ashift:SI (const_int 1)
1602: (match_operand:QI 1 "general_operand" "rmn")) 0)
1603: (match_dup 0)))]
1604: ""
1605: "sbitb %1,%0")
1606:
1607: (define_insn ""
1608: [(set (match_operand:QI 0 "general_operand" "=g")
1609: (ior:QI
1610: (match_dup 0)
1611: (subreg:QI
1612: (ashift:SI (const_int 1)
1613: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1614: ""
1615: "sbitb %1,%0")
1616:
1617: (define_insn ""
1618: [(set (match_operand:SI 0 "general_operand" "=g")
1619: (and:SI
1620: (not:SI
1621: (ashift:SI (const_int 1)
1622: (match_operand:SI 1 "general_operand" "rmn")))
1623: (match_dup 0)))]
1624: ""
1625: "cbitd %1,%0")
1626:
1627: (define_insn ""
1628: [(set (match_operand:SI 0 "general_operand" "=g")
1629: (and:SI
1630: (match_dup 0)
1631: (not:SI
1632: (ashift:SI (const_int 1)
1633: (match_operand:SI 1 "general_operand" "rmn")))))]
1634: ""
1635: "cbitd %1,%0")
1636:
1637: (define_insn ""
1638: [(set (match_operand:QI 0 "general_operand" "=g")
1639: (and:QI
1640: (subreg:QI
1641: (not:SI
1642: (ashift:SI (const_int 1)
1643: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1644: (match_dup 0)))]
1645: ""
1646: "cbitb %1,%0")
1647:
1648: (define_insn ""
1649: [(set (match_operand:QI 0 "general_operand" "=g")
1650: (and:QI
1651: (match_dup 0)
1652: (subreg:QI
1653: (not:SI
1654: (ashift:SI (const_int 1)
1655: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1656: ""
1657: "cbitb %1,%0")
1658:
1659: (define_insn ""
1660: [(set (match_operand:SI 0 "general_operand" "=g")
1661: (xor:SI
1662: (ashift:SI (const_int 1)
1663: (match_operand:SI 1 "general_operand" "rmn"))
1664: (match_dup 0)))]
1665: ""
1666: "ibitd %1,%0")
1667:
1668: (define_insn ""
1669: [(set (match_operand:SI 0 "general_operand" "=g")
1670: (xor:SI
1671: (match_dup 0)
1672: (ashift:SI (const_int 1)
1673: (match_operand:SI 1 "general_operand" "rmn"))))]
1674: ""
1675: "ibitd %1,%0")
1676:
1677: (define_insn ""
1678: [(set (match_operand:QI 0 "general_operand" "=g")
1679: (xor:QI
1680: (subreg:QI
1681: (ashift:SI (const_int 1)
1682: (match_operand:QI 1 "general_operand" "rmn")) 0)
1683: (match_dup 0)))]
1684: ""
1685: "ibitb %1,%0")
1686:
1687: (define_insn ""
1688: [(set (match_operand:QI 0 "general_operand" "=g")
1689: (xor:QI
1690: (match_dup 0)
1691: (subreg:QI
1692: (ashift:SI (const_int 1)
1693: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1694: ""
1695: "ibitb %1,%0")
1696:
1697: ;; Recognize jbs and jbc instructions.
1698:
1699: (define_insn ""
1700: [(set (cc0)
1.1.1.7 root 1701: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1.1 root 1702: (const_int 1)
1703: (match_operand:SI 1 "general_operand" "rmn")))]
1704: ""
1705: "*
1706: { cc_status.flags = CC_Z_IN_F;
1707: return \"tbitd %1,%0\";
1708: }")
1709:
1710: (define_insn ""
1711: [(set (cc0)
1.1.1.7 root 1712: (minus (zero_extract (match_operand:SI 0 "general_operand" "rm")
1.1 root 1713: (const_int 1)
1714: (match_operand:SI 1 "general_operand" "rmn"))
1715: (const_int 1)))]
1716: ""
1717: "*
1718: { cc_status.flags = CC_Z_IN_NOT_F;
1719: return \"tbitd %1,%0\";
1720: }")
1721:
1722: (define_insn ""
1723: [(set (cc0)
1724: (zero_extract (match_operand:HI 0 "general_operand" "g")
1725: (const_int 1)
1726: (match_operand:HI 1 "general_operand" "g")))]
1727: ""
1728: "*
1729: { cc_status.flags = CC_Z_IN_F;
1730: return \"tbitw %1,%0\";
1731: }")
1732:
1733: (define_insn ""
1734: [(set (cc0)
1735: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1736: (const_int 1)
1737: (match_operand:HI 1 "general_operand" "rmn"))
1738: (const_int 1)))]
1739: ""
1740: "*
1741: { cc_status.flags = CC_Z_IN_NOT_F;
1742: return \"tbitw %1,%0\";
1743: }")
1744:
1745: (define_insn ""
1746: [(set (cc0)
1747: (zero_extract (match_operand:QI 0 "general_operand" "g")
1748: (const_int 1)
1749: (match_operand:QI 1 "general_operand" "g")))]
1750: ""
1751: "*
1752: { cc_status.flags = CC_Z_IN_F;
1753: return \"tbitb %1,%0\";
1754: }")
1755:
1756: (define_insn ""
1757: [(set (cc0)
1758: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1759: (const_int 1)
1760: (match_operand:QI 1 "general_operand" "rmn"))
1761: (const_int 1)))]
1762: ""
1763: "*
1764: { cc_status.flags = CC_Z_IN_NOT_F;
1765: return \"tbitb %1,%0\";
1766: }")
1767:
1768: (define_insn ""
1769: [(set (cc0)
1.1.1.7 root 1770: (and:SI (match_operand:SI 0 "general_operand" "rm")
1.1 root 1771: (match_operand:SI 1 "immediate_operand" "i")))]
1772: "GET_CODE (operands[1]) == CONST_INT
1773: && exact_log2 (INTVAL (operands[1])) >= 0"
1774: "*
1775: {
1776: operands[1]
1777: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1778: cc_status.flags = CC_Z_IN_F;
1779: return \"tbitd %1,%0\";
1780: }")
1781:
1782: ;; extract(base, width, offset)
1783: ;; Signed bitfield extraction is not supported in hardware on the
1784: ;; NS 32032. It is therefore better to let GCC figure out a
1785: ;; good strategy for generating the proper instruction sequence
1786: ;; and represent it as rtl.
1787:
1.1.1.2 root 1788: ;; Optimize the case of extracting a byte or word from a register.
1789: ;; Otherwise we must load a register with the offset of the
1790: ;; chunk we want, and perform an extract insn (each of which
1791: ;; is very expensive). Since we use the stack to do our bit-twiddling
1792: ;; we cannot use it for a destination. Perhaps things are fast
1793: ;; enough on the 32532 that such hacks are not needed.
1794:
1795: (define_insn ""
1796: [(set (match_operand:SI 0 "general_operand" "=ro")
1797: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1798: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1799: (match_operand:SI 3 "const_int" "i")))]
1800: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1801: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1802: "*
1803: {
1804: output_asm_insn (\"movd %1,tos\", operands);
1805: if (INTVAL (operands[2]) == 16)
1806: {
1807: if (INTVAL (operands[3]) == 8)
1808: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1809: else
1810: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1811: }
1812: else
1813: {
1814: if (INTVAL (operands[3]) == 8)
1815: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1816: else if (INTVAL (operands[3]) == 16)
1817: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1818: else
1819: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1820: }
1.1.1.6 root 1821: #if defined(ns32532) || defined(ns32332)
1822: return \"cmpqd %$0,tos # adjsp -4\";
1823: #else
1.1.1.2 root 1824: return \"adjspb %$-4\";
1.1.1.6 root 1825: #endif
1.1.1.2 root 1826: }")
1827:
1828: (define_insn ""
1829: [(set (match_operand:SI 0 "general_operand" "=ro")
1830: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1831: (match_operand:SI 2 "const_int" "i")
1832: (match_operand:SI 3 "const_int" "i")))]
1833: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1834: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1835:
1836: (define_insn "extzv"
1837: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1838: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1839: (match_operand:SI 2 "const_int" "i,i")
1840: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1841: ""
1842: "*
1843: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1844: {
1845: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1846: operands[1] = adj_offsetable_operand (operands[1],
1847: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1848: return \"extsd %1,%0,%3,%2\";
1849: }
1.1 root 1850: else return \"extd %3,%1,%0,%2\";
1851: }")
1852:
1853: (define_insn ""
1.1.1.2 root 1854: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1855: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1856: (match_operand:SI 2 "const_int" "i,i")
1857: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1858: ""
1859: "*
1860: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1861: {
1862: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1863: operands[1] = adj_offsetable_operand (operands[1],
1864: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1865: return \"extsd %1,%0,%3,%2\";
1866: }
1.1 root 1867: else return \"extd %3,%1,%0,%2\";
1868: }")
1869:
1870: (define_insn ""
1871: [(set (match_operand:SI 0 "general_operand" "=g<")
1872: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1873: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1874: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1875: ""
1876: "*
1877: { if (GET_CODE (operands[3]) == CONST_INT)
1878: return \"extsd %1,%0,%3,%2\";
1879: else return \"extd %3,%1,%0,%2\";
1880: }")
1881:
1882: (define_insn "insv"
1.1.1.4 root 1883: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1.1.1.2 root 1884: (match_operand:SI 1 "const_int" "i,i")
1885: (match_operand:SI 2 "general_operand" "rK,n"))
1886: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1887: ""
1888: "*
1889: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1890: {
1.1.1.4 root 1891: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1892: {
1893: operands[0] = adj_offsetable_operand (operands[0],
1894: INTVAL (operands[2]) / 8);
1895: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1896: }
1.1.1.2 root 1897: if (INTVAL (operands[1]) <= 8)
1898: return \"inssb %3,%0,%2,%1\";
1899: else if (INTVAL (operands[1]) <= 16)
1900: return \"inssw %3,%0,%2,%1\";
1901: else
1902: return \"inssd %3,%0,%2,%1\";
1903: }
1904: return \"insd %2,%3,%0,%1\";
1.1 root 1905: }")
1906:
1907: (define_insn ""
1.1.1.4 root 1908: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1.1.1.2 root 1909: (match_operand:SI 1 "const_int" "i,i")
1910: (match_operand:SI 2 "general_operand" "rK,n"))
1911: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1912: ""
1913: "*
1914: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1915: {
1.1.1.4 root 1916: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1917: {
1918: operands[0] = adj_offsetable_operand (operands[0],
1919: INTVAL (operands[2]) / 8);
1920: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1921: }
1.1.1.2 root 1922: if (INTVAL (operands[1]) <= 8)
1923: return \"inssb %3,%0,%2,%1\";
1924: else if (INTVAL (operands[1]) <= 16)
1925: return \"inssw %3,%0,%2,%1\";
1926: else
1927: return \"inssd %3,%0,%2,%1\";
1928: }
1929: return \"insd %2,%3,%0,%1\";
1.1 root 1930: }")
1931:
1932: (define_insn ""
1933: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1934: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1935: (match_operand:SI 2 "general_operand" "rn"))
1936: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1937: ""
1938: "*
1939: { if (GET_CODE (operands[2]) == CONST_INT)
1940: if (INTVAL (operands[1]) <= 8)
1941: return \"inssb %3,%0,%2,%1\";
1942: else if (INTVAL (operands[1]) <= 16)
1943: return \"inssw %3,%0,%2,%1\";
1944: else
1945: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1946: return \"insd %2,%3,%0,%1\";
1.1 root 1947: }")
1948:
1949:
1950: (define_insn "jump"
1951: [(set (pc)
1952: (label_ref (match_operand 0 "" "")))]
1953: ""
1954: "br %l0")
1955:
1956: (define_insn "beq"
1957: [(set (pc)
1958: (if_then_else (eq (cc0)
1959: (const_int 0))
1960: (label_ref (match_operand 0 "" ""))
1961: (pc)))]
1962: ""
1963: "*
1964: { if (cc_prev_status.flags & CC_Z_IN_F)
1965: return \"bfc %l0\";
1966: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1967: return \"bfs %l0\";
1968: else return \"beq %l0\";
1969: }")
1970:
1971: (define_insn "bne"
1972: [(set (pc)
1973: (if_then_else (ne (cc0)
1974: (const_int 0))
1975: (label_ref (match_operand 0 "" ""))
1976: (pc)))]
1977: ""
1978: "*
1979: { if (cc_prev_status.flags & CC_Z_IN_F)
1980: return \"bfs %l0\";
1981: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1982: return \"bfc %l0\";
1983: else return \"bne %l0\";
1984: }")
1985:
1986: (define_insn "bgt"
1987: [(set (pc)
1988: (if_then_else (gt (cc0)
1989: (const_int 0))
1990: (label_ref (match_operand 0 "" ""))
1991: (pc)))]
1992: ""
1993: "bgt %l0")
1994:
1995: (define_insn "bgtu"
1996: [(set (pc)
1997: (if_then_else (gtu (cc0)
1998: (const_int 0))
1999: (label_ref (match_operand 0 "" ""))
2000: (pc)))]
2001: ""
2002: "bhi %l0")
2003:
2004: (define_insn "blt"
2005: [(set (pc)
2006: (if_then_else (lt (cc0)
2007: (const_int 0))
2008: (label_ref (match_operand 0 "" ""))
2009: (pc)))]
2010: ""
2011: "blt %l0")
2012:
2013: (define_insn "bltu"
2014: [(set (pc)
2015: (if_then_else (ltu (cc0)
2016: (const_int 0))
2017: (label_ref (match_operand 0 "" ""))
2018: (pc)))]
2019: ""
2020: "blo %l0")
2021:
2022: (define_insn "bge"
2023: [(set (pc)
2024: (if_then_else (ge (cc0)
2025: (const_int 0))
2026: (label_ref (match_operand 0 "" ""))
2027: (pc)))]
2028: ""
2029: "bge %l0")
2030:
2031: (define_insn "bgeu"
2032: [(set (pc)
2033: (if_then_else (geu (cc0)
2034: (const_int 0))
2035: (label_ref (match_operand 0 "" ""))
2036: (pc)))]
2037: ""
2038: "bhs %l0")
2039:
2040: (define_insn "ble"
2041: [(set (pc)
2042: (if_then_else (le (cc0)
2043: (const_int 0))
2044: (label_ref (match_operand 0 "" ""))
2045: (pc)))]
2046: ""
2047: "ble %l0")
2048:
2049: (define_insn "bleu"
2050: [(set (pc)
2051: (if_then_else (leu (cc0)
2052: (const_int 0))
2053: (label_ref (match_operand 0 "" ""))
2054: (pc)))]
2055: ""
2056: "bls %l0")
2057:
2058: (define_insn ""
2059: [(set (pc)
2060: (if_then_else (eq (cc0)
2061: (const_int 0))
2062: (pc)
2063: (label_ref (match_operand 0 "" ""))))]
2064: ""
2065: "*
2066: { if (cc_prev_status.flags & CC_Z_IN_F)
2067: return \"bfs %l0\";
2068: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2069: return \"bfc %l0\";
2070: else return \"bne %l0\";
2071: }")
2072:
2073: (define_insn ""
2074: [(set (pc)
2075: (if_then_else (ne (cc0)
2076: (const_int 0))
2077: (pc)
2078: (label_ref (match_operand 0 "" ""))))]
2079: ""
2080: "*
2081: { if (cc_prev_status.flags & CC_Z_IN_F)
2082: return \"bfc %l0\";
2083: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2084: return \"bfs %l0\";
2085: else return \"beq %l0\";
2086: }")
2087:
2088: (define_insn ""
2089: [(set (pc)
2090: (if_then_else (gt (cc0)
2091: (const_int 0))
2092: (pc)
2093: (label_ref (match_operand 0 "" ""))))]
2094: ""
2095: "ble %l0")
2096:
2097: (define_insn ""
2098: [(set (pc)
2099: (if_then_else (gtu (cc0)
2100: (const_int 0))
2101: (pc)
2102: (label_ref (match_operand 0 "" ""))))]
2103: ""
2104: "bls %l0")
2105:
2106: (define_insn ""
2107: [(set (pc)
2108: (if_then_else (lt (cc0)
2109: (const_int 0))
2110: (pc)
2111: (label_ref (match_operand 0 "" ""))))]
2112: ""
2113: "bge %l0")
2114:
2115: (define_insn ""
2116: [(set (pc)
2117: (if_then_else (ltu (cc0)
2118: (const_int 0))
2119: (pc)
2120: (label_ref (match_operand 0 "" ""))))]
2121: ""
2122: "bhs %l0")
2123:
2124: (define_insn ""
2125: [(set (pc)
2126: (if_then_else (ge (cc0)
2127: (const_int 0))
2128: (pc)
2129: (label_ref (match_operand 0 "" ""))))]
2130: ""
2131: "blt %l0")
2132:
2133: (define_insn ""
2134: [(set (pc)
2135: (if_then_else (geu (cc0)
2136: (const_int 0))
2137: (pc)
2138: (label_ref (match_operand 0 "" ""))))]
2139: ""
2140: "blo %l0")
2141:
2142: (define_insn ""
2143: [(set (pc)
2144: (if_then_else (le (cc0)
2145: (const_int 0))
2146: (pc)
2147: (label_ref (match_operand 0 "" ""))))]
2148: ""
2149: "bgt %l0")
2150:
2151: (define_insn ""
2152: [(set (pc)
2153: (if_then_else (leu (cc0)
2154: (const_int 0))
2155: (pc)
2156: (label_ref (match_operand 0 "" ""))))]
2157: ""
2158: "bhi %l0")
2159:
2160: ;; Subtract-and-jump and Add-and-jump insns.
2161: ;; These can actually be used for adding numbers in the range -8 to 7
2162:
2163: (define_insn ""
2164: [(set (pc)
2165: (if_then_else
2166: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2167: (match_operand:SI 1 "general_operand" "i"))
2168: (const_int 0))
2169: (label_ref (match_operand 2 "" ""))
2170: (pc)))
2171: (set (match_dup 0)
2172: (minus:SI (match_dup 0)
2173: (match_dup 1)))]
2174: "GET_CODE (operands[1]) == CONST_INT
2175: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2176: "acbd %$%n1,%0,%l2")
2177:
2178: (define_insn ""
2179: [(set (pc)
2180: (if_then_else
2181: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2182: (match_operand:SI 1 "general_operand" "i"))
2183: (const_int 0))
2184: (label_ref (match_operand 2 "" ""))
2185: (pc)))
2186: (set (match_dup 0)
2187: (plus:SI (match_dup 0)
2188: (match_dup 1)))]
2189: "GET_CODE (operands[1]) == CONST_INT
2190: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2191: "acbd %1,%0,%l2")
2192:
2193: ;; Reversed
2194:
2195: (define_insn ""
2196: [(set (pc)
2197: (if_then_else
2198: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2199: (match_operand:SI 1 "general_operand" "i"))
2200: (const_int 0))
2201: (pc)
2202: (label_ref (match_operand 2 "" ""))))
2203: (set (match_dup 0)
2204: (minus:SI (match_dup 0)
2205: (match_dup 1)))]
2206: "GET_CODE (operands[1]) == CONST_INT
2207: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2208: "acbd %$%n1,%0,%l2")
2209:
2210: (define_insn ""
2211: [(set (pc)
2212: (if_then_else
2213: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2214: (match_operand:SI 1 "general_operand" "i"))
2215: (const_int 0))
2216: (pc)
2217: (label_ref (match_operand 2 "" ""))))
2218: (set (match_dup 0)
2219: (plus:SI (match_dup 0)
2220: (match_dup 1)))]
2221: "GET_CODE (operands[1]) == CONST_INT
2222: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2223: "acbd %1,%0,%l2")
2224:
2225: (define_insn "call"
2226: [(call (match_operand:QI 0 "general_operand" "g")
2227: (match_operand:QI 1 "general_operand" "g"))]
2228: ""
2229: "*
2230: {
2231: if (GET_CODE (operands[0]) == MEM)
2232: {
2233: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.4 root 2234: #ifdef GNX_V3
2235: return \"bsr %0\";
2236: #else
1.1.1.2 root 2237: return \"bsr %?%a0\";
1.1.1.4 root 2238: #endif
1.1 root 2239: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.4 root 2240: #ifdef GNX_V3
2241: return \"jsr %0\";
2242: #else
1.1 root 2243: return \"jsr %a0\";
1.1.1.4 root 2244: #endif
1.1 root 2245: }
2246: return \"jsr %0\";
2247: }")
2248:
2249: (define_insn "call_value"
2250: [(set (match_operand 0 "" "fg")
2251: (call (match_operand:QI 1 "general_operand" "g")
2252: (match_operand:QI 2 "general_operand" "g")))]
2253: ""
2254: "*
2255: {
2256: if (GET_CODE (operands[1]) == MEM)
2257: {
2258: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.4 root 2259: #ifdef GNX_V3
2260: return \"bsr %1\";
2261: #else
1.1.1.2 root 2262: return \"bsr %?%a1\";
1.1.1.4 root 2263: #endif
1.1 root 2264: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.4 root 2265: #ifdef GNX_V3
2266: return \"jsr %1\";
2267: #else
1.1 root 2268: return \"jsr %a1\";
1.1.1.4 root 2269: #endif
1.1 root 2270: }
2271: return \"jsr %1\";
2272: }")
2273:
2274: (define_insn "return"
2275: [(return)]
1.1.1.5 root 2276: "0"
1.1 root 2277: "ret 0")
2278:
2279: (define_insn "abssf2"
2280: [(set (match_operand:SF 0 "general_operand" "=fm<")
2281: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2282: "TARGET_32081"
2283: "absf %1,%0")
2284:
2285: (define_insn "absdf2"
2286: [(set (match_operand:DF 0 "general_operand" "=fm<")
2287: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2288: "TARGET_32081"
2289: "absl %1,%0")
2290:
2291: (define_insn "abssi2"
2292: [(set (match_operand:SI 0 "general_operand" "=g<")
2293: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2294: ""
2295: "absd %1,%0")
2296:
2297: (define_insn "abshi2"
2298: [(set (match_operand:HI 0 "general_operand" "=g<")
2299: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2300: ""
2301: "absw %1,%0")
2302:
2303: (define_insn "absqi2"
2304: [(set (match_operand:QI 0 "general_operand" "=g<")
2305: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2306: ""
2307: "absb %1,%0")
2308:
2309: ;;(define_insn "tablejump"
2310: ;; [(set (pc)
2311: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2312: ;; (pc)))]
2313: ;; ""
2314: ;; "cased %0")
2315:
2316: (define_insn "tablejump"
2317: [(set (pc)
2318: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2319: (use (label_ref (match_operand 1 "" "")))]
2320: ""
2321: "*
2322: {
2323: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2324: CODE_LABEL_NUMBER (operands[1]));
2325: return \"casew %0\";
2326: }")
2327:
2328: ;;(define_insn ""
2329: ;; [(set (pc)
2330: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2331: ;; (pc)))]
2332: ;; ""
2333: ;; "caseb %0")
2334:
2335: ;; Scondi instructions
2336: (define_insn "seq"
2337: [(set (match_operand:SI 0 "general_operand" "=g<")
2338: (eq (cc0) (const_int 0)))]
2339: ""
2340: "*
2341: { if (cc_prev_status.flags & CC_Z_IN_F)
2342: return \"sfcd %0\";
2343: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2344: return \"sfsd %0\";
2345: else return \"seqd %0\";
2346: }")
2347:
2348: (define_insn ""
2349: [(set (match_operand:HI 0 "general_operand" "=g<")
2350: (eq (cc0) (const_int 0)))]
2351: ""
2352: "*
2353: { if (cc_prev_status.flags & CC_Z_IN_F)
2354: return \"sfcw %0\";
2355: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2356: return \"sfsw %0\";
2357: else return \"seqw %0\";
2358: }")
2359:
2360: (define_insn ""
2361: [(set (match_operand:QI 0 "general_operand" "=g<")
2362: (eq (cc0) (const_int 0)))]
2363: ""
2364: "*
2365: { if (cc_prev_status.flags & CC_Z_IN_F)
2366: return \"sfcb %0\";
2367: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2368: return \"sfsb %0\";
2369: else return \"seqb %0\";
2370: }")
2371:
2372: (define_insn "sne"
2373: [(set (match_operand:SI 0 "general_operand" "=g<")
2374: (ne (cc0) (const_int 0)))]
2375: ""
2376: "*
2377: { if (cc_prev_status.flags & CC_Z_IN_F)
2378: return \"sfsd %0\";
2379: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2380: return \"sfcd %0\";
2381: else return \"sned %0\";
2382: }")
2383:
2384: (define_insn ""
2385: [(set (match_operand:HI 0 "general_operand" "=g<")
2386: (ne (cc0) (const_int 0)))]
2387: ""
2388: "*
2389: { if (cc_prev_status.flags & CC_Z_IN_F)
2390: return \"sfsw %0\";
2391: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2392: return \"sfcw %0\";
2393: else return \"snew %0\";
2394: }")
2395:
2396: (define_insn ""
2397: [(set (match_operand:QI 0 "general_operand" "=g<")
2398: (ne (cc0) (const_int 0)))]
2399: ""
2400: "*
2401: { if (cc_prev_status.flags & CC_Z_IN_F)
2402: return \"sfsb %0\";
2403: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2404: return \"sfcb %0\";
2405: else return \"sneb %0\";
2406: }")
2407:
2408: (define_insn "sgt"
2409: [(set (match_operand:SI 0 "general_operand" "=g<")
2410: (gt (cc0) (const_int 0)))]
2411: ""
2412: "sgtd %0")
2413:
2414: (define_insn ""
2415: [(set (match_operand:HI 0 "general_operand" "=g<")
2416: (gt (cc0) (const_int 0)))]
2417: ""
2418: "sgtw %0")
2419:
2420: (define_insn ""
2421: [(set (match_operand:QI 0 "general_operand" "=g<")
2422: (gt (cc0) (const_int 0)))]
2423: ""
2424: "sgtb %0")
2425:
2426: (define_insn "sgtu"
2427: [(set (match_operand:SI 0 "general_operand" "=g<")
2428: (gtu (cc0) (const_int 0)))]
2429: ""
2430: "shid %0")
2431:
2432: (define_insn ""
2433: [(set (match_operand:HI 0 "general_operand" "=g<")
2434: (gtu (cc0) (const_int 0)))]
2435: ""
2436: "shiw %0")
2437:
2438: (define_insn ""
2439: [(set (match_operand:QI 0 "general_operand" "=g<")
2440: (gtu (cc0) (const_int 0)))]
2441: ""
2442: "shib %0")
2443:
2444: (define_insn "slt"
2445: [(set (match_operand:SI 0 "general_operand" "=g<")
2446: (lt (cc0) (const_int 0)))]
2447: ""
2448: "sltd %0")
2449:
2450: (define_insn ""
2451: [(set (match_operand:HI 0 "general_operand" "=g<")
2452: (lt (cc0) (const_int 0)))]
2453: ""
2454: "sltw %0")
2455:
2456: (define_insn ""
2457: [(set (match_operand:QI 0 "general_operand" "=g<")
2458: (lt (cc0) (const_int 0)))]
2459: ""
2460: "sltb %0")
2461:
2462: (define_insn "sltu"
2463: [(set (match_operand:SI 0 "general_operand" "=g<")
2464: (ltu (cc0) (const_int 0)))]
2465: ""
2466: "slod %0")
2467:
2468: (define_insn ""
2469: [(set (match_operand:HI 0 "general_operand" "=g<")
2470: (ltu (cc0) (const_int 0)))]
2471: ""
2472: "slow %0")
2473:
2474: (define_insn ""
2475: [(set (match_operand:QI 0 "general_operand" "=g<")
2476: (ltu (cc0) (const_int 0)))]
2477: ""
2478: "slob %0")
2479:
2480: (define_insn "sge"
2481: [(set (match_operand:SI 0 "general_operand" "=g<")
2482: (ge (cc0) (const_int 0)))]
2483: ""
2484: "sged %0")
2485:
2486: (define_insn ""
2487: [(set (match_operand:HI 0 "general_operand" "=g<")
2488: (ge (cc0) (const_int 0)))]
2489: ""
2490: "sgew %0")
2491:
2492: (define_insn ""
2493: [(set (match_operand:QI 0 "general_operand" "=g<")
2494: (ge (cc0) (const_int 0)))]
2495: ""
2496: "sgeb %0")
2497:
2498: (define_insn "sgeu"
2499: [(set (match_operand:SI 0 "general_operand" "=g<")
2500: (geu (cc0) (const_int 0)))]
2501: ""
2502: "shsd %0")
2503:
2504: (define_insn ""
2505: [(set (match_operand:HI 0 "general_operand" "=g<")
2506: (geu (cc0) (const_int 0)))]
2507: ""
2508: "shsw %0")
2509:
2510: (define_insn ""
2511: [(set (match_operand:QI 0 "general_operand" "=g<")
2512: (geu (cc0) (const_int 0)))]
2513: ""
2514: "shsb %0")
2515:
2516: (define_insn "sle"
2517: [(set (match_operand:SI 0 "general_operand" "=g<")
2518: (le (cc0) (const_int 0)))]
2519: ""
2520: "sled %0")
2521:
2522: (define_insn ""
2523: [(set (match_operand:HI 0 "general_operand" "=g<")
2524: (le (cc0) (const_int 0)))]
2525: ""
2526: "slew %0")
2527:
2528: (define_insn ""
2529: [(set (match_operand:QI 0 "general_operand" "=g<")
2530: (le (cc0) (const_int 0)))]
2531: ""
2532: "sleb %0")
2533:
2534: (define_insn "sleu"
2535: [(set (match_operand:SI 0 "general_operand" "=g<")
2536: (leu (cc0) (const_int 0)))]
2537: ""
2538: "slsd %0")
2539:
2540: (define_insn ""
2541: [(set (match_operand:HI 0 "general_operand" "=g<")
2542: (leu (cc0) (const_int 0)))]
2543: ""
2544: "slsw %0")
2545:
2546: (define_insn ""
2547: [(set (match_operand:QI 0 "general_operand" "=g<")
2548: (leu (cc0) (const_int 0)))]
2549: ""
2550: "slsb %0")
2551:
2552: ;;- Local variables:
2553: ;;- mode:emacs-lisp
2554: ;;- comment-start: ";;- "
2555: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2556: ;;- eval: (modify-syntax-entry ?[ "(]")
2557: ;;- eval: (modify-syntax-entry ?] ")[")
2558: ;;- eval: (modify-syntax-entry ?{ "(}")
2559: ;;- eval: (modify-syntax-entry ?} "){")
2560: ;;- End:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.