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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
1.1.1.11! root 16: ;; GNU CC is free software; you can redistribute it and/or modify
! 17: ;; it under the terms of the GNU General Public License as published by
! 18: ;; the Free Software Foundation; either version 1, or (at your option)
! 19: ;; any later version.
! 20:
1.1 root 21: ;; GNU CC is distributed in the hope that it will be useful,
1.1.1.11! root 22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
! 23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
! 24: ;; GNU General Public License for more details.
! 25:
! 26: ;; You should have received a copy of the GNU General Public License
! 27: ;; along with GNU CC; see the file COPYING. If not, write to
! 28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
1.1 root 29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ; tstsi is first test insn so that it is the one to match
40: ; a constant argument.
41:
42: (define_insn "tstsi"
43: [(set (cc0)
44: (match_operand:SI 0 "general_operand" "rmn"))]
45: ""
46: "*
1.1.1.2 root 47: { cc_status.flags |= CC_REVERSED;
48: operands[1] = const0_rtx;
49: return \"cmpqd %1,%0\"; }")
1.1 root 50:
51: (define_insn "tsthi"
52: [(set (cc0)
53: (match_operand:HI 0 "general_operand" "g"))]
54: ""
55: "*
1.1.1.2 root 56: { cc_status.flags |= CC_REVERSED;
57: operands[1] = const0_rtx;
58: return \"cmpqw %1,%0\"; }")
1.1 root 59:
60: (define_insn "tstqi"
61: [(set (cc0)
62: (match_operand:QI 0 "general_operand" "g"))]
63: ""
64: "*
1.1.1.2 root 65: { cc_status.flags |= CC_REVERSED;
66: operands[1] = const0_rtx;
67: return \"cmpqb %1,%0\"; }")
1.1 root 68:
69: (define_insn "tstdf"
70: [(set (cc0)
71: (match_operand:DF 0 "general_operand" "fmF"))]
72: "TARGET_32081"
73: "*
1.1.1.2 root 74: { cc_status.flags |= CC_REVERSED;
75: operands[1] = dconst0_rtx;
76: return \"cmpl %1,%0\"; }")
1.1 root 77:
78: (define_insn "tstsf"
79: [(set (cc0)
80: (match_operand:SF 0 "general_operand" "fmF"))]
81: "TARGET_32081"
82: "*
1.1.1.2 root 83: { cc_status.flags |= CC_REVERSED;
84: operands[1] = fconst0_rtx;
85: return \"cmpf %1,%0\"; }")
1.1 root 86:
87: (define_insn "cmpdf"
88: [(set (cc0)
1.1.1.11! root 89: (compare (match_operand:DF 0 "general_operand" "fmF")
! 90: (match_operand:DF 1 "general_operand" "fmF")))]
1.1 root 91: "TARGET_32081"
92: "cmpl %0,%1")
93:
94: (define_insn "cmpsf"
95: [(set (cc0)
1.1.1.11! root 96: (compare (match_operand:SF 0 "general_operand" "fmF")
! 97: (match_operand:SF 1 "general_operand" "fmF")))]
1.1 root 98: "TARGET_32081"
99: "cmpf %0,%1")
100:
101: (define_insn "cmpsi"
102: [(set (cc0)
1.1.1.11! root 103: (compare (match_operand:SI 0 "general_operand" "rmn")
! 104: (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 105: ""
106: "*
107: {
108: if (GET_CODE (operands[1]) == CONST_INT)
109: {
110: int i = INTVAL (operands[1]);
111: if (i <= 7 && i >= -8)
112: {
113: cc_status.flags |= CC_REVERSED;
114: return \"cmpqd %1,%0\";
115: }
116: }
117: cc_status.flags &= ~CC_REVERSED;
118: if (GET_CODE (operands[0]) == CONST_INT)
119: {
120: int i = INTVAL (operands[0]);
121: if (i <= 7 && i >= -8)
122: return \"cmpqd %0,%1\";
123: }
124: return \"cmpd %0,%1\";
125: }")
126:
127: (define_insn "cmphi"
128: [(set (cc0)
1.1.1.11! root 129: (compare (match_operand:HI 0 "general_operand" "g")
! 130: (match_operand:HI 1 "general_operand" "g")))]
1.1 root 131: ""
132: "*
133: {
134: if (GET_CODE (operands[1]) == CONST_INT)
135: {
136: short i = INTVAL (operands[1]);
137: if (i <= 7 && i >= -8)
138: {
139: cc_status.flags |= CC_REVERSED;
140: if (INTVAL (operands[1]) > 7)
141: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
142: return \"cmpqw %1,%0\";
143: }
144: }
145: cc_status.flags &= ~CC_REVERSED;
146: if (GET_CODE (operands[0]) == CONST_INT)
147: {
148: short i = INTVAL (operands[0]);
149: if (i <= 7 && i >= -8)
150: {
151: if (INTVAL (operands[0]) > 7)
152: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
153: return \"cmpqw %0,%1\";
154: }
155: }
156: return \"cmpw %0,%1\";
157: }")
158:
159: (define_insn "cmpqi"
160: [(set (cc0)
1.1.1.11! root 161: (compare (match_operand:QI 0 "general_operand" "g")
! 162: (match_operand:QI 1 "general_operand" "g")))]
1.1 root 163: ""
164: "*
165: {
166: if (GET_CODE (operands[1]) == CONST_INT)
167: {
168: char i = INTVAL (operands[1]);
169: if (i <= 7 && i >= -8)
170: {
171: cc_status.flags |= CC_REVERSED;
172: if (INTVAL (operands[1]) > 7)
173: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
174: return \"cmpqb %1,%0\";
175: }
176: }
177: cc_status.flags &= ~CC_REVERSED;
178: if (GET_CODE (operands[0]) == CONST_INT)
179: {
180: char i = INTVAL (operands[0]);
181: if (i <= 7 && i >= -8)
182: {
183: if (INTVAL (operands[0]) > 7)
184: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
185: return \"cmpqb %0,%1\";
186: }
187: }
188: return \"cmpb %0,%1\";
189: }")
190:
191: (define_insn "movdf"
1.1.1.8 root 192: [(set (match_operand:DF 0 "general_operand" "=&fg<")
1.1 root 193: (match_operand:DF 1 "general_operand" "fFg"))]
194: ""
195: "*
196: {
197: if (FP_REG_P (operands[0]))
198: {
199: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
200: return \"movl %1,%0\";
201: if (REG_P (operands[1]))
202: {
203: rtx xoperands[2];
204: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
205: output_asm_insn (\"movd %1,tos\", xoperands);
206: output_asm_insn (\"movd %1,tos\", operands);
207: return \"movl tos,%0\";
208: }
209: return \"movl %1,%0\";
210: }
211: else if (FP_REG_P (operands[1]))
212: {
213: if (REG_P (operands[0]))
214: {
215: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
216: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
217: return \"movd tos,%0\";
218: }
219: else
220: return \"movl %1,%0\";
221: }
222: return output_move_double (operands);
223: }")
224:
225: (define_insn "movsf"
226: [(set (match_operand:SF 0 "general_operand" "=fg<")
227: (match_operand:SF 1 "general_operand" "fFg"))]
228: ""
229: "*
230: {
231: if (FP_REG_P (operands[0]))
232: {
233: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
234: return \"movd %1,tos\;movf tos,%0\";
235: else
236: return \"movf %1,%0\";
237: }
238: else if (FP_REG_P (operands[1]))
239: {
240: if (REG_P (operands[0]))
241: return \"movf %1,tos\;movd tos,%0\";
242: return \"movf %1,%0\";
243: }
244: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
245: {
246: /* Is there a better machine-independent way to to this? */
247: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
248: return \"movd %1,%0\";
249: }
250: else return \"movd %1,%0\";
251: }")
252:
253: (define_insn ""
254: [(set (match_operand:TI 0 "memory_operand" "=m")
255: (match_operand:TI 1 "memory_operand" "m"))]
256: ""
257: "movmd %1,%0,4")
258:
259: (define_insn "movdi"
1.1.1.8 root 260: [(set (match_operand:DI 0 "general_operand" "=&g<")
1.1.1.3 root 261: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 262: ""
263: "* return output_move_double (operands); ")
264:
1.1.1.9 root 265: ;; This special case must precede movsi.
266: (define_insn ""
267: [(set (reg:SI 17)
268: (match_operand:SI 0 "general_operand" "rmn"))]
269: ""
270: "lprd sp,%0")
271:
1.1 root 272: (define_insn "movsi"
273: [(set (match_operand:SI 0 "general_operand" "=g<")
274: (match_operand:SI 1 "general_operand" "gx"))]
275: ""
276: "*
277: { if (GET_CODE (operands[1]) == CONST_INT)
278: {
279: int i = INTVAL (operands[1]);
280: if (i <= 7 && i >= -8)
281: return \"movqd %1,%0\";
282: if (i < 0x4000 && i >= -0x4000)
1.1.1.4 root 283: #ifdef GNX_V3
284: return \"addr %c1,%0\";
285: #else
1.1.1.2 root 286: return \"addr @%c1,%0\";
1.1.1.4 root 287: #endif
1.1 root 288: return \"movd %1,%0\";
289: }
290: else if (GET_CODE (operands[1]) == REG)
291: if (REGNO (operands[1]) < 16)
292: return \"movd %1,%0\";
293: else if (REGNO (operands[1]) == 16)
294: return \"addr 0(fp),%0\";
295: else return \"addr tos,%0\";
296: else if (GET_CODE (operands[1]) == MEM)
297: return \"movd %1,%0\";
1.1.1.2 root 298: /* Check if this effective address can be
299: calculated faster by pulling it apart. */
300: if (REG_P (operands[0])
301: && GET_CODE (operands[1]) == MULT
302: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
303: && (INTVAL (XEXP (operands[1], 1)) == 2
304: || INTVAL (XEXP (operands[1], 1)) == 4))
305: {
306: rtx xoperands[3];
307: xoperands[0] = operands[0];
308: xoperands[1] = XEXP (operands[1], 0);
309: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
310: return output_shift_insn (xoperands);
311: }
1.1 root 312: return \"addr %a1,%0\";
313: }")
314:
315: (define_insn "movhi"
316: [(set (match_operand:HI 0 "general_operand" "=g<")
317: (match_operand:HI 1 "general_operand" "g"))]
318: ""
319: "*
320: {
321: if (GET_CODE (operands[1]) == CONST_INT)
322: {
323: short i = INTVAL (operands[1]);
324: if (i <= 7 && i >= -8)
325: {
326: if (INTVAL (operands[1]) > 7)
327: operands[1] =
328: gen_rtx (CONST_INT, VOIDmode, i);
329: return \"movqw %1,%0\";
330: }
331: }
332: return \"movw %1,%0\";
333: }")
334:
335: (define_insn "movstricthi"
336: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
337: (match_operand:HI 1 "general_operand" "g"))]
338: ""
339: "*
340: {
341: if (GET_CODE (operands[1]) == CONST_INT
342: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
343: return \"movqw %1,%0\";
344: return \"movw %1,%0\";
345: }")
346:
347: (define_insn "movqi"
348: [(set (match_operand:QI 0 "general_operand" "=g<")
349: (match_operand:QI 1 "general_operand" "g"))]
350: ""
351: "*
352: { if (GET_CODE (operands[1]) == CONST_INT)
353: {
354: char char_val = (char)INTVAL (operands[1]);
355: if (char_val <= 7 && char_val >= -8)
356: {
357: if (INTVAL (operands[1]) > 7)
358: operands[1] =
359: gen_rtx (CONST_INT, VOIDmode, char_val);
360: return \"movqb %1,%0\";
361: }
362: }
363: return \"movb %1,%0\";
364: }")
365:
366: (define_insn "movstrictqi"
367: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
368: (match_operand:QI 1 "general_operand" "g"))]
369: ""
370: "*
371: {
372: if (GET_CODE (operands[1]) == CONST_INT
373: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
374: return \"movqb %1,%0\";
375: return \"movb %1,%0\";
376: }")
377:
378: ;; The definition of this insn does not really explain what it does,
379: ;; but it should suffice
380: ;; that anything generated as this insn will be recognized as one
381: ;; and that it won't successfully combine with anything.
382: (define_insn "movstrsi"
383: [(set (match_operand:BLK 0 "general_operand" "=g")
384: (match_operand:BLK 1 "general_operand" "g"))
385: (use (match_operand:SI 2 "general_operand" "rmn"))
386: (clobber (reg:SI 0))
387: (clobber (reg:SI 1))
388: (clobber (reg:SI 2))]
389: ""
390: "*
391: {
392: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
393: abort ();
394: operands[0] = XEXP (operands[0], 0);
395: operands[1] = XEXP (operands[1], 0);
396: if (GET_CODE (operands[0]) == MEM)
397: if (GET_CODE (operands[1]) == MEM)
398: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
399: else
400: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
401: else if (GET_CODE (operands[1]) == MEM)
402: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
403: else
404: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
405:
406: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
407: {
408: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
409: if ((unsigned) INTVAL (operands[2]) <= 7)
410: return \"movqd %2,r0\;movsd\";
411: else
412: return \"movd %2,r0\;movsd\";
413: }
414: else
415: {
416: return \"movd %2,r0\;movsb\";
417: }
418: }")
419:
420: ;; Extension and truncation insns.
421: ;; Those for integer source operand
422: ;; are ordered widest source type first.
423:
424: (define_insn "truncsiqi2"
425: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 426: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 427: ""
428: "movb %1,%0")
429:
430: (define_insn "truncsihi2"
431: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 432: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 433: ""
434: "movw %1,%0")
435:
436: (define_insn "trunchiqi2"
437: [(set (match_operand:QI 0 "general_operand" "=g<")
438: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
439: ""
440: "movb %1,%0")
441:
442: (define_insn "extendhisi2"
443: [(set (match_operand:SI 0 "general_operand" "=g<")
444: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
445: ""
446: "movxwd %1,%0")
447:
448: (define_insn "extendqihi2"
449: [(set (match_operand:HI 0 "general_operand" "=g<")
450: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
451: ""
452: "movxbw %1,%0")
453:
454: (define_insn "extendqisi2"
455: [(set (match_operand:SI 0 "general_operand" "=g<")
456: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
457: ""
458: "movxbd %1,%0")
459:
460: (define_insn "extendsfdf2"
461: [(set (match_operand:DF 0 "general_operand" "=fm<")
462: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
463: "TARGET_32081"
464: "movfl %1,%0")
465:
466: (define_insn "truncdfsf2"
467: [(set (match_operand:SF 0 "general_operand" "=fm<")
468: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
469: "TARGET_32081"
470: "movlf %1,%0")
471:
472: (define_insn "zero_extendhisi2"
473: [(set (match_operand:SI 0 "general_operand" "=g<")
474: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
475: ""
476: "movzwd %1,%0")
477:
478: (define_insn "zero_extendqihi2"
479: [(set (match_operand:HI 0 "general_operand" "=g<")
480: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
481: ""
482: "movzbw %1,%0")
483:
484: (define_insn "zero_extendqisi2"
485: [(set (match_operand:SI 0 "general_operand" "=g<")
486: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
487: ""
488: "movzbd %1,%0")
489:
490: ;; Fix-to-float conversion insns.
491: ;; Note that the ones that start with SImode come first.
492: ;; That is so that an operand that is a CONST_INT
493: ;; (and therefore lacks a specific machine mode).
494: ;; will be recognized as SImode (which is always valid)
495: ;; rather than as QImode or HImode.
496:
497: ;; Rumor has it that the National part does not correctly convert
498: ;; constant ints to floats. This conversion is therefore disabled.
499: ;; A register must be used to perform the conversion.
500:
501: (define_insn "floatsisf2"
502: [(set (match_operand:SF 0 "general_operand" "=fm<")
503: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
504: "TARGET_32081"
505: "movdf %1,%0")
506:
507: (define_insn "floatsidf2"
508: [(set (match_operand:DF 0 "general_operand" "=fm<")
509: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
510: "TARGET_32081"
511: "movdl %1,%0")
512:
513: (define_insn "floathisf2"
514: [(set (match_operand:SF 0 "general_operand" "=fm<")
515: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
516: "TARGET_32081"
517: "movwf %1,%0")
518:
519: (define_insn "floathidf2"
520: [(set (match_operand:DF 0 "general_operand" "=fm<")
521: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
522: "TARGET_32081"
523: "movwl %1,%0")
524:
525: (define_insn "floatqisf2"
526: [(set (match_operand:SF 0 "general_operand" "=fm<")
527: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
528: "TARGET_32081"
529: "movbf %1,%0")
530:
1.1.1.3 root 531: ; Some assemblers warn that this insn doesn't work.
532: ; Maybe they know something we don't.
533: ;(define_insn "floatqidf2"
534: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
535: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
536: ; "TARGET_32081"
537: ; "movbl %1,%0")
1.1 root 538:
539: ;; Float-to-fix conversion insns.
540: ;; The sequent compiler always generates "trunc" insns.
541:
542: (define_insn "fixsfqi2"
543: [(set (match_operand:QI 0 "general_operand" "=g<")
544: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
545: "TARGET_32081"
546: "truncfb %1,%0")
547:
548: (define_insn "fixsfhi2"
549: [(set (match_operand:HI 0 "general_operand" "=g<")
550: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
551: "TARGET_32081"
552: "truncfw %1,%0")
553:
554: (define_insn "fixsfsi2"
555: [(set (match_operand:SI 0 "general_operand" "=g<")
556: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
557: "TARGET_32081"
558: "truncfd %1,%0")
559:
560: (define_insn "fixdfqi2"
561: [(set (match_operand:QI 0 "general_operand" "=g<")
562: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
563: "TARGET_32081"
564: "trunclb %1,%0")
565:
566: (define_insn "fixdfhi2"
567: [(set (match_operand:HI 0 "general_operand" "=g<")
568: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
569: "TARGET_32081"
570: "trunclw %1,%0")
571:
572: (define_insn "fixdfsi2"
573: [(set (match_operand:SI 0 "general_operand" "=g<")
574: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
575: "TARGET_32081"
576: "truncld %1,%0")
577:
578: ;; Unsigned
579:
580: (define_insn "fixunssfqi2"
581: [(set (match_operand:QI 0 "general_operand" "=g<")
582: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
583: "TARGET_32081"
584: "truncfb %1,%0")
585:
586: (define_insn "fixunssfhi2"
587: [(set (match_operand:HI 0 "general_operand" "=g<")
588: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
589: "TARGET_32081"
590: "truncfw %1,%0")
591:
592: (define_insn "fixunssfsi2"
593: [(set (match_operand:SI 0 "general_operand" "=g<")
594: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
595: "TARGET_32081"
596: "truncfd %1,%0")
597:
598: (define_insn "fixunsdfqi2"
599: [(set (match_operand:QI 0 "general_operand" "=g<")
600: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
601: "TARGET_32081"
602: "trunclb %1,%0")
603:
604: (define_insn "fixunsdfhi2"
605: [(set (match_operand:HI 0 "general_operand" "=g<")
606: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
607: "TARGET_32081"
608: "trunclw %1,%0")
609:
610: (define_insn "fixunsdfsi2"
611: [(set (match_operand:SI 0 "general_operand" "=g<")
612: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
613: "TARGET_32081"
614: "truncld %1,%0")
615:
616: ;;; These are not yet used by GCC
617: (define_insn "fix_truncsfqi2"
618: [(set (match_operand:QI 0 "general_operand" "=g<")
619: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
620: "TARGET_32081"
621: "truncfb %1,%0")
622:
623: (define_insn "fix_truncsfhi2"
624: [(set (match_operand:HI 0 "general_operand" "=g<")
625: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
626: "TARGET_32081"
627: "truncfw %1,%0")
628:
629: (define_insn "fix_truncsfsi2"
630: [(set (match_operand:SI 0 "general_operand" "=g<")
631: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
632: "TARGET_32081"
633: "truncfd %1,%0")
634:
635: (define_insn "fix_truncdfqi2"
636: [(set (match_operand:QI 0 "general_operand" "=g<")
637: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
638: "TARGET_32081"
639: "trunclb %1,%0")
640:
641: (define_insn "fix_truncdfhi2"
642: [(set (match_operand:HI 0 "general_operand" "=g<")
643: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
644: "TARGET_32081"
645: "trunclw %1,%0")
646:
647: (define_insn "fix_truncdfsi2"
648: [(set (match_operand:SI 0 "general_operand" "=g<")
649: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
650: "TARGET_32081"
651: "truncld %1,%0")
652:
653: ;;- All kinds of add instructions.
654:
655: (define_insn "adddf3"
656: [(set (match_operand:DF 0 "general_operand" "=fm")
657: (plus:DF (match_operand:DF 1 "general_operand" "%0")
658: (match_operand:DF 2 "general_operand" "fmF")))]
659: "TARGET_32081"
660: "addl %2,%0")
661:
662:
663: (define_insn "addsf3"
664: [(set (match_operand:SF 0 "general_operand" "=fm")
665: (plus:SF (match_operand:SF 1 "general_operand" "%0")
666: (match_operand:SF 2 "general_operand" "fmF")))]
667: "TARGET_32081"
668: "addf %2,%0")
669:
670: (define_insn ""
671: [(set (reg:SI 17)
672: (plus:SI (reg:SI 17)
673: (match_operand:SI 0 "immediate_operand" "i")))]
674: "GET_CODE (operands[0]) == CONST_INT"
675: "*
676: {
1.1.1.6 root 677: #if defined(ns32532)
678: if (INTVAL(operands[0]) == 8)
679: return \"cmpd tos,tos # adjsp -8\";
680: #endif
681: #if defined(ns32532) || defined(ns32332)
682: if (INTVAL(operands[0]) == 4)
683: return \"cmpqd %$0,tos # adjsp -4\";
684: #endif
1.1 root 685: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
686: return \"adjspb %$%n0\";
687: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
688: return \"adjspw %$%n0\";
689: return \"adjspd %$%n0\";
690: }")
691:
692: (define_insn ""
693: [(set (match_operand:SI 0 "general_operand" "=g<")
694: (plus:SI (reg:SI 16)
695: (match_operand:SI 1 "immediate_operand" "i")))]
696: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 697: "addr %c1(fp),%0")
1.1 root 698:
699: (define_insn ""
700: [(set (match_operand:SI 0 "general_operand" "=g<")
701: (plus:SI (reg:SI 17)
702: (match_operand:SI 1 "immediate_operand" "i")))]
703: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 704: "addr %c1(sp),%0")
1.1 root 705:
706: (define_insn "addsi3"
1.1.1.9 root 707: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
708: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
709: (match_operand:SI 2 "general_operand" "rmn,n")))]
1.1 root 710: ""
711: "*
712: {
1.1.1.9 root 713: if (which_alternative == 1)
714: return \"addr %c2(%1),%0\";
1.1 root 715: if (GET_CODE (operands[2]) == CONST_INT)
716: {
717: int i = INTVAL (operands[2]);
718:
719: if (i <= 7 && i >= -8)
720: return \"addqd %2,%0\";
721: else if (GET_CODE (operands[0]) == REG
722: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 723: return \"addr %c2(%0),%0\";
1.1 root 724: }
725: return \"addd %2,%0\";
726: }")
727:
728: (define_insn "addhi3"
729: [(set (match_operand:HI 0 "general_operand" "=g")
730: (plus:HI (match_operand:HI 1 "general_operand" "%0")
731: (match_operand:HI 2 "general_operand" "g")))]
732: ""
733: "*
734: { if (GET_CODE (operands[2]) == CONST_INT)
735: {
736: int i = INTVAL (operands[2]);
737: if (i <= 7 && i >= -8)
738: return \"addqw %2,%0\";
739: }
740: return \"addw %2,%0\";
741: }")
742:
743: (define_insn ""
744: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
745: (plus:HI (match_operand:HI 1 "general_operand" "0")
746: (match_operand:HI 2 "general_operand" "g")))]
747: ""
748: "*
749: {
750: if (GET_CODE (operands[1]) == CONST_INT
751: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
752: return \"addqw %1,%0\";
753: return \"addw %1,%0\";
754: }")
755:
756: (define_insn "addqi3"
757: [(set (match_operand:QI 0 "general_operand" "=g")
758: (plus:QI (match_operand:QI 1 "general_operand" "%0")
759: (match_operand:QI 2 "general_operand" "g")))]
760: ""
761: "*
762: { if (GET_CODE (operands[2]) == CONST_INT)
763: {
764: int i = INTVAL (operands[2]);
765: if (i <= 7 && i >= -8)
766: return \"addqb %2,%0\";
767: }
768: return \"addb %2,%0\";
769: }")
770:
771: (define_insn ""
772: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
773: (plus:QI (match_operand:QI 1 "general_operand" "0")
774: (match_operand:QI 2 "general_operand" "g")))]
775: ""
776: "*
777: {
778: if (GET_CODE (operands[1]) == CONST_INT
779: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
780: return \"addqb %1,%0\";
781: return \"addb %1,%0\";
782: }")
783:
784: ;;- All kinds of subtract instructions.
785:
786: (define_insn "subdf3"
787: [(set (match_operand:DF 0 "general_operand" "=fm")
788: (minus:DF (match_operand:DF 1 "general_operand" "0")
789: (match_operand:DF 2 "general_operand" "fmF")))]
790: "TARGET_32081"
791: "subl %2,%0")
792:
793: (define_insn "subsf3"
794: [(set (match_operand:SF 0 "general_operand" "=fm")
795: (minus:SF (match_operand:SF 1 "general_operand" "0")
796: (match_operand:SF 2 "general_operand" "fmF")))]
797: "TARGET_32081"
798: "subf %2,%0")
799:
800: (define_insn ""
801: [(set (reg:SI 17)
802: (minus:SI (reg:SI 17)
803: (match_operand:SI 0 "immediate_operand" "i")))]
804: "GET_CODE (operands[0]) == CONST_INT"
805: "*
806: {
807: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
808: && INTVAL(operands[0]) > -64)
809: return \"adjspb %0\";
810: return \"adjspd %0\";
811: }")
812:
813: (define_insn "subsi3"
814: [(set (match_operand:SI 0 "general_operand" "=g")
815: (minus:SI (match_operand:SI 1 "general_operand" "0")
816: (match_operand:SI 2 "general_operand" "rmn")))]
817: ""
818: "*
819: { if (GET_CODE (operands[2]) == CONST_INT)
820: {
821: int i = INTVAL (operands[2]);
822:
823: if (i <= 8 && i >= -7)
824: return \"addqd %$%n2,%0\";
825: }
826: return \"subd %2,%0\";
827: }")
828:
829: (define_insn "subhi3"
830: [(set (match_operand:HI 0 "general_operand" "=g")
831: (minus:HI (match_operand:HI 1 "general_operand" "0")
832: (match_operand:HI 2 "general_operand" "g")))]
833: ""
834: "*
835: { if (GET_CODE (operands[2]) == CONST_INT)
836: {
837: int i = INTVAL (operands[2]);
838:
839: if (i <= 8 && i >= -7)
840: return \"addqw %$%n2,%0\";
841: }
842: return \"subw %2,%0\";
843: }")
844:
845: (define_insn ""
846: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
847: (minus:HI (match_operand:HI 1 "general_operand" "0")
848: (match_operand:HI 2 "general_operand" "g")))]
849: ""
850: "*
851: {
852: if (GET_CODE (operands[1]) == CONST_INT
853: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
854: return \"addqw %$%n1,%0\";
855: return \"subw %1,%0\";
856: }")
857:
858: (define_insn "subqi3"
859: [(set (match_operand:QI 0 "general_operand" "=g")
860: (minus:QI (match_operand:QI 1 "general_operand" "0")
861: (match_operand:QI 2 "general_operand" "g")))]
862: ""
863: "*
864: { if (GET_CODE (operands[2]) == CONST_INT)
865: {
866: int i = INTVAL (operands[2]);
867:
868: if (i <= 8 && i >= -7)
869: return \"addqb %$%n2,%0\";
870: }
871: return \"subb %2,%0\";
872: }")
873:
874: (define_insn ""
875: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
876: (minus:QI (match_operand:QI 1 "general_operand" "0")
877: (match_operand:QI 2 "general_operand" "g")))]
878: ""
879: "*
880: {
881: if (GET_CODE (operands[1]) == CONST_INT
882: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
883: return \"addqb %$%n1,%0\";
884: return \"subb %1,%0\";
885: }")
886:
887: ;;- Multiply instructions.
888:
889: (define_insn "muldf3"
890: [(set (match_operand:DF 0 "general_operand" "=fm")
891: (mult:DF (match_operand:DF 1 "general_operand" "%0")
892: (match_operand:DF 2 "general_operand" "fmF")))]
893: "TARGET_32081"
894: "mull %2,%0")
895:
896: (define_insn "mulsf3"
897: [(set (match_operand:SF 0 "general_operand" "=fm")
898: (mult:SF (match_operand:SF 1 "general_operand" "%0")
899: (match_operand:SF 2 "general_operand" "fmF")))]
900: "TARGET_32081"
901: "mulf %2,%0")
902:
903: (define_insn "mulsi3"
904: [(set (match_operand:SI 0 "general_operand" "=g")
905: (mult:SI (match_operand:SI 1 "general_operand" "%0")
906: (match_operand:SI 2 "general_operand" "rmn")))]
907: ""
908: "muld %2,%0")
909:
910: (define_insn "mulhi3"
911: [(set (match_operand:HI 0 "general_operand" "=g")
912: (mult:HI (match_operand:HI 1 "general_operand" "%0")
913: (match_operand:HI 2 "general_operand" "g")))]
914: ""
915: "mulw %2,%0")
916:
917: (define_insn "mulqi3"
918: [(set (match_operand:QI 0 "general_operand" "=g")
919: (mult:QI (match_operand:QI 1 "general_operand" "%0")
920: (match_operand:QI 2 "general_operand" "g")))]
921: ""
922: "mulb %2,%0")
923:
924: (define_insn "umulsi3"
925: [(set (match_operand:SI 0 "general_operand" "=g")
926: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 927: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 928: ""
929: "muld %2,%0")
930:
931: (define_insn "umulhi3"
932: [(set (match_operand:HI 0 "general_operand" "=g")
933: (umult:HI (match_operand:HI 1 "general_operand" "%0")
934: (match_operand:HI 2 "general_operand" "g")))]
935: ""
936: "mulw %2,%0")
937:
938: (define_insn "umulqi3"
939: [(set (match_operand:QI 0 "general_operand" "=g")
940: (umult:QI (match_operand:QI 1 "general_operand" "%0")
941: (match_operand:QI 2 "general_operand" "g")))]
942: ""
943: "mulb %2,%0")
944:
945: (define_insn "umulsidi3"
946: [(set (match_operand:DI 0 "general_operand" "=g")
947: (umult:DI (match_operand:SI 1 "general_operand" "0")
948: (match_operand:SI 2 "general_operand" "rmn")))]
949: ""
950: "meid %2,%0")
951:
952: ;;- Divide instructions.
953:
954: (define_insn "divdf3"
955: [(set (match_operand:DF 0 "general_operand" "=fm")
956: (div:DF (match_operand:DF 1 "general_operand" "0")
957: (match_operand:DF 2 "general_operand" "fmF")))]
958: "TARGET_32081"
959: "divl %2,%0")
960:
961: (define_insn "divsf3"
962: [(set (match_operand:SF 0 "general_operand" "=fm")
963: (div:SF (match_operand:SF 1 "general_operand" "0")
964: (match_operand:SF 2 "general_operand" "fmF")))]
965: "TARGET_32081"
966: "divf %2,%0")
967:
968: (define_insn "divsi3"
969: [(set (match_operand:SI 0 "general_operand" "=g")
970: (div:SI (match_operand:SI 1 "general_operand" "0")
971: (match_operand:SI 2 "general_operand" "rmn")))]
972: ""
973: "quod %2,%0")
974:
975: (define_insn "divhi3"
976: [(set (match_operand:HI 0 "general_operand" "=g")
977: (div:HI (match_operand:HI 1 "general_operand" "0")
978: (match_operand:HI 2 "general_operand" "g")))]
979: ""
980: "quow %2,%0")
981:
982: (define_insn "divqi3"
983: [(set (match_operand:QI 0 "general_operand" "=g")
984: (div:QI (match_operand:QI 1 "general_operand" "0")
985: (match_operand:QI 2 "general_operand" "g")))]
986: ""
987: "quob %2,%0")
988:
989: (define_insn "udivsi3"
990: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 991: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 992: (match_operand:SI 2 "general_operand" "rmn")))]
993: ""
994: "*
995: {
996: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
997: return \"deid %2,%0\;movd %1,%0\";
998: }")
999:
1000: (define_insn "udivhi3"
1001: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1002: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1003: (match_operand:HI 2 "general_operand" "g")))]
1004: ""
1005: "*
1006: {
1007: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1008: return \"deiw %2,%0\;movw %1,%0\";
1009: }")
1010:
1011: (define_insn "udivqi3"
1012: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1013: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1014: (match_operand:QI 2 "general_operand" "g")))]
1015: ""
1016: "*
1017: {
1018: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1019: return \"deib %2,%0\;movb %1,%0\";
1020: }")
1021:
1022: ;; Remainder instructions.
1023:
1024: (define_insn "modsi3"
1025: [(set (match_operand:SI 0 "general_operand" "=g")
1026: (mod:SI (match_operand:SI 1 "general_operand" "0")
1027: (match_operand:SI 2 "general_operand" "rmn")))]
1028: ""
1029: "remd %2,%0")
1030:
1031: (define_insn "modhi3"
1032: [(set (match_operand:HI 0 "general_operand" "=g")
1033: (mod:HI (match_operand:HI 1 "general_operand" "0")
1034: (match_operand:HI 2 "general_operand" "g")))]
1035: ""
1036: "remw %2,%0")
1037:
1038: (define_insn "modqi3"
1039: [(set (match_operand:QI 0 "general_operand" "=g")
1040: (mod:QI (match_operand:QI 1 "general_operand" "0")
1041: (match_operand:QI 2 "general_operand" "g")))]
1042: ""
1043: "remb %2,%0")
1044:
1045: (define_insn "umodsi3"
1046: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1047: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1048: (match_operand:SI 2 "general_operand" "rmn")))]
1049: ""
1050: "deid %2,%0")
1051:
1052: (define_insn "umodhi3"
1053: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1054: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1055: (match_operand:HI 2 "general_operand" "g")))]
1056: ""
1057: "deiw %2,%0")
1058:
1059: (define_insn "umodqi3"
1060: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1061: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1062: (match_operand:QI 2 "general_operand" "g")))]
1063: ""
1064: "deib %2,%0")
1065:
1066: ; This isn't be usable in its current form.
1067: ;(define_insn "udivmoddisi4"
1068: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1069: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1070: ; (match_operand:SI 2 "general_operand" "rmn")))
1071: ; (set (subreg:SI (match_dup 0) 0)
1072: ; (umod:SI (match_dup 1) (match_dup 2)))]
1073: ; ""
1074: ; "deid %2,%0")
1075:
1076: ;;- Logical Instructions: AND
1077:
1078: (define_insn "andsi3"
1079: [(set (match_operand:SI 0 "general_operand" "=g")
1080: (and:SI (match_operand:SI 1 "general_operand" "%0")
1081: (match_operand:SI 2 "general_operand" "rmn")))]
1082: ""
1083: "*
1084: {
1.1.1.9 root 1085: if (GET_CODE (operands[2]) == CONST_INT)
1086: {
1087: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1088: {
1089: if (INTVAL (operands[2]) == 0xffffff00)
1090: return \"movqb %$0,%0\";
1091: else
1092: {
1093: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1094: INTVAL (operands[2]) & 0xff);
1095: return \"andb %2,%0\";
1096: }
1097: }
1098: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1099: {
1100: if (INTVAL (operands[2]) == 0xffff0000)
1101: return \"movqw %$0,%0\";
1102: else
1103: {
1104: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1105: INTVAL (operands[2]) & 0xffff);
1106: return \"andw %2,%0\";
1107: }
1108: }
1109: }
1.1 root 1110: return \"andd %2,%0\";
1111: }")
1112:
1113: (define_insn "andhi3"
1114: [(set (match_operand:HI 0 "general_operand" "=g")
1115: (and:HI (match_operand:HI 1 "general_operand" "%0")
1116: (match_operand:HI 2 "general_operand" "g")))]
1117: ""
1118: "*
1119: {
1120: if (GET_CODE (operands[2]) == CONST_INT
1121: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1.1.1.9 root 1122: {
1123: if (INTVAL (operands[2]) == 0xffffff00)
1124: return \"movqb %$0,%0\";
1125: else
1126: {
1127: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1128: INTVAL (operands[2]) & 0xff);
1129: return \"andb %2,%0\";
1130: }
1.1 root 1131: }
1132: return \"andw %2,%0\";
1133: }")
1134:
1135: (define_insn "andqi3"
1136: [(set (match_operand:QI 0 "general_operand" "=g")
1137: (and:QI (match_operand:QI 1 "general_operand" "%0")
1138: (match_operand:QI 2 "general_operand" "g")))]
1139: ""
1140: "andb %2,%0")
1141:
1142: (define_insn "andcbsi3"
1143: [(set (match_operand:SI 0 "general_operand" "=g")
1144: (and:SI (match_operand:SI 1 "general_operand" "0")
1145: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1146: ""
1147: "*
1148: {
1149: if (GET_CODE (operands[2]) == CONST_INT)
1150: {
1151: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1152: return \"bicb %2,%0\";
1153: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1154: return \"bicw %2,%0\";
1155: }
1156: return \"bicd %2,%0\";
1157: }")
1158:
1159: (define_insn ""
1160: [(set (match_operand:SI 0 "general_operand" "=g")
1161: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1162: (match_operand:SI 2 "general_operand" "0")))]
1163: ""
1164: "*
1165: {
1166: if (GET_CODE (operands[1]) == CONST_INT)
1167: {
1168: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1169: return \"bicb %1,%0\";
1170: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1171: return \"bicw %1,%0\";
1172: }
1173: return \"bicd %1,%0\";
1174: }")
1175:
1176: (define_insn "andcbhi3"
1177: [(set (match_operand:HI 0 "general_operand" "=g")
1178: (and:HI (match_operand:HI 1 "general_operand" "%0")
1179: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1180: ""
1181: "*
1182: {
1183: if (GET_CODE (operands[2]) == CONST_INT
1184: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1185: return \"bicb %2,%0\";
1186: return \"bicw %2,%0\";
1187: }")
1188:
1189: (define_insn ""
1190: [(set (match_operand:HI 0 "general_operand" "=g")
1191: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1192: (match_operand:HI 2 "general_operand" "0")))]
1193: ""
1194: "*
1195: {
1196: if (GET_CODE (operands[1]) == CONST_INT
1197: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1198: return \"bicb %1,%0\";
1199: return \"bicw %1,%0\";
1200: }")
1201:
1202: (define_insn "andcbqi3"
1203: [(set (match_operand:QI 0 "general_operand" "=g")
1204: (and:QI (match_operand:QI 1 "general_operand" "%0")
1205: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1206: ""
1207: "bicb %2,%0")
1208:
1209: (define_insn ""
1210: [(set (match_operand:QI 0 "general_operand" "=g")
1211: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1212: (match_operand:QI 2 "general_operand" "0")))]
1213: ""
1214: "bicb %1,%0")
1215:
1216: ;;- Bit set instructions.
1217:
1218: (define_insn "iorsi3"
1219: [(set (match_operand:SI 0 "general_operand" "=g")
1220: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1221: (match_operand:SI 2 "general_operand" "rmn")))]
1222: ""
1223: "*
1224: {
1225: if (GET_CODE (operands[2]) == CONST_INT) {
1226: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1227: return \"orb %2,%0\";
1228: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1229: return \"orw %2,%0\";
1230: }
1231: return \"ord %2,%0\";
1232: }")
1233:
1234: (define_insn "iorhi3"
1235: [(set (match_operand:HI 0 "general_operand" "=g")
1236: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1237: (match_operand:HI 2 "general_operand" "g")))]
1238: ""
1239: "*
1240: {
1241: if (GET_CODE(operands[2]) == CONST_INT &&
1242: (INTVAL(operands[2]) & 0xffffff00) == 0)
1243: return \"orb %2,%0\";
1244: return \"orw %2,%0\";
1245: }")
1246:
1247: (define_insn "iorqi3"
1248: [(set (match_operand:QI 0 "general_operand" "=g")
1249: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1250: (match_operand:QI 2 "general_operand" "g")))]
1251: ""
1252: "orb %2,%0")
1253:
1254: ;;- xor instructions.
1255:
1256: (define_insn "xorsi3"
1257: [(set (match_operand:SI 0 "general_operand" "=g")
1258: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1259: (match_operand:SI 2 "general_operand" "rmn")))]
1260: ""
1261: "*
1262: {
1263: if (GET_CODE (operands[2]) == CONST_INT) {
1264: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1265: return \"xorb %2,%0\";
1266: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1267: return \"xorw %2,%0\";
1268: }
1269: return \"xord %2,%0\";
1270: }")
1271:
1272: (define_insn "xorhi3"
1273: [(set (match_operand:HI 0 "general_operand" "=g")
1274: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1275: (match_operand:HI 2 "general_operand" "g")))]
1276: ""
1277: "*
1278: {
1279: if (GET_CODE(operands[2]) == CONST_INT &&
1280: (INTVAL(operands[2]) & 0xffffff00) == 0)
1281: return \"xorb %2,%0\";
1282: return \"xorw %2,%0\";
1283: }")
1284:
1285: (define_insn "xorqi3"
1286: [(set (match_operand:QI 0 "general_operand" "=g")
1287: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1288: (match_operand:QI 2 "general_operand" "g")))]
1289: ""
1290: "xorb %2,%0")
1291:
1292: (define_insn "negdf2"
1293: [(set (match_operand:DF 0 "general_operand" "=fm<")
1294: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1295: "TARGET_32081"
1296: "negl %1,%0")
1297:
1298: (define_insn "negsf2"
1299: [(set (match_operand:SF 0 "general_operand" "=fm<")
1300: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1301: "TARGET_32081"
1302: "negf %1,%0")
1303:
1304: (define_insn "negsi2"
1305: [(set (match_operand:SI 0 "general_operand" "=g<")
1306: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1307: ""
1308: "negd %1,%0")
1309:
1310: (define_insn "neghi2"
1311: [(set (match_operand:HI 0 "general_operand" "=g<")
1312: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1313: ""
1314: "negw %1,%0")
1315:
1316: (define_insn "negqi2"
1317: [(set (match_operand:QI 0 "general_operand" "=g<")
1318: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1319: ""
1320: "negb %1,%0")
1321:
1322: (define_insn "one_cmplsi2"
1323: [(set (match_operand:SI 0 "general_operand" "=g<")
1324: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1325: ""
1326: "comd %1,%0")
1327:
1328: (define_insn "one_cmplhi2"
1329: [(set (match_operand:HI 0 "general_operand" "=g<")
1330: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1331: ""
1332: "comw %1,%0")
1333:
1334: (define_insn "one_cmplqi2"
1335: [(set (match_operand:QI 0 "general_operand" "=g<")
1336: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1337: ""
1338: "comb %1,%0")
1339:
1340: ;; arithmetic left and right shift operations
1341:
1342: (define_insn "ashlsi3"
1343: [(set (match_operand:SI 0 "general_operand" "=g,g")
1344: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1345: (match_operand:SI 2 "general_operand" "I,rmn")))]
1346: ""
1.1.1.2 root 1347: "* output_shift_insn (operands);")
1.1 root 1348:
1349: (define_insn ""
1350: [(set (match_operand:SI 0 "general_operand" "=g")
1351: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1352: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1353: (const_int 31))))]
1354: ""
1355: "ashd %2,%0")
1356:
1357: (define_insn "ashlhi3"
1358: [(set (match_operand:HI 0 "general_operand" "=g")
1359: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1360: (match_operand:SI 2 "general_operand" "rmn")))]
1361: ""
1362: "*
1363: { if (GET_CODE (operands[2]) == CONST_INT)
1364: if (INTVAL (operands[2]) == 1)
1365: return \"addw %1,%0\";
1366: else if (INTVAL (operands[2]) == 2)
1367: return \"addw %1,%0\;addw %0,%0\";
1368: return \"ashw %2,%0\";
1369: }")
1370:
1371: (define_insn "ashlqi3"
1372: [(set (match_operand:QI 0 "general_operand" "=g")
1373: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1374: (match_operand:SI 2 "general_operand" "rmn")))]
1375: ""
1376: "*
1377: { if (GET_CODE (operands[2]) == CONST_INT)
1378: if (INTVAL (operands[2]) == 1)
1379: return \"addb %1,%0\";
1380: else if (INTVAL (operands[2]) == 2)
1381: return \"addb %1,%0\;addb %0,%0\";
1382: return \"ashb %2,%0\";
1383: }")
1384:
1.1.1.6 root 1385: ;; Arithmetic right shift on the 32k works by negating the shift count.
1386: (define_expand "ashrsi3"
1387: [(set (match_operand:SI 0 "general_operand" "=g")
1388: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1389: (match_operand:SI 2 "general_operand" "g")))]
1390: ""
1391: "
1392: {
1.1.1.7 root 1393: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1394: }")
1395:
1396: (define_expand "ashrhi3"
1397: [(set (match_operand:HI 0 "general_operand" "=g")
1398: (ashift:HI (match_operand:HI 1 "general_operand" "g")
1399: (match_operand:SI 2 "general_operand" "g")))]
1400: ""
1401: "
1402: {
1.1.1.7 root 1403: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1404: }")
1405:
1406: (define_expand "ashrqi3"
1407: [(set (match_operand:QI 0 "general_operand" "=g")
1408: (ashift:QI (match_operand:QI 1 "general_operand" "g")
1409: (match_operand:SI 2 "general_operand" "g")))]
1410: ""
1411: "
1412: {
1.1.1.7 root 1413: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1414: }")
1415:
1.1 root 1416: ;; logical shift instructions
1417:
1418: (define_insn "lshlsi3"
1419: [(set (match_operand:SI 0 "general_operand" "=g")
1420: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1421: (match_operand:SI 2 "general_operand" "rmn")))]
1422: ""
1423: "lshd %2,%0")
1424:
1425: (define_insn ""
1426: [(set (match_operand:SI 0 "general_operand" "=g")
1427: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1428: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1429: (const_int 31))))]
1430: ""
1431: "lshd %2,%0")
1432:
1433: (define_insn "lshlhi3"
1434: [(set (match_operand:HI 0 "general_operand" "=g")
1435: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1436: (match_operand:SI 2 "general_operand" "rmn")))]
1437: ""
1438: "lshw %2,%0")
1439:
1440: (define_insn "lshlqi3"
1441: [(set (match_operand:QI 0 "general_operand" "=g")
1442: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1443: (match_operand:SI 2 "general_operand" "rmn")))]
1444: ""
1445: "lshb %2,%0")
1446:
1.1.1.6 root 1447: ;; Logical right shift on the 32k works by negating the shift count.
1448: (define_expand "lshrsi3"
1449: [(set (match_operand:SI 0 "general_operand" "=g")
1450: (lshift:SI (match_operand:SI 1 "general_operand" "g")
1451: (match_operand:SI 2 "general_operand" "g")))]
1452: ""
1453: "
1454: {
1.1.1.7 root 1455: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1456: }")
1457:
1458: (define_expand "lshrhi3"
1459: [(set (match_operand:HI 0 "general_operand" "=g")
1460: (lshift:HI (match_operand:HI 1 "general_operand" "g")
1461: (match_operand:SI 2 "general_operand" "g")))]
1462: ""
1463: "
1464: {
1.1.1.7 root 1465: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1466: }")
1467:
1468: (define_expand "lshrqi3"
1469: [(set (match_operand:QI 0 "general_operand" "=g")
1470: (lshift:QI (match_operand:QI 1 "general_operand" "g")
1471: (match_operand:SI 2 "general_operand" "g")))]
1472: ""
1473: "
1474: {
1.1.1.7 root 1475: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1476: }")
1477:
1.1 root 1478: ;; Rotate instructions
1479:
1480: (define_insn "rotlsi3"
1481: [(set (match_operand:SI 0 "general_operand" "=g")
1482: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1483: (match_operand:SI 2 "general_operand" "rmn")))]
1484: ""
1485: "rotd %2,%0")
1486:
1487: (define_insn "rotlhi3"
1488: [(set (match_operand:HI 0 "general_operand" "=g")
1489: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1490: (match_operand:SI 2 "general_operand" "rmn")))]
1491: ""
1492: "rotw %2,%0")
1493:
1494: (define_insn "rotlqi3"
1495: [(set (match_operand:QI 0 "general_operand" "=g")
1496: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1497: (match_operand:SI 2 "general_operand" "rmn")))]
1498: ""
1499: "rotb %2,%0")
1.1.1.6 root 1500:
1501: ;; Right rotate on the 32k works by negating the shift count.
1502: (define_expand "rotrsi3"
1503: [(set (match_operand:SI 0 "general_operand" "=g")
1504: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1505: (match_operand:SI 2 "general_operand" "g")))]
1506: ""
1507: "
1508: {
1.1.1.7 root 1509: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1510: }")
1511:
1512: (define_expand "rotrhi3"
1513: [(set (match_operand:HI 0 "general_operand" "=g")
1514: (rotate:HI (match_operand:HI 1 "general_operand" "g")
1515: (match_operand:SI 2 "general_operand" "g")))]
1516: ""
1517: "
1518: {
1.1.1.7 root 1519: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1520: }")
1521:
1522: (define_expand "rotrqi3"
1523: [(set (match_operand:QI 0 "general_operand" "=g")
1524: (rotate:QI (match_operand:QI 1 "general_operand" "g")
1525: (match_operand:SI 2 "general_operand" "g")))]
1526: ""
1527: "
1528: {
1.1.1.7 root 1529: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1530: }")
1.1 root 1531:
1532: ;;- load or push effective address
1533: ;; These come after the move, add, and multiply patterns
1534: ;; because we don't want pushl $1 turned into pushad 1.
1535:
1536: (define_insn ""
1537: [(set (match_operand:SI 0 "general_operand" "=g<")
1538: (match_operand:QI 1 "address_operand" "p"))]
1539: ""
1.1.1.2 root 1540: "*
1541: {
1542: if (REG_P (operands[0])
1543: && GET_CODE (operands[1]) == MULT
1544: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1545: && (INTVAL (XEXP (operands[1], 1)) == 2
1546: || INTVAL (XEXP (operands[1], 1)) == 4))
1547: {
1548: rtx xoperands[3];
1549: xoperands[0] = operands[0];
1550: xoperands[1] = XEXP (operands[1], 0);
1551: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1552: return output_shift_insn (xoperands);
1553: }
1554: return \"addr %a1,%0\";
1555: }")
1.1 root 1556:
1557: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1558: ;;; but slower then using power-of-2 shifts if we can use them
1559: ;
1560: ;(define_insn ""
1561: ; [(set (match_operand:SI 0 "register_operand" "=r")
1562: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1563: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1564: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1565: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1566: ; "indexd %0,%3,%1")
1567: ;
1568: ;(define_insn ""
1569: ; [(set (match_operand:SI 0 "register_operand" "=r")
1570: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1571: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1572: ; (match_operand:SI 3 "general_operand" "rmn")))]
1573: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1574: ; "indexd %0,%2,%3")
1575:
1576: ;; Set, Clear, and Invert bit
1577:
1578: (define_insn ""
1579: [(set (match_operand:SI 0 "general_operand" "=g")
1580: (ior:SI
1581: (ashift:SI (const_int 1)
1582: (match_operand:SI 1 "general_operand" "rmn"))
1583: (match_dup 0)))]
1584: ""
1585: "sbitd %1,%0")
1586:
1587: (define_insn ""
1588: [(set (match_operand:SI 0 "general_operand" "=g")
1589: (ior:SI
1590: (match_dup 0)
1591: (ashift:SI (const_int 1)
1592: (match_operand:SI 1 "general_operand" "rmn"))))]
1593: ""
1594: "sbitd %1,%0")
1595:
1596: (define_insn ""
1597: [(set (match_operand:QI 0 "general_operand" "=g")
1598: (ior:QI
1599: (subreg:QI
1600: (ashift:SI (const_int 1)
1601: (match_operand:QI 1 "general_operand" "rmn")) 0)
1602: (match_dup 0)))]
1603: ""
1604: "sbitb %1,%0")
1605:
1606: (define_insn ""
1607: [(set (match_operand:QI 0 "general_operand" "=g")
1608: (ior:QI
1609: (match_dup 0)
1610: (subreg:QI
1611: (ashift:SI (const_int 1)
1612: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1613: ""
1614: "sbitb %1,%0")
1615:
1616: (define_insn ""
1617: [(set (match_operand:SI 0 "general_operand" "=g")
1618: (and:SI
1619: (not:SI
1620: (ashift:SI (const_int 1)
1621: (match_operand:SI 1 "general_operand" "rmn")))
1622: (match_dup 0)))]
1623: ""
1624: "cbitd %1,%0")
1625:
1626: (define_insn ""
1627: [(set (match_operand:SI 0 "general_operand" "=g")
1628: (and:SI
1629: (match_dup 0)
1630: (not:SI
1631: (ashift:SI (const_int 1)
1632: (match_operand:SI 1 "general_operand" "rmn")))))]
1633: ""
1634: "cbitd %1,%0")
1635:
1636: (define_insn ""
1637: [(set (match_operand:QI 0 "general_operand" "=g")
1638: (and:QI
1639: (subreg:QI
1640: (not:SI
1641: (ashift:SI (const_int 1)
1642: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1643: (match_dup 0)))]
1644: ""
1645: "cbitb %1,%0")
1646:
1647: (define_insn ""
1648: [(set (match_operand:QI 0 "general_operand" "=g")
1649: (and:QI
1650: (match_dup 0)
1651: (subreg:QI
1652: (not:SI
1653: (ashift:SI (const_int 1)
1654: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1655: ""
1656: "cbitb %1,%0")
1657:
1658: (define_insn ""
1659: [(set (match_operand:SI 0 "general_operand" "=g")
1660: (xor:SI
1661: (ashift:SI (const_int 1)
1662: (match_operand:SI 1 "general_operand" "rmn"))
1663: (match_dup 0)))]
1664: ""
1665: "ibitd %1,%0")
1666:
1667: (define_insn ""
1668: [(set (match_operand:SI 0 "general_operand" "=g")
1669: (xor:SI
1670: (match_dup 0)
1671: (ashift:SI (const_int 1)
1672: (match_operand:SI 1 "general_operand" "rmn"))))]
1673: ""
1674: "ibitd %1,%0")
1675:
1676: (define_insn ""
1677: [(set (match_operand:QI 0 "general_operand" "=g")
1678: (xor:QI
1679: (subreg:QI
1680: (ashift:SI (const_int 1)
1681: (match_operand:QI 1 "general_operand" "rmn")) 0)
1682: (match_dup 0)))]
1683: ""
1684: "ibitb %1,%0")
1685:
1686: (define_insn ""
1687: [(set (match_operand:QI 0 "general_operand" "=g")
1688: (xor:QI
1689: (match_dup 0)
1690: (subreg:QI
1691: (ashift:SI (const_int 1)
1692: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1693: ""
1694: "ibitb %1,%0")
1695:
1696: ;; Recognize jbs and jbc instructions.
1697:
1698: (define_insn ""
1699: [(set (cc0)
1.1.1.7 root 1700: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1.1 root 1701: (const_int 1)
1702: (match_operand:SI 1 "general_operand" "rmn")))]
1703: ""
1704: "*
1705: { cc_status.flags = CC_Z_IN_F;
1706: return \"tbitd %1,%0\";
1707: }")
1708:
1709: (define_insn ""
1710: [(set (cc0)
1.1.1.11! root 1711: (compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
! 1712: (const_int 1)
! 1713: (match_operand:SI 1 "general_operand" "rmn"))
! 1714: (const_int 1)))]
1.1 root 1715: ""
1716: "*
1717: { cc_status.flags = CC_Z_IN_NOT_F;
1718: return \"tbitd %1,%0\";
1719: }")
1720:
1721: (define_insn ""
1722: [(set (cc0)
1723: (zero_extract (match_operand:HI 0 "general_operand" "g")
1724: (const_int 1)
1725: (match_operand:HI 1 "general_operand" "g")))]
1726: ""
1727: "*
1728: { cc_status.flags = CC_Z_IN_F;
1729: return \"tbitw %1,%0\";
1730: }")
1731:
1732: (define_insn ""
1733: [(set (cc0)
1.1.1.11! root 1734: (compare (zero_extract (match_operand:HI 0 "general_operand" "g")
! 1735: (const_int 1)
! 1736: (match_operand:HI 1 "general_operand" "rmn"))
! 1737: (const_int 1)))]
1.1 root 1738: ""
1739: "*
1740: { cc_status.flags = CC_Z_IN_NOT_F;
1741: return \"tbitw %1,%0\";
1742: }")
1743:
1744: (define_insn ""
1745: [(set (cc0)
1746: (zero_extract (match_operand:QI 0 "general_operand" "g")
1747: (const_int 1)
1748: (match_operand:QI 1 "general_operand" "g")))]
1749: ""
1750: "*
1751: { cc_status.flags = CC_Z_IN_F;
1752: return \"tbitb %1,%0\";
1753: }")
1754:
1755: (define_insn ""
1756: [(set (cc0)
1.1.1.11! root 1757: (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
! 1758: (const_int 1)
! 1759: (match_operand:QI 1 "general_operand" "rmn"))
! 1760: (const_int 1)))]
1.1 root 1761: ""
1762: "*
1763: { cc_status.flags = CC_Z_IN_NOT_F;
1764: return \"tbitb %1,%0\";
1765: }")
1766:
1767: (define_insn ""
1768: [(set (cc0)
1.1.1.7 root 1769: (and:SI (match_operand:SI 0 "general_operand" "rm")
1.1 root 1770: (match_operand:SI 1 "immediate_operand" "i")))]
1771: "GET_CODE (operands[1]) == CONST_INT
1772: && exact_log2 (INTVAL (operands[1])) >= 0"
1773: "*
1774: {
1775: operands[1]
1776: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1777: cc_status.flags = CC_Z_IN_F;
1778: return \"tbitd %1,%0\";
1779: }")
1780:
1781: ;; extract(base, width, offset)
1782: ;; Signed bitfield extraction is not supported in hardware on the
1783: ;; NS 32032. It is therefore better to let GCC figure out a
1784: ;; good strategy for generating the proper instruction sequence
1785: ;; and represent it as rtl.
1786:
1.1.1.2 root 1787: ;; Optimize the case of extracting a byte or word from a register.
1788: ;; Otherwise we must load a register with the offset of the
1789: ;; chunk we want, and perform an extract insn (each of which
1790: ;; is very expensive). Since we use the stack to do our bit-twiddling
1791: ;; we cannot use it for a destination. Perhaps things are fast
1792: ;; enough on the 32532 that such hacks are not needed.
1793:
1794: (define_insn ""
1795: [(set (match_operand:SI 0 "general_operand" "=ro")
1796: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1797: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1798: (match_operand:SI 3 "const_int" "i")))]
1799: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1800: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1801: "*
1802: {
1803: output_asm_insn (\"movd %1,tos\", operands);
1804: if (INTVAL (operands[2]) == 16)
1805: {
1806: if (INTVAL (operands[3]) == 8)
1807: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1808: else
1809: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1810: }
1811: else
1812: {
1813: if (INTVAL (operands[3]) == 8)
1814: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1815: else if (INTVAL (operands[3]) == 16)
1816: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1817: else
1818: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1819: }
1.1.1.6 root 1820: #if defined(ns32532) || defined(ns32332)
1821: return \"cmpqd %$0,tos # adjsp -4\";
1822: #else
1.1.1.2 root 1823: return \"adjspb %$-4\";
1.1.1.6 root 1824: #endif
1.1.1.2 root 1825: }")
1826:
1827: (define_insn ""
1828: [(set (match_operand:SI 0 "general_operand" "=ro")
1829: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1830: (match_operand:SI 2 "const_int" "i")
1831: (match_operand:SI 3 "const_int" "i")))]
1832: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1833: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1834:
1835: (define_insn "extzv"
1836: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1837: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1838: (match_operand:SI 2 "const_int" "i,i")
1839: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1840: ""
1841: "*
1842: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1843: {
1844: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1845: operands[1] = adj_offsetable_operand (operands[1],
1846: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1847: return \"extsd %1,%0,%3,%2\";
1848: }
1.1 root 1849: else return \"extd %3,%1,%0,%2\";
1850: }")
1851:
1852: (define_insn ""
1.1.1.2 root 1853: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1854: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1855: (match_operand:SI 2 "const_int" "i,i")
1856: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1857: ""
1858: "*
1859: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1860: {
1861: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1862: operands[1] = adj_offsetable_operand (operands[1],
1863: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1864: return \"extsd %1,%0,%3,%2\";
1865: }
1.1 root 1866: else return \"extd %3,%1,%0,%2\";
1867: }")
1868:
1869: (define_insn ""
1870: [(set (match_operand:SI 0 "general_operand" "=g<")
1871: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1872: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1873: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1874: ""
1875: "*
1876: { if (GET_CODE (operands[3]) == CONST_INT)
1877: return \"extsd %1,%0,%3,%2\";
1878: else return \"extd %3,%1,%0,%2\";
1879: }")
1880:
1881: (define_insn "insv"
1.1.1.4 root 1882: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1.1.1.2 root 1883: (match_operand:SI 1 "const_int" "i,i")
1884: (match_operand:SI 2 "general_operand" "rK,n"))
1885: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1886: ""
1887: "*
1888: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1889: {
1.1.1.4 root 1890: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1891: {
1892: operands[0] = adj_offsetable_operand (operands[0],
1893: INTVAL (operands[2]) / 8);
1894: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1895: }
1.1.1.2 root 1896: if (INTVAL (operands[1]) <= 8)
1897: return \"inssb %3,%0,%2,%1\";
1898: else if (INTVAL (operands[1]) <= 16)
1899: return \"inssw %3,%0,%2,%1\";
1900: else
1901: return \"inssd %3,%0,%2,%1\";
1902: }
1903: return \"insd %2,%3,%0,%1\";
1.1 root 1904: }")
1905:
1906: (define_insn ""
1.1.1.4 root 1907: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1.1.1.2 root 1908: (match_operand:SI 1 "const_int" "i,i")
1909: (match_operand:SI 2 "general_operand" "rK,n"))
1910: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1911: ""
1912: "*
1913: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1914: {
1.1.1.4 root 1915: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1916: {
1917: operands[0] = adj_offsetable_operand (operands[0],
1918: INTVAL (operands[2]) / 8);
1919: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1920: }
1.1.1.2 root 1921: if (INTVAL (operands[1]) <= 8)
1922: return \"inssb %3,%0,%2,%1\";
1923: else if (INTVAL (operands[1]) <= 16)
1924: return \"inssw %3,%0,%2,%1\";
1925: else
1926: return \"inssd %3,%0,%2,%1\";
1927: }
1928: return \"insd %2,%3,%0,%1\";
1.1 root 1929: }")
1930:
1931: (define_insn ""
1932: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1933: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1934: (match_operand:SI 2 "general_operand" "rn"))
1935: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1936: ""
1937: "*
1938: { if (GET_CODE (operands[2]) == CONST_INT)
1939: if (INTVAL (operands[1]) <= 8)
1940: return \"inssb %3,%0,%2,%1\";
1941: else if (INTVAL (operands[1]) <= 16)
1942: return \"inssw %3,%0,%2,%1\";
1943: else
1944: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1945: return \"insd %2,%3,%0,%1\";
1.1 root 1946: }")
1947:
1948:
1949: (define_insn "jump"
1950: [(set (pc)
1951: (label_ref (match_operand 0 "" "")))]
1952: ""
1953: "br %l0")
1954:
1955: (define_insn "beq"
1956: [(set (pc)
1957: (if_then_else (eq (cc0)
1958: (const_int 0))
1959: (label_ref (match_operand 0 "" ""))
1960: (pc)))]
1961: ""
1962: "*
1963: { if (cc_prev_status.flags & CC_Z_IN_F)
1964: return \"bfc %l0\";
1965: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1966: return \"bfs %l0\";
1967: else return \"beq %l0\";
1968: }")
1969:
1970: (define_insn "bne"
1971: [(set (pc)
1972: (if_then_else (ne (cc0)
1973: (const_int 0))
1974: (label_ref (match_operand 0 "" ""))
1975: (pc)))]
1976: ""
1977: "*
1978: { if (cc_prev_status.flags & CC_Z_IN_F)
1979: return \"bfs %l0\";
1980: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1981: return \"bfc %l0\";
1982: else return \"bne %l0\";
1983: }")
1984:
1985: (define_insn "bgt"
1986: [(set (pc)
1987: (if_then_else (gt (cc0)
1988: (const_int 0))
1989: (label_ref (match_operand 0 "" ""))
1990: (pc)))]
1991: ""
1992: "bgt %l0")
1993:
1994: (define_insn "bgtu"
1995: [(set (pc)
1996: (if_then_else (gtu (cc0)
1997: (const_int 0))
1998: (label_ref (match_operand 0 "" ""))
1999: (pc)))]
2000: ""
2001: "bhi %l0")
2002:
2003: (define_insn "blt"
2004: [(set (pc)
2005: (if_then_else (lt (cc0)
2006: (const_int 0))
2007: (label_ref (match_operand 0 "" ""))
2008: (pc)))]
2009: ""
2010: "blt %l0")
2011:
2012: (define_insn "bltu"
2013: [(set (pc)
2014: (if_then_else (ltu (cc0)
2015: (const_int 0))
2016: (label_ref (match_operand 0 "" ""))
2017: (pc)))]
2018: ""
2019: "blo %l0")
2020:
2021: (define_insn "bge"
2022: [(set (pc)
2023: (if_then_else (ge (cc0)
2024: (const_int 0))
2025: (label_ref (match_operand 0 "" ""))
2026: (pc)))]
2027: ""
2028: "bge %l0")
2029:
2030: (define_insn "bgeu"
2031: [(set (pc)
2032: (if_then_else (geu (cc0)
2033: (const_int 0))
2034: (label_ref (match_operand 0 "" ""))
2035: (pc)))]
2036: ""
2037: "bhs %l0")
2038:
2039: (define_insn "ble"
2040: [(set (pc)
2041: (if_then_else (le (cc0)
2042: (const_int 0))
2043: (label_ref (match_operand 0 "" ""))
2044: (pc)))]
2045: ""
2046: "ble %l0")
2047:
2048: (define_insn "bleu"
2049: [(set (pc)
2050: (if_then_else (leu (cc0)
2051: (const_int 0))
2052: (label_ref (match_operand 0 "" ""))
2053: (pc)))]
2054: ""
2055: "bls %l0")
2056:
2057: (define_insn ""
2058: [(set (pc)
2059: (if_then_else (eq (cc0)
2060: (const_int 0))
2061: (pc)
2062: (label_ref (match_operand 0 "" ""))))]
2063: ""
2064: "*
2065: { if (cc_prev_status.flags & CC_Z_IN_F)
2066: return \"bfs %l0\";
2067: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2068: return \"bfc %l0\";
2069: else return \"bne %l0\";
2070: }")
2071:
2072: (define_insn ""
2073: [(set (pc)
2074: (if_then_else (ne (cc0)
2075: (const_int 0))
2076: (pc)
2077: (label_ref (match_operand 0 "" ""))))]
2078: ""
2079: "*
2080: { if (cc_prev_status.flags & CC_Z_IN_F)
2081: return \"bfc %l0\";
2082: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2083: return \"bfs %l0\";
2084: else return \"beq %l0\";
2085: }")
2086:
2087: (define_insn ""
2088: [(set (pc)
2089: (if_then_else (gt (cc0)
2090: (const_int 0))
2091: (pc)
2092: (label_ref (match_operand 0 "" ""))))]
2093: ""
2094: "ble %l0")
2095:
2096: (define_insn ""
2097: [(set (pc)
2098: (if_then_else (gtu (cc0)
2099: (const_int 0))
2100: (pc)
2101: (label_ref (match_operand 0 "" ""))))]
2102: ""
2103: "bls %l0")
2104:
2105: (define_insn ""
2106: [(set (pc)
2107: (if_then_else (lt (cc0)
2108: (const_int 0))
2109: (pc)
2110: (label_ref (match_operand 0 "" ""))))]
2111: ""
2112: "bge %l0")
2113:
2114: (define_insn ""
2115: [(set (pc)
2116: (if_then_else (ltu (cc0)
2117: (const_int 0))
2118: (pc)
2119: (label_ref (match_operand 0 "" ""))))]
2120: ""
2121: "bhs %l0")
2122:
2123: (define_insn ""
2124: [(set (pc)
2125: (if_then_else (ge (cc0)
2126: (const_int 0))
2127: (pc)
2128: (label_ref (match_operand 0 "" ""))))]
2129: ""
2130: "blt %l0")
2131:
2132: (define_insn ""
2133: [(set (pc)
2134: (if_then_else (geu (cc0)
2135: (const_int 0))
2136: (pc)
2137: (label_ref (match_operand 0 "" ""))))]
2138: ""
2139: "blo %l0")
2140:
2141: (define_insn ""
2142: [(set (pc)
2143: (if_then_else (le (cc0)
2144: (const_int 0))
2145: (pc)
2146: (label_ref (match_operand 0 "" ""))))]
2147: ""
2148: "bgt %l0")
2149:
2150: (define_insn ""
2151: [(set (pc)
2152: (if_then_else (leu (cc0)
2153: (const_int 0))
2154: (pc)
2155: (label_ref (match_operand 0 "" ""))))]
2156: ""
2157: "bhi %l0")
2158:
2159: ;; Subtract-and-jump and Add-and-jump insns.
2160: ;; These can actually be used for adding numbers in the range -8 to 7
2161:
2162: (define_insn ""
2163: [(set (pc)
2164: (if_then_else
2165: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2166: (match_operand:SI 1 "general_operand" "i"))
2167: (const_int 0))
2168: (label_ref (match_operand 2 "" ""))
2169: (pc)))
2170: (set (match_dup 0)
2171: (minus:SI (match_dup 0)
2172: (match_dup 1)))]
2173: "GET_CODE (operands[1]) == CONST_INT
2174: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2175: "acbd %$%n1,%0,%l2")
2176:
2177: (define_insn ""
2178: [(set (pc)
2179: (if_then_else
2180: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2181: (match_operand:SI 1 "general_operand" "i"))
2182: (const_int 0))
2183: (label_ref (match_operand 2 "" ""))
2184: (pc)))
2185: (set (match_dup 0)
2186: (plus:SI (match_dup 0)
2187: (match_dup 1)))]
2188: "GET_CODE (operands[1]) == CONST_INT
2189: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2190: "acbd %1,%0,%l2")
2191:
2192: ;; Reversed
2193:
2194: (define_insn ""
2195: [(set (pc)
2196: (if_then_else
2197: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2198: (match_operand:SI 1 "general_operand" "i"))
2199: (const_int 0))
2200: (pc)
2201: (label_ref (match_operand 2 "" ""))))
2202: (set (match_dup 0)
2203: (minus:SI (match_dup 0)
2204: (match_dup 1)))]
2205: "GET_CODE (operands[1]) == CONST_INT
2206: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2207: "acbd %$%n1,%0,%l2")
2208:
2209: (define_insn ""
2210: [(set (pc)
2211: (if_then_else
2212: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2213: (match_operand:SI 1 "general_operand" "i"))
2214: (const_int 0))
2215: (pc)
2216: (label_ref (match_operand 2 "" ""))))
2217: (set (match_dup 0)
2218: (plus:SI (match_dup 0)
2219: (match_dup 1)))]
2220: "GET_CODE (operands[1]) == CONST_INT
2221: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2222: "acbd %1,%0,%l2")
2223:
2224: (define_insn "call"
2225: [(call (match_operand:QI 0 "general_operand" "g")
2226: (match_operand:QI 1 "general_operand" "g"))]
2227: ""
2228: "*
2229: {
2230: if (GET_CODE (operands[0]) == MEM)
2231: {
2232: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.4 root 2233: #ifdef GNX_V3
2234: return \"bsr %0\";
2235: #else
1.1.1.2 root 2236: return \"bsr %?%a0\";
1.1.1.4 root 2237: #endif
1.1 root 2238: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.4 root 2239: #ifdef GNX_V3
2240: return \"jsr %0\";
2241: #else
1.1 root 2242: return \"jsr %a0\";
1.1.1.4 root 2243: #endif
1.1 root 2244: }
2245: return \"jsr %0\";
2246: }")
2247:
2248: (define_insn "call_value"
2249: [(set (match_operand 0 "" "fg")
2250: (call (match_operand:QI 1 "general_operand" "g")
2251: (match_operand:QI 2 "general_operand" "g")))]
2252: ""
2253: "*
2254: {
2255: if (GET_CODE (operands[1]) == MEM)
2256: {
2257: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.4 root 2258: #ifdef GNX_V3
2259: return \"bsr %1\";
2260: #else
1.1.1.2 root 2261: return \"bsr %?%a1\";
1.1.1.4 root 2262: #endif
1.1 root 2263: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.4 root 2264: #ifdef GNX_V3
2265: return \"jsr %1\";
2266: #else
1.1 root 2267: return \"jsr %a1\";
1.1.1.4 root 2268: #endif
1.1 root 2269: }
2270: return \"jsr %1\";
2271: }")
2272:
2273: (define_insn "return"
2274: [(return)]
1.1.1.5 root 2275: "0"
1.1 root 2276: "ret 0")
2277:
2278: (define_insn "abssf2"
2279: [(set (match_operand:SF 0 "general_operand" "=fm<")
2280: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2281: "TARGET_32081"
2282: "absf %1,%0")
2283:
2284: (define_insn "absdf2"
2285: [(set (match_operand:DF 0 "general_operand" "=fm<")
2286: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2287: "TARGET_32081"
2288: "absl %1,%0")
2289:
2290: (define_insn "abssi2"
2291: [(set (match_operand:SI 0 "general_operand" "=g<")
2292: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2293: ""
2294: "absd %1,%0")
2295:
2296: (define_insn "abshi2"
2297: [(set (match_operand:HI 0 "general_operand" "=g<")
2298: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2299: ""
2300: "absw %1,%0")
2301:
2302: (define_insn "absqi2"
2303: [(set (match_operand:QI 0 "general_operand" "=g<")
2304: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2305: ""
2306: "absb %1,%0")
2307:
2308: ;;(define_insn "tablejump"
2309: ;; [(set (pc)
2310: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2311: ;; (pc)))]
2312: ;; ""
2313: ;; "cased %0")
2314:
2315: (define_insn "tablejump"
2316: [(set (pc)
2317: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2318: (use (label_ref (match_operand 1 "" "")))]
2319: ""
2320: "*
2321: {
2322: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2323: CODE_LABEL_NUMBER (operands[1]));
2324: return \"casew %0\";
2325: }")
2326:
2327: ;;(define_insn ""
2328: ;; [(set (pc)
2329: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2330: ;; (pc)))]
2331: ;; ""
2332: ;; "caseb %0")
2333:
2334: ;; Scondi instructions
2335: (define_insn "seq"
2336: [(set (match_operand:SI 0 "general_operand" "=g<")
2337: (eq (cc0) (const_int 0)))]
2338: ""
2339: "*
2340: { if (cc_prev_status.flags & CC_Z_IN_F)
2341: return \"sfcd %0\";
2342: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2343: return \"sfsd %0\";
2344: else return \"seqd %0\";
2345: }")
2346:
2347: (define_insn ""
2348: [(set (match_operand:HI 0 "general_operand" "=g<")
2349: (eq (cc0) (const_int 0)))]
2350: ""
2351: "*
2352: { if (cc_prev_status.flags & CC_Z_IN_F)
2353: return \"sfcw %0\";
2354: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2355: return \"sfsw %0\";
2356: else return \"seqw %0\";
2357: }")
2358:
2359: (define_insn ""
2360: [(set (match_operand:QI 0 "general_operand" "=g<")
2361: (eq (cc0) (const_int 0)))]
2362: ""
2363: "*
2364: { if (cc_prev_status.flags & CC_Z_IN_F)
2365: return \"sfcb %0\";
2366: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2367: return \"sfsb %0\";
2368: else return \"seqb %0\";
2369: }")
2370:
2371: (define_insn "sne"
2372: [(set (match_operand:SI 0 "general_operand" "=g<")
2373: (ne (cc0) (const_int 0)))]
2374: ""
2375: "*
2376: { if (cc_prev_status.flags & CC_Z_IN_F)
2377: return \"sfsd %0\";
2378: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2379: return \"sfcd %0\";
2380: else return \"sned %0\";
2381: }")
2382:
2383: (define_insn ""
2384: [(set (match_operand:HI 0 "general_operand" "=g<")
2385: (ne (cc0) (const_int 0)))]
2386: ""
2387: "*
2388: { if (cc_prev_status.flags & CC_Z_IN_F)
2389: return \"sfsw %0\";
2390: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2391: return \"sfcw %0\";
2392: else return \"snew %0\";
2393: }")
2394:
2395: (define_insn ""
2396: [(set (match_operand:QI 0 "general_operand" "=g<")
2397: (ne (cc0) (const_int 0)))]
2398: ""
2399: "*
2400: { if (cc_prev_status.flags & CC_Z_IN_F)
2401: return \"sfsb %0\";
2402: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2403: return \"sfcb %0\";
2404: else return \"sneb %0\";
2405: }")
2406:
2407: (define_insn "sgt"
2408: [(set (match_operand:SI 0 "general_operand" "=g<")
2409: (gt (cc0) (const_int 0)))]
2410: ""
2411: "sgtd %0")
2412:
2413: (define_insn ""
2414: [(set (match_operand:HI 0 "general_operand" "=g<")
2415: (gt (cc0) (const_int 0)))]
2416: ""
2417: "sgtw %0")
2418:
2419: (define_insn ""
2420: [(set (match_operand:QI 0 "general_operand" "=g<")
2421: (gt (cc0) (const_int 0)))]
2422: ""
2423: "sgtb %0")
2424:
2425: (define_insn "sgtu"
2426: [(set (match_operand:SI 0 "general_operand" "=g<")
2427: (gtu (cc0) (const_int 0)))]
2428: ""
2429: "shid %0")
2430:
2431: (define_insn ""
2432: [(set (match_operand:HI 0 "general_operand" "=g<")
2433: (gtu (cc0) (const_int 0)))]
2434: ""
2435: "shiw %0")
2436:
2437: (define_insn ""
2438: [(set (match_operand:QI 0 "general_operand" "=g<")
2439: (gtu (cc0) (const_int 0)))]
2440: ""
2441: "shib %0")
2442:
2443: (define_insn "slt"
2444: [(set (match_operand:SI 0 "general_operand" "=g<")
2445: (lt (cc0) (const_int 0)))]
2446: ""
2447: "sltd %0")
2448:
2449: (define_insn ""
2450: [(set (match_operand:HI 0 "general_operand" "=g<")
2451: (lt (cc0) (const_int 0)))]
2452: ""
2453: "sltw %0")
2454:
2455: (define_insn ""
2456: [(set (match_operand:QI 0 "general_operand" "=g<")
2457: (lt (cc0) (const_int 0)))]
2458: ""
2459: "sltb %0")
2460:
2461: (define_insn "sltu"
2462: [(set (match_operand:SI 0 "general_operand" "=g<")
2463: (ltu (cc0) (const_int 0)))]
2464: ""
2465: "slod %0")
2466:
2467: (define_insn ""
2468: [(set (match_operand:HI 0 "general_operand" "=g<")
2469: (ltu (cc0) (const_int 0)))]
2470: ""
2471: "slow %0")
2472:
2473: (define_insn ""
2474: [(set (match_operand:QI 0 "general_operand" "=g<")
2475: (ltu (cc0) (const_int 0)))]
2476: ""
2477: "slob %0")
2478:
2479: (define_insn "sge"
2480: [(set (match_operand:SI 0 "general_operand" "=g<")
2481: (ge (cc0) (const_int 0)))]
2482: ""
2483: "sged %0")
2484:
2485: (define_insn ""
2486: [(set (match_operand:HI 0 "general_operand" "=g<")
2487: (ge (cc0) (const_int 0)))]
2488: ""
2489: "sgew %0")
2490:
2491: (define_insn ""
2492: [(set (match_operand:QI 0 "general_operand" "=g<")
2493: (ge (cc0) (const_int 0)))]
2494: ""
2495: "sgeb %0")
2496:
2497: (define_insn "sgeu"
2498: [(set (match_operand:SI 0 "general_operand" "=g<")
2499: (geu (cc0) (const_int 0)))]
2500: ""
2501: "shsd %0")
2502:
2503: (define_insn ""
2504: [(set (match_operand:HI 0 "general_operand" "=g<")
2505: (geu (cc0) (const_int 0)))]
2506: ""
2507: "shsw %0")
2508:
2509: (define_insn ""
2510: [(set (match_operand:QI 0 "general_operand" "=g<")
2511: (geu (cc0) (const_int 0)))]
2512: ""
2513: "shsb %0")
2514:
2515: (define_insn "sle"
2516: [(set (match_operand:SI 0 "general_operand" "=g<")
2517: (le (cc0) (const_int 0)))]
2518: ""
2519: "sled %0")
2520:
2521: (define_insn ""
2522: [(set (match_operand:HI 0 "general_operand" "=g<")
2523: (le (cc0) (const_int 0)))]
2524: ""
2525: "slew %0")
2526:
2527: (define_insn ""
2528: [(set (match_operand:QI 0 "general_operand" "=g<")
2529: (le (cc0) (const_int 0)))]
2530: ""
2531: "sleb %0")
2532:
2533: (define_insn "sleu"
2534: [(set (match_operand:SI 0 "general_operand" "=g<")
2535: (leu (cc0) (const_int 0)))]
2536: ""
2537: "slsd %0")
2538:
2539: (define_insn ""
2540: [(set (match_operand:HI 0 "general_operand" "=g<")
2541: (leu (cc0) (const_int 0)))]
2542: ""
2543: "slsw %0")
2544:
2545: (define_insn ""
2546: [(set (match_operand:QI 0 "general_operand" "=g<")
2547: (leu (cc0) (const_int 0)))]
2548: ""
2549: "slsb %0")
2550:
2551: ;;- Local variables:
2552: ;;- mode:emacs-lisp
2553: ;;- comment-start: ";;- "
2554: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2555: ;;- eval: (modify-syntax-entry ?[ "(]")
2556: ;;- eval: (modify-syntax-entry ?] ")[")
2557: ;;- eval: (modify-syntax-entry ?{ "(}")
2558: ;;- eval: (modify-syntax-entry ?} "){")
2559: ;;- End:
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