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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
1.1.1.2 root 48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
1.1 root 51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "general_operand" "g"))]
55: ""
56: "*
1.1.1.2 root 57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
1.1 root 60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "general_operand" "g"))]
64: ""
65: "*
1.1.1.2 root 66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
1.1 root 69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
1.1.1.2 root 75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = dconst0_rtx;
77: return \"cmpl %1,%0\"; }")
1.1 root 78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
1.1.1.2 root 84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = fconst0_rtx;
86: return \"cmpf %1,%0\"; }")
1.1 root 87:
88: (define_insn "cmpdf"
89: [(set (cc0)
90: (minus (match_operand:DF 0 "general_operand" "fmF")
91: (match_operand:DF 1 "general_operand" "fmF")))]
92: "TARGET_32081"
93: "cmpl %0,%1")
94:
95: (define_insn "cmpsf"
96: [(set (cc0)
97: (minus (match_operand:SF 0 "general_operand" "fmF")
98: (match_operand:SF 1 "general_operand" "fmF")))]
99: "TARGET_32081"
100: "cmpf %0,%1")
101:
102: (define_insn "cmpsi"
103: [(set (cc0)
104: (minus (match_operand:SI 0 "general_operand" "rmn")
105: (match_operand:SI 1 "general_operand" "rmn")))]
106: ""
107: "*
108: {
109: if (GET_CODE (operands[1]) == CONST_INT)
110: {
111: int i = INTVAL (operands[1]);
112: if (i <= 7 && i >= -8)
113: {
114: cc_status.flags |= CC_REVERSED;
115: return \"cmpqd %1,%0\";
116: }
117: }
118: cc_status.flags &= ~CC_REVERSED;
119: if (GET_CODE (operands[0]) == CONST_INT)
120: {
121: int i = INTVAL (operands[0]);
122: if (i <= 7 && i >= -8)
123: return \"cmpqd %0,%1\";
124: }
125: return \"cmpd %0,%1\";
126: }")
127:
128: (define_insn "cmphi"
129: [(set (cc0)
130: (minus (match_operand:HI 0 "general_operand" "g")
131: (match_operand:HI 1 "general_operand" "g")))]
132: ""
133: "*
134: {
135: if (GET_CODE (operands[1]) == CONST_INT)
136: {
137: short i = INTVAL (operands[1]);
138: if (i <= 7 && i >= -8)
139: {
140: cc_status.flags |= CC_REVERSED;
141: if (INTVAL (operands[1]) > 7)
142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
143: return \"cmpqw %1,%0\";
144: }
145: }
146: cc_status.flags &= ~CC_REVERSED;
147: if (GET_CODE (operands[0]) == CONST_INT)
148: {
149: short i = INTVAL (operands[0]);
150: if (i <= 7 && i >= -8)
151: {
152: if (INTVAL (operands[0]) > 7)
153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
154: return \"cmpqw %0,%1\";
155: }
156: }
157: return \"cmpw %0,%1\";
158: }")
159:
160: (define_insn "cmpqi"
161: [(set (cc0)
162: (minus (match_operand:QI 0 "general_operand" "g")
163: (match_operand:QI 1 "general_operand" "g")))]
164: ""
165: "*
166: {
167: if (GET_CODE (operands[1]) == CONST_INT)
168: {
169: char i = INTVAL (operands[1]);
170: if (i <= 7 && i >= -8)
171: {
172: cc_status.flags |= CC_REVERSED;
173: if (INTVAL (operands[1]) > 7)
174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
175: return \"cmpqb %1,%0\";
176: }
177: }
178: cc_status.flags &= ~CC_REVERSED;
179: if (GET_CODE (operands[0]) == CONST_INT)
180: {
181: char i = INTVAL (operands[0]);
182: if (i <= 7 && i >= -8)
183: {
184: if (INTVAL (operands[0]) > 7)
185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
186: return \"cmpqb %0,%1\";
187: }
188: }
189: return \"cmpb %0,%1\";
190: }")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
246: {
247: /* Is there a better machine-independent way to to this? */
248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
249: return \"movd %1,%0\";
250: }
251: else return \"movd %1,%0\";
252: }")
253:
254: (define_insn ""
255: [(set (match_operand:TI 0 "memory_operand" "=m")
256: (match_operand:TI 1 "memory_operand" "m"))]
257: ""
258: "movmd %1,%0,4")
259:
260: (define_insn "movdi"
261: [(set (match_operand:DI 0 "general_operand" "=g<")
1.1.1.3 ! root 262: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 263: ""
264: "* return output_move_double (operands); ")
265:
266: (define_insn "movsi"
267: [(set (match_operand:SI 0 "general_operand" "=g<")
268: (match_operand:SI 1 "general_operand" "gx"))]
269: ""
270: "*
271: { if (GET_CODE (operands[1]) == CONST_INT)
272: {
273: int i = INTVAL (operands[1]);
274: if (i <= 7 && i >= -8)
275: return \"movqd %1,%0\";
276: if (i < 0x4000 && i >= -0x4000)
1.1.1.2 root 277: return \"addr @%c1,%0\";
1.1 root 278: return \"movd %1,%0\";
279: }
280: else if (GET_CODE (operands[1]) == REG)
281: if (REGNO (operands[1]) < 16)
282: return \"movd %1,%0\";
283: else if (REGNO (operands[1]) == 16)
284: return \"addr 0(fp),%0\";
285: else return \"addr tos,%0\";
286: else if (GET_CODE (operands[1]) == MEM)
287: return \"movd %1,%0\";
1.1.1.2 root 288: /* Check if this effective address can be
289: calculated faster by pulling it apart. */
290: if (REG_P (operands[0])
291: && GET_CODE (operands[1]) == MULT
292: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
293: && (INTVAL (XEXP (operands[1], 1)) == 2
294: || INTVAL (XEXP (operands[1], 1)) == 4))
295: {
296: rtx xoperands[3];
297: xoperands[0] = operands[0];
298: xoperands[1] = XEXP (operands[1], 0);
299: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
300: return output_shift_insn (xoperands);
301: }
1.1 root 302: return \"addr %a1,%0\";
303: }")
304:
305: (define_insn "movhi"
306: [(set (match_operand:HI 0 "general_operand" "=g<")
307: (match_operand:HI 1 "general_operand" "g"))]
308: ""
309: "*
310: {
311: if (GET_CODE (operands[1]) == CONST_INT)
312: {
313: short i = INTVAL (operands[1]);
314: if (i <= 7 && i >= -8)
315: {
316: if (INTVAL (operands[1]) > 7)
317: operands[1] =
318: gen_rtx (CONST_INT, VOIDmode, i);
319: return \"movqw %1,%0\";
320: }
321: }
322: return \"movw %1,%0\";
323: }")
324:
325: (define_insn "movstricthi"
326: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
327: (match_operand:HI 1 "general_operand" "g"))]
328: ""
329: "*
330: {
331: if (GET_CODE (operands[1]) == CONST_INT
332: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
333: return \"movqw %1,%0\";
334: return \"movw %1,%0\";
335: }")
336:
337: (define_insn "movqi"
338: [(set (match_operand:QI 0 "general_operand" "=g<")
339: (match_operand:QI 1 "general_operand" "g"))]
340: ""
341: "*
342: { if (GET_CODE (operands[1]) == CONST_INT)
343: {
344: char char_val = (char)INTVAL (operands[1]);
345: if (char_val <= 7 && char_val >= -8)
346: {
347: if (INTVAL (operands[1]) > 7)
348: operands[1] =
349: gen_rtx (CONST_INT, VOIDmode, char_val);
350: return \"movqb %1,%0\";
351: }
352: }
353: return \"movb %1,%0\";
354: }")
355:
356: (define_insn "movstrictqi"
357: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
358: (match_operand:QI 1 "general_operand" "g"))]
359: ""
360: "*
361: {
362: if (GET_CODE (operands[1]) == CONST_INT
363: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
364: return \"movqb %1,%0\";
365: return \"movb %1,%0\";
366: }")
367:
368: (define_insn ""
369: [(set (reg:SI 17)
1.1.1.2 root 370: (match_operand:SI 0 "general_operand" "rmn"))]
1.1 root 371: ""
372: "lprd sp,%0")
373:
374: ;; The definition of this insn does not really explain what it does,
375: ;; but it should suffice
376: ;; that anything generated as this insn will be recognized as one
377: ;; and that it won't successfully combine with anything.
378: (define_insn "movstrsi"
379: [(set (match_operand:BLK 0 "general_operand" "=g")
380: (match_operand:BLK 1 "general_operand" "g"))
381: (use (match_operand:SI 2 "general_operand" "rmn"))
382: (clobber (reg:SI 0))
383: (clobber (reg:SI 1))
384: (clobber (reg:SI 2))]
385: ""
386: "*
387: {
388: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
389: abort ();
390: operands[0] = XEXP (operands[0], 0);
391: operands[1] = XEXP (operands[1], 0);
392: if (GET_CODE (operands[0]) == MEM)
393: if (GET_CODE (operands[1]) == MEM)
394: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
395: else
396: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
397: else if (GET_CODE (operands[1]) == MEM)
398: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
399: else
400: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
401:
402: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
403: {
404: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
405: if ((unsigned) INTVAL (operands[2]) <= 7)
406: return \"movqd %2,r0\;movsd\";
407: else
408: return \"movd %2,r0\;movsd\";
409: }
410: else
411: {
412: return \"movd %2,r0\;movsb\";
413: }
414: }")
415:
416: ;; Extension and truncation insns.
417: ;; Those for integer source operand
418: ;; are ordered widest source type first.
419:
420: (define_insn "truncsiqi2"
421: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 422: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 423: ""
424: "movb %1,%0")
425:
426: (define_insn "truncsihi2"
427: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 428: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 429: ""
430: "movw %1,%0")
431:
432: (define_insn "trunchiqi2"
433: [(set (match_operand:QI 0 "general_operand" "=g<")
434: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
435: ""
436: "movb %1,%0")
437:
438: (define_insn "extendhisi2"
439: [(set (match_operand:SI 0 "general_operand" "=g<")
440: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
441: ""
442: "movxwd %1,%0")
443:
444: (define_insn "extendqihi2"
445: [(set (match_operand:HI 0 "general_operand" "=g<")
446: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
447: ""
448: "movxbw %1,%0")
449:
450: (define_insn "extendqisi2"
451: [(set (match_operand:SI 0 "general_operand" "=g<")
452: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
453: ""
454: "movxbd %1,%0")
455:
456: (define_insn "extendsfdf2"
457: [(set (match_operand:DF 0 "general_operand" "=fm<")
458: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
459: "TARGET_32081"
460: "movfl %1,%0")
461:
462: (define_insn "truncdfsf2"
463: [(set (match_operand:SF 0 "general_operand" "=fm<")
464: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
465: "TARGET_32081"
466: "movlf %1,%0")
467:
468: (define_insn "zero_extendhisi2"
469: [(set (match_operand:SI 0 "general_operand" "=g<")
470: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
471: ""
472: "movzwd %1,%0")
473:
474: (define_insn "zero_extendqihi2"
475: [(set (match_operand:HI 0 "general_operand" "=g<")
476: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
477: ""
478: "movzbw %1,%0")
479:
480: (define_insn "zero_extendqisi2"
481: [(set (match_operand:SI 0 "general_operand" "=g<")
482: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
483: ""
484: "movzbd %1,%0")
485:
486: ;; Fix-to-float conversion insns.
487: ;; Note that the ones that start with SImode come first.
488: ;; That is so that an operand that is a CONST_INT
489: ;; (and therefore lacks a specific machine mode).
490: ;; will be recognized as SImode (which is always valid)
491: ;; rather than as QImode or HImode.
492:
493: ;; Rumor has it that the National part does not correctly convert
494: ;; constant ints to floats. This conversion is therefore disabled.
495: ;; A register must be used to perform the conversion.
496:
497: (define_insn "floatsisf2"
498: [(set (match_operand:SF 0 "general_operand" "=fm<")
499: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
500: "TARGET_32081"
501: "movdf %1,%0")
502:
503: (define_insn "floatsidf2"
504: [(set (match_operand:DF 0 "general_operand" "=fm<")
505: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
506: "TARGET_32081"
507: "movdl %1,%0")
508:
509: (define_insn "floathisf2"
510: [(set (match_operand:SF 0 "general_operand" "=fm<")
511: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
512: "TARGET_32081"
513: "movwf %1,%0")
514:
515: (define_insn "floathidf2"
516: [(set (match_operand:DF 0 "general_operand" "=fm<")
517: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
518: "TARGET_32081"
519: "movwl %1,%0")
520:
521: (define_insn "floatqisf2"
522: [(set (match_operand:SF 0 "general_operand" "=fm<")
523: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
524: "TARGET_32081"
525: "movbf %1,%0")
526:
1.1.1.3 ! root 527: ; Some assemblers warn that this insn doesn't work.
! 528: ; Maybe they know something we don't.
! 529: ;(define_insn "floatqidf2"
! 530: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
! 531: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
! 532: ; "TARGET_32081"
! 533: ; "movbl %1,%0")
1.1 root 534:
535: ;; Float-to-fix conversion insns.
536: ;; The sequent compiler always generates "trunc" insns.
537:
538: (define_insn "fixsfqi2"
539: [(set (match_operand:QI 0 "general_operand" "=g<")
540: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
541: "TARGET_32081"
542: "truncfb %1,%0")
543:
544: (define_insn "fixsfhi2"
545: [(set (match_operand:HI 0 "general_operand" "=g<")
546: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
547: "TARGET_32081"
548: "truncfw %1,%0")
549:
550: (define_insn "fixsfsi2"
551: [(set (match_operand:SI 0 "general_operand" "=g<")
552: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
553: "TARGET_32081"
554: "truncfd %1,%0")
555:
556: (define_insn "fixdfqi2"
557: [(set (match_operand:QI 0 "general_operand" "=g<")
558: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
559: "TARGET_32081"
560: "trunclb %1,%0")
561:
562: (define_insn "fixdfhi2"
563: [(set (match_operand:HI 0 "general_operand" "=g<")
564: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
565: "TARGET_32081"
566: "trunclw %1,%0")
567:
568: (define_insn "fixdfsi2"
569: [(set (match_operand:SI 0 "general_operand" "=g<")
570: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
571: "TARGET_32081"
572: "truncld %1,%0")
573:
574: ;; Unsigned
575:
576: (define_insn "fixunssfqi2"
577: [(set (match_operand:QI 0 "general_operand" "=g<")
578: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
579: "TARGET_32081"
580: "truncfb %1,%0")
581:
582: (define_insn "fixunssfhi2"
583: [(set (match_operand:HI 0 "general_operand" "=g<")
584: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
585: "TARGET_32081"
586: "truncfw %1,%0")
587:
588: (define_insn "fixunssfsi2"
589: [(set (match_operand:SI 0 "general_operand" "=g<")
590: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
591: "TARGET_32081"
592: "truncfd %1,%0")
593:
594: (define_insn "fixunsdfqi2"
595: [(set (match_operand:QI 0 "general_operand" "=g<")
596: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
597: "TARGET_32081"
598: "trunclb %1,%0")
599:
600: (define_insn "fixunsdfhi2"
601: [(set (match_operand:HI 0 "general_operand" "=g<")
602: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
603: "TARGET_32081"
604: "trunclw %1,%0")
605:
606: (define_insn "fixunsdfsi2"
607: [(set (match_operand:SI 0 "general_operand" "=g<")
608: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
609: "TARGET_32081"
610: "truncld %1,%0")
611:
612: ;;; These are not yet used by GCC
613: (define_insn "fix_truncsfqi2"
614: [(set (match_operand:QI 0 "general_operand" "=g<")
615: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
616: "TARGET_32081"
617: "truncfb %1,%0")
618:
619: (define_insn "fix_truncsfhi2"
620: [(set (match_operand:HI 0 "general_operand" "=g<")
621: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
622: "TARGET_32081"
623: "truncfw %1,%0")
624:
625: (define_insn "fix_truncsfsi2"
626: [(set (match_operand:SI 0 "general_operand" "=g<")
627: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
628: "TARGET_32081"
629: "truncfd %1,%0")
630:
631: (define_insn "fix_truncdfqi2"
632: [(set (match_operand:QI 0 "general_operand" "=g<")
633: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
634: "TARGET_32081"
635: "trunclb %1,%0")
636:
637: (define_insn "fix_truncdfhi2"
638: [(set (match_operand:HI 0 "general_operand" "=g<")
639: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
640: "TARGET_32081"
641: "trunclw %1,%0")
642:
643: (define_insn "fix_truncdfsi2"
644: [(set (match_operand:SI 0 "general_operand" "=g<")
645: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
646: "TARGET_32081"
647: "truncld %1,%0")
648:
649: ;;- All kinds of add instructions.
650:
651: (define_insn "adddf3"
652: [(set (match_operand:DF 0 "general_operand" "=fm")
653: (plus:DF (match_operand:DF 1 "general_operand" "%0")
654: (match_operand:DF 2 "general_operand" "fmF")))]
655: "TARGET_32081"
656: "addl %2,%0")
657:
658:
659: (define_insn "addsf3"
660: [(set (match_operand:SF 0 "general_operand" "=fm")
661: (plus:SF (match_operand:SF 1 "general_operand" "%0")
662: (match_operand:SF 2 "general_operand" "fmF")))]
663: "TARGET_32081"
664: "addf %2,%0")
665:
666: (define_insn ""
667: [(set (reg:SI 17)
668: (plus:SI (reg:SI 17)
669: (match_operand:SI 0 "immediate_operand" "i")))]
670: "GET_CODE (operands[0]) == CONST_INT"
671: "*
672: {
673: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
674: return \"adjspb %$%n0\";
675: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
676: return \"adjspw %$%n0\";
677: return \"adjspd %$%n0\";
678: }")
679:
680: (define_insn ""
681: [(set (match_operand:SI 0 "general_operand" "=g<")
682: (plus:SI (reg:SI 16)
683: (match_operand:SI 1 "immediate_operand" "i")))]
684: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 685: "addr %c1(fp),%0")
1.1 root 686:
687: (define_insn ""
688: [(set (match_operand:SI 0 "general_operand" "=g<")
689: (plus:SI (reg:SI 17)
690: (match_operand:SI 1 "immediate_operand" "i")))]
691: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 692: "addr %c1(sp),%0")
1.1 root 693:
694: (define_insn "addsi3"
695: [(set (match_operand:SI 0 "general_operand" "=g")
696: (plus:SI (match_operand:SI 1 "general_operand" "%0")
697: (match_operand:SI 2 "general_operand" "rmn")))]
698: ""
699: "*
700: {
701: if (GET_CODE (operands[2]) == CONST_INT)
702: {
703: int i = INTVAL (operands[2]);
704:
705: if (i <= 7 && i >= -8)
706: return \"addqd %2,%0\";
707: else if (GET_CODE (operands[0]) == REG
708: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 709: return \"addr %c2(%0),%0\";
1.1 root 710: }
711: return \"addd %2,%0\";
712: }")
713:
714: (define_insn "addhi3"
715: [(set (match_operand:HI 0 "general_operand" "=g")
716: (plus:HI (match_operand:HI 1 "general_operand" "%0")
717: (match_operand:HI 2 "general_operand" "g")))]
718: ""
719: "*
720: { if (GET_CODE (operands[2]) == CONST_INT)
721: {
722: int i = INTVAL (operands[2]);
723: if (i <= 7 && i >= -8)
724: return \"addqw %2,%0\";
725: }
726: return \"addw %2,%0\";
727: }")
728:
729: (define_insn ""
730: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
731: (plus:HI (match_operand:HI 1 "general_operand" "0")
732: (match_operand:HI 2 "general_operand" "g")))]
733: ""
734: "*
735: {
736: if (GET_CODE (operands[1]) == CONST_INT
737: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
738: return \"addqw %1,%0\";
739: return \"addw %1,%0\";
740: }")
741:
742: (define_insn "addqi3"
743: [(set (match_operand:QI 0 "general_operand" "=g")
744: (plus:QI (match_operand:QI 1 "general_operand" "%0")
745: (match_operand:QI 2 "general_operand" "g")))]
746: ""
747: "*
748: { if (GET_CODE (operands[2]) == CONST_INT)
749: {
750: int i = INTVAL (operands[2]);
751: if (i <= 7 && i >= -8)
752: return \"addqb %2,%0\";
753: }
754: return \"addb %2,%0\";
755: }")
756:
757: (define_insn ""
758: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
759: (plus:QI (match_operand:QI 1 "general_operand" "0")
760: (match_operand:QI 2 "general_operand" "g")))]
761: ""
762: "*
763: {
764: if (GET_CODE (operands[1]) == CONST_INT
765: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
766: return \"addqb %1,%0\";
767: return \"addb %1,%0\";
768: }")
769:
770: ;;- All kinds of subtract instructions.
771:
772: (define_insn "subdf3"
773: [(set (match_operand:DF 0 "general_operand" "=fm")
774: (minus:DF (match_operand:DF 1 "general_operand" "0")
775: (match_operand:DF 2 "general_operand" "fmF")))]
776: "TARGET_32081"
777: "subl %2,%0")
778:
779: (define_insn "subsf3"
780: [(set (match_operand:SF 0 "general_operand" "=fm")
781: (minus:SF (match_operand:SF 1 "general_operand" "0")
782: (match_operand:SF 2 "general_operand" "fmF")))]
783: "TARGET_32081"
784: "subf %2,%0")
785:
786: (define_insn ""
787: [(set (reg:SI 17)
788: (minus:SI (reg:SI 17)
789: (match_operand:SI 0 "immediate_operand" "i")))]
790: "GET_CODE (operands[0]) == CONST_INT"
791: "*
792: {
793: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
794: && INTVAL(operands[0]) > -64)
795: return \"adjspb %0\";
796: return \"adjspd %0\";
797: }")
798:
799: (define_insn "subsi3"
800: [(set (match_operand:SI 0 "general_operand" "=g")
801: (minus:SI (match_operand:SI 1 "general_operand" "0")
802: (match_operand:SI 2 "general_operand" "rmn")))]
803: ""
804: "*
805: { if (GET_CODE (operands[2]) == CONST_INT)
806: {
807: int i = INTVAL (operands[2]);
808:
809: if (i <= 8 && i >= -7)
810: return \"addqd %$%n2,%0\";
811: }
812: return \"subd %2,%0\";
813: }")
814:
815: (define_insn "subhi3"
816: [(set (match_operand:HI 0 "general_operand" "=g")
817: (minus:HI (match_operand:HI 1 "general_operand" "0")
818: (match_operand:HI 2 "general_operand" "g")))]
819: ""
820: "*
821: { if (GET_CODE (operands[2]) == CONST_INT)
822: {
823: int i = INTVAL (operands[2]);
824:
825: if (i <= 8 && i >= -7)
826: return \"addqw %$%n2,%0\";
827: }
828: return \"subw %2,%0\";
829: }")
830:
831: (define_insn ""
832: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
833: (minus:HI (match_operand:HI 1 "general_operand" "0")
834: (match_operand:HI 2 "general_operand" "g")))]
835: ""
836: "*
837: {
838: if (GET_CODE (operands[1]) == CONST_INT
839: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
840: return \"addqw %$%n1,%0\";
841: return \"subw %1,%0\";
842: }")
843:
844: (define_insn "subqi3"
845: [(set (match_operand:QI 0 "general_operand" "=g")
846: (minus:QI (match_operand:QI 1 "general_operand" "0")
847: (match_operand:QI 2 "general_operand" "g")))]
848: ""
849: "*
850: { if (GET_CODE (operands[2]) == CONST_INT)
851: {
852: int i = INTVAL (operands[2]);
853:
854: if (i <= 8 && i >= -7)
855: return \"addqb %$%n2,%0\";
856: }
857: return \"subb %2,%0\";
858: }")
859:
860: (define_insn ""
861: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
862: (minus:QI (match_operand:QI 1 "general_operand" "0")
863: (match_operand:QI 2 "general_operand" "g")))]
864: ""
865: "*
866: {
867: if (GET_CODE (operands[1]) == CONST_INT
868: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
869: return \"addqb %$%n1,%0\";
870: return \"subb %1,%0\";
871: }")
872:
873: ;;- Multiply instructions.
874:
875: (define_insn "muldf3"
876: [(set (match_operand:DF 0 "general_operand" "=fm")
877: (mult:DF (match_operand:DF 1 "general_operand" "%0")
878: (match_operand:DF 2 "general_operand" "fmF")))]
879: "TARGET_32081"
880: "mull %2,%0")
881:
882: (define_insn "mulsf3"
883: [(set (match_operand:SF 0 "general_operand" "=fm")
884: (mult:SF (match_operand:SF 1 "general_operand" "%0")
885: (match_operand:SF 2 "general_operand" "fmF")))]
886: "TARGET_32081"
887: "mulf %2,%0")
888:
889: (define_insn "mulsi3"
890: [(set (match_operand:SI 0 "general_operand" "=g")
891: (mult:SI (match_operand:SI 1 "general_operand" "%0")
892: (match_operand:SI 2 "general_operand" "rmn")))]
893: ""
894: "muld %2,%0")
895:
896: (define_insn "mulhi3"
897: [(set (match_operand:HI 0 "general_operand" "=g")
898: (mult:HI (match_operand:HI 1 "general_operand" "%0")
899: (match_operand:HI 2 "general_operand" "g")))]
900: ""
901: "mulw %2,%0")
902:
903: (define_insn "mulqi3"
904: [(set (match_operand:QI 0 "general_operand" "=g")
905: (mult:QI (match_operand:QI 1 "general_operand" "%0")
906: (match_operand:QI 2 "general_operand" "g")))]
907: ""
908: "mulb %2,%0")
909:
910: (define_insn "umulsi3"
911: [(set (match_operand:SI 0 "general_operand" "=g")
912: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 913: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 914: ""
915: "muld %2,%0")
916:
917: (define_insn "umulhi3"
918: [(set (match_operand:HI 0 "general_operand" "=g")
919: (umult:HI (match_operand:HI 1 "general_operand" "%0")
920: (match_operand:HI 2 "general_operand" "g")))]
921: ""
922: "mulw %2,%0")
923:
924: (define_insn "umulqi3"
925: [(set (match_operand:QI 0 "general_operand" "=g")
926: (umult:QI (match_operand:QI 1 "general_operand" "%0")
927: (match_operand:QI 2 "general_operand" "g")))]
928: ""
929: "mulb %2,%0")
930:
931: (define_insn "umulsidi3"
932: [(set (match_operand:DI 0 "general_operand" "=g")
933: (umult:DI (match_operand:SI 1 "general_operand" "0")
934: (match_operand:SI 2 "general_operand" "rmn")))]
935: ""
936: "meid %2,%0")
937:
938: ;;- Divide instructions.
939:
940: (define_insn "divdf3"
941: [(set (match_operand:DF 0 "general_operand" "=fm")
942: (div:DF (match_operand:DF 1 "general_operand" "0")
943: (match_operand:DF 2 "general_operand" "fmF")))]
944: "TARGET_32081"
945: "divl %2,%0")
946:
947: (define_insn "divsf3"
948: [(set (match_operand:SF 0 "general_operand" "=fm")
949: (div:SF (match_operand:SF 1 "general_operand" "0")
950: (match_operand:SF 2 "general_operand" "fmF")))]
951: "TARGET_32081"
952: "divf %2,%0")
953:
954: (define_insn "divsi3"
955: [(set (match_operand:SI 0 "general_operand" "=g")
956: (div:SI (match_operand:SI 1 "general_operand" "0")
957: (match_operand:SI 2 "general_operand" "rmn")))]
958: ""
959: "quod %2,%0")
960:
961: (define_insn "divhi3"
962: [(set (match_operand:HI 0 "general_operand" "=g")
963: (div:HI (match_operand:HI 1 "general_operand" "0")
964: (match_operand:HI 2 "general_operand" "g")))]
965: ""
966: "quow %2,%0")
967:
968: (define_insn "divqi3"
969: [(set (match_operand:QI 0 "general_operand" "=g")
970: (div:QI (match_operand:QI 1 "general_operand" "0")
971: (match_operand:QI 2 "general_operand" "g")))]
972: ""
973: "quob %2,%0")
974:
975: (define_insn "udivsi3"
976: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 977: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 978: (match_operand:SI 2 "general_operand" "rmn")))]
979: ""
980: "*
981: {
982: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
983: return \"deid %2,%0\;movd %1,%0\";
984: }")
985:
986: (define_insn "udivhi3"
987: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 988: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 989: (match_operand:HI 2 "general_operand" "g")))]
990: ""
991: "*
992: {
993: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
994: return \"deiw %2,%0\;movw %1,%0\";
995: }")
996:
997: (define_insn "udivqi3"
998: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 999: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1000: (match_operand:QI 2 "general_operand" "g")))]
1001: ""
1002: "*
1003: {
1004: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1005: return \"deib %2,%0\;movb %1,%0\";
1006: }")
1007:
1008: ;; Remainder instructions.
1009:
1010: (define_insn "modsi3"
1011: [(set (match_operand:SI 0 "general_operand" "=g")
1012: (mod:SI (match_operand:SI 1 "general_operand" "0")
1013: (match_operand:SI 2 "general_operand" "rmn")))]
1014: ""
1015: "remd %2,%0")
1016:
1017: (define_insn "modhi3"
1018: [(set (match_operand:HI 0 "general_operand" "=g")
1019: (mod:HI (match_operand:HI 1 "general_operand" "0")
1020: (match_operand:HI 2 "general_operand" "g")))]
1021: ""
1022: "remw %2,%0")
1023:
1024: (define_insn "modqi3"
1025: [(set (match_operand:QI 0 "general_operand" "=g")
1026: (mod:QI (match_operand:QI 1 "general_operand" "0")
1027: (match_operand:QI 2 "general_operand" "g")))]
1028: ""
1029: "remb %2,%0")
1030:
1031: (define_insn "umodsi3"
1032: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1033: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1034: (match_operand:SI 2 "general_operand" "rmn")))]
1035: ""
1036: "deid %2,%0")
1037:
1038: (define_insn "umodhi3"
1039: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1040: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1041: (match_operand:HI 2 "general_operand" "g")))]
1042: ""
1043: "deiw %2,%0")
1044:
1045: (define_insn "umodqi3"
1046: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1047: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1048: (match_operand:QI 2 "general_operand" "g")))]
1049: ""
1050: "deib %2,%0")
1051:
1052: ; This isn't be usable in its current form.
1053: ;(define_insn "udivmoddisi4"
1054: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1055: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1056: ; (match_operand:SI 2 "general_operand" "rmn")))
1057: ; (set (subreg:SI (match_dup 0) 0)
1058: ; (umod:SI (match_dup 1) (match_dup 2)))]
1059: ; ""
1060: ; "deid %2,%0")
1061:
1062: ;;- Logical Instructions: AND
1063:
1064: (define_insn "andsi3"
1065: [(set (match_operand:SI 0 "general_operand" "=g")
1066: (and:SI (match_operand:SI 1 "general_operand" "%0")
1067: (match_operand:SI 2 "general_operand" "rmn")))]
1068: ""
1069: "*
1070: {
1071: if (GET_CODE (operands[2]) == CONST_INT) {
1072: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1073: if (INTVAL (operands[2]) == 0xffffff00)
1074: return \"movqb %$0,%0\";
1075: else {
1076: INTVAL (operands[2]) &= 0xff;
1077: return \"andb %2,%0\";
1078: }
1079: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1080: if (INTVAL (operands[2]) == 0xffff0000)
1081: return \"movqw %$0,%0\";
1082: else {
1083: INTVAL (operands[2]) &= 0xffff;
1084: return \"andw %2,%0\";
1085: }
1086: }
1087: return \"andd %2,%0\";
1088: }")
1089:
1090: (define_insn "andhi3"
1091: [(set (match_operand:HI 0 "general_operand" "=g")
1092: (and:HI (match_operand:HI 1 "general_operand" "%0")
1093: (match_operand:HI 2 "general_operand" "g")))]
1094: ""
1095: "*
1096: {
1097: if (GET_CODE (operands[2]) == CONST_INT
1098: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1099: if (INTVAL (operands[2]) == 0xffffff00)
1100: return \"movqb %$0,%0\";
1101: else {
1102: INTVAL (operands[2]) &= 0xff;
1103: return \"andb %2,%0\";
1104: }
1105: return \"andw %2,%0\";
1106: }")
1107:
1108: (define_insn "andqi3"
1109: [(set (match_operand:QI 0 "general_operand" "=g")
1110: (and:QI (match_operand:QI 1 "general_operand" "%0")
1111: (match_operand:QI 2 "general_operand" "g")))]
1112: ""
1113: "andb %2,%0")
1114:
1115: (define_insn "andcbsi3"
1116: [(set (match_operand:SI 0 "general_operand" "=g")
1117: (and:SI (match_operand:SI 1 "general_operand" "0")
1118: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1119: ""
1120: "*
1121: {
1122: if (GET_CODE (operands[2]) == CONST_INT)
1123: {
1124: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1125: return \"bicb %2,%0\";
1126: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1127: return \"bicw %2,%0\";
1128: }
1129: return \"bicd %2,%0\";
1130: }")
1131:
1132: (define_insn ""
1133: [(set (match_operand:SI 0 "general_operand" "=g")
1134: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1135: (match_operand:SI 2 "general_operand" "0")))]
1136: ""
1137: "*
1138: {
1139: if (GET_CODE (operands[1]) == CONST_INT)
1140: {
1141: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1142: return \"bicb %1,%0\";
1143: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1144: return \"bicw %1,%0\";
1145: }
1146: return \"bicd %1,%0\";
1147: }")
1148:
1149: (define_insn "andcbhi3"
1150: [(set (match_operand:HI 0 "general_operand" "=g")
1151: (and:HI (match_operand:HI 1 "general_operand" "%0")
1152: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1153: ""
1154: "*
1155: {
1156: if (GET_CODE (operands[2]) == CONST_INT
1157: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1158: return \"bicb %2,%0\";
1159: return \"bicw %2,%0\";
1160: }")
1161:
1162: (define_insn ""
1163: [(set (match_operand:HI 0 "general_operand" "=g")
1164: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1165: (match_operand:HI 2 "general_operand" "0")))]
1166: ""
1167: "*
1168: {
1169: if (GET_CODE (operands[1]) == CONST_INT
1170: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1171: return \"bicb %1,%0\";
1172: return \"bicw %1,%0\";
1173: }")
1174:
1175: (define_insn "andcbqi3"
1176: [(set (match_operand:QI 0 "general_operand" "=g")
1177: (and:QI (match_operand:QI 1 "general_operand" "%0")
1178: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1179: ""
1180: "bicb %2,%0")
1181:
1182: (define_insn ""
1183: [(set (match_operand:QI 0 "general_operand" "=g")
1184: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1185: (match_operand:QI 2 "general_operand" "0")))]
1186: ""
1187: "bicb %1,%0")
1188:
1189: ;;- Bit set instructions.
1190:
1191: (define_insn "iorsi3"
1192: [(set (match_operand:SI 0 "general_operand" "=g")
1193: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1194: (match_operand:SI 2 "general_operand" "rmn")))]
1195: ""
1196: "*
1197: {
1198: if (GET_CODE (operands[2]) == CONST_INT) {
1199: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1200: return \"orb %2,%0\";
1201: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1202: return \"orw %2,%0\";
1203: }
1204: return \"ord %2,%0\";
1205: }")
1206:
1207: (define_insn "iorhi3"
1208: [(set (match_operand:HI 0 "general_operand" "=g")
1209: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1210: (match_operand:HI 2 "general_operand" "g")))]
1211: ""
1212: "*
1213: {
1214: if (GET_CODE(operands[2]) == CONST_INT &&
1215: (INTVAL(operands[2]) & 0xffffff00) == 0)
1216: return \"orb %2,%0\";
1217: return \"orw %2,%0\";
1218: }")
1219:
1220: (define_insn "iorqi3"
1221: [(set (match_operand:QI 0 "general_operand" "=g")
1222: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1223: (match_operand:QI 2 "general_operand" "g")))]
1224: ""
1225: "orb %2,%0")
1226:
1227: ;;- xor instructions.
1228:
1229: (define_insn "xorsi3"
1230: [(set (match_operand:SI 0 "general_operand" "=g")
1231: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1232: (match_operand:SI 2 "general_operand" "rmn")))]
1233: ""
1234: "*
1235: {
1236: if (GET_CODE (operands[2]) == CONST_INT) {
1237: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1238: return \"xorb %2,%0\";
1239: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1240: return \"xorw %2,%0\";
1241: }
1242: return \"xord %2,%0\";
1243: }")
1244:
1245: (define_insn "xorhi3"
1246: [(set (match_operand:HI 0 "general_operand" "=g")
1247: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1248: (match_operand:HI 2 "general_operand" "g")))]
1249: ""
1250: "*
1251: {
1252: if (GET_CODE(operands[2]) == CONST_INT &&
1253: (INTVAL(operands[2]) & 0xffffff00) == 0)
1254: return \"xorb %2,%0\";
1255: return \"xorw %2,%0\";
1256: }")
1257:
1258: (define_insn "xorqi3"
1259: [(set (match_operand:QI 0 "general_operand" "=g")
1260: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1261: (match_operand:QI 2 "general_operand" "g")))]
1262: ""
1263: "xorb %2,%0")
1264:
1265: (define_insn "negdf2"
1266: [(set (match_operand:DF 0 "general_operand" "=fm<")
1267: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1268: "TARGET_32081"
1269: "negl %1,%0")
1270:
1271: (define_insn "negsf2"
1272: [(set (match_operand:SF 0 "general_operand" "=fm<")
1273: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1274: "TARGET_32081"
1275: "negf %1,%0")
1276:
1277: (define_insn "negsi2"
1278: [(set (match_operand:SI 0 "general_operand" "=g<")
1279: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1280: ""
1281: "negd %1,%0")
1282:
1283: (define_insn "neghi2"
1284: [(set (match_operand:HI 0 "general_operand" "=g<")
1285: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1286: ""
1287: "negw %1,%0")
1288:
1289: (define_insn "negqi2"
1290: [(set (match_operand:QI 0 "general_operand" "=g<")
1291: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1292: ""
1293: "negb %1,%0")
1294:
1295: (define_insn "one_cmplsi2"
1296: [(set (match_operand:SI 0 "general_operand" "=g<")
1297: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1298: ""
1299: "comd %1,%0")
1300:
1301: (define_insn "one_cmplhi2"
1302: [(set (match_operand:HI 0 "general_operand" "=g<")
1303: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1304: ""
1305: "comw %1,%0")
1306:
1307: (define_insn "one_cmplqi2"
1308: [(set (match_operand:QI 0 "general_operand" "=g<")
1309: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1310: ""
1311: "comb %1,%0")
1312:
1313: ;; arithmetic left and right shift operations
1314:
1315: (define_insn "ashlsi3"
1316: [(set (match_operand:SI 0 "general_operand" "=g,g")
1317: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1318: (match_operand:SI 2 "general_operand" "I,rmn")))]
1319: ""
1.1.1.2 root 1320: "* output_shift_insn (operands);")
1.1 root 1321:
1322: (define_insn ""
1323: [(set (match_operand:SI 0 "general_operand" "=g")
1324: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1325: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1326: (const_int 31))))]
1327: ""
1328: "ashd %2,%0")
1329:
1330: (define_insn "ashlhi3"
1331: [(set (match_operand:HI 0 "general_operand" "=g")
1332: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1333: (match_operand:SI 2 "general_operand" "rmn")))]
1334: ""
1335: "*
1336: { if (GET_CODE (operands[2]) == CONST_INT)
1337: if (INTVAL (operands[2]) == 1)
1338: return \"addw %1,%0\";
1339: else if (INTVAL (operands[2]) == 2)
1340: return \"addw %1,%0\;addw %0,%0\";
1341: return \"ashw %2,%0\";
1342: }")
1343:
1344: (define_insn "ashlqi3"
1345: [(set (match_operand:QI 0 "general_operand" "=g")
1346: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1347: (match_operand:SI 2 "general_operand" "rmn")))]
1348: ""
1349: "*
1350: { if (GET_CODE (operands[2]) == CONST_INT)
1351: if (INTVAL (operands[2]) == 1)
1352: return \"addb %1,%0\";
1353: else if (INTVAL (operands[2]) == 2)
1354: return \"addb %1,%0\;addb %0,%0\";
1355: return \"ashb %2,%0\";
1356: }")
1357:
1358: ;; logical shift instructions
1359:
1360: (define_insn "lshlsi3"
1361: [(set (match_operand:SI 0 "general_operand" "=g")
1362: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1363: (match_operand:SI 2 "general_operand" "rmn")))]
1364: ""
1365: "lshd %2,%0")
1366:
1367: (define_insn ""
1368: [(set (match_operand:SI 0 "general_operand" "=g")
1369: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1370: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1371: (const_int 31))))]
1372: ""
1373: "lshd %2,%0")
1374:
1375: (define_insn "lshlhi3"
1376: [(set (match_operand:HI 0 "general_operand" "=g")
1377: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1378: (match_operand:SI 2 "general_operand" "rmn")))]
1379: ""
1380: "lshw %2,%0")
1381:
1382: (define_insn "lshlqi3"
1383: [(set (match_operand:QI 0 "general_operand" "=g")
1384: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1385: (match_operand:SI 2 "general_operand" "rmn")))]
1386: ""
1387: "lshb %2,%0")
1388:
1389: ;; Rotate instructions
1390:
1391: (define_insn "rotlsi3"
1392: [(set (match_operand:SI 0 "general_operand" "=g")
1393: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1394: (match_operand:SI 2 "general_operand" "rmn")))]
1395: ""
1396: "rotd %2,%0")
1397:
1398: (define_insn "rotlhi3"
1399: [(set (match_operand:HI 0 "general_operand" "=g")
1400: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1401: (match_operand:SI 2 "general_operand" "rmn")))]
1402: ""
1403: "rotw %2,%0")
1404:
1405: (define_insn "rotlqi3"
1406: [(set (match_operand:QI 0 "general_operand" "=g")
1407: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1408: (match_operand:SI 2 "general_operand" "rmn")))]
1409: ""
1410: "rotb %2,%0")
1411:
1412: ;;- load or push effective address
1413: ;; These come after the move, add, and multiply patterns
1414: ;; because we don't want pushl $1 turned into pushad 1.
1415:
1416: (define_insn ""
1417: [(set (match_operand:SI 0 "general_operand" "=g<")
1418: (match_operand:QI 1 "address_operand" "p"))]
1419: ""
1.1.1.2 root 1420: "*
1421: {
1422: if (REG_P (operands[0])
1423: && GET_CODE (operands[1]) == MULT
1424: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1425: && (INTVAL (XEXP (operands[1], 1)) == 2
1426: || INTVAL (XEXP (operands[1], 1)) == 4))
1427: {
1428: rtx xoperands[3];
1429: xoperands[0] = operands[0];
1430: xoperands[1] = XEXP (operands[1], 0);
1431: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1432: return output_shift_insn (xoperands);
1433: }
1434: return \"addr %a1,%0\";
1435: }")
1.1 root 1436:
1437: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1438: ;;; but slower then using power-of-2 shifts if we can use them
1439: ;
1440: ;(define_insn ""
1441: ; [(set (match_operand:SI 0 "register_operand" "=r")
1442: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1443: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1444: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1445: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1446: ; "indexd %0,%3,%1")
1447: ;
1448: ;(define_insn ""
1449: ; [(set (match_operand:SI 0 "register_operand" "=r")
1450: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1451: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1452: ; (match_operand:SI 3 "general_operand" "rmn")))]
1453: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1454: ; "indexd %0,%2,%3")
1455:
1456: ;; Set, Clear, and Invert bit
1457:
1458: (define_insn ""
1459: [(set (match_operand:SI 0 "general_operand" "=g")
1460: (ior:SI
1461: (ashift:SI (const_int 1)
1462: (match_operand:SI 1 "general_operand" "rmn"))
1463: (match_dup 0)))]
1464: ""
1465: "sbitd %1,%0")
1466:
1467: (define_insn ""
1468: [(set (match_operand:SI 0 "general_operand" "=g")
1469: (ior:SI
1470: (match_dup 0)
1471: (ashift:SI (const_int 1)
1472: (match_operand:SI 1 "general_operand" "rmn"))))]
1473: ""
1474: "sbitd %1,%0")
1475:
1476: (define_insn ""
1477: [(set (match_operand:QI 0 "general_operand" "=g")
1478: (ior:QI
1479: (subreg:QI
1480: (ashift:SI (const_int 1)
1481: (match_operand:QI 1 "general_operand" "rmn")) 0)
1482: (match_dup 0)))]
1483: ""
1484: "sbitb %1,%0")
1485:
1486: (define_insn ""
1487: [(set (match_operand:QI 0 "general_operand" "=g")
1488: (ior:QI
1489: (match_dup 0)
1490: (subreg:QI
1491: (ashift:SI (const_int 1)
1492: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1493: ""
1494: "sbitb %1,%0")
1495:
1496: (define_insn ""
1497: [(set (match_operand:SI 0 "general_operand" "=g")
1498: (and:SI
1499: (not:SI
1500: (ashift:SI (const_int 1)
1501: (match_operand:SI 1 "general_operand" "rmn")))
1502: (match_dup 0)))]
1503: ""
1504: "cbitd %1,%0")
1505:
1506: (define_insn ""
1507: [(set (match_operand:SI 0 "general_operand" "=g")
1508: (and:SI
1509: (match_dup 0)
1510: (not:SI
1511: (ashift:SI (const_int 1)
1512: (match_operand:SI 1 "general_operand" "rmn")))))]
1513: ""
1514: "cbitd %1,%0")
1515:
1516: (define_insn ""
1517: [(set (match_operand:QI 0 "general_operand" "=g")
1518: (and:QI
1519: (subreg:QI
1520: (not:SI
1521: (ashift:SI (const_int 1)
1522: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1523: (match_dup 0)))]
1524: ""
1525: "cbitb %1,%0")
1526:
1527: (define_insn ""
1528: [(set (match_operand:QI 0 "general_operand" "=g")
1529: (and:QI
1530: (match_dup 0)
1531: (subreg:QI
1532: (not:SI
1533: (ashift:SI (const_int 1)
1534: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1535: ""
1536: "cbitb %1,%0")
1537:
1538: (define_insn ""
1539: [(set (match_operand:SI 0 "general_operand" "=g")
1540: (xor:SI
1541: (ashift:SI (const_int 1)
1542: (match_operand:SI 1 "general_operand" "rmn"))
1543: (match_dup 0)))]
1544: ""
1545: "ibitd %1,%0")
1546:
1547: (define_insn ""
1548: [(set (match_operand:SI 0 "general_operand" "=g")
1549: (xor:SI
1550: (match_dup 0)
1551: (ashift:SI (const_int 1)
1552: (match_operand:SI 1 "general_operand" "rmn"))))]
1553: ""
1554: "ibitd %1,%0")
1555:
1556: (define_insn ""
1557: [(set (match_operand:QI 0 "general_operand" "=g")
1558: (xor:QI
1559: (subreg:QI
1560: (ashift:SI (const_int 1)
1561: (match_operand:QI 1 "general_operand" "rmn")) 0)
1562: (match_dup 0)))]
1563: ""
1564: "ibitb %1,%0")
1565:
1566: (define_insn ""
1567: [(set (match_operand:QI 0 "general_operand" "=g")
1568: (xor:QI
1569: (match_dup 0)
1570: (subreg:QI
1571: (ashift:SI (const_int 1)
1572: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1573: ""
1574: "ibitb %1,%0")
1575:
1576: ;; Recognize jbs and jbc instructions.
1577:
1578: (define_insn ""
1579: [(set (cc0)
1580: (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1581: (const_int 1)
1582: (match_operand:SI 1 "general_operand" "rmn")))]
1583: ""
1584: "*
1585: { cc_status.flags = CC_Z_IN_F;
1586: return \"tbitd %1,%0\";
1587: }")
1588:
1589: (define_insn ""
1590: [(set (cc0)
1591: (minus (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1592: (const_int 1)
1593: (match_operand:SI 1 "general_operand" "rmn"))
1594: (const_int 1)))]
1595: ""
1596: "*
1597: { cc_status.flags = CC_Z_IN_NOT_F;
1598: return \"tbitd %1,%0\";
1599: }")
1600:
1601: (define_insn ""
1602: [(set (cc0)
1603: (zero_extract (match_operand:HI 0 "general_operand" "g")
1604: (const_int 1)
1605: (match_operand:HI 1 "general_operand" "g")))]
1606: ""
1607: "*
1608: { cc_status.flags = CC_Z_IN_F;
1609: return \"tbitw %1,%0\";
1610: }")
1611:
1612: (define_insn ""
1613: [(set (cc0)
1614: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1615: (const_int 1)
1616: (match_operand:HI 1 "general_operand" "rmn"))
1617: (const_int 1)))]
1618: ""
1619: "*
1620: { cc_status.flags = CC_Z_IN_NOT_F;
1621: return \"tbitw %1,%0\";
1622: }")
1623:
1624: (define_insn ""
1625: [(set (cc0)
1626: (zero_extract (match_operand:QI 0 "general_operand" "g")
1627: (const_int 1)
1628: (match_operand:QI 1 "general_operand" "g")))]
1629: ""
1630: "*
1631: { cc_status.flags = CC_Z_IN_F;
1632: return \"tbitb %1,%0\";
1633: }")
1634:
1635: (define_insn ""
1636: [(set (cc0)
1637: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1638: (const_int 1)
1639: (match_operand:QI 1 "general_operand" "rmn"))
1640: (const_int 1)))]
1641: ""
1642: "*
1643: { cc_status.flags = CC_Z_IN_NOT_F;
1644: return \"tbitb %1,%0\";
1645: }")
1646:
1647: (define_insn ""
1648: [(set (cc0)
1649: (and:SI (match_operand:SI 0 "general_operand" "rmn")
1650: (match_operand:SI 1 "immediate_operand" "i")))]
1651: "GET_CODE (operands[1]) == CONST_INT
1652: && exact_log2 (INTVAL (operands[1])) >= 0"
1653: "*
1654: {
1655: operands[1]
1656: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1657: cc_status.flags = CC_Z_IN_F;
1658: return \"tbitd %1,%0\";
1659: }")
1660:
1661: ;; extract(base, width, offset)
1662: ;; Signed bitfield extraction is not supported in hardware on the
1663: ;; NS 32032. It is therefore better to let GCC figure out a
1664: ;; good strategy for generating the proper instruction sequence
1665: ;; and represent it as rtl.
1666:
1.1.1.2 root 1667: ;; Optimize the case of extracting a byte or word from a register.
1668: ;; Otherwise we must load a register with the offset of the
1669: ;; chunk we want, and perform an extract insn (each of which
1670: ;; is very expensive). Since we use the stack to do our bit-twiddling
1671: ;; we cannot use it for a destination. Perhaps things are fast
1672: ;; enough on the 32532 that such hacks are not needed.
1673:
1674: (define_insn ""
1675: [(set (match_operand:SI 0 "general_operand" "=ro")
1676: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1677: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1678: (match_operand:SI 3 "const_int" "i")))]
1679: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1680: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1681: "*
1682: {
1683: output_asm_insn (\"movd %1,tos\", operands);
1684: if (INTVAL (operands[2]) == 16)
1685: {
1686: if (INTVAL (operands[3]) == 8)
1687: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1688: else
1689: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1690: }
1691: else
1692: {
1693: if (INTVAL (operands[3]) == 8)
1694: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1695: else if (INTVAL (operands[3]) == 16)
1696: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1697: else
1698: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1699: }
1700: return \"adjspb %$-4\";
1701: }")
1702:
1703: (define_insn ""
1704: [(set (match_operand:SI 0 "general_operand" "=ro")
1705: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1706: (match_operand:SI 2 "const_int" "i")
1707: (match_operand:SI 3 "const_int" "i")))]
1708: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1709: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1710:
1711: (define_insn "extzv"
1712: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1713: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1714: (match_operand:SI 2 "const_int" "i,i")
1715: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1716: ""
1717: "*
1718: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1719: {
1720: if (INTVAL (operands[3]) >= 8)
1721: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1722: return \"extsd %1,%0,%3,%2\";
1723: }
1.1 root 1724: else return \"extd %3,%1,%0,%2\";
1725: }")
1726:
1727: (define_insn ""
1.1.1.2 root 1728: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1729: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1730: (match_operand:SI 2 "const_int" "i,i")
1731: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1732: ""
1733: "*
1734: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1735: {
1736: if (INTVAL (operands[3]) >= 8)
1737: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1738: return \"extsd %1,%0,%3,%2\";
1739: }
1.1 root 1740: else return \"extd %3,%1,%0,%2\";
1741: }")
1742:
1743: (define_insn ""
1744: [(set (match_operand:SI 0 "general_operand" "=g<")
1745: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1746: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1747: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1748: ""
1749: "*
1750: { if (GET_CODE (operands[3]) == CONST_INT)
1751: return \"extsd %1,%0,%3,%2\";
1752: else return \"extd %3,%1,%0,%2\";
1753: }")
1754:
1755: (define_insn "insv"
1.1.1.2 root 1756: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "=g,o")
1757: (match_operand:SI 1 "const_int" "i,i")
1758: (match_operand:SI 2 "general_operand" "rK,n"))
1759: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1760: ""
1761: "*
1762: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1763: {
1764: if (INTVAL (operands[2]) >= 8)
1765: operands[0] = plus_constant (operands[0], INTVAL (operands[2]) >> 3);
1766: if (INTVAL (operands[1]) <= 8)
1767: return \"inssb %3,%0,%2,%1\";
1768: else if (INTVAL (operands[1]) <= 16)
1769: return \"inssw %3,%0,%2,%1\";
1770: else
1771: return \"inssd %3,%0,%2,%1\";
1772: }
1773: return \"insd %2,%3,%0,%1\";
1.1 root 1774: }")
1775:
1776: (define_insn ""
1.1.1.2 root 1777: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "=g,o")
1778: (match_operand:SI 1 "const_int" "i,i")
1779: (match_operand:SI 2 "general_operand" "rK,n"))
1780: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1781: ""
1782: "*
1783: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1784: {
1785: if (INTVAL (operands[2]) >= 8)
1786: operands[0] = plus_constant (operands[0], INTVAL (operands[2]) >> 3);
1787: if (INTVAL (operands[1]) <= 8)
1788: return \"inssb %3,%0,%2,%1\";
1789: else if (INTVAL (operands[1]) <= 16)
1790: return \"inssw %3,%0,%2,%1\";
1791: else
1792: return \"inssd %3,%0,%2,%1\";
1793: }
1794: return \"insd %2,%3,%0,%1\";
1.1 root 1795: }")
1796:
1797: (define_insn ""
1798: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1799: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1800: (match_operand:SI 2 "general_operand" "rn"))
1801: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1802: ""
1803: "*
1804: { if (GET_CODE (operands[2]) == CONST_INT)
1805: if (INTVAL (operands[1]) <= 8)
1806: return \"inssb %3,%0,%2,%1\";
1807: else if (INTVAL (operands[1]) <= 16)
1808: return \"inssw %3,%0,%2,%1\";
1809: else
1810: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1811: return \"insd %2,%3,%0,%1\";
1.1 root 1812: }")
1813:
1814:
1815: (define_insn "jump"
1816: [(set (pc)
1817: (label_ref (match_operand 0 "" "")))]
1818: ""
1819: "br %l0")
1820:
1821: (define_insn "beq"
1822: [(set (pc)
1823: (if_then_else (eq (cc0)
1824: (const_int 0))
1825: (label_ref (match_operand 0 "" ""))
1826: (pc)))]
1827: ""
1828: "*
1829: { if (cc_prev_status.flags & CC_Z_IN_F)
1830: return \"bfc %l0\";
1831: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1832: return \"bfs %l0\";
1833: else return \"beq %l0\";
1834: }")
1835:
1836: (define_insn "bne"
1837: [(set (pc)
1838: (if_then_else (ne (cc0)
1839: (const_int 0))
1840: (label_ref (match_operand 0 "" ""))
1841: (pc)))]
1842: ""
1843: "*
1844: { if (cc_prev_status.flags & CC_Z_IN_F)
1845: return \"bfs %l0\";
1846: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1847: return \"bfc %l0\";
1848: else return \"bne %l0\";
1849: }")
1850:
1851: (define_insn "bgt"
1852: [(set (pc)
1853: (if_then_else (gt (cc0)
1854: (const_int 0))
1855: (label_ref (match_operand 0 "" ""))
1856: (pc)))]
1857: ""
1858: "bgt %l0")
1859:
1860: (define_insn "bgtu"
1861: [(set (pc)
1862: (if_then_else (gtu (cc0)
1863: (const_int 0))
1864: (label_ref (match_operand 0 "" ""))
1865: (pc)))]
1866: ""
1867: "bhi %l0")
1868:
1869: (define_insn "blt"
1870: [(set (pc)
1871: (if_then_else (lt (cc0)
1872: (const_int 0))
1873: (label_ref (match_operand 0 "" ""))
1874: (pc)))]
1875: ""
1876: "blt %l0")
1877:
1878: (define_insn "bltu"
1879: [(set (pc)
1880: (if_then_else (ltu (cc0)
1881: (const_int 0))
1882: (label_ref (match_operand 0 "" ""))
1883: (pc)))]
1884: ""
1885: "blo %l0")
1886:
1887: (define_insn "bge"
1888: [(set (pc)
1889: (if_then_else (ge (cc0)
1890: (const_int 0))
1891: (label_ref (match_operand 0 "" ""))
1892: (pc)))]
1893: ""
1894: "bge %l0")
1895:
1896: (define_insn "bgeu"
1897: [(set (pc)
1898: (if_then_else (geu (cc0)
1899: (const_int 0))
1900: (label_ref (match_operand 0 "" ""))
1901: (pc)))]
1902: ""
1903: "bhs %l0")
1904:
1905: (define_insn "ble"
1906: [(set (pc)
1907: (if_then_else (le (cc0)
1908: (const_int 0))
1909: (label_ref (match_operand 0 "" ""))
1910: (pc)))]
1911: ""
1912: "ble %l0")
1913:
1914: (define_insn "bleu"
1915: [(set (pc)
1916: (if_then_else (leu (cc0)
1917: (const_int 0))
1918: (label_ref (match_operand 0 "" ""))
1919: (pc)))]
1920: ""
1921: "bls %l0")
1922:
1923: (define_insn ""
1924: [(set (pc)
1925: (if_then_else (eq (cc0)
1926: (const_int 0))
1927: (pc)
1928: (label_ref (match_operand 0 "" ""))))]
1929: ""
1930: "*
1931: { if (cc_prev_status.flags & CC_Z_IN_F)
1932: return \"bfs %l0\";
1933: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1934: return \"bfc %l0\";
1935: else return \"bne %l0\";
1936: }")
1937:
1938: (define_insn ""
1939: [(set (pc)
1940: (if_then_else (ne (cc0)
1941: (const_int 0))
1942: (pc)
1943: (label_ref (match_operand 0 "" ""))))]
1944: ""
1945: "*
1946: { if (cc_prev_status.flags & CC_Z_IN_F)
1947: return \"bfc %l0\";
1948: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1949: return \"bfs %l0\";
1950: else return \"beq %l0\";
1951: }")
1952:
1953: (define_insn ""
1954: [(set (pc)
1955: (if_then_else (gt (cc0)
1956: (const_int 0))
1957: (pc)
1958: (label_ref (match_operand 0 "" ""))))]
1959: ""
1960: "ble %l0")
1961:
1962: (define_insn ""
1963: [(set (pc)
1964: (if_then_else (gtu (cc0)
1965: (const_int 0))
1966: (pc)
1967: (label_ref (match_operand 0 "" ""))))]
1968: ""
1969: "bls %l0")
1970:
1971: (define_insn ""
1972: [(set (pc)
1973: (if_then_else (lt (cc0)
1974: (const_int 0))
1975: (pc)
1976: (label_ref (match_operand 0 "" ""))))]
1977: ""
1978: "bge %l0")
1979:
1980: (define_insn ""
1981: [(set (pc)
1982: (if_then_else (ltu (cc0)
1983: (const_int 0))
1984: (pc)
1985: (label_ref (match_operand 0 "" ""))))]
1986: ""
1987: "bhs %l0")
1988:
1989: (define_insn ""
1990: [(set (pc)
1991: (if_then_else (ge (cc0)
1992: (const_int 0))
1993: (pc)
1994: (label_ref (match_operand 0 "" ""))))]
1995: ""
1996: "blt %l0")
1997:
1998: (define_insn ""
1999: [(set (pc)
2000: (if_then_else (geu (cc0)
2001: (const_int 0))
2002: (pc)
2003: (label_ref (match_operand 0 "" ""))))]
2004: ""
2005: "blo %l0")
2006:
2007: (define_insn ""
2008: [(set (pc)
2009: (if_then_else (le (cc0)
2010: (const_int 0))
2011: (pc)
2012: (label_ref (match_operand 0 "" ""))))]
2013: ""
2014: "bgt %l0")
2015:
2016: (define_insn ""
2017: [(set (pc)
2018: (if_then_else (leu (cc0)
2019: (const_int 0))
2020: (pc)
2021: (label_ref (match_operand 0 "" ""))))]
2022: ""
2023: "bhi %l0")
2024:
2025: ;; Subtract-and-jump and Add-and-jump insns.
2026: ;; These can actually be used for adding numbers in the range -8 to 7
2027:
2028: (define_insn ""
2029: [(set (pc)
2030: (if_then_else
2031: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2032: (match_operand:SI 1 "general_operand" "i"))
2033: (const_int 0))
2034: (label_ref (match_operand 2 "" ""))
2035: (pc)))
2036: (set (match_dup 0)
2037: (minus:SI (match_dup 0)
2038: (match_dup 1)))]
2039: "GET_CODE (operands[1]) == CONST_INT
2040: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2041: "acbd %$%n1,%0,%l2")
2042:
2043: (define_insn ""
2044: [(set (pc)
2045: (if_then_else
2046: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2047: (match_operand:SI 1 "general_operand" "i"))
2048: (const_int 0))
2049: (label_ref (match_operand 2 "" ""))
2050: (pc)))
2051: (set (match_dup 0)
2052: (plus:SI (match_dup 0)
2053: (match_dup 1)))]
2054: "GET_CODE (operands[1]) == CONST_INT
2055: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2056: "acbd %1,%0,%l2")
2057:
2058: ;; Reversed
2059:
2060: (define_insn ""
2061: [(set (pc)
2062: (if_then_else
2063: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2064: (match_operand:SI 1 "general_operand" "i"))
2065: (const_int 0))
2066: (pc)
2067: (label_ref (match_operand 2 "" ""))))
2068: (set (match_dup 0)
2069: (minus:SI (match_dup 0)
2070: (match_dup 1)))]
2071: "GET_CODE (operands[1]) == CONST_INT
2072: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2073: "acbd %$%n1,%0,%l2")
2074:
2075: (define_insn ""
2076: [(set (pc)
2077: (if_then_else
2078: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2079: (match_operand:SI 1 "general_operand" "i"))
2080: (const_int 0))
2081: (pc)
2082: (label_ref (match_operand 2 "" ""))))
2083: (set (match_dup 0)
2084: (plus:SI (match_dup 0)
2085: (match_dup 1)))]
2086: "GET_CODE (operands[1]) == CONST_INT
2087: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2088: "acbd %1,%0,%l2")
2089:
2090: (define_insn "call"
2091: [(call (match_operand:QI 0 "general_operand" "g")
2092: (match_operand:QI 1 "general_operand" "g"))]
2093: ""
2094: "*
2095: {
2096: if (GET_CODE (operands[0]) == MEM)
2097: {
2098: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.2 root 2099: return \"bsr %?%a0\";
1.1 root 2100: if (GET_CODE (XEXP (operands[0], 0)) == REG)
2101: return \"jsr %a0\";
2102: }
2103: return \"jsr %0\";
2104: }")
2105:
2106: (define_insn "call_value"
2107: [(set (match_operand 0 "" "fg")
2108: (call (match_operand:QI 1 "general_operand" "g")
2109: (match_operand:QI 2 "general_operand" "g")))]
2110: ""
2111: "*
2112: {
2113: if (GET_CODE (operands[1]) == MEM)
2114: {
2115: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.2 root 2116: return \"bsr %?%a1\";
1.1 root 2117: if (GET_CODE (XEXP (operands[1], 0)) == REG)
2118: return \"jsr %a1\";
2119: }
2120: return \"jsr %1\";
2121: }")
2122:
2123: (define_insn "return"
2124: [(return)]
2125: ""
2126: "ret 0")
2127:
2128: (define_insn "abssf2"
2129: [(set (match_operand:SF 0 "general_operand" "=fm<")
2130: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2131: "TARGET_32081"
2132: "absf %1,%0")
2133:
2134: (define_insn "absdf2"
2135: [(set (match_operand:DF 0 "general_operand" "=fm<")
2136: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2137: "TARGET_32081"
2138: "absl %1,%0")
2139:
2140: (define_insn "abssi2"
2141: [(set (match_operand:SI 0 "general_operand" "=g<")
2142: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2143: ""
2144: "absd %1,%0")
2145:
2146: (define_insn "abshi2"
2147: [(set (match_operand:HI 0 "general_operand" "=g<")
2148: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2149: ""
2150: "absw %1,%0")
2151:
2152: (define_insn "absqi2"
2153: [(set (match_operand:QI 0 "general_operand" "=g<")
2154: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2155: ""
2156: "absb %1,%0")
2157:
2158: ;;(define_insn "tablejump"
2159: ;; [(set (pc)
2160: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2161: ;; (pc)))]
2162: ;; ""
2163: ;; "cased %0")
2164:
2165: (define_insn "tablejump"
2166: [(set (pc)
2167: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2168: (use (label_ref (match_operand 1 "" "")))]
2169: ""
2170: "*
2171: {
2172: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2173: CODE_LABEL_NUMBER (operands[1]));
2174: return \"casew %0\";
2175: }")
2176:
2177: ;;(define_insn ""
2178: ;; [(set (pc)
2179: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2180: ;; (pc)))]
2181: ;; ""
2182: ;; "caseb %0")
2183:
2184: ;; Scondi instructions
2185: (define_insn "seq"
2186: [(set (match_operand:SI 0 "general_operand" "=g<")
2187: (eq (cc0) (const_int 0)))]
2188: ""
2189: "*
2190: { if (cc_prev_status.flags & CC_Z_IN_F)
2191: return \"sfcd %0\";
2192: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2193: return \"sfsd %0\";
2194: else return \"seqd %0\";
2195: }")
2196:
2197: (define_insn ""
2198: [(set (match_operand:HI 0 "general_operand" "=g<")
2199: (eq (cc0) (const_int 0)))]
2200: ""
2201: "*
2202: { if (cc_prev_status.flags & CC_Z_IN_F)
2203: return \"sfcw %0\";
2204: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2205: return \"sfsw %0\";
2206: else return \"seqw %0\";
2207: }")
2208:
2209: (define_insn ""
2210: [(set (match_operand:QI 0 "general_operand" "=g<")
2211: (eq (cc0) (const_int 0)))]
2212: ""
2213: "*
2214: { if (cc_prev_status.flags & CC_Z_IN_F)
2215: return \"sfcb %0\";
2216: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2217: return \"sfsb %0\";
2218: else return \"seqb %0\";
2219: }")
2220:
2221: (define_insn "sne"
2222: [(set (match_operand:SI 0 "general_operand" "=g<")
2223: (ne (cc0) (const_int 0)))]
2224: ""
2225: "*
2226: { if (cc_prev_status.flags & CC_Z_IN_F)
2227: return \"sfsd %0\";
2228: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2229: return \"sfcd %0\";
2230: else return \"sned %0\";
2231: }")
2232:
2233: (define_insn ""
2234: [(set (match_operand:HI 0 "general_operand" "=g<")
2235: (ne (cc0) (const_int 0)))]
2236: ""
2237: "*
2238: { if (cc_prev_status.flags & CC_Z_IN_F)
2239: return \"sfsw %0\";
2240: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2241: return \"sfcw %0\";
2242: else return \"snew %0\";
2243: }")
2244:
2245: (define_insn ""
2246: [(set (match_operand:QI 0 "general_operand" "=g<")
2247: (ne (cc0) (const_int 0)))]
2248: ""
2249: "*
2250: { if (cc_prev_status.flags & CC_Z_IN_F)
2251: return \"sfsb %0\";
2252: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2253: return \"sfcb %0\";
2254: else return \"sneb %0\";
2255: }")
2256:
2257: (define_insn "sgt"
2258: [(set (match_operand:SI 0 "general_operand" "=g<")
2259: (gt (cc0) (const_int 0)))]
2260: ""
2261: "sgtd %0")
2262:
2263: (define_insn ""
2264: [(set (match_operand:HI 0 "general_operand" "=g<")
2265: (gt (cc0) (const_int 0)))]
2266: ""
2267: "sgtw %0")
2268:
2269: (define_insn ""
2270: [(set (match_operand:QI 0 "general_operand" "=g<")
2271: (gt (cc0) (const_int 0)))]
2272: ""
2273: "sgtb %0")
2274:
2275: (define_insn "sgtu"
2276: [(set (match_operand:SI 0 "general_operand" "=g<")
2277: (gtu (cc0) (const_int 0)))]
2278: ""
2279: "shid %0")
2280:
2281: (define_insn ""
2282: [(set (match_operand:HI 0 "general_operand" "=g<")
2283: (gtu (cc0) (const_int 0)))]
2284: ""
2285: "shiw %0")
2286:
2287: (define_insn ""
2288: [(set (match_operand:QI 0 "general_operand" "=g<")
2289: (gtu (cc0) (const_int 0)))]
2290: ""
2291: "shib %0")
2292:
2293: (define_insn "slt"
2294: [(set (match_operand:SI 0 "general_operand" "=g<")
2295: (lt (cc0) (const_int 0)))]
2296: ""
2297: "sltd %0")
2298:
2299: (define_insn ""
2300: [(set (match_operand:HI 0 "general_operand" "=g<")
2301: (lt (cc0) (const_int 0)))]
2302: ""
2303: "sltw %0")
2304:
2305: (define_insn ""
2306: [(set (match_operand:QI 0 "general_operand" "=g<")
2307: (lt (cc0) (const_int 0)))]
2308: ""
2309: "sltb %0")
2310:
2311: (define_insn "sltu"
2312: [(set (match_operand:SI 0 "general_operand" "=g<")
2313: (ltu (cc0) (const_int 0)))]
2314: ""
2315: "slod %0")
2316:
2317: (define_insn ""
2318: [(set (match_operand:HI 0 "general_operand" "=g<")
2319: (ltu (cc0) (const_int 0)))]
2320: ""
2321: "slow %0")
2322:
2323: (define_insn ""
2324: [(set (match_operand:QI 0 "general_operand" "=g<")
2325: (ltu (cc0) (const_int 0)))]
2326: ""
2327: "slob %0")
2328:
2329: (define_insn "sge"
2330: [(set (match_operand:SI 0 "general_operand" "=g<")
2331: (ge (cc0) (const_int 0)))]
2332: ""
2333: "sged %0")
2334:
2335: (define_insn ""
2336: [(set (match_operand:HI 0 "general_operand" "=g<")
2337: (ge (cc0) (const_int 0)))]
2338: ""
2339: "sgew %0")
2340:
2341: (define_insn ""
2342: [(set (match_operand:QI 0 "general_operand" "=g<")
2343: (ge (cc0) (const_int 0)))]
2344: ""
2345: "sgeb %0")
2346:
2347: (define_insn "sgeu"
2348: [(set (match_operand:SI 0 "general_operand" "=g<")
2349: (geu (cc0) (const_int 0)))]
2350: ""
2351: "shsd %0")
2352:
2353: (define_insn ""
2354: [(set (match_operand:HI 0 "general_operand" "=g<")
2355: (geu (cc0) (const_int 0)))]
2356: ""
2357: "shsw %0")
2358:
2359: (define_insn ""
2360: [(set (match_operand:QI 0 "general_operand" "=g<")
2361: (geu (cc0) (const_int 0)))]
2362: ""
2363: "shsb %0")
2364:
2365: (define_insn "sle"
2366: [(set (match_operand:SI 0 "general_operand" "=g<")
2367: (le (cc0) (const_int 0)))]
2368: ""
2369: "sled %0")
2370:
2371: (define_insn ""
2372: [(set (match_operand:HI 0 "general_operand" "=g<")
2373: (le (cc0) (const_int 0)))]
2374: ""
2375: "slew %0")
2376:
2377: (define_insn ""
2378: [(set (match_operand:QI 0 "general_operand" "=g<")
2379: (le (cc0) (const_int 0)))]
2380: ""
2381: "sleb %0")
2382:
2383: (define_insn "sleu"
2384: [(set (match_operand:SI 0 "general_operand" "=g<")
2385: (leu (cc0) (const_int 0)))]
2386: ""
2387: "slsd %0")
2388:
2389: (define_insn ""
2390: [(set (match_operand:HI 0 "general_operand" "=g<")
2391: (leu (cc0) (const_int 0)))]
2392: ""
2393: "slsw %0")
2394:
2395: (define_insn ""
2396: [(set (match_operand:QI 0 "general_operand" "=g<")
2397: (leu (cc0) (const_int 0)))]
2398: ""
2399: "slsb %0")
2400:
2401: ;;- Local variables:
2402: ;;- mode:emacs-lisp
2403: ;;- comment-start: ";;- "
2404: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2405: ;;- eval: (modify-syntax-entry ?[ "(]")
2406: ;;- eval: (modify-syntax-entry ?] ")[")
2407: ;;- eval: (modify-syntax-entry ?{ "(}")
2408: ;;- eval: (modify-syntax-entry ?} "){")
2409: ;;- End:
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