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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
1.1.1.2 root 48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
1.1 root 51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "general_operand" "g"))]
55: ""
56: "*
1.1.1.2 root 57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
1.1 root 60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "general_operand" "g"))]
64: ""
65: "*
1.1.1.2 root 66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
1.1 root 69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
1.1.1.2 root 75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = dconst0_rtx;
77: return \"cmpl %1,%0\"; }")
1.1 root 78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
1.1.1.2 root 84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = fconst0_rtx;
86: return \"cmpf %1,%0\"; }")
1.1 root 87:
88: (define_insn "cmpdf"
89: [(set (cc0)
90: (minus (match_operand:DF 0 "general_operand" "fmF")
91: (match_operand:DF 1 "general_operand" "fmF")))]
92: "TARGET_32081"
93: "cmpl %0,%1")
94:
95: (define_insn "cmpsf"
96: [(set (cc0)
97: (minus (match_operand:SF 0 "general_operand" "fmF")
98: (match_operand:SF 1 "general_operand" "fmF")))]
99: "TARGET_32081"
100: "cmpf %0,%1")
101:
102: (define_insn "cmpsi"
103: [(set (cc0)
104: (minus (match_operand:SI 0 "general_operand" "rmn")
105: (match_operand:SI 1 "general_operand" "rmn")))]
106: ""
107: "*
108: {
109: if (GET_CODE (operands[1]) == CONST_INT)
110: {
111: int i = INTVAL (operands[1]);
112: if (i <= 7 && i >= -8)
113: {
114: cc_status.flags |= CC_REVERSED;
115: return \"cmpqd %1,%0\";
116: }
117: }
118: cc_status.flags &= ~CC_REVERSED;
119: if (GET_CODE (operands[0]) == CONST_INT)
120: {
121: int i = INTVAL (operands[0]);
122: if (i <= 7 && i >= -8)
123: return \"cmpqd %0,%1\";
124: }
125: return \"cmpd %0,%1\";
126: }")
127:
128: (define_insn "cmphi"
129: [(set (cc0)
130: (minus (match_operand:HI 0 "general_operand" "g")
131: (match_operand:HI 1 "general_operand" "g")))]
132: ""
133: "*
134: {
135: if (GET_CODE (operands[1]) == CONST_INT)
136: {
137: short i = INTVAL (operands[1]);
138: if (i <= 7 && i >= -8)
139: {
140: cc_status.flags |= CC_REVERSED;
141: if (INTVAL (operands[1]) > 7)
142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
143: return \"cmpqw %1,%0\";
144: }
145: }
146: cc_status.flags &= ~CC_REVERSED;
147: if (GET_CODE (operands[0]) == CONST_INT)
148: {
149: short i = INTVAL (operands[0]);
150: if (i <= 7 && i >= -8)
151: {
152: if (INTVAL (operands[0]) > 7)
153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
154: return \"cmpqw %0,%1\";
155: }
156: }
157: return \"cmpw %0,%1\";
158: }")
159:
160: (define_insn "cmpqi"
161: [(set (cc0)
162: (minus (match_operand:QI 0 "general_operand" "g")
163: (match_operand:QI 1 "general_operand" "g")))]
164: ""
165: "*
166: {
167: if (GET_CODE (operands[1]) == CONST_INT)
168: {
169: char i = INTVAL (operands[1]);
170: if (i <= 7 && i >= -8)
171: {
172: cc_status.flags |= CC_REVERSED;
173: if (INTVAL (operands[1]) > 7)
174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
175: return \"cmpqb %1,%0\";
176: }
177: }
178: cc_status.flags &= ~CC_REVERSED;
179: if (GET_CODE (operands[0]) == CONST_INT)
180: {
181: char i = INTVAL (operands[0]);
182: if (i <= 7 && i >= -8)
183: {
184: if (INTVAL (operands[0]) > 7)
185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
186: return \"cmpqb %0,%1\";
187: }
188: }
189: return \"cmpb %0,%1\";
190: }")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
246: {
247: /* Is there a better machine-independent way to to this? */
248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
249: return \"movd %1,%0\";
250: }
251: else return \"movd %1,%0\";
252: }")
253:
254: (define_insn ""
255: [(set (match_operand:TI 0 "memory_operand" "=m")
256: (match_operand:TI 1 "memory_operand" "m"))]
257: ""
258: "movmd %1,%0,4")
259:
260: (define_insn "movdi"
261: [(set (match_operand:DI 0 "general_operand" "=g<")
1.1.1.3 root 262: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 263: ""
264: "* return output_move_double (operands); ")
265:
266: (define_insn "movsi"
267: [(set (match_operand:SI 0 "general_operand" "=g<")
268: (match_operand:SI 1 "general_operand" "gx"))]
269: ""
270: "*
271: { if (GET_CODE (operands[1]) == CONST_INT)
272: {
273: int i = INTVAL (operands[1]);
274: if (i <= 7 && i >= -8)
275: return \"movqd %1,%0\";
276: if (i < 0x4000 && i >= -0x4000)
1.1.1.4 ! root 277: #ifdef GNX_V3
! 278: return \"addr %c1,%0\";
! 279: #else
1.1.1.2 root 280: return \"addr @%c1,%0\";
1.1.1.4 ! root 281: #endif
1.1 root 282: return \"movd %1,%0\";
283: }
284: else if (GET_CODE (operands[1]) == REG)
285: if (REGNO (operands[1]) < 16)
286: return \"movd %1,%0\";
287: else if (REGNO (operands[1]) == 16)
288: return \"addr 0(fp),%0\";
289: else return \"addr tos,%0\";
290: else if (GET_CODE (operands[1]) == MEM)
291: return \"movd %1,%0\";
1.1.1.2 root 292: /* Check if this effective address can be
293: calculated faster by pulling it apart. */
294: if (REG_P (operands[0])
295: && GET_CODE (operands[1]) == MULT
296: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
297: && (INTVAL (XEXP (operands[1], 1)) == 2
298: || INTVAL (XEXP (operands[1], 1)) == 4))
299: {
300: rtx xoperands[3];
301: xoperands[0] = operands[0];
302: xoperands[1] = XEXP (operands[1], 0);
303: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
304: return output_shift_insn (xoperands);
305: }
1.1 root 306: return \"addr %a1,%0\";
307: }")
308:
309: (define_insn "movhi"
310: [(set (match_operand:HI 0 "general_operand" "=g<")
311: (match_operand:HI 1 "general_operand" "g"))]
312: ""
313: "*
314: {
315: if (GET_CODE (operands[1]) == CONST_INT)
316: {
317: short i = INTVAL (operands[1]);
318: if (i <= 7 && i >= -8)
319: {
320: if (INTVAL (operands[1]) > 7)
321: operands[1] =
322: gen_rtx (CONST_INT, VOIDmode, i);
323: return \"movqw %1,%0\";
324: }
325: }
326: return \"movw %1,%0\";
327: }")
328:
329: (define_insn "movstricthi"
330: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
331: (match_operand:HI 1 "general_operand" "g"))]
332: ""
333: "*
334: {
335: if (GET_CODE (operands[1]) == CONST_INT
336: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
337: return \"movqw %1,%0\";
338: return \"movw %1,%0\";
339: }")
340:
341: (define_insn "movqi"
342: [(set (match_operand:QI 0 "general_operand" "=g<")
343: (match_operand:QI 1 "general_operand" "g"))]
344: ""
345: "*
346: { if (GET_CODE (operands[1]) == CONST_INT)
347: {
348: char char_val = (char)INTVAL (operands[1]);
349: if (char_val <= 7 && char_val >= -8)
350: {
351: if (INTVAL (operands[1]) > 7)
352: operands[1] =
353: gen_rtx (CONST_INT, VOIDmode, char_val);
354: return \"movqb %1,%0\";
355: }
356: }
357: return \"movb %1,%0\";
358: }")
359:
360: (define_insn "movstrictqi"
361: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
362: (match_operand:QI 1 "general_operand" "g"))]
363: ""
364: "*
365: {
366: if (GET_CODE (operands[1]) == CONST_INT
367: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
368: return \"movqb %1,%0\";
369: return \"movb %1,%0\";
370: }")
371:
372: (define_insn ""
373: [(set (reg:SI 17)
1.1.1.2 root 374: (match_operand:SI 0 "general_operand" "rmn"))]
1.1 root 375: ""
376: "lprd sp,%0")
377:
378: ;; The definition of this insn does not really explain what it does,
379: ;; but it should suffice
380: ;; that anything generated as this insn will be recognized as one
381: ;; and that it won't successfully combine with anything.
382: (define_insn "movstrsi"
383: [(set (match_operand:BLK 0 "general_operand" "=g")
384: (match_operand:BLK 1 "general_operand" "g"))
385: (use (match_operand:SI 2 "general_operand" "rmn"))
386: (clobber (reg:SI 0))
387: (clobber (reg:SI 1))
388: (clobber (reg:SI 2))]
389: ""
390: "*
391: {
392: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
393: abort ();
394: operands[0] = XEXP (operands[0], 0);
395: operands[1] = XEXP (operands[1], 0);
396: if (GET_CODE (operands[0]) == MEM)
397: if (GET_CODE (operands[1]) == MEM)
398: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
399: else
400: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
401: else if (GET_CODE (operands[1]) == MEM)
402: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
403: else
404: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
405:
406: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
407: {
408: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
409: if ((unsigned) INTVAL (operands[2]) <= 7)
410: return \"movqd %2,r0\;movsd\";
411: else
412: return \"movd %2,r0\;movsd\";
413: }
414: else
415: {
416: return \"movd %2,r0\;movsb\";
417: }
418: }")
419:
420: ;; Extension and truncation insns.
421: ;; Those for integer source operand
422: ;; are ordered widest source type first.
423:
424: (define_insn "truncsiqi2"
425: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 426: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 427: ""
428: "movb %1,%0")
429:
430: (define_insn "truncsihi2"
431: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 432: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 433: ""
434: "movw %1,%0")
435:
436: (define_insn "trunchiqi2"
437: [(set (match_operand:QI 0 "general_operand" "=g<")
438: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
439: ""
440: "movb %1,%0")
441:
442: (define_insn "extendhisi2"
443: [(set (match_operand:SI 0 "general_operand" "=g<")
444: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
445: ""
446: "movxwd %1,%0")
447:
448: (define_insn "extendqihi2"
449: [(set (match_operand:HI 0 "general_operand" "=g<")
450: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
451: ""
452: "movxbw %1,%0")
453:
454: (define_insn "extendqisi2"
455: [(set (match_operand:SI 0 "general_operand" "=g<")
456: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
457: ""
458: "movxbd %1,%0")
459:
460: (define_insn "extendsfdf2"
461: [(set (match_operand:DF 0 "general_operand" "=fm<")
462: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
463: "TARGET_32081"
464: "movfl %1,%0")
465:
466: (define_insn "truncdfsf2"
467: [(set (match_operand:SF 0 "general_operand" "=fm<")
468: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
469: "TARGET_32081"
470: "movlf %1,%0")
471:
472: (define_insn "zero_extendhisi2"
473: [(set (match_operand:SI 0 "general_operand" "=g<")
474: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
475: ""
476: "movzwd %1,%0")
477:
478: (define_insn "zero_extendqihi2"
479: [(set (match_operand:HI 0 "general_operand" "=g<")
480: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
481: ""
482: "movzbw %1,%0")
483:
484: (define_insn "zero_extendqisi2"
485: [(set (match_operand:SI 0 "general_operand" "=g<")
486: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
487: ""
488: "movzbd %1,%0")
489:
490: ;; Fix-to-float conversion insns.
491: ;; Note that the ones that start with SImode come first.
492: ;; That is so that an operand that is a CONST_INT
493: ;; (and therefore lacks a specific machine mode).
494: ;; will be recognized as SImode (which is always valid)
495: ;; rather than as QImode or HImode.
496:
497: ;; Rumor has it that the National part does not correctly convert
498: ;; constant ints to floats. This conversion is therefore disabled.
499: ;; A register must be used to perform the conversion.
500:
501: (define_insn "floatsisf2"
502: [(set (match_operand:SF 0 "general_operand" "=fm<")
503: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
504: "TARGET_32081"
505: "movdf %1,%0")
506:
507: (define_insn "floatsidf2"
508: [(set (match_operand:DF 0 "general_operand" "=fm<")
509: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
510: "TARGET_32081"
511: "movdl %1,%0")
512:
513: (define_insn "floathisf2"
514: [(set (match_operand:SF 0 "general_operand" "=fm<")
515: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
516: "TARGET_32081"
517: "movwf %1,%0")
518:
519: (define_insn "floathidf2"
520: [(set (match_operand:DF 0 "general_operand" "=fm<")
521: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
522: "TARGET_32081"
523: "movwl %1,%0")
524:
525: (define_insn "floatqisf2"
526: [(set (match_operand:SF 0 "general_operand" "=fm<")
527: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
528: "TARGET_32081"
529: "movbf %1,%0")
530:
1.1.1.3 root 531: ; Some assemblers warn that this insn doesn't work.
532: ; Maybe they know something we don't.
533: ;(define_insn "floatqidf2"
534: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
535: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
536: ; "TARGET_32081"
537: ; "movbl %1,%0")
1.1 root 538:
539: ;; Float-to-fix conversion insns.
540: ;; The sequent compiler always generates "trunc" insns.
541:
542: (define_insn "fixsfqi2"
543: [(set (match_operand:QI 0 "general_operand" "=g<")
544: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
545: "TARGET_32081"
546: "truncfb %1,%0")
547:
548: (define_insn "fixsfhi2"
549: [(set (match_operand:HI 0 "general_operand" "=g<")
550: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
551: "TARGET_32081"
552: "truncfw %1,%0")
553:
554: (define_insn "fixsfsi2"
555: [(set (match_operand:SI 0 "general_operand" "=g<")
556: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
557: "TARGET_32081"
558: "truncfd %1,%0")
559:
560: (define_insn "fixdfqi2"
561: [(set (match_operand:QI 0 "general_operand" "=g<")
562: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
563: "TARGET_32081"
564: "trunclb %1,%0")
565:
566: (define_insn "fixdfhi2"
567: [(set (match_operand:HI 0 "general_operand" "=g<")
568: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
569: "TARGET_32081"
570: "trunclw %1,%0")
571:
572: (define_insn "fixdfsi2"
573: [(set (match_operand:SI 0 "general_operand" "=g<")
574: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
575: "TARGET_32081"
576: "truncld %1,%0")
577:
578: ;; Unsigned
579:
580: (define_insn "fixunssfqi2"
581: [(set (match_operand:QI 0 "general_operand" "=g<")
582: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
583: "TARGET_32081"
584: "truncfb %1,%0")
585:
586: (define_insn "fixunssfhi2"
587: [(set (match_operand:HI 0 "general_operand" "=g<")
588: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
589: "TARGET_32081"
590: "truncfw %1,%0")
591:
592: (define_insn "fixunssfsi2"
593: [(set (match_operand:SI 0 "general_operand" "=g<")
594: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
595: "TARGET_32081"
596: "truncfd %1,%0")
597:
598: (define_insn "fixunsdfqi2"
599: [(set (match_operand:QI 0 "general_operand" "=g<")
600: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
601: "TARGET_32081"
602: "trunclb %1,%0")
603:
604: (define_insn "fixunsdfhi2"
605: [(set (match_operand:HI 0 "general_operand" "=g<")
606: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
607: "TARGET_32081"
608: "trunclw %1,%0")
609:
610: (define_insn "fixunsdfsi2"
611: [(set (match_operand:SI 0 "general_operand" "=g<")
612: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
613: "TARGET_32081"
614: "truncld %1,%0")
615:
616: ;;; These are not yet used by GCC
617: (define_insn "fix_truncsfqi2"
618: [(set (match_operand:QI 0 "general_operand" "=g<")
619: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
620: "TARGET_32081"
621: "truncfb %1,%0")
622:
623: (define_insn "fix_truncsfhi2"
624: [(set (match_operand:HI 0 "general_operand" "=g<")
625: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
626: "TARGET_32081"
627: "truncfw %1,%0")
628:
629: (define_insn "fix_truncsfsi2"
630: [(set (match_operand:SI 0 "general_operand" "=g<")
631: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
632: "TARGET_32081"
633: "truncfd %1,%0")
634:
635: (define_insn "fix_truncdfqi2"
636: [(set (match_operand:QI 0 "general_operand" "=g<")
637: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
638: "TARGET_32081"
639: "trunclb %1,%0")
640:
641: (define_insn "fix_truncdfhi2"
642: [(set (match_operand:HI 0 "general_operand" "=g<")
643: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
644: "TARGET_32081"
645: "trunclw %1,%0")
646:
647: (define_insn "fix_truncdfsi2"
648: [(set (match_operand:SI 0 "general_operand" "=g<")
649: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
650: "TARGET_32081"
651: "truncld %1,%0")
652:
653: ;;- All kinds of add instructions.
654:
655: (define_insn "adddf3"
656: [(set (match_operand:DF 0 "general_operand" "=fm")
657: (plus:DF (match_operand:DF 1 "general_operand" "%0")
658: (match_operand:DF 2 "general_operand" "fmF")))]
659: "TARGET_32081"
660: "addl %2,%0")
661:
662:
663: (define_insn "addsf3"
664: [(set (match_operand:SF 0 "general_operand" "=fm")
665: (plus:SF (match_operand:SF 1 "general_operand" "%0")
666: (match_operand:SF 2 "general_operand" "fmF")))]
667: "TARGET_32081"
668: "addf %2,%0")
669:
670: (define_insn ""
671: [(set (reg:SI 17)
672: (plus:SI (reg:SI 17)
673: (match_operand:SI 0 "immediate_operand" "i")))]
674: "GET_CODE (operands[0]) == CONST_INT"
675: "*
676: {
677: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
678: return \"adjspb %$%n0\";
679: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
680: return \"adjspw %$%n0\";
681: return \"adjspd %$%n0\";
682: }")
683:
684: (define_insn ""
685: [(set (match_operand:SI 0 "general_operand" "=g<")
686: (plus:SI (reg:SI 16)
687: (match_operand:SI 1 "immediate_operand" "i")))]
688: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 689: "addr %c1(fp),%0")
1.1 root 690:
691: (define_insn ""
692: [(set (match_operand:SI 0 "general_operand" "=g<")
693: (plus:SI (reg:SI 17)
694: (match_operand:SI 1 "immediate_operand" "i")))]
695: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 696: "addr %c1(sp),%0")
1.1 root 697:
698: (define_insn "addsi3"
699: [(set (match_operand:SI 0 "general_operand" "=g")
700: (plus:SI (match_operand:SI 1 "general_operand" "%0")
701: (match_operand:SI 2 "general_operand" "rmn")))]
702: ""
703: "*
704: {
705: if (GET_CODE (operands[2]) == CONST_INT)
706: {
707: int i = INTVAL (operands[2]);
708:
709: if (i <= 7 && i >= -8)
710: return \"addqd %2,%0\";
711: else if (GET_CODE (operands[0]) == REG
712: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 713: return \"addr %c2(%0),%0\";
1.1 root 714: }
715: return \"addd %2,%0\";
716: }")
717:
718: (define_insn "addhi3"
719: [(set (match_operand:HI 0 "general_operand" "=g")
720: (plus:HI (match_operand:HI 1 "general_operand" "%0")
721: (match_operand:HI 2 "general_operand" "g")))]
722: ""
723: "*
724: { if (GET_CODE (operands[2]) == CONST_INT)
725: {
726: int i = INTVAL (operands[2]);
727: if (i <= 7 && i >= -8)
728: return \"addqw %2,%0\";
729: }
730: return \"addw %2,%0\";
731: }")
732:
733: (define_insn ""
734: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
735: (plus:HI (match_operand:HI 1 "general_operand" "0")
736: (match_operand:HI 2 "general_operand" "g")))]
737: ""
738: "*
739: {
740: if (GET_CODE (operands[1]) == CONST_INT
741: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
742: return \"addqw %1,%0\";
743: return \"addw %1,%0\";
744: }")
745:
746: (define_insn "addqi3"
747: [(set (match_operand:QI 0 "general_operand" "=g")
748: (plus:QI (match_operand:QI 1 "general_operand" "%0")
749: (match_operand:QI 2 "general_operand" "g")))]
750: ""
751: "*
752: { if (GET_CODE (operands[2]) == CONST_INT)
753: {
754: int i = INTVAL (operands[2]);
755: if (i <= 7 && i >= -8)
756: return \"addqb %2,%0\";
757: }
758: return \"addb %2,%0\";
759: }")
760:
761: (define_insn ""
762: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
763: (plus:QI (match_operand:QI 1 "general_operand" "0")
764: (match_operand:QI 2 "general_operand" "g")))]
765: ""
766: "*
767: {
768: if (GET_CODE (operands[1]) == CONST_INT
769: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
770: return \"addqb %1,%0\";
771: return \"addb %1,%0\";
772: }")
773:
774: ;;- All kinds of subtract instructions.
775:
776: (define_insn "subdf3"
777: [(set (match_operand:DF 0 "general_operand" "=fm")
778: (minus:DF (match_operand:DF 1 "general_operand" "0")
779: (match_operand:DF 2 "general_operand" "fmF")))]
780: "TARGET_32081"
781: "subl %2,%0")
782:
783: (define_insn "subsf3"
784: [(set (match_operand:SF 0 "general_operand" "=fm")
785: (minus:SF (match_operand:SF 1 "general_operand" "0")
786: (match_operand:SF 2 "general_operand" "fmF")))]
787: "TARGET_32081"
788: "subf %2,%0")
789:
790: (define_insn ""
791: [(set (reg:SI 17)
792: (minus:SI (reg:SI 17)
793: (match_operand:SI 0 "immediate_operand" "i")))]
794: "GET_CODE (operands[0]) == CONST_INT"
795: "*
796: {
797: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
798: && INTVAL(operands[0]) > -64)
799: return \"adjspb %0\";
800: return \"adjspd %0\";
801: }")
802:
803: (define_insn "subsi3"
804: [(set (match_operand:SI 0 "general_operand" "=g")
805: (minus:SI (match_operand:SI 1 "general_operand" "0")
806: (match_operand:SI 2 "general_operand" "rmn")))]
807: ""
808: "*
809: { if (GET_CODE (operands[2]) == CONST_INT)
810: {
811: int i = INTVAL (operands[2]);
812:
813: if (i <= 8 && i >= -7)
814: return \"addqd %$%n2,%0\";
815: }
816: return \"subd %2,%0\";
817: }")
818:
819: (define_insn "subhi3"
820: [(set (match_operand:HI 0 "general_operand" "=g")
821: (minus:HI (match_operand:HI 1 "general_operand" "0")
822: (match_operand:HI 2 "general_operand" "g")))]
823: ""
824: "*
825: { if (GET_CODE (operands[2]) == CONST_INT)
826: {
827: int i = INTVAL (operands[2]);
828:
829: if (i <= 8 && i >= -7)
830: return \"addqw %$%n2,%0\";
831: }
832: return \"subw %2,%0\";
833: }")
834:
835: (define_insn ""
836: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
837: (minus:HI (match_operand:HI 1 "general_operand" "0")
838: (match_operand:HI 2 "general_operand" "g")))]
839: ""
840: "*
841: {
842: if (GET_CODE (operands[1]) == CONST_INT
843: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
844: return \"addqw %$%n1,%0\";
845: return \"subw %1,%0\";
846: }")
847:
848: (define_insn "subqi3"
849: [(set (match_operand:QI 0 "general_operand" "=g")
850: (minus:QI (match_operand:QI 1 "general_operand" "0")
851: (match_operand:QI 2 "general_operand" "g")))]
852: ""
853: "*
854: { if (GET_CODE (operands[2]) == CONST_INT)
855: {
856: int i = INTVAL (operands[2]);
857:
858: if (i <= 8 && i >= -7)
859: return \"addqb %$%n2,%0\";
860: }
861: return \"subb %2,%0\";
862: }")
863:
864: (define_insn ""
865: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
866: (minus:QI (match_operand:QI 1 "general_operand" "0")
867: (match_operand:QI 2 "general_operand" "g")))]
868: ""
869: "*
870: {
871: if (GET_CODE (operands[1]) == CONST_INT
872: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
873: return \"addqb %$%n1,%0\";
874: return \"subb %1,%0\";
875: }")
876:
877: ;;- Multiply instructions.
878:
879: (define_insn "muldf3"
880: [(set (match_operand:DF 0 "general_operand" "=fm")
881: (mult:DF (match_operand:DF 1 "general_operand" "%0")
882: (match_operand:DF 2 "general_operand" "fmF")))]
883: "TARGET_32081"
884: "mull %2,%0")
885:
886: (define_insn "mulsf3"
887: [(set (match_operand:SF 0 "general_operand" "=fm")
888: (mult:SF (match_operand:SF 1 "general_operand" "%0")
889: (match_operand:SF 2 "general_operand" "fmF")))]
890: "TARGET_32081"
891: "mulf %2,%0")
892:
893: (define_insn "mulsi3"
894: [(set (match_operand:SI 0 "general_operand" "=g")
895: (mult:SI (match_operand:SI 1 "general_operand" "%0")
896: (match_operand:SI 2 "general_operand" "rmn")))]
897: ""
898: "muld %2,%0")
899:
900: (define_insn "mulhi3"
901: [(set (match_operand:HI 0 "general_operand" "=g")
902: (mult:HI (match_operand:HI 1 "general_operand" "%0")
903: (match_operand:HI 2 "general_operand" "g")))]
904: ""
905: "mulw %2,%0")
906:
907: (define_insn "mulqi3"
908: [(set (match_operand:QI 0 "general_operand" "=g")
909: (mult:QI (match_operand:QI 1 "general_operand" "%0")
910: (match_operand:QI 2 "general_operand" "g")))]
911: ""
912: "mulb %2,%0")
913:
914: (define_insn "umulsi3"
915: [(set (match_operand:SI 0 "general_operand" "=g")
916: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 917: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 918: ""
919: "muld %2,%0")
920:
921: (define_insn "umulhi3"
922: [(set (match_operand:HI 0 "general_operand" "=g")
923: (umult:HI (match_operand:HI 1 "general_operand" "%0")
924: (match_operand:HI 2 "general_operand" "g")))]
925: ""
926: "mulw %2,%0")
927:
928: (define_insn "umulqi3"
929: [(set (match_operand:QI 0 "general_operand" "=g")
930: (umult:QI (match_operand:QI 1 "general_operand" "%0")
931: (match_operand:QI 2 "general_operand" "g")))]
932: ""
933: "mulb %2,%0")
934:
935: (define_insn "umulsidi3"
936: [(set (match_operand:DI 0 "general_operand" "=g")
937: (umult:DI (match_operand:SI 1 "general_operand" "0")
938: (match_operand:SI 2 "general_operand" "rmn")))]
939: ""
940: "meid %2,%0")
941:
942: ;;- Divide instructions.
943:
944: (define_insn "divdf3"
945: [(set (match_operand:DF 0 "general_operand" "=fm")
946: (div:DF (match_operand:DF 1 "general_operand" "0")
947: (match_operand:DF 2 "general_operand" "fmF")))]
948: "TARGET_32081"
949: "divl %2,%0")
950:
951: (define_insn "divsf3"
952: [(set (match_operand:SF 0 "general_operand" "=fm")
953: (div:SF (match_operand:SF 1 "general_operand" "0")
954: (match_operand:SF 2 "general_operand" "fmF")))]
955: "TARGET_32081"
956: "divf %2,%0")
957:
958: (define_insn "divsi3"
959: [(set (match_operand:SI 0 "general_operand" "=g")
960: (div:SI (match_operand:SI 1 "general_operand" "0")
961: (match_operand:SI 2 "general_operand" "rmn")))]
962: ""
963: "quod %2,%0")
964:
965: (define_insn "divhi3"
966: [(set (match_operand:HI 0 "general_operand" "=g")
967: (div:HI (match_operand:HI 1 "general_operand" "0")
968: (match_operand:HI 2 "general_operand" "g")))]
969: ""
970: "quow %2,%0")
971:
972: (define_insn "divqi3"
973: [(set (match_operand:QI 0 "general_operand" "=g")
974: (div:QI (match_operand:QI 1 "general_operand" "0")
975: (match_operand:QI 2 "general_operand" "g")))]
976: ""
977: "quob %2,%0")
978:
979: (define_insn "udivsi3"
980: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 981: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 982: (match_operand:SI 2 "general_operand" "rmn")))]
983: ""
984: "*
985: {
986: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
987: return \"deid %2,%0\;movd %1,%0\";
988: }")
989:
990: (define_insn "udivhi3"
991: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 992: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 993: (match_operand:HI 2 "general_operand" "g")))]
994: ""
995: "*
996: {
997: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
998: return \"deiw %2,%0\;movw %1,%0\";
999: }")
1000:
1001: (define_insn "udivqi3"
1002: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1003: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1004: (match_operand:QI 2 "general_operand" "g")))]
1005: ""
1006: "*
1007: {
1008: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1009: return \"deib %2,%0\;movb %1,%0\";
1010: }")
1011:
1012: ;; Remainder instructions.
1013:
1014: (define_insn "modsi3"
1015: [(set (match_operand:SI 0 "general_operand" "=g")
1016: (mod:SI (match_operand:SI 1 "general_operand" "0")
1017: (match_operand:SI 2 "general_operand" "rmn")))]
1018: ""
1019: "remd %2,%0")
1020:
1021: (define_insn "modhi3"
1022: [(set (match_operand:HI 0 "general_operand" "=g")
1023: (mod:HI (match_operand:HI 1 "general_operand" "0")
1024: (match_operand:HI 2 "general_operand" "g")))]
1025: ""
1026: "remw %2,%0")
1027:
1028: (define_insn "modqi3"
1029: [(set (match_operand:QI 0 "general_operand" "=g")
1030: (mod:QI (match_operand:QI 1 "general_operand" "0")
1031: (match_operand:QI 2 "general_operand" "g")))]
1032: ""
1033: "remb %2,%0")
1034:
1035: (define_insn "umodsi3"
1036: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1037: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1038: (match_operand:SI 2 "general_operand" "rmn")))]
1039: ""
1040: "deid %2,%0")
1041:
1042: (define_insn "umodhi3"
1043: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1044: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1045: (match_operand:HI 2 "general_operand" "g")))]
1046: ""
1047: "deiw %2,%0")
1048:
1049: (define_insn "umodqi3"
1050: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1051: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1052: (match_operand:QI 2 "general_operand" "g")))]
1053: ""
1054: "deib %2,%0")
1055:
1056: ; This isn't be usable in its current form.
1057: ;(define_insn "udivmoddisi4"
1058: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1059: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1060: ; (match_operand:SI 2 "general_operand" "rmn")))
1061: ; (set (subreg:SI (match_dup 0) 0)
1062: ; (umod:SI (match_dup 1) (match_dup 2)))]
1063: ; ""
1064: ; "deid %2,%0")
1065:
1066: ;;- Logical Instructions: AND
1067:
1068: (define_insn "andsi3"
1069: [(set (match_operand:SI 0 "general_operand" "=g")
1070: (and:SI (match_operand:SI 1 "general_operand" "%0")
1071: (match_operand:SI 2 "general_operand" "rmn")))]
1072: ""
1073: "*
1074: {
1075: if (GET_CODE (operands[2]) == CONST_INT) {
1076: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1077: if (INTVAL (operands[2]) == 0xffffff00)
1078: return \"movqb %$0,%0\";
1079: else {
1080: INTVAL (operands[2]) &= 0xff;
1081: return \"andb %2,%0\";
1082: }
1083: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1084: if (INTVAL (operands[2]) == 0xffff0000)
1085: return \"movqw %$0,%0\";
1086: else {
1087: INTVAL (operands[2]) &= 0xffff;
1088: return \"andw %2,%0\";
1089: }
1090: }
1091: return \"andd %2,%0\";
1092: }")
1093:
1094: (define_insn "andhi3"
1095: [(set (match_operand:HI 0 "general_operand" "=g")
1096: (and:HI (match_operand:HI 1 "general_operand" "%0")
1097: (match_operand:HI 2 "general_operand" "g")))]
1098: ""
1099: "*
1100: {
1101: if (GET_CODE (operands[2]) == CONST_INT
1102: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1103: if (INTVAL (operands[2]) == 0xffffff00)
1104: return \"movqb %$0,%0\";
1105: else {
1106: INTVAL (operands[2]) &= 0xff;
1107: return \"andb %2,%0\";
1108: }
1109: return \"andw %2,%0\";
1110: }")
1111:
1112: (define_insn "andqi3"
1113: [(set (match_operand:QI 0 "general_operand" "=g")
1114: (and:QI (match_operand:QI 1 "general_operand" "%0")
1115: (match_operand:QI 2 "general_operand" "g")))]
1116: ""
1117: "andb %2,%0")
1118:
1119: (define_insn "andcbsi3"
1120: [(set (match_operand:SI 0 "general_operand" "=g")
1121: (and:SI (match_operand:SI 1 "general_operand" "0")
1122: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1123: ""
1124: "*
1125: {
1126: if (GET_CODE (operands[2]) == CONST_INT)
1127: {
1128: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1129: return \"bicb %2,%0\";
1130: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1131: return \"bicw %2,%0\";
1132: }
1133: return \"bicd %2,%0\";
1134: }")
1135:
1136: (define_insn ""
1137: [(set (match_operand:SI 0 "general_operand" "=g")
1138: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1139: (match_operand:SI 2 "general_operand" "0")))]
1140: ""
1141: "*
1142: {
1143: if (GET_CODE (operands[1]) == CONST_INT)
1144: {
1145: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1146: return \"bicb %1,%0\";
1147: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1148: return \"bicw %1,%0\";
1149: }
1150: return \"bicd %1,%0\";
1151: }")
1152:
1153: (define_insn "andcbhi3"
1154: [(set (match_operand:HI 0 "general_operand" "=g")
1155: (and:HI (match_operand:HI 1 "general_operand" "%0")
1156: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1157: ""
1158: "*
1159: {
1160: if (GET_CODE (operands[2]) == CONST_INT
1161: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1162: return \"bicb %2,%0\";
1163: return \"bicw %2,%0\";
1164: }")
1165:
1166: (define_insn ""
1167: [(set (match_operand:HI 0 "general_operand" "=g")
1168: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1169: (match_operand:HI 2 "general_operand" "0")))]
1170: ""
1171: "*
1172: {
1173: if (GET_CODE (operands[1]) == CONST_INT
1174: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1175: return \"bicb %1,%0\";
1176: return \"bicw %1,%0\";
1177: }")
1178:
1179: (define_insn "andcbqi3"
1180: [(set (match_operand:QI 0 "general_operand" "=g")
1181: (and:QI (match_operand:QI 1 "general_operand" "%0")
1182: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1183: ""
1184: "bicb %2,%0")
1185:
1186: (define_insn ""
1187: [(set (match_operand:QI 0 "general_operand" "=g")
1188: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1189: (match_operand:QI 2 "general_operand" "0")))]
1190: ""
1191: "bicb %1,%0")
1192:
1193: ;;- Bit set instructions.
1194:
1195: (define_insn "iorsi3"
1196: [(set (match_operand:SI 0 "general_operand" "=g")
1197: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1198: (match_operand:SI 2 "general_operand" "rmn")))]
1199: ""
1200: "*
1201: {
1202: if (GET_CODE (operands[2]) == CONST_INT) {
1203: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1204: return \"orb %2,%0\";
1205: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1206: return \"orw %2,%0\";
1207: }
1208: return \"ord %2,%0\";
1209: }")
1210:
1211: (define_insn "iorhi3"
1212: [(set (match_operand:HI 0 "general_operand" "=g")
1213: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1214: (match_operand:HI 2 "general_operand" "g")))]
1215: ""
1216: "*
1217: {
1218: if (GET_CODE(operands[2]) == CONST_INT &&
1219: (INTVAL(operands[2]) & 0xffffff00) == 0)
1220: return \"orb %2,%0\";
1221: return \"orw %2,%0\";
1222: }")
1223:
1224: (define_insn "iorqi3"
1225: [(set (match_operand:QI 0 "general_operand" "=g")
1226: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1227: (match_operand:QI 2 "general_operand" "g")))]
1228: ""
1229: "orb %2,%0")
1230:
1231: ;;- xor instructions.
1232:
1233: (define_insn "xorsi3"
1234: [(set (match_operand:SI 0 "general_operand" "=g")
1235: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1236: (match_operand:SI 2 "general_operand" "rmn")))]
1237: ""
1238: "*
1239: {
1240: if (GET_CODE (operands[2]) == CONST_INT) {
1241: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1242: return \"xorb %2,%0\";
1243: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1244: return \"xorw %2,%0\";
1245: }
1246: return \"xord %2,%0\";
1247: }")
1248:
1249: (define_insn "xorhi3"
1250: [(set (match_operand:HI 0 "general_operand" "=g")
1251: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1252: (match_operand:HI 2 "general_operand" "g")))]
1253: ""
1254: "*
1255: {
1256: if (GET_CODE(operands[2]) == CONST_INT &&
1257: (INTVAL(operands[2]) & 0xffffff00) == 0)
1258: return \"xorb %2,%0\";
1259: return \"xorw %2,%0\";
1260: }")
1261:
1262: (define_insn "xorqi3"
1263: [(set (match_operand:QI 0 "general_operand" "=g")
1264: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1265: (match_operand:QI 2 "general_operand" "g")))]
1266: ""
1267: "xorb %2,%0")
1268:
1269: (define_insn "negdf2"
1270: [(set (match_operand:DF 0 "general_operand" "=fm<")
1271: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1272: "TARGET_32081"
1273: "negl %1,%0")
1274:
1275: (define_insn "negsf2"
1276: [(set (match_operand:SF 0 "general_operand" "=fm<")
1277: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1278: "TARGET_32081"
1279: "negf %1,%0")
1280:
1281: (define_insn "negsi2"
1282: [(set (match_operand:SI 0 "general_operand" "=g<")
1283: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1284: ""
1285: "negd %1,%0")
1286:
1287: (define_insn "neghi2"
1288: [(set (match_operand:HI 0 "general_operand" "=g<")
1289: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1290: ""
1291: "negw %1,%0")
1292:
1293: (define_insn "negqi2"
1294: [(set (match_operand:QI 0 "general_operand" "=g<")
1295: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1296: ""
1297: "negb %1,%0")
1298:
1299: (define_insn "one_cmplsi2"
1300: [(set (match_operand:SI 0 "general_operand" "=g<")
1301: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1302: ""
1303: "comd %1,%0")
1304:
1305: (define_insn "one_cmplhi2"
1306: [(set (match_operand:HI 0 "general_operand" "=g<")
1307: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1308: ""
1309: "comw %1,%0")
1310:
1311: (define_insn "one_cmplqi2"
1312: [(set (match_operand:QI 0 "general_operand" "=g<")
1313: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1314: ""
1315: "comb %1,%0")
1316:
1317: ;; arithmetic left and right shift operations
1318:
1319: (define_insn "ashlsi3"
1320: [(set (match_operand:SI 0 "general_operand" "=g,g")
1321: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1322: (match_operand:SI 2 "general_operand" "I,rmn")))]
1323: ""
1.1.1.2 root 1324: "* output_shift_insn (operands);")
1.1 root 1325:
1326: (define_insn ""
1327: [(set (match_operand:SI 0 "general_operand" "=g")
1328: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1329: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1330: (const_int 31))))]
1331: ""
1332: "ashd %2,%0")
1333:
1334: (define_insn "ashlhi3"
1335: [(set (match_operand:HI 0 "general_operand" "=g")
1336: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1337: (match_operand:SI 2 "general_operand" "rmn")))]
1338: ""
1339: "*
1340: { if (GET_CODE (operands[2]) == CONST_INT)
1341: if (INTVAL (operands[2]) == 1)
1342: return \"addw %1,%0\";
1343: else if (INTVAL (operands[2]) == 2)
1344: return \"addw %1,%0\;addw %0,%0\";
1345: return \"ashw %2,%0\";
1346: }")
1347:
1348: (define_insn "ashlqi3"
1349: [(set (match_operand:QI 0 "general_operand" "=g")
1350: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1351: (match_operand:SI 2 "general_operand" "rmn")))]
1352: ""
1353: "*
1354: { if (GET_CODE (operands[2]) == CONST_INT)
1355: if (INTVAL (operands[2]) == 1)
1356: return \"addb %1,%0\";
1357: else if (INTVAL (operands[2]) == 2)
1358: return \"addb %1,%0\;addb %0,%0\";
1359: return \"ashb %2,%0\";
1360: }")
1361:
1362: ;; logical shift instructions
1363:
1364: (define_insn "lshlsi3"
1365: [(set (match_operand:SI 0 "general_operand" "=g")
1366: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1367: (match_operand:SI 2 "general_operand" "rmn")))]
1368: ""
1369: "lshd %2,%0")
1370:
1371: (define_insn ""
1372: [(set (match_operand:SI 0 "general_operand" "=g")
1373: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1374: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1375: (const_int 31))))]
1376: ""
1377: "lshd %2,%0")
1378:
1379: (define_insn "lshlhi3"
1380: [(set (match_operand:HI 0 "general_operand" "=g")
1381: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1382: (match_operand:SI 2 "general_operand" "rmn")))]
1383: ""
1384: "lshw %2,%0")
1385:
1386: (define_insn "lshlqi3"
1387: [(set (match_operand:QI 0 "general_operand" "=g")
1388: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1389: (match_operand:SI 2 "general_operand" "rmn")))]
1390: ""
1391: "lshb %2,%0")
1392:
1393: ;; Rotate instructions
1394:
1395: (define_insn "rotlsi3"
1396: [(set (match_operand:SI 0 "general_operand" "=g")
1397: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1398: (match_operand:SI 2 "general_operand" "rmn")))]
1399: ""
1400: "rotd %2,%0")
1401:
1402: (define_insn "rotlhi3"
1403: [(set (match_operand:HI 0 "general_operand" "=g")
1404: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1405: (match_operand:SI 2 "general_operand" "rmn")))]
1406: ""
1407: "rotw %2,%0")
1408:
1409: (define_insn "rotlqi3"
1410: [(set (match_operand:QI 0 "general_operand" "=g")
1411: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1412: (match_operand:SI 2 "general_operand" "rmn")))]
1413: ""
1414: "rotb %2,%0")
1415:
1416: ;;- load or push effective address
1417: ;; These come after the move, add, and multiply patterns
1418: ;; because we don't want pushl $1 turned into pushad 1.
1419:
1420: (define_insn ""
1421: [(set (match_operand:SI 0 "general_operand" "=g<")
1422: (match_operand:QI 1 "address_operand" "p"))]
1423: ""
1.1.1.2 root 1424: "*
1425: {
1426: if (REG_P (operands[0])
1427: && GET_CODE (operands[1]) == MULT
1428: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1429: && (INTVAL (XEXP (operands[1], 1)) == 2
1430: || INTVAL (XEXP (operands[1], 1)) == 4))
1431: {
1432: rtx xoperands[3];
1433: xoperands[0] = operands[0];
1434: xoperands[1] = XEXP (operands[1], 0);
1435: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1436: return output_shift_insn (xoperands);
1437: }
1438: return \"addr %a1,%0\";
1439: }")
1.1 root 1440:
1441: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1442: ;;; but slower then using power-of-2 shifts if we can use them
1443: ;
1444: ;(define_insn ""
1445: ; [(set (match_operand:SI 0 "register_operand" "=r")
1446: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1447: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1448: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1449: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1450: ; "indexd %0,%3,%1")
1451: ;
1452: ;(define_insn ""
1453: ; [(set (match_operand:SI 0 "register_operand" "=r")
1454: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1455: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1456: ; (match_operand:SI 3 "general_operand" "rmn")))]
1457: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1458: ; "indexd %0,%2,%3")
1459:
1460: ;; Set, Clear, and Invert bit
1461:
1462: (define_insn ""
1463: [(set (match_operand:SI 0 "general_operand" "=g")
1464: (ior:SI
1465: (ashift:SI (const_int 1)
1466: (match_operand:SI 1 "general_operand" "rmn"))
1467: (match_dup 0)))]
1468: ""
1469: "sbitd %1,%0")
1470:
1471: (define_insn ""
1472: [(set (match_operand:SI 0 "general_operand" "=g")
1473: (ior:SI
1474: (match_dup 0)
1475: (ashift:SI (const_int 1)
1476: (match_operand:SI 1 "general_operand" "rmn"))))]
1477: ""
1478: "sbitd %1,%0")
1479:
1480: (define_insn ""
1481: [(set (match_operand:QI 0 "general_operand" "=g")
1482: (ior:QI
1483: (subreg:QI
1484: (ashift:SI (const_int 1)
1485: (match_operand:QI 1 "general_operand" "rmn")) 0)
1486: (match_dup 0)))]
1487: ""
1488: "sbitb %1,%0")
1489:
1490: (define_insn ""
1491: [(set (match_operand:QI 0 "general_operand" "=g")
1492: (ior:QI
1493: (match_dup 0)
1494: (subreg:QI
1495: (ashift:SI (const_int 1)
1496: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1497: ""
1498: "sbitb %1,%0")
1499:
1500: (define_insn ""
1501: [(set (match_operand:SI 0 "general_operand" "=g")
1502: (and:SI
1503: (not:SI
1504: (ashift:SI (const_int 1)
1505: (match_operand:SI 1 "general_operand" "rmn")))
1506: (match_dup 0)))]
1507: ""
1508: "cbitd %1,%0")
1509:
1510: (define_insn ""
1511: [(set (match_operand:SI 0 "general_operand" "=g")
1512: (and:SI
1513: (match_dup 0)
1514: (not:SI
1515: (ashift:SI (const_int 1)
1516: (match_operand:SI 1 "general_operand" "rmn")))))]
1517: ""
1518: "cbitd %1,%0")
1519:
1520: (define_insn ""
1521: [(set (match_operand:QI 0 "general_operand" "=g")
1522: (and:QI
1523: (subreg:QI
1524: (not:SI
1525: (ashift:SI (const_int 1)
1526: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1527: (match_dup 0)))]
1528: ""
1529: "cbitb %1,%0")
1530:
1531: (define_insn ""
1532: [(set (match_operand:QI 0 "general_operand" "=g")
1533: (and:QI
1534: (match_dup 0)
1535: (subreg:QI
1536: (not:SI
1537: (ashift:SI (const_int 1)
1538: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1539: ""
1540: "cbitb %1,%0")
1541:
1542: (define_insn ""
1543: [(set (match_operand:SI 0 "general_operand" "=g")
1544: (xor:SI
1545: (ashift:SI (const_int 1)
1546: (match_operand:SI 1 "general_operand" "rmn"))
1547: (match_dup 0)))]
1548: ""
1549: "ibitd %1,%0")
1550:
1551: (define_insn ""
1552: [(set (match_operand:SI 0 "general_operand" "=g")
1553: (xor:SI
1554: (match_dup 0)
1555: (ashift:SI (const_int 1)
1556: (match_operand:SI 1 "general_operand" "rmn"))))]
1557: ""
1558: "ibitd %1,%0")
1559:
1560: (define_insn ""
1561: [(set (match_operand:QI 0 "general_operand" "=g")
1562: (xor:QI
1563: (subreg:QI
1564: (ashift:SI (const_int 1)
1565: (match_operand:QI 1 "general_operand" "rmn")) 0)
1566: (match_dup 0)))]
1567: ""
1568: "ibitb %1,%0")
1569:
1570: (define_insn ""
1571: [(set (match_operand:QI 0 "general_operand" "=g")
1572: (xor:QI
1573: (match_dup 0)
1574: (subreg:QI
1575: (ashift:SI (const_int 1)
1576: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1577: ""
1578: "ibitb %1,%0")
1579:
1580: ;; Recognize jbs and jbc instructions.
1581:
1582: (define_insn ""
1583: [(set (cc0)
1584: (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1585: (const_int 1)
1586: (match_operand:SI 1 "general_operand" "rmn")))]
1587: ""
1588: "*
1589: { cc_status.flags = CC_Z_IN_F;
1590: return \"tbitd %1,%0\";
1591: }")
1592:
1593: (define_insn ""
1594: [(set (cc0)
1595: (minus (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1596: (const_int 1)
1597: (match_operand:SI 1 "general_operand" "rmn"))
1598: (const_int 1)))]
1599: ""
1600: "*
1601: { cc_status.flags = CC_Z_IN_NOT_F;
1602: return \"tbitd %1,%0\";
1603: }")
1604:
1605: (define_insn ""
1606: [(set (cc0)
1607: (zero_extract (match_operand:HI 0 "general_operand" "g")
1608: (const_int 1)
1609: (match_operand:HI 1 "general_operand" "g")))]
1610: ""
1611: "*
1612: { cc_status.flags = CC_Z_IN_F;
1613: return \"tbitw %1,%0\";
1614: }")
1615:
1616: (define_insn ""
1617: [(set (cc0)
1618: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1619: (const_int 1)
1620: (match_operand:HI 1 "general_operand" "rmn"))
1621: (const_int 1)))]
1622: ""
1623: "*
1624: { cc_status.flags = CC_Z_IN_NOT_F;
1625: return \"tbitw %1,%0\";
1626: }")
1627:
1628: (define_insn ""
1629: [(set (cc0)
1630: (zero_extract (match_operand:QI 0 "general_operand" "g")
1631: (const_int 1)
1632: (match_operand:QI 1 "general_operand" "g")))]
1633: ""
1634: "*
1635: { cc_status.flags = CC_Z_IN_F;
1636: return \"tbitb %1,%0\";
1637: }")
1638:
1639: (define_insn ""
1640: [(set (cc0)
1641: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1642: (const_int 1)
1643: (match_operand:QI 1 "general_operand" "rmn"))
1644: (const_int 1)))]
1645: ""
1646: "*
1647: { cc_status.flags = CC_Z_IN_NOT_F;
1648: return \"tbitb %1,%0\";
1649: }")
1650:
1651: (define_insn ""
1652: [(set (cc0)
1653: (and:SI (match_operand:SI 0 "general_operand" "rmn")
1654: (match_operand:SI 1 "immediate_operand" "i")))]
1655: "GET_CODE (operands[1]) == CONST_INT
1656: && exact_log2 (INTVAL (operands[1])) >= 0"
1657: "*
1658: {
1659: operands[1]
1660: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1661: cc_status.flags = CC_Z_IN_F;
1662: return \"tbitd %1,%0\";
1663: }")
1664:
1665: ;; extract(base, width, offset)
1666: ;; Signed bitfield extraction is not supported in hardware on the
1667: ;; NS 32032. It is therefore better to let GCC figure out a
1668: ;; good strategy for generating the proper instruction sequence
1669: ;; and represent it as rtl.
1670:
1.1.1.2 root 1671: ;; Optimize the case of extracting a byte or word from a register.
1672: ;; Otherwise we must load a register with the offset of the
1673: ;; chunk we want, and perform an extract insn (each of which
1674: ;; is very expensive). Since we use the stack to do our bit-twiddling
1675: ;; we cannot use it for a destination. Perhaps things are fast
1676: ;; enough on the 32532 that such hacks are not needed.
1677:
1678: (define_insn ""
1679: [(set (match_operand:SI 0 "general_operand" "=ro")
1680: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1681: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1682: (match_operand:SI 3 "const_int" "i")))]
1683: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1684: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1685: "*
1686: {
1687: output_asm_insn (\"movd %1,tos\", operands);
1688: if (INTVAL (operands[2]) == 16)
1689: {
1690: if (INTVAL (operands[3]) == 8)
1691: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1692: else
1693: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1694: }
1695: else
1696: {
1697: if (INTVAL (operands[3]) == 8)
1698: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1699: else if (INTVAL (operands[3]) == 16)
1700: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1701: else
1702: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1703: }
1704: return \"adjspb %$-4\";
1705: }")
1706:
1707: (define_insn ""
1708: [(set (match_operand:SI 0 "general_operand" "=ro")
1709: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1710: (match_operand:SI 2 "const_int" "i")
1711: (match_operand:SI 3 "const_int" "i")))]
1712: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1713: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1714:
1715: (define_insn "extzv"
1716: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1717: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1718: (match_operand:SI 2 "const_int" "i,i")
1719: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1720: ""
1721: "*
1722: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1723: {
1724: if (INTVAL (operands[3]) >= 8)
1725: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1726: return \"extsd %1,%0,%3,%2\";
1727: }
1.1 root 1728: else return \"extd %3,%1,%0,%2\";
1729: }")
1730:
1731: (define_insn ""
1.1.1.2 root 1732: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1733: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1734: (match_operand:SI 2 "const_int" "i,i")
1735: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1736: ""
1737: "*
1738: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1739: {
1740: if (INTVAL (operands[3]) >= 8)
1741: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1742: return \"extsd %1,%0,%3,%2\";
1743: }
1.1 root 1744: else return \"extd %3,%1,%0,%2\";
1745: }")
1746:
1747: (define_insn ""
1748: [(set (match_operand:SI 0 "general_operand" "=g<")
1749: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1750: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1751: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1752: ""
1753: "*
1754: { if (GET_CODE (operands[3]) == CONST_INT)
1755: return \"extsd %1,%0,%3,%2\";
1756: else return \"extd %3,%1,%0,%2\";
1757: }")
1758:
1759: (define_insn "insv"
1.1.1.4 ! root 1760: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1.1.1.2 root 1761: (match_operand:SI 1 "const_int" "i,i")
1762: (match_operand:SI 2 "general_operand" "rK,n"))
1763: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1764: ""
1765: "*
1766: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1767: {
1.1.1.4 ! root 1768: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
! 1769: {
! 1770: operands[0] = adj_offsetable_operand (operands[0],
! 1771: INTVAL (operands[2]) / 8);
! 1772: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
! 1773: }
1.1.1.2 root 1774: if (INTVAL (operands[1]) <= 8)
1775: return \"inssb %3,%0,%2,%1\";
1776: else if (INTVAL (operands[1]) <= 16)
1777: return \"inssw %3,%0,%2,%1\";
1778: else
1779: return \"inssd %3,%0,%2,%1\";
1780: }
1781: return \"insd %2,%3,%0,%1\";
1.1 root 1782: }")
1783:
1784: (define_insn ""
1.1.1.4 ! root 1785: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1.1.1.2 root 1786: (match_operand:SI 1 "const_int" "i,i")
1787: (match_operand:SI 2 "general_operand" "rK,n"))
1788: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1789: ""
1790: "*
1791: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1792: {
1.1.1.4 ! root 1793: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
! 1794: {
! 1795: operands[0] = adj_offsetable_operand (operands[0],
! 1796: INTVAL (operands[2]) / 8);
! 1797: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
! 1798: }
1.1.1.2 root 1799: if (INTVAL (operands[1]) <= 8)
1800: return \"inssb %3,%0,%2,%1\";
1801: else if (INTVAL (operands[1]) <= 16)
1802: return \"inssw %3,%0,%2,%1\";
1803: else
1804: return \"inssd %3,%0,%2,%1\";
1805: }
1806: return \"insd %2,%3,%0,%1\";
1.1 root 1807: }")
1808:
1809: (define_insn ""
1810: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1811: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1812: (match_operand:SI 2 "general_operand" "rn"))
1813: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1814: ""
1815: "*
1816: { if (GET_CODE (operands[2]) == CONST_INT)
1817: if (INTVAL (operands[1]) <= 8)
1818: return \"inssb %3,%0,%2,%1\";
1819: else if (INTVAL (operands[1]) <= 16)
1820: return \"inssw %3,%0,%2,%1\";
1821: else
1822: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1823: return \"insd %2,%3,%0,%1\";
1.1 root 1824: }")
1825:
1826:
1827: (define_insn "jump"
1828: [(set (pc)
1829: (label_ref (match_operand 0 "" "")))]
1830: ""
1831: "br %l0")
1832:
1833: (define_insn "beq"
1834: [(set (pc)
1835: (if_then_else (eq (cc0)
1836: (const_int 0))
1837: (label_ref (match_operand 0 "" ""))
1838: (pc)))]
1839: ""
1840: "*
1841: { if (cc_prev_status.flags & CC_Z_IN_F)
1842: return \"bfc %l0\";
1843: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1844: return \"bfs %l0\";
1845: else return \"beq %l0\";
1846: }")
1847:
1848: (define_insn "bne"
1849: [(set (pc)
1850: (if_then_else (ne (cc0)
1851: (const_int 0))
1852: (label_ref (match_operand 0 "" ""))
1853: (pc)))]
1854: ""
1855: "*
1856: { if (cc_prev_status.flags & CC_Z_IN_F)
1857: return \"bfs %l0\";
1858: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1859: return \"bfc %l0\";
1860: else return \"bne %l0\";
1861: }")
1862:
1863: (define_insn "bgt"
1864: [(set (pc)
1865: (if_then_else (gt (cc0)
1866: (const_int 0))
1867: (label_ref (match_operand 0 "" ""))
1868: (pc)))]
1869: ""
1870: "bgt %l0")
1871:
1872: (define_insn "bgtu"
1873: [(set (pc)
1874: (if_then_else (gtu (cc0)
1875: (const_int 0))
1876: (label_ref (match_operand 0 "" ""))
1877: (pc)))]
1878: ""
1879: "bhi %l0")
1880:
1881: (define_insn "blt"
1882: [(set (pc)
1883: (if_then_else (lt (cc0)
1884: (const_int 0))
1885: (label_ref (match_operand 0 "" ""))
1886: (pc)))]
1887: ""
1888: "blt %l0")
1889:
1890: (define_insn "bltu"
1891: [(set (pc)
1892: (if_then_else (ltu (cc0)
1893: (const_int 0))
1894: (label_ref (match_operand 0 "" ""))
1895: (pc)))]
1896: ""
1897: "blo %l0")
1898:
1899: (define_insn "bge"
1900: [(set (pc)
1901: (if_then_else (ge (cc0)
1902: (const_int 0))
1903: (label_ref (match_operand 0 "" ""))
1904: (pc)))]
1905: ""
1906: "bge %l0")
1907:
1908: (define_insn "bgeu"
1909: [(set (pc)
1910: (if_then_else (geu (cc0)
1911: (const_int 0))
1912: (label_ref (match_operand 0 "" ""))
1913: (pc)))]
1914: ""
1915: "bhs %l0")
1916:
1917: (define_insn "ble"
1918: [(set (pc)
1919: (if_then_else (le (cc0)
1920: (const_int 0))
1921: (label_ref (match_operand 0 "" ""))
1922: (pc)))]
1923: ""
1924: "ble %l0")
1925:
1926: (define_insn "bleu"
1927: [(set (pc)
1928: (if_then_else (leu (cc0)
1929: (const_int 0))
1930: (label_ref (match_operand 0 "" ""))
1931: (pc)))]
1932: ""
1933: "bls %l0")
1934:
1935: (define_insn ""
1936: [(set (pc)
1937: (if_then_else (eq (cc0)
1938: (const_int 0))
1939: (pc)
1940: (label_ref (match_operand 0 "" ""))))]
1941: ""
1942: "*
1943: { if (cc_prev_status.flags & CC_Z_IN_F)
1944: return \"bfs %l0\";
1945: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1946: return \"bfc %l0\";
1947: else return \"bne %l0\";
1948: }")
1949:
1950: (define_insn ""
1951: [(set (pc)
1952: (if_then_else (ne (cc0)
1953: (const_int 0))
1954: (pc)
1955: (label_ref (match_operand 0 "" ""))))]
1956: ""
1957: "*
1958: { if (cc_prev_status.flags & CC_Z_IN_F)
1959: return \"bfc %l0\";
1960: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1961: return \"bfs %l0\";
1962: else return \"beq %l0\";
1963: }")
1964:
1965: (define_insn ""
1966: [(set (pc)
1967: (if_then_else (gt (cc0)
1968: (const_int 0))
1969: (pc)
1970: (label_ref (match_operand 0 "" ""))))]
1971: ""
1972: "ble %l0")
1973:
1974: (define_insn ""
1975: [(set (pc)
1976: (if_then_else (gtu (cc0)
1977: (const_int 0))
1978: (pc)
1979: (label_ref (match_operand 0 "" ""))))]
1980: ""
1981: "bls %l0")
1982:
1983: (define_insn ""
1984: [(set (pc)
1985: (if_then_else (lt (cc0)
1986: (const_int 0))
1987: (pc)
1988: (label_ref (match_operand 0 "" ""))))]
1989: ""
1990: "bge %l0")
1991:
1992: (define_insn ""
1993: [(set (pc)
1994: (if_then_else (ltu (cc0)
1995: (const_int 0))
1996: (pc)
1997: (label_ref (match_operand 0 "" ""))))]
1998: ""
1999: "bhs %l0")
2000:
2001: (define_insn ""
2002: [(set (pc)
2003: (if_then_else (ge (cc0)
2004: (const_int 0))
2005: (pc)
2006: (label_ref (match_operand 0 "" ""))))]
2007: ""
2008: "blt %l0")
2009:
2010: (define_insn ""
2011: [(set (pc)
2012: (if_then_else (geu (cc0)
2013: (const_int 0))
2014: (pc)
2015: (label_ref (match_operand 0 "" ""))))]
2016: ""
2017: "blo %l0")
2018:
2019: (define_insn ""
2020: [(set (pc)
2021: (if_then_else (le (cc0)
2022: (const_int 0))
2023: (pc)
2024: (label_ref (match_operand 0 "" ""))))]
2025: ""
2026: "bgt %l0")
2027:
2028: (define_insn ""
2029: [(set (pc)
2030: (if_then_else (leu (cc0)
2031: (const_int 0))
2032: (pc)
2033: (label_ref (match_operand 0 "" ""))))]
2034: ""
2035: "bhi %l0")
2036:
2037: ;; Subtract-and-jump and Add-and-jump insns.
2038: ;; These can actually be used for adding numbers in the range -8 to 7
2039:
2040: (define_insn ""
2041: [(set (pc)
2042: (if_then_else
2043: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2044: (match_operand:SI 1 "general_operand" "i"))
2045: (const_int 0))
2046: (label_ref (match_operand 2 "" ""))
2047: (pc)))
2048: (set (match_dup 0)
2049: (minus:SI (match_dup 0)
2050: (match_dup 1)))]
2051: "GET_CODE (operands[1]) == CONST_INT
2052: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2053: "acbd %$%n1,%0,%l2")
2054:
2055: (define_insn ""
2056: [(set (pc)
2057: (if_then_else
2058: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2059: (match_operand:SI 1 "general_operand" "i"))
2060: (const_int 0))
2061: (label_ref (match_operand 2 "" ""))
2062: (pc)))
2063: (set (match_dup 0)
2064: (plus:SI (match_dup 0)
2065: (match_dup 1)))]
2066: "GET_CODE (operands[1]) == CONST_INT
2067: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2068: "acbd %1,%0,%l2")
2069:
2070: ;; Reversed
2071:
2072: (define_insn ""
2073: [(set (pc)
2074: (if_then_else
2075: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2076: (match_operand:SI 1 "general_operand" "i"))
2077: (const_int 0))
2078: (pc)
2079: (label_ref (match_operand 2 "" ""))))
2080: (set (match_dup 0)
2081: (minus:SI (match_dup 0)
2082: (match_dup 1)))]
2083: "GET_CODE (operands[1]) == CONST_INT
2084: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2085: "acbd %$%n1,%0,%l2")
2086:
2087: (define_insn ""
2088: [(set (pc)
2089: (if_then_else
2090: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2091: (match_operand:SI 1 "general_operand" "i"))
2092: (const_int 0))
2093: (pc)
2094: (label_ref (match_operand 2 "" ""))))
2095: (set (match_dup 0)
2096: (plus:SI (match_dup 0)
2097: (match_dup 1)))]
2098: "GET_CODE (operands[1]) == CONST_INT
2099: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2100: "acbd %1,%0,%l2")
2101:
2102: (define_insn "call"
2103: [(call (match_operand:QI 0 "general_operand" "g")
2104: (match_operand:QI 1 "general_operand" "g"))]
2105: ""
2106: "*
2107: {
2108: if (GET_CODE (operands[0]) == MEM)
2109: {
2110: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.4 ! root 2111: #ifdef GNX_V3
! 2112: return \"bsr %0\";
! 2113: #else
1.1.1.2 root 2114: return \"bsr %?%a0\";
1.1.1.4 ! root 2115: #endif
1.1 root 2116: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.4 ! root 2117: #ifdef GNX_V3
! 2118: return \"jsr %0\";
! 2119: #else
1.1 root 2120: return \"jsr %a0\";
1.1.1.4 ! root 2121: #endif
1.1 root 2122: }
2123: return \"jsr %0\";
2124: }")
2125:
2126: (define_insn "call_value"
2127: [(set (match_operand 0 "" "fg")
2128: (call (match_operand:QI 1 "general_operand" "g")
2129: (match_operand:QI 2 "general_operand" "g")))]
2130: ""
2131: "*
2132: {
2133: if (GET_CODE (operands[1]) == MEM)
2134: {
2135: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.4 ! root 2136: #ifdef GNX_V3
! 2137: return \"bsr %1\";
! 2138: #else
1.1.1.2 root 2139: return \"bsr %?%a1\";
1.1.1.4 ! root 2140: #endif
1.1 root 2141: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.4 ! root 2142: #ifdef GNX_V3
! 2143: return \"jsr %1\";
! 2144: #else
1.1 root 2145: return \"jsr %a1\";
1.1.1.4 ! root 2146: #endif
1.1 root 2147: }
2148: return \"jsr %1\";
2149: }")
2150:
2151: (define_insn "return"
2152: [(return)]
2153: ""
2154: "ret 0")
2155:
2156: (define_insn "abssf2"
2157: [(set (match_operand:SF 0 "general_operand" "=fm<")
2158: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2159: "TARGET_32081"
2160: "absf %1,%0")
2161:
2162: (define_insn "absdf2"
2163: [(set (match_operand:DF 0 "general_operand" "=fm<")
2164: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2165: "TARGET_32081"
2166: "absl %1,%0")
2167:
2168: (define_insn "abssi2"
2169: [(set (match_operand:SI 0 "general_operand" "=g<")
2170: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2171: ""
2172: "absd %1,%0")
2173:
2174: (define_insn "abshi2"
2175: [(set (match_operand:HI 0 "general_operand" "=g<")
2176: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2177: ""
2178: "absw %1,%0")
2179:
2180: (define_insn "absqi2"
2181: [(set (match_operand:QI 0 "general_operand" "=g<")
2182: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2183: ""
2184: "absb %1,%0")
2185:
2186: ;;(define_insn "tablejump"
2187: ;; [(set (pc)
2188: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2189: ;; (pc)))]
2190: ;; ""
2191: ;; "cased %0")
2192:
2193: (define_insn "tablejump"
2194: [(set (pc)
2195: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2196: (use (label_ref (match_operand 1 "" "")))]
2197: ""
2198: "*
2199: {
2200: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2201: CODE_LABEL_NUMBER (operands[1]));
2202: return \"casew %0\";
2203: }")
2204:
2205: ;;(define_insn ""
2206: ;; [(set (pc)
2207: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2208: ;; (pc)))]
2209: ;; ""
2210: ;; "caseb %0")
2211:
2212: ;; Scondi instructions
2213: (define_insn "seq"
2214: [(set (match_operand:SI 0 "general_operand" "=g<")
2215: (eq (cc0) (const_int 0)))]
2216: ""
2217: "*
2218: { if (cc_prev_status.flags & CC_Z_IN_F)
2219: return \"sfcd %0\";
2220: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2221: return \"sfsd %0\";
2222: else return \"seqd %0\";
2223: }")
2224:
2225: (define_insn ""
2226: [(set (match_operand:HI 0 "general_operand" "=g<")
2227: (eq (cc0) (const_int 0)))]
2228: ""
2229: "*
2230: { if (cc_prev_status.flags & CC_Z_IN_F)
2231: return \"sfcw %0\";
2232: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2233: return \"sfsw %0\";
2234: else return \"seqw %0\";
2235: }")
2236:
2237: (define_insn ""
2238: [(set (match_operand:QI 0 "general_operand" "=g<")
2239: (eq (cc0) (const_int 0)))]
2240: ""
2241: "*
2242: { if (cc_prev_status.flags & CC_Z_IN_F)
2243: return \"sfcb %0\";
2244: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2245: return \"sfsb %0\";
2246: else return \"seqb %0\";
2247: }")
2248:
2249: (define_insn "sne"
2250: [(set (match_operand:SI 0 "general_operand" "=g<")
2251: (ne (cc0) (const_int 0)))]
2252: ""
2253: "*
2254: { if (cc_prev_status.flags & CC_Z_IN_F)
2255: return \"sfsd %0\";
2256: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2257: return \"sfcd %0\";
2258: else return \"sned %0\";
2259: }")
2260:
2261: (define_insn ""
2262: [(set (match_operand:HI 0 "general_operand" "=g<")
2263: (ne (cc0) (const_int 0)))]
2264: ""
2265: "*
2266: { if (cc_prev_status.flags & CC_Z_IN_F)
2267: return \"sfsw %0\";
2268: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2269: return \"sfcw %0\";
2270: else return \"snew %0\";
2271: }")
2272:
2273: (define_insn ""
2274: [(set (match_operand:QI 0 "general_operand" "=g<")
2275: (ne (cc0) (const_int 0)))]
2276: ""
2277: "*
2278: { if (cc_prev_status.flags & CC_Z_IN_F)
2279: return \"sfsb %0\";
2280: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2281: return \"sfcb %0\";
2282: else return \"sneb %0\";
2283: }")
2284:
2285: (define_insn "sgt"
2286: [(set (match_operand:SI 0 "general_operand" "=g<")
2287: (gt (cc0) (const_int 0)))]
2288: ""
2289: "sgtd %0")
2290:
2291: (define_insn ""
2292: [(set (match_operand:HI 0 "general_operand" "=g<")
2293: (gt (cc0) (const_int 0)))]
2294: ""
2295: "sgtw %0")
2296:
2297: (define_insn ""
2298: [(set (match_operand:QI 0 "general_operand" "=g<")
2299: (gt (cc0) (const_int 0)))]
2300: ""
2301: "sgtb %0")
2302:
2303: (define_insn "sgtu"
2304: [(set (match_operand:SI 0 "general_operand" "=g<")
2305: (gtu (cc0) (const_int 0)))]
2306: ""
2307: "shid %0")
2308:
2309: (define_insn ""
2310: [(set (match_operand:HI 0 "general_operand" "=g<")
2311: (gtu (cc0) (const_int 0)))]
2312: ""
2313: "shiw %0")
2314:
2315: (define_insn ""
2316: [(set (match_operand:QI 0 "general_operand" "=g<")
2317: (gtu (cc0) (const_int 0)))]
2318: ""
2319: "shib %0")
2320:
2321: (define_insn "slt"
2322: [(set (match_operand:SI 0 "general_operand" "=g<")
2323: (lt (cc0) (const_int 0)))]
2324: ""
2325: "sltd %0")
2326:
2327: (define_insn ""
2328: [(set (match_operand:HI 0 "general_operand" "=g<")
2329: (lt (cc0) (const_int 0)))]
2330: ""
2331: "sltw %0")
2332:
2333: (define_insn ""
2334: [(set (match_operand:QI 0 "general_operand" "=g<")
2335: (lt (cc0) (const_int 0)))]
2336: ""
2337: "sltb %0")
2338:
2339: (define_insn "sltu"
2340: [(set (match_operand:SI 0 "general_operand" "=g<")
2341: (ltu (cc0) (const_int 0)))]
2342: ""
2343: "slod %0")
2344:
2345: (define_insn ""
2346: [(set (match_operand:HI 0 "general_operand" "=g<")
2347: (ltu (cc0) (const_int 0)))]
2348: ""
2349: "slow %0")
2350:
2351: (define_insn ""
2352: [(set (match_operand:QI 0 "general_operand" "=g<")
2353: (ltu (cc0) (const_int 0)))]
2354: ""
2355: "slob %0")
2356:
2357: (define_insn "sge"
2358: [(set (match_operand:SI 0 "general_operand" "=g<")
2359: (ge (cc0) (const_int 0)))]
2360: ""
2361: "sged %0")
2362:
2363: (define_insn ""
2364: [(set (match_operand:HI 0 "general_operand" "=g<")
2365: (ge (cc0) (const_int 0)))]
2366: ""
2367: "sgew %0")
2368:
2369: (define_insn ""
2370: [(set (match_operand:QI 0 "general_operand" "=g<")
2371: (ge (cc0) (const_int 0)))]
2372: ""
2373: "sgeb %0")
2374:
2375: (define_insn "sgeu"
2376: [(set (match_operand:SI 0 "general_operand" "=g<")
2377: (geu (cc0) (const_int 0)))]
2378: ""
2379: "shsd %0")
2380:
2381: (define_insn ""
2382: [(set (match_operand:HI 0 "general_operand" "=g<")
2383: (geu (cc0) (const_int 0)))]
2384: ""
2385: "shsw %0")
2386:
2387: (define_insn ""
2388: [(set (match_operand:QI 0 "general_operand" "=g<")
2389: (geu (cc0) (const_int 0)))]
2390: ""
2391: "shsb %0")
2392:
2393: (define_insn "sle"
2394: [(set (match_operand:SI 0 "general_operand" "=g<")
2395: (le (cc0) (const_int 0)))]
2396: ""
2397: "sled %0")
2398:
2399: (define_insn ""
2400: [(set (match_operand:HI 0 "general_operand" "=g<")
2401: (le (cc0) (const_int 0)))]
2402: ""
2403: "slew %0")
2404:
2405: (define_insn ""
2406: [(set (match_operand:QI 0 "general_operand" "=g<")
2407: (le (cc0) (const_int 0)))]
2408: ""
2409: "sleb %0")
2410:
2411: (define_insn "sleu"
2412: [(set (match_operand:SI 0 "general_operand" "=g<")
2413: (leu (cc0) (const_int 0)))]
2414: ""
2415: "slsd %0")
2416:
2417: (define_insn ""
2418: [(set (match_operand:HI 0 "general_operand" "=g<")
2419: (leu (cc0) (const_int 0)))]
2420: ""
2421: "slsw %0")
2422:
2423: (define_insn ""
2424: [(set (match_operand:QI 0 "general_operand" "=g<")
2425: (leu (cc0) (const_int 0)))]
2426: ""
2427: "slsb %0")
2428:
2429: ;;- Local variables:
2430: ;;- mode:emacs-lisp
2431: ;;- comment-start: ";;- "
2432: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2433: ;;- eval: (modify-syntax-entry ?[ "(]")
2434: ;;- eval: (modify-syntax-entry ?] ")[")
2435: ;;- eval: (modify-syntax-entry ?{ "(}")
2436: ;;- eval: (modify-syntax-entry ?} "){")
2437: ;;- End:
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