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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
1.1.1.2 root 48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
1.1 root 51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "general_operand" "g"))]
55: ""
56: "*
1.1.1.2 root 57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
1.1 root 60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "general_operand" "g"))]
64: ""
65: "*
1.1.1.2 root 66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
1.1 root 69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
1.1.1.2 root 75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = dconst0_rtx;
77: return \"cmpl %1,%0\"; }")
1.1 root 78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
1.1.1.2 root 84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = fconst0_rtx;
86: return \"cmpf %1,%0\"; }")
1.1 root 87:
88: (define_insn "cmpdf"
89: [(set (cc0)
90: (minus (match_operand:DF 0 "general_operand" "fmF")
91: (match_operand:DF 1 "general_operand" "fmF")))]
92: "TARGET_32081"
93: "cmpl %0,%1")
94:
95: (define_insn "cmpsf"
96: [(set (cc0)
97: (minus (match_operand:SF 0 "general_operand" "fmF")
98: (match_operand:SF 1 "general_operand" "fmF")))]
99: "TARGET_32081"
100: "cmpf %0,%1")
101:
102: (define_insn "cmpsi"
103: [(set (cc0)
104: (minus (match_operand:SI 0 "general_operand" "rmn")
105: (match_operand:SI 1 "general_operand" "rmn")))]
106: ""
107: "*
108: {
109: if (GET_CODE (operands[1]) == CONST_INT)
110: {
111: int i = INTVAL (operands[1]);
112: if (i <= 7 && i >= -8)
113: {
114: cc_status.flags |= CC_REVERSED;
115: return \"cmpqd %1,%0\";
116: }
117: }
118: cc_status.flags &= ~CC_REVERSED;
119: if (GET_CODE (operands[0]) == CONST_INT)
120: {
121: int i = INTVAL (operands[0]);
122: if (i <= 7 && i >= -8)
123: return \"cmpqd %0,%1\";
124: }
125: return \"cmpd %0,%1\";
126: }")
127:
128: (define_insn "cmphi"
129: [(set (cc0)
130: (minus (match_operand:HI 0 "general_operand" "g")
131: (match_operand:HI 1 "general_operand" "g")))]
132: ""
133: "*
134: {
135: if (GET_CODE (operands[1]) == CONST_INT)
136: {
137: short i = INTVAL (operands[1]);
138: if (i <= 7 && i >= -8)
139: {
140: cc_status.flags |= CC_REVERSED;
141: if (INTVAL (operands[1]) > 7)
142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
143: return \"cmpqw %1,%0\";
144: }
145: }
146: cc_status.flags &= ~CC_REVERSED;
147: if (GET_CODE (operands[0]) == CONST_INT)
148: {
149: short i = INTVAL (operands[0]);
150: if (i <= 7 && i >= -8)
151: {
152: if (INTVAL (operands[0]) > 7)
153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
154: return \"cmpqw %0,%1\";
155: }
156: }
157: return \"cmpw %0,%1\";
158: }")
159:
160: (define_insn "cmpqi"
161: [(set (cc0)
162: (minus (match_operand:QI 0 "general_operand" "g")
163: (match_operand:QI 1 "general_operand" "g")))]
164: ""
165: "*
166: {
167: if (GET_CODE (operands[1]) == CONST_INT)
168: {
169: char i = INTVAL (operands[1]);
170: if (i <= 7 && i >= -8)
171: {
172: cc_status.flags |= CC_REVERSED;
173: if (INTVAL (operands[1]) > 7)
174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
175: return \"cmpqb %1,%0\";
176: }
177: }
178: cc_status.flags &= ~CC_REVERSED;
179: if (GET_CODE (operands[0]) == CONST_INT)
180: {
181: char i = INTVAL (operands[0]);
182: if (i <= 7 && i >= -8)
183: {
184: if (INTVAL (operands[0]) > 7)
185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
186: return \"cmpqb %0,%1\";
187: }
188: }
189: return \"cmpb %0,%1\";
190: }")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
246: {
247: /* Is there a better machine-independent way to to this? */
248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
249: return \"movd %1,%0\";
250: }
251: else return \"movd %1,%0\";
252: }")
253:
254: (define_insn ""
255: [(set (match_operand:TI 0 "memory_operand" "=m")
256: (match_operand:TI 1 "memory_operand" "m"))]
257: ""
258: "movmd %1,%0,4")
259:
260: (define_insn "movdi"
261: [(set (match_operand:DI 0 "general_operand" "=g<")
1.1.1.3 root 262: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 263: ""
264: "* return output_move_double (operands); ")
265:
266: (define_insn "movsi"
267: [(set (match_operand:SI 0 "general_operand" "=g<")
268: (match_operand:SI 1 "general_operand" "gx"))]
269: ""
270: "*
271: { if (GET_CODE (operands[1]) == CONST_INT)
272: {
273: int i = INTVAL (operands[1]);
274: if (i <= 7 && i >= -8)
275: return \"movqd %1,%0\";
276: if (i < 0x4000 && i >= -0x4000)
1.1.1.4 root 277: #ifdef GNX_V3
278: return \"addr %c1,%0\";
279: #else
1.1.1.2 root 280: return \"addr @%c1,%0\";
1.1.1.4 root 281: #endif
1.1 root 282: return \"movd %1,%0\";
283: }
284: else if (GET_CODE (operands[1]) == REG)
285: if (REGNO (operands[1]) < 16)
286: return \"movd %1,%0\";
287: else if (REGNO (operands[1]) == 16)
288: return \"addr 0(fp),%0\";
289: else return \"addr tos,%0\";
290: else if (GET_CODE (operands[1]) == MEM)
291: return \"movd %1,%0\";
1.1.1.2 root 292: /* Check if this effective address can be
293: calculated faster by pulling it apart. */
294: if (REG_P (operands[0])
295: && GET_CODE (operands[1]) == MULT
296: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
297: && (INTVAL (XEXP (operands[1], 1)) == 2
298: || INTVAL (XEXP (operands[1], 1)) == 4))
299: {
300: rtx xoperands[3];
301: xoperands[0] = operands[0];
302: xoperands[1] = XEXP (operands[1], 0);
303: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
304: return output_shift_insn (xoperands);
305: }
1.1 root 306: return \"addr %a1,%0\";
307: }")
308:
309: (define_insn "movhi"
310: [(set (match_operand:HI 0 "general_operand" "=g<")
311: (match_operand:HI 1 "general_operand" "g"))]
312: ""
313: "*
314: {
315: if (GET_CODE (operands[1]) == CONST_INT)
316: {
317: short i = INTVAL (operands[1]);
318: if (i <= 7 && i >= -8)
319: {
320: if (INTVAL (operands[1]) > 7)
321: operands[1] =
322: gen_rtx (CONST_INT, VOIDmode, i);
323: return \"movqw %1,%0\";
324: }
325: }
326: return \"movw %1,%0\";
327: }")
328:
329: (define_insn "movstricthi"
330: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
331: (match_operand:HI 1 "general_operand" "g"))]
332: ""
333: "*
334: {
335: if (GET_CODE (operands[1]) == CONST_INT
336: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
337: return \"movqw %1,%0\";
338: return \"movw %1,%0\";
339: }")
340:
341: (define_insn "movqi"
342: [(set (match_operand:QI 0 "general_operand" "=g<")
343: (match_operand:QI 1 "general_operand" "g"))]
344: ""
345: "*
346: { if (GET_CODE (operands[1]) == CONST_INT)
347: {
348: char char_val = (char)INTVAL (operands[1]);
349: if (char_val <= 7 && char_val >= -8)
350: {
351: if (INTVAL (operands[1]) > 7)
352: operands[1] =
353: gen_rtx (CONST_INT, VOIDmode, char_val);
354: return \"movqb %1,%0\";
355: }
356: }
357: return \"movb %1,%0\";
358: }")
359:
360: (define_insn "movstrictqi"
361: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
362: (match_operand:QI 1 "general_operand" "g"))]
363: ""
364: "*
365: {
366: if (GET_CODE (operands[1]) == CONST_INT
367: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
368: return \"movqb %1,%0\";
369: return \"movb %1,%0\";
370: }")
371:
372: (define_insn ""
373: [(set (reg:SI 17)
1.1.1.2 root 374: (match_operand:SI 0 "general_operand" "rmn"))]
1.1 root 375: ""
376: "lprd sp,%0")
377:
378: ;; The definition of this insn does not really explain what it does,
379: ;; but it should suffice
380: ;; that anything generated as this insn will be recognized as one
381: ;; and that it won't successfully combine with anything.
382: (define_insn "movstrsi"
383: [(set (match_operand:BLK 0 "general_operand" "=g")
384: (match_operand:BLK 1 "general_operand" "g"))
385: (use (match_operand:SI 2 "general_operand" "rmn"))
386: (clobber (reg:SI 0))
387: (clobber (reg:SI 1))
388: (clobber (reg:SI 2))]
389: ""
390: "*
391: {
392: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
393: abort ();
394: operands[0] = XEXP (operands[0], 0);
395: operands[1] = XEXP (operands[1], 0);
396: if (GET_CODE (operands[0]) == MEM)
397: if (GET_CODE (operands[1]) == MEM)
398: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
399: else
400: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
401: else if (GET_CODE (operands[1]) == MEM)
402: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
403: else
404: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
405:
406: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
407: {
408: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
409: if ((unsigned) INTVAL (operands[2]) <= 7)
410: return \"movqd %2,r0\;movsd\";
411: else
412: return \"movd %2,r0\;movsd\";
413: }
414: else
415: {
416: return \"movd %2,r0\;movsb\";
417: }
418: }")
419:
420: ;; Extension and truncation insns.
421: ;; Those for integer source operand
422: ;; are ordered widest source type first.
423:
424: (define_insn "truncsiqi2"
425: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 426: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 427: ""
428: "movb %1,%0")
429:
430: (define_insn "truncsihi2"
431: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 432: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 433: ""
434: "movw %1,%0")
435:
436: (define_insn "trunchiqi2"
437: [(set (match_operand:QI 0 "general_operand" "=g<")
438: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
439: ""
440: "movb %1,%0")
441:
442: (define_insn "extendhisi2"
443: [(set (match_operand:SI 0 "general_operand" "=g<")
444: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
445: ""
446: "movxwd %1,%0")
447:
448: (define_insn "extendqihi2"
449: [(set (match_operand:HI 0 "general_operand" "=g<")
450: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
451: ""
452: "movxbw %1,%0")
453:
454: (define_insn "extendqisi2"
455: [(set (match_operand:SI 0 "general_operand" "=g<")
456: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
457: ""
458: "movxbd %1,%0")
459:
460: (define_insn "extendsfdf2"
461: [(set (match_operand:DF 0 "general_operand" "=fm<")
462: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
463: "TARGET_32081"
464: "movfl %1,%0")
465:
466: (define_insn "truncdfsf2"
467: [(set (match_operand:SF 0 "general_operand" "=fm<")
468: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
469: "TARGET_32081"
470: "movlf %1,%0")
471:
472: (define_insn "zero_extendhisi2"
473: [(set (match_operand:SI 0 "general_operand" "=g<")
474: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
475: ""
476: "movzwd %1,%0")
477:
478: (define_insn "zero_extendqihi2"
479: [(set (match_operand:HI 0 "general_operand" "=g<")
480: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
481: ""
482: "movzbw %1,%0")
483:
484: (define_insn "zero_extendqisi2"
485: [(set (match_operand:SI 0 "general_operand" "=g<")
486: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
487: ""
488: "movzbd %1,%0")
489:
490: ;; Fix-to-float conversion insns.
491: ;; Note that the ones that start with SImode come first.
492: ;; That is so that an operand that is a CONST_INT
493: ;; (and therefore lacks a specific machine mode).
494: ;; will be recognized as SImode (which is always valid)
495: ;; rather than as QImode or HImode.
496:
497: ;; Rumor has it that the National part does not correctly convert
498: ;; constant ints to floats. This conversion is therefore disabled.
499: ;; A register must be used to perform the conversion.
500:
501: (define_insn "floatsisf2"
502: [(set (match_operand:SF 0 "general_operand" "=fm<")
503: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
504: "TARGET_32081"
505: "movdf %1,%0")
506:
507: (define_insn "floatsidf2"
508: [(set (match_operand:DF 0 "general_operand" "=fm<")
509: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
510: "TARGET_32081"
511: "movdl %1,%0")
512:
513: (define_insn "floathisf2"
514: [(set (match_operand:SF 0 "general_operand" "=fm<")
515: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
516: "TARGET_32081"
517: "movwf %1,%0")
518:
519: (define_insn "floathidf2"
520: [(set (match_operand:DF 0 "general_operand" "=fm<")
521: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
522: "TARGET_32081"
523: "movwl %1,%0")
524:
525: (define_insn "floatqisf2"
526: [(set (match_operand:SF 0 "general_operand" "=fm<")
527: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
528: "TARGET_32081"
529: "movbf %1,%0")
530:
1.1.1.3 root 531: ; Some assemblers warn that this insn doesn't work.
532: ; Maybe they know something we don't.
533: ;(define_insn "floatqidf2"
534: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
535: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
536: ; "TARGET_32081"
537: ; "movbl %1,%0")
1.1 root 538:
539: ;; Float-to-fix conversion insns.
540: ;; The sequent compiler always generates "trunc" insns.
541:
542: (define_insn "fixsfqi2"
543: [(set (match_operand:QI 0 "general_operand" "=g<")
544: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
545: "TARGET_32081"
546: "truncfb %1,%0")
547:
548: (define_insn "fixsfhi2"
549: [(set (match_operand:HI 0 "general_operand" "=g<")
550: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
551: "TARGET_32081"
552: "truncfw %1,%0")
553:
554: (define_insn "fixsfsi2"
555: [(set (match_operand:SI 0 "general_operand" "=g<")
556: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
557: "TARGET_32081"
558: "truncfd %1,%0")
559:
560: (define_insn "fixdfqi2"
561: [(set (match_operand:QI 0 "general_operand" "=g<")
562: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
563: "TARGET_32081"
564: "trunclb %1,%0")
565:
566: (define_insn "fixdfhi2"
567: [(set (match_operand:HI 0 "general_operand" "=g<")
568: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
569: "TARGET_32081"
570: "trunclw %1,%0")
571:
572: (define_insn "fixdfsi2"
573: [(set (match_operand:SI 0 "general_operand" "=g<")
574: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
575: "TARGET_32081"
576: "truncld %1,%0")
577:
578: ;; Unsigned
579:
580: (define_insn "fixunssfqi2"
581: [(set (match_operand:QI 0 "general_operand" "=g<")
582: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
583: "TARGET_32081"
584: "truncfb %1,%0")
585:
586: (define_insn "fixunssfhi2"
587: [(set (match_operand:HI 0 "general_operand" "=g<")
588: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
589: "TARGET_32081"
590: "truncfw %1,%0")
591:
592: (define_insn "fixunssfsi2"
593: [(set (match_operand:SI 0 "general_operand" "=g<")
594: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
595: "TARGET_32081"
596: "truncfd %1,%0")
597:
598: (define_insn "fixunsdfqi2"
599: [(set (match_operand:QI 0 "general_operand" "=g<")
600: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
601: "TARGET_32081"
602: "trunclb %1,%0")
603:
604: (define_insn "fixunsdfhi2"
605: [(set (match_operand:HI 0 "general_operand" "=g<")
606: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
607: "TARGET_32081"
608: "trunclw %1,%0")
609:
610: (define_insn "fixunsdfsi2"
611: [(set (match_operand:SI 0 "general_operand" "=g<")
612: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
613: "TARGET_32081"
614: "truncld %1,%0")
615:
616: ;;; These are not yet used by GCC
617: (define_insn "fix_truncsfqi2"
618: [(set (match_operand:QI 0 "general_operand" "=g<")
619: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
620: "TARGET_32081"
621: "truncfb %1,%0")
622:
623: (define_insn "fix_truncsfhi2"
624: [(set (match_operand:HI 0 "general_operand" "=g<")
625: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
626: "TARGET_32081"
627: "truncfw %1,%0")
628:
629: (define_insn "fix_truncsfsi2"
630: [(set (match_operand:SI 0 "general_operand" "=g<")
631: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
632: "TARGET_32081"
633: "truncfd %1,%0")
634:
635: (define_insn "fix_truncdfqi2"
636: [(set (match_operand:QI 0 "general_operand" "=g<")
637: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
638: "TARGET_32081"
639: "trunclb %1,%0")
640:
641: (define_insn "fix_truncdfhi2"
642: [(set (match_operand:HI 0 "general_operand" "=g<")
643: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
644: "TARGET_32081"
645: "trunclw %1,%0")
646:
647: (define_insn "fix_truncdfsi2"
648: [(set (match_operand:SI 0 "general_operand" "=g<")
649: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
650: "TARGET_32081"
651: "truncld %1,%0")
652:
653: ;;- All kinds of add instructions.
654:
655: (define_insn "adddf3"
656: [(set (match_operand:DF 0 "general_operand" "=fm")
657: (plus:DF (match_operand:DF 1 "general_operand" "%0")
658: (match_operand:DF 2 "general_operand" "fmF")))]
659: "TARGET_32081"
660: "addl %2,%0")
661:
662:
663: (define_insn "addsf3"
664: [(set (match_operand:SF 0 "general_operand" "=fm")
665: (plus:SF (match_operand:SF 1 "general_operand" "%0")
666: (match_operand:SF 2 "general_operand" "fmF")))]
667: "TARGET_32081"
668: "addf %2,%0")
669:
670: (define_insn ""
671: [(set (reg:SI 17)
672: (plus:SI (reg:SI 17)
673: (match_operand:SI 0 "immediate_operand" "i")))]
674: "GET_CODE (operands[0]) == CONST_INT"
675: "*
676: {
1.1.1.6 ! root 677: #if defined(ns32532)
! 678: if (INTVAL(operands[0]) == 8)
! 679: return \"cmpd tos,tos # adjsp -8\";
! 680: #endif
! 681: #if defined(ns32532) || defined(ns32332)
! 682: if (INTVAL(operands[0]) == 4)
! 683: return \"cmpqd %$0,tos # adjsp -4\";
! 684: #endif
1.1 root 685: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
686: return \"adjspb %$%n0\";
687: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
688: return \"adjspw %$%n0\";
689: return \"adjspd %$%n0\";
690: }")
691:
692: (define_insn ""
693: [(set (match_operand:SI 0 "general_operand" "=g<")
694: (plus:SI (reg:SI 16)
695: (match_operand:SI 1 "immediate_operand" "i")))]
696: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 697: "addr %c1(fp),%0")
1.1 root 698:
699: (define_insn ""
700: [(set (match_operand:SI 0 "general_operand" "=g<")
701: (plus:SI (reg:SI 17)
702: (match_operand:SI 1 "immediate_operand" "i")))]
703: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 704: "addr %c1(sp),%0")
1.1 root 705:
706: (define_insn "addsi3"
707: [(set (match_operand:SI 0 "general_operand" "=g")
708: (plus:SI (match_operand:SI 1 "general_operand" "%0")
709: (match_operand:SI 2 "general_operand" "rmn")))]
710: ""
711: "*
712: {
713: if (GET_CODE (operands[2]) == CONST_INT)
714: {
715: int i = INTVAL (operands[2]);
716:
717: if (i <= 7 && i >= -8)
718: return \"addqd %2,%0\";
719: else if (GET_CODE (operands[0]) == REG
720: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 721: return \"addr %c2(%0),%0\";
1.1 root 722: }
723: return \"addd %2,%0\";
724: }")
725:
726: (define_insn "addhi3"
727: [(set (match_operand:HI 0 "general_operand" "=g")
728: (plus:HI (match_operand:HI 1 "general_operand" "%0")
729: (match_operand:HI 2 "general_operand" "g")))]
730: ""
731: "*
732: { if (GET_CODE (operands[2]) == CONST_INT)
733: {
734: int i = INTVAL (operands[2]);
735: if (i <= 7 && i >= -8)
736: return \"addqw %2,%0\";
737: }
738: return \"addw %2,%0\";
739: }")
740:
741: (define_insn ""
742: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
743: (plus:HI (match_operand:HI 1 "general_operand" "0")
744: (match_operand:HI 2 "general_operand" "g")))]
745: ""
746: "*
747: {
748: if (GET_CODE (operands[1]) == CONST_INT
749: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
750: return \"addqw %1,%0\";
751: return \"addw %1,%0\";
752: }")
753:
754: (define_insn "addqi3"
755: [(set (match_operand:QI 0 "general_operand" "=g")
756: (plus:QI (match_operand:QI 1 "general_operand" "%0")
757: (match_operand:QI 2 "general_operand" "g")))]
758: ""
759: "*
760: { if (GET_CODE (operands[2]) == CONST_INT)
761: {
762: int i = INTVAL (operands[2]);
763: if (i <= 7 && i >= -8)
764: return \"addqb %2,%0\";
765: }
766: return \"addb %2,%0\";
767: }")
768:
769: (define_insn ""
770: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
771: (plus:QI (match_operand:QI 1 "general_operand" "0")
772: (match_operand:QI 2 "general_operand" "g")))]
773: ""
774: "*
775: {
776: if (GET_CODE (operands[1]) == CONST_INT
777: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
778: return \"addqb %1,%0\";
779: return \"addb %1,%0\";
780: }")
781:
782: ;;- All kinds of subtract instructions.
783:
784: (define_insn "subdf3"
785: [(set (match_operand:DF 0 "general_operand" "=fm")
786: (minus:DF (match_operand:DF 1 "general_operand" "0")
787: (match_operand:DF 2 "general_operand" "fmF")))]
788: "TARGET_32081"
789: "subl %2,%0")
790:
791: (define_insn "subsf3"
792: [(set (match_operand:SF 0 "general_operand" "=fm")
793: (minus:SF (match_operand:SF 1 "general_operand" "0")
794: (match_operand:SF 2 "general_operand" "fmF")))]
795: "TARGET_32081"
796: "subf %2,%0")
797:
798: (define_insn ""
799: [(set (reg:SI 17)
800: (minus:SI (reg:SI 17)
801: (match_operand:SI 0 "immediate_operand" "i")))]
802: "GET_CODE (operands[0]) == CONST_INT"
803: "*
804: {
805: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
806: && INTVAL(operands[0]) > -64)
807: return \"adjspb %0\";
808: return \"adjspd %0\";
809: }")
810:
811: (define_insn "subsi3"
812: [(set (match_operand:SI 0 "general_operand" "=g")
813: (minus:SI (match_operand:SI 1 "general_operand" "0")
814: (match_operand:SI 2 "general_operand" "rmn")))]
815: ""
816: "*
817: { if (GET_CODE (operands[2]) == CONST_INT)
818: {
819: int i = INTVAL (operands[2]);
820:
821: if (i <= 8 && i >= -7)
822: return \"addqd %$%n2,%0\";
823: }
824: return \"subd %2,%0\";
825: }")
826:
827: (define_insn "subhi3"
828: [(set (match_operand:HI 0 "general_operand" "=g")
829: (minus:HI (match_operand:HI 1 "general_operand" "0")
830: (match_operand:HI 2 "general_operand" "g")))]
831: ""
832: "*
833: { if (GET_CODE (operands[2]) == CONST_INT)
834: {
835: int i = INTVAL (operands[2]);
836:
837: if (i <= 8 && i >= -7)
838: return \"addqw %$%n2,%0\";
839: }
840: return \"subw %2,%0\";
841: }")
842:
843: (define_insn ""
844: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
845: (minus:HI (match_operand:HI 1 "general_operand" "0")
846: (match_operand:HI 2 "general_operand" "g")))]
847: ""
848: "*
849: {
850: if (GET_CODE (operands[1]) == CONST_INT
851: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
852: return \"addqw %$%n1,%0\";
853: return \"subw %1,%0\";
854: }")
855:
856: (define_insn "subqi3"
857: [(set (match_operand:QI 0 "general_operand" "=g")
858: (minus:QI (match_operand:QI 1 "general_operand" "0")
859: (match_operand:QI 2 "general_operand" "g")))]
860: ""
861: "*
862: { if (GET_CODE (operands[2]) == CONST_INT)
863: {
864: int i = INTVAL (operands[2]);
865:
866: if (i <= 8 && i >= -7)
867: return \"addqb %$%n2,%0\";
868: }
869: return \"subb %2,%0\";
870: }")
871:
872: (define_insn ""
873: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
874: (minus:QI (match_operand:QI 1 "general_operand" "0")
875: (match_operand:QI 2 "general_operand" "g")))]
876: ""
877: "*
878: {
879: if (GET_CODE (operands[1]) == CONST_INT
880: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
881: return \"addqb %$%n1,%0\";
882: return \"subb %1,%0\";
883: }")
884:
885: ;;- Multiply instructions.
886:
887: (define_insn "muldf3"
888: [(set (match_operand:DF 0 "general_operand" "=fm")
889: (mult:DF (match_operand:DF 1 "general_operand" "%0")
890: (match_operand:DF 2 "general_operand" "fmF")))]
891: "TARGET_32081"
892: "mull %2,%0")
893:
894: (define_insn "mulsf3"
895: [(set (match_operand:SF 0 "general_operand" "=fm")
896: (mult:SF (match_operand:SF 1 "general_operand" "%0")
897: (match_operand:SF 2 "general_operand" "fmF")))]
898: "TARGET_32081"
899: "mulf %2,%0")
900:
901: (define_insn "mulsi3"
902: [(set (match_operand:SI 0 "general_operand" "=g")
903: (mult:SI (match_operand:SI 1 "general_operand" "%0")
904: (match_operand:SI 2 "general_operand" "rmn")))]
905: ""
906: "muld %2,%0")
907:
908: (define_insn "mulhi3"
909: [(set (match_operand:HI 0 "general_operand" "=g")
910: (mult:HI (match_operand:HI 1 "general_operand" "%0")
911: (match_operand:HI 2 "general_operand" "g")))]
912: ""
913: "mulw %2,%0")
914:
915: (define_insn "mulqi3"
916: [(set (match_operand:QI 0 "general_operand" "=g")
917: (mult:QI (match_operand:QI 1 "general_operand" "%0")
918: (match_operand:QI 2 "general_operand" "g")))]
919: ""
920: "mulb %2,%0")
921:
922: (define_insn "umulsi3"
923: [(set (match_operand:SI 0 "general_operand" "=g")
924: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 925: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 926: ""
927: "muld %2,%0")
928:
929: (define_insn "umulhi3"
930: [(set (match_operand:HI 0 "general_operand" "=g")
931: (umult:HI (match_operand:HI 1 "general_operand" "%0")
932: (match_operand:HI 2 "general_operand" "g")))]
933: ""
934: "mulw %2,%0")
935:
936: (define_insn "umulqi3"
937: [(set (match_operand:QI 0 "general_operand" "=g")
938: (umult:QI (match_operand:QI 1 "general_operand" "%0")
939: (match_operand:QI 2 "general_operand" "g")))]
940: ""
941: "mulb %2,%0")
942:
943: (define_insn "umulsidi3"
944: [(set (match_operand:DI 0 "general_operand" "=g")
945: (umult:DI (match_operand:SI 1 "general_operand" "0")
946: (match_operand:SI 2 "general_operand" "rmn")))]
947: ""
948: "meid %2,%0")
949:
950: ;;- Divide instructions.
951:
952: (define_insn "divdf3"
953: [(set (match_operand:DF 0 "general_operand" "=fm")
954: (div:DF (match_operand:DF 1 "general_operand" "0")
955: (match_operand:DF 2 "general_operand" "fmF")))]
956: "TARGET_32081"
957: "divl %2,%0")
958:
959: (define_insn "divsf3"
960: [(set (match_operand:SF 0 "general_operand" "=fm")
961: (div:SF (match_operand:SF 1 "general_operand" "0")
962: (match_operand:SF 2 "general_operand" "fmF")))]
963: "TARGET_32081"
964: "divf %2,%0")
965:
966: (define_insn "divsi3"
967: [(set (match_operand:SI 0 "general_operand" "=g")
968: (div:SI (match_operand:SI 1 "general_operand" "0")
969: (match_operand:SI 2 "general_operand" "rmn")))]
970: ""
971: "quod %2,%0")
972:
973: (define_insn "divhi3"
974: [(set (match_operand:HI 0 "general_operand" "=g")
975: (div:HI (match_operand:HI 1 "general_operand" "0")
976: (match_operand:HI 2 "general_operand" "g")))]
977: ""
978: "quow %2,%0")
979:
980: (define_insn "divqi3"
981: [(set (match_operand:QI 0 "general_operand" "=g")
982: (div:QI (match_operand:QI 1 "general_operand" "0")
983: (match_operand:QI 2 "general_operand" "g")))]
984: ""
985: "quob %2,%0")
986:
987: (define_insn "udivsi3"
988: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 989: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 990: (match_operand:SI 2 "general_operand" "rmn")))]
991: ""
992: "*
993: {
994: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
995: return \"deid %2,%0\;movd %1,%0\";
996: }")
997:
998: (define_insn "udivhi3"
999: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1000: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1001: (match_operand:HI 2 "general_operand" "g")))]
1002: ""
1003: "*
1004: {
1005: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1006: return \"deiw %2,%0\;movw %1,%0\";
1007: }")
1008:
1009: (define_insn "udivqi3"
1010: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1011: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1012: (match_operand:QI 2 "general_operand" "g")))]
1013: ""
1014: "*
1015: {
1016: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1017: return \"deib %2,%0\;movb %1,%0\";
1018: }")
1019:
1020: ;; Remainder instructions.
1021:
1022: (define_insn "modsi3"
1023: [(set (match_operand:SI 0 "general_operand" "=g")
1024: (mod:SI (match_operand:SI 1 "general_operand" "0")
1025: (match_operand:SI 2 "general_operand" "rmn")))]
1026: ""
1027: "remd %2,%0")
1028:
1029: (define_insn "modhi3"
1030: [(set (match_operand:HI 0 "general_operand" "=g")
1031: (mod:HI (match_operand:HI 1 "general_operand" "0")
1032: (match_operand:HI 2 "general_operand" "g")))]
1033: ""
1034: "remw %2,%0")
1035:
1036: (define_insn "modqi3"
1037: [(set (match_operand:QI 0 "general_operand" "=g")
1038: (mod:QI (match_operand:QI 1 "general_operand" "0")
1039: (match_operand:QI 2 "general_operand" "g")))]
1040: ""
1041: "remb %2,%0")
1042:
1043: (define_insn "umodsi3"
1044: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1045: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1046: (match_operand:SI 2 "general_operand" "rmn")))]
1047: ""
1048: "deid %2,%0")
1049:
1050: (define_insn "umodhi3"
1051: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1052: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1053: (match_operand:HI 2 "general_operand" "g")))]
1054: ""
1055: "deiw %2,%0")
1056:
1057: (define_insn "umodqi3"
1058: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1059: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1060: (match_operand:QI 2 "general_operand" "g")))]
1061: ""
1062: "deib %2,%0")
1063:
1064: ; This isn't be usable in its current form.
1065: ;(define_insn "udivmoddisi4"
1066: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1067: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1068: ; (match_operand:SI 2 "general_operand" "rmn")))
1069: ; (set (subreg:SI (match_dup 0) 0)
1070: ; (umod:SI (match_dup 1) (match_dup 2)))]
1071: ; ""
1072: ; "deid %2,%0")
1073:
1074: ;;- Logical Instructions: AND
1075:
1076: (define_insn "andsi3"
1077: [(set (match_operand:SI 0 "general_operand" "=g")
1078: (and:SI (match_operand:SI 1 "general_operand" "%0")
1079: (match_operand:SI 2 "general_operand" "rmn")))]
1080: ""
1081: "*
1082: {
1083: if (GET_CODE (operands[2]) == CONST_INT) {
1084: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1085: if (INTVAL (operands[2]) == 0xffffff00)
1086: return \"movqb %$0,%0\";
1087: else {
1088: INTVAL (operands[2]) &= 0xff;
1089: return \"andb %2,%0\";
1090: }
1091: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1092: if (INTVAL (operands[2]) == 0xffff0000)
1093: return \"movqw %$0,%0\";
1094: else {
1095: INTVAL (operands[2]) &= 0xffff;
1096: return \"andw %2,%0\";
1097: }
1098: }
1099: return \"andd %2,%0\";
1100: }")
1101:
1102: (define_insn "andhi3"
1103: [(set (match_operand:HI 0 "general_operand" "=g")
1104: (and:HI (match_operand:HI 1 "general_operand" "%0")
1105: (match_operand:HI 2 "general_operand" "g")))]
1106: ""
1107: "*
1108: {
1109: if (GET_CODE (operands[2]) == CONST_INT
1110: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1111: if (INTVAL (operands[2]) == 0xffffff00)
1112: return \"movqb %$0,%0\";
1113: else {
1114: INTVAL (operands[2]) &= 0xff;
1115: return \"andb %2,%0\";
1116: }
1117: return \"andw %2,%0\";
1118: }")
1119:
1120: (define_insn "andqi3"
1121: [(set (match_operand:QI 0 "general_operand" "=g")
1122: (and:QI (match_operand:QI 1 "general_operand" "%0")
1123: (match_operand:QI 2 "general_operand" "g")))]
1124: ""
1125: "andb %2,%0")
1126:
1127: (define_insn "andcbsi3"
1128: [(set (match_operand:SI 0 "general_operand" "=g")
1129: (and:SI (match_operand:SI 1 "general_operand" "0")
1130: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1131: ""
1132: "*
1133: {
1134: if (GET_CODE (operands[2]) == CONST_INT)
1135: {
1136: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1137: return \"bicb %2,%0\";
1138: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1139: return \"bicw %2,%0\";
1140: }
1141: return \"bicd %2,%0\";
1142: }")
1143:
1144: (define_insn ""
1145: [(set (match_operand:SI 0 "general_operand" "=g")
1146: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1147: (match_operand:SI 2 "general_operand" "0")))]
1148: ""
1149: "*
1150: {
1151: if (GET_CODE (operands[1]) == CONST_INT)
1152: {
1153: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1154: return \"bicb %1,%0\";
1155: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1156: return \"bicw %1,%0\";
1157: }
1158: return \"bicd %1,%0\";
1159: }")
1160:
1161: (define_insn "andcbhi3"
1162: [(set (match_operand:HI 0 "general_operand" "=g")
1163: (and:HI (match_operand:HI 1 "general_operand" "%0")
1164: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1165: ""
1166: "*
1167: {
1168: if (GET_CODE (operands[2]) == CONST_INT
1169: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1170: return \"bicb %2,%0\";
1171: return \"bicw %2,%0\";
1172: }")
1173:
1174: (define_insn ""
1175: [(set (match_operand:HI 0 "general_operand" "=g")
1176: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1177: (match_operand:HI 2 "general_operand" "0")))]
1178: ""
1179: "*
1180: {
1181: if (GET_CODE (operands[1]) == CONST_INT
1182: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1183: return \"bicb %1,%0\";
1184: return \"bicw %1,%0\";
1185: }")
1186:
1187: (define_insn "andcbqi3"
1188: [(set (match_operand:QI 0 "general_operand" "=g")
1189: (and:QI (match_operand:QI 1 "general_operand" "%0")
1190: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1191: ""
1192: "bicb %2,%0")
1193:
1194: (define_insn ""
1195: [(set (match_operand:QI 0 "general_operand" "=g")
1196: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1197: (match_operand:QI 2 "general_operand" "0")))]
1198: ""
1199: "bicb %1,%0")
1200:
1201: ;;- Bit set instructions.
1202:
1203: (define_insn "iorsi3"
1204: [(set (match_operand:SI 0 "general_operand" "=g")
1205: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1206: (match_operand:SI 2 "general_operand" "rmn")))]
1207: ""
1208: "*
1209: {
1210: if (GET_CODE (operands[2]) == CONST_INT) {
1211: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1212: return \"orb %2,%0\";
1213: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1214: return \"orw %2,%0\";
1215: }
1216: return \"ord %2,%0\";
1217: }")
1218:
1219: (define_insn "iorhi3"
1220: [(set (match_operand:HI 0 "general_operand" "=g")
1221: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1222: (match_operand:HI 2 "general_operand" "g")))]
1223: ""
1224: "*
1225: {
1226: if (GET_CODE(operands[2]) == CONST_INT &&
1227: (INTVAL(operands[2]) & 0xffffff00) == 0)
1228: return \"orb %2,%0\";
1229: return \"orw %2,%0\";
1230: }")
1231:
1232: (define_insn "iorqi3"
1233: [(set (match_operand:QI 0 "general_operand" "=g")
1234: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1235: (match_operand:QI 2 "general_operand" "g")))]
1236: ""
1237: "orb %2,%0")
1238:
1239: ;;- xor instructions.
1240:
1241: (define_insn "xorsi3"
1242: [(set (match_operand:SI 0 "general_operand" "=g")
1243: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1244: (match_operand:SI 2 "general_operand" "rmn")))]
1245: ""
1246: "*
1247: {
1248: if (GET_CODE (operands[2]) == CONST_INT) {
1249: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1250: return \"xorb %2,%0\";
1251: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1252: return \"xorw %2,%0\";
1253: }
1254: return \"xord %2,%0\";
1255: }")
1256:
1257: (define_insn "xorhi3"
1258: [(set (match_operand:HI 0 "general_operand" "=g")
1259: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1260: (match_operand:HI 2 "general_operand" "g")))]
1261: ""
1262: "*
1263: {
1264: if (GET_CODE(operands[2]) == CONST_INT &&
1265: (INTVAL(operands[2]) & 0xffffff00) == 0)
1266: return \"xorb %2,%0\";
1267: return \"xorw %2,%0\";
1268: }")
1269:
1270: (define_insn "xorqi3"
1271: [(set (match_operand:QI 0 "general_operand" "=g")
1272: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1273: (match_operand:QI 2 "general_operand" "g")))]
1274: ""
1275: "xorb %2,%0")
1276:
1277: (define_insn "negdf2"
1278: [(set (match_operand:DF 0 "general_operand" "=fm<")
1279: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1280: "TARGET_32081"
1281: "negl %1,%0")
1282:
1283: (define_insn "negsf2"
1284: [(set (match_operand:SF 0 "general_operand" "=fm<")
1285: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1286: "TARGET_32081"
1287: "negf %1,%0")
1288:
1289: (define_insn "negsi2"
1290: [(set (match_operand:SI 0 "general_operand" "=g<")
1291: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1292: ""
1293: "negd %1,%0")
1294:
1295: (define_insn "neghi2"
1296: [(set (match_operand:HI 0 "general_operand" "=g<")
1297: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1298: ""
1299: "negw %1,%0")
1300:
1301: (define_insn "negqi2"
1302: [(set (match_operand:QI 0 "general_operand" "=g<")
1303: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1304: ""
1305: "negb %1,%0")
1306:
1307: (define_insn "one_cmplsi2"
1308: [(set (match_operand:SI 0 "general_operand" "=g<")
1309: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1310: ""
1311: "comd %1,%0")
1312:
1313: (define_insn "one_cmplhi2"
1314: [(set (match_operand:HI 0 "general_operand" "=g<")
1315: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1316: ""
1317: "comw %1,%0")
1318:
1319: (define_insn "one_cmplqi2"
1320: [(set (match_operand:QI 0 "general_operand" "=g<")
1321: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1322: ""
1323: "comb %1,%0")
1324:
1325: ;; arithmetic left and right shift operations
1326:
1327: (define_insn "ashlsi3"
1328: [(set (match_operand:SI 0 "general_operand" "=g,g")
1329: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1330: (match_operand:SI 2 "general_operand" "I,rmn")))]
1331: ""
1.1.1.2 root 1332: "* output_shift_insn (operands);")
1.1 root 1333:
1334: (define_insn ""
1335: [(set (match_operand:SI 0 "general_operand" "=g")
1336: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1337: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1338: (const_int 31))))]
1339: ""
1340: "ashd %2,%0")
1341:
1342: (define_insn "ashlhi3"
1343: [(set (match_operand:HI 0 "general_operand" "=g")
1344: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1345: (match_operand:SI 2 "general_operand" "rmn")))]
1346: ""
1347: "*
1348: { if (GET_CODE (operands[2]) == CONST_INT)
1349: if (INTVAL (operands[2]) == 1)
1350: return \"addw %1,%0\";
1351: else if (INTVAL (operands[2]) == 2)
1352: return \"addw %1,%0\;addw %0,%0\";
1353: return \"ashw %2,%0\";
1354: }")
1355:
1356: (define_insn "ashlqi3"
1357: [(set (match_operand:QI 0 "general_operand" "=g")
1358: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1359: (match_operand:SI 2 "general_operand" "rmn")))]
1360: ""
1361: "*
1362: { if (GET_CODE (operands[2]) == CONST_INT)
1363: if (INTVAL (operands[2]) == 1)
1364: return \"addb %1,%0\";
1365: else if (INTVAL (operands[2]) == 2)
1366: return \"addb %1,%0\;addb %0,%0\";
1367: return \"ashb %2,%0\";
1368: }")
1369:
1.1.1.6 ! root 1370: ;; Arithmetic right shift on the 32k works by negating the shift count.
! 1371: (define_expand "ashrsi3"
! 1372: [(set (match_operand:SI 0 "general_operand" "=g")
! 1373: (ashift:SI (match_operand:SI 1 "general_operand" "g")
! 1374: (match_operand:SI 2 "general_operand" "g")))]
! 1375: ""
! 1376: "
! 1377: {
! 1378: extern rtx negate_rtx ();
! 1379: operands[2] = negate_rtx (operands[2]);
! 1380: }")
! 1381:
! 1382: (define_expand "ashrhi3"
! 1383: [(set (match_operand:HI 0 "general_operand" "=g")
! 1384: (ashift:HI (match_operand:HI 1 "general_operand" "g")
! 1385: (match_operand:SI 2 "general_operand" "g")))]
! 1386: ""
! 1387: "
! 1388: {
! 1389: extern rtx negate_rtx ();
! 1390: operands[2] = negate_rtx (operands[2]);
! 1391: }")
! 1392:
! 1393: (define_expand "ashrqi3"
! 1394: [(set (match_operand:QI 0 "general_operand" "=g")
! 1395: (ashift:QI (match_operand:QI 1 "general_operand" "g")
! 1396: (match_operand:SI 2 "general_operand" "g")))]
! 1397: ""
! 1398: "
! 1399: {
! 1400: extern rtx negate_rtx ();
! 1401: operands[2] = negate_rtx (operands[2]);
! 1402: }")
! 1403:
1.1 root 1404: ;; logical shift instructions
1405:
1406: (define_insn "lshlsi3"
1407: [(set (match_operand:SI 0 "general_operand" "=g")
1408: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1409: (match_operand:SI 2 "general_operand" "rmn")))]
1410: ""
1411: "lshd %2,%0")
1412:
1413: (define_insn ""
1414: [(set (match_operand:SI 0 "general_operand" "=g")
1415: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1416: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1417: (const_int 31))))]
1418: ""
1419: "lshd %2,%0")
1420:
1421: (define_insn "lshlhi3"
1422: [(set (match_operand:HI 0 "general_operand" "=g")
1423: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1424: (match_operand:SI 2 "general_operand" "rmn")))]
1425: ""
1426: "lshw %2,%0")
1427:
1428: (define_insn "lshlqi3"
1429: [(set (match_operand:QI 0 "general_operand" "=g")
1430: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1431: (match_operand:SI 2 "general_operand" "rmn")))]
1432: ""
1433: "lshb %2,%0")
1434:
1.1.1.6 ! root 1435: ;; Logical right shift on the 32k works by negating the shift count.
! 1436: (define_expand "lshrsi3"
! 1437: [(set (match_operand:SI 0 "general_operand" "=g")
! 1438: (lshift:SI (match_operand:SI 1 "general_operand" "g")
! 1439: (match_operand:SI 2 "general_operand" "g")))]
! 1440: ""
! 1441: "
! 1442: {
! 1443: extern rtx negate_rtx ();
! 1444: operands[2] = negate_rtx (operands[2]);
! 1445: }")
! 1446:
! 1447: (define_expand "lshrhi3"
! 1448: [(set (match_operand:HI 0 "general_operand" "=g")
! 1449: (lshift:HI (match_operand:HI 1 "general_operand" "g")
! 1450: (match_operand:SI 2 "general_operand" "g")))]
! 1451: ""
! 1452: "
! 1453: {
! 1454: extern rtx negate_rtx ();
! 1455: operands[2] = negate_rtx (operands[2]);
! 1456: }")
! 1457:
! 1458: (define_expand "lshrqi3"
! 1459: [(set (match_operand:QI 0 "general_operand" "=g")
! 1460: (lshift:QI (match_operand:QI 1 "general_operand" "g")
! 1461: (match_operand:SI 2 "general_operand" "g")))]
! 1462: ""
! 1463: "
! 1464: {
! 1465: extern rtx negate_rtx ();
! 1466: operands[2] = negate_rtx (operands[2]);
! 1467: }")
! 1468:
1.1 root 1469: ;; Rotate instructions
1470:
1471: (define_insn "rotlsi3"
1472: [(set (match_operand:SI 0 "general_operand" "=g")
1473: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1474: (match_operand:SI 2 "general_operand" "rmn")))]
1475: ""
1476: "rotd %2,%0")
1477:
1478: (define_insn "rotlhi3"
1479: [(set (match_operand:HI 0 "general_operand" "=g")
1480: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1481: (match_operand:SI 2 "general_operand" "rmn")))]
1482: ""
1483: "rotw %2,%0")
1484:
1485: (define_insn "rotlqi3"
1486: [(set (match_operand:QI 0 "general_operand" "=g")
1487: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1488: (match_operand:SI 2 "general_operand" "rmn")))]
1489: ""
1490: "rotb %2,%0")
1.1.1.6 ! root 1491:
! 1492: ;; Right rotate on the 32k works by negating the shift count.
! 1493: (define_expand "rotrsi3"
! 1494: [(set (match_operand:SI 0 "general_operand" "=g")
! 1495: (rotate:SI (match_operand:SI 1 "general_operand" "g")
! 1496: (match_operand:SI 2 "general_operand" "g")))]
! 1497: ""
! 1498: "
! 1499: {
! 1500: extern rtx negate_rtx ();
! 1501: operands[2] = negate_rtx (operands[2]);
! 1502: }")
! 1503:
! 1504: (define_expand "rotrhi3"
! 1505: [(set (match_operand:HI 0 "general_operand" "=g")
! 1506: (rotate:HI (match_operand:HI 1 "general_operand" "g")
! 1507: (match_operand:SI 2 "general_operand" "g")))]
! 1508: ""
! 1509: "
! 1510: {
! 1511: extern rtx negate_rtx ();
! 1512: operands[2] = negate_rtx (operands[2]);
! 1513: }")
! 1514:
! 1515: (define_expand "rotrqi3"
! 1516: [(set (match_operand:QI 0 "general_operand" "=g")
! 1517: (rotate:QI (match_operand:QI 1 "general_operand" "g")
! 1518: (match_operand:SI 2 "general_operand" "g")))]
! 1519: ""
! 1520: "
! 1521: {
! 1522: extern rtx negate_rtx ();
! 1523: operands[2] = negate_rtx (operands[2]);
! 1524: }")
1.1 root 1525:
1526: ;;- load or push effective address
1527: ;; These come after the move, add, and multiply patterns
1528: ;; because we don't want pushl $1 turned into pushad 1.
1529:
1530: (define_insn ""
1531: [(set (match_operand:SI 0 "general_operand" "=g<")
1532: (match_operand:QI 1 "address_operand" "p"))]
1533: ""
1.1.1.2 root 1534: "*
1535: {
1536: if (REG_P (operands[0])
1537: && GET_CODE (operands[1]) == MULT
1538: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1539: && (INTVAL (XEXP (operands[1], 1)) == 2
1540: || INTVAL (XEXP (operands[1], 1)) == 4))
1541: {
1542: rtx xoperands[3];
1543: xoperands[0] = operands[0];
1544: xoperands[1] = XEXP (operands[1], 0);
1545: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1546: return output_shift_insn (xoperands);
1547: }
1548: return \"addr %a1,%0\";
1549: }")
1.1 root 1550:
1551: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1552: ;;; but slower then using power-of-2 shifts if we can use them
1553: ;
1554: ;(define_insn ""
1555: ; [(set (match_operand:SI 0 "register_operand" "=r")
1556: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1557: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1558: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1559: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1560: ; "indexd %0,%3,%1")
1561: ;
1562: ;(define_insn ""
1563: ; [(set (match_operand:SI 0 "register_operand" "=r")
1564: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1565: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1566: ; (match_operand:SI 3 "general_operand" "rmn")))]
1567: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1568: ; "indexd %0,%2,%3")
1569:
1570: ;; Set, Clear, and Invert bit
1571:
1572: (define_insn ""
1573: [(set (match_operand:SI 0 "general_operand" "=g")
1574: (ior:SI
1575: (ashift:SI (const_int 1)
1576: (match_operand:SI 1 "general_operand" "rmn"))
1577: (match_dup 0)))]
1578: ""
1579: "sbitd %1,%0")
1580:
1581: (define_insn ""
1582: [(set (match_operand:SI 0 "general_operand" "=g")
1583: (ior:SI
1584: (match_dup 0)
1585: (ashift:SI (const_int 1)
1586: (match_operand:SI 1 "general_operand" "rmn"))))]
1587: ""
1588: "sbitd %1,%0")
1589:
1590: (define_insn ""
1591: [(set (match_operand:QI 0 "general_operand" "=g")
1592: (ior:QI
1593: (subreg:QI
1594: (ashift:SI (const_int 1)
1595: (match_operand:QI 1 "general_operand" "rmn")) 0)
1596: (match_dup 0)))]
1597: ""
1598: "sbitb %1,%0")
1599:
1600: (define_insn ""
1601: [(set (match_operand:QI 0 "general_operand" "=g")
1602: (ior:QI
1603: (match_dup 0)
1604: (subreg:QI
1605: (ashift:SI (const_int 1)
1606: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1607: ""
1608: "sbitb %1,%0")
1609:
1610: (define_insn ""
1611: [(set (match_operand:SI 0 "general_operand" "=g")
1612: (and:SI
1613: (not:SI
1614: (ashift:SI (const_int 1)
1615: (match_operand:SI 1 "general_operand" "rmn")))
1616: (match_dup 0)))]
1617: ""
1618: "cbitd %1,%0")
1619:
1620: (define_insn ""
1621: [(set (match_operand:SI 0 "general_operand" "=g")
1622: (and:SI
1623: (match_dup 0)
1624: (not:SI
1625: (ashift:SI (const_int 1)
1626: (match_operand:SI 1 "general_operand" "rmn")))))]
1627: ""
1628: "cbitd %1,%0")
1629:
1630: (define_insn ""
1631: [(set (match_operand:QI 0 "general_operand" "=g")
1632: (and:QI
1633: (subreg:QI
1634: (not:SI
1635: (ashift:SI (const_int 1)
1636: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1637: (match_dup 0)))]
1638: ""
1639: "cbitb %1,%0")
1640:
1641: (define_insn ""
1642: [(set (match_operand:QI 0 "general_operand" "=g")
1643: (and:QI
1644: (match_dup 0)
1645: (subreg:QI
1646: (not:SI
1647: (ashift:SI (const_int 1)
1648: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1649: ""
1650: "cbitb %1,%0")
1651:
1652: (define_insn ""
1653: [(set (match_operand:SI 0 "general_operand" "=g")
1654: (xor:SI
1655: (ashift:SI (const_int 1)
1656: (match_operand:SI 1 "general_operand" "rmn"))
1657: (match_dup 0)))]
1658: ""
1659: "ibitd %1,%0")
1660:
1661: (define_insn ""
1662: [(set (match_operand:SI 0 "general_operand" "=g")
1663: (xor:SI
1664: (match_dup 0)
1665: (ashift:SI (const_int 1)
1666: (match_operand:SI 1 "general_operand" "rmn"))))]
1667: ""
1668: "ibitd %1,%0")
1669:
1670: (define_insn ""
1671: [(set (match_operand:QI 0 "general_operand" "=g")
1672: (xor:QI
1673: (subreg:QI
1674: (ashift:SI (const_int 1)
1675: (match_operand:QI 1 "general_operand" "rmn")) 0)
1676: (match_dup 0)))]
1677: ""
1678: "ibitb %1,%0")
1679:
1680: (define_insn ""
1681: [(set (match_operand:QI 0 "general_operand" "=g")
1682: (xor:QI
1683: (match_dup 0)
1684: (subreg:QI
1685: (ashift:SI (const_int 1)
1686: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1687: ""
1688: "ibitb %1,%0")
1689:
1690: ;; Recognize jbs and jbc instructions.
1691:
1692: (define_insn ""
1693: [(set (cc0)
1694: (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1695: (const_int 1)
1696: (match_operand:SI 1 "general_operand" "rmn")))]
1697: ""
1698: "*
1699: { cc_status.flags = CC_Z_IN_F;
1700: return \"tbitd %1,%0\";
1701: }")
1702:
1703: (define_insn ""
1704: [(set (cc0)
1705: (minus (zero_extract (match_operand:SI 0 "general_operand" "rmn")
1706: (const_int 1)
1707: (match_operand:SI 1 "general_operand" "rmn"))
1708: (const_int 1)))]
1709: ""
1710: "*
1711: { cc_status.flags = CC_Z_IN_NOT_F;
1712: return \"tbitd %1,%0\";
1713: }")
1714:
1715: (define_insn ""
1716: [(set (cc0)
1717: (zero_extract (match_operand:HI 0 "general_operand" "g")
1718: (const_int 1)
1719: (match_operand:HI 1 "general_operand" "g")))]
1720: ""
1721: "*
1722: { cc_status.flags = CC_Z_IN_F;
1723: return \"tbitw %1,%0\";
1724: }")
1725:
1726: (define_insn ""
1727: [(set (cc0)
1728: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1729: (const_int 1)
1730: (match_operand:HI 1 "general_operand" "rmn"))
1731: (const_int 1)))]
1732: ""
1733: "*
1734: { cc_status.flags = CC_Z_IN_NOT_F;
1735: return \"tbitw %1,%0\";
1736: }")
1737:
1738: (define_insn ""
1739: [(set (cc0)
1740: (zero_extract (match_operand:QI 0 "general_operand" "g")
1741: (const_int 1)
1742: (match_operand:QI 1 "general_operand" "g")))]
1743: ""
1744: "*
1745: { cc_status.flags = CC_Z_IN_F;
1746: return \"tbitb %1,%0\";
1747: }")
1748:
1749: (define_insn ""
1750: [(set (cc0)
1751: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1752: (const_int 1)
1753: (match_operand:QI 1 "general_operand" "rmn"))
1754: (const_int 1)))]
1755: ""
1756: "*
1757: { cc_status.flags = CC_Z_IN_NOT_F;
1758: return \"tbitb %1,%0\";
1759: }")
1760:
1761: (define_insn ""
1762: [(set (cc0)
1763: (and:SI (match_operand:SI 0 "general_operand" "rmn")
1764: (match_operand:SI 1 "immediate_operand" "i")))]
1765: "GET_CODE (operands[1]) == CONST_INT
1766: && exact_log2 (INTVAL (operands[1])) >= 0"
1767: "*
1768: {
1769: operands[1]
1770: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1771: cc_status.flags = CC_Z_IN_F;
1772: return \"tbitd %1,%0\";
1773: }")
1774:
1775: ;; extract(base, width, offset)
1776: ;; Signed bitfield extraction is not supported in hardware on the
1777: ;; NS 32032. It is therefore better to let GCC figure out a
1778: ;; good strategy for generating the proper instruction sequence
1779: ;; and represent it as rtl.
1780:
1.1.1.2 root 1781: ;; Optimize the case of extracting a byte or word from a register.
1782: ;; Otherwise we must load a register with the offset of the
1783: ;; chunk we want, and perform an extract insn (each of which
1784: ;; is very expensive). Since we use the stack to do our bit-twiddling
1785: ;; we cannot use it for a destination. Perhaps things are fast
1786: ;; enough on the 32532 that such hacks are not needed.
1787:
1788: (define_insn ""
1789: [(set (match_operand:SI 0 "general_operand" "=ro")
1790: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1791: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1792: (match_operand:SI 3 "const_int" "i")))]
1793: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1794: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1795: "*
1796: {
1797: output_asm_insn (\"movd %1,tos\", operands);
1798: if (INTVAL (operands[2]) == 16)
1799: {
1800: if (INTVAL (operands[3]) == 8)
1801: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1802: else
1803: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1804: }
1805: else
1806: {
1807: if (INTVAL (operands[3]) == 8)
1808: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1809: else if (INTVAL (operands[3]) == 16)
1810: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1811: else
1812: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1813: }
1.1.1.6 ! root 1814: #if defined(ns32532) || defined(ns32332)
! 1815: return \"cmpqd %$0,tos # adjsp -4\";
! 1816: #else
1.1.1.2 root 1817: return \"adjspb %$-4\";
1.1.1.6 ! root 1818: #endif
1.1.1.2 root 1819: }")
1820:
1821: (define_insn ""
1822: [(set (match_operand:SI 0 "general_operand" "=ro")
1823: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1824: (match_operand:SI 2 "const_int" "i")
1825: (match_operand:SI 3 "const_int" "i")))]
1826: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1827: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1828:
1829: (define_insn "extzv"
1830: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1831: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1832: (match_operand:SI 2 "const_int" "i,i")
1833: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1834: ""
1835: "*
1836: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1837: {
1838: if (INTVAL (operands[3]) >= 8)
1839: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1840: return \"extsd %1,%0,%3,%2\";
1841: }
1.1 root 1842: else return \"extd %3,%1,%0,%2\";
1843: }")
1844:
1845: (define_insn ""
1.1.1.2 root 1846: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1847: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1848: (match_operand:SI 2 "const_int" "i,i")
1849: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1850: ""
1851: "*
1852: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1853: {
1854: if (INTVAL (operands[3]) >= 8)
1855: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3);
1856: return \"extsd %1,%0,%3,%2\";
1857: }
1.1 root 1858: else return \"extd %3,%1,%0,%2\";
1859: }")
1860:
1861: (define_insn ""
1862: [(set (match_operand:SI 0 "general_operand" "=g<")
1863: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1864: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1865: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1866: ""
1867: "*
1868: { if (GET_CODE (operands[3]) == CONST_INT)
1869: return \"extsd %1,%0,%3,%2\";
1870: else return \"extd %3,%1,%0,%2\";
1871: }")
1872:
1873: (define_insn "insv"
1.1.1.4 root 1874: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1.1.1.2 root 1875: (match_operand:SI 1 "const_int" "i,i")
1876: (match_operand:SI 2 "general_operand" "rK,n"))
1877: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1878: ""
1879: "*
1880: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1881: {
1.1.1.4 root 1882: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1883: {
1884: operands[0] = adj_offsetable_operand (operands[0],
1885: INTVAL (operands[2]) / 8);
1886: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1887: }
1.1.1.2 root 1888: if (INTVAL (operands[1]) <= 8)
1889: return \"inssb %3,%0,%2,%1\";
1890: else if (INTVAL (operands[1]) <= 16)
1891: return \"inssw %3,%0,%2,%1\";
1892: else
1893: return \"inssd %3,%0,%2,%1\";
1894: }
1895: return \"insd %2,%3,%0,%1\";
1.1 root 1896: }")
1897:
1898: (define_insn ""
1.1.1.4 root 1899: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1.1.1.2 root 1900: (match_operand:SI 1 "const_int" "i,i")
1901: (match_operand:SI 2 "general_operand" "rK,n"))
1902: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1903: ""
1904: "*
1905: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1906: {
1.1.1.4 root 1907: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1908: {
1909: operands[0] = adj_offsetable_operand (operands[0],
1910: INTVAL (operands[2]) / 8);
1911: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1912: }
1.1.1.2 root 1913: if (INTVAL (operands[1]) <= 8)
1914: return \"inssb %3,%0,%2,%1\";
1915: else if (INTVAL (operands[1]) <= 16)
1916: return \"inssw %3,%0,%2,%1\";
1917: else
1918: return \"inssd %3,%0,%2,%1\";
1919: }
1920: return \"insd %2,%3,%0,%1\";
1.1 root 1921: }")
1922:
1923: (define_insn ""
1924: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1925: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1926: (match_operand:SI 2 "general_operand" "rn"))
1927: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1928: ""
1929: "*
1930: { if (GET_CODE (operands[2]) == CONST_INT)
1931: if (INTVAL (operands[1]) <= 8)
1932: return \"inssb %3,%0,%2,%1\";
1933: else if (INTVAL (operands[1]) <= 16)
1934: return \"inssw %3,%0,%2,%1\";
1935: else
1936: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1937: return \"insd %2,%3,%0,%1\";
1.1 root 1938: }")
1939:
1940:
1941: (define_insn "jump"
1942: [(set (pc)
1943: (label_ref (match_operand 0 "" "")))]
1944: ""
1945: "br %l0")
1946:
1947: (define_insn "beq"
1948: [(set (pc)
1949: (if_then_else (eq (cc0)
1950: (const_int 0))
1951: (label_ref (match_operand 0 "" ""))
1952: (pc)))]
1953: ""
1954: "*
1955: { if (cc_prev_status.flags & CC_Z_IN_F)
1956: return \"bfc %l0\";
1957: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1958: return \"bfs %l0\";
1959: else return \"beq %l0\";
1960: }")
1961:
1962: (define_insn "bne"
1963: [(set (pc)
1964: (if_then_else (ne (cc0)
1965: (const_int 0))
1966: (label_ref (match_operand 0 "" ""))
1967: (pc)))]
1968: ""
1969: "*
1970: { if (cc_prev_status.flags & CC_Z_IN_F)
1971: return \"bfs %l0\";
1972: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1973: return \"bfc %l0\";
1974: else return \"bne %l0\";
1975: }")
1976:
1977: (define_insn "bgt"
1978: [(set (pc)
1979: (if_then_else (gt (cc0)
1980: (const_int 0))
1981: (label_ref (match_operand 0 "" ""))
1982: (pc)))]
1983: ""
1984: "bgt %l0")
1985:
1986: (define_insn "bgtu"
1987: [(set (pc)
1988: (if_then_else (gtu (cc0)
1989: (const_int 0))
1990: (label_ref (match_operand 0 "" ""))
1991: (pc)))]
1992: ""
1993: "bhi %l0")
1994:
1995: (define_insn "blt"
1996: [(set (pc)
1997: (if_then_else (lt (cc0)
1998: (const_int 0))
1999: (label_ref (match_operand 0 "" ""))
2000: (pc)))]
2001: ""
2002: "blt %l0")
2003:
2004: (define_insn "bltu"
2005: [(set (pc)
2006: (if_then_else (ltu (cc0)
2007: (const_int 0))
2008: (label_ref (match_operand 0 "" ""))
2009: (pc)))]
2010: ""
2011: "blo %l0")
2012:
2013: (define_insn "bge"
2014: [(set (pc)
2015: (if_then_else (ge (cc0)
2016: (const_int 0))
2017: (label_ref (match_operand 0 "" ""))
2018: (pc)))]
2019: ""
2020: "bge %l0")
2021:
2022: (define_insn "bgeu"
2023: [(set (pc)
2024: (if_then_else (geu (cc0)
2025: (const_int 0))
2026: (label_ref (match_operand 0 "" ""))
2027: (pc)))]
2028: ""
2029: "bhs %l0")
2030:
2031: (define_insn "ble"
2032: [(set (pc)
2033: (if_then_else (le (cc0)
2034: (const_int 0))
2035: (label_ref (match_operand 0 "" ""))
2036: (pc)))]
2037: ""
2038: "ble %l0")
2039:
2040: (define_insn "bleu"
2041: [(set (pc)
2042: (if_then_else (leu (cc0)
2043: (const_int 0))
2044: (label_ref (match_operand 0 "" ""))
2045: (pc)))]
2046: ""
2047: "bls %l0")
2048:
2049: (define_insn ""
2050: [(set (pc)
2051: (if_then_else (eq (cc0)
2052: (const_int 0))
2053: (pc)
2054: (label_ref (match_operand 0 "" ""))))]
2055: ""
2056: "*
2057: { if (cc_prev_status.flags & CC_Z_IN_F)
2058: return \"bfs %l0\";
2059: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2060: return \"bfc %l0\";
2061: else return \"bne %l0\";
2062: }")
2063:
2064: (define_insn ""
2065: [(set (pc)
2066: (if_then_else (ne (cc0)
2067: (const_int 0))
2068: (pc)
2069: (label_ref (match_operand 0 "" ""))))]
2070: ""
2071: "*
2072: { if (cc_prev_status.flags & CC_Z_IN_F)
2073: return \"bfc %l0\";
2074: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2075: return \"bfs %l0\";
2076: else return \"beq %l0\";
2077: }")
2078:
2079: (define_insn ""
2080: [(set (pc)
2081: (if_then_else (gt (cc0)
2082: (const_int 0))
2083: (pc)
2084: (label_ref (match_operand 0 "" ""))))]
2085: ""
2086: "ble %l0")
2087:
2088: (define_insn ""
2089: [(set (pc)
2090: (if_then_else (gtu (cc0)
2091: (const_int 0))
2092: (pc)
2093: (label_ref (match_operand 0 "" ""))))]
2094: ""
2095: "bls %l0")
2096:
2097: (define_insn ""
2098: [(set (pc)
2099: (if_then_else (lt (cc0)
2100: (const_int 0))
2101: (pc)
2102: (label_ref (match_operand 0 "" ""))))]
2103: ""
2104: "bge %l0")
2105:
2106: (define_insn ""
2107: [(set (pc)
2108: (if_then_else (ltu (cc0)
2109: (const_int 0))
2110: (pc)
2111: (label_ref (match_operand 0 "" ""))))]
2112: ""
2113: "bhs %l0")
2114:
2115: (define_insn ""
2116: [(set (pc)
2117: (if_then_else (ge (cc0)
2118: (const_int 0))
2119: (pc)
2120: (label_ref (match_operand 0 "" ""))))]
2121: ""
2122: "blt %l0")
2123:
2124: (define_insn ""
2125: [(set (pc)
2126: (if_then_else (geu (cc0)
2127: (const_int 0))
2128: (pc)
2129: (label_ref (match_operand 0 "" ""))))]
2130: ""
2131: "blo %l0")
2132:
2133: (define_insn ""
2134: [(set (pc)
2135: (if_then_else (le (cc0)
2136: (const_int 0))
2137: (pc)
2138: (label_ref (match_operand 0 "" ""))))]
2139: ""
2140: "bgt %l0")
2141:
2142: (define_insn ""
2143: [(set (pc)
2144: (if_then_else (leu (cc0)
2145: (const_int 0))
2146: (pc)
2147: (label_ref (match_operand 0 "" ""))))]
2148: ""
2149: "bhi %l0")
2150:
2151: ;; Subtract-and-jump and Add-and-jump insns.
2152: ;; These can actually be used for adding numbers in the range -8 to 7
2153:
2154: (define_insn ""
2155: [(set (pc)
2156: (if_then_else
2157: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2158: (match_operand:SI 1 "general_operand" "i"))
2159: (const_int 0))
2160: (label_ref (match_operand 2 "" ""))
2161: (pc)))
2162: (set (match_dup 0)
2163: (minus:SI (match_dup 0)
2164: (match_dup 1)))]
2165: "GET_CODE (operands[1]) == CONST_INT
2166: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2167: "acbd %$%n1,%0,%l2")
2168:
2169: (define_insn ""
2170: [(set (pc)
2171: (if_then_else
2172: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2173: (match_operand:SI 1 "general_operand" "i"))
2174: (const_int 0))
2175: (label_ref (match_operand 2 "" ""))
2176: (pc)))
2177: (set (match_dup 0)
2178: (plus:SI (match_dup 0)
2179: (match_dup 1)))]
2180: "GET_CODE (operands[1]) == CONST_INT
2181: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2182: "acbd %1,%0,%l2")
2183:
2184: ;; Reversed
2185:
2186: (define_insn ""
2187: [(set (pc)
2188: (if_then_else
2189: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2190: (match_operand:SI 1 "general_operand" "i"))
2191: (const_int 0))
2192: (pc)
2193: (label_ref (match_operand 2 "" ""))))
2194: (set (match_dup 0)
2195: (minus:SI (match_dup 0)
2196: (match_dup 1)))]
2197: "GET_CODE (operands[1]) == CONST_INT
2198: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2199: "acbd %$%n1,%0,%l2")
2200:
2201: (define_insn ""
2202: [(set (pc)
2203: (if_then_else
2204: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2205: (match_operand:SI 1 "general_operand" "i"))
2206: (const_int 0))
2207: (pc)
2208: (label_ref (match_operand 2 "" ""))))
2209: (set (match_dup 0)
2210: (plus:SI (match_dup 0)
2211: (match_dup 1)))]
2212: "GET_CODE (operands[1]) == CONST_INT
2213: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2214: "acbd %1,%0,%l2")
2215:
2216: (define_insn "call"
2217: [(call (match_operand:QI 0 "general_operand" "g")
2218: (match_operand:QI 1 "general_operand" "g"))]
2219: ""
2220: "*
2221: {
2222: if (GET_CODE (operands[0]) == MEM)
2223: {
2224: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.4 root 2225: #ifdef GNX_V3
2226: return \"bsr %0\";
2227: #else
1.1.1.2 root 2228: return \"bsr %?%a0\";
1.1.1.4 root 2229: #endif
1.1 root 2230: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.4 root 2231: #ifdef GNX_V3
2232: return \"jsr %0\";
2233: #else
1.1 root 2234: return \"jsr %a0\";
1.1.1.4 root 2235: #endif
1.1 root 2236: }
2237: return \"jsr %0\";
2238: }")
2239:
2240: (define_insn "call_value"
2241: [(set (match_operand 0 "" "fg")
2242: (call (match_operand:QI 1 "general_operand" "g")
2243: (match_operand:QI 2 "general_operand" "g")))]
2244: ""
2245: "*
2246: {
2247: if (GET_CODE (operands[1]) == MEM)
2248: {
2249: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.4 root 2250: #ifdef GNX_V3
2251: return \"bsr %1\";
2252: #else
1.1.1.2 root 2253: return \"bsr %?%a1\";
1.1.1.4 root 2254: #endif
1.1 root 2255: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.4 root 2256: #ifdef GNX_V3
2257: return \"jsr %1\";
2258: #else
1.1 root 2259: return \"jsr %a1\";
1.1.1.4 root 2260: #endif
1.1 root 2261: }
2262: return \"jsr %1\";
2263: }")
2264:
2265: (define_insn "return"
2266: [(return)]
1.1.1.5 root 2267: "0"
1.1 root 2268: "ret 0")
2269:
2270: (define_insn "abssf2"
2271: [(set (match_operand:SF 0 "general_operand" "=fm<")
2272: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2273: "TARGET_32081"
2274: "absf %1,%0")
2275:
2276: (define_insn "absdf2"
2277: [(set (match_operand:DF 0 "general_operand" "=fm<")
2278: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2279: "TARGET_32081"
2280: "absl %1,%0")
2281:
2282: (define_insn "abssi2"
2283: [(set (match_operand:SI 0 "general_operand" "=g<")
2284: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2285: ""
2286: "absd %1,%0")
2287:
2288: (define_insn "abshi2"
2289: [(set (match_operand:HI 0 "general_operand" "=g<")
2290: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2291: ""
2292: "absw %1,%0")
2293:
2294: (define_insn "absqi2"
2295: [(set (match_operand:QI 0 "general_operand" "=g<")
2296: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2297: ""
2298: "absb %1,%0")
2299:
2300: ;;(define_insn "tablejump"
2301: ;; [(set (pc)
2302: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2303: ;; (pc)))]
2304: ;; ""
2305: ;; "cased %0")
2306:
2307: (define_insn "tablejump"
2308: [(set (pc)
2309: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2310: (use (label_ref (match_operand 1 "" "")))]
2311: ""
2312: "*
2313: {
2314: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2315: CODE_LABEL_NUMBER (operands[1]));
2316: return \"casew %0\";
2317: }")
2318:
2319: ;;(define_insn ""
2320: ;; [(set (pc)
2321: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2322: ;; (pc)))]
2323: ;; ""
2324: ;; "caseb %0")
2325:
2326: ;; Scondi instructions
2327: (define_insn "seq"
2328: [(set (match_operand:SI 0 "general_operand" "=g<")
2329: (eq (cc0) (const_int 0)))]
2330: ""
2331: "*
2332: { if (cc_prev_status.flags & CC_Z_IN_F)
2333: return \"sfcd %0\";
2334: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2335: return \"sfsd %0\";
2336: else return \"seqd %0\";
2337: }")
2338:
2339: (define_insn ""
2340: [(set (match_operand:HI 0 "general_operand" "=g<")
2341: (eq (cc0) (const_int 0)))]
2342: ""
2343: "*
2344: { if (cc_prev_status.flags & CC_Z_IN_F)
2345: return \"sfcw %0\";
2346: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2347: return \"sfsw %0\";
2348: else return \"seqw %0\";
2349: }")
2350:
2351: (define_insn ""
2352: [(set (match_operand:QI 0 "general_operand" "=g<")
2353: (eq (cc0) (const_int 0)))]
2354: ""
2355: "*
2356: { if (cc_prev_status.flags & CC_Z_IN_F)
2357: return \"sfcb %0\";
2358: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2359: return \"sfsb %0\";
2360: else return \"seqb %0\";
2361: }")
2362:
2363: (define_insn "sne"
2364: [(set (match_operand:SI 0 "general_operand" "=g<")
2365: (ne (cc0) (const_int 0)))]
2366: ""
2367: "*
2368: { if (cc_prev_status.flags & CC_Z_IN_F)
2369: return \"sfsd %0\";
2370: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2371: return \"sfcd %0\";
2372: else return \"sned %0\";
2373: }")
2374:
2375: (define_insn ""
2376: [(set (match_operand:HI 0 "general_operand" "=g<")
2377: (ne (cc0) (const_int 0)))]
2378: ""
2379: "*
2380: { if (cc_prev_status.flags & CC_Z_IN_F)
2381: return \"sfsw %0\";
2382: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2383: return \"sfcw %0\";
2384: else return \"snew %0\";
2385: }")
2386:
2387: (define_insn ""
2388: [(set (match_operand:QI 0 "general_operand" "=g<")
2389: (ne (cc0) (const_int 0)))]
2390: ""
2391: "*
2392: { if (cc_prev_status.flags & CC_Z_IN_F)
2393: return \"sfsb %0\";
2394: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2395: return \"sfcb %0\";
2396: else return \"sneb %0\";
2397: }")
2398:
2399: (define_insn "sgt"
2400: [(set (match_operand:SI 0 "general_operand" "=g<")
2401: (gt (cc0) (const_int 0)))]
2402: ""
2403: "sgtd %0")
2404:
2405: (define_insn ""
2406: [(set (match_operand:HI 0 "general_operand" "=g<")
2407: (gt (cc0) (const_int 0)))]
2408: ""
2409: "sgtw %0")
2410:
2411: (define_insn ""
2412: [(set (match_operand:QI 0 "general_operand" "=g<")
2413: (gt (cc0) (const_int 0)))]
2414: ""
2415: "sgtb %0")
2416:
2417: (define_insn "sgtu"
2418: [(set (match_operand:SI 0 "general_operand" "=g<")
2419: (gtu (cc0) (const_int 0)))]
2420: ""
2421: "shid %0")
2422:
2423: (define_insn ""
2424: [(set (match_operand:HI 0 "general_operand" "=g<")
2425: (gtu (cc0) (const_int 0)))]
2426: ""
2427: "shiw %0")
2428:
2429: (define_insn ""
2430: [(set (match_operand:QI 0 "general_operand" "=g<")
2431: (gtu (cc0) (const_int 0)))]
2432: ""
2433: "shib %0")
2434:
2435: (define_insn "slt"
2436: [(set (match_operand:SI 0 "general_operand" "=g<")
2437: (lt (cc0) (const_int 0)))]
2438: ""
2439: "sltd %0")
2440:
2441: (define_insn ""
2442: [(set (match_operand:HI 0 "general_operand" "=g<")
2443: (lt (cc0) (const_int 0)))]
2444: ""
2445: "sltw %0")
2446:
2447: (define_insn ""
2448: [(set (match_operand:QI 0 "general_operand" "=g<")
2449: (lt (cc0) (const_int 0)))]
2450: ""
2451: "sltb %0")
2452:
2453: (define_insn "sltu"
2454: [(set (match_operand:SI 0 "general_operand" "=g<")
2455: (ltu (cc0) (const_int 0)))]
2456: ""
2457: "slod %0")
2458:
2459: (define_insn ""
2460: [(set (match_operand:HI 0 "general_operand" "=g<")
2461: (ltu (cc0) (const_int 0)))]
2462: ""
2463: "slow %0")
2464:
2465: (define_insn ""
2466: [(set (match_operand:QI 0 "general_operand" "=g<")
2467: (ltu (cc0) (const_int 0)))]
2468: ""
2469: "slob %0")
2470:
2471: (define_insn "sge"
2472: [(set (match_operand:SI 0 "general_operand" "=g<")
2473: (ge (cc0) (const_int 0)))]
2474: ""
2475: "sged %0")
2476:
2477: (define_insn ""
2478: [(set (match_operand:HI 0 "general_operand" "=g<")
2479: (ge (cc0) (const_int 0)))]
2480: ""
2481: "sgew %0")
2482:
2483: (define_insn ""
2484: [(set (match_operand:QI 0 "general_operand" "=g<")
2485: (ge (cc0) (const_int 0)))]
2486: ""
2487: "sgeb %0")
2488:
2489: (define_insn "sgeu"
2490: [(set (match_operand:SI 0 "general_operand" "=g<")
2491: (geu (cc0) (const_int 0)))]
2492: ""
2493: "shsd %0")
2494:
2495: (define_insn ""
2496: [(set (match_operand:HI 0 "general_operand" "=g<")
2497: (geu (cc0) (const_int 0)))]
2498: ""
2499: "shsw %0")
2500:
2501: (define_insn ""
2502: [(set (match_operand:QI 0 "general_operand" "=g<")
2503: (geu (cc0) (const_int 0)))]
2504: ""
2505: "shsb %0")
2506:
2507: (define_insn "sle"
2508: [(set (match_operand:SI 0 "general_operand" "=g<")
2509: (le (cc0) (const_int 0)))]
2510: ""
2511: "sled %0")
2512:
2513: (define_insn ""
2514: [(set (match_operand:HI 0 "general_operand" "=g<")
2515: (le (cc0) (const_int 0)))]
2516: ""
2517: "slew %0")
2518:
2519: (define_insn ""
2520: [(set (match_operand:QI 0 "general_operand" "=g<")
2521: (le (cc0) (const_int 0)))]
2522: ""
2523: "sleb %0")
2524:
2525: (define_insn "sleu"
2526: [(set (match_operand:SI 0 "general_operand" "=g<")
2527: (leu (cc0) (const_int 0)))]
2528: ""
2529: "slsd %0")
2530:
2531: (define_insn ""
2532: [(set (match_operand:HI 0 "general_operand" "=g<")
2533: (leu (cc0) (const_int 0)))]
2534: ""
2535: "slsw %0")
2536:
2537: (define_insn ""
2538: [(set (match_operand:QI 0 "general_operand" "=g<")
2539: (leu (cc0) (const_int 0)))]
2540: ""
2541: "slsb %0")
2542:
2543: ;;- Local variables:
2544: ;;- mode:emacs-lisp
2545: ;;- comment-start: ";;- "
2546: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2547: ;;- eval: (modify-syntax-entry ?[ "(]")
2548: ;;- eval: (modify-syntax-entry ?] ")[")
2549: ;;- eval: (modify-syntax-entry ?{ "(}")
2550: ;;- eval: (modify-syntax-entry ?} "){")
2551: ;;- End:
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